drivers/net/dsa/mv88e6xxx/chip.c

   1 /*
   2  * Marvell 88e6xxx Ethernet switch single-chip support
   3  *
   4  * Copyright (c) 2008 Marvell Semiconductor
   5  *
   6  * Copyright (c) 2015 CMC Electronics, Inc.
   7  *      Added support for VLAN Table Unit operations
   8  *
   9  * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  */
  16
  17 #include <linux/delay.h>
  18 #include <linux/etherdevice.h>
  19 #include <linux/ethtool.h>
  20 #include <linux/if_bridge.h>
  21 #include <linux/jiffies.h>
  22 #include <linux/list.h>
  23 #include <linux/mdio.h>
  24 #include <linux/module.h>
  25 #include <linux/of_device.h>
  26 #include <linux/of_mdio.h>
  27 #include <linux/netdevice.h>
  28 #include <linux/gpio/consumer.h>
  29 #include <linux/phy.h>
  30 #include <net/dsa.h>
  31 #include <net/switchdev.h>
  32 #include "mv88e6xxx.h"
  33
  34 static void assert_reg_lock(struct mv88e6xxx_chip *chip)
  35 {
  36         if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
  37                 dev_err(chip->dev, "Switch registers lock not held!\n");
  38                 dump_stack();
  39         }
  40 }
  41
  42 /* The switch ADDR[4:1] configuration pins define the chip SMI device address
  43  * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
  44  *
  45  * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
  46  * is the only device connected to the SMI master. In this mode it responds to
  47  * all 32 possible SMI addresses, and thus maps directly the internal devices.
  48  *
  49  * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
  50  * multiple devices to share the SMI interface. In this mode it responds to only
  51  * 2 registers, used to indirectly access the internal SMI devices.
  52  */
  53
  54 static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
  55                               int addr, int reg, u16 *val)
  56 {
  57         if (!chip->smi_ops)
  58                 return -EOPNOTSUPP;
  59
  60         return chip->smi_ops->read(chip, addr, reg, val);
  61 }
  62
  63 static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
  64                                int addr, int reg, u16 val)
  65 {
  66         if (!chip->smi_ops)
  67                 return -EOPNOTSUPP;
  68
  69         return chip->smi_ops->write(chip, addr, reg, val);
  70 }
  71
  72 static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
  73                                           int addr, int reg, u16 *val)
  74 {
  75         int ret;
  76
  77         ret = mdiobus_read_nested(chip->bus, addr, reg);
  78         if (ret < 0)
  79                 return ret;
  80
  81         *val = ret & 0xffff;
  82
  83         return 0;
  84 }
  85
  86 static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
  87                                            int addr, int reg, u16 val)
  88 {
  89         int ret;
  90
  91         ret = mdiobus_write_nested(chip->bus, addr, reg, val);
  92         if (ret < 0)
  93                 return ret;
  94
  95         return 0;
  96 }
  97
  98 static const struct mv88e6xxx_ops mv88e6xxx_smi_single_chip_ops = {
  99         .read = mv88e6xxx_smi_single_chip_read,
 100         .write = mv88e6xxx_smi_single_chip_write,
 101 };
 102
 103 static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
 104 {
 105         int ret;
 106         int i;
 107
 108         for (i = 0; i < 16; i++) {
 109                 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
 110                 if (ret < 0)
 111                         return ret;
 112
 113                 if ((ret & SMI_CMD_BUSY) == 0)
 114                         return 0;
 115         }
 116
 117         return -ETIMEDOUT;
 118 }
 119
 120 static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
 121                                          int addr, int reg, u16 *val)
 122 {
 123         int ret;
 124
 125         /* Wait for the bus to become free. */
 126         ret = mv88e6xxx_smi_multi_chip_wait(chip);
 127         if (ret < 0)
 128                 return ret;
 129
 130         /* Transmit the read command. */
 131         ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
 132                                    SMI_CMD_OP_22_READ | (addr << 5) | reg);
 133         if (ret < 0)
 134                 return ret;
 135
 136         /* Wait for the read command to complete. */
 137         ret = mv88e6xxx_smi_multi_chip_wait(chip);
 138         if (ret < 0)
 139                 return ret;
 140
 141         /* Read the data. */
 142         ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
 143         if (ret < 0)
 144                 return ret;
 145
 146         *val = ret & 0xffff;
 147
 148         return 0;
 149 }
 150
 151 static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
 152                                           int addr, int reg, u16 val)
 153 {
 154         int ret;
 155
 156         /* Wait for the bus to become free. */
 157         ret = mv88e6xxx_smi_multi_chip_wait(chip);
 158         if (ret < 0)
 159                 return ret;
 160
 161         /* Transmit the data to write. */
 162         ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
 163         if (ret < 0)
 164                 return ret;
 165
 166         /* Transmit the write command. */
 167         ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
 168                                    SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
 169         if (ret < 0)
 170                 return ret;
 171
 172         /* Wait for the write command to complete. */
 173         ret = mv88e6xxx_smi_multi_chip_wait(chip);
 174         if (ret < 0)
 175                 return ret;
 176
 177         return 0;
 178 }
 179
 180 static const struct mv88e6xxx_ops mv88e6xxx_smi_multi_chip_ops = {
 181         .read = mv88e6xxx_smi_multi_chip_read,
 182         .write = mv88e6xxx_smi_multi_chip_write,
 183 };
 184
 185 static int mv88e6xxx_read(struct mv88e6xxx_chip *chip,
 186                           int addr, int reg, u16 *val)
 187 {
 188         int err;
 189
 190         assert_reg_lock(chip);
 191
 192         err = mv88e6xxx_smi_read(chip, addr, reg, val);
 193         if (err)
 194                 return err;
 195
 196         dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
 197                 addr, reg, *val);
 198
 199         return 0;
 200 }
 201
 202 static int mv88e6xxx_write(struct mv88e6xxx_chip *chip,
 203                            int addr, int reg, u16 val)
 204 {
 205         int err;
 206
 207         assert_reg_lock(chip);
 208
 209         err = mv88e6xxx_smi_write(chip, addr, reg, val);
 210         if (err)
 211                 return err;
 212
 213         dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
 214                 addr, reg, val);
 215
 216         return 0;
 217 }
 218
 219 static int mv88e6xxx_phy_read(struct mv88e6xxx_chip *chip, int phy,
 220                               int reg, u16 *val)
 221 {
 222         int addr = phy; /* PHY devices addresses start at 0x0 */
 223
 224         if (!chip->phy_ops)
 225                 return -EOPNOTSUPP;
 226
 227         return chip->phy_ops->read(chip, addr, reg, val);
 228 }
 229
 230 static int mv88e6xxx_phy_write(struct mv88e6xxx_chip *chip, int phy,
 231                                int reg, u16 val)
 232 {
 233         int addr = phy; /* PHY devices addresses start at 0x0 */
 234
 235         if (!chip->phy_ops)
 236                 return -EOPNOTSUPP;
 237
 238         return chip->phy_ops->write(chip, addr, reg, val);
 239 }
 240
 241 static int mv88e6xxx_phy_page_get(struct mv88e6xxx_chip *chip, int phy, u8 page)
 242 {
 243         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_PHY_PAGE))
 244                 return -EOPNOTSUPP;
 245
 246         return mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
 247 }
 248
 249 static void mv88e6xxx_phy_page_put(struct mv88e6xxx_chip *chip, int phy)
 250 {
 251         int err;
 252
 253         /* Restore PHY page Copper 0x0 for access via the registered MDIO bus */
 254         err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, PHY_PAGE_COPPER);
 255         if (unlikely(err)) {
 256                 dev_err(chip->dev, "failed to restore PHY %d page Copper (%d)\n",
 257                         phy, err);
 258         }
 259 }
 260
 261 static int mv88e6xxx_phy_page_read(struct mv88e6xxx_chip *chip, int phy,
 262                                    u8 page, int reg, u16 *val)
 263 {
 264         int err;
 265
 266         /* There is no paging for registers 22 */
 267         if (reg == PHY_PAGE)
 268                 return -EINVAL;
 269
 270         err = mv88e6xxx_phy_page_get(chip, phy, page);
 271         if (!err) {
 272                 err = mv88e6xxx_phy_read(chip, phy, reg, val);
 273                 mv88e6xxx_phy_page_put(chip, phy);
 274         }
 275
 276         return err;
 277 }
 278
 279 static int mv88e6xxx_phy_page_write(struct mv88e6xxx_chip *chip, int phy,
 280                                     u8 page, int reg, u16 val)
 281 {
 282         int err;
 283
 284         /* There is no paging for registers 22 */
 285         if (reg == PHY_PAGE)
 286                 return -EINVAL;
 287
 288         err = mv88e6xxx_phy_page_get(chip, phy, page);
 289         if (!err) {
 290                 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
 291                 mv88e6xxx_phy_page_put(chip, phy);
 292         }
 293
 294         return err;
 295 }
 296
 297 static int mv88e6xxx_serdes_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
 298 {
 299         return mv88e6xxx_phy_page_read(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
 300                                        reg, val);
 301 }
 302
 303 static int mv88e6xxx_serdes_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
 304 {
 305         return mv88e6xxx_phy_page_write(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
 306                                         reg, val);
 307 }
 308
 309 static int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg,
 310                           u16 mask)
 311 {
 312         unsigned long timeout = jiffies + HZ / 10;
 313
 314         while (time_before(jiffies, timeout)) {
 315                 u16 val;
 316                 int err;
 317
 318                 err = mv88e6xxx_read(chip, addr, reg, &val);
 319                 if (err)
 320                         return err;
 321
 322                 if (!(val & mask))
 323                         return 0;
 324
 325                 usleep_range(1000, 2000);
 326         }
 327
 328         return -ETIMEDOUT;
 329 }
 330
 331 /* Indirect write to single pointer-data register with an Update bit */
 332 static int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg,
 333                             u16 update)
 334 {
 335         u16 val;
 336         int i, err;
 337
 338         /* Wait until the previous operation is completed */
 339         for (i = 0; i < 16; ++i) {
 340                 err = mv88e6xxx_read(chip, addr, reg, &val);
 341                 if (err)
 342                         return err;
 343
 344                 if (!(val & BIT(15)))
 345                         break;
 346         }
 347
 348         if (i == 16)
 349                 return -ETIMEDOUT;
 350
 351         /* Set the Update bit to trigger a write operation */
 352         val = BIT(15) | update;
 353
 354         return mv88e6xxx_write(chip, addr, reg, val);
 355 }
 356
 357 static int _mv88e6xxx_reg_read(struct mv88e6xxx_chip *chip, int addr, int reg)
 358 {
 359         u16 val;
 360         int err;
 361
 362         err = mv88e6xxx_read(chip, addr, reg, &val);
 363         if (err)
 364                 return err;
 365
 366         return val;
 367 }
 368
 369 static int _mv88e6xxx_reg_write(struct mv88e6xxx_chip *chip, int addr,
 370                                 int reg, u16 val)
 371 {
 372         return mv88e6xxx_write(chip, addr, reg, val);
 373 }
 374
 375 static int mv88e6xxx_ppu_disable(struct mv88e6xxx_chip *chip)
 376 {
 377         int ret;
 378         unsigned long timeout;
 379
 380         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_CONTROL);
 381         if (ret < 0)
 382                 return ret;
 383
 384         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL,
 385                                    ret & ~GLOBAL_CONTROL_PPU_ENABLE);
 386         if (ret)
 387                 return ret;
 388
 389         timeout = jiffies + 1 * HZ;
 390         while (time_before(jiffies, timeout)) {
 391                 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATUS);
 392                 if (ret < 0)
 393                         return ret;
 394
 395                 usleep_range(1000, 2000);
 396                 if ((ret & GLOBAL_STATUS_PPU_MASK) !=
 397                     GLOBAL_STATUS_PPU_POLLING)
 398                         return 0;
 399         }
 400
 401         return -ETIMEDOUT;
 402 }
 403
 404 static int mv88e6xxx_ppu_enable(struct mv88e6xxx_chip *chip)
 405 {
 406         int ret, err;
 407         unsigned long timeout;
 408
 409         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_CONTROL);
 410         if (ret < 0)
 411                 return ret;
 412
 413         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL,
 414                                    ret | GLOBAL_CONTROL_PPU_ENABLE);
 415         if (err)
 416                 return err;
 417
 418         timeout = jiffies + 1 * HZ;
 419         while (time_before(jiffies, timeout)) {
 420                 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATUS);
 421                 if (ret < 0)
 422                         return ret;
 423
 424                 usleep_range(1000, 2000);
 425                 if ((ret & GLOBAL_STATUS_PPU_MASK) ==
 426                     GLOBAL_STATUS_PPU_POLLING)
 427                         return 0;
 428         }
 429
 430         return -ETIMEDOUT;
 431 }
 432
 433 static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
 434 {
 435         struct mv88e6xxx_chip *chip;
 436
 437         chip = container_of(ugly, struct mv88e6xxx_chip, ppu_work);
 438
 439         mutex_lock(&chip->reg_lock);
 440
 441         if (mutex_trylock(&chip->ppu_mutex)) {
 442                 if (mv88e6xxx_ppu_enable(chip) == 0)
 443                         chip->ppu_disabled = 0;
 444                 mutex_unlock(&chip->ppu_mutex);
 445         }
 446
 447         mutex_unlock(&chip->reg_lock);
 448 }
 449
 450 static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
 451 {
 452         struct mv88e6xxx_chip *chip = (void *)_ps;
 453
 454         schedule_work(&chip->ppu_work);
 455 }
 456
 457 static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_chip *chip)
 458 {
 459         int ret;
 460
 461         mutex_lock(&chip->ppu_mutex);
 462
 463         /* If the PHY polling unit is enabled, disable it so that
 464          * we can access the PHY registers.  If it was already
 465          * disabled, cancel the timer that is going to re-enable
 466          * it.
 467          */
 468         if (!chip->ppu_disabled) {
 469                 ret = mv88e6xxx_ppu_disable(chip);
 470                 if (ret < 0) {
 471                         mutex_unlock(&chip->ppu_mutex);
 472                         return ret;
 473                 }
 474                 chip->ppu_disabled = 1;
 475         } else {
 476                 del_timer(&chip->ppu_timer);
 477                 ret = 0;
 478         }
 479
 480         return ret;
 481 }
 482
 483 static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_chip *chip)
 484 {
 485         /* Schedule a timer to re-enable the PHY polling unit. */
 486         mod_timer(&chip->ppu_timer, jiffies + msecs_to_jiffies(10));
 487         mutex_unlock(&chip->ppu_mutex);
 488 }
 489
 490 static void mv88e6xxx_ppu_state_init(struct mv88e6xxx_chip *chip)
 491 {
 492         mutex_init(&chip->ppu_mutex);
 493         INIT_WORK(&chip->ppu_work, mv88e6xxx_ppu_reenable_work);
 494         init_timer(&chip->ppu_timer);
 495         chip->ppu_timer.data = (unsigned long)chip;
 496         chip->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
 497 }
 498
 499 static int mv88e6xxx_phy_ppu_read(struct mv88e6xxx_chip *chip, int addr,
 500                                   int reg, u16 *val)
 501 {
 502         int err;
 503
 504         err = mv88e6xxx_ppu_access_get(chip);
 505         if (!err) {
 506                 err = mv88e6xxx_read(chip, addr, reg, val);
 507                 mv88e6xxx_ppu_access_put(chip);
 508         }
 509
 510         return err;
 511 }
 512
 513 static int mv88e6xxx_phy_ppu_write(struct mv88e6xxx_chip *chip, int addr,
 514                                    int reg, u16 val)
 515 {
 516         int err;
 517
 518         err = mv88e6xxx_ppu_access_get(chip);
 519         if (!err) {
 520                 err = mv88e6xxx_write(chip, addr, reg, val);
 521                 mv88e6xxx_ppu_access_put(chip);
 522         }
 523
 524         return err;
 525 }
 526
 527 static const struct mv88e6xxx_ops mv88e6xxx_phy_ppu_ops = {
 528         .read = mv88e6xxx_phy_ppu_read,
 529         .write = mv88e6xxx_phy_ppu_write,
 530 };
 531
 532 static bool mv88e6xxx_6065_family(struct mv88e6xxx_chip *chip)
 533 {
 534         return chip->info->family == MV88E6XXX_FAMILY_6065;
 535 }
 536
 537 static bool mv88e6xxx_6095_family(struct mv88e6xxx_chip *chip)
 538 {
 539         return chip->info->family == MV88E6XXX_FAMILY_6095;
 540 }
 541
 542 static bool mv88e6xxx_6097_family(struct mv88e6xxx_chip *chip)
 543 {
 544         return chip->info->family == MV88E6XXX_FAMILY_6097;
 545 }
 546
 547 static bool mv88e6xxx_6165_family(struct mv88e6xxx_chip *chip)
 548 {
 549         return chip->info->family == MV88E6XXX_FAMILY_6165;
 550 }
 551
 552 static bool mv88e6xxx_6185_family(struct mv88e6xxx_chip *chip)
 553 {
 554         return chip->info->family == MV88E6XXX_FAMILY_6185;
 555 }
 556
 557 static bool mv88e6xxx_6320_family(struct mv88e6xxx_chip *chip)
 558 {
 559         return chip->info->family == MV88E6XXX_FAMILY_6320;
 560 }
 561
 562 static bool mv88e6xxx_6351_family(struct mv88e6xxx_chip *chip)
 563 {
 564         return chip->info->family == MV88E6XXX_FAMILY_6351;
 565 }
 566
 567 static bool mv88e6xxx_6352_family(struct mv88e6xxx_chip *chip)
 568 {
 569         return chip->info->family == MV88E6XXX_FAMILY_6352;
 570 }
 571
 572 static unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip)
 573 {
 574         return chip->info->num_databases;
 575 }
 576
 577 static bool mv88e6xxx_has_fid_reg(struct mv88e6xxx_chip *chip)
 578 {
 579         /* Does the device have dedicated FID registers for ATU and VTU ops? */
 580         if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
 581             mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip))
 582                 return true;
 583
 584         return false;
 585 }
 586
 587 /* We expect the switch to perform auto negotiation if there is a real
 588  * phy. However, in the case of a fixed link phy, we force the port
 589  * settings from the fixed link settings.
 590  */
 591 static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
 592                                   struct phy_device *phydev)
 593 {
 594         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 595         u32 reg;
 596         int ret;
 597
 598         if (!phy_is_pseudo_fixed_link(phydev))
 599                 return;
 600
 601         mutex_lock(&chip->reg_lock);
 602
 603         ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_PCS_CTRL);
 604         if (ret < 0)
 605                 goto out;
 606
 607         reg = ret & ~(PORT_PCS_CTRL_LINK_UP |
 608                       PORT_PCS_CTRL_FORCE_LINK |
 609                       PORT_PCS_CTRL_DUPLEX_FULL |
 610                       PORT_PCS_CTRL_FORCE_DUPLEX |
 611                       PORT_PCS_CTRL_UNFORCED);
 612
 613         reg |= PORT_PCS_CTRL_FORCE_LINK;
 614         if (phydev->link)
 615                 reg |= PORT_PCS_CTRL_LINK_UP;
 616
 617         if (mv88e6xxx_6065_family(chip) && phydev->speed > SPEED_100)
 618                 goto out;
 619
 620         switch (phydev->speed) {
 621         case SPEED_1000:
 622                 reg |= PORT_PCS_CTRL_1000;
 623                 break;
 624         case SPEED_100:
 625                 reg |= PORT_PCS_CTRL_100;
 626                 break;
 627         case SPEED_10:
 628                 reg |= PORT_PCS_CTRL_10;
 629                 break;
 630         default:
 631                 pr_info("Unknown speed");
 632                 goto out;
 633         }
 634
 635         reg |= PORT_PCS_CTRL_FORCE_DUPLEX;
 636         if (phydev->duplex == DUPLEX_FULL)
 637                 reg |= PORT_PCS_CTRL_DUPLEX_FULL;
 638
 639         if ((mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip)) &&
 640             (port >= chip->info->num_ports - 2)) {
 641                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
 642                         reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK;
 643                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
 644                         reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
 645                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
 646                         reg |= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
 647                                 PORT_PCS_CTRL_RGMII_DELAY_TXCLK);
 648         }
 649         _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_PCS_CTRL, reg);
 650
 651 out:
 652         mutex_unlock(&chip->reg_lock);
 653 }
 654
 655 static int _mv88e6xxx_stats_wait(struct mv88e6xxx_chip *chip)
 656 {
 657         int ret;
 658         int i;
 659
 660         for (i = 0; i < 10; i++) {
 661                 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_OP);
 662                 if ((ret & GLOBAL_STATS_OP_BUSY) == 0)
 663                         return 0;
 664         }
 665
 666         return -ETIMEDOUT;
 667 }
 668
 669 static int _mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
 670 {
 671         int ret;
 672
 673         if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip))
 674                 port = (port + 1) << 5;
 675
 676         /* Snapshot the hardware statistics counters for this port. */
 677         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP,
 678                                    GLOBAL_STATS_OP_CAPTURE_PORT |
 679                                    GLOBAL_STATS_OP_HIST_RX_TX | port);
 680         if (ret < 0)
 681                 return ret;
 682
 683         /* Wait for the snapshotting to complete. */
 684         ret = _mv88e6xxx_stats_wait(chip);
 685         if (ret < 0)
 686                 return ret;
 687
 688         return 0;
 689 }
 690
 691 static void _mv88e6xxx_stats_read(struct mv88e6xxx_chip *chip,
 692                                   int stat, u32 *val)
 693 {
 694         u32 _val;
 695         int ret;
 696
 697         *val = 0;
 698
 699         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP,
 700                                    GLOBAL_STATS_OP_READ_CAPTURED |
 701                                    GLOBAL_STATS_OP_HIST_RX_TX | stat);
 702         if (ret < 0)
 703                 return;
 704
 705         ret = _mv88e6xxx_stats_wait(chip);
 706         if (ret < 0)
 707                 return;
 708
 709         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_COUNTER_32);
 710         if (ret < 0)
 711                 return;
 712
 713         _val = ret << 16;
 714
 715         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_COUNTER_01);
 716         if (ret < 0)
 717                 return;
 718
 719         *val = _val | ret;
 720 }
 721
 722 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
 723         { "in_good_octets",     8, 0x00, BANK0, },
 724         { "in_bad_octets",      4, 0x02, BANK0, },
 725         { "in_unicast",         4, 0x04, BANK0, },
 726         { "in_broadcasts",      4, 0x06, BANK0, },
 727         { "in_multicasts",      4, 0x07, BANK0, },
 728         { "in_pause",           4, 0x16, BANK0, },
 729         { "in_undersize",       4, 0x18, BANK0, },
 730         { "in_fragments",       4, 0x19, BANK0, },
 731         { "in_oversize",        4, 0x1a, BANK0, },
 732         { "in_jabber",          4, 0x1b, BANK0, },
 733         { "in_rx_error",        4, 0x1c, BANK0, },
 734         { "in_fcs_error",       4, 0x1d, BANK0, },
 735         { "out_octets",         8, 0x0e, BANK0, },
 736         { "out_unicast",        4, 0x10, BANK0, },
 737         { "out_broadcasts",     4, 0x13, BANK0, },
 738         { "out_multicasts",     4, 0x12, BANK0, },
 739         { "out_pause",          4, 0x15, BANK0, },
 740         { "excessive",          4, 0x11, BANK0, },
 741         { "collisions",         4, 0x1e, BANK0, },
 742         { "deferred",           4, 0x05, BANK0, },
 743         { "single",             4, 0x14, BANK0, },
 744         { "multiple",           4, 0x17, BANK0, },
 745         { "out_fcs_error",      4, 0x03, BANK0, },
 746         { "late",               4, 0x1f, BANK0, },
 747         { "hist_64bytes",       4, 0x08, BANK0, },
 748         { "hist_65_127bytes",   4, 0x09, BANK0, },
 749         { "hist_128_255bytes",  4, 0x0a, BANK0, },
 750         { "hist_256_511bytes",  4, 0x0b, BANK0, },
 751         { "hist_512_1023bytes", 4, 0x0c, BANK0, },
 752         { "hist_1024_max_bytes", 4, 0x0d, BANK0, },
 753         { "sw_in_discards",     4, 0x10, PORT, },
 754         { "sw_in_filtered",     2, 0x12, PORT, },
 755         { "sw_out_filtered",    2, 0x13, PORT, },
 756         { "in_discards",        4, 0x00 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 757         { "in_filtered",        4, 0x01 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 758         { "in_accepted",        4, 0x02 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 759         { "in_bad_accepted",    4, 0x03 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 760         { "in_good_avb_class_a", 4, 0x04 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 761         { "in_good_avb_class_b", 4, 0x05 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 762         { "in_bad_avb_class_a", 4, 0x06 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 763         { "in_bad_avb_class_b", 4, 0x07 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 764         { "tcam_counter_0",     4, 0x08 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 765         { "tcam_counter_1",     4, 0x09 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 766         { "tcam_counter_2",     4, 0x0a | GLOBAL_STATS_OP_BANK_1, BANK1, },
 767         { "tcam_counter_3",     4, 0x0b | GLOBAL_STATS_OP_BANK_1, BANK1, },
 768         { "in_da_unknown",      4, 0x0e | GLOBAL_STATS_OP_BANK_1, BANK1, },
 769         { "in_management",      4, 0x0f | GLOBAL_STATS_OP_BANK_1, BANK1, },
 770         { "out_queue_0",        4, 0x10 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 771         { "out_queue_1",        4, 0x11 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 772         { "out_queue_2",        4, 0x12 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 773         { "out_queue_3",        4, 0x13 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 774         { "out_queue_4",        4, 0x14 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 775         { "out_queue_5",        4, 0x15 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 776         { "out_queue_6",        4, 0x16 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 777         { "out_queue_7",        4, 0x17 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 778         { "out_cut_through",    4, 0x18 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 779         { "out_octets_a",       4, 0x1a | GLOBAL_STATS_OP_BANK_1, BANK1, },
 780         { "out_octets_b",       4, 0x1b | GLOBAL_STATS_OP_BANK_1, BANK1, },
 781         { "out_management",     4, 0x1f | GLOBAL_STATS_OP_BANK_1, BANK1, },
 782 };
 783
 784 static bool mv88e6xxx_has_stat(struct mv88e6xxx_chip *chip,
 785                                struct mv88e6xxx_hw_stat *stat)
 786 {
 787         switch (stat->type) {
 788         case BANK0:
 789                 return true;
 790         case BANK1:
 791                 return mv88e6xxx_6320_family(chip);
 792         case PORT:
 793                 return mv88e6xxx_6095_family(chip) ||
 794                         mv88e6xxx_6185_family(chip) ||
 795                         mv88e6xxx_6097_family(chip) ||
 796                         mv88e6xxx_6165_family(chip) ||
 797                         mv88e6xxx_6351_family(chip) ||
 798                         mv88e6xxx_6352_family(chip);
 799         }
 800         return false;
 801 }
 802
 803 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
 804                                             struct mv88e6xxx_hw_stat *s,
 805                                             int port)
 806 {
 807         u32 low;
 808         u32 high = 0;
 809         int ret;
 810         u64 value;
 811
 812         switch (s->type) {
 813         case PORT:
 814                 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), s->reg);
 815                 if (ret < 0)
 816                         return UINT64_MAX;
 817
 818                 low = ret;
 819                 if (s->sizeof_stat == 4) {
 820                         ret = _mv88e6xxx_reg_read(chip, REG_PORT(port),
 821                                                   s->reg + 1);
 822                         if (ret < 0)
 823                                 return UINT64_MAX;
 824                         high = ret;
 825                 }
 826                 break;
 827         case BANK0:
 828         case BANK1:
 829                 _mv88e6xxx_stats_read(chip, s->reg, &low);
 830                 if (s->sizeof_stat == 8)
 831                         _mv88e6xxx_stats_read(chip, s->reg + 1, &high);
 832         }
 833         value = (((u64)high) << 16) | low;
 834         return value;
 835 }
 836
 837 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
 838                                   uint8_t *data)
 839 {
 840         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 841         struct mv88e6xxx_hw_stat *stat;
 842         int i, j;
 843
 844         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
 845                 stat = &mv88e6xxx_hw_stats[i];
 846                 if (mv88e6xxx_has_stat(chip, stat)) {
 847                         memcpy(data + j * ETH_GSTRING_LEN, stat->string,
 848                                ETH_GSTRING_LEN);
 849                         j++;
 850                 }
 851         }
 852 }
 853
 854 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
 855 {
 856         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 857         struct mv88e6xxx_hw_stat *stat;
 858         int i, j;
 859
 860         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
 861                 stat = &mv88e6xxx_hw_stats[i];
 862                 if (mv88e6xxx_has_stat(chip, stat))
 863                         j++;
 864         }
 865         return j;
 866 }
 867
 868 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
 869                                         uint64_t *data)
 870 {
 871         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 872         struct mv88e6xxx_hw_stat *stat;
 873         int ret;
 874         int i, j;
 875
 876         mutex_lock(&chip->reg_lock);
 877
 878         ret = _mv88e6xxx_stats_snapshot(chip, port);
 879         if (ret < 0) {
 880                 mutex_unlock(&chip->reg_lock);
 881                 return;
 882         }
 883         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
 884                 stat = &mv88e6xxx_hw_stats[i];
 885                 if (mv88e6xxx_has_stat(chip, stat)) {
 886                         data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port);
 887                         j++;
 888                 }
 889         }
 890
 891         mutex_unlock(&chip->reg_lock);
 892 }
 893
 894 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
 895 {
 896         return 32 * sizeof(u16);
 897 }
 898
 899 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
 900                                struct ethtool_regs *regs, void *_p)
 901 {
 902         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 903         u16 *p = _p;
 904         int i;
 905
 906         regs->version = 0;
 907
 908         memset(p, 0xff, 32 * sizeof(u16));
 909
 910         mutex_lock(&chip->reg_lock);
 911
 912         for (i = 0; i < 32; i++) {
 913                 int ret;
 914
 915                 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), i);
 916                 if (ret >= 0)
 917                         p[i] = ret;
 918         }
 919
 920         mutex_unlock(&chip->reg_lock);
 921 }
 922
 923 static int _mv88e6xxx_atu_wait(struct mv88e6xxx_chip *chip)
 924 {
 925         return mv88e6xxx_wait(chip, REG_GLOBAL, GLOBAL_ATU_OP,
 926                               GLOBAL_ATU_OP_BUSY);
 927 }
 928
 929 static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port,
 930                              struct ethtool_eee *e)
 931 {
 932         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 933         u16 reg;
 934         int err;
 935
 936         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
 937                 return -EOPNOTSUPP;
 938
 939         mutex_lock(&chip->reg_lock);
 940
 941         err = mv88e6xxx_phy_read(chip, port, 16, &reg);
 942         if (err)
 943                 goto out;
 944
 945         e->eee_enabled = !!(reg & 0x0200);
 946         e->tx_lpi_enabled = !!(reg & 0x0100);
 947
 948         err = mv88e6xxx_read(chip, REG_PORT(port), PORT_STATUS, &reg);
 949         if (err)
 950                 goto out;
 951
 952         e->eee_active = !!(reg & PORT_STATUS_EEE);
 953 out:
 954         mutex_unlock(&chip->reg_lock);
 955
 956         return err;
 957 }
 958
 959 static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
 960                              struct phy_device *phydev, struct ethtool_eee *e)
 961 {
 962         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 963         u16 reg;
 964         int err;
 965
 966         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
 967                 return -EOPNOTSUPP;
 968
 969         mutex_lock(&chip->reg_lock);
 970
 971         err = mv88e6xxx_phy_read(chip, port, 16, &reg);
 972         if (err)
 973                 goto out;
 974
 975         reg &= ~0x0300;
 976         if (e->eee_enabled)
 977                 reg |= 0x0200;
 978         if (e->tx_lpi_enabled)
 979                 reg |= 0x0100;
 980
 981         err = mv88e6xxx_phy_write(chip, port, 16, reg);
 982 out:
 983         mutex_unlock(&chip->reg_lock);
 984
 985         return err;
 986 }
 987
 988 static int _mv88e6xxx_atu_cmd(struct mv88e6xxx_chip *chip, u16 fid, u16 cmd)
 989 {
 990         int ret;
 991
 992         if (mv88e6xxx_has_fid_reg(chip)) {
 993                 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_FID,
 994                                            fid);
 995                 if (ret < 0)
 996                         return ret;
 997         } else if (mv88e6xxx_num_databases(chip) == 256) {
 998                 /* ATU DBNum[7:4] are located in ATU Control 15:12 */
 999                 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL);
1000                 if (ret < 0)
1001                         return ret;
1002
1003                 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL,
1004                                            (ret & 0xfff) |
1005                                            ((fid << 8) & 0xf000));
1006                 if (ret < 0)
1007                         return ret;
1008
1009                 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */
1010                 cmd |= fid & 0xf;
1011         }
1012
1013         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_OP, cmd);
1014         if (ret < 0)
1015                 return ret;
1016
1017         return _mv88e6xxx_atu_wait(chip);
1018 }
1019
1020 static int _mv88e6xxx_atu_data_write(struct mv88e6xxx_chip *chip,
1021                                      struct mv88e6xxx_atu_entry *entry)
1022 {
1023         u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK;
1024
1025         if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1026                 unsigned int mask, shift;
1027
1028                 if (entry->trunk) {
1029                         data |= GLOBAL_ATU_DATA_TRUNK;
1030                         mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
1031                         shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
1032                 } else {
1033                         mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
1034                         shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
1035                 }
1036
1037                 data |= (entry->portv_trunkid << shift) & mask;
1038         }
1039
1040         return _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_DATA, data);
1041 }
1042
1043 static int _mv88e6xxx_atu_flush_move(struct mv88e6xxx_chip *chip,
1044                                      struct mv88e6xxx_atu_entry *entry,
1045                                      bool static_too)
1046 {
1047         int op;
1048         int err;
1049
1050         err = _mv88e6xxx_atu_wait(chip);
1051         if (err)
1052                 return err;
1053
1054         err = _mv88e6xxx_atu_data_write(chip, entry);
1055         if (err)
1056                 return err;
1057
1058         if (entry->fid) {
1059                 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB :
1060                         GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
1061         } else {
1062                 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL :
1063                         GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC;
1064         }
1065
1066         return _mv88e6xxx_atu_cmd(chip, entry->fid, op);
1067 }
1068
1069 static int _mv88e6xxx_atu_flush(struct mv88e6xxx_chip *chip,
1070                                 u16 fid, bool static_too)
1071 {
1072         struct mv88e6xxx_atu_entry entry = {
1073                 .fid = fid,
1074                 .state = 0, /* EntryState bits must be 0 */
1075         };
1076
1077         return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
1078 }
1079
1080 static int _mv88e6xxx_atu_move(struct mv88e6xxx_chip *chip, u16 fid,
1081                                int from_port, int to_port, bool static_too)
1082 {
1083         struct mv88e6xxx_atu_entry entry = {
1084                 .trunk = false,
1085                 .fid = fid,
1086         };
1087
1088         /* EntryState bits must be 0xF */
1089         entry.state = GLOBAL_ATU_DATA_STATE_MASK;
1090
1091         /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
1092         entry.portv_trunkid = (to_port & 0x0f) << 4;
1093         entry.portv_trunkid |= from_port & 0x0f;
1094
1095         return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
1096 }
1097
1098 static int _mv88e6xxx_atu_remove(struct mv88e6xxx_chip *chip, u16 fid,
1099                                  int port, bool static_too)
1100 {
1101         /* Destination port 0xF means remove the entries */
1102         return _mv88e6xxx_atu_move(chip, fid, port, 0x0f, static_too);
1103 }
1104
1105 static const char * const mv88e6xxx_port_state_names[] = {
1106         [PORT_CONTROL_STATE_DISABLED] = "Disabled",
1107         [PORT_CONTROL_STATE_BLOCKING] = "Blocking/Listening",
1108         [PORT_CONTROL_STATE_LEARNING] = "Learning",
1109         [PORT_CONTROL_STATE_FORWARDING] = "Forwarding",
1110 };
1111
1112 static int _mv88e6xxx_port_state(struct mv88e6xxx_chip *chip, int port,
1113                                  u8 state)
1114 {
1115         struct dsa_switch *ds = chip->ds;
1116         int reg, ret = 0;
1117         u8 oldstate;
1118
1119         reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_CONTROL);
1120         if (reg < 0)
1121                 return reg;
1122
1123         oldstate = reg & PORT_CONTROL_STATE_MASK;
1124
1125         if (oldstate != state) {
1126                 /* Flush forwarding database if we're moving a port
1127                  * from Learning or Forwarding state to Disabled or
1128                  * Blocking or Listening state.
1129                  */
1130                 if ((oldstate == PORT_CONTROL_STATE_LEARNING ||
1131                      oldstate == PORT_CONTROL_STATE_FORWARDING) &&
1132                     (state == PORT_CONTROL_STATE_DISABLED ||
1133                      state == PORT_CONTROL_STATE_BLOCKING)) {
1134                         ret = _mv88e6xxx_atu_remove(chip, 0, port, false);
1135                         if (ret)
1136                                 return ret;
1137                 }
1138
1139                 reg = (reg & ~PORT_CONTROL_STATE_MASK) | state;
1140                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL,
1141                                            reg);
1142                 if (ret)
1143                         return ret;
1144
1145                 netdev_dbg(ds->ports[port].netdev, "PortState %s (was %s)\n",
1146                            mv88e6xxx_port_state_names[state],
1147                            mv88e6xxx_port_state_names[oldstate]);
1148         }
1149
1150         return ret;
1151 }
1152
1153 static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_chip *chip, int port)
1154 {
1155         struct net_device *bridge = chip->ports[port].bridge_dev;
1156         const u16 mask = (1 << chip->info->num_ports) - 1;
1157         struct dsa_switch *ds = chip->ds;
1158         u16 output_ports = 0;
1159         int reg;
1160         int i;
1161
1162         /* allow CPU port or DSA link(s) to send frames to every port */
1163         if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
1164                 output_ports = mask;
1165         } else {
1166                 for (i = 0; i < chip->info->num_ports; ++i) {
1167                         /* allow sending frames to every group member */
1168                         if (bridge && chip->ports[i].bridge_dev == bridge)
1169                                 output_ports |= BIT(i);
1170
1171                         /* allow sending frames to CPU port and DSA link(s) */
1172                         if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1173                                 output_ports |= BIT(i);
1174                 }
1175         }
1176
1177         /* prevent frames from going back out of the port they came in on */
1178         output_ports &= ~BIT(port);
1179
1180         reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_BASE_VLAN);
1181         if (reg < 0)
1182                 return reg;
1183
1184         reg &= ~mask;
1185         reg |= output_ports & mask;
1186
1187         return _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_BASE_VLAN, reg);
1188 }
1189
1190 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1191                                          u8 state)
1192 {
1193         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1194         int stp_state;
1195         int err;
1196
1197         switch (state) {
1198         case BR_STATE_DISABLED:
1199                 stp_state = PORT_CONTROL_STATE_DISABLED;
1200                 break;
1201         case BR_STATE_BLOCKING:
1202         case BR_STATE_LISTENING:
1203                 stp_state = PORT_CONTROL_STATE_BLOCKING;
1204                 break;
1205         case BR_STATE_LEARNING:
1206                 stp_state = PORT_CONTROL_STATE_LEARNING;
1207                 break;
1208         case BR_STATE_FORWARDING:
1209         default:
1210                 stp_state = PORT_CONTROL_STATE_FORWARDING;
1211                 break;
1212         }
1213
1214         mutex_lock(&chip->reg_lock);
1215         err = _mv88e6xxx_port_state(chip, port, stp_state);
1216         mutex_unlock(&chip->reg_lock);
1217
1218         if (err)
1219                 netdev_err(ds->ports[port].netdev,
1220                            "failed to update state to %s\n",
1221                            mv88e6xxx_port_state_names[stp_state]);
1222 }
1223
1224 static int _mv88e6xxx_port_pvid(struct mv88e6xxx_chip *chip, int port,
1225                                 u16 *new, u16 *old)
1226 {
1227         struct dsa_switch *ds = chip->ds;
1228         u16 pvid;
1229         int ret;
1230
1231         ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_DEFAULT_VLAN);
1232         if (ret < 0)
1233                 return ret;
1234
1235         pvid = ret & PORT_DEFAULT_VLAN_MASK;
1236
1237         if (new) {
1238                 ret &= ~PORT_DEFAULT_VLAN_MASK;
1239                 ret |= *new & PORT_DEFAULT_VLAN_MASK;
1240
1241                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
1242                                            PORT_DEFAULT_VLAN, ret);
1243                 if (ret < 0)
1244                         return ret;
1245
1246                 netdev_dbg(ds->ports[port].netdev,
1247                            "DefaultVID %d (was %d)\n", *new, pvid);
1248         }
1249
1250         if (old)
1251                 *old = pvid;
1252
1253         return 0;
1254 }
1255
1256 static int _mv88e6xxx_port_pvid_get(struct mv88e6xxx_chip *chip,
1257                                     int port, u16 *pvid)
1258 {
1259         return _mv88e6xxx_port_pvid(chip, port, NULL, pvid);
1260 }
1261
1262 static int _mv88e6xxx_port_pvid_set(struct mv88e6xxx_chip *chip,
1263                                     int port, u16 pvid)
1264 {
1265         return _mv88e6xxx_port_pvid(chip, port, &pvid, NULL);
1266 }
1267
1268 static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_chip *chip)
1269 {
1270         return mv88e6xxx_wait(chip, REG_GLOBAL, GLOBAL_VTU_OP,
1271                               GLOBAL_VTU_OP_BUSY);
1272 }
1273
1274 static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_chip *chip, u16 op)
1275 {
1276         int ret;
1277
1278         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_OP, op);
1279         if (ret < 0)
1280                 return ret;
1281
1282         return _mv88e6xxx_vtu_wait(chip);
1283 }
1284
1285 static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_chip *chip)
1286 {
1287         int ret;
1288
1289         ret = _mv88e6xxx_vtu_wait(chip);
1290         if (ret < 0)
1291                 return ret;
1292
1293         return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_FLUSH_ALL);
1294 }
1295
1296 static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_chip *chip,
1297                                         struct mv88e6xxx_vtu_stu_entry *entry,
1298                                         unsigned int nibble_offset)
1299 {
1300         u16 regs[3];
1301         int i;
1302         int ret;
1303
1304         for (i = 0; i < 3; ++i) {
1305                 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
1306                                           GLOBAL_VTU_DATA_0_3 + i);
1307                 if (ret < 0)
1308                         return ret;
1309
1310                 regs[i] = ret;
1311         }
1312
1313         for (i = 0; i < chip->info->num_ports; ++i) {
1314                 unsigned int shift = (i % 4) * 4 + nibble_offset;
1315                 u16 reg = regs[i / 4];
1316
1317                 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1318         }
1319
1320         return 0;
1321 }
1322
1323 static int mv88e6xxx_vtu_data_read(struct mv88e6xxx_chip *chip,
1324                                    struct mv88e6xxx_vtu_stu_entry *entry)
1325 {
1326         return _mv88e6xxx_vtu_stu_data_read(chip, entry, 0);
1327 }
1328
1329 static int mv88e6xxx_stu_data_read(struct mv88e6xxx_chip *chip,
1330                                    struct mv88e6xxx_vtu_stu_entry *entry)
1331 {
1332         return _mv88e6xxx_vtu_stu_data_read(chip, entry, 2);
1333 }
1334
1335 static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_chip *chip,
1336                                          struct mv88e6xxx_vtu_stu_entry *entry,
1337                                          unsigned int nibble_offset)
1338 {
1339         u16 regs[3] = { 0 };
1340         int i;
1341         int ret;
1342
1343         for (i = 0; i < chip->info->num_ports; ++i) {
1344                 unsigned int shift = (i % 4) * 4 + nibble_offset;
1345                 u8 data = entry->data[i];
1346
1347                 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1348         }
1349
1350         for (i = 0; i < 3; ++i) {
1351                 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL,
1352                                            GLOBAL_VTU_DATA_0_3 + i, regs[i]);
1353                 if (ret < 0)
1354                         return ret;
1355         }
1356
1357         return 0;
1358 }
1359
1360 static int mv88e6xxx_vtu_data_write(struct mv88e6xxx_chip *chip,
1361                                     struct mv88e6xxx_vtu_stu_entry *entry)
1362 {
1363         return _mv88e6xxx_vtu_stu_data_write(chip, entry, 0);
1364 }
1365
1366 static int mv88e6xxx_stu_data_write(struct mv88e6xxx_chip *chip,
1367                                     struct mv88e6xxx_vtu_stu_entry *entry)
1368 {
1369         return _mv88e6xxx_vtu_stu_data_write(chip, entry, 2);
1370 }
1371
1372 static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_chip *chip, u16 vid)
1373 {
1374         return _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID,
1375                                     vid & GLOBAL_VTU_VID_MASK);
1376 }
1377
1378 static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
1379                                   struct mv88e6xxx_vtu_stu_entry *entry)
1380 {
1381         struct mv88e6xxx_vtu_stu_entry next = { 0 };
1382         int ret;
1383
1384         ret = _mv88e6xxx_vtu_wait(chip);
1385         if (ret < 0)
1386                 return ret;
1387
1388         ret = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_VTU_GET_NEXT);
1389         if (ret < 0)
1390                 return ret;
1391
1392         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_VID);
1393         if (ret < 0)
1394                 return ret;
1395
1396         next.vid = ret & GLOBAL_VTU_VID_MASK;
1397         next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1398
1399         if (next.valid) {
1400                 ret = mv88e6xxx_vtu_data_read(chip, &next);
1401                 if (ret < 0)
1402                         return ret;
1403
1404                 if (mv88e6xxx_has_fid_reg(chip)) {
1405                         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
1406                                                   GLOBAL_VTU_FID);
1407                         if (ret < 0)
1408                                 return ret;
1409
1410                         next.fid = ret & GLOBAL_VTU_FID_MASK;
1411                 } else if (mv88e6xxx_num_databases(chip) == 256) {
1412                         /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1413                          * VTU DBNum[3:0] are located in VTU Operation 3:0
1414                          */
1415                         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
1416                                                   GLOBAL_VTU_OP);
1417                         if (ret < 0)
1418                                 return ret;
1419
1420                         next.fid = (ret & 0xf00) >> 4;
1421                         next.fid |= ret & 0xf;
1422                 }
1423
1424                 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
1425                         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
1426                                                   GLOBAL_VTU_SID);
1427                         if (ret < 0)
1428                                 return ret;
1429
1430                         next.sid = ret & GLOBAL_VTU_SID_MASK;
1431                 }
1432         }
1433
1434         *entry = next;
1435         return 0;
1436 }
1437
1438 static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1439                                     struct switchdev_obj_port_vlan *vlan,
1440                                     int (*cb)(struct switchdev_obj *obj))
1441 {
1442         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1443         struct mv88e6xxx_vtu_stu_entry next;
1444         u16 pvid;
1445         int err;
1446
1447         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1448                 return -EOPNOTSUPP;
1449
1450         mutex_lock(&chip->reg_lock);
1451
1452         err = _mv88e6xxx_port_pvid_get(chip, port, &pvid);
1453         if (err)
1454                 goto unlock;
1455
1456         err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
1457         if (err)
1458                 goto unlock;
1459
1460         do {
1461                 err = _mv88e6xxx_vtu_getnext(chip, &next);
1462                 if (err)
1463                         break;
1464
1465                 if (!next.valid)
1466                         break;
1467
1468                 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1469                         continue;
1470
1471                 /* reinit and dump this VLAN obj */
1472                 vlan->vid_begin = next.vid;
1473                 vlan->vid_end = next.vid;
1474                 vlan->flags = 0;
1475
1476                 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1477                         vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1478
1479                 if (next.vid == pvid)
1480                         vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1481
1482                 err = cb(&vlan->obj);
1483                 if (err)
1484                         break;
1485         } while (next.vid < GLOBAL_VTU_VID_MASK);
1486
1487 unlock:
1488         mutex_unlock(&chip->reg_lock);
1489
1490         return err;
1491 }
1492
1493 static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1494                                     struct mv88e6xxx_vtu_stu_entry *entry)
1495 {
1496         u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE;
1497         u16 reg = 0;
1498         int ret;
1499
1500         ret = _mv88e6xxx_vtu_wait(chip);
1501         if (ret < 0)
1502                 return ret;
1503
1504         if (!entry->valid)
1505                 goto loadpurge;
1506
1507         /* Write port member tags */
1508         ret = mv88e6xxx_vtu_data_write(chip, entry);
1509         if (ret < 0)
1510                 return ret;
1511
1512         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
1513                 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1514                 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID,
1515                                            reg);
1516                 if (ret < 0)
1517                         return ret;
1518         }
1519
1520         if (mv88e6xxx_has_fid_reg(chip)) {
1521                 reg = entry->fid & GLOBAL_VTU_FID_MASK;
1522                 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_FID,
1523                                            reg);
1524                 if (ret < 0)
1525                         return ret;
1526         } else if (mv88e6xxx_num_databases(chip) == 256) {
1527                 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1528                  * VTU DBNum[3:0] are located in VTU Operation 3:0
1529                  */
1530                 op |= (entry->fid & 0xf0) << 8;
1531                 op |= entry->fid & 0xf;
1532         }
1533
1534         reg = GLOBAL_VTU_VID_VALID;
1535 loadpurge:
1536         reg |= entry->vid & GLOBAL_VTU_VID_MASK;
1537         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1538         if (ret < 0)
1539                 return ret;
1540
1541         return _mv88e6xxx_vtu_cmd(chip, op);
1542 }
1543
1544 static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_chip *chip, u8 sid,
1545                                   struct mv88e6xxx_vtu_stu_entry *entry)
1546 {
1547         struct mv88e6xxx_vtu_stu_entry next = { 0 };
1548         int ret;
1549
1550         ret = _mv88e6xxx_vtu_wait(chip);
1551         if (ret < 0)
1552                 return ret;
1553
1554         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID,
1555                                    sid & GLOBAL_VTU_SID_MASK);
1556         if (ret < 0)
1557                 return ret;
1558
1559         ret = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_GET_NEXT);
1560         if (ret < 0)
1561                 return ret;
1562
1563         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_SID);
1564         if (ret < 0)
1565                 return ret;
1566
1567         next.sid = ret & GLOBAL_VTU_SID_MASK;
1568
1569         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_VID);
1570         if (ret < 0)
1571                 return ret;
1572
1573         next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1574
1575         if (next.valid) {
1576                 ret = mv88e6xxx_stu_data_read(chip, &next);
1577                 if (ret < 0)
1578                         return ret;
1579         }
1580
1581         *entry = next;
1582         return 0;
1583 }
1584
1585 static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip,
1586                                     struct mv88e6xxx_vtu_stu_entry *entry)
1587 {
1588         u16 reg = 0;
1589         int ret;
1590
1591         ret = _mv88e6xxx_vtu_wait(chip);
1592         if (ret < 0)
1593                 return ret;
1594
1595         if (!entry->valid)
1596                 goto loadpurge;
1597
1598         /* Write port states */
1599         ret = mv88e6xxx_stu_data_write(chip, entry);
1600         if (ret < 0)
1601                 return ret;
1602
1603         reg = GLOBAL_VTU_VID_VALID;
1604 loadpurge:
1605         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1606         if (ret < 0)
1607                 return ret;
1608
1609         reg = entry->sid & GLOBAL_VTU_SID_MASK;
1610         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID, reg);
1611         if (ret < 0)
1612                 return ret;
1613
1614         return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_LOAD_PURGE);
1615 }
1616
1617 static int _mv88e6xxx_port_fid(struct mv88e6xxx_chip *chip, int port,
1618                                u16 *new, u16 *old)
1619 {
1620         struct dsa_switch *ds = chip->ds;
1621         u16 upper_mask;
1622         u16 fid;
1623         int ret;
1624
1625         if (mv88e6xxx_num_databases(chip) == 4096)
1626                 upper_mask = 0xff;
1627         else if (mv88e6xxx_num_databases(chip) == 256)
1628                 upper_mask = 0xf;
1629         else
1630                 return -EOPNOTSUPP;
1631
1632         /* Port's default FID bits 3:0 are located in reg 0x06, offset 12 */
1633         ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_BASE_VLAN);
1634         if (ret < 0)
1635                 return ret;
1636
1637         fid = (ret & PORT_BASE_VLAN_FID_3_0_MASK) >> 12;
1638
1639         if (new) {
1640                 ret &= ~PORT_BASE_VLAN_FID_3_0_MASK;
1641                 ret |= (*new << 12) & PORT_BASE_VLAN_FID_3_0_MASK;
1642
1643                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_BASE_VLAN,
1644                                            ret);
1645                 if (ret < 0)
1646                         return ret;
1647         }
1648
1649         /* Port's default FID bits 11:4 are located in reg 0x05, offset 0 */
1650         ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_CONTROL_1);
1651         if (ret < 0)
1652                 return ret;
1653
1654         fid |= (ret & upper_mask) << 4;
1655
1656         if (new) {
1657                 ret &= ~upper_mask;
1658                 ret |= (*new >> 4) & upper_mask;
1659
1660                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL_1,
1661                                            ret);
1662                 if (ret < 0)
1663                         return ret;
1664
1665                 netdev_dbg(ds->ports[port].netdev,
1666                            "FID %d (was %d)\n", *new, fid);
1667         }
1668
1669         if (old)
1670                 *old = fid;
1671
1672         return 0;
1673 }
1674
1675 static int _mv88e6xxx_port_fid_get(struct mv88e6xxx_chip *chip,
1676                                    int port, u16 *fid)
1677 {
1678         return _mv88e6xxx_port_fid(chip, port, NULL, fid);
1679 }
1680
1681 static int _mv88e6xxx_port_fid_set(struct mv88e6xxx_chip *chip,
1682                                    int port, u16 fid)
1683 {
1684         return _mv88e6xxx_port_fid(chip, port, &fid, NULL);
1685 }
1686
1687 static int _mv88e6xxx_fid_new(struct mv88e6xxx_chip *chip, u16 *fid)
1688 {
1689         DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1690         struct mv88e6xxx_vtu_stu_entry vlan;
1691         int i, err;
1692
1693         bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1694
1695         /* Set every FID bit used by the (un)bridged ports */
1696         for (i = 0; i < chip->info->num_ports; ++i) {
1697                 err = _mv88e6xxx_port_fid_get(chip, i, fid);
1698                 if (err)
1699                         return err;
1700
1701                 set_bit(*fid, fid_bitmap);
1702         }
1703
1704         /* Set every FID bit used by the VLAN entries */
1705         err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
1706         if (err)
1707                 return err;
1708
1709         do {
1710                 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
1711                 if (err)
1712                         return err;
1713
1714                 if (!vlan.valid)
1715                         break;
1716
1717                 set_bit(vlan.fid, fid_bitmap);
1718         } while (vlan.vid < GLOBAL_VTU_VID_MASK);
1719
1720         /* The reset value 0x000 is used to indicate that multiple address
1721          * databases are not needed. Return the next positive available.
1722          */
1723         *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1724         if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1725                 return -ENOSPC;
1726
1727         /* Clear the database */
1728         return _mv88e6xxx_atu_flush(chip, *fid, true);
1729 }
1730
1731 static int _mv88e6xxx_vtu_new(struct mv88e6xxx_chip *chip, u16 vid,
1732                               struct mv88e6xxx_vtu_stu_entry *entry)
1733 {
1734         struct dsa_switch *ds = chip->ds;
1735         struct mv88e6xxx_vtu_stu_entry vlan = {
1736                 .valid = true,
1737                 .vid = vid,
1738         };
1739         int i, err;
1740
1741         err = _mv88e6xxx_fid_new(chip, &vlan.fid);
1742         if (err)
1743                 return err;
1744
1745         /* exclude all ports except the CPU and DSA ports */
1746         for (i = 0; i < chip->info->num_ports; ++i)
1747                 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)
1748                         ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1749                         : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1750
1751         if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
1752             mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip)) {
1753                 struct mv88e6xxx_vtu_stu_entry vstp;
1754
1755                 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1756                  * implemented, only one STU entry is needed to cover all VTU
1757                  * entries. Thus, validate the SID 0.
1758                  */
1759                 vlan.sid = 0;
1760                 err = _mv88e6xxx_stu_getnext(chip, GLOBAL_VTU_SID_MASK, &vstp);
1761                 if (err)
1762                         return err;
1763
1764                 if (vstp.sid != vlan.sid || !vstp.valid) {
1765                         memset(&vstp, 0, sizeof(vstp));
1766                         vstp.valid = true;
1767                         vstp.sid = vlan.sid;
1768
1769                         err = _mv88e6xxx_stu_loadpurge(chip, &vstp);
1770                         if (err)
1771                                 return err;
1772                 }
1773         }
1774
1775         *entry = vlan;
1776         return 0;
1777 }
1778
1779 static int _mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1780                               struct mv88e6xxx_vtu_stu_entry *entry, bool creat)
1781 {
1782         int err;
1783
1784         if (!vid)
1785                 return -EINVAL;
1786
1787         err = _mv88e6xxx_vtu_vid_write(chip, vid - 1);
1788         if (err)
1789                 return err;
1790
1791         err = _mv88e6xxx_vtu_getnext(chip, entry);
1792         if (err)
1793                 return err;
1794
1795         if (entry->vid != vid || !entry->valid) {
1796                 if (!creat)
1797                         return -EOPNOTSUPP;
1798                 /* -ENOENT would've been more appropriate, but switchdev expects
1799                  * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
1800                  */
1801
1802                 err = _mv88e6xxx_vtu_new(chip, vid, entry);
1803         }
1804
1805         return err;
1806 }
1807
1808 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1809                                         u16 vid_begin, u16 vid_end)
1810 {
1811         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1812         struct mv88e6xxx_vtu_stu_entry vlan;
1813         int i, err;
1814
1815         if (!vid_begin)
1816                 return -EOPNOTSUPP;
1817
1818         mutex_lock(&chip->reg_lock);
1819
1820         err = _mv88e6xxx_vtu_vid_write(chip, vid_begin - 1);
1821         if (err)
1822                 goto unlock;
1823
1824         do {
1825                 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
1826                 if (err)
1827                         goto unlock;
1828
1829                 if (!vlan.valid)
1830                         break;
1831
1832                 if (vlan.vid > vid_end)
1833                         break;
1834
1835                 for (i = 0; i < chip->info->num_ports; ++i) {
1836                         if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1837                                 continue;
1838
1839                         if (vlan.data[i] ==
1840                             GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1841                                 continue;
1842
1843                         if (chip->ports[i].bridge_dev ==
1844                             chip->ports[port].bridge_dev)
1845                                 break; /* same bridge, check next VLAN */
1846
1847                         netdev_warn(ds->ports[port].netdev,
1848                                     "hardware VLAN %d already used by %s\n",
1849                                     vlan.vid,
1850                                     netdev_name(chip->ports[i].bridge_dev));
1851                         err = -EOPNOTSUPP;
1852                         goto unlock;
1853                 }
1854         } while (vlan.vid < vid_end);
1855
1856 unlock:
1857         mutex_unlock(&chip->reg_lock);
1858
1859         return err;
1860 }
1861
1862 static const char * const mv88e6xxx_port_8021q_mode_names[] = {
1863         [PORT_CONTROL_2_8021Q_DISABLED] = "Disabled",
1864         [PORT_CONTROL_2_8021Q_FALLBACK] = "Fallback",
1865         [PORT_CONTROL_2_8021Q_CHECK] = "Check",
1866         [PORT_CONTROL_2_8021Q_SECURE] = "Secure",
1867 };
1868
1869 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1870                                          bool vlan_filtering)
1871 {
1872         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1873         u16 old, new = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE :
1874                 PORT_CONTROL_2_8021Q_DISABLED;
1875         int ret;
1876
1877         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1878                 return -EOPNOTSUPP;
1879
1880         mutex_lock(&chip->reg_lock);
1881
1882         ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_CONTROL_2);
1883         if (ret < 0)
1884                 goto unlock;
1885
1886         old = ret & PORT_CONTROL_2_8021Q_MASK;
1887
1888         if (new != old) {
1889                 ret &= ~PORT_CONTROL_2_8021Q_MASK;
1890                 ret |= new & PORT_CONTROL_2_8021Q_MASK;
1891
1892                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL_2,
1893                                            ret);
1894                 if (ret < 0)
1895                         goto unlock;
1896
1897                 netdev_dbg(ds->ports[port].netdev, "802.1Q Mode %s (was %s)\n",
1898                            mv88e6xxx_port_8021q_mode_names[new],
1899                            mv88e6xxx_port_8021q_mode_names[old]);
1900         }
1901
1902         ret = 0;
1903 unlock:
1904         mutex_unlock(&chip->reg_lock);
1905
1906         return ret;
1907 }
1908
1909 static int
1910 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1911                             const struct switchdev_obj_port_vlan *vlan,
1912                             struct switchdev_trans *trans)
1913 {
1914         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1915         int err;
1916
1917         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1918                 return -EOPNOTSUPP;
1919
1920         /* If the requested port doesn't belong to the same bridge as the VLAN
1921          * members, do not support it (yet) and fallback to software VLAN.
1922          */
1923         err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1924                                            vlan->vid_end);
1925         if (err)
1926                 return err;
1927
1928         /* We don't need any dynamic resource from the kernel (yet),
1929          * so skip the prepare phase.
1930          */
1931         return 0;
1932 }
1933
1934 static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
1935                                     u16 vid, bool untagged)
1936 {
1937         struct mv88e6xxx_vtu_stu_entry vlan;
1938         int err;
1939
1940         err = _mv88e6xxx_vtu_get(chip, vid, &vlan, true);
1941         if (err)
1942                 return err;
1943
1944         vlan.data[port] = untagged ?
1945                 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
1946                 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
1947
1948         return _mv88e6xxx_vtu_loadpurge(chip, &vlan);
1949 }
1950
1951 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1952                                     const struct switchdev_obj_port_vlan *vlan,
1953                                     struct switchdev_trans *trans)
1954 {
1955         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1956         bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1957         bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1958         u16 vid;
1959
1960         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1961                 return;
1962
1963         mutex_lock(&chip->reg_lock);
1964
1965         for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
1966                 if (_mv88e6xxx_port_vlan_add(chip, port, vid, untagged))
1967                         netdev_err(ds->ports[port].netdev,
1968                                    "failed to add VLAN %d%c\n",
1969                                    vid, untagged ? 'u' : 't');
1970
1971         if (pvid && _mv88e6xxx_port_pvid_set(chip, port, vlan->vid_end))
1972                 netdev_err(ds->ports[port].netdev, "failed to set PVID %d\n",
1973                            vlan->vid_end);
1974
1975         mutex_unlock(&chip->reg_lock);
1976 }
1977
1978 static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
1979                                     int port, u16 vid)
1980 {
1981         struct dsa_switch *ds = chip->ds;
1982         struct mv88e6xxx_vtu_stu_entry vlan;
1983         int i, err;
1984
1985         err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
1986         if (err)
1987                 return err;
1988
1989         /* Tell switchdev if this VLAN is handled in software */
1990         if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1991                 return -EOPNOTSUPP;
1992
1993         vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1994
1995         /* keep the VLAN unless all ports are excluded */
1996         vlan.valid = false;
1997         for (i = 0; i < chip->info->num_ports; ++i) {
1998                 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1999                         continue;
2000
2001                 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
2002                         vlan.valid = true;
2003                         break;
2004                 }
2005         }
2006
2007         err = _mv88e6xxx_vtu_loadpurge(chip, &vlan);
2008         if (err)
2009                 return err;
2010
2011         return _mv88e6xxx_atu_remove(chip, vlan.fid, port, false);
2012 }
2013
2014 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
2015                                    const struct switchdev_obj_port_vlan *vlan)
2016 {
2017         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2018         u16 pvid, vid;
2019         int err = 0;
2020
2021         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
2022                 return -EOPNOTSUPP;
2023
2024         mutex_lock(&chip->reg_lock);
2025
2026         err = _mv88e6xxx_port_pvid_get(chip, port, &pvid);
2027         if (err)
2028                 goto unlock;
2029
2030         for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
2031                 err = _mv88e6xxx_port_vlan_del(chip, port, vid);
2032                 if (err)
2033                         goto unlock;
2034
2035                 if (vid == pvid) {
2036                         err = _mv88e6xxx_port_pvid_set(chip, port, 0);
2037                         if (err)
2038                                 goto unlock;
2039                 }
2040         }
2041
2042 unlock:
2043         mutex_unlock(&chip->reg_lock);
2044
2045         return err;
2046 }
2047
2048 static int _mv88e6xxx_atu_mac_write(struct mv88e6xxx_chip *chip,
2049                                     const unsigned char *addr)
2050 {
2051         int i, ret;
2052
2053         for (i = 0; i < 3; i++) {
2054                 ret = _mv88e6xxx_reg_write(
2055                         chip, REG_GLOBAL, GLOBAL_ATU_MAC_01 + i,
2056                         (addr[i * 2] << 8) | addr[i * 2 + 1]);
2057                 if (ret < 0)
2058                         return ret;
2059         }
2060
2061         return 0;
2062 }
2063
2064 static int _mv88e6xxx_atu_mac_read(struct mv88e6xxx_chip *chip,
2065                                    unsigned char *addr)
2066 {
2067         int i, ret;
2068
2069         for (i = 0; i < 3; i++) {
2070                 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
2071                                           GLOBAL_ATU_MAC_01 + i);
2072                 if (ret < 0)
2073                         return ret;
2074                 addr[i * 2] = ret >> 8;
2075                 addr[i * 2 + 1] = ret & 0xff;
2076         }
2077
2078         return 0;
2079 }
2080
2081 static int _mv88e6xxx_atu_load(struct mv88e6xxx_chip *chip,
2082                                struct mv88e6xxx_atu_entry *entry)
2083 {
2084         int ret;
2085
2086         ret = _mv88e6xxx_atu_wait(chip);
2087         if (ret < 0)
2088                 return ret;
2089
2090         ret = _mv88e6xxx_atu_mac_write(chip, entry->mac);
2091         if (ret < 0)
2092                 return ret;
2093
2094         ret = _mv88e6xxx_atu_data_write(chip, entry);
2095         if (ret < 0)
2096                 return ret;
2097
2098         return _mv88e6xxx_atu_cmd(chip, entry->fid, GLOBAL_ATU_OP_LOAD_DB);
2099 }
2100
2101 static int _mv88e6xxx_port_fdb_load(struct mv88e6xxx_chip *chip, int port,
2102                                     const unsigned char *addr, u16 vid,
2103                                     u8 state)
2104 {
2105         struct mv88e6xxx_atu_entry entry = { 0 };
2106         struct mv88e6xxx_vtu_stu_entry vlan;
2107         int err;
2108
2109         /* Null VLAN ID corresponds to the port private database */
2110         if (vid == 0)
2111                 err = _mv88e6xxx_port_fid_get(chip, port, &vlan.fid);
2112         else
2113                 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
2114         if (err)
2115                 return err;
2116
2117         entry.fid = vlan.fid;
2118         entry.state = state;
2119         ether_addr_copy(entry.mac, addr);
2120         if (state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2121                 entry.trunk = false;
2122                 entry.portv_trunkid = BIT(port);
2123         }
2124
2125         return _mv88e6xxx_atu_load(chip, &entry);
2126 }
2127
2128 static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
2129                                       const struct switchdev_obj_port_fdb *fdb,
2130                                       struct switchdev_trans *trans)
2131 {
2132         /* We don't need any dynamic resource from the kernel (yet),
2133          * so skip the prepare phase.
2134          */
2135         return 0;
2136 }
2137
2138 static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2139                                    const struct switchdev_obj_port_fdb *fdb,
2140                                    struct switchdev_trans *trans)
2141 {
2142         int state = is_multicast_ether_addr(fdb->addr) ?
2143                 GLOBAL_ATU_DATA_STATE_MC_STATIC :
2144                 GLOBAL_ATU_DATA_STATE_UC_STATIC;
2145         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2146
2147         mutex_lock(&chip->reg_lock);
2148         if (_mv88e6xxx_port_fdb_load(chip, port, fdb->addr, fdb->vid, state))
2149                 netdev_err(ds->ports[port].netdev,
2150                            "failed to load MAC address\n");
2151         mutex_unlock(&chip->reg_lock);
2152 }
2153
2154 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2155                                   const struct switchdev_obj_port_fdb *fdb)
2156 {
2157         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2158         int ret;
2159
2160         mutex_lock(&chip->reg_lock);
2161         ret = _mv88e6xxx_port_fdb_load(chip, port, fdb->addr, fdb->vid,
2162                                        GLOBAL_ATU_DATA_STATE_UNUSED);
2163         mutex_unlock(&chip->reg_lock);
2164
2165         return ret;
2166 }
2167
2168 static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
2169                                   struct mv88e6xxx_atu_entry *entry)
2170 {
2171         struct mv88e6xxx_atu_entry next = { 0 };
2172         int ret;
2173
2174         next.fid = fid;
2175
2176         ret = _mv88e6xxx_atu_wait(chip);
2177         if (ret < 0)
2178                 return ret;
2179
2180         ret = _mv88e6xxx_atu_cmd(chip, fid, GLOBAL_ATU_OP_GET_NEXT_DB);
2181         if (ret < 0)
2182                 return ret;
2183
2184         ret = _mv88e6xxx_atu_mac_read(chip, next.mac);
2185         if (ret < 0)
2186                 return ret;
2187
2188         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_ATU_DATA);
2189         if (ret < 0)
2190                 return ret;
2191
2192         next.state = ret & GLOBAL_ATU_DATA_STATE_MASK;
2193         if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2194                 unsigned int mask, shift;
2195
2196                 if (ret & GLOBAL_ATU_DATA_TRUNK) {
2197                         next.trunk = true;
2198                         mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
2199                         shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
2200                 } else {
2201                         next.trunk = false;
2202                         mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
2203                         shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
2204                 }
2205
2206                 next.portv_trunkid = (ret & mask) >> shift;
2207         }
2208
2209         *entry = next;
2210         return 0;
2211 }
2212
2213 static int _mv88e6xxx_port_fdb_dump_one(struct mv88e6xxx_chip *chip,
2214                                         u16 fid, u16 vid, int port,
2215                                         struct switchdev_obj_port_fdb *fdb,
2216                                         int (*cb)(struct switchdev_obj *obj))
2217 {
2218         struct mv88e6xxx_atu_entry addr = {
2219                 .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
2220         };
2221         int err;
2222
2223         err = _mv88e6xxx_atu_mac_write(chip, addr.mac);
2224         if (err)
2225                 return err;
2226
2227         do {
2228                 err = _mv88e6xxx_atu_getnext(chip, fid, &addr);
2229                 if (err)
2230                         break;
2231
2232                 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2233                         break;
2234
2235                 if (!addr.trunk && addr.portv_trunkid & BIT(port)) {
2236                         bool is_static = addr.state ==
2237                                 (is_multicast_ether_addr(addr.mac) ?
2238                                  GLOBAL_ATU_DATA_STATE_MC_STATIC :
2239                                  GLOBAL_ATU_DATA_STATE_UC_STATIC);
2240
2241                         fdb->vid = vid;
2242                         ether_addr_copy(fdb->addr, addr.mac);
2243                         fdb->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE;
2244
2245                         err = cb(&fdb->obj);
2246                         if (err)
2247                                 break;
2248                 }
2249         } while (!is_broadcast_ether_addr(addr.mac));
2250
2251         return err;
2252 }
2253
2254 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2255                                    struct switchdev_obj_port_fdb *fdb,
2256                                    int (*cb)(struct switchdev_obj *obj))
2257 {
2258         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2259         struct mv88e6xxx_vtu_stu_entry vlan = {
2260                 .vid = GLOBAL_VTU_VID_MASK, /* all ones */
2261         };
2262         u16 fid;
2263         int err;
2264
2265         mutex_lock(&chip->reg_lock);
2266
2267         /* Dump port's default Filtering Information Database (VLAN ID 0) */
2268         err = _mv88e6xxx_port_fid_get(chip, port, &fid);
2269         if (err)
2270                 goto unlock;
2271
2272         err = _mv88e6xxx_port_fdb_dump_one(chip, fid, 0, port, fdb, cb);
2273         if (err)
2274                 goto unlock;
2275
2276         /* Dump VLANs' Filtering Information Databases */
2277         err = _mv88e6xxx_vtu_vid_write(chip, vlan.vid);
2278         if (err)
2279                 goto unlock;
2280
2281         do {
2282                 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
2283                 if (err)
2284                         break;
2285
2286                 if (!vlan.valid)
2287                         break;
2288
2289                 err = _mv88e6xxx_port_fdb_dump_one(chip, vlan.fid, vlan.vid,
2290                                                    port, fdb, cb);
2291                 if (err)
2292                         break;
2293         } while (vlan.vid < GLOBAL_VTU_VID_MASK);
2294
2295 unlock:
2296         mutex_unlock(&chip->reg_lock);
2297
2298         return err;
2299 }
2300
2301 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2302                                       struct net_device *bridge)
2303 {
2304         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2305         int i, err = 0;
2306
2307         mutex_lock(&chip->reg_lock);
2308
2309         /* Assign the bridge and remap each port's VLANTable */
2310         chip->ports[port].bridge_dev = bridge;
2311
2312         for (i = 0; i < chip->info->num_ports; ++i) {
2313                 if (chip->ports[i].bridge_dev == bridge) {
2314                         err = _mv88e6xxx_port_based_vlan_map(chip, i);
2315                         if (err)
2316                                 break;
2317                 }
2318         }
2319
2320         mutex_unlock(&chip->reg_lock);
2321
2322         return err;
2323 }
2324
2325 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port)
2326 {
2327         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2328         struct net_device *bridge = chip->ports[port].bridge_dev;
2329         int i;
2330
2331         mutex_lock(&chip->reg_lock);
2332
2333         /* Unassign the bridge and remap each port's VLANTable */
2334         chip->ports[port].bridge_dev = NULL;
2335
2336         for (i = 0; i < chip->info->num_ports; ++i)
2337                 if (i == port || chip->ports[i].bridge_dev == bridge)
2338                         if (_mv88e6xxx_port_based_vlan_map(chip, i))
2339                                 netdev_warn(ds->ports[i].netdev,
2340                                             "failed to remap\n");
2341
2342         mutex_unlock(&chip->reg_lock);
2343 }
2344
2345 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
2346 {
2347         bool ppu_active = mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE);
2348         u16 is_reset = (ppu_active ? 0x8800 : 0xc800);
2349         struct gpio_desc *gpiod = chip->reset;
2350         unsigned long timeout;
2351         int ret;
2352         int i;
2353
2354         /* Set all ports to the disabled state. */
2355         for (i = 0; i < chip->info->num_ports; i++) {
2356                 ret = _mv88e6xxx_reg_read(chip, REG_PORT(i), PORT_CONTROL);
2357                 if (ret < 0)
2358                         return ret;
2359
2360                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(i), PORT_CONTROL,
2361                                            ret & 0xfffc);
2362                 if (ret)
2363                         return ret;
2364         }
2365
2366         /* Wait for transmit queues to drain. */
2367         usleep_range(2000, 4000);
2368
2369         /* If there is a gpio connected to the reset pin, toggle it */
2370         if (gpiod) {
2371                 gpiod_set_value_cansleep(gpiod, 1);
2372                 usleep_range(10000, 20000);
2373                 gpiod_set_value_cansleep(gpiod, 0);
2374                 usleep_range(10000, 20000);
2375         }
2376
2377         /* Reset the switch. Keep the PPU active if requested. The PPU
2378          * needs to be active to support indirect phy register access
2379          * through global registers 0x18 and 0x19.
2380          */
2381         if (ppu_active)
2382                 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, 0x04, 0xc000);
2383         else
2384                 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, 0x04, 0xc400);
2385         if (ret)
2386                 return ret;
2387
2388         /* Wait up to one second for reset to complete. */
2389         timeout = jiffies + 1 * HZ;
2390         while (time_before(jiffies, timeout)) {
2391                 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, 0x00);
2392                 if (ret < 0)
2393                         return ret;
2394
2395                 if ((ret & is_reset) == is_reset)
2396                         break;
2397                 usleep_range(1000, 2000);
2398         }
2399         if (time_after(jiffies, timeout))
2400                 ret = -ETIMEDOUT;
2401         else
2402                 ret = 0;
2403
2404         return ret;
2405 }
2406
2407 static int mv88e6xxx_serdes_power_on(struct mv88e6xxx_chip *chip)
2408 {
2409         u16 val;
2410         int err;
2411
2412         /* Clear Power Down bit */
2413         err = mv88e6xxx_serdes_read(chip, MII_BMCR, &val);
2414         if (err)
2415                 return err;
2416
2417         if (val & BMCR_PDOWN) {
2418                 val &= ~BMCR_PDOWN;
2419                 err = mv88e6xxx_serdes_write(chip, MII_BMCR, val);
2420         }
2421
2422         return err;
2423 }
2424
2425 static int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port,
2426                                int reg, u16 *val)
2427 {
2428         int addr = chip->info->port_base_addr + port;
2429
2430         if (port >= chip->info->num_ports)
2431                 return -EINVAL;
2432
2433         return mv88e6xxx_read(chip, addr, reg, val);
2434 }
2435
2436 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
2437 {
2438         struct dsa_switch *ds = chip->ds;
2439         int ret;
2440         u16 reg;
2441
2442         if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2443             mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2444             mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip) ||
2445             mv88e6xxx_6065_family(chip) || mv88e6xxx_6320_family(chip)) {
2446                 /* MAC Forcing register: don't force link, speed,
2447                  * duplex or flow control state to any particular
2448                  * values on physical ports, but force the CPU port
2449                  * and all DSA ports to their maximum bandwidth and
2450                  * full duplex.
2451                  */
2452                 reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_PCS_CTRL);
2453                 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
2454                         reg &= ~PORT_PCS_CTRL_UNFORCED;
2455                         reg |= PORT_PCS_CTRL_FORCE_LINK |
2456                                 PORT_PCS_CTRL_LINK_UP |
2457                                 PORT_PCS_CTRL_DUPLEX_FULL |
2458                                 PORT_PCS_CTRL_FORCE_DUPLEX;
2459                         if (mv88e6xxx_6065_family(chip))
2460                                 reg |= PORT_PCS_CTRL_100;
2461                         else
2462                                 reg |= PORT_PCS_CTRL_1000;
2463                 } else {
2464                         reg |= PORT_PCS_CTRL_UNFORCED;
2465                 }
2466
2467                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2468                                            PORT_PCS_CTRL, reg);
2469                 if (ret)
2470                         return ret;
2471         }
2472
2473         /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2474          * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2475          * tunneling, determine priority by looking at 802.1p and IP
2476          * priority fields (IP prio has precedence), and set STP state
2477          * to Forwarding.
2478          *
2479          * If this is the CPU link, use DSA or EDSA tagging depending
2480          * on which tagging mode was configured.
2481          *
2482          * If this is a link to another switch, use DSA tagging mode.
2483          *
2484          * If this is the upstream port for this switch, enable
2485          * forwarding of unknown unicasts and multicasts.
2486          */
2487         reg = 0;
2488         if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2489             mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2490             mv88e6xxx_6095_family(chip) || mv88e6xxx_6065_family(chip) ||
2491             mv88e6xxx_6185_family(chip) || mv88e6xxx_6320_family(chip))
2492                 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
2493                 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2494                 PORT_CONTROL_STATE_FORWARDING;
2495         if (dsa_is_cpu_port(ds, port)) {
2496                 if (mv88e6xxx_6095_family(chip) || mv88e6xxx_6185_family(chip))
2497                         reg |= PORT_CONTROL_DSA_TAG;
2498                 if (mv88e6xxx_6352_family(chip) ||
2499                     mv88e6xxx_6351_family(chip) ||
2500                     mv88e6xxx_6165_family(chip) ||
2501                     mv88e6xxx_6097_family(chip) ||
2502                     mv88e6xxx_6320_family(chip)) {
2503                         reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA |
2504                                 PORT_CONTROL_FORWARD_UNKNOWN |
2505                                 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2506                 }
2507
2508                 if (mv88e6xxx_6352_family(chip) ||
2509                     mv88e6xxx_6351_family(chip) ||
2510                     mv88e6xxx_6165_family(chip) ||
2511                     mv88e6xxx_6097_family(chip) ||
2512                     mv88e6xxx_6095_family(chip) ||
2513                     mv88e6xxx_6065_family(chip) ||
2514                     mv88e6xxx_6185_family(chip) ||
2515                     mv88e6xxx_6320_family(chip)) {
2516                         reg |= PORT_CONTROL_EGRESS_ADD_TAG;
2517                 }
2518         }
2519         if (dsa_is_dsa_port(ds, port)) {
2520                 if (mv88e6xxx_6095_family(chip) ||
2521                     mv88e6xxx_6185_family(chip))
2522                         reg |= PORT_CONTROL_DSA_TAG;
2523                 if (mv88e6xxx_6352_family(chip) ||
2524                     mv88e6xxx_6351_family(chip) ||
2525                     mv88e6xxx_6165_family(chip) ||
2526                     mv88e6xxx_6097_family(chip) ||
2527                     mv88e6xxx_6320_family(chip)) {
2528                         reg |= PORT_CONTROL_FRAME_MODE_DSA;
2529                 }
2530
2531                 if (port == dsa_upstream_port(ds))
2532                         reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2533                                 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2534         }
2535         if (reg) {
2536                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2537                                            PORT_CONTROL, reg);
2538                 if (ret)
2539                         return ret;
2540         }
2541
2542         /* If this port is connected to a SerDes, make sure the SerDes is not
2543          * powered down.
2544          */
2545         if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_SERDES)) {
2546                 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_STATUS);
2547                 if (ret < 0)
2548                         return ret;
2549                 ret &= PORT_STATUS_CMODE_MASK;
2550                 if ((ret == PORT_STATUS_CMODE_100BASE_X) ||
2551                     (ret == PORT_STATUS_CMODE_1000BASE_X) ||
2552                     (ret == PORT_STATUS_CMODE_SGMII)) {
2553                         ret = mv88e6xxx_serdes_power_on(chip);
2554                         if (ret < 0)
2555                                 return ret;
2556                 }
2557         }
2558
2559         /* Port Control 2: don't force a good FCS, set the maximum frame size to
2560          * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
2561          * untagged frames on this port, do a destination address lookup on all
2562          * received packets as usual, disable ARP mirroring and don't send a
2563          * copy of all transmitted/received frames on this port to the CPU.
2564          */
2565         reg = 0;
2566         if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2567             mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2568             mv88e6xxx_6095_family(chip) || mv88e6xxx_6320_family(chip) ||
2569             mv88e6xxx_6185_family(chip))
2570                 reg = PORT_CONTROL_2_MAP_DA;
2571
2572         if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2573             mv88e6xxx_6165_family(chip) || mv88e6xxx_6320_family(chip))
2574                 reg |= PORT_CONTROL_2_JUMBO_10240;
2575
2576         if (mv88e6xxx_6095_family(chip) || mv88e6xxx_6185_family(chip)) {
2577                 /* Set the upstream port this port should use */
2578                 reg |= dsa_upstream_port(ds);
2579                 /* enable forwarding of unknown multicast addresses to
2580                  * the upstream port
2581                  */
2582                 if (port == dsa_upstream_port(ds))
2583                         reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
2584         }
2585
2586         reg |= PORT_CONTROL_2_8021Q_DISABLED;
2587
2588         if (reg) {
2589                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2590                                            PORT_CONTROL_2, reg);
2591                 if (ret)
2592                         return ret;
2593         }
2594
2595         /* Port Association Vector: when learning source addresses
2596          * of packets, add the address to the address database using
2597          * a port bitmap that has only the bit for this port set and
2598          * the other bits clear.
2599          */
2600         reg = 1 << port;
2601         /* Disable learning for CPU port */
2602         if (dsa_is_cpu_port(ds, port))
2603                 reg = 0;
2604
2605         ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_ASSOC_VECTOR,
2606                                    reg);
2607         if (ret)
2608                 return ret;
2609
2610         /* Egress rate control 2: disable egress rate control. */
2611         ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_RATE_CONTROL_2,
2612                                    0x0000);
2613         if (ret)
2614                 return ret;
2615
2616         if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2617             mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2618             mv88e6xxx_6320_family(chip)) {
2619                 /* Do not limit the period of time that this port can
2620                  * be paused for by the remote end or the period of
2621                  * time that this port can pause the remote end.
2622                  */
2623                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2624                                            PORT_PAUSE_CTRL, 0x0000);
2625                 if (ret)
2626                         return ret;
2627
2628                 /* Port ATU control: disable limiting the number of
2629                  * address database entries that this port is allowed
2630                  * to use.
2631                  */
2632                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2633                                            PORT_ATU_CONTROL, 0x0000);
2634                 /* Priority Override: disable DA, SA and VTU priority
2635                  * override.
2636                  */
2637                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2638                                            PORT_PRI_OVERRIDE, 0x0000);
2639                 if (ret)
2640                         return ret;
2641
2642                 /* Port Ethertype: use the Ethertype DSA Ethertype
2643                  * value.
2644                  */
2645                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2646                                            PORT_ETH_TYPE, ETH_P_EDSA);
2647                 if (ret)
2648                         return ret;
2649                 /* Tag Remap: use an identity 802.1p prio -> switch
2650                  * prio mapping.
2651                  */
2652                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2653                                            PORT_TAG_REGMAP_0123, 0x3210);
2654                 if (ret)
2655                         return ret;
2656
2657                 /* Tag Remap 2: use an identity 802.1p prio -> switch
2658                  * prio mapping.
2659                  */
2660                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2661                                            PORT_TAG_REGMAP_4567, 0x7654);
2662                 if (ret)
2663                         return ret;
2664         }
2665
2666         if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2667             mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2668             mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip) ||
2669             mv88e6xxx_6320_family(chip)) {
2670                 /* Rate Control: disable ingress rate limiting. */
2671                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2672                                            PORT_RATE_CONTROL, 0x0001);
2673                 if (ret)
2674                         return ret;
2675         }
2676
2677         /* Port Control 1: disable trunking, disable sending
2678          * learning messages to this port.
2679          */
2680         ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL_1,
2681                                    0x0000);
2682         if (ret)
2683                 return ret;
2684
2685         /* Port based VLAN map: give each port the same default address
2686          * database, and allow bidirectional communication between the
2687          * CPU and DSA port(s), and the other ports.
2688          */
2689         ret = _mv88e6xxx_port_fid_set(chip, port, 0);
2690         if (ret)
2691                 return ret;
2692
2693         ret = _mv88e6xxx_port_based_vlan_map(chip, port);
2694         if (ret)
2695                 return ret;
2696
2697         /* Default VLAN ID and priority: don't set a default VLAN
2698          * ID, and set the default packet priority to zero.
2699          */
2700         ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_DEFAULT_VLAN,
2701                                    0x0000);
2702         if (ret)
2703                 return ret;
2704
2705         return 0;
2706 }
2707
2708 static int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
2709 {
2710         int err;
2711
2712         err = mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_MAC_01,
2713                               (addr[0] << 8) | addr[1]);
2714         if (err)
2715                 return err;
2716
2717         err = mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_MAC_23,
2718                               (addr[2] << 8) | addr[3]);
2719         if (err)
2720                 return err;
2721
2722         return mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_MAC_45,
2723                                (addr[4] << 8) | addr[5]);
2724 }
2725
2726 static int mv88e6xxx_g1_set_age_time(struct mv88e6xxx_chip *chip,
2727                                      unsigned int msecs)
2728 {
2729         const unsigned int coeff = chip->info->age_time_coeff;
2730         const unsigned int min = 0x01 * coeff;
2731         const unsigned int max = 0xff * coeff;
2732         u8 age_time;
2733         u16 val;
2734         int err;
2735
2736         if (msecs < min || msecs > max)
2737                 return -ERANGE;
2738
2739         /* Round to nearest multiple of coeff */
2740         age_time = (msecs + coeff / 2) / coeff;
2741
2742         err = mv88e6xxx_read(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL, &val);
2743         if (err)
2744                 return err;
2745
2746         /* AgeTime is 11:4 bits */
2747         val &= ~0xff0;
2748         val |= age_time << 4;
2749
2750         return mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL, val);
2751 }
2752
2753 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2754                                      unsigned int ageing_time)
2755 {
2756         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2757         int err;
2758
2759         mutex_lock(&chip->reg_lock);
2760         err = mv88e6xxx_g1_set_age_time(chip, ageing_time);
2761         mutex_unlock(&chip->reg_lock);
2762
2763         return err;
2764 }
2765
2766 static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
2767 {
2768         struct dsa_switch *ds = chip->ds;
2769         u32 upstream_port = dsa_upstream_port(ds);
2770         u16 reg;
2771         int err;
2772
2773         /* Enable the PHY Polling Unit if present, don't discard any packets,
2774          * and mask all interrupt sources.
2775          */
2776         reg = 0;
2777         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU) ||
2778             mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE))
2779                 reg |= GLOBAL_CONTROL_PPU_ENABLE;
2780
2781         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL, reg);
2782         if (err)
2783                 return err;
2784
2785         /* Configure the upstream port, and configure it as the port to which
2786          * ingress and egress and ARP monitor frames are to be sent.
2787          */
2788         reg = upstream_port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT |
2789                 upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT |
2790                 upstream_port << GLOBAL_MONITOR_CONTROL_ARP_SHIFT;
2791         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_MONITOR_CONTROL,
2792                                    reg);
2793         if (err)
2794                 return err;
2795
2796         /* Disable remote management, and set the switch's DSA device number. */
2797         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL_2,
2798                                    GLOBAL_CONTROL_2_MULTIPLE_CASCADE |
2799                                    (ds->index & 0x1f));
2800         if (err)
2801                 return err;
2802
2803         /* Clear all the VTU and STU entries */
2804         err = _mv88e6xxx_vtu_stu_flush(chip);
2805         if (err < 0)
2806                 return err;
2807
2808         /* Set the default address aging time to 5 minutes, and
2809          * enable address learn messages to be sent to all message
2810          * ports.
2811          */
2812         err = mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL,
2813                               GLOBAL_ATU_CONTROL_LEARN2ALL);
2814         if (err)
2815                 return err;
2816
2817         err = mv88e6xxx_g1_set_age_time(chip, 300000);
2818         if (err)
2819                 return err;
2820
2821         /* Clear all ATU entries */
2822         err = _mv88e6xxx_atu_flush(chip, 0, true);
2823         if (err)
2824                 return err;
2825
2826         /* Configure the IP ToS mapping registers. */
2827         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000);
2828         if (err)
2829                 return err;
2830         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000);
2831         if (err)
2832                 return err;
2833         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555);
2834         if (err)
2835                 return err;
2836         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555);
2837         if (err)
2838                 return err;
2839         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa);
2840         if (err)
2841                 return err;
2842         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa);
2843         if (err)
2844                 return err;
2845         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff);
2846         if (err)
2847                 return err;
2848         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff);
2849         if (err)
2850                 return err;
2851
2852         /* Configure the IEEE 802.1p priority mapping register. */
2853         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41);
2854         if (err)
2855                 return err;
2856
2857         /* Clear the statistics counters for all ports */
2858         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP,
2859                                    GLOBAL_STATS_OP_FLUSH_ALL);
2860         if (err)
2861                 return err;
2862
2863         /* Wait for the flush to complete. */
2864         err = _mv88e6xxx_stats_wait(chip);
2865         if (err)
2866                 return err;
2867
2868         return 0;
2869 }
2870
2871 static int mv88e6xxx_g2_device_mapping_write(struct mv88e6xxx_chip *chip,
2872                                              int target, int port)
2873 {
2874         u16 val = (target << 8) | (port & 0xf);
2875
2876         return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_DEVICE_MAPPING, val);
2877 }
2878
2879 static int mv88e6xxx_g2_set_device_mapping(struct mv88e6xxx_chip *chip)
2880 {
2881         int target, port;
2882         int err;
2883
2884         /* Initialize the routing port to the 32 possible target devices */
2885         for (target = 0; target < 32; ++target) {
2886                 port = 0xf;
2887
2888                 if (target < DSA_MAX_SWITCHES) {
2889                         port = chip->ds->rtable[target];
2890                         if (port == DSA_RTABLE_NONE)
2891                                 port = 0xf;
2892                 }
2893
2894                 err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
2895                 if (err)
2896                         break;
2897         }
2898
2899         return err;
2900 }
2901
2902 static int mv88e6xxx_g2_trunk_mask_write(struct mv88e6xxx_chip *chip, int num,
2903                                          bool hask, u16 mask)
2904 {
2905         const u16 port_mask = BIT(chip->info->num_ports) - 1;
2906         u16 val = (num << 12) | (mask & port_mask);
2907
2908         if (hask)
2909                 val |= GLOBAL2_TRUNK_MASK_HASK;
2910
2911         return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_TRUNK_MASK, val);
2912 }
2913
2914 static int mv88e6xxx_g2_trunk_mapping_write(struct mv88e6xxx_chip *chip, int id,
2915                                             u16 map)
2916 {
2917         const u16 port_mask = BIT(chip->info->num_ports) - 1;
2918         u16 val = (id << 11) | (map & port_mask);
2919
2920         return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_TRUNK_MAPPING, val);
2921 }
2922
2923 static int mv88e6xxx_g2_clear_trunk(struct mv88e6xxx_chip *chip)
2924 {
2925         const u16 port_mask = BIT(chip->info->num_ports) - 1;
2926         int i, err;
2927
2928         /* Clear all eight possible Trunk Mask vectors */
2929         for (i = 0; i < 8; ++i) {
2930                 err = mv88e6xxx_g2_trunk_mask_write(chip, i, false, port_mask);
2931                 if (err)
2932                         return err;
2933         }
2934
2935         /* Clear all sixteen possible Trunk ID routing vectors */
2936         for (i = 0; i < 16; ++i) {
2937                 err = mv88e6xxx_g2_trunk_mapping_write(chip, i, 0);
2938                 if (err)
2939                         return err;
2940         }
2941
2942         return 0;
2943 }
2944
2945 static int mv88e6xxx_g2_clear_irl(struct mv88e6xxx_chip *chip)
2946 {
2947         int port, err;
2948
2949         /* Init all Ingress Rate Limit resources of all ports */
2950         for (port = 0; port < chip->info->num_ports; ++port) {
2951                 /* XXX newer chips (like 88E6390) have different 2-bit ops */
2952                 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_IRL_CMD,
2953                                       GLOBAL2_IRL_CMD_OP_INIT_ALL |
2954                                       (port << 8));
2955                 if (err)
2956                         break;
2957
2958                 /* Wait for the operation to complete */
2959                 err = mv88e6xxx_wait(chip, REG_GLOBAL2, GLOBAL2_IRL_CMD,
2960                                      GLOBAL2_IRL_CMD_BUSY);
2961                 if (err)
2962                         break;
2963         }
2964
2965         return err;
2966 }
2967
2968 /* Indirect write to the Switch MAC/WoL/WoF register */
2969 static int mv88e6xxx_g2_switch_mac_write(struct mv88e6xxx_chip *chip,
2970                                          unsigned int pointer, u8 data)
2971 {
2972         u16 val = (pointer << 8) | data;
2973
2974         return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_SWITCH_MAC, val);
2975 }
2976
2977 static int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
2978 {
2979         int i, err;
2980
2981         for (i = 0; i < 6; i++) {
2982                 err = mv88e6xxx_g2_switch_mac_write(chip, i, addr[i]);
2983                 if (err)
2984                         break;
2985         }
2986
2987         return err;
2988 }
2989
2990 static int mv88e6xxx_g2_pot_write(struct mv88e6xxx_chip *chip, int pointer,
2991                                   u8 data)
2992 {
2993         u16 val = (pointer << 8) | (data & 0x7);
2994
2995         return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_PRIO_OVERRIDE, val);
2996 }
2997
2998 static int mv88e6xxx_g2_clear_pot(struct mv88e6xxx_chip *chip)
2999 {
3000         int i, err;
3001
3002         /* Clear all sixteen possible Priority Override entries */
3003         for (i = 0; i < 16; i++) {
3004                 err = mv88e6xxx_g2_pot_write(chip, i, 0);
3005                 if (err)
3006                         break;
3007         }
3008
3009         return err;
3010 }
3011
3012 static int mv88e6xxx_g2_eeprom_wait(struct mv88e6xxx_chip *chip)
3013 {
3014         return mv88e6xxx_wait(chip, REG_GLOBAL2, GLOBAL2_EEPROM_CMD,
3015                               GLOBAL2_EEPROM_CMD_BUSY |
3016                               GLOBAL2_EEPROM_CMD_RUNNING);
3017 }
3018
3019 static int mv88e6xxx_g2_eeprom_cmd(struct mv88e6xxx_chip *chip, u16 cmd)
3020 {
3021         int err;
3022
3023         err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_EEPROM_CMD, cmd);
3024         if (err)
3025                 return err;
3026
3027         return mv88e6xxx_g2_eeprom_wait(chip);
3028 }
3029
3030 static int mv88e6xxx_g2_eeprom_read16(struct mv88e6xxx_chip *chip,
3031                                       u8 addr, u16 *data)
3032 {
3033         u16 cmd = GLOBAL2_EEPROM_CMD_OP_READ | addr;
3034         int err;
3035
3036         err = mv88e6xxx_g2_eeprom_wait(chip);
3037         if (err)
3038                 return err;
3039
3040         err = mv88e6xxx_g2_eeprom_cmd(chip, cmd);
3041         if (err)
3042                 return err;
3043
3044         return mv88e6xxx_read(chip, REG_GLOBAL2, GLOBAL2_EEPROM_DATA, data);
3045 }
3046
3047 static int mv88e6xxx_g2_eeprom_write16(struct mv88e6xxx_chip *chip,
3048                                        u8 addr, u16 data)
3049 {
3050         u16 cmd = GLOBAL2_EEPROM_CMD_OP_WRITE | addr;
3051         int err;
3052
3053         err = mv88e6xxx_g2_eeprom_wait(chip);
3054         if (err)
3055                 return err;
3056
3057         err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_EEPROM_DATA, data);
3058         if (err)
3059                 return err;
3060
3061         return mv88e6xxx_g2_eeprom_cmd(chip, cmd);
3062 }
3063
3064 static int mv88e6xxx_g2_smi_phy_wait(struct mv88e6xxx_chip *chip)
3065 {
3066         return mv88e6xxx_wait(chip, REG_GLOBAL2, GLOBAL2_SMI_PHY_CMD,
3067                               GLOBAL2_SMI_PHY_CMD_BUSY);
3068 }
3069
3070 static int mv88e6xxx_g2_smi_phy_cmd(struct mv88e6xxx_chip *chip, u16 cmd)
3071 {
3072         int err;
3073
3074         err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_SMI_PHY_CMD, cmd);
3075         if (err)
3076                 return err;
3077
3078         return mv88e6xxx_g2_smi_phy_wait(chip);
3079 }
3080
3081 static int mv88e6xxx_g2_smi_phy_read(struct mv88e6xxx_chip *chip, int addr,
3082                                      int reg, u16 *val)
3083 {
3084         u16 cmd = GLOBAL2_SMI_PHY_CMD_OP_22_READ_DATA | (addr << 5) | reg;
3085         int err;
3086
3087         err = mv88e6xxx_g2_smi_phy_wait(chip);
3088         if (err)
3089                 return err;
3090
3091         err = mv88e6xxx_g2_smi_phy_cmd(chip, cmd);
3092         if (err)
3093                 return err;
3094
3095         return mv88e6xxx_read(chip, REG_GLOBAL2, GLOBAL2_SMI_PHY_DATA, val);
3096 }
3097
3098 static int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip, int addr,
3099                                       int reg, u16 val)
3100 {
3101         u16 cmd = GLOBAL2_SMI_PHY_CMD_OP_22_WRITE_DATA | (addr << 5) | reg;
3102         int err;
3103
3104         err = mv88e6xxx_g2_smi_phy_wait(chip);
3105         if (err)
3106                 return err;
3107
3108         err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_SMI_PHY_DATA, val);
3109         if (err)
3110                 return err;
3111
3112         return mv88e6xxx_g2_smi_phy_cmd(chip, cmd);
3113 }
3114
3115 static const struct mv88e6xxx_ops mv88e6xxx_g2_smi_phy_ops = {
3116         .read = mv88e6xxx_g2_smi_phy_read,
3117         .write = mv88e6xxx_g2_smi_phy_write,
3118 };
3119
3120 static int mv88e6xxx_g2_setup(struct mv88e6xxx_chip *chip)
3121 {
3122         u16 reg;
3123         int err;
3124
3125         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_2X)) {
3126                 /* Consider the frames with reserved multicast destination
3127                  * addresses matching 01:80:c2:00:00:2x as MGMT.
3128                  */
3129                 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_MGMT_EN_2X,
3130                                       0xffff);
3131                 if (err)
3132                         return err;
3133         }
3134
3135         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_0X)) {
3136                 /* Consider the frames with reserved multicast destination
3137                  * addresses matching 01:80:c2:00:00:0x as MGMT.
3138                  */
3139                 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_MGMT_EN_0X,
3140                                       0xffff);
3141                 if (err)
3142                         return err;
3143         }
3144
3145         /* Ignore removed tag data on doubly tagged packets, disable
3146          * flow control messages, force flow control priority to the
3147          * highest, and send all special multicast frames to the CPU
3148          * port at the highest priority.
3149          */
3150         reg = GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI | (0x7 << 4);
3151         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_0X) ||
3152             mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_2X))
3153                 reg |= GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x7;
3154         err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_SWITCH_MGMT, reg);
3155         if (err)
3156                 return err;
3157
3158         /* Program the DSA routing table. */
3159         err = mv88e6xxx_g2_set_device_mapping(chip);
3160         if (err)
3161                 return err;
3162
3163         /* Clear all trunk masks and mapping. */
3164         err = mv88e6xxx_g2_clear_trunk(chip);
3165         if (err)
3166                 return err;
3167
3168         if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_IRL)) {
3169                 /* Disable ingress rate limiting by resetting all per port
3170                  * ingress rate limit resources to their initial state.
3171                  */
3172                 err = mv88e6xxx_g2_clear_irl(chip);
3173                         if (err)
3174                                 return err;
3175         }
3176
3177         if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_PVT)) {
3178                 /* Initialize Cross-chip Port VLAN Table to reset defaults */
3179                 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_PVT_ADDR,
3180                                       GLOBAL2_PVT_ADDR_OP_INIT_ONES);
3181                 if (err)
3182                         return err;
3183         }
3184
3185         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_POT)) {
3186                 /* Clear the priority override table. */
3187                 err = mv88e6xxx_g2_clear_pot(chip);
3188                 if (err)
3189                         return err;
3190         }
3191
3192         return 0;
3193 }
3194
3195 static int mv88e6xxx_setup(struct dsa_switch *ds)
3196 {
3197         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3198         int err;
3199         int i;
3200
3201         chip->ds = ds;
3202         ds->slave_mii_bus = chip->mdio_bus;
3203
3204         mutex_lock(&chip->reg_lock);
3205
3206         err = mv88e6xxx_switch_reset(chip);
3207         if (err)
3208                 goto unlock;
3209
3210         /* Setup Switch Port Registers */
3211         for (i = 0; i < chip->info->num_ports; i++) {
3212                 err = mv88e6xxx_setup_port(chip, i);
3213                 if (err)
3214                         goto unlock;
3215         }
3216
3217         /* Setup Switch Global 1 Registers */
3218         err = mv88e6xxx_g1_setup(chip);
3219         if (err)
3220                 goto unlock;
3221
3222         /* Setup Switch Global 2 Registers */
3223         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_GLOBAL2)) {
3224                 err = mv88e6xxx_g2_setup(chip);
3225                 if (err)
3226                         goto unlock;
3227         }
3228
3229 unlock:
3230         mutex_unlock(&chip->reg_lock);
3231
3232         return err;
3233 }
3234
3235 static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr)
3236 {
3237         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3238         int err;
3239
3240         mutex_lock(&chip->reg_lock);
3241
3242         /* Has an indirect Switch MAC/WoL/WoF register in Global 2? */
3243         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_SWITCH_MAC))
3244                 err = mv88e6xxx_g2_set_switch_mac(chip, addr);
3245         else
3246                 err = mv88e6xxx_g1_set_switch_mac(chip, addr);
3247
3248         mutex_unlock(&chip->reg_lock);
3249
3250         return err;
3251 }
3252
3253 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
3254 {
3255         struct mv88e6xxx_chip *chip = bus->priv;
3256         u16 val;
3257         int err;
3258
3259         if (phy >= chip->info->num_ports)
3260                 return 0xffff;
3261
3262         mutex_lock(&chip->reg_lock);
3263         err = mv88e6xxx_phy_read(chip, phy, reg, &val);
3264         mutex_unlock(&chip->reg_lock);
3265
3266         return err ? err : val;
3267 }
3268
3269 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
3270 {
3271         struct mv88e6xxx_chip *chip = bus->priv;
3272         int err;
3273
3274         if (phy >= chip->info->num_ports)
3275                 return 0xffff;
3276
3277         mutex_lock(&chip->reg_lock);
3278         err = mv88e6xxx_phy_write(chip, phy, reg, val);
3279         mutex_unlock(&chip->reg_lock);
3280
3281         return err;
3282 }
3283
3284 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
3285                                    struct device_node *np)
3286 {
3287         static int index;
3288         struct mii_bus *bus;
3289         int err;
3290
3291         if (np)
3292                 chip->mdio_np = of_get_child_by_name(np, "mdio");
3293
3294         bus = devm_mdiobus_alloc(chip->dev);
3295         if (!bus)
3296                 return -ENOMEM;
3297
3298         bus->priv = (void *)chip;
3299         if (np) {
3300                 bus->name = np->full_name;
3301                 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", np->full_name);
3302         } else {
3303                 bus->name = "mv88e6xxx SMI";
3304                 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
3305         }
3306
3307         bus->read = mv88e6xxx_mdio_read;
3308         bus->write = mv88e6xxx_mdio_write;
3309         bus->parent = chip->dev;
3310
3311         if (chip->mdio_np)
3312                 err = of_mdiobus_register(bus, chip->mdio_np);
3313         else
3314                 err = mdiobus_register(bus);
3315         if (err) {
3316                 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
3317                 goto out;
3318         }
3319         chip->mdio_bus = bus;
3320
3321         return 0;
3322
3323 out:
3324         if (chip->mdio_np)
3325                 of_node_put(chip->mdio_np);
3326
3327         return err;
3328 }
3329
3330 static void mv88e6xxx_mdio_unregister(struct mv88e6xxx_chip *chip)
3331
3332 {
3333         struct mii_bus *bus = chip->mdio_bus;
3334
3335         mdiobus_unregister(bus);
3336
3337         if (chip->mdio_np)
3338                 of_node_put(chip->mdio_np);
3339 }
3340
3341 #ifdef CONFIG_NET_DSA_HWMON
3342
3343 static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp)
3344 {
3345         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3346         u16 val;
3347         int ret;
3348
3349         *temp = 0;
3350
3351         mutex_lock(&chip->reg_lock);
3352
3353         ret = mv88e6xxx_phy_write(chip, 0x0, 0x16, 0x6);
3354         if (ret < 0)
3355                 goto error;
3356
3357         /* Enable temperature sensor */
3358         ret = mv88e6xxx_phy_read(chip, 0x0, 0x1a, &val);
3359         if (ret < 0)
3360                 goto error;
3361
3362         ret = mv88e6xxx_phy_write(chip, 0x0, 0x1a, val | (1 << 5));
3363         if (ret < 0)
3364                 goto error;
3365
3366         /* Wait for temperature to stabilize */
3367         usleep_range(10000, 12000);
3368
3369         ret = mv88e6xxx_phy_read(chip, 0x0, 0x1a, &val);
3370         if (ret < 0)
3371                 goto error;
3372
3373         /* Disable temperature sensor */
3374         ret = mv88e6xxx_phy_write(chip, 0x0, 0x1a, val & ~(1 << 5));
3375         if (ret < 0)
3376                 goto error;
3377
3378         *temp = ((val & 0x1f) - 5) * 5;
3379
3380 error:
3381         mv88e6xxx_phy_write(chip, 0x0, 0x16, 0x0);
3382         mutex_unlock(&chip->reg_lock);
3383         return ret;
3384 }
3385
3386 static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp)
3387 {
3388         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3389         int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3390         u16 val;
3391         int ret;
3392
3393         *temp = 0;
3394
3395         mutex_lock(&chip->reg_lock);
3396         ret = mv88e6xxx_phy_page_read(chip, phy, 6, 27, &val);
3397         mutex_unlock(&chip->reg_lock);
3398         if (ret < 0)
3399                 return ret;
3400
3401         *temp = (val & 0xff) - 25;
3402
3403         return 0;
3404 }
3405
3406 static int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
3407 {
3408         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3409
3410         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP))
3411                 return -EOPNOTSUPP;
3412
3413         if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip))
3414                 return mv88e63xx_get_temp(ds, temp);
3415
3416         return mv88e61xx_get_temp(ds, temp);
3417 }
3418
3419 static int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp)
3420 {
3421         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3422         int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3423         u16 val;
3424         int ret;
3425
3426         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
3427                 return -EOPNOTSUPP;
3428
3429         *temp = 0;
3430
3431         mutex_lock(&chip->reg_lock);
3432         ret = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3433         mutex_unlock(&chip->reg_lock);
3434         if (ret < 0)
3435                 return ret;
3436
3437         *temp = (((val >> 8) & 0x1f) * 5) - 25;
3438
3439         return 0;
3440 }
3441
3442 static int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp)
3443 {
3444         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3445         int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3446         u16 val;
3447         int err;
3448
3449         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
3450                 return -EOPNOTSUPP;
3451
3452         mutex_lock(&chip->reg_lock);
3453         err = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3454         if (err)
3455                 goto unlock;
3456         temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
3457         err = mv88e6xxx_phy_page_write(chip, phy, 6, 26,
3458                                        (val & 0xe0ff) | (temp << 8));
3459 unlock:
3460         mutex_unlock(&chip->reg_lock);
3461
3462         return err;
3463 }
3464
3465 static int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm)
3466 {
3467         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3468         int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3469         u16 val;
3470         int ret;
3471
3472         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
3473                 return -EOPNOTSUPP;
3474
3475         *alarm = false;
3476
3477         mutex_lock(&chip->reg_lock);
3478         ret = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3479         mutex_unlock(&chip->reg_lock);
3480         if (ret < 0)
3481                 return ret;
3482
3483         *alarm = !!(val & 0x40);
3484
3485         return 0;
3486 }
3487 #endif /* CONFIG_NET_DSA_HWMON */
3488
3489 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
3490 {
3491         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3492
3493         return chip->eeprom_len;
3494 }
3495
3496 static int mv88e6xxx_get_eeprom16(struct mv88e6xxx_chip *chip,
3497                                   struct ethtool_eeprom *eeprom, u8 *data)
3498 {
3499         unsigned int offset = eeprom->offset;
3500         unsigned int len = eeprom->len;
3501         u16 val;
3502         int err;
3503
3504         eeprom->len = 0;
3505
3506         if (offset & 1) {
3507                 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
3508                 if (err)
3509                         return err;
3510
3511                 *data++ = (val >> 8) & 0xff;
3512
3513                 offset++;
3514                 len--;
3515                 eeprom->len++;
3516         }
3517
3518         while (len >= 2) {
3519                 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
3520                 if (err)
3521                         return err;
3522
3523                 *data++ = val & 0xff;
3524                 *data++ = (val >> 8) & 0xff;
3525
3526                 offset += 2;
3527                 len -= 2;
3528                 eeprom->len += 2;
3529         }
3530
3531         if (len) {
3532                 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
3533                 if (err)
3534                         return err;
3535
3536                 *data++ = val & 0xff;
3537
3538                 offset++;
3539                 len--;
3540                 eeprom->len++;
3541         }
3542
3543         return 0;
3544 }
3545
3546 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
3547                                 struct ethtool_eeprom *eeprom, u8 *data)
3548 {
3549         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3550         int err;
3551
3552         mutex_lock(&chip->reg_lock);
3553
3554         if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_EEPROM16))
3555                 err = mv88e6xxx_get_eeprom16(chip, eeprom, data);
3556         else
3557                 err = -EOPNOTSUPP;
3558
3559         mutex_unlock(&chip->reg_lock);
3560
3561         if (err)
3562                 return err;
3563
3564         eeprom->magic = 0xc3ec4951;
3565
3566         return 0;
3567 }
3568
3569 static int mv88e6xxx_set_eeprom16(struct mv88e6xxx_chip *chip,
3570                                   struct ethtool_eeprom *eeprom, u8 *data)
3571 {
3572         unsigned int offset = eeprom->offset;
3573         unsigned int len = eeprom->len;
3574         u16 val;
3575         int err;
3576
3577         /* Ensure the RO WriteEn bit is set */
3578         err = mv88e6xxx_read(chip, REG_GLOBAL2, GLOBAL2_EEPROM_CMD, &val);
3579         if (err)
3580                 return err;
3581
3582         if (!(val & GLOBAL2_EEPROM_CMD_WRITE_EN))
3583                 return -EROFS;
3584
3585         eeprom->len = 0;
3586
3587         if (offset & 1) {
3588                 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
3589                 if (err)
3590                         return err;
3591
3592                 val = (*data++ << 8) | (val & 0xff);
3593
3594                 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
3595                 if (err)
3596                         return err;
3597
3598                 offset++;
3599                 len--;
3600                 eeprom->len++;
3601         }
3602
3603         while (len >= 2) {
3604                 val = *data++;
3605                 val |= *data++ << 8;
3606
3607                 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
3608                 if (err)
3609                         return err;
3610
3611                 offset += 2;
3612                 len -= 2;
3613                 eeprom->len += 2;
3614         }
3615
3616         if (len) {
3617                 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
3618                 if (err)
3619                         return err;
3620
3621                 val = (val & 0xff00) | *data++;
3622
3623                 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
3624                 if (err)
3625                         return err;
3626
3627                 offset++;
3628                 len--;
3629                 eeprom->len++;
3630         }
3631
3632         return 0;
3633 }
3634
3635 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
3636                                 struct ethtool_eeprom *eeprom, u8 *data)
3637 {
3638         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3639         int err;
3640
3641         if (eeprom->magic != 0xc3ec4951)
3642                 return -EINVAL;
3643
3644         mutex_lock(&chip->reg_lock);
3645
3646         if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_EEPROM16))
3647                 err = mv88e6xxx_set_eeprom16(chip, eeprom, data);
3648         else
3649                 err = -EOPNOTSUPP;
3650
3651         mutex_unlock(&chip->reg_lock);
3652
3653         return err;
3654 }
3655
3656 static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3657         [MV88E6085] = {
3658                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6085,
3659                 .family = MV88E6XXX_FAMILY_6097,
3660                 .name = "Marvell 88E6085",
3661                 .num_databases = 4096,
3662                 .num_ports = 10,
3663                 .port_base_addr = 0x10,
3664                 .age_time_coeff = 15000,
3665                 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
3666         },
3667
3668         [MV88E6095] = {
3669                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6095,
3670                 .family = MV88E6XXX_FAMILY_6095,
3671                 .name = "Marvell 88E6095/88E6095F",
3672                 .num_databases = 256,
3673                 .num_ports = 11,
3674                 .port_base_addr = 0x10,
3675                 .age_time_coeff = 15000,
3676                 .flags = MV88E6XXX_FLAGS_FAMILY_6095,
3677         },
3678
3679         [MV88E6123] = {
3680                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6123,
3681                 .family = MV88E6XXX_FAMILY_6165,
3682                 .name = "Marvell 88E6123",
3683                 .num_databases = 4096,
3684                 .num_ports = 3,
3685                 .port_base_addr = 0x10,
3686                 .age_time_coeff = 15000,
3687                 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3688         },
3689
3690         [MV88E6131] = {
3691                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6131,
3692                 .family = MV88E6XXX_FAMILY_6185,
3693                 .name = "Marvell 88E6131",
3694                 .num_databases = 256,
3695                 .num_ports = 8,
3696                 .port_base_addr = 0x10,
3697                 .age_time_coeff = 15000,
3698                 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
3699         },
3700
3701         [MV88E6161] = {
3702                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6161,
3703                 .family = MV88E6XXX_FAMILY_6165,
3704                 .name = "Marvell 88E6161",
3705                 .num_databases = 4096,
3706                 .num_ports = 6,
3707                 .port_base_addr = 0x10,
3708                 .age_time_coeff = 15000,
3709                 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3710         },
3711
3712         [MV88E6165] = {
3713                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6165,
3714                 .family = MV88E6XXX_FAMILY_6165,
3715                 .name = "Marvell 88E6165",
3716                 .num_databases = 4096,
3717                 .num_ports = 6,
3718                 .port_base_addr = 0x10,
3719                 .age_time_coeff = 15000,
3720                 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3721         },
3722
3723         [MV88E6171] = {
3724                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6171,
3725                 .family = MV88E6XXX_FAMILY_6351,
3726                 .name = "Marvell 88E6171",
3727                 .num_databases = 4096,
3728                 .num_ports = 7,
3729                 .port_base_addr = 0x10,
3730                 .age_time_coeff = 15000,
3731                 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3732         },
3733
3734         [MV88E6172] = {
3735                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6172,
3736                 .family = MV88E6XXX_FAMILY_6352,
3737                 .name = "Marvell 88E6172",
3738                 .num_databases = 4096,
3739                 .num_ports = 7,
3740                 .port_base_addr = 0x10,
3741                 .age_time_coeff = 15000,
3742                 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3743         },
3744
3745         [MV88E6175] = {
3746                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6175,
3747                 .family = MV88E6XXX_FAMILY_6351,
3748                 .name = "Marvell 88E6175",
3749                 .num_databases = 4096,
3750                 .num_ports = 7,
3751                 .port_base_addr = 0x10,
3752                 .age_time_coeff = 15000,
3753                 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3754         },
3755
3756         [MV88E6176] = {
3757                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6176,
3758                 .family = MV88E6XXX_FAMILY_6352,
3759                 .name = "Marvell 88E6176",
3760                 .num_databases = 4096,
3761                 .num_ports = 7,
3762                 .port_base_addr = 0x10,
3763                 .age_time_coeff = 15000,
3764                 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3765         },
3766
3767         [MV88E6185] = {
3768                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6185,
3769                 .family = MV88E6XXX_FAMILY_6185,
3770                 .name = "Marvell 88E6185",
3771                 .num_databases = 256,
3772                 .num_ports = 10,
3773                 .port_base_addr = 0x10,
3774                 .age_time_coeff = 15000,
3775                 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
3776         },
3777
3778         [MV88E6240] = {
3779                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6240,
3780                 .family = MV88E6XXX_FAMILY_6352,
3781                 .name = "Marvell 88E6240",
3782                 .num_databases = 4096,
3783                 .num_ports = 7,
3784                 .port_base_addr = 0x10,
3785                 .age_time_coeff = 15000,
3786                 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3787         },
3788
3789         [MV88E6320] = {
3790                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6320,
3791                 .family = MV88E6XXX_FAMILY_6320,
3792                 .name = "Marvell 88E6320",
3793                 .num_databases = 4096,
3794                 .num_ports = 7,
3795                 .port_base_addr = 0x10,
3796                 .age_time_coeff = 15000,
3797                 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
3798         },
3799
3800         [MV88E6321] = {
3801                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6321,
3802                 .family = MV88E6XXX_FAMILY_6320,
3803                 .name = "Marvell 88E6321",
3804                 .num_databases = 4096,
3805                 .num_ports = 7,
3806                 .port_base_addr = 0x10,
3807                 .age_time_coeff = 15000,
3808                 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
3809         },
3810
3811         [MV88E6350] = {
3812                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6350,
3813                 .family = MV88E6XXX_FAMILY_6351,
3814                 .name = "Marvell 88E6350",
3815                 .num_databases = 4096,
3816                 .num_ports = 7,
3817                 .port_base_addr = 0x10,
3818                 .age_time_coeff = 15000,
3819                 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3820         },
3821
3822         [MV88E6351] = {
3823                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6351,
3824                 .family = MV88E6XXX_FAMILY_6351,
3825                 .name = "Marvell 88E6351",
3826                 .num_databases = 4096,
3827                 .num_ports = 7,
3828                 .port_base_addr = 0x10,
3829                 .age_time_coeff = 15000,
3830                 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3831         },
3832
3833         [MV88E6352] = {
3834                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6352,
3835                 .family = MV88E6XXX_FAMILY_6352,
3836                 .name = "Marvell 88E6352",
3837                 .num_databases = 4096,
3838                 .num_ports = 7,
3839                 .port_base_addr = 0x10,
3840                 .age_time_coeff = 15000,
3841                 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3842         },
3843 };
3844
3845 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
3846 {
3847         int i;
3848
3849         for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
3850                 if (mv88e6xxx_table[i].prod_num == prod_num)
3851                         return &mv88e6xxx_table[i];
3852
3853         return NULL;
3854 }
3855
3856 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
3857 {
3858         const struct mv88e6xxx_info *info;
3859         unsigned int prod_num, rev;
3860         u16 id;
3861         int err;
3862
3863         mutex_lock(&chip->reg_lock);
3864         err = mv88e6xxx_port_read(chip, 0, PORT_SWITCH_ID, &id);
3865         mutex_unlock(&chip->reg_lock);
3866         if (err)
3867                 return err;
3868
3869         prod_num = (id & 0xfff0) >> 4;
3870         rev = id & 0x000f;
3871
3872         info = mv88e6xxx_lookup_info(prod_num);
3873         if (!info)
3874                 return -ENODEV;
3875
3876         /* Update the compatible info with the probed one */
3877         chip->info = info;
3878
3879         dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
3880                  chip->info->prod_num, chip->info->name, rev);
3881
3882         return 0;
3883 }
3884
3885 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
3886 {
3887         struct mv88e6xxx_chip *chip;
3888
3889         chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
3890         if (!chip)
3891                 return NULL;
3892
3893         chip->dev = dev;
3894
3895         mutex_init(&chip->reg_lock);
3896
3897         return chip;
3898 }
3899
3900 static const struct mv88e6xxx_ops mv88e6xxx_phy_ops = {
3901         .read = mv88e6xxx_read,
3902         .write = mv88e6xxx_write,
3903 };
3904
3905 static void mv88e6xxx_phy_init(struct mv88e6xxx_chip *chip)
3906 {
3907         if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_SMI_PHY)) {
3908                 chip->phy_ops = &mv88e6xxx_g2_smi_phy_ops;
3909         } else if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU)) {
3910                 chip->phy_ops = &mv88e6xxx_phy_ppu_ops;
3911                 mv88e6xxx_ppu_state_init(chip);
3912         } else {
3913                 chip->phy_ops = &mv88e6xxx_phy_ops;
3914         }
3915 }
3916
3917 static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
3918                               struct mii_bus *bus, int sw_addr)
3919 {
3920         /* ADDR[0] pin is unavailable externally and considered zero */
3921         if (sw_addr & 0x1)
3922                 return -EINVAL;
3923
3924         if (sw_addr == 0)
3925                 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
3926         else if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_MULTI_CHIP))
3927                 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
3928         else
3929                 return -EINVAL;
3930
3931         chip->bus = bus;
3932         chip->sw_addr = sw_addr;
3933
3934         return 0;
3935 }
3936
3937 static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
3938                                        struct device *host_dev, int sw_addr,
3939                                        void **priv)
3940 {
3941         struct mv88e6xxx_chip *chip;
3942         struct mii_bus *bus;
3943         int err;
3944
3945         bus = dsa_host_dev_to_mii_bus(host_dev);
3946         if (!bus)
3947                 return NULL;
3948
3949         chip = mv88e6xxx_alloc_chip(dsa_dev);
3950         if (!chip)
3951                 return NULL;
3952
3953         /* Legacy SMI probing will only support chips similar to 88E6085 */
3954         chip->info = &mv88e6xxx_table[MV88E6085];
3955
3956         err = mv88e6xxx_smi_init(chip, bus, sw_addr);
3957         if (err)
3958                 goto free;
3959
3960         err = mv88e6xxx_detect(chip);
3961         if (err)
3962                 goto free;
3963
3964         mv88e6xxx_phy_init(chip);
3965
3966         err = mv88e6xxx_mdio_register(chip, NULL);
3967         if (err)
3968                 goto free;
3969
3970         *priv = chip;
3971
3972         return chip->info->name;
3973 free:
3974         devm_kfree(dsa_dev, chip);
3975
3976         return NULL;
3977 }
3978
3979 static struct dsa_switch_driver mv88e6xxx_switch_driver = {
3980         .tag_protocol           = DSA_TAG_PROTO_EDSA,
3981         .probe                  = mv88e6xxx_drv_probe,
3982         .setup                  = mv88e6xxx_setup,
3983         .set_addr               = mv88e6xxx_set_addr,
3984         .adjust_link            = mv88e6xxx_adjust_link,
3985         .get_strings            = mv88e6xxx_get_strings,
3986         .get_ethtool_stats      = mv88e6xxx_get_ethtool_stats,
3987         .get_sset_count         = mv88e6xxx_get_sset_count,
3988         .set_eee                = mv88e6xxx_set_eee,
3989         .get_eee                = mv88e6xxx_get_eee,
3990 #ifdef CONFIG_NET_DSA_HWMON
3991         .get_temp               = mv88e6xxx_get_temp,
3992         .get_temp_limit         = mv88e6xxx_get_temp_limit,
3993         .set_temp_limit         = mv88e6xxx_set_temp_limit,
3994         .get_temp_alarm         = mv88e6xxx_get_temp_alarm,
3995 #endif
3996         .get_eeprom_len         = mv88e6xxx_get_eeprom_len,
3997         .get_eeprom             = mv88e6xxx_get_eeprom,
3998         .set_eeprom             = mv88e6xxx_set_eeprom,
3999         .get_regs_len           = mv88e6xxx_get_regs_len,
4000         .get_regs               = mv88e6xxx_get_regs,
4001         .set_ageing_time        = mv88e6xxx_set_ageing_time,
4002         .port_bridge_join       = mv88e6xxx_port_bridge_join,
4003         .port_bridge_leave      = mv88e6xxx_port_bridge_leave,
4004         .port_stp_state_set     = mv88e6xxx_port_stp_state_set,
4005         .port_vlan_filtering    = mv88e6xxx_port_vlan_filtering,
4006         .port_vlan_prepare      = mv88e6xxx_port_vlan_prepare,
4007         .port_vlan_add          = mv88e6xxx_port_vlan_add,
4008         .port_vlan_del          = mv88e6xxx_port_vlan_del,
4009         .port_vlan_dump         = mv88e6xxx_port_vlan_dump,
4010         .port_fdb_prepare       = mv88e6xxx_port_fdb_prepare,
4011         .port_fdb_add           = mv88e6xxx_port_fdb_add,
4012         .port_fdb_del           = mv88e6xxx_port_fdb_del,
4013         .port_fdb_dump          = mv88e6xxx_port_fdb_dump,
4014 };
4015
4016 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip,
4017                                      struct device_node *np)
4018 {
4019         struct device *dev = chip->dev;
4020         struct dsa_switch *ds;
4021
4022         ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
4023         if (!ds)
4024                 return -ENOMEM;
4025
4026         ds->dev = dev;
4027         ds->priv = chip;
4028         ds->drv = &mv88e6xxx_switch_driver;
4029
4030         dev_set_drvdata(dev, ds);
4031
4032         return dsa_register_switch(ds, np);
4033 }
4034
4035 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
4036 {
4037         dsa_unregister_switch(chip->ds);
4038 }
4039
4040 static int mv88e6xxx_probe(struct mdio_device *mdiodev)
4041 {
4042         struct device *dev = &mdiodev->dev;
4043         struct device_node *np = dev->of_node;
4044         const struct mv88e6xxx_info *compat_info;
4045         struct mv88e6xxx_chip *chip;
4046         u32 eeprom_len;
4047         int err;
4048
4049         compat_info = of_device_get_match_data(dev);
4050         if (!compat_info)
4051                 return -EINVAL;
4052
4053         chip = mv88e6xxx_alloc_chip(dev);
4054         if (!chip)
4055                 return -ENOMEM;
4056
4057         chip->info = compat_info;
4058
4059         err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
4060         if (err)
4061                 return err;
4062
4063         err = mv88e6xxx_detect(chip);
4064         if (err)
4065                 return err;
4066
4067         mv88e6xxx_phy_init(chip);
4068
4069         chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_ASIS);
4070         if (IS_ERR(chip->reset))
4071                 return PTR_ERR(chip->reset);
4072
4073         if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_EEPROM16) &&
4074             !of_property_read_u32(np, "eeprom-length", &eeprom_len))
4075                 chip->eeprom_len = eeprom_len;
4076
4077         err = mv88e6xxx_mdio_register(chip, np);
4078         if (err)
4079                 return err;
4080
4081         err = mv88e6xxx_register_switch(chip, np);
4082         if (err) {
4083                 mv88e6xxx_mdio_unregister(chip);
4084                 return err;
4085         }
4086
4087         return 0;
4088 }
4089
4090 static void mv88e6xxx_remove(struct mdio_device *mdiodev)
4091 {
4092         struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
4093         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
4094
4095         mv88e6xxx_unregister_switch(chip);
4096         mv88e6xxx_mdio_unregister(chip);
4097 }
4098
4099 static const struct of_device_id mv88e6xxx_of_match[] = {
4100         {
4101                 .compatible = "marvell,mv88e6085",
4102                 .data = &mv88e6xxx_table[MV88E6085],
4103         },
4104         { /* sentinel */ },
4105 };
4106
4107 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
4108
4109 static struct mdio_driver mv88e6xxx_driver = {
4110         .probe  = mv88e6xxx_probe,
4111         .remove = mv88e6xxx_remove,
4112         .mdiodrv.driver = {
4113                 .name = "mv88e6085",
4114                 .of_match_table = mv88e6xxx_of_match,
4115         },
4116 };
4117
4118 static int __init mv88e6xxx_init(void)
4119 {
4120         register_switch_driver(&mv88e6xxx_switch_driver);
4121         return mdio_driver_register(&mv88e6xxx_driver);
4122 }
4123 module_init(mv88e6xxx_init);
4124
4125 static void __exit mv88e6xxx_cleanup(void)
4126 {
4127         mdio_driver_unregister(&mv88e6xxx_driver);
4128         unregister_switch_driver(&mv88e6xxx_switch_driver);
4129 }
4130 module_exit(mv88e6xxx_cleanup);
4131
4132 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
4133 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
4134 MODULE_LICENSE("GPL");