2 * Marvell 88e6xxx common definitions
4 * Copyright (c) 2008 Marvell Semiconductor
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
15 #include <linux/if_vlan.h>
16 #include <linux/gpio/consumer.h>
19 #define UINT64_MAX (u64)(~((u64)0))
23 #define SMI_CMD_BUSY BIT(15)
24 #define SMI_CMD_CLAUSE_22 BIT(12)
25 #define SMI_CMD_OP_22_WRITE ((1 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22)
26 #define SMI_CMD_OP_22_READ ((2 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22)
27 #define SMI_CMD_OP_45_WRITE_ADDR ((0 << 10) | SMI_CMD_BUSY)
28 #define SMI_CMD_OP_45_WRITE_DATA ((1 << 10) | SMI_CMD_BUSY)
29 #define SMI_CMD_OP_45_READ_DATA ((2 << 10) | SMI_CMD_BUSY)
30 #define SMI_CMD_OP_45_READ_DATA_INC ((3 << 10) | SMI_CMD_BUSY)
35 #define PHY_PAGE_COPPER 0x00
37 #define ADDR_SERDES 0x0f
38 #define SERDES_PAGE_FIBER 0x01
40 #define PORT_STATUS 0x00
41 #define PORT_STATUS_PAUSE_EN BIT(15)
42 #define PORT_STATUS_MY_PAUSE BIT(14)
43 #define PORT_STATUS_HD_FLOW BIT(13)
44 #define PORT_STATUS_PHY_DETECT BIT(12)
45 #define PORT_STATUS_LINK BIT(11)
46 #define PORT_STATUS_DUPLEX BIT(10)
47 #define PORT_STATUS_SPEED_MASK 0x0300
48 #define PORT_STATUS_SPEED_10 0x0000
49 #define PORT_STATUS_SPEED_100 0x0100
50 #define PORT_STATUS_SPEED_1000 0x0200
51 #define PORT_STATUS_EEE BIT(6) /* 6352 */
52 #define PORT_STATUS_AM_DIS BIT(6) /* 6165 */
53 #define PORT_STATUS_MGMII BIT(6) /* 6185 */
54 #define PORT_STATUS_TX_PAUSED BIT(5)
55 #define PORT_STATUS_FLOW_CTRL BIT(4)
56 #define PORT_STATUS_CMODE_MASK 0x0f
57 #define PORT_STATUS_CMODE_100BASE_X 0x8
58 #define PORT_STATUS_CMODE_1000BASE_X 0x9
59 #define PORT_STATUS_CMODE_SGMII 0xa
60 #define PORT_PCS_CTRL 0x01
61 #define PORT_PCS_CTRL_RGMII_DELAY_RXCLK BIT(15)
62 #define PORT_PCS_CTRL_RGMII_DELAY_TXCLK BIT(14)
63 #define PORT_PCS_CTRL_FC BIT(7)
64 #define PORT_PCS_CTRL_FORCE_FC BIT(6)
65 #define PORT_PCS_CTRL_LINK_UP BIT(5)
66 #define PORT_PCS_CTRL_FORCE_LINK BIT(4)
67 #define PORT_PCS_CTRL_DUPLEX_FULL BIT(3)
68 #define PORT_PCS_CTRL_FORCE_DUPLEX BIT(2)
69 #define PORT_PCS_CTRL_10 0x00
70 #define PORT_PCS_CTRL_100 0x01
71 #define PORT_PCS_CTRL_1000 0x02
72 #define PORT_PCS_CTRL_UNFORCED 0x03
73 #define PORT_PAUSE_CTRL 0x02
74 #define PORT_SWITCH_ID 0x03
75 #define PORT_SWITCH_ID_PROD_NUM_6085 0x04a
76 #define PORT_SWITCH_ID_PROD_NUM_6095 0x095
77 #define PORT_SWITCH_ID_PROD_NUM_6131 0x106
78 #define PORT_SWITCH_ID_PROD_NUM_6320 0x115
79 #define PORT_SWITCH_ID_PROD_NUM_6123 0x121
80 #define PORT_SWITCH_ID_PROD_NUM_6161 0x161
81 #define PORT_SWITCH_ID_PROD_NUM_6165 0x165
82 #define PORT_SWITCH_ID_PROD_NUM_6171 0x171
83 #define PORT_SWITCH_ID_PROD_NUM_6172 0x172
84 #define PORT_SWITCH_ID_PROD_NUM_6175 0x175
85 #define PORT_SWITCH_ID_PROD_NUM_6176 0x176
86 #define PORT_SWITCH_ID_PROD_NUM_6185 0x1a7
87 #define PORT_SWITCH_ID_PROD_NUM_6240 0x240
88 #define PORT_SWITCH_ID_PROD_NUM_6321 0x310
89 #define PORT_SWITCH_ID_PROD_NUM_6352 0x352
90 #define PORT_SWITCH_ID_PROD_NUM_6350 0x371
91 #define PORT_SWITCH_ID_PROD_NUM_6351 0x375
92 #define PORT_CONTROL 0x04
93 #define PORT_CONTROL_USE_CORE_TAG BIT(15)
94 #define PORT_CONTROL_DROP_ON_LOCK BIT(14)
95 #define PORT_CONTROL_EGRESS_UNMODIFIED (0x0 << 12)
96 #define PORT_CONTROL_EGRESS_UNTAGGED (0x1 << 12)
97 #define PORT_CONTROL_EGRESS_TAGGED (0x2 << 12)
98 #define PORT_CONTROL_EGRESS_ADD_TAG (0x3 << 12)
99 #define PORT_CONTROL_HEADER BIT(11)
100 #define PORT_CONTROL_IGMP_MLD_SNOOP BIT(10)
101 #define PORT_CONTROL_DOUBLE_TAG BIT(9)
102 #define PORT_CONTROL_FRAME_MODE_NORMAL (0x0 << 8)
103 #define PORT_CONTROL_FRAME_MODE_DSA (0x1 << 8)
104 #define PORT_CONTROL_FRAME_MODE_PROVIDER (0x2 << 8)
105 #define PORT_CONTROL_FRAME_ETHER_TYPE_DSA (0x3 << 8)
106 #define PORT_CONTROL_DSA_TAG BIT(8)
107 #define PORT_CONTROL_VLAN_TUNNEL BIT(7)
108 #define PORT_CONTROL_TAG_IF_BOTH BIT(6)
109 #define PORT_CONTROL_USE_IP BIT(5)
110 #define PORT_CONTROL_USE_TAG BIT(4)
111 #define PORT_CONTROL_FORWARD_UNKNOWN_MC BIT(3)
112 #define PORT_CONTROL_FORWARD_UNKNOWN BIT(2)
113 #define PORT_CONTROL_STATE_MASK 0x03
114 #define PORT_CONTROL_STATE_DISABLED 0x00
115 #define PORT_CONTROL_STATE_BLOCKING 0x01
116 #define PORT_CONTROL_STATE_LEARNING 0x02
117 #define PORT_CONTROL_STATE_FORWARDING 0x03
118 #define PORT_CONTROL_1 0x05
119 #define PORT_CONTROL_1_FID_11_4_MASK (0xff << 0)
120 #define PORT_BASE_VLAN 0x06
121 #define PORT_BASE_VLAN_FID_3_0_MASK (0xf << 12)
122 #define PORT_DEFAULT_VLAN 0x07
123 #define PORT_DEFAULT_VLAN_MASK 0xfff
124 #define PORT_CONTROL_2 0x08
125 #define PORT_CONTROL_2_IGNORE_FCS BIT(15)
126 #define PORT_CONTROL_2_VTU_PRI_OVERRIDE BIT(14)
127 #define PORT_CONTROL_2_SA_PRIO_OVERRIDE BIT(13)
128 #define PORT_CONTROL_2_DA_PRIO_OVERRIDE BIT(12)
129 #define PORT_CONTROL_2_JUMBO_1522 (0x00 << 12)
130 #define PORT_CONTROL_2_JUMBO_2048 (0x01 << 12)
131 #define PORT_CONTROL_2_JUMBO_10240 (0x02 << 12)
132 #define PORT_CONTROL_2_8021Q_MASK (0x03 << 10)
133 #define PORT_CONTROL_2_8021Q_DISABLED (0x00 << 10)
134 #define PORT_CONTROL_2_8021Q_FALLBACK (0x01 << 10)
135 #define PORT_CONTROL_2_8021Q_CHECK (0x02 << 10)
136 #define PORT_CONTROL_2_8021Q_SECURE (0x03 << 10)
137 #define PORT_CONTROL_2_DISCARD_TAGGED BIT(9)
138 #define PORT_CONTROL_2_DISCARD_UNTAGGED BIT(8)
139 #define PORT_CONTROL_2_MAP_DA BIT(7)
140 #define PORT_CONTROL_2_DEFAULT_FORWARD BIT(6)
141 #define PORT_CONTROL_2_FORWARD_UNKNOWN BIT(6)
142 #define PORT_CONTROL_2_EGRESS_MONITOR BIT(5)
143 #define PORT_CONTROL_2_INGRESS_MONITOR BIT(4)
144 #define PORT_RATE_CONTROL 0x09
145 #define PORT_RATE_CONTROL_2 0x0a
146 #define PORT_ASSOC_VECTOR 0x0b
147 #define PORT_ASSOC_VECTOR_HOLD_AT_1 BIT(15)
148 #define PORT_ASSOC_VECTOR_INT_AGE_OUT BIT(14)
149 #define PORT_ASSOC_VECTOR_LOCKED_PORT BIT(13)
150 #define PORT_ASSOC_VECTOR_IGNORE_WRONG BIT(12)
151 #define PORT_ASSOC_VECTOR_REFRESH_LOCKED BIT(11)
152 #define PORT_ATU_CONTROL 0x0c
153 #define PORT_PRI_OVERRIDE 0x0d
154 #define PORT_ETH_TYPE 0x0f
155 #define PORT_IN_DISCARD_LO 0x10
156 #define PORT_IN_DISCARD_HI 0x11
157 #define PORT_IN_FILTERED 0x12
158 #define PORT_OUT_FILTERED 0x13
159 #define PORT_TAG_REGMAP_0123 0x18
160 #define PORT_TAG_REGMAP_4567 0x19
162 #define REG_GLOBAL 0x1b
163 #define GLOBAL_STATUS 0x00
164 #define GLOBAL_STATUS_PPU_STATE BIT(15) /* 6351 and 6171 */
165 /* Two bits for 6165, 6185 etc */
166 #define GLOBAL_STATUS_PPU_MASK (0x3 << 14)
167 #define GLOBAL_STATUS_PPU_DISABLED_RST (0x0 << 14)
168 #define GLOBAL_STATUS_PPU_INITIALIZING (0x1 << 14)
169 #define GLOBAL_STATUS_PPU_DISABLED (0x2 << 14)
170 #define GLOBAL_STATUS_PPU_POLLING (0x3 << 14)
171 #define GLOBAL_MAC_01 0x01
172 #define GLOBAL_MAC_23 0x02
173 #define GLOBAL_MAC_45 0x03
174 #define GLOBAL_ATU_FID 0x01 /* 6097 6165 6351 6352 */
175 #define GLOBAL_VTU_FID 0x02 /* 6097 6165 6351 6352 */
176 #define GLOBAL_VTU_FID_MASK 0xfff
177 #define GLOBAL_VTU_SID 0x03 /* 6097 6165 6351 6352 */
178 #define GLOBAL_VTU_SID_MASK 0x3f
179 #define GLOBAL_CONTROL 0x04
180 #define GLOBAL_CONTROL_SW_RESET BIT(15)
181 #define GLOBAL_CONTROL_PPU_ENABLE BIT(14)
182 #define GLOBAL_CONTROL_DISCARD_EXCESS BIT(13) /* 6352 */
183 #define GLOBAL_CONTROL_SCHED_PRIO BIT(11) /* 6152 */
184 #define GLOBAL_CONTROL_MAX_FRAME_1632 BIT(10) /* 6152 */
185 #define GLOBAL_CONTROL_RELOAD_EEPROM BIT(9) /* 6152 */
186 #define GLOBAL_CONTROL_DEVICE_EN BIT(7)
187 #define GLOBAL_CONTROL_STATS_DONE_EN BIT(6)
188 #define GLOBAL_CONTROL_VTU_PROBLEM_EN BIT(5)
189 #define GLOBAL_CONTROL_VTU_DONE_EN BIT(4)
190 #define GLOBAL_CONTROL_ATU_PROBLEM_EN BIT(3)
191 #define GLOBAL_CONTROL_ATU_DONE_EN BIT(2)
192 #define GLOBAL_CONTROL_TCAM_EN BIT(1)
193 #define GLOBAL_CONTROL_EEPROM_DONE_EN BIT(0)
194 #define GLOBAL_VTU_OP 0x05
195 #define GLOBAL_VTU_OP_BUSY BIT(15)
196 #define GLOBAL_VTU_OP_FLUSH_ALL ((0x01 << 12) | GLOBAL_VTU_OP_BUSY)
197 #define GLOBAL_VTU_OP_VTU_LOAD_PURGE ((0x03 << 12) | GLOBAL_VTU_OP_BUSY)
198 #define GLOBAL_VTU_OP_VTU_GET_NEXT ((0x04 << 12) | GLOBAL_VTU_OP_BUSY)
199 #define GLOBAL_VTU_OP_STU_LOAD_PURGE ((0x05 << 12) | GLOBAL_VTU_OP_BUSY)
200 #define GLOBAL_VTU_OP_STU_GET_NEXT ((0x06 << 12) | GLOBAL_VTU_OP_BUSY)
201 #define GLOBAL_VTU_VID 0x06
202 #define GLOBAL_VTU_VID_MASK 0xfff
203 #define GLOBAL_VTU_VID_VALID BIT(12)
204 #define GLOBAL_VTU_DATA_0_3 0x07
205 #define GLOBAL_VTU_DATA_4_7 0x08
206 #define GLOBAL_VTU_DATA_8_11 0x09
207 #define GLOBAL_VTU_STU_DATA_MASK 0x03
208 #define GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED 0x00
209 #define GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED 0x01
210 #define GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED 0x02
211 #define GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER 0x03
212 #define GLOBAL_STU_DATA_PORT_STATE_DISABLED 0x00
213 #define GLOBAL_STU_DATA_PORT_STATE_BLOCKING 0x01
214 #define GLOBAL_STU_DATA_PORT_STATE_LEARNING 0x02
215 #define GLOBAL_STU_DATA_PORT_STATE_FORWARDING 0x03
216 #define GLOBAL_ATU_CONTROL 0x0a
217 #define GLOBAL_ATU_CONTROL_LEARN2ALL BIT(3)
218 #define GLOBAL_ATU_OP 0x0b
219 #define GLOBAL_ATU_OP_BUSY BIT(15)
220 #define GLOBAL_ATU_OP_NOP (0 << 12)
221 #define GLOBAL_ATU_OP_FLUSH_MOVE_ALL ((1 << 12) | GLOBAL_ATU_OP_BUSY)
222 #define GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC ((2 << 12) | GLOBAL_ATU_OP_BUSY)
223 #define GLOBAL_ATU_OP_LOAD_DB ((3 << 12) | GLOBAL_ATU_OP_BUSY)
224 #define GLOBAL_ATU_OP_GET_NEXT_DB ((4 << 12) | GLOBAL_ATU_OP_BUSY)
225 #define GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB ((5 << 12) | GLOBAL_ATU_OP_BUSY)
226 #define GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB ((6 << 12) | GLOBAL_ATU_OP_BUSY)
227 #define GLOBAL_ATU_OP_GET_CLR_VIOLATION ((7 << 12) | GLOBAL_ATU_OP_BUSY)
228 #define GLOBAL_ATU_DATA 0x0c
229 #define GLOBAL_ATU_DATA_TRUNK BIT(15)
230 #define GLOBAL_ATU_DATA_TRUNK_ID_MASK 0x00f0
231 #define GLOBAL_ATU_DATA_TRUNK_ID_SHIFT 4
232 #define GLOBAL_ATU_DATA_PORT_VECTOR_MASK 0x3ff0
233 #define GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT 4
234 #define GLOBAL_ATU_DATA_STATE_MASK 0x0f
235 #define GLOBAL_ATU_DATA_STATE_UNUSED 0x00
236 #define GLOBAL_ATU_DATA_STATE_UC_MGMT 0x0d
237 #define GLOBAL_ATU_DATA_STATE_UC_STATIC 0x0e
238 #define GLOBAL_ATU_DATA_STATE_UC_PRIO_OVER 0x0f
239 #define GLOBAL_ATU_DATA_STATE_MC_NONE_RATE 0x05
240 #define GLOBAL_ATU_DATA_STATE_MC_STATIC 0x07
241 #define GLOBAL_ATU_DATA_STATE_MC_MGMT 0x0e
242 #define GLOBAL_ATU_DATA_STATE_MC_PRIO_OVER 0x0f
243 #define GLOBAL_ATU_MAC_01 0x0d
244 #define GLOBAL_ATU_MAC_23 0x0e
245 #define GLOBAL_ATU_MAC_45 0x0f
246 #define GLOBAL_IP_PRI_0 0x10
247 #define GLOBAL_IP_PRI_1 0x11
248 #define GLOBAL_IP_PRI_2 0x12
249 #define GLOBAL_IP_PRI_3 0x13
250 #define GLOBAL_IP_PRI_4 0x14
251 #define GLOBAL_IP_PRI_5 0x15
252 #define GLOBAL_IP_PRI_6 0x16
253 #define GLOBAL_IP_PRI_7 0x17
254 #define GLOBAL_IEEE_PRI 0x18
255 #define GLOBAL_CORE_TAG_TYPE 0x19
256 #define GLOBAL_MONITOR_CONTROL 0x1a
257 #define GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT 12
258 #define GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT 8
259 #define GLOBAL_MONITOR_CONTROL_ARP_SHIFT 4
260 #define GLOBAL_MONITOR_CONTROL_MIRROR_SHIFT 0
261 #define GLOBAL_MONITOR_CONTROL_ARP_DISABLED (0xf0)
262 #define GLOBAL_CONTROL_2 0x1c
263 #define GLOBAL_CONTROL_2_NO_CASCADE 0xe000
264 #define GLOBAL_CONTROL_2_MULTIPLE_CASCADE 0xf000
266 #define GLOBAL_STATS_OP 0x1d
267 #define GLOBAL_STATS_OP_BUSY BIT(15)
268 #define GLOBAL_STATS_OP_NOP (0 << 12)
269 #define GLOBAL_STATS_OP_FLUSH_ALL ((1 << 12) | GLOBAL_STATS_OP_BUSY)
270 #define GLOBAL_STATS_OP_FLUSH_PORT ((2 << 12) | GLOBAL_STATS_OP_BUSY)
271 #define GLOBAL_STATS_OP_READ_CAPTURED ((4 << 12) | GLOBAL_STATS_OP_BUSY)
272 #define GLOBAL_STATS_OP_CAPTURE_PORT ((5 << 12) | GLOBAL_STATS_OP_BUSY)
273 #define GLOBAL_STATS_OP_HIST_RX ((1 << 10) | GLOBAL_STATS_OP_BUSY)
274 #define GLOBAL_STATS_OP_HIST_TX ((2 << 10) | GLOBAL_STATS_OP_BUSY)
275 #define GLOBAL_STATS_OP_HIST_RX_TX ((3 << 10) | GLOBAL_STATS_OP_BUSY)
276 #define GLOBAL_STATS_OP_BANK_1 BIT(9)
277 #define GLOBAL_STATS_COUNTER_32 0x1e
278 #define GLOBAL_STATS_COUNTER_01 0x1f
280 #define REG_GLOBAL2 0x1c
281 #define GLOBAL2_INT_SOURCE 0x00
282 #define GLOBAL2_INT_MASK 0x01
283 #define GLOBAL2_MGMT_EN_2X 0x02
284 #define GLOBAL2_MGMT_EN_0X 0x03
285 #define GLOBAL2_FLOW_CONTROL 0x04
286 #define GLOBAL2_SWITCH_MGMT 0x05
287 #define GLOBAL2_SWITCH_MGMT_USE_DOUBLE_TAG_DATA BIT(15)
288 #define GLOBAL2_SWITCH_MGMT_PREVENT_LOOPS BIT(14)
289 #define GLOBAL2_SWITCH_MGMT_FLOW_CONTROL_MSG BIT(13)
290 #define GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI BIT(7)
291 #define GLOBAL2_SWITCH_MGMT_RSVD2CPU BIT(3)
292 #define GLOBAL2_DEVICE_MAPPING 0x06
293 #define GLOBAL2_DEVICE_MAPPING_UPDATE BIT(15)
294 #define GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT 8
295 #define GLOBAL2_DEVICE_MAPPING_PORT_MASK 0x0f
296 #define GLOBAL2_TRUNK_MASK 0x07
297 #define GLOBAL2_TRUNK_MASK_UPDATE BIT(15)
298 #define GLOBAL2_TRUNK_MASK_NUM_SHIFT 12
299 #define GLOBAL2_TRUNK_MASK_HASK BIT(11)
300 #define GLOBAL2_TRUNK_MAPPING 0x08
301 #define GLOBAL2_TRUNK_MAPPING_UPDATE BIT(15)
302 #define GLOBAL2_TRUNK_MAPPING_ID_SHIFT 11
303 #define GLOBAL2_IRL_CMD 0x09
304 #define GLOBAL2_IRL_CMD_BUSY BIT(15)
305 #define GLOBAL2_IRL_CMD_OP_INIT_ALL ((0x001 << 12) | GLOBAL2_IRL_CMD_BUSY)
306 #define GLOBAL2_IRL_CMD_OP_INIT_SEL ((0x010 << 12) | GLOBAL2_IRL_CMD_BUSY)
307 #define GLOBAL2_IRL_CMD_OP_WRITE_SEL ((0x011 << 12) | GLOBAL2_IRL_CMD_BUSY)
308 #define GLOBAL2_IRL_CMD_OP_READ_SEL ((0x100 << 12) | GLOBAL2_IRL_CMD_BUSY)
309 #define GLOBAL2_IRL_DATA 0x0a
310 #define GLOBAL2_PVT_ADDR 0x0b
311 #define GLOBAL2_PVT_ADDR_BUSY BIT(15)
312 #define GLOBAL2_PVT_ADDR_OP_INIT_ONES ((0x01 << 12) | GLOBAL2_PVT_ADDR_BUSY)
313 #define GLOBAL2_PVT_ADDR_OP_WRITE_PVLAN ((0x03 << 12) | GLOBAL2_PVT_ADDR_BUSY)
314 #define GLOBAL2_PVT_ADDR_OP_READ ((0x04 << 12) | GLOBAL2_PVT_ADDR_BUSY)
315 #define GLOBAL2_PVT_DATA 0x0c
316 #define GLOBAL2_SWITCH_MAC 0x0d
317 #define GLOBAL2_ATU_STATS 0x0e
318 #define GLOBAL2_PRIO_OVERRIDE 0x0f
319 #define GLOBAL2_PRIO_OVERRIDE_FORCE_SNOOP BIT(7)
320 #define GLOBAL2_PRIO_OVERRIDE_SNOOP_SHIFT 4
321 #define GLOBAL2_PRIO_OVERRIDE_FORCE_ARP BIT(3)
322 #define GLOBAL2_PRIO_OVERRIDE_ARP_SHIFT 0
323 #define GLOBAL2_EEPROM_CMD 0x14
324 #define GLOBAL2_EEPROM_CMD_BUSY BIT(15)
325 #define GLOBAL2_EEPROM_CMD_OP_WRITE ((0x3 << 12) | GLOBAL2_EEPROM_CMD_BUSY)
326 #define GLOBAL2_EEPROM_CMD_OP_READ ((0x4 << 12) | GLOBAL2_EEPROM_CMD_BUSY)
327 #define GLOBAL2_EEPROM_CMD_OP_LOAD ((0x6 << 12) | GLOBAL2_EEPROM_CMD_BUSY)
328 #define GLOBAL2_EEPROM_CMD_RUNNING BIT(11)
329 #define GLOBAL2_EEPROM_CMD_WRITE_EN BIT(10)
330 #define GLOBAL2_EEPROM_CMD_ADDR_MASK 0xff
331 #define GLOBAL2_EEPROM_DATA 0x15
332 #define GLOBAL2_PTP_AVB_OP 0x16
333 #define GLOBAL2_PTP_AVB_DATA 0x17
334 #define GLOBAL2_SMI_PHY_CMD 0x18
335 #define GLOBAL2_SMI_PHY_CMD_BUSY BIT(15)
336 #define GLOBAL2_SMI_PHY_CMD_MODE_22 BIT(12)
337 #define GLOBAL2_SMI_PHY_CMD_OP_22_WRITE_DATA ((0x1 << 10) | \
338 GLOBAL2_SMI_PHY_CMD_MODE_22 | \
339 GLOBAL2_SMI_PHY_CMD_BUSY)
340 #define GLOBAL2_SMI_PHY_CMD_OP_22_READ_DATA ((0x2 << 10) | \
341 GLOBAL2_SMI_PHY_CMD_MODE_22 | \
342 GLOBAL2_SMI_PHY_CMD_BUSY)
343 #define GLOBAL2_SMI_PHY_DATA 0x19
344 #define GLOBAL2_SCRATCH_MISC 0x1a
345 #define GLOBAL2_SCRATCH_BUSY BIT(15)
346 #define GLOBAL2_SCRATCH_REGISTER_SHIFT 8
347 #define GLOBAL2_SCRATCH_VALUE_MASK 0xff
348 #define GLOBAL2_WDOG_CONTROL 0x1b
349 #define GLOBAL2_QOS_WEIGHT 0x1c
350 #define GLOBAL2_MISC 0x1d
352 #define MV88E6XXX_N_FID 4096
354 /* List of supported models */
355 enum mv88e6xxx_model {
375 enum mv88e6xxx_family {
376 MV88E6XXX_FAMILY_NONE,
377 MV88E6XXX_FAMILY_6065, /* 6031 6035 6061 6065 */
378 MV88E6XXX_FAMILY_6095, /* 6092 6095 */
379 MV88E6XXX_FAMILY_6097, /* 6046 6085 6096 6097 */
380 MV88E6XXX_FAMILY_6165, /* 6123 6161 6165 */
381 MV88E6XXX_FAMILY_6185, /* 6108 6121 6122 6131 6152 6155 6182 6185 */
382 MV88E6XXX_FAMILY_6320, /* 6320 6321 */
383 MV88E6XXX_FAMILY_6351, /* 6171 6175 6350 6351 */
384 MV88E6XXX_FAMILY_6352, /* 6172 6176 6240 6352 */
388 /* Two different tag protocols can be used by the driver. All
389 * switches support DSA, but only later generations support
394 /* Energy Efficient Ethernet.
398 /* Multi-chip Addressing Mode.
399 * Some chips respond to only 2 registers of its own SMI device address
400 * when it is non-zero, and use indirect access to internal registers.
402 MV88E6XXX_CAP_SMI_CMD, /* (0x00) SMI Command */
403 MV88E6XXX_CAP_SMI_DATA, /* (0x01) SMI Data */
407 MV88E6XXX_CAP_PHY_PAGE, /* (0x16) Page Register */
409 /* Fiber/SERDES Registers (SMI address F).
411 MV88E6XXX_CAP_SERDES,
413 /* Switch Global 2 Registers.
414 * The device contains a second set of global 16-bit registers.
416 MV88E6XXX_CAP_GLOBAL2,
417 MV88E6XXX_CAP_G2_MGMT_EN_2X, /* (0x02) MGMT Enable Register 2x */
418 MV88E6XXX_CAP_G2_MGMT_EN_0X, /* (0x03) MGMT Enable Register 0x */
419 MV88E6XXX_CAP_G2_IRL_CMD, /* (0x09) Ingress Rate Command */
420 MV88E6XXX_CAP_G2_IRL_DATA, /* (0x0a) Ingress Rate Data */
421 MV88E6XXX_CAP_G2_PVT_ADDR, /* (0x0b) Cross Chip Port VLAN Addr */
422 MV88E6XXX_CAP_G2_PVT_DATA, /* (0x0c) Cross Chip Port VLAN Data */
423 MV88E6XXX_CAP_G2_SWITCH_MAC, /* (0x0d) Switch MAC/WoL/WoF */
424 MV88E6XXX_CAP_G2_POT, /* (0x0f) Priority Override Table */
425 MV88E6XXX_CAP_G2_EEPROM_CMD, /* (0x14) EEPROM Command */
426 MV88E6XXX_CAP_G2_EEPROM_DATA, /* (0x15) EEPROM Data */
427 MV88E6XXX_CAP_G2_SMI_PHY_CMD, /* (0x18) SMI PHY Command */
428 MV88E6XXX_CAP_G2_SMI_PHY_DATA, /* (0x19) SMI PHY Data */
431 * See GLOBAL_CONTROL_PPU_ENABLE and GLOBAL_STATUS_PPU_POLLING.
434 MV88E6XXX_CAP_PPU_ACTIVE,
436 /* Per VLAN Spanning Tree Unit (STU).
437 * The Port State database, if present, is accessed through VTU
438 * operations and dedicated SID registers. See GLOBAL_VTU_SID.
442 /* Internal temperature sensor.
443 * Available from any enabled port's PHY register 26, page 6.
446 MV88E6XXX_CAP_TEMP_LIMIT,
449 * The VTU is used to program 802.1Q VLANs. See GLOBAL_VTU_OP.
454 /* Bitmask of capabilities */
455 #define MV88E6XXX_FLAG_EDSA BIT_ULL(MV88E6XXX_CAP_EDSA)
456 #define MV88E6XXX_FLAG_EEE BIT_ULL(MV88E6XXX_CAP_EEE)
458 #define MV88E6XXX_FLAG_SMI_CMD BIT_ULL(MV88E6XXX_CAP_SMI_CMD)
459 #define MV88E6XXX_FLAG_SMI_DATA BIT_ULL(MV88E6XXX_CAP_SMI_DATA)
461 #define MV88E6XXX_FLAG_PHY_PAGE BIT_ULL(MV88E6XXX_CAP_PHY_PAGE)
463 #define MV88E6XXX_FLAG_SERDES BIT_ULL(MV88E6XXX_CAP_SERDES)
465 #define MV88E6XXX_FLAG_GLOBAL2 BIT_ULL(MV88E6XXX_CAP_GLOBAL2)
466 #define MV88E6XXX_FLAG_G2_MGMT_EN_2X BIT_ULL(MV88E6XXX_CAP_G2_MGMT_EN_2X)
467 #define MV88E6XXX_FLAG_G2_MGMT_EN_0X BIT_ULL(MV88E6XXX_CAP_G2_MGMT_EN_0X)
468 #define MV88E6XXX_FLAG_G2_IRL_CMD BIT_ULL(MV88E6XXX_CAP_G2_IRL_CMD)
469 #define MV88E6XXX_FLAG_G2_IRL_DATA BIT_ULL(MV88E6XXX_CAP_G2_IRL_DATA)
470 #define MV88E6XXX_FLAG_G2_PVT_ADDR BIT_ULL(MV88E6XXX_CAP_G2_PVT_ADDR)
471 #define MV88E6XXX_FLAG_G2_PVT_DATA BIT_ULL(MV88E6XXX_CAP_G2_PVT_DATA)
472 #define MV88E6XXX_FLAG_G2_SWITCH_MAC BIT_ULL(MV88E6XXX_CAP_G2_SWITCH_MAC)
473 #define MV88E6XXX_FLAG_G2_POT BIT_ULL(MV88E6XXX_CAP_G2_POT)
474 #define MV88E6XXX_FLAG_G2_EEPROM_CMD BIT_ULL(MV88E6XXX_CAP_G2_EEPROM_CMD)
475 #define MV88E6XXX_FLAG_G2_EEPROM_DATA BIT_ULL(MV88E6XXX_CAP_G2_EEPROM_DATA)
476 #define MV88E6XXX_FLAG_G2_SMI_PHY_CMD BIT_ULL(MV88E6XXX_CAP_G2_SMI_PHY_CMD)
477 #define MV88E6XXX_FLAG_G2_SMI_PHY_DATA BIT_ULL(MV88E6XXX_CAP_G2_SMI_PHY_DATA)
479 #define MV88E6XXX_FLAG_PPU BIT_ULL(MV88E6XXX_CAP_PPU)
480 #define MV88E6XXX_FLAG_PPU_ACTIVE BIT_ULL(MV88E6XXX_CAP_PPU_ACTIVE)
481 #define MV88E6XXX_FLAG_STU BIT_ULL(MV88E6XXX_CAP_STU)
482 #define MV88E6XXX_FLAG_TEMP BIT_ULL(MV88E6XXX_CAP_TEMP)
483 #define MV88E6XXX_FLAG_TEMP_LIMIT BIT_ULL(MV88E6XXX_CAP_TEMP_LIMIT)
484 #define MV88E6XXX_FLAG_VTU BIT_ULL(MV88E6XXX_CAP_VTU)
486 /* EEPROM Programming via Global2 with 16-bit data */
487 #define MV88E6XXX_FLAGS_EEPROM16 \
488 (MV88E6XXX_FLAG_G2_EEPROM_CMD | \
489 MV88E6XXX_FLAG_G2_EEPROM_DATA)
491 /* Ingress Rate Limit unit */
492 #define MV88E6XXX_FLAGS_IRL \
493 (MV88E6XXX_FLAG_G2_IRL_CMD | \
494 MV88E6XXX_FLAG_G2_IRL_DATA)
496 /* Multi-chip Addressing Mode */
497 #define MV88E6XXX_FLAGS_MULTI_CHIP \
498 (MV88E6XXX_FLAG_SMI_CMD | \
499 MV88E6XXX_FLAG_SMI_DATA)
501 /* Cross-chip Port VLAN Table */
502 #define MV88E6XXX_FLAGS_PVT \
503 (MV88E6XXX_FLAG_G2_PVT_ADDR | \
504 MV88E6XXX_FLAG_G2_PVT_DATA)
506 /* Fiber/SERDES Registers at SMI address F, page 1 */
507 #define MV88E6XXX_FLAGS_SERDES \
508 (MV88E6XXX_FLAG_PHY_PAGE | \
509 MV88E6XXX_FLAG_SERDES)
511 /* Indirect PHY access via Global2 SMI PHY registers */
512 #define MV88E6XXX_FLAGS_SMI_PHY \
513 (MV88E6XXX_FLAG_G2_SMI_PHY_CMD |\
514 MV88E6XXX_FLAG_G2_SMI_PHY_DATA)
516 #define MV88E6XXX_FLAGS_FAMILY_6095 \
517 (MV88E6XXX_FLAG_GLOBAL2 | \
518 MV88E6XXX_FLAG_G2_MGMT_EN_0X | \
519 MV88E6XXX_FLAG_PPU | \
520 MV88E6XXX_FLAG_VTU | \
521 MV88E6XXX_FLAGS_MULTI_CHIP)
523 #define MV88E6XXX_FLAGS_FAMILY_6097 \
524 (MV88E6XXX_FLAG_GLOBAL2 | \
525 MV88E6XXX_FLAG_G2_MGMT_EN_2X | \
526 MV88E6XXX_FLAG_G2_MGMT_EN_0X | \
527 MV88E6XXX_FLAG_G2_POT | \
528 MV88E6XXX_FLAG_PPU | \
529 MV88E6XXX_FLAG_STU | \
530 MV88E6XXX_FLAG_VTU | \
531 MV88E6XXX_FLAGS_IRL | \
532 MV88E6XXX_FLAGS_MULTI_CHIP | \
535 #define MV88E6XXX_FLAGS_FAMILY_6165 \
536 (MV88E6XXX_FLAG_GLOBAL2 | \
537 MV88E6XXX_FLAG_G2_MGMT_EN_2X | \
538 MV88E6XXX_FLAG_G2_MGMT_EN_0X | \
539 MV88E6XXX_FLAG_G2_SWITCH_MAC | \
540 MV88E6XXX_FLAG_G2_POT | \
541 MV88E6XXX_FLAG_STU | \
542 MV88E6XXX_FLAG_TEMP | \
543 MV88E6XXX_FLAG_VTU | \
544 MV88E6XXX_FLAGS_IRL | \
545 MV88E6XXX_FLAGS_MULTI_CHIP | \
548 #define MV88E6XXX_FLAGS_FAMILY_6185 \
549 (MV88E6XXX_FLAG_GLOBAL2 | \
550 MV88E6XXX_FLAG_G2_MGMT_EN_0X | \
551 MV88E6XXX_FLAGS_MULTI_CHIP | \
552 MV88E6XXX_FLAG_PPU | \
555 #define MV88E6XXX_FLAGS_FAMILY_6320 \
556 (MV88E6XXX_FLAG_EDSA | \
557 MV88E6XXX_FLAG_EEE | \
558 MV88E6XXX_FLAG_GLOBAL2 | \
559 MV88E6XXX_FLAG_G2_MGMT_EN_2X | \
560 MV88E6XXX_FLAG_G2_MGMT_EN_0X | \
561 MV88E6XXX_FLAG_G2_SWITCH_MAC | \
562 MV88E6XXX_FLAG_G2_POT | \
563 MV88E6XXX_FLAG_PPU_ACTIVE | \
564 MV88E6XXX_FLAG_TEMP | \
565 MV88E6XXX_FLAG_TEMP_LIMIT | \
566 MV88E6XXX_FLAG_VTU | \
567 MV88E6XXX_FLAGS_EEPROM16 | \
568 MV88E6XXX_FLAGS_IRL | \
569 MV88E6XXX_FLAGS_MULTI_CHIP | \
570 MV88E6XXX_FLAGS_PVT | \
571 MV88E6XXX_FLAGS_SMI_PHY)
573 #define MV88E6XXX_FLAGS_FAMILY_6351 \
574 (MV88E6XXX_FLAG_EDSA | \
575 MV88E6XXX_FLAG_GLOBAL2 | \
576 MV88E6XXX_FLAG_G2_MGMT_EN_2X | \
577 MV88E6XXX_FLAG_G2_MGMT_EN_0X | \
578 MV88E6XXX_FLAG_G2_SWITCH_MAC | \
579 MV88E6XXX_FLAG_G2_POT | \
580 MV88E6XXX_FLAG_PPU_ACTIVE | \
581 MV88E6XXX_FLAG_STU | \
582 MV88E6XXX_FLAG_TEMP | \
583 MV88E6XXX_FLAG_VTU | \
584 MV88E6XXX_FLAGS_IRL | \
585 MV88E6XXX_FLAGS_MULTI_CHIP | \
586 MV88E6XXX_FLAGS_PVT | \
587 MV88E6XXX_FLAGS_SMI_PHY)
589 #define MV88E6XXX_FLAGS_FAMILY_6352 \
590 (MV88E6XXX_FLAG_EDSA | \
591 MV88E6XXX_FLAG_EEE | \
592 MV88E6XXX_FLAG_GLOBAL2 | \
593 MV88E6XXX_FLAG_G2_MGMT_EN_2X | \
594 MV88E6XXX_FLAG_G2_MGMT_EN_0X | \
595 MV88E6XXX_FLAG_G2_SWITCH_MAC | \
596 MV88E6XXX_FLAG_G2_POT | \
597 MV88E6XXX_FLAG_PPU_ACTIVE | \
598 MV88E6XXX_FLAG_STU | \
599 MV88E6XXX_FLAG_TEMP | \
600 MV88E6XXX_FLAG_TEMP_LIMIT | \
601 MV88E6XXX_FLAG_VTU | \
602 MV88E6XXX_FLAGS_EEPROM16 | \
603 MV88E6XXX_FLAGS_IRL | \
604 MV88E6XXX_FLAGS_MULTI_CHIP | \
605 MV88E6XXX_FLAGS_PVT | \
606 MV88E6XXX_FLAGS_SERDES | \
607 MV88E6XXX_FLAGS_SMI_PHY)
609 struct mv88e6xxx_info {
610 enum mv88e6xxx_family family;
613 unsigned int num_databases;
614 unsigned int num_ports;
615 unsigned int port_base_addr;
616 unsigned int age_time_coeff;
617 unsigned long long flags;
620 struct mv88e6xxx_atu_entry {
628 struct mv88e6xxx_vtu_stu_entry {
636 u8 data[DSA_MAX_PORTS];
639 struct mv88e6xxx_ops;
641 struct mv88e6xxx_priv_port {
642 struct net_device *bridge_dev;
645 struct mv88e6xxx_chip {
646 const struct mv88e6xxx_info *info;
648 /* The dsa_switch this private structure is related to */
649 struct dsa_switch *ds;
651 /* The device this structure is associated to */
654 /* This mutex protects the access to the switch registers */
655 struct mutex reg_lock;
657 /* The MII bus and the address on the bus that is used to
658 * communication with the switch
660 const struct mv88e6xxx_ops *smi_ops;
664 /* Handles automatic disabling and re-enabling of the PHY
667 const struct mv88e6xxx_ops *phy_ops;
668 struct mutex ppu_mutex;
670 struct work_struct ppu_work;
671 struct timer_list ppu_timer;
673 /* This mutex serialises access to the statistics unit.
674 * Hold this mutex over snapshot + dump sequences.
676 struct mutex stats_mutex;
678 struct mv88e6xxx_priv_port ports[DSA_MAX_PORTS];
680 /* A switch may have a GPIO line tied to its reset pin. Parse
681 * this from the device tree, and use it before performing
684 struct gpio_desc *reset;
686 /* set to size of eeprom if supported by the switch */
689 /* Device node for the MDIO bus */
690 struct device_node *mdio_np;
692 /* And the MDIO bus itself */
693 struct mii_bus *mdio_bus;
696 struct mv88e6xxx_ops {
697 int (*read)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val);
698 int (*write)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val);
707 struct mv88e6xxx_hw_stat {
708 char string[ETH_GSTRING_LEN];
714 static inline bool mv88e6xxx_has(struct mv88e6xxx_chip *chip,
717 return (chip->info->flags & flags) == flags;
720 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val);
721 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val);
722 int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg,
724 int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask);