2 * net/dsa/mv88e6xxx.c - Marvell 88e6xxx switch chip support
3 * Copyright (c) 2008 Marvell Semiconductor
5 * Copyright (c) 2015 CMC Electronics, Inc.
6 * Added support for VLAN Table Unit operations
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/delay.h>
15 #include <linux/etherdevice.h>
16 #include <linux/ethtool.h>
17 #include <linux/if_bridge.h>
18 #include <linux/jiffies.h>
19 #include <linux/list.h>
20 #include <linux/module.h>
21 #include <linux/netdevice.h>
22 #include <linux/phy.h>
24 #include <net/switchdev.h>
25 #include "mv88e6xxx.h"
27 /* MDIO bus access can be nested in the case of PHYs connected to the
28 * internal MDIO bus of the switch, which is accessed via MDIO bus of
29 * the Ethernet interface. Avoid lockdep false positives by using
30 * mutex_lock_nested().
32 static int mv88e6xxx_mdiobus_read(struct mii_bus *bus, int addr, u32 regnum)
36 mutex_lock_nested(&bus->mdio_lock, SINGLE_DEPTH_NESTING);
37 ret = bus->read(bus, addr, regnum);
38 mutex_unlock(&bus->mdio_lock);
43 static int mv88e6xxx_mdiobus_write(struct mii_bus *bus, int addr, u32 regnum,
48 mutex_lock_nested(&bus->mdio_lock, SINGLE_DEPTH_NESTING);
49 ret = bus->write(bus, addr, regnum, val);
50 mutex_unlock(&bus->mdio_lock);
55 /* If the switch's ADDR[4:0] strap pins are strapped to zero, it will
56 * use all 32 SMI bus addresses on its SMI bus, and all switch registers
57 * will be directly accessible on some {device address,register address}
58 * pair. If the ADDR[4:0] pins are not strapped to zero, the switch
59 * will only respond to SMI transactions to that specific address, and
60 * an indirect addressing mechanism needs to be used to access its
63 static int mv88e6xxx_reg_wait_ready(struct mii_bus *bus, int sw_addr)
68 for (i = 0; i < 16; i++) {
69 ret = mv88e6xxx_mdiobus_read(bus, sw_addr, SMI_CMD);
73 if ((ret & SMI_CMD_BUSY) == 0)
80 int __mv88e6xxx_reg_read(struct mii_bus *bus, int sw_addr, int addr, int reg)
85 return mv88e6xxx_mdiobus_read(bus, addr, reg);
87 /* Wait for the bus to become free. */
88 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
92 /* Transmit the read command. */
93 ret = mv88e6xxx_mdiobus_write(bus, sw_addr, SMI_CMD,
94 SMI_CMD_OP_22_READ | (addr << 5) | reg);
98 /* Wait for the read command to complete. */
99 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
104 ret = mv88e6xxx_mdiobus_read(bus, sw_addr, SMI_DATA);
111 /* Must be called with SMI mutex held */
112 static int _mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
114 struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
120 ret = __mv88e6xxx_reg_read(bus, ds->pd->sw_addr, addr, reg);
124 dev_dbg(ds->master_dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
130 int mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
132 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
135 mutex_lock(&ps->smi_mutex);
136 ret = _mv88e6xxx_reg_read(ds, addr, reg);
137 mutex_unlock(&ps->smi_mutex);
142 int __mv88e6xxx_reg_write(struct mii_bus *bus, int sw_addr, int addr,
148 return mv88e6xxx_mdiobus_write(bus, addr, reg, val);
150 /* Wait for the bus to become free. */
151 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
155 /* Transmit the data to write. */
156 ret = mv88e6xxx_mdiobus_write(bus, sw_addr, SMI_DATA, val);
160 /* Transmit the write command. */
161 ret = mv88e6xxx_mdiobus_write(bus, sw_addr, SMI_CMD,
162 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
166 /* Wait for the write command to complete. */
167 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
174 /* Must be called with SMI mutex held */
175 static int _mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg,
178 struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
183 dev_dbg(ds->master_dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
186 return __mv88e6xxx_reg_write(bus, ds->pd->sw_addr, addr, reg, val);
189 int mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
191 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
194 mutex_lock(&ps->smi_mutex);
195 ret = _mv88e6xxx_reg_write(ds, addr, reg, val);
196 mutex_unlock(&ps->smi_mutex);
201 int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr)
203 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]);
204 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
205 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
210 int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr)
215 for (i = 0; i < 6; i++) {
218 /* Write the MAC address byte. */
219 REG_WRITE(REG_GLOBAL2, GLOBAL2_SWITCH_MAC,
220 GLOBAL2_SWITCH_MAC_BUSY | (i << 8) | addr[i]);
222 /* Wait for the write to complete. */
223 for (j = 0; j < 16; j++) {
224 ret = REG_READ(REG_GLOBAL2, GLOBAL2_SWITCH_MAC);
225 if ((ret & GLOBAL2_SWITCH_MAC_BUSY) == 0)
235 /* Must be called with SMI mutex held */
236 static int _mv88e6xxx_phy_read(struct dsa_switch *ds, int addr, int regnum)
239 return _mv88e6xxx_reg_read(ds, addr, regnum);
243 /* Must be called with SMI mutex held */
244 static int _mv88e6xxx_phy_write(struct dsa_switch *ds, int addr, int regnum,
248 return _mv88e6xxx_reg_write(ds, addr, regnum, val);
252 #ifdef CONFIG_NET_DSA_MV88E6XXX_NEED_PPU
253 static int mv88e6xxx_ppu_disable(struct dsa_switch *ds)
256 unsigned long timeout;
258 ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL);
259 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL,
260 ret & ~GLOBAL_CONTROL_PPU_ENABLE);
262 timeout = jiffies + 1 * HZ;
263 while (time_before(jiffies, timeout)) {
264 ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS);
265 usleep_range(1000, 2000);
266 if ((ret & GLOBAL_STATUS_PPU_MASK) !=
267 GLOBAL_STATUS_PPU_POLLING)
274 static int mv88e6xxx_ppu_enable(struct dsa_switch *ds)
277 unsigned long timeout;
279 ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL);
280 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, ret | GLOBAL_CONTROL_PPU_ENABLE);
282 timeout = jiffies + 1 * HZ;
283 while (time_before(jiffies, timeout)) {
284 ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS);
285 usleep_range(1000, 2000);
286 if ((ret & GLOBAL_STATUS_PPU_MASK) ==
287 GLOBAL_STATUS_PPU_POLLING)
294 static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
296 struct mv88e6xxx_priv_state *ps;
298 ps = container_of(ugly, struct mv88e6xxx_priv_state, ppu_work);
299 if (mutex_trylock(&ps->ppu_mutex)) {
300 struct dsa_switch *ds = ((struct dsa_switch *)ps) - 1;
302 if (mv88e6xxx_ppu_enable(ds) == 0)
303 ps->ppu_disabled = 0;
304 mutex_unlock(&ps->ppu_mutex);
308 static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
310 struct mv88e6xxx_priv_state *ps = (void *)_ps;
312 schedule_work(&ps->ppu_work);
315 static int mv88e6xxx_ppu_access_get(struct dsa_switch *ds)
317 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
320 mutex_lock(&ps->ppu_mutex);
322 /* If the PHY polling unit is enabled, disable it so that
323 * we can access the PHY registers. If it was already
324 * disabled, cancel the timer that is going to re-enable
327 if (!ps->ppu_disabled) {
328 ret = mv88e6xxx_ppu_disable(ds);
330 mutex_unlock(&ps->ppu_mutex);
333 ps->ppu_disabled = 1;
335 del_timer(&ps->ppu_timer);
342 static void mv88e6xxx_ppu_access_put(struct dsa_switch *ds)
344 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
346 /* Schedule a timer to re-enable the PHY polling unit. */
347 mod_timer(&ps->ppu_timer, jiffies + msecs_to_jiffies(10));
348 mutex_unlock(&ps->ppu_mutex);
351 void mv88e6xxx_ppu_state_init(struct dsa_switch *ds)
353 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
355 mutex_init(&ps->ppu_mutex);
356 INIT_WORK(&ps->ppu_work, mv88e6xxx_ppu_reenable_work);
357 init_timer(&ps->ppu_timer);
358 ps->ppu_timer.data = (unsigned long)ps;
359 ps->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
362 int mv88e6xxx_phy_read_ppu(struct dsa_switch *ds, int addr, int regnum)
366 ret = mv88e6xxx_ppu_access_get(ds);
368 ret = mv88e6xxx_reg_read(ds, addr, regnum);
369 mv88e6xxx_ppu_access_put(ds);
375 int mv88e6xxx_phy_write_ppu(struct dsa_switch *ds, int addr,
380 ret = mv88e6xxx_ppu_access_get(ds);
382 ret = mv88e6xxx_reg_write(ds, addr, regnum, val);
383 mv88e6xxx_ppu_access_put(ds);
390 static bool mv88e6xxx_6065_family(struct dsa_switch *ds)
392 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
395 case PORT_SWITCH_ID_6031:
396 case PORT_SWITCH_ID_6061:
397 case PORT_SWITCH_ID_6035:
398 case PORT_SWITCH_ID_6065:
404 static bool mv88e6xxx_6095_family(struct dsa_switch *ds)
406 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
409 case PORT_SWITCH_ID_6092:
410 case PORT_SWITCH_ID_6095:
416 static bool mv88e6xxx_6097_family(struct dsa_switch *ds)
418 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
421 case PORT_SWITCH_ID_6046:
422 case PORT_SWITCH_ID_6085:
423 case PORT_SWITCH_ID_6096:
424 case PORT_SWITCH_ID_6097:
430 static bool mv88e6xxx_6165_family(struct dsa_switch *ds)
432 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
435 case PORT_SWITCH_ID_6123:
436 case PORT_SWITCH_ID_6161:
437 case PORT_SWITCH_ID_6165:
443 static bool mv88e6xxx_6185_family(struct dsa_switch *ds)
445 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
448 case PORT_SWITCH_ID_6121:
449 case PORT_SWITCH_ID_6122:
450 case PORT_SWITCH_ID_6152:
451 case PORT_SWITCH_ID_6155:
452 case PORT_SWITCH_ID_6182:
453 case PORT_SWITCH_ID_6185:
454 case PORT_SWITCH_ID_6108:
455 case PORT_SWITCH_ID_6131:
461 static bool mv88e6xxx_6320_family(struct dsa_switch *ds)
463 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
466 case PORT_SWITCH_ID_6320:
467 case PORT_SWITCH_ID_6321:
473 static bool mv88e6xxx_6351_family(struct dsa_switch *ds)
475 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
478 case PORT_SWITCH_ID_6171:
479 case PORT_SWITCH_ID_6175:
480 case PORT_SWITCH_ID_6350:
481 case PORT_SWITCH_ID_6351:
487 static bool mv88e6xxx_6352_family(struct dsa_switch *ds)
489 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
492 case PORT_SWITCH_ID_6172:
493 case PORT_SWITCH_ID_6176:
494 case PORT_SWITCH_ID_6240:
495 case PORT_SWITCH_ID_6352:
501 /* We expect the switch to perform auto negotiation if there is a real
502 * phy. However, in the case of a fixed link phy, we force the port
503 * settings from the fixed link settings.
505 void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
506 struct phy_device *phydev)
508 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
512 if (!phy_is_pseudo_fixed_link(phydev))
515 mutex_lock(&ps->smi_mutex);
517 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_PCS_CTRL);
521 reg = ret & ~(PORT_PCS_CTRL_LINK_UP |
522 PORT_PCS_CTRL_FORCE_LINK |
523 PORT_PCS_CTRL_DUPLEX_FULL |
524 PORT_PCS_CTRL_FORCE_DUPLEX |
525 PORT_PCS_CTRL_UNFORCED);
527 reg |= PORT_PCS_CTRL_FORCE_LINK;
529 reg |= PORT_PCS_CTRL_LINK_UP;
531 if (mv88e6xxx_6065_family(ds) && phydev->speed > SPEED_100)
534 switch (phydev->speed) {
536 reg |= PORT_PCS_CTRL_1000;
539 reg |= PORT_PCS_CTRL_100;
542 reg |= PORT_PCS_CTRL_10;
545 pr_info("Unknown speed");
549 reg |= PORT_PCS_CTRL_FORCE_DUPLEX;
550 if (phydev->duplex == DUPLEX_FULL)
551 reg |= PORT_PCS_CTRL_DUPLEX_FULL;
553 if ((mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds)) &&
554 (port >= ps->num_ports - 2)) {
555 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
556 reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK;
557 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
558 reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
559 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
560 reg |= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
561 PORT_PCS_CTRL_RGMII_DELAY_TXCLK);
563 _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_PCS_CTRL, reg);
566 mutex_unlock(&ps->smi_mutex);
569 /* Must be called with SMI mutex held */
570 static int _mv88e6xxx_stats_wait(struct dsa_switch *ds)
575 for (i = 0; i < 10; i++) {
576 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_OP);
577 if ((ret & GLOBAL_STATS_OP_BUSY) == 0)
584 /* Must be called with SMI mutex held */
585 static int _mv88e6xxx_stats_snapshot(struct dsa_switch *ds, int port)
589 if (mv88e6xxx_6320_family(ds) || mv88e6xxx_6352_family(ds))
590 port = (port + 1) << 5;
592 /* Snapshot the hardware statistics counters for this port. */
593 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_STATS_OP,
594 GLOBAL_STATS_OP_CAPTURE_PORT |
595 GLOBAL_STATS_OP_HIST_RX_TX | port);
599 /* Wait for the snapshotting to complete. */
600 ret = _mv88e6xxx_stats_wait(ds);
607 /* Must be called with SMI mutex held */
608 static void _mv88e6xxx_stats_read(struct dsa_switch *ds, int stat, u32 *val)
615 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_STATS_OP,
616 GLOBAL_STATS_OP_READ_CAPTURED |
617 GLOBAL_STATS_OP_HIST_RX_TX | stat);
621 ret = _mv88e6xxx_stats_wait(ds);
625 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_32);
631 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_01);
638 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
639 { "in_good_octets", 8, 0x00, },
640 { "in_bad_octets", 4, 0x02, },
641 { "in_unicast", 4, 0x04, },
642 { "in_broadcasts", 4, 0x06, },
643 { "in_multicasts", 4, 0x07, },
644 { "in_pause", 4, 0x16, },
645 { "in_undersize", 4, 0x18, },
646 { "in_fragments", 4, 0x19, },
647 { "in_oversize", 4, 0x1a, },
648 { "in_jabber", 4, 0x1b, },
649 { "in_rx_error", 4, 0x1c, },
650 { "in_fcs_error", 4, 0x1d, },
651 { "out_octets", 8, 0x0e, },
652 { "out_unicast", 4, 0x10, },
653 { "out_broadcasts", 4, 0x13, },
654 { "out_multicasts", 4, 0x12, },
655 { "out_pause", 4, 0x15, },
656 { "excessive", 4, 0x11, },
657 { "collisions", 4, 0x1e, },
658 { "deferred", 4, 0x05, },
659 { "single", 4, 0x14, },
660 { "multiple", 4, 0x17, },
661 { "out_fcs_error", 4, 0x03, },
662 { "late", 4, 0x1f, },
663 { "hist_64bytes", 4, 0x08, },
664 { "hist_65_127bytes", 4, 0x09, },
665 { "hist_128_255bytes", 4, 0x0a, },
666 { "hist_256_511bytes", 4, 0x0b, },
667 { "hist_512_1023bytes", 4, 0x0c, },
668 { "hist_1024_max_bytes", 4, 0x0d, },
669 /* Not all devices have the following counters */
670 { "sw_in_discards", 4, 0x110, },
671 { "sw_in_filtered", 2, 0x112, },
672 { "sw_out_filtered", 2, 0x113, },
676 static bool have_sw_in_discards(struct dsa_switch *ds)
678 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
681 case PORT_SWITCH_ID_6095: case PORT_SWITCH_ID_6161:
682 case PORT_SWITCH_ID_6165: case PORT_SWITCH_ID_6171:
683 case PORT_SWITCH_ID_6172: case PORT_SWITCH_ID_6176:
684 case PORT_SWITCH_ID_6182: case PORT_SWITCH_ID_6185:
685 case PORT_SWITCH_ID_6352:
692 static void _mv88e6xxx_get_strings(struct dsa_switch *ds,
694 struct mv88e6xxx_hw_stat *stats,
695 int port, uint8_t *data)
699 for (i = 0; i < nr_stats; i++) {
700 memcpy(data + i * ETH_GSTRING_LEN,
701 stats[i].string, ETH_GSTRING_LEN);
705 static uint64_t _mv88e6xxx_get_ethtool_stat(struct dsa_switch *ds,
707 struct mv88e6xxx_hw_stat *stats,
710 struct mv88e6xxx_hw_stat *s = stats + stat;
716 if (s->reg >= 0x100) {
717 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port),
723 if (s->sizeof_stat == 4) {
724 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port),
731 _mv88e6xxx_stats_read(ds, s->reg, &low);
732 if (s->sizeof_stat == 8)
733 _mv88e6xxx_stats_read(ds, s->reg + 1, &high);
735 value = (((u64)high) << 16) | low;
739 static void _mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds,
741 struct mv88e6xxx_hw_stat *stats,
742 int port, uint64_t *data)
744 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
748 mutex_lock(&ps->smi_mutex);
750 ret = _mv88e6xxx_stats_snapshot(ds, port);
752 mutex_unlock(&ps->smi_mutex);
756 /* Read each of the counters. */
757 for (i = 0; i < nr_stats; i++)
758 data[i] = _mv88e6xxx_get_ethtool_stat(ds, i, stats, port);
760 mutex_unlock(&ps->smi_mutex);
763 /* All the statistics in the table */
765 mv88e6xxx_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
767 if (have_sw_in_discards(ds))
768 _mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6xxx_hw_stats),
769 mv88e6xxx_hw_stats, port, data);
771 _mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6xxx_hw_stats) - 3,
772 mv88e6xxx_hw_stats, port, data);
775 int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
777 if (have_sw_in_discards(ds))
778 return ARRAY_SIZE(mv88e6xxx_hw_stats);
779 return ARRAY_SIZE(mv88e6xxx_hw_stats) - 3;
783 mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds,
784 int port, uint64_t *data)
786 if (have_sw_in_discards(ds))
787 _mv88e6xxx_get_ethtool_stats(
788 ds, ARRAY_SIZE(mv88e6xxx_hw_stats),
789 mv88e6xxx_hw_stats, port, data);
791 _mv88e6xxx_get_ethtool_stats(
792 ds, ARRAY_SIZE(mv88e6xxx_hw_stats) - 3,
793 mv88e6xxx_hw_stats, port, data);
796 int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
798 return 32 * sizeof(u16);
801 void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
802 struct ethtool_regs *regs, void *_p)
809 memset(p, 0xff, 32 * sizeof(u16));
811 for (i = 0; i < 32; i++) {
814 ret = mv88e6xxx_reg_read(ds, REG_PORT(port), i);
820 /* Must be called with SMI lock held */
821 static int _mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset,
824 unsigned long timeout = jiffies + HZ / 10;
826 while (time_before(jiffies, timeout)) {
829 ret = _mv88e6xxx_reg_read(ds, reg, offset);
835 usleep_range(1000, 2000);
840 static int mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset, u16 mask)
842 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
845 mutex_lock(&ps->smi_mutex);
846 ret = _mv88e6xxx_wait(ds, reg, offset, mask);
847 mutex_unlock(&ps->smi_mutex);
852 static int _mv88e6xxx_phy_wait(struct dsa_switch *ds)
854 return _mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
855 GLOBAL2_SMI_OP_BUSY);
858 int mv88e6xxx_eeprom_load_wait(struct dsa_switch *ds)
860 return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
861 GLOBAL2_EEPROM_OP_LOAD);
864 int mv88e6xxx_eeprom_busy_wait(struct dsa_switch *ds)
866 return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
867 GLOBAL2_EEPROM_OP_BUSY);
870 /* Must be called with SMI lock held */
871 static int _mv88e6xxx_atu_wait(struct dsa_switch *ds)
873 return _mv88e6xxx_wait(ds, REG_GLOBAL, GLOBAL_ATU_OP,
877 /* Must be called with SMI mutex held */
878 static int _mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int addr,
883 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
884 GLOBAL2_SMI_OP_22_READ | (addr << 5) |
889 ret = _mv88e6xxx_phy_wait(ds);
893 return _mv88e6xxx_reg_read(ds, REG_GLOBAL2, GLOBAL2_SMI_DATA);
896 /* Must be called with SMI mutex held */
897 static int _mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int addr,
902 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_DATA, val);
906 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
907 GLOBAL2_SMI_OP_22_WRITE | (addr << 5) |
910 return _mv88e6xxx_phy_wait(ds);
913 int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
915 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
918 mutex_lock(&ps->smi_mutex);
920 reg = _mv88e6xxx_phy_read_indirect(ds, port, 16);
924 e->eee_enabled = !!(reg & 0x0200);
925 e->tx_lpi_enabled = !!(reg & 0x0100);
927 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_STATUS);
931 e->eee_active = !!(reg & PORT_STATUS_EEE);
935 mutex_unlock(&ps->smi_mutex);
939 int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
940 struct phy_device *phydev, struct ethtool_eee *e)
942 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
946 mutex_lock(&ps->smi_mutex);
948 ret = _mv88e6xxx_phy_read_indirect(ds, port, 16);
955 if (e->tx_lpi_enabled)
958 ret = _mv88e6xxx_phy_write_indirect(ds, port, 16, reg);
960 mutex_unlock(&ps->smi_mutex);
965 static int _mv88e6xxx_atu_cmd(struct dsa_switch *ds, u16 cmd)
969 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_OP, cmd);
973 return _mv88e6xxx_atu_wait(ds);
976 static int _mv88e6xxx_atu_data_write(struct dsa_switch *ds,
977 struct mv88e6xxx_atu_entry *entry)
979 u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK;
981 if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
982 unsigned int mask, shift;
985 data |= GLOBAL_ATU_DATA_TRUNK;
986 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
987 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
989 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
990 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
993 data |= (entry->portv_trunkid << shift) & mask;
996 return _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_DATA, data);
999 static int _mv88e6xxx_atu_flush_move(struct dsa_switch *ds,
1000 struct mv88e6xxx_atu_entry *entry,
1006 err = _mv88e6xxx_atu_wait(ds);
1010 err = _mv88e6xxx_atu_data_write(ds, entry);
1015 err = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_FID,
1020 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB :
1021 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
1023 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL :
1024 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC;
1027 return _mv88e6xxx_atu_cmd(ds, op);
1030 static int _mv88e6xxx_atu_flush(struct dsa_switch *ds, u16 fid, bool static_too)
1032 struct mv88e6xxx_atu_entry entry = {
1034 .state = 0, /* EntryState bits must be 0 */
1037 return _mv88e6xxx_atu_flush_move(ds, &entry, static_too);
1040 static int _mv88e6xxx_atu_move(struct dsa_switch *ds, u16 fid, int from_port,
1041 int to_port, bool static_too)
1043 struct mv88e6xxx_atu_entry entry = {
1048 /* EntryState bits must be 0xF */
1049 entry.state = GLOBAL_ATU_DATA_STATE_MASK;
1051 /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
1052 entry.portv_trunkid = (to_port & 0x0f) << 4;
1053 entry.portv_trunkid |= from_port & 0x0f;
1055 return _mv88e6xxx_atu_flush_move(ds, &entry, static_too);
1058 static int _mv88e6xxx_atu_remove(struct dsa_switch *ds, u16 fid, int port,
1061 /* Destination port 0xF means remove the entries */
1062 return _mv88e6xxx_atu_move(ds, fid, port, 0x0f, static_too);
1065 static int mv88e6xxx_set_port_state(struct dsa_switch *ds, int port, u8 state)
1067 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1071 mutex_lock(&ps->smi_mutex);
1073 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_CONTROL);
1079 oldstate = reg & PORT_CONTROL_STATE_MASK;
1080 if (oldstate != state) {
1081 /* Flush forwarding database if we're moving a port
1082 * from Learning or Forwarding state to Disabled or
1083 * Blocking or Listening state.
1085 if (oldstate >= PORT_CONTROL_STATE_LEARNING &&
1086 state <= PORT_CONTROL_STATE_BLOCKING) {
1087 ret = _mv88e6xxx_atu_remove(ds, 0, port, false);
1091 reg = (reg & ~PORT_CONTROL_STATE_MASK) | state;
1092 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL,
1097 mutex_unlock(&ps->smi_mutex);
1101 static int _mv88e6xxx_port_vlan_map_set(struct dsa_switch *ds, int port,
1104 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1105 const u16 mask = (1 << ps->num_ports) - 1;
1108 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_BASE_VLAN);
1113 reg |= output_ports & mask;
1115 return _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_BASE_VLAN, reg);
1118 int mv88e6xxx_port_stp_update(struct dsa_switch *ds, int port, u8 state)
1120 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1124 case BR_STATE_DISABLED:
1125 stp_state = PORT_CONTROL_STATE_DISABLED;
1127 case BR_STATE_BLOCKING:
1128 case BR_STATE_LISTENING:
1129 stp_state = PORT_CONTROL_STATE_BLOCKING;
1131 case BR_STATE_LEARNING:
1132 stp_state = PORT_CONTROL_STATE_LEARNING;
1134 case BR_STATE_FORWARDING:
1136 stp_state = PORT_CONTROL_STATE_FORWARDING;
1140 netdev_dbg(ds->ports[port], "port state %d [%d]\n", state, stp_state);
1142 /* mv88e6xxx_port_stp_update may be called with softirqs disabled,
1143 * so we can not update the port state directly but need to schedule it.
1145 ps->port_state[port] = stp_state;
1146 set_bit(port, &ps->port_state_update_mask);
1147 schedule_work(&ps->bridge_work);
1152 int mv88e6xxx_port_pvid_get(struct dsa_switch *ds, int port, u16 *pvid)
1156 ret = mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_DEFAULT_VLAN);
1160 *pvid = ret & PORT_DEFAULT_VLAN_MASK;
1165 int mv88e6xxx_port_pvid_set(struct dsa_switch *ds, int port, u16 pvid)
1167 return mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_DEFAULT_VLAN,
1168 pvid & PORT_DEFAULT_VLAN_MASK);
1171 static int _mv88e6xxx_vtu_wait(struct dsa_switch *ds)
1173 return _mv88e6xxx_wait(ds, REG_GLOBAL, GLOBAL_VTU_OP,
1174 GLOBAL_VTU_OP_BUSY);
1177 static int _mv88e6xxx_vtu_cmd(struct dsa_switch *ds, u16 op)
1181 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_OP, op);
1185 return _mv88e6xxx_vtu_wait(ds);
1188 static int _mv88e6xxx_vtu_stu_flush(struct dsa_switch *ds)
1192 ret = _mv88e6xxx_vtu_wait(ds);
1196 return _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_FLUSH_ALL);
1199 static int _mv88e6xxx_vtu_stu_data_read(struct dsa_switch *ds,
1200 struct mv88e6xxx_vtu_stu_entry *entry,
1201 unsigned int nibble_offset)
1203 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1208 for (i = 0; i < 3; ++i) {
1209 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1210 GLOBAL_VTU_DATA_0_3 + i);
1217 for (i = 0; i < ps->num_ports; ++i) {
1218 unsigned int shift = (i % 4) * 4 + nibble_offset;
1219 u16 reg = regs[i / 4];
1221 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1227 static int _mv88e6xxx_vtu_stu_data_write(struct dsa_switch *ds,
1228 struct mv88e6xxx_vtu_stu_entry *entry,
1229 unsigned int nibble_offset)
1231 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1232 u16 regs[3] = { 0 };
1236 for (i = 0; i < ps->num_ports; ++i) {
1237 unsigned int shift = (i % 4) * 4 + nibble_offset;
1238 u8 data = entry->data[i];
1240 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1243 for (i = 0; i < 3; ++i) {
1244 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL,
1245 GLOBAL_VTU_DATA_0_3 + i, regs[i]);
1253 static int _mv88e6xxx_vtu_vid_write(struct dsa_switch *ds, u16 vid)
1255 return _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_VID,
1256 vid & GLOBAL_VTU_VID_MASK);
1259 static int _mv88e6xxx_vtu_getnext(struct dsa_switch *ds,
1260 struct mv88e6xxx_vtu_stu_entry *entry)
1262 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1265 ret = _mv88e6xxx_vtu_wait(ds);
1269 ret = _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_VTU_GET_NEXT);
1273 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_VTU_VID);
1277 next.vid = ret & GLOBAL_VTU_VID_MASK;
1278 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1281 ret = _mv88e6xxx_vtu_stu_data_read(ds, &next, 0);
1285 if (mv88e6xxx_6097_family(ds) || mv88e6xxx_6165_family(ds) ||
1286 mv88e6xxx_6351_family(ds) || mv88e6xxx_6352_family(ds)) {
1287 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1292 next.fid = ret & GLOBAL_VTU_FID_MASK;
1294 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1299 next.sid = ret & GLOBAL_VTU_SID_MASK;
1307 static int _mv88e6xxx_vtu_loadpurge(struct dsa_switch *ds,
1308 struct mv88e6xxx_vtu_stu_entry *entry)
1313 ret = _mv88e6xxx_vtu_wait(ds);
1320 /* Write port member tags */
1321 ret = _mv88e6xxx_vtu_stu_data_write(ds, entry, 0);
1325 if (mv88e6xxx_6097_family(ds) || mv88e6xxx_6165_family(ds) ||
1326 mv88e6xxx_6351_family(ds) || mv88e6xxx_6352_family(ds)) {
1327 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1328 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_SID, reg);
1332 reg = entry->fid & GLOBAL_VTU_FID_MASK;
1333 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_FID, reg);
1338 reg = GLOBAL_VTU_VID_VALID;
1340 reg |= entry->vid & GLOBAL_VTU_VID_MASK;
1341 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1345 return _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_VTU_LOAD_PURGE);
1348 static int _mv88e6xxx_stu_getnext(struct dsa_switch *ds, u8 sid,
1349 struct mv88e6xxx_vtu_stu_entry *entry)
1351 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1354 ret = _mv88e6xxx_vtu_wait(ds);
1358 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_SID,
1359 sid & GLOBAL_VTU_SID_MASK);
1363 ret = _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_STU_GET_NEXT);
1367 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_VTU_SID);
1371 next.sid = ret & GLOBAL_VTU_SID_MASK;
1373 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_VTU_VID);
1377 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1380 ret = _mv88e6xxx_vtu_stu_data_read(ds, &next, 2);
1389 static int _mv88e6xxx_stu_loadpurge(struct dsa_switch *ds,
1390 struct mv88e6xxx_vtu_stu_entry *entry)
1395 ret = _mv88e6xxx_vtu_wait(ds);
1402 /* Write port states */
1403 ret = _mv88e6xxx_vtu_stu_data_write(ds, entry, 2);
1407 reg = GLOBAL_VTU_VID_VALID;
1409 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1413 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1414 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_SID, reg);
1418 return _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_STU_LOAD_PURGE);
1421 static int _mv88e6xxx_vlan_init(struct dsa_switch *ds, u16 vid,
1422 struct mv88e6xxx_vtu_stu_entry *entry)
1424 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1425 struct mv88e6xxx_vtu_stu_entry vlan = {
1428 .fid = vid, /* We use one FID per VLAN */
1432 /* exclude all ports except the CPU */
1433 for (i = 0; i < ps->num_ports; ++i)
1434 vlan.data[i] = dsa_is_cpu_port(ds, i) ?
1435 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED :
1436 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1438 if (mv88e6xxx_6097_family(ds) || mv88e6xxx_6165_family(ds) ||
1439 mv88e6xxx_6351_family(ds) || mv88e6xxx_6352_family(ds)) {
1440 struct mv88e6xxx_vtu_stu_entry vstp;
1443 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1444 * implemented, only one STU entry is needed to cover all VTU
1445 * entries. Thus, validate the SID 0.
1448 err = _mv88e6xxx_stu_getnext(ds, GLOBAL_VTU_SID_MASK, &vstp);
1452 if (vstp.sid != vlan.sid || !vstp.valid) {
1453 memset(&vstp, 0, sizeof(vstp));
1455 vstp.sid = vlan.sid;
1457 err = _mv88e6xxx_stu_loadpurge(ds, &vstp);
1462 /* Clear all MAC addresses from the new database */
1463 err = _mv88e6xxx_atu_flush(ds, vlan.fid, true);
1472 int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, u16 vid,
1475 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1476 struct mv88e6xxx_vtu_stu_entry vlan;
1479 mutex_lock(&ps->smi_mutex);
1481 err = _mv88e6xxx_vtu_vid_write(ds, vid - 1);
1485 err = _mv88e6xxx_vtu_getnext(ds, &vlan);
1489 if (vlan.vid != vid || !vlan.valid) {
1490 err = _mv88e6xxx_vlan_init(ds, vid, &vlan);
1495 vlan.data[port] = untagged ?
1496 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
1497 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
1499 err = _mv88e6xxx_vtu_loadpurge(ds, &vlan);
1501 mutex_unlock(&ps->smi_mutex);
1506 int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, u16 vid)
1508 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1509 struct mv88e6xxx_vtu_stu_entry vlan;
1512 mutex_lock(&ps->smi_mutex);
1514 err = _mv88e6xxx_vtu_vid_write(ds, vid - 1);
1518 err = _mv88e6xxx_vtu_getnext(ds, &vlan);
1522 if (vlan.vid != vid || !vlan.valid ||
1523 vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
1528 vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1530 /* keep the VLAN unless all ports are excluded */
1532 for (i = 0; i < ps->num_ports; ++i) {
1533 if (dsa_is_cpu_port(ds, i))
1536 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
1542 err = _mv88e6xxx_vtu_loadpurge(ds, &vlan);
1546 err = _mv88e6xxx_atu_remove(ds, vlan.fid, port, false);
1548 mutex_unlock(&ps->smi_mutex);
1553 int mv88e6xxx_vlan_getnext(struct dsa_switch *ds, u16 *vid,
1554 unsigned long *ports, unsigned long *untagged)
1556 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1557 struct mv88e6xxx_vtu_stu_entry next;
1564 mutex_lock(&ps->smi_mutex);
1565 err = _mv88e6xxx_vtu_vid_write(ds, *vid);
1569 err = _mv88e6xxx_vtu_getnext(ds, &next);
1571 mutex_unlock(&ps->smi_mutex);
1581 for (port = 0; port < ps->num_ports; ++port) {
1582 clear_bit(port, ports);
1583 clear_bit(port, untagged);
1585 if (dsa_is_cpu_port(ds, port))
1588 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED ||
1589 next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1590 set_bit(port, ports);
1592 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1593 set_bit(port, untagged);
1599 static int _mv88e6xxx_atu_mac_write(struct dsa_switch *ds,
1600 const unsigned char *addr)
1604 for (i = 0; i < 3; i++) {
1605 ret = _mv88e6xxx_reg_write(
1606 ds, REG_GLOBAL, GLOBAL_ATU_MAC_01 + i,
1607 (addr[i * 2] << 8) | addr[i * 2 + 1]);
1615 static int _mv88e6xxx_atu_mac_read(struct dsa_switch *ds, unsigned char *addr)
1619 for (i = 0; i < 3; i++) {
1620 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1621 GLOBAL_ATU_MAC_01 + i);
1624 addr[i * 2] = ret >> 8;
1625 addr[i * 2 + 1] = ret & 0xff;
1631 static int _mv88e6xxx_atu_load(struct dsa_switch *ds,
1632 struct mv88e6xxx_atu_entry *entry)
1636 ret = _mv88e6xxx_atu_wait(ds);
1640 ret = _mv88e6xxx_atu_mac_write(ds, entry->mac);
1644 ret = _mv88e6xxx_atu_data_write(ds, entry);
1648 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_FID, entry->fid);
1652 return _mv88e6xxx_atu_cmd(ds, GLOBAL_ATU_OP_LOAD_DB);
1655 static int _mv88e6xxx_port_fdb_load(struct dsa_switch *ds, int port,
1656 const unsigned char *addr, u16 vid,
1659 struct mv88e6xxx_atu_entry entry = { 0 };
1661 entry.fid = vid; /* We use one FID per VLAN */
1662 entry.state = state;
1663 ether_addr_copy(entry.mac, addr);
1664 if (state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1665 entry.trunk = false;
1666 entry.portv_trunkid = BIT(port);
1669 return _mv88e6xxx_atu_load(ds, &entry);
1672 int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
1673 const struct switchdev_obj_port_fdb *fdb,
1674 struct switchdev_trans *trans)
1676 /* We don't use per-port FDB */
1680 /* We don't need any dynamic resource from the kernel (yet),
1681 * so skip the prepare phase.
1686 int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
1687 const struct switchdev_obj_port_fdb *fdb,
1688 struct switchdev_trans *trans)
1690 int state = is_multicast_ether_addr(fdb->addr) ?
1691 GLOBAL_ATU_DATA_STATE_MC_STATIC :
1692 GLOBAL_ATU_DATA_STATE_UC_STATIC;
1693 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1696 mutex_lock(&ps->smi_mutex);
1697 ret = _mv88e6xxx_port_fdb_load(ds, port, fdb->addr, fdb->vid, state);
1698 mutex_unlock(&ps->smi_mutex);
1703 int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
1704 const struct switchdev_obj_port_fdb *fdb)
1706 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1709 mutex_lock(&ps->smi_mutex);
1710 ret = _mv88e6xxx_port_fdb_load(ds, port, fdb->addr, fdb->vid,
1711 GLOBAL_ATU_DATA_STATE_UNUSED);
1712 mutex_unlock(&ps->smi_mutex);
1717 static int _mv88e6xxx_atu_getnext(struct dsa_switch *ds, u16 fid,
1718 struct mv88e6xxx_atu_entry *entry)
1720 struct mv88e6xxx_atu_entry next = { 0 };
1725 ret = _mv88e6xxx_atu_wait(ds);
1729 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_FID, fid);
1733 ret = _mv88e6xxx_atu_cmd(ds, GLOBAL_ATU_OP_GET_NEXT_DB);
1737 ret = _mv88e6xxx_atu_mac_read(ds, next.mac);
1741 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_ATU_DATA);
1745 next.state = ret & GLOBAL_ATU_DATA_STATE_MASK;
1746 if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1747 unsigned int mask, shift;
1749 if (ret & GLOBAL_ATU_DATA_TRUNK) {
1751 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
1752 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
1755 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
1756 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
1759 next.portv_trunkid = (ret & mask) >> shift;
1766 int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
1767 struct switchdev_obj_port_fdb *fdb,
1768 int (*cb)(struct switchdev_obj *obj))
1770 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1771 struct mv88e6xxx_vtu_stu_entry vlan = {
1772 .vid = GLOBAL_VTU_VID_MASK, /* all ones */
1776 mutex_lock(&ps->smi_mutex);
1778 err = _mv88e6xxx_vtu_vid_write(ds, vlan.vid);
1783 struct mv88e6xxx_atu_entry addr = {
1784 .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
1787 err = _mv88e6xxx_vtu_getnext(ds, &vlan);
1794 err = _mv88e6xxx_atu_mac_write(ds, addr.mac);
1799 err = _mv88e6xxx_atu_getnext(ds, vlan.fid, &addr);
1803 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
1806 if (!addr.trunk && addr.portv_trunkid & BIT(port)) {
1807 bool is_static = addr.state ==
1808 (is_multicast_ether_addr(addr.mac) ?
1809 GLOBAL_ATU_DATA_STATE_MC_STATIC :
1810 GLOBAL_ATU_DATA_STATE_UC_STATIC);
1812 fdb->vid = vlan.vid;
1813 ether_addr_copy(fdb->addr, addr.mac);
1814 fdb->ndm_state = is_static ? NUD_NOARP :
1817 err = cb(&fdb->obj);
1821 } while (!is_broadcast_ether_addr(addr.mac));
1823 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
1826 mutex_unlock(&ps->smi_mutex);
1831 static void mv88e6xxx_bridge_work(struct work_struct *work)
1833 struct mv88e6xxx_priv_state *ps;
1834 struct dsa_switch *ds;
1837 ps = container_of(work, struct mv88e6xxx_priv_state, bridge_work);
1838 ds = ((struct dsa_switch *)ps) - 1;
1840 while (ps->port_state_update_mask) {
1841 port = __ffs(ps->port_state_update_mask);
1842 clear_bit(port, &ps->port_state_update_mask);
1843 mv88e6xxx_set_port_state(ds, port, ps->port_state[port]);
1847 static int mv88e6xxx_setup_port(struct dsa_switch *ds, int port)
1849 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1853 mutex_lock(&ps->smi_mutex);
1855 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1856 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1857 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
1858 mv88e6xxx_6065_family(ds) || mv88e6xxx_6320_family(ds)) {
1859 /* MAC Forcing register: don't force link, speed,
1860 * duplex or flow control state to any particular
1861 * values on physical ports, but force the CPU port
1862 * and all DSA ports to their maximum bandwidth and
1865 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_PCS_CTRL);
1866 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
1867 reg &= ~PORT_PCS_CTRL_UNFORCED;
1868 reg |= PORT_PCS_CTRL_FORCE_LINK |
1869 PORT_PCS_CTRL_LINK_UP |
1870 PORT_PCS_CTRL_DUPLEX_FULL |
1871 PORT_PCS_CTRL_FORCE_DUPLEX;
1872 if (mv88e6xxx_6065_family(ds))
1873 reg |= PORT_PCS_CTRL_100;
1875 reg |= PORT_PCS_CTRL_1000;
1877 reg |= PORT_PCS_CTRL_UNFORCED;
1880 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1881 PORT_PCS_CTRL, reg);
1886 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
1887 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
1888 * tunneling, determine priority by looking at 802.1p and IP
1889 * priority fields (IP prio has precedence), and set STP state
1892 * If this is the CPU link, use DSA or EDSA tagging depending
1893 * on which tagging mode was configured.
1895 * If this is a link to another switch, use DSA tagging mode.
1897 * If this is the upstream port for this switch, enable
1898 * forwarding of unknown unicasts and multicasts.
1901 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1902 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1903 mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) ||
1904 mv88e6xxx_6185_family(ds) || mv88e6xxx_6320_family(ds))
1905 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
1906 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
1907 PORT_CONTROL_STATE_FORWARDING;
1908 if (dsa_is_cpu_port(ds, port)) {
1909 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds))
1910 reg |= PORT_CONTROL_DSA_TAG;
1911 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1912 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1913 mv88e6xxx_6320_family(ds)) {
1914 if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)
1915 reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA;
1917 reg |= PORT_CONTROL_FRAME_MODE_DSA;
1918 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
1919 PORT_CONTROL_FORWARD_UNKNOWN_MC;
1922 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1923 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1924 mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) ||
1925 mv88e6xxx_6185_family(ds) || mv88e6xxx_6320_family(ds)) {
1926 if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)
1927 reg |= PORT_CONTROL_EGRESS_ADD_TAG;
1930 if (dsa_is_dsa_port(ds, port)) {
1931 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds))
1932 reg |= PORT_CONTROL_DSA_TAG;
1933 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1934 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1935 mv88e6xxx_6320_family(ds)) {
1936 reg |= PORT_CONTROL_FRAME_MODE_DSA;
1939 if (port == dsa_upstream_port(ds))
1940 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
1941 PORT_CONTROL_FORWARD_UNKNOWN_MC;
1944 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1950 /* Port Control 2: don't force a good FCS, set the maximum frame size to
1951 * 10240 bytes, enable secure 802.1q tags, don't discard tagged or
1952 * untagged frames on this port, do a destination address lookup on all
1953 * received packets as usual, disable ARP mirroring and don't send a
1954 * copy of all transmitted/received frames on this port to the CPU.
1957 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1958 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1959 mv88e6xxx_6095_family(ds) || mv88e6xxx_6320_family(ds))
1960 reg = PORT_CONTROL_2_MAP_DA;
1962 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1963 mv88e6xxx_6165_family(ds) || mv88e6xxx_6320_family(ds))
1964 reg |= PORT_CONTROL_2_JUMBO_10240;
1966 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds)) {
1967 /* Set the upstream port this port should use */
1968 reg |= dsa_upstream_port(ds);
1969 /* enable forwarding of unknown multicast addresses to
1972 if (port == dsa_upstream_port(ds))
1973 reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
1976 reg |= PORT_CONTROL_2_8021Q_SECURE;
1979 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1980 PORT_CONTROL_2, reg);
1985 /* Port Association Vector: when learning source addresses
1986 * of packets, add the address to the address database using
1987 * a port bitmap that has only the bit for this port set and
1988 * the other bits clear.
1990 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_ASSOC_VECTOR,
1995 /* Egress rate control 2: disable egress rate control. */
1996 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_RATE_CONTROL_2,
2001 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2002 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2003 mv88e6xxx_6320_family(ds)) {
2004 /* Do not limit the period of time that this port can
2005 * be paused for by the remote end or the period of
2006 * time that this port can pause the remote end.
2008 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2009 PORT_PAUSE_CTRL, 0x0000);
2013 /* Port ATU control: disable limiting the number of
2014 * address database entries that this port is allowed
2017 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2018 PORT_ATU_CONTROL, 0x0000);
2019 /* Priority Override: disable DA, SA and VTU priority
2022 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2023 PORT_PRI_OVERRIDE, 0x0000);
2027 /* Port Ethertype: use the Ethertype DSA Ethertype
2030 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2031 PORT_ETH_TYPE, ETH_P_EDSA);
2034 /* Tag Remap: use an identity 802.1p prio -> switch
2037 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2038 PORT_TAG_REGMAP_0123, 0x3210);
2042 /* Tag Remap 2: use an identity 802.1p prio -> switch
2045 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2046 PORT_TAG_REGMAP_4567, 0x7654);
2051 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2052 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2053 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
2054 mv88e6xxx_6320_family(ds)) {
2055 /* Rate Control: disable ingress rate limiting. */
2056 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2057 PORT_RATE_CONTROL, 0x0001);
2062 /* Port Control 1: disable trunking, disable sending
2063 * learning messages to this port.
2065 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL_1, 0x0000);
2069 /* Port based VLAN map: do not give each port its own address
2070 * database, and allow every port to egress frames on all other ports.
2072 reg = BIT(ps->num_ports) - 1; /* all ports */
2073 ret = _mv88e6xxx_port_vlan_map_set(ds, port, reg & ~port);
2077 /* Default VLAN ID and priority: don't set a default VLAN
2078 * ID, and set the default packet priority to zero.
2080 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_DEFAULT_VLAN,
2083 mutex_unlock(&ps->smi_mutex);
2087 int mv88e6xxx_setup_ports(struct dsa_switch *ds)
2089 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2093 for (i = 0; i < ps->num_ports; i++) {
2094 ret = mv88e6xxx_setup_port(ds, i);
2101 int mv88e6xxx_setup_common(struct dsa_switch *ds)
2103 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2105 mutex_init(&ps->smi_mutex);
2107 ps->id = REG_READ(REG_PORT(0), PORT_SWITCH_ID) & 0xfff0;
2109 INIT_WORK(&ps->bridge_work, mv88e6xxx_bridge_work);
2114 int mv88e6xxx_setup_global(struct dsa_switch *ds)
2116 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2120 /* Set the default address aging time to 5 minutes, and
2121 * enable address learn messages to be sent to all message
2124 REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL,
2125 0x0140 | GLOBAL_ATU_CONTROL_LEARN2ALL);
2127 /* Configure the IP ToS mapping registers. */
2128 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000);
2129 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000);
2130 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555);
2131 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555);
2132 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa);
2133 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa);
2134 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff);
2135 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff);
2137 /* Configure the IEEE 802.1p priority mapping register. */
2138 REG_WRITE(REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41);
2140 /* Send all frames with destination addresses matching
2141 * 01:80:c2:00:00:0x to the CPU port.
2143 REG_WRITE(REG_GLOBAL2, GLOBAL2_MGMT_EN_0X, 0xffff);
2145 /* Ignore removed tag data on doubly tagged packets, disable
2146 * flow control messages, force flow control priority to the
2147 * highest, and send all special multicast frames to the CPU
2148 * port at the highest priority.
2150 REG_WRITE(REG_GLOBAL2, GLOBAL2_SWITCH_MGMT,
2151 0x7 | GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x70 |
2152 GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI);
2154 /* Program the DSA routing table. */
2155 for (i = 0; i < 32; i++) {
2158 if (ds->pd->rtable &&
2159 i != ds->index && i < ds->dst->pd->nr_chips)
2160 nexthop = ds->pd->rtable[i] & 0x1f;
2162 REG_WRITE(REG_GLOBAL2, GLOBAL2_DEVICE_MAPPING,
2163 GLOBAL2_DEVICE_MAPPING_UPDATE |
2164 (i << GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT) |
2168 /* Clear all trunk masks. */
2169 for (i = 0; i < 8; i++)
2170 REG_WRITE(REG_GLOBAL2, GLOBAL2_TRUNK_MASK,
2171 0x8000 | (i << GLOBAL2_TRUNK_MASK_NUM_SHIFT) |
2172 ((1 << ps->num_ports) - 1));
2174 /* Clear all trunk mappings. */
2175 for (i = 0; i < 16; i++)
2176 REG_WRITE(REG_GLOBAL2, GLOBAL2_TRUNK_MAPPING,
2177 GLOBAL2_TRUNK_MAPPING_UPDATE |
2178 (i << GLOBAL2_TRUNK_MAPPING_ID_SHIFT));
2180 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2181 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2182 mv88e6xxx_6320_family(ds)) {
2183 /* Send all frames with destination addresses matching
2184 * 01:80:c2:00:00:2x to the CPU port.
2186 REG_WRITE(REG_GLOBAL2, GLOBAL2_MGMT_EN_2X, 0xffff);
2188 /* Initialise cross-chip port VLAN table to reset
2191 REG_WRITE(REG_GLOBAL2, GLOBAL2_PVT_ADDR, 0x9000);
2193 /* Clear the priority override table. */
2194 for (i = 0; i < 16; i++)
2195 REG_WRITE(REG_GLOBAL2, GLOBAL2_PRIO_OVERRIDE,
2199 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2200 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2201 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
2202 mv88e6xxx_6320_family(ds)) {
2203 /* Disable ingress rate limiting by resetting all
2204 * ingress rate limit registers to their initial
2207 for (i = 0; i < ps->num_ports; i++)
2208 REG_WRITE(REG_GLOBAL2, GLOBAL2_INGRESS_OP,
2212 /* Clear the statistics counters for all ports */
2213 REG_WRITE(REG_GLOBAL, GLOBAL_STATS_OP, GLOBAL_STATS_OP_FLUSH_ALL);
2215 /* Wait for the flush to complete. */
2216 mutex_lock(&ps->smi_mutex);
2217 ret = _mv88e6xxx_stats_wait(ds);
2221 /* Clear all ATU entries */
2222 ret = _mv88e6xxx_atu_flush(ds, 0, true);
2226 /* Clear all the VTU and STU entries */
2227 ret = _mv88e6xxx_vtu_stu_flush(ds);
2229 mutex_unlock(&ps->smi_mutex);
2234 int mv88e6xxx_switch_reset(struct dsa_switch *ds, bool ppu_active)
2236 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2237 u16 is_reset = (ppu_active ? 0x8800 : 0xc800);
2238 unsigned long timeout;
2242 /* Set all ports to the disabled state. */
2243 for (i = 0; i < ps->num_ports; i++) {
2244 ret = REG_READ(REG_PORT(i), PORT_CONTROL);
2245 REG_WRITE(REG_PORT(i), PORT_CONTROL, ret & 0xfffc);
2248 /* Wait for transmit queues to drain. */
2249 usleep_range(2000, 4000);
2251 /* Reset the switch. Keep the PPU active if requested. The PPU
2252 * needs to be active to support indirect phy register access
2253 * through global registers 0x18 and 0x19.
2256 REG_WRITE(REG_GLOBAL, 0x04, 0xc000);
2258 REG_WRITE(REG_GLOBAL, 0x04, 0xc400);
2260 /* Wait up to one second for reset to complete. */
2261 timeout = jiffies + 1 * HZ;
2262 while (time_before(jiffies, timeout)) {
2263 ret = REG_READ(REG_GLOBAL, 0x00);
2264 if ((ret & is_reset) == is_reset)
2266 usleep_range(1000, 2000);
2268 if (time_after(jiffies, timeout))
2274 int mv88e6xxx_phy_page_read(struct dsa_switch *ds, int port, int page, int reg)
2276 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2279 mutex_lock(&ps->smi_mutex);
2280 ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page);
2283 ret = _mv88e6xxx_phy_read_indirect(ds, port, reg);
2285 _mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0);
2286 mutex_unlock(&ps->smi_mutex);
2290 int mv88e6xxx_phy_page_write(struct dsa_switch *ds, int port, int page,
2293 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2296 mutex_lock(&ps->smi_mutex);
2297 ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page);
2301 ret = _mv88e6xxx_phy_write_indirect(ds, port, reg, val);
2303 _mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0);
2304 mutex_unlock(&ps->smi_mutex);
2308 static int mv88e6xxx_port_to_phy_addr(struct dsa_switch *ds, int port)
2310 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2312 if (port >= 0 && port < ps->num_ports)
2318 mv88e6xxx_phy_read(struct dsa_switch *ds, int port, int regnum)
2320 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2321 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2327 mutex_lock(&ps->smi_mutex);
2328 ret = _mv88e6xxx_phy_read(ds, addr, regnum);
2329 mutex_unlock(&ps->smi_mutex);
2334 mv88e6xxx_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
2336 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2337 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2343 mutex_lock(&ps->smi_mutex);
2344 ret = _mv88e6xxx_phy_write(ds, addr, regnum, val);
2345 mutex_unlock(&ps->smi_mutex);
2350 mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int port, int regnum)
2352 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2353 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2359 mutex_lock(&ps->smi_mutex);
2360 ret = _mv88e6xxx_phy_read_indirect(ds, addr, regnum);
2361 mutex_unlock(&ps->smi_mutex);
2366 mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int port, int regnum,
2369 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2370 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2376 mutex_lock(&ps->smi_mutex);
2377 ret = _mv88e6xxx_phy_write_indirect(ds, addr, regnum, val);
2378 mutex_unlock(&ps->smi_mutex);
2382 #ifdef CONFIG_NET_DSA_HWMON
2384 static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp)
2386 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2392 mutex_lock(&ps->smi_mutex);
2394 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x6);
2398 /* Enable temperature sensor */
2399 ret = _mv88e6xxx_phy_read(ds, 0x0, 0x1a);
2403 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret | (1 << 5));
2407 /* Wait for temperature to stabilize */
2408 usleep_range(10000, 12000);
2410 val = _mv88e6xxx_phy_read(ds, 0x0, 0x1a);
2416 /* Disable temperature sensor */
2417 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret & ~(1 << 5));
2421 *temp = ((val & 0x1f) - 5) * 5;
2424 _mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x0);
2425 mutex_unlock(&ps->smi_mutex);
2429 static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp)
2431 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
2436 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 27);
2440 *temp = (ret & 0xff) - 25;
2445 int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
2447 if (mv88e6xxx_6320_family(ds) || mv88e6xxx_6352_family(ds))
2448 return mv88e63xx_get_temp(ds, temp);
2450 return mv88e61xx_get_temp(ds, temp);
2453 int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp)
2455 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
2458 if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds))
2463 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
2467 *temp = (((ret >> 8) & 0x1f) * 5) - 25;
2472 int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp)
2474 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
2477 if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds))
2480 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
2483 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
2484 return mv88e6xxx_phy_page_write(ds, phy, 6, 26,
2485 (ret & 0xe0ff) | (temp << 8));
2488 int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm)
2490 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
2493 if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds))
2498 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
2502 *alarm = !!(ret & 0x40);
2506 #endif /* CONFIG_NET_DSA_HWMON */
2508 static int __init mv88e6xxx_init(void)
2510 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
2511 register_switch_driver(&mv88e6131_switch_driver);
2513 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65)
2514 register_switch_driver(&mv88e6123_61_65_switch_driver);
2516 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
2517 register_switch_driver(&mv88e6352_switch_driver);
2519 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
2520 register_switch_driver(&mv88e6171_switch_driver);
2524 module_init(mv88e6xxx_init);
2526 static void __exit mv88e6xxx_cleanup(void)
2528 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
2529 unregister_switch_driver(&mv88e6171_switch_driver);
2531 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
2532 unregister_switch_driver(&mv88e6352_switch_driver);
2534 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65)
2535 unregister_switch_driver(&mv88e6123_61_65_switch_driver);
2537 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
2538 unregister_switch_driver(&mv88e6131_switch_driver);
2541 module_exit(mv88e6xxx_cleanup);
2543 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
2544 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
2545 MODULE_LICENSE("GPL");