2 * net/dsa/mv88e6xxx.c - Marvell 88e6xxx switch chip support
3 * Copyright (c) 2008 Marvell Semiconductor
5 * Copyright (c) 2015 CMC Electronics, Inc.
6 * Added support for VLAN Table Unit operations
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/debugfs.h>
15 #include <linux/delay.h>
16 #include <linux/etherdevice.h>
17 #include <linux/ethtool.h>
18 #include <linux/if_bridge.h>
19 #include <linux/jiffies.h>
20 #include <linux/list.h>
21 #include <linux/module.h>
22 #include <linux/netdevice.h>
23 #include <linux/phy.h>
24 #include <linux/seq_file.h>
26 #include <net/switchdev.h>
27 #include "mv88e6xxx.h"
29 /* MDIO bus access can be nested in the case of PHYs connected to the
30 * internal MDIO bus of the switch, which is accessed via MDIO bus of
31 * the Ethernet interface. Avoid lockdep false positives by using
32 * mutex_lock_nested().
34 static int mv88e6xxx_mdiobus_read(struct mii_bus *bus, int addr, u32 regnum)
38 mutex_lock_nested(&bus->mdio_lock, SINGLE_DEPTH_NESTING);
39 ret = bus->read(bus, addr, regnum);
40 mutex_unlock(&bus->mdio_lock);
45 static int mv88e6xxx_mdiobus_write(struct mii_bus *bus, int addr, u32 regnum,
50 mutex_lock_nested(&bus->mdio_lock, SINGLE_DEPTH_NESTING);
51 ret = bus->write(bus, addr, regnum, val);
52 mutex_unlock(&bus->mdio_lock);
57 /* If the switch's ADDR[4:0] strap pins are strapped to zero, it will
58 * use all 32 SMI bus addresses on its SMI bus, and all switch registers
59 * will be directly accessible on some {device address,register address}
60 * pair. If the ADDR[4:0] pins are not strapped to zero, the switch
61 * will only respond to SMI transactions to that specific address, and
62 * an indirect addressing mechanism needs to be used to access its
65 static int mv88e6xxx_reg_wait_ready(struct mii_bus *bus, int sw_addr)
70 for (i = 0; i < 16; i++) {
71 ret = mv88e6xxx_mdiobus_read(bus, sw_addr, SMI_CMD);
75 if ((ret & SMI_CMD_BUSY) == 0)
82 int __mv88e6xxx_reg_read(struct mii_bus *bus, int sw_addr, int addr, int reg)
87 return mv88e6xxx_mdiobus_read(bus, addr, reg);
89 /* Wait for the bus to become free. */
90 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
94 /* Transmit the read command. */
95 ret = mv88e6xxx_mdiobus_write(bus, sw_addr, SMI_CMD,
96 SMI_CMD_OP_22_READ | (addr << 5) | reg);
100 /* Wait for the read command to complete. */
101 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
106 ret = mv88e6xxx_mdiobus_read(bus, sw_addr, SMI_DATA);
113 /* Must be called with SMI mutex held */
114 static int _mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
116 struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
122 ret = __mv88e6xxx_reg_read(bus, ds->pd->sw_addr, addr, reg);
126 dev_dbg(ds->master_dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
132 int mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
134 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
137 mutex_lock(&ps->smi_mutex);
138 ret = _mv88e6xxx_reg_read(ds, addr, reg);
139 mutex_unlock(&ps->smi_mutex);
144 int __mv88e6xxx_reg_write(struct mii_bus *bus, int sw_addr, int addr,
150 return mv88e6xxx_mdiobus_write(bus, addr, reg, val);
152 /* Wait for the bus to become free. */
153 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
157 /* Transmit the data to write. */
158 ret = mv88e6xxx_mdiobus_write(bus, sw_addr, SMI_DATA, val);
162 /* Transmit the write command. */
163 ret = mv88e6xxx_mdiobus_write(bus, sw_addr, SMI_CMD,
164 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
168 /* Wait for the write command to complete. */
169 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
176 /* Must be called with SMI mutex held */
177 static int _mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg,
180 struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
185 dev_dbg(ds->master_dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
188 return __mv88e6xxx_reg_write(bus, ds->pd->sw_addr, addr, reg, val);
191 int mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
193 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
196 mutex_lock(&ps->smi_mutex);
197 ret = _mv88e6xxx_reg_write(ds, addr, reg, val);
198 mutex_unlock(&ps->smi_mutex);
203 int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr)
205 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]);
206 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
207 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
212 int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr)
217 for (i = 0; i < 6; i++) {
220 /* Write the MAC address byte. */
221 REG_WRITE(REG_GLOBAL2, GLOBAL2_SWITCH_MAC,
222 GLOBAL2_SWITCH_MAC_BUSY | (i << 8) | addr[i]);
224 /* Wait for the write to complete. */
225 for (j = 0; j < 16; j++) {
226 ret = REG_READ(REG_GLOBAL2, GLOBAL2_SWITCH_MAC);
227 if ((ret & GLOBAL2_SWITCH_MAC_BUSY) == 0)
237 /* Must be called with SMI mutex held */
238 static int _mv88e6xxx_phy_read(struct dsa_switch *ds, int addr, int regnum)
241 return _mv88e6xxx_reg_read(ds, addr, regnum);
245 /* Must be called with SMI mutex held */
246 static int _mv88e6xxx_phy_write(struct dsa_switch *ds, int addr, int regnum,
250 return _mv88e6xxx_reg_write(ds, addr, regnum, val);
254 #ifdef CONFIG_NET_DSA_MV88E6XXX_NEED_PPU
255 static int mv88e6xxx_ppu_disable(struct dsa_switch *ds)
258 unsigned long timeout;
260 ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL);
261 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL,
262 ret & ~GLOBAL_CONTROL_PPU_ENABLE);
264 timeout = jiffies + 1 * HZ;
265 while (time_before(jiffies, timeout)) {
266 ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS);
267 usleep_range(1000, 2000);
268 if ((ret & GLOBAL_STATUS_PPU_MASK) !=
269 GLOBAL_STATUS_PPU_POLLING)
276 static int mv88e6xxx_ppu_enable(struct dsa_switch *ds)
279 unsigned long timeout;
281 ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL);
282 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, ret | GLOBAL_CONTROL_PPU_ENABLE);
284 timeout = jiffies + 1 * HZ;
285 while (time_before(jiffies, timeout)) {
286 ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS);
287 usleep_range(1000, 2000);
288 if ((ret & GLOBAL_STATUS_PPU_MASK) ==
289 GLOBAL_STATUS_PPU_POLLING)
296 static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
298 struct mv88e6xxx_priv_state *ps;
300 ps = container_of(ugly, struct mv88e6xxx_priv_state, ppu_work);
301 if (mutex_trylock(&ps->ppu_mutex)) {
302 struct dsa_switch *ds = ((struct dsa_switch *)ps) - 1;
304 if (mv88e6xxx_ppu_enable(ds) == 0)
305 ps->ppu_disabled = 0;
306 mutex_unlock(&ps->ppu_mutex);
310 static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
312 struct mv88e6xxx_priv_state *ps = (void *)_ps;
314 schedule_work(&ps->ppu_work);
317 static int mv88e6xxx_ppu_access_get(struct dsa_switch *ds)
319 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
322 mutex_lock(&ps->ppu_mutex);
324 /* If the PHY polling unit is enabled, disable it so that
325 * we can access the PHY registers. If it was already
326 * disabled, cancel the timer that is going to re-enable
329 if (!ps->ppu_disabled) {
330 ret = mv88e6xxx_ppu_disable(ds);
332 mutex_unlock(&ps->ppu_mutex);
335 ps->ppu_disabled = 1;
337 del_timer(&ps->ppu_timer);
344 static void mv88e6xxx_ppu_access_put(struct dsa_switch *ds)
346 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
348 /* Schedule a timer to re-enable the PHY polling unit. */
349 mod_timer(&ps->ppu_timer, jiffies + msecs_to_jiffies(10));
350 mutex_unlock(&ps->ppu_mutex);
353 void mv88e6xxx_ppu_state_init(struct dsa_switch *ds)
355 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
357 mutex_init(&ps->ppu_mutex);
358 INIT_WORK(&ps->ppu_work, mv88e6xxx_ppu_reenable_work);
359 init_timer(&ps->ppu_timer);
360 ps->ppu_timer.data = (unsigned long)ps;
361 ps->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
364 int mv88e6xxx_phy_read_ppu(struct dsa_switch *ds, int addr, int regnum)
368 ret = mv88e6xxx_ppu_access_get(ds);
370 ret = mv88e6xxx_reg_read(ds, addr, regnum);
371 mv88e6xxx_ppu_access_put(ds);
377 int mv88e6xxx_phy_write_ppu(struct dsa_switch *ds, int addr,
382 ret = mv88e6xxx_ppu_access_get(ds);
384 ret = mv88e6xxx_reg_write(ds, addr, regnum, val);
385 mv88e6xxx_ppu_access_put(ds);
392 static bool mv88e6xxx_6065_family(struct dsa_switch *ds)
394 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
397 case PORT_SWITCH_ID_6031:
398 case PORT_SWITCH_ID_6061:
399 case PORT_SWITCH_ID_6035:
400 case PORT_SWITCH_ID_6065:
406 static bool mv88e6xxx_6095_family(struct dsa_switch *ds)
408 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
411 case PORT_SWITCH_ID_6092:
412 case PORT_SWITCH_ID_6095:
418 static bool mv88e6xxx_6097_family(struct dsa_switch *ds)
420 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
423 case PORT_SWITCH_ID_6046:
424 case PORT_SWITCH_ID_6085:
425 case PORT_SWITCH_ID_6096:
426 case PORT_SWITCH_ID_6097:
432 static bool mv88e6xxx_6165_family(struct dsa_switch *ds)
434 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
437 case PORT_SWITCH_ID_6123:
438 case PORT_SWITCH_ID_6161:
439 case PORT_SWITCH_ID_6165:
445 static bool mv88e6xxx_6185_family(struct dsa_switch *ds)
447 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
450 case PORT_SWITCH_ID_6121:
451 case PORT_SWITCH_ID_6122:
452 case PORT_SWITCH_ID_6152:
453 case PORT_SWITCH_ID_6155:
454 case PORT_SWITCH_ID_6182:
455 case PORT_SWITCH_ID_6185:
456 case PORT_SWITCH_ID_6108:
457 case PORT_SWITCH_ID_6131:
463 static bool mv88e6xxx_6320_family(struct dsa_switch *ds)
465 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
468 case PORT_SWITCH_ID_6320:
469 case PORT_SWITCH_ID_6321:
475 static bool mv88e6xxx_6351_family(struct dsa_switch *ds)
477 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
480 case PORT_SWITCH_ID_6171:
481 case PORT_SWITCH_ID_6175:
482 case PORT_SWITCH_ID_6350:
483 case PORT_SWITCH_ID_6351:
489 static bool mv88e6xxx_6352_family(struct dsa_switch *ds)
491 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
494 case PORT_SWITCH_ID_6172:
495 case PORT_SWITCH_ID_6176:
496 case PORT_SWITCH_ID_6240:
497 case PORT_SWITCH_ID_6352:
503 /* We expect the switch to perform auto negotiation if there is a real
504 * phy. However, in the case of a fixed link phy, we force the port
505 * settings from the fixed link settings.
507 void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
508 struct phy_device *phydev)
510 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
514 if (!phy_is_pseudo_fixed_link(phydev))
517 mutex_lock(&ps->smi_mutex);
519 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_PCS_CTRL);
523 reg = ret & ~(PORT_PCS_CTRL_LINK_UP |
524 PORT_PCS_CTRL_FORCE_LINK |
525 PORT_PCS_CTRL_DUPLEX_FULL |
526 PORT_PCS_CTRL_FORCE_DUPLEX |
527 PORT_PCS_CTRL_UNFORCED);
529 reg |= PORT_PCS_CTRL_FORCE_LINK;
531 reg |= PORT_PCS_CTRL_LINK_UP;
533 if (mv88e6xxx_6065_family(ds) && phydev->speed > SPEED_100)
536 switch (phydev->speed) {
538 reg |= PORT_PCS_CTRL_1000;
541 reg |= PORT_PCS_CTRL_100;
544 reg |= PORT_PCS_CTRL_10;
547 pr_info("Unknown speed");
551 reg |= PORT_PCS_CTRL_FORCE_DUPLEX;
552 if (phydev->duplex == DUPLEX_FULL)
553 reg |= PORT_PCS_CTRL_DUPLEX_FULL;
555 if ((mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds)) &&
556 (port >= ps->num_ports - 2)) {
557 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
558 reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK;
559 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
560 reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
561 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
562 reg |= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
563 PORT_PCS_CTRL_RGMII_DELAY_TXCLK);
565 _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_PCS_CTRL, reg);
568 mutex_unlock(&ps->smi_mutex);
571 /* Must be called with SMI mutex held */
572 static int _mv88e6xxx_stats_wait(struct dsa_switch *ds)
577 for (i = 0; i < 10; i++) {
578 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_OP);
579 if ((ret & GLOBAL_STATS_OP_BUSY) == 0)
586 /* Must be called with SMI mutex held */
587 static int _mv88e6xxx_stats_snapshot(struct dsa_switch *ds, int port)
591 if (mv88e6xxx_6320_family(ds) || mv88e6xxx_6352_family(ds))
592 port = (port + 1) << 5;
594 /* Snapshot the hardware statistics counters for this port. */
595 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_STATS_OP,
596 GLOBAL_STATS_OP_CAPTURE_PORT |
597 GLOBAL_STATS_OP_HIST_RX_TX | port);
601 /* Wait for the snapshotting to complete. */
602 ret = _mv88e6xxx_stats_wait(ds);
609 /* Must be called with SMI mutex held */
610 static void _mv88e6xxx_stats_read(struct dsa_switch *ds, int stat, u32 *val)
617 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_STATS_OP,
618 GLOBAL_STATS_OP_READ_CAPTURED |
619 GLOBAL_STATS_OP_HIST_RX_TX | stat);
623 ret = _mv88e6xxx_stats_wait(ds);
627 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_32);
633 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_01);
640 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
641 { "in_good_octets", 8, 0x00, },
642 { "in_bad_octets", 4, 0x02, },
643 { "in_unicast", 4, 0x04, },
644 { "in_broadcasts", 4, 0x06, },
645 { "in_multicasts", 4, 0x07, },
646 { "in_pause", 4, 0x16, },
647 { "in_undersize", 4, 0x18, },
648 { "in_fragments", 4, 0x19, },
649 { "in_oversize", 4, 0x1a, },
650 { "in_jabber", 4, 0x1b, },
651 { "in_rx_error", 4, 0x1c, },
652 { "in_fcs_error", 4, 0x1d, },
653 { "out_octets", 8, 0x0e, },
654 { "out_unicast", 4, 0x10, },
655 { "out_broadcasts", 4, 0x13, },
656 { "out_multicasts", 4, 0x12, },
657 { "out_pause", 4, 0x15, },
658 { "excessive", 4, 0x11, },
659 { "collisions", 4, 0x1e, },
660 { "deferred", 4, 0x05, },
661 { "single", 4, 0x14, },
662 { "multiple", 4, 0x17, },
663 { "out_fcs_error", 4, 0x03, },
664 { "late", 4, 0x1f, },
665 { "hist_64bytes", 4, 0x08, },
666 { "hist_65_127bytes", 4, 0x09, },
667 { "hist_128_255bytes", 4, 0x0a, },
668 { "hist_256_511bytes", 4, 0x0b, },
669 { "hist_512_1023bytes", 4, 0x0c, },
670 { "hist_1024_max_bytes", 4, 0x0d, },
671 /* Not all devices have the following counters */
672 { "sw_in_discards", 4, 0x110, },
673 { "sw_in_filtered", 2, 0x112, },
674 { "sw_out_filtered", 2, 0x113, },
678 static bool have_sw_in_discards(struct dsa_switch *ds)
680 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
683 case PORT_SWITCH_ID_6095: case PORT_SWITCH_ID_6161:
684 case PORT_SWITCH_ID_6165: case PORT_SWITCH_ID_6171:
685 case PORT_SWITCH_ID_6172: case PORT_SWITCH_ID_6176:
686 case PORT_SWITCH_ID_6182: case PORT_SWITCH_ID_6185:
687 case PORT_SWITCH_ID_6352:
694 static void _mv88e6xxx_get_strings(struct dsa_switch *ds,
696 struct mv88e6xxx_hw_stat *stats,
697 int port, uint8_t *data)
701 for (i = 0; i < nr_stats; i++) {
702 memcpy(data + i * ETH_GSTRING_LEN,
703 stats[i].string, ETH_GSTRING_LEN);
707 static uint64_t _mv88e6xxx_get_ethtool_stat(struct dsa_switch *ds,
709 struct mv88e6xxx_hw_stat *stats,
712 struct mv88e6xxx_hw_stat *s = stats + stat;
718 if (s->reg >= 0x100) {
719 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port),
725 if (s->sizeof_stat == 4) {
726 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port),
733 _mv88e6xxx_stats_read(ds, s->reg, &low);
734 if (s->sizeof_stat == 8)
735 _mv88e6xxx_stats_read(ds, s->reg + 1, &high);
737 value = (((u64)high) << 16) | low;
741 static void _mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds,
743 struct mv88e6xxx_hw_stat *stats,
744 int port, uint64_t *data)
746 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
750 mutex_lock(&ps->smi_mutex);
752 ret = _mv88e6xxx_stats_snapshot(ds, port);
754 mutex_unlock(&ps->smi_mutex);
758 /* Read each of the counters. */
759 for (i = 0; i < nr_stats; i++)
760 data[i] = _mv88e6xxx_get_ethtool_stat(ds, i, stats, port);
762 mutex_unlock(&ps->smi_mutex);
765 /* All the statistics in the table */
767 mv88e6xxx_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
769 if (have_sw_in_discards(ds))
770 _mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6xxx_hw_stats),
771 mv88e6xxx_hw_stats, port, data);
773 _mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6xxx_hw_stats) - 3,
774 mv88e6xxx_hw_stats, port, data);
777 int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
779 if (have_sw_in_discards(ds))
780 return ARRAY_SIZE(mv88e6xxx_hw_stats);
781 return ARRAY_SIZE(mv88e6xxx_hw_stats) - 3;
785 mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds,
786 int port, uint64_t *data)
788 if (have_sw_in_discards(ds))
789 _mv88e6xxx_get_ethtool_stats(
790 ds, ARRAY_SIZE(mv88e6xxx_hw_stats),
791 mv88e6xxx_hw_stats, port, data);
793 _mv88e6xxx_get_ethtool_stats(
794 ds, ARRAY_SIZE(mv88e6xxx_hw_stats) - 3,
795 mv88e6xxx_hw_stats, port, data);
798 int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
800 return 32 * sizeof(u16);
803 void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
804 struct ethtool_regs *regs, void *_p)
811 memset(p, 0xff, 32 * sizeof(u16));
813 for (i = 0; i < 32; i++) {
816 ret = mv88e6xxx_reg_read(ds, REG_PORT(port), i);
822 /* Must be called with SMI lock held */
823 static int _mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset,
826 unsigned long timeout = jiffies + HZ / 10;
828 while (time_before(jiffies, timeout)) {
831 ret = _mv88e6xxx_reg_read(ds, reg, offset);
837 usleep_range(1000, 2000);
842 static int mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset, u16 mask)
844 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
847 mutex_lock(&ps->smi_mutex);
848 ret = _mv88e6xxx_wait(ds, reg, offset, mask);
849 mutex_unlock(&ps->smi_mutex);
854 static int _mv88e6xxx_phy_wait(struct dsa_switch *ds)
856 return _mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
857 GLOBAL2_SMI_OP_BUSY);
860 int mv88e6xxx_eeprom_load_wait(struct dsa_switch *ds)
862 return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
863 GLOBAL2_EEPROM_OP_LOAD);
866 int mv88e6xxx_eeprom_busy_wait(struct dsa_switch *ds)
868 return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
869 GLOBAL2_EEPROM_OP_BUSY);
872 /* Must be called with SMI lock held */
873 static int _mv88e6xxx_atu_wait(struct dsa_switch *ds)
875 return _mv88e6xxx_wait(ds, REG_GLOBAL, GLOBAL_ATU_OP,
879 /* Must be called with SMI lock held */
880 static int _mv88e6xxx_scratch_wait(struct dsa_switch *ds)
882 return _mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_SCRATCH_MISC,
883 GLOBAL2_SCRATCH_BUSY);
886 /* Must be called with SMI mutex held */
887 static int _mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int addr,
892 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
893 GLOBAL2_SMI_OP_22_READ | (addr << 5) |
898 ret = _mv88e6xxx_phy_wait(ds);
902 return _mv88e6xxx_reg_read(ds, REG_GLOBAL2, GLOBAL2_SMI_DATA);
905 /* Must be called with SMI mutex held */
906 static int _mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int addr,
911 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_DATA, val);
915 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
916 GLOBAL2_SMI_OP_22_WRITE | (addr << 5) |
919 return _mv88e6xxx_phy_wait(ds);
922 int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
924 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
927 mutex_lock(&ps->smi_mutex);
929 reg = _mv88e6xxx_phy_read_indirect(ds, port, 16);
933 e->eee_enabled = !!(reg & 0x0200);
934 e->tx_lpi_enabled = !!(reg & 0x0100);
936 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_STATUS);
940 e->eee_active = !!(reg & PORT_STATUS_EEE);
944 mutex_unlock(&ps->smi_mutex);
948 int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
949 struct phy_device *phydev, struct ethtool_eee *e)
951 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
955 mutex_lock(&ps->smi_mutex);
957 ret = _mv88e6xxx_phy_read_indirect(ds, port, 16);
964 if (e->tx_lpi_enabled)
967 ret = _mv88e6xxx_phy_write_indirect(ds, port, 16, reg);
969 mutex_unlock(&ps->smi_mutex);
974 static int _mv88e6xxx_atu_cmd(struct dsa_switch *ds, u16 cmd)
978 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_OP, cmd);
982 return _mv88e6xxx_atu_wait(ds);
985 static int _mv88e6xxx_atu_data_write(struct dsa_switch *ds,
986 struct mv88e6xxx_atu_entry *entry)
988 u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK;
990 if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
991 unsigned int mask, shift;
994 data |= GLOBAL_ATU_DATA_TRUNK;
995 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
996 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
998 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
999 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
1002 data |= (entry->portv_trunkid << shift) & mask;
1005 return _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_DATA, data);
1008 static int _mv88e6xxx_atu_flush_move(struct dsa_switch *ds,
1009 struct mv88e6xxx_atu_entry *entry,
1015 err = _mv88e6xxx_atu_wait(ds);
1019 err = _mv88e6xxx_atu_data_write(ds, entry);
1024 err = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_FID,
1029 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB :
1030 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
1032 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL :
1033 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC;
1036 return _mv88e6xxx_atu_cmd(ds, op);
1039 static int _mv88e6xxx_atu_flush(struct dsa_switch *ds, u16 fid, bool static_too)
1041 struct mv88e6xxx_atu_entry entry = {
1043 .state = 0, /* EntryState bits must be 0 */
1046 return _mv88e6xxx_atu_flush_move(ds, &entry, static_too);
1049 static int _mv88e6xxx_atu_move(struct dsa_switch *ds, u16 fid, int from_port,
1050 int to_port, bool static_too)
1052 struct mv88e6xxx_atu_entry entry = {
1057 /* EntryState bits must be 0xF */
1058 entry.state = GLOBAL_ATU_DATA_STATE_MASK;
1060 /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
1061 entry.portv_trunkid = (to_port & 0x0f) << 4;
1062 entry.portv_trunkid |= from_port & 0x0f;
1064 return _mv88e6xxx_atu_flush_move(ds, &entry, static_too);
1067 static int _mv88e6xxx_atu_remove(struct dsa_switch *ds, u16 fid, int port,
1070 /* Destination port 0xF means remove the entries */
1071 return _mv88e6xxx_atu_move(ds, fid, port, 0x0f, static_too);
1074 static int mv88e6xxx_set_port_state(struct dsa_switch *ds, int port, u8 state)
1076 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1080 mutex_lock(&ps->smi_mutex);
1082 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_CONTROL);
1088 oldstate = reg & PORT_CONTROL_STATE_MASK;
1089 if (oldstate != state) {
1090 /* Flush forwarding database if we're moving a port
1091 * from Learning or Forwarding state to Disabled or
1092 * Blocking or Listening state.
1094 if (oldstate >= PORT_CONTROL_STATE_LEARNING &&
1095 state <= PORT_CONTROL_STATE_BLOCKING) {
1096 ret = _mv88e6xxx_atu_remove(ds, 0, port, false);
1100 reg = (reg & ~PORT_CONTROL_STATE_MASK) | state;
1101 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL,
1106 mutex_unlock(&ps->smi_mutex);
1110 static int _mv88e6xxx_port_vlan_map_set(struct dsa_switch *ds, int port,
1113 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1114 const u16 mask = (1 << ps->num_ports) - 1;
1117 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_BASE_VLAN);
1122 reg |= output_ports & mask;
1124 return _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_BASE_VLAN, reg);
1127 int mv88e6xxx_port_stp_update(struct dsa_switch *ds, int port, u8 state)
1129 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1133 case BR_STATE_DISABLED:
1134 stp_state = PORT_CONTROL_STATE_DISABLED;
1136 case BR_STATE_BLOCKING:
1137 case BR_STATE_LISTENING:
1138 stp_state = PORT_CONTROL_STATE_BLOCKING;
1140 case BR_STATE_LEARNING:
1141 stp_state = PORT_CONTROL_STATE_LEARNING;
1143 case BR_STATE_FORWARDING:
1145 stp_state = PORT_CONTROL_STATE_FORWARDING;
1149 netdev_dbg(ds->ports[port], "port state %d [%d]\n", state, stp_state);
1151 /* mv88e6xxx_port_stp_update may be called with softirqs disabled,
1152 * so we can not update the port state directly but need to schedule it.
1154 ps->port_state[port] = stp_state;
1155 set_bit(port, &ps->port_state_update_mask);
1156 schedule_work(&ps->bridge_work);
1161 int mv88e6xxx_port_pvid_get(struct dsa_switch *ds, int port, u16 *pvid)
1165 ret = mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_DEFAULT_VLAN);
1169 *pvid = ret & PORT_DEFAULT_VLAN_MASK;
1174 int mv88e6xxx_port_pvid_set(struct dsa_switch *ds, int port, u16 pvid)
1176 return mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_DEFAULT_VLAN,
1177 pvid & PORT_DEFAULT_VLAN_MASK);
1180 static int _mv88e6xxx_vtu_wait(struct dsa_switch *ds)
1182 return _mv88e6xxx_wait(ds, REG_GLOBAL, GLOBAL_VTU_OP,
1183 GLOBAL_VTU_OP_BUSY);
1186 static int _mv88e6xxx_vtu_cmd(struct dsa_switch *ds, u16 op)
1190 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_OP, op);
1194 return _mv88e6xxx_vtu_wait(ds);
1197 static int _mv88e6xxx_vtu_stu_flush(struct dsa_switch *ds)
1201 ret = _mv88e6xxx_vtu_wait(ds);
1205 return _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_FLUSH_ALL);
1208 static int _mv88e6xxx_vtu_stu_data_read(struct dsa_switch *ds,
1209 struct mv88e6xxx_vtu_stu_entry *entry,
1210 unsigned int nibble_offset)
1212 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1217 for (i = 0; i < 3; ++i) {
1218 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1219 GLOBAL_VTU_DATA_0_3 + i);
1226 for (i = 0; i < ps->num_ports; ++i) {
1227 unsigned int shift = (i % 4) * 4 + nibble_offset;
1228 u16 reg = regs[i / 4];
1230 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1236 static int _mv88e6xxx_vtu_stu_data_write(struct dsa_switch *ds,
1237 struct mv88e6xxx_vtu_stu_entry *entry,
1238 unsigned int nibble_offset)
1240 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1241 u16 regs[3] = { 0 };
1245 for (i = 0; i < ps->num_ports; ++i) {
1246 unsigned int shift = (i % 4) * 4 + nibble_offset;
1247 u8 data = entry->data[i];
1249 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1252 for (i = 0; i < 3; ++i) {
1253 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL,
1254 GLOBAL_VTU_DATA_0_3 + i, regs[i]);
1262 static int _mv88e6xxx_vtu_getnext(struct dsa_switch *ds, u16 vid,
1263 struct mv88e6xxx_vtu_stu_entry *entry)
1265 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1268 ret = _mv88e6xxx_vtu_wait(ds);
1272 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_VID,
1273 vid & GLOBAL_VTU_VID_MASK);
1277 ret = _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_VTU_GET_NEXT);
1281 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_VTU_VID);
1285 next.vid = ret & GLOBAL_VTU_VID_MASK;
1286 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1289 ret = _mv88e6xxx_vtu_stu_data_read(ds, &next, 0);
1293 if (mv88e6xxx_6097_family(ds) || mv88e6xxx_6165_family(ds) ||
1294 mv88e6xxx_6351_family(ds) || mv88e6xxx_6352_family(ds)) {
1295 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1300 next.fid = ret & GLOBAL_VTU_FID_MASK;
1302 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1307 next.sid = ret & GLOBAL_VTU_SID_MASK;
1315 static int _mv88e6xxx_vtu_loadpurge(struct dsa_switch *ds,
1316 struct mv88e6xxx_vtu_stu_entry *entry)
1321 ret = _mv88e6xxx_vtu_wait(ds);
1328 /* Write port member tags */
1329 ret = _mv88e6xxx_vtu_stu_data_write(ds, entry, 0);
1333 if (mv88e6xxx_6097_family(ds) || mv88e6xxx_6165_family(ds) ||
1334 mv88e6xxx_6351_family(ds) || mv88e6xxx_6352_family(ds)) {
1335 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1336 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_SID, reg);
1340 reg = entry->fid & GLOBAL_VTU_FID_MASK;
1341 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_FID, reg);
1346 reg = GLOBAL_VTU_VID_VALID;
1348 reg |= entry->vid & GLOBAL_VTU_VID_MASK;
1349 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1353 return _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_VTU_LOAD_PURGE);
1356 static int _mv88e6xxx_stu_getnext(struct dsa_switch *ds, u8 sid,
1357 struct mv88e6xxx_vtu_stu_entry *entry)
1359 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1362 ret = _mv88e6xxx_vtu_wait(ds);
1366 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_SID,
1367 sid & GLOBAL_VTU_SID_MASK);
1371 ret = _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_STU_GET_NEXT);
1375 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_VTU_SID);
1379 next.sid = ret & GLOBAL_VTU_SID_MASK;
1381 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_VTU_VID);
1385 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1388 ret = _mv88e6xxx_vtu_stu_data_read(ds, &next, 2);
1397 static int _mv88e6xxx_stu_loadpurge(struct dsa_switch *ds,
1398 struct mv88e6xxx_vtu_stu_entry *entry)
1403 ret = _mv88e6xxx_vtu_wait(ds);
1410 /* Write port states */
1411 ret = _mv88e6xxx_vtu_stu_data_write(ds, entry, 2);
1415 reg = GLOBAL_VTU_VID_VALID;
1417 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1421 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1422 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_SID, reg);
1426 return _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_STU_LOAD_PURGE);
1429 static int _mv88e6xxx_vlan_init(struct dsa_switch *ds, u16 vid,
1430 struct mv88e6xxx_vtu_stu_entry *entry)
1432 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1433 struct mv88e6xxx_vtu_stu_entry vlan = {
1436 .fid = vid, /* We use one FID per VLAN */
1440 /* exclude all ports except the CPU */
1441 for (i = 0; i < ps->num_ports; ++i)
1442 vlan.data[i] = dsa_is_cpu_port(ds, i) ?
1443 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED :
1444 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1446 if (mv88e6xxx_6097_family(ds) || mv88e6xxx_6165_family(ds) ||
1447 mv88e6xxx_6351_family(ds) || mv88e6xxx_6352_family(ds)) {
1448 struct mv88e6xxx_vtu_stu_entry vstp;
1451 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1452 * implemented, only one STU entry is needed to cover all VTU
1453 * entries. Thus, validate the SID 0.
1456 err = _mv88e6xxx_stu_getnext(ds, GLOBAL_VTU_SID_MASK, &vstp);
1460 if (vstp.sid != vlan.sid || !vstp.valid) {
1461 memset(&vstp, 0, sizeof(vstp));
1463 vstp.sid = vlan.sid;
1465 err = _mv88e6xxx_stu_loadpurge(ds, &vstp);
1470 /* Clear all MAC addresses from the new database */
1471 err = _mv88e6xxx_atu_flush(ds, vlan.fid, true);
1480 int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, u16 vid,
1483 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1484 struct mv88e6xxx_vtu_stu_entry vlan;
1487 mutex_lock(&ps->smi_mutex);
1488 err = _mv88e6xxx_vtu_getnext(ds, vid - 1, &vlan);
1492 if (vlan.vid != vid || !vlan.valid) {
1493 err = _mv88e6xxx_vlan_init(ds, vid, &vlan);
1498 vlan.data[port] = untagged ?
1499 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
1500 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
1502 err = _mv88e6xxx_vtu_loadpurge(ds, &vlan);
1504 mutex_unlock(&ps->smi_mutex);
1509 int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, u16 vid)
1511 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1512 struct mv88e6xxx_vtu_stu_entry vlan;
1515 mutex_lock(&ps->smi_mutex);
1517 err = _mv88e6xxx_vtu_getnext(ds, vid - 1, &vlan);
1521 if (vlan.vid != vid || !vlan.valid ||
1522 vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
1527 vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1529 /* keep the VLAN unless all ports are excluded */
1531 for (i = 0; i < ps->num_ports; ++i) {
1532 if (dsa_is_cpu_port(ds, i))
1535 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
1541 err = _mv88e6xxx_vtu_loadpurge(ds, &vlan);
1545 err = _mv88e6xxx_atu_remove(ds, vlan.fid, port, false);
1547 mutex_unlock(&ps->smi_mutex);
1552 static int _mv88e6xxx_port_vtu_getnext(struct dsa_switch *ds, int port, u16 vid,
1553 struct mv88e6xxx_vtu_stu_entry *entry)
1561 err = _mv88e6xxx_vtu_getnext(ds, vid, entry);
1569 } while (entry->data[port] != GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED &&
1570 entry->data[port] != GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED);
1575 int mv88e6xxx_vlan_getnext(struct dsa_switch *ds, u16 *vid,
1576 unsigned long *ports, unsigned long *untagged)
1578 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1579 struct mv88e6xxx_vtu_stu_entry next;
1586 mutex_lock(&ps->smi_mutex);
1587 err = _mv88e6xxx_vtu_getnext(ds, *vid, &next);
1588 mutex_unlock(&ps->smi_mutex);
1598 for (port = 0; port < ps->num_ports; ++port) {
1599 clear_bit(port, ports);
1600 clear_bit(port, untagged);
1602 if (dsa_is_cpu_port(ds, port))
1605 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED ||
1606 next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1607 set_bit(port, ports);
1609 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1610 set_bit(port, untagged);
1616 static int _mv88e6xxx_atu_mac_write(struct dsa_switch *ds,
1617 const unsigned char *addr)
1621 for (i = 0; i < 3; i++) {
1622 ret = _mv88e6xxx_reg_write(
1623 ds, REG_GLOBAL, GLOBAL_ATU_MAC_01 + i,
1624 (addr[i * 2] << 8) | addr[i * 2 + 1]);
1632 static int _mv88e6xxx_atu_mac_read(struct dsa_switch *ds, unsigned char *addr)
1636 for (i = 0; i < 3; i++) {
1637 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1638 GLOBAL_ATU_MAC_01 + i);
1641 addr[i * 2] = ret >> 8;
1642 addr[i * 2 + 1] = ret & 0xff;
1648 static int _mv88e6xxx_atu_load(struct dsa_switch *ds,
1649 struct mv88e6xxx_atu_entry *entry)
1653 ret = _mv88e6xxx_atu_wait(ds);
1657 ret = _mv88e6xxx_atu_mac_write(ds, entry->mac);
1661 ret = _mv88e6xxx_atu_data_write(ds, entry);
1665 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_FID, entry->fid);
1669 return _mv88e6xxx_atu_cmd(ds, GLOBAL_ATU_OP_LOAD_DB);
1672 static int _mv88e6xxx_port_fdb_load(struct dsa_switch *ds, int port,
1673 const unsigned char *addr, u16 vid,
1676 struct mv88e6xxx_atu_entry entry = { 0 };
1678 entry.fid = vid; /* We use one FID per VLAN */
1679 entry.state = state;
1680 ether_addr_copy(entry.mac, addr);
1681 if (state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1682 entry.trunk = false;
1683 entry.portv_trunkid = BIT(port);
1686 return _mv88e6xxx_atu_load(ds, &entry);
1689 int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
1690 const struct switchdev_obj_port_fdb *fdb,
1691 struct switchdev_trans *trans)
1693 /* We don't use per-port FDB */
1697 /* We don't need any dynamic resource from the kernel (yet),
1698 * so skip the prepare phase.
1703 int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
1704 const struct switchdev_obj_port_fdb *fdb,
1705 struct switchdev_trans *trans)
1707 int state = is_multicast_ether_addr(fdb->addr) ?
1708 GLOBAL_ATU_DATA_STATE_MC_STATIC :
1709 GLOBAL_ATU_DATA_STATE_UC_STATIC;
1710 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1713 mutex_lock(&ps->smi_mutex);
1714 ret = _mv88e6xxx_port_fdb_load(ds, port, fdb->addr, fdb->vid, state);
1715 mutex_unlock(&ps->smi_mutex);
1720 int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
1721 const struct switchdev_obj_port_fdb *fdb)
1723 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1726 mutex_lock(&ps->smi_mutex);
1727 ret = _mv88e6xxx_port_fdb_load(ds, port, fdb->addr, fdb->vid,
1728 GLOBAL_ATU_DATA_STATE_UNUSED);
1729 mutex_unlock(&ps->smi_mutex);
1734 static int _mv88e6xxx_atu_getnext(struct dsa_switch *ds, u16 fid,
1735 const unsigned char *addr,
1736 struct mv88e6xxx_atu_entry *entry)
1738 struct mv88e6xxx_atu_entry next = { 0 };
1743 ret = _mv88e6xxx_atu_wait(ds);
1747 ret = _mv88e6xxx_atu_mac_write(ds, addr);
1751 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_FID, fid);
1755 ret = _mv88e6xxx_atu_cmd(ds, GLOBAL_ATU_OP_GET_NEXT_DB);
1759 ret = _mv88e6xxx_atu_mac_read(ds, next.mac);
1763 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_ATU_DATA);
1767 next.state = ret & GLOBAL_ATU_DATA_STATE_MASK;
1768 if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1769 unsigned int mask, shift;
1771 if (ret & GLOBAL_ATU_DATA_TRUNK) {
1773 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
1774 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
1777 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
1778 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
1781 next.portv_trunkid = (ret & mask) >> shift;
1788 /* get next entry for port */
1789 int mv88e6xxx_port_fdb_getnext(struct dsa_switch *ds, int port,
1790 unsigned char *addr, u16 *vid, bool *is_static)
1792 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1793 struct mv88e6xxx_atu_entry next;
1794 u16 fid = *vid; /* We use one FID per VLAN */
1797 mutex_lock(&ps->smi_mutex);
1800 if (is_broadcast_ether_addr(addr)) {
1801 struct mv88e6xxx_vtu_stu_entry vtu;
1803 ret = _mv88e6xxx_port_vtu_getnext(ds, port, *vid, &vtu);
1811 ret = _mv88e6xxx_atu_getnext(ds, fid, addr, &next);
1815 ether_addr_copy(addr, next.mac);
1817 if (next.state == GLOBAL_ATU_DATA_STATE_UNUSED)
1819 } while (next.trunk || (next.portv_trunkid & BIT(port)) == 0);
1821 *is_static = next.state == (is_multicast_ether_addr(addr) ?
1822 GLOBAL_ATU_DATA_STATE_MC_STATIC :
1823 GLOBAL_ATU_DATA_STATE_UC_STATIC);
1825 mutex_unlock(&ps->smi_mutex);
1830 static void mv88e6xxx_bridge_work(struct work_struct *work)
1832 struct mv88e6xxx_priv_state *ps;
1833 struct dsa_switch *ds;
1836 ps = container_of(work, struct mv88e6xxx_priv_state, bridge_work);
1837 ds = ((struct dsa_switch *)ps) - 1;
1839 while (ps->port_state_update_mask) {
1840 port = __ffs(ps->port_state_update_mask);
1841 clear_bit(port, &ps->port_state_update_mask);
1842 mv88e6xxx_set_port_state(ds, port, ps->port_state[port]);
1846 static int mv88e6xxx_setup_port(struct dsa_switch *ds, int port)
1848 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1852 mutex_lock(&ps->smi_mutex);
1854 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1855 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1856 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
1857 mv88e6xxx_6065_family(ds) || mv88e6xxx_6320_family(ds)) {
1858 /* MAC Forcing register: don't force link, speed,
1859 * duplex or flow control state to any particular
1860 * values on physical ports, but force the CPU port
1861 * and all DSA ports to their maximum bandwidth and
1864 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_PCS_CTRL);
1865 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
1866 reg &= ~PORT_PCS_CTRL_UNFORCED;
1867 reg |= PORT_PCS_CTRL_FORCE_LINK |
1868 PORT_PCS_CTRL_LINK_UP |
1869 PORT_PCS_CTRL_DUPLEX_FULL |
1870 PORT_PCS_CTRL_FORCE_DUPLEX;
1871 if (mv88e6xxx_6065_family(ds))
1872 reg |= PORT_PCS_CTRL_100;
1874 reg |= PORT_PCS_CTRL_1000;
1876 reg |= PORT_PCS_CTRL_UNFORCED;
1879 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1880 PORT_PCS_CTRL, reg);
1885 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
1886 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
1887 * tunneling, determine priority by looking at 802.1p and IP
1888 * priority fields (IP prio has precedence), and set STP state
1891 * If this is the CPU link, use DSA or EDSA tagging depending
1892 * on which tagging mode was configured.
1894 * If this is a link to another switch, use DSA tagging mode.
1896 * If this is the upstream port for this switch, enable
1897 * forwarding of unknown unicasts and multicasts.
1900 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1901 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1902 mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) ||
1903 mv88e6xxx_6185_family(ds) || mv88e6xxx_6320_family(ds))
1904 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
1905 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
1906 PORT_CONTROL_STATE_FORWARDING;
1907 if (dsa_is_cpu_port(ds, port)) {
1908 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds))
1909 reg |= PORT_CONTROL_DSA_TAG;
1910 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1911 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1912 mv88e6xxx_6320_family(ds)) {
1913 if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)
1914 reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA;
1916 reg |= PORT_CONTROL_FRAME_MODE_DSA;
1917 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
1918 PORT_CONTROL_FORWARD_UNKNOWN_MC;
1921 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1922 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1923 mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) ||
1924 mv88e6xxx_6185_family(ds) || mv88e6xxx_6320_family(ds)) {
1925 if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)
1926 reg |= PORT_CONTROL_EGRESS_ADD_TAG;
1929 if (dsa_is_dsa_port(ds, port)) {
1930 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds))
1931 reg |= PORT_CONTROL_DSA_TAG;
1932 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1933 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1934 mv88e6xxx_6320_family(ds)) {
1935 reg |= PORT_CONTROL_FRAME_MODE_DSA;
1938 if (port == dsa_upstream_port(ds))
1939 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
1940 PORT_CONTROL_FORWARD_UNKNOWN_MC;
1943 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1949 /* Port Control 2: don't force a good FCS, set the maximum frame size to
1950 * 10240 bytes, enable secure 802.1q tags, don't discard tagged or
1951 * untagged frames on this port, do a destination address lookup on all
1952 * received packets as usual, disable ARP mirroring and don't send a
1953 * copy of all transmitted/received frames on this port to the CPU.
1956 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1957 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
1958 mv88e6xxx_6095_family(ds) || mv88e6xxx_6320_family(ds))
1959 reg = PORT_CONTROL_2_MAP_DA;
1961 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
1962 mv88e6xxx_6165_family(ds) || mv88e6xxx_6320_family(ds))
1963 reg |= PORT_CONTROL_2_JUMBO_10240;
1965 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds)) {
1966 /* Set the upstream port this port should use */
1967 reg |= dsa_upstream_port(ds);
1968 /* enable forwarding of unknown multicast addresses to
1971 if (port == dsa_upstream_port(ds))
1972 reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
1975 reg |= PORT_CONTROL_2_8021Q_SECURE;
1978 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1979 PORT_CONTROL_2, reg);
1984 /* Port Association Vector: when learning source addresses
1985 * of packets, add the address to the address database using
1986 * a port bitmap that has only the bit for this port set and
1987 * the other bits clear.
1989 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_ASSOC_VECTOR,
1994 /* Egress rate control 2: disable egress rate control. */
1995 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_RATE_CONTROL_2,
2000 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2001 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2002 mv88e6xxx_6320_family(ds)) {
2003 /* Do not limit the period of time that this port can
2004 * be paused for by the remote end or the period of
2005 * time that this port can pause the remote end.
2007 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2008 PORT_PAUSE_CTRL, 0x0000);
2012 /* Port ATU control: disable limiting the number of
2013 * address database entries that this port is allowed
2016 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2017 PORT_ATU_CONTROL, 0x0000);
2018 /* Priority Override: disable DA, SA and VTU priority
2021 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2022 PORT_PRI_OVERRIDE, 0x0000);
2026 /* Port Ethertype: use the Ethertype DSA Ethertype
2029 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2030 PORT_ETH_TYPE, ETH_P_EDSA);
2033 /* Tag Remap: use an identity 802.1p prio -> switch
2036 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2037 PORT_TAG_REGMAP_0123, 0x3210);
2041 /* Tag Remap 2: use an identity 802.1p prio -> switch
2044 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2045 PORT_TAG_REGMAP_4567, 0x7654);
2050 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2051 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2052 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
2053 mv88e6xxx_6320_family(ds)) {
2054 /* Rate Control: disable ingress rate limiting. */
2055 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2056 PORT_RATE_CONTROL, 0x0001);
2061 /* Port Control 1: disable trunking, disable sending
2062 * learning messages to this port.
2064 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL_1, 0x0000);
2068 /* Port based VLAN map: do not give each port its own address
2069 * database, and allow every port to egress frames on all other ports.
2071 reg = BIT(ps->num_ports) - 1; /* all ports */
2072 ret = _mv88e6xxx_port_vlan_map_set(ds, port, reg & ~port);
2076 /* Default VLAN ID and priority: don't set a default VLAN
2077 * ID, and set the default packet priority to zero.
2079 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_DEFAULT_VLAN,
2082 mutex_unlock(&ps->smi_mutex);
2086 int mv88e6xxx_setup_ports(struct dsa_switch *ds)
2088 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2092 for (i = 0; i < ps->num_ports; i++) {
2093 ret = mv88e6xxx_setup_port(ds, i);
2100 static int mv88e6xxx_regs_show(struct seq_file *s, void *p)
2102 struct dsa_switch *ds = s->private;
2104 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2107 seq_puts(s, " GLOBAL GLOBAL2 ");
2108 for (port = 0 ; port < ps->num_ports; port++)
2109 seq_printf(s, " %2d ", port);
2112 for (reg = 0; reg < 32; reg++) {
2113 seq_printf(s, "%2x: ", reg);
2114 seq_printf(s, " %4x %4x ",
2115 mv88e6xxx_reg_read(ds, REG_GLOBAL, reg),
2116 mv88e6xxx_reg_read(ds, REG_GLOBAL2, reg));
2118 for (port = 0 ; port < ps->num_ports; port++)
2119 seq_printf(s, "%4x ",
2120 mv88e6xxx_reg_read(ds, REG_PORT(port), reg));
2127 static int mv88e6xxx_regs_open(struct inode *inode, struct file *file)
2129 return single_open(file, mv88e6xxx_regs_show, inode->i_private);
2132 static const struct file_operations mv88e6xxx_regs_fops = {
2133 .open = mv88e6xxx_regs_open,
2135 .llseek = no_llseek,
2136 .release = single_release,
2137 .owner = THIS_MODULE,
2140 static void mv88e6xxx_atu_show_header(struct seq_file *s)
2142 seq_puts(s, "DB T/P Vec State Addr\n");
2145 static void mv88e6xxx_atu_show_entry(struct seq_file *s, int dbnum,
2146 unsigned char *addr, int data)
2148 bool trunk = !!(data & GLOBAL_ATU_DATA_TRUNK);
2149 int portvec = ((data & GLOBAL_ATU_DATA_PORT_VECTOR_MASK) >>
2150 GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT);
2151 int state = data & GLOBAL_ATU_DATA_STATE_MASK;
2153 seq_printf(s, "%03x %5s %10pb %x %pM\n",
2154 dbnum, (trunk ? "Trunk" : "Port"), &portvec, state, addr);
2157 static int mv88e6xxx_atu_show_db(struct seq_file *s, struct dsa_switch *ds,
2160 unsigned char bcast[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
2161 unsigned char addr[6];
2162 int ret, data, state;
2164 ret = _mv88e6xxx_atu_mac_write(ds, bcast);
2169 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_FID,
2174 ret = _mv88e6xxx_atu_cmd(ds, GLOBAL_ATU_OP_GET_NEXT_DB);
2178 data = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_ATU_DATA);
2182 state = data & GLOBAL_ATU_DATA_STATE_MASK;
2183 if (state == GLOBAL_ATU_DATA_STATE_UNUSED)
2185 ret = _mv88e6xxx_atu_mac_read(ds, addr);
2188 mv88e6xxx_atu_show_entry(s, dbnum, addr, data);
2189 } while (state != GLOBAL_ATU_DATA_STATE_UNUSED);
2194 static int mv88e6xxx_atu_show(struct seq_file *s, void *p)
2196 struct dsa_switch *ds = s->private;
2197 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2200 mv88e6xxx_atu_show_header(s);
2202 for (dbnum = 0; dbnum < 255; dbnum++) {
2203 mutex_lock(&ps->smi_mutex);
2204 mv88e6xxx_atu_show_db(s, ds, dbnum);
2205 mutex_unlock(&ps->smi_mutex);
2211 static int mv88e6xxx_atu_open(struct inode *inode, struct file *file)
2213 return single_open(file, mv88e6xxx_atu_show, inode->i_private);
2216 static const struct file_operations mv88e6xxx_atu_fops = {
2217 .open = mv88e6xxx_atu_open,
2219 .llseek = no_llseek,
2220 .release = single_release,
2221 .owner = THIS_MODULE,
2224 static void mv88e6xxx_stats_show_header(struct seq_file *s,
2225 struct mv88e6xxx_priv_state *ps)
2229 seq_puts(s, " Statistic ");
2230 for (port = 0 ; port < ps->num_ports; port++)
2231 seq_printf(s, "Port %2d ", port);
2235 static int mv88e6xxx_stats_show(struct seq_file *s, void *p)
2237 struct dsa_switch *ds = s->private;
2238 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2239 struct mv88e6xxx_hw_stat *stats = mv88e6xxx_hw_stats;
2240 int port, stat, max_stats;
2243 if (have_sw_in_discards(ds))
2244 max_stats = ARRAY_SIZE(mv88e6xxx_hw_stats);
2246 max_stats = ARRAY_SIZE(mv88e6xxx_hw_stats) - 3;
2248 mv88e6xxx_stats_show_header(s, ps);
2250 mutex_lock(&ps->smi_mutex);
2252 for (stat = 0; stat < max_stats; stat++) {
2253 seq_printf(s, "%19s: ", stats[stat].string);
2254 for (port = 0 ; port < ps->num_ports; port++) {
2255 _mv88e6xxx_stats_snapshot(ds, port);
2256 value = _mv88e6xxx_get_ethtool_stat(ds, stat, stats,
2258 seq_printf(s, "%8llu ", value);
2262 mutex_unlock(&ps->smi_mutex);
2267 static int mv88e6xxx_stats_open(struct inode *inode, struct file *file)
2269 return single_open(file, mv88e6xxx_stats_show, inode->i_private);
2272 static const struct file_operations mv88e6xxx_stats_fops = {
2273 .open = mv88e6xxx_stats_open,
2275 .llseek = no_llseek,
2276 .release = single_release,
2277 .owner = THIS_MODULE,
2280 static int mv88e6xxx_device_map_show(struct seq_file *s, void *p)
2282 struct dsa_switch *ds = s->private;
2283 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2286 seq_puts(s, "Target Port\n");
2288 mutex_lock(&ps->smi_mutex);
2289 for (target = 0; target < 32; target++) {
2290 ret = _mv88e6xxx_reg_write(
2291 ds, REG_GLOBAL2, GLOBAL2_DEVICE_MAPPING,
2292 target << GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT);
2295 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL2,
2296 GLOBAL2_DEVICE_MAPPING);
2297 seq_printf(s, " %2d %2d\n", target,
2298 ret & GLOBAL2_DEVICE_MAPPING_PORT_MASK);
2301 mutex_unlock(&ps->smi_mutex);
2306 static int mv88e6xxx_device_map_open(struct inode *inode, struct file *file)
2308 return single_open(file, mv88e6xxx_device_map_show, inode->i_private);
2311 static const struct file_operations mv88e6xxx_device_map_fops = {
2312 .open = mv88e6xxx_device_map_open,
2314 .llseek = no_llseek,
2315 .release = single_release,
2316 .owner = THIS_MODULE,
2319 static int mv88e6xxx_scratch_show(struct seq_file *s, void *p)
2321 struct dsa_switch *ds = s->private;
2322 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2325 seq_puts(s, "Register Value\n");
2327 mutex_lock(&ps->smi_mutex);
2328 for (reg = 0; reg < 0x80; reg++) {
2329 ret = _mv88e6xxx_reg_write(
2330 ds, REG_GLOBAL2, GLOBAL2_SCRATCH_MISC,
2331 reg << GLOBAL2_SCRATCH_REGISTER_SHIFT);
2335 ret = _mv88e6xxx_scratch_wait(ds);
2339 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL2,
2340 GLOBAL2_SCRATCH_MISC);
2341 seq_printf(s, " %2x %2x\n", reg,
2342 ret & GLOBAL2_SCRATCH_VALUE_MASK);
2345 mutex_unlock(&ps->smi_mutex);
2350 static int mv88e6xxx_scratch_open(struct inode *inode, struct file *file)
2352 return single_open(file, mv88e6xxx_scratch_show, inode->i_private);
2355 static const struct file_operations mv88e6xxx_scratch_fops = {
2356 .open = mv88e6xxx_scratch_open,
2358 .llseek = no_llseek,
2359 .release = single_release,
2360 .owner = THIS_MODULE,
2363 int mv88e6xxx_setup_common(struct dsa_switch *ds)
2365 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2368 mutex_init(&ps->smi_mutex);
2370 ps->id = REG_READ(REG_PORT(0), PORT_SWITCH_ID) & 0xfff0;
2372 INIT_WORK(&ps->bridge_work, mv88e6xxx_bridge_work);
2374 name = kasprintf(GFP_KERNEL, "dsa%d", ds->index);
2375 ps->dbgfs = debugfs_create_dir(name, NULL);
2378 debugfs_create_file("regs", S_IRUGO, ps->dbgfs, ds,
2379 &mv88e6xxx_regs_fops);
2381 debugfs_create_file("atu", S_IRUGO, ps->dbgfs, ds,
2382 &mv88e6xxx_atu_fops);
2384 debugfs_create_file("stats", S_IRUGO, ps->dbgfs, ds,
2385 &mv88e6xxx_stats_fops);
2387 debugfs_create_file("device_map", S_IRUGO, ps->dbgfs, ds,
2388 &mv88e6xxx_device_map_fops);
2390 debugfs_create_file("scratch", S_IRUGO, ps->dbgfs, ds,
2391 &mv88e6xxx_scratch_fops);
2395 int mv88e6xxx_setup_global(struct dsa_switch *ds)
2397 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2401 /* Set the default address aging time to 5 minutes, and
2402 * enable address learn messages to be sent to all message
2405 REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL,
2406 0x0140 | GLOBAL_ATU_CONTROL_LEARN2ALL);
2408 /* Configure the IP ToS mapping registers. */
2409 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000);
2410 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000);
2411 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555);
2412 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555);
2413 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa);
2414 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa);
2415 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff);
2416 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff);
2418 /* Configure the IEEE 802.1p priority mapping register. */
2419 REG_WRITE(REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41);
2421 /* Send all frames with destination addresses matching
2422 * 01:80:c2:00:00:0x to the CPU port.
2424 REG_WRITE(REG_GLOBAL2, GLOBAL2_MGMT_EN_0X, 0xffff);
2426 /* Ignore removed tag data on doubly tagged packets, disable
2427 * flow control messages, force flow control priority to the
2428 * highest, and send all special multicast frames to the CPU
2429 * port at the highest priority.
2431 REG_WRITE(REG_GLOBAL2, GLOBAL2_SWITCH_MGMT,
2432 0x7 | GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x70 |
2433 GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI);
2435 /* Program the DSA routing table. */
2436 for (i = 0; i < 32; i++) {
2439 if (ds->pd->rtable &&
2440 i != ds->index && i < ds->dst->pd->nr_chips)
2441 nexthop = ds->pd->rtable[i] & 0x1f;
2443 REG_WRITE(REG_GLOBAL2, GLOBAL2_DEVICE_MAPPING,
2444 GLOBAL2_DEVICE_MAPPING_UPDATE |
2445 (i << GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT) |
2449 /* Clear all trunk masks. */
2450 for (i = 0; i < 8; i++)
2451 REG_WRITE(REG_GLOBAL2, GLOBAL2_TRUNK_MASK,
2452 0x8000 | (i << GLOBAL2_TRUNK_MASK_NUM_SHIFT) |
2453 ((1 << ps->num_ports) - 1));
2455 /* Clear all trunk mappings. */
2456 for (i = 0; i < 16; i++)
2457 REG_WRITE(REG_GLOBAL2, GLOBAL2_TRUNK_MAPPING,
2458 GLOBAL2_TRUNK_MAPPING_UPDATE |
2459 (i << GLOBAL2_TRUNK_MAPPING_ID_SHIFT));
2461 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2462 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2463 mv88e6xxx_6320_family(ds)) {
2464 /* Send all frames with destination addresses matching
2465 * 01:80:c2:00:00:2x to the CPU port.
2467 REG_WRITE(REG_GLOBAL2, GLOBAL2_MGMT_EN_2X, 0xffff);
2469 /* Initialise cross-chip port VLAN table to reset
2472 REG_WRITE(REG_GLOBAL2, GLOBAL2_PVT_ADDR, 0x9000);
2474 /* Clear the priority override table. */
2475 for (i = 0; i < 16; i++)
2476 REG_WRITE(REG_GLOBAL2, GLOBAL2_PRIO_OVERRIDE,
2480 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2481 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2482 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
2483 mv88e6xxx_6320_family(ds)) {
2484 /* Disable ingress rate limiting by resetting all
2485 * ingress rate limit registers to their initial
2488 for (i = 0; i < ps->num_ports; i++)
2489 REG_WRITE(REG_GLOBAL2, GLOBAL2_INGRESS_OP,
2493 /* Clear the statistics counters for all ports */
2494 REG_WRITE(REG_GLOBAL, GLOBAL_STATS_OP, GLOBAL_STATS_OP_FLUSH_ALL);
2496 /* Wait for the flush to complete. */
2497 mutex_lock(&ps->smi_mutex);
2498 ret = _mv88e6xxx_stats_wait(ds);
2502 /* Clear all ATU entries */
2503 ret = _mv88e6xxx_atu_flush(ds, 0, true);
2507 /* Clear all the VTU and STU entries */
2508 ret = _mv88e6xxx_vtu_stu_flush(ds);
2510 mutex_unlock(&ps->smi_mutex);
2515 int mv88e6xxx_switch_reset(struct dsa_switch *ds, bool ppu_active)
2517 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2518 u16 is_reset = (ppu_active ? 0x8800 : 0xc800);
2519 unsigned long timeout;
2523 /* Set all ports to the disabled state. */
2524 for (i = 0; i < ps->num_ports; i++) {
2525 ret = REG_READ(REG_PORT(i), PORT_CONTROL);
2526 REG_WRITE(REG_PORT(i), PORT_CONTROL, ret & 0xfffc);
2529 /* Wait for transmit queues to drain. */
2530 usleep_range(2000, 4000);
2532 /* Reset the switch. Keep the PPU active if requested. The PPU
2533 * needs to be active to support indirect phy register access
2534 * through global registers 0x18 and 0x19.
2537 REG_WRITE(REG_GLOBAL, 0x04, 0xc000);
2539 REG_WRITE(REG_GLOBAL, 0x04, 0xc400);
2541 /* Wait up to one second for reset to complete. */
2542 timeout = jiffies + 1 * HZ;
2543 while (time_before(jiffies, timeout)) {
2544 ret = REG_READ(REG_GLOBAL, 0x00);
2545 if ((ret & is_reset) == is_reset)
2547 usleep_range(1000, 2000);
2549 if (time_after(jiffies, timeout))
2555 int mv88e6xxx_phy_page_read(struct dsa_switch *ds, int port, int page, int reg)
2557 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2560 mutex_lock(&ps->smi_mutex);
2561 ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page);
2564 ret = _mv88e6xxx_phy_read_indirect(ds, port, reg);
2566 _mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0);
2567 mutex_unlock(&ps->smi_mutex);
2571 int mv88e6xxx_phy_page_write(struct dsa_switch *ds, int port, int page,
2574 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2577 mutex_lock(&ps->smi_mutex);
2578 ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page);
2582 ret = _mv88e6xxx_phy_write_indirect(ds, port, reg, val);
2584 _mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0);
2585 mutex_unlock(&ps->smi_mutex);
2589 static int mv88e6xxx_port_to_phy_addr(struct dsa_switch *ds, int port)
2591 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2593 if (port >= 0 && port < ps->num_ports)
2599 mv88e6xxx_phy_read(struct dsa_switch *ds, int port, int regnum)
2601 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2602 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2608 mutex_lock(&ps->smi_mutex);
2609 ret = _mv88e6xxx_phy_read(ds, addr, regnum);
2610 mutex_unlock(&ps->smi_mutex);
2615 mv88e6xxx_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
2617 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2618 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2624 mutex_lock(&ps->smi_mutex);
2625 ret = _mv88e6xxx_phy_write(ds, addr, regnum, val);
2626 mutex_unlock(&ps->smi_mutex);
2631 mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int port, int regnum)
2633 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2634 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2640 mutex_lock(&ps->smi_mutex);
2641 ret = _mv88e6xxx_phy_read_indirect(ds, addr, regnum);
2642 mutex_unlock(&ps->smi_mutex);
2647 mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int port, int regnum,
2650 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2651 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2657 mutex_lock(&ps->smi_mutex);
2658 ret = _mv88e6xxx_phy_write_indirect(ds, addr, regnum, val);
2659 mutex_unlock(&ps->smi_mutex);
2663 #ifdef CONFIG_NET_DSA_HWMON
2665 static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp)
2667 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2673 mutex_lock(&ps->smi_mutex);
2675 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x6);
2679 /* Enable temperature sensor */
2680 ret = _mv88e6xxx_phy_read(ds, 0x0, 0x1a);
2684 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret | (1 << 5));
2688 /* Wait for temperature to stabilize */
2689 usleep_range(10000, 12000);
2691 val = _mv88e6xxx_phy_read(ds, 0x0, 0x1a);
2697 /* Disable temperature sensor */
2698 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret & ~(1 << 5));
2702 *temp = ((val & 0x1f) - 5) * 5;
2705 _mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x0);
2706 mutex_unlock(&ps->smi_mutex);
2710 static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp)
2712 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
2717 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 27);
2721 *temp = (ret & 0xff) - 25;
2726 int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
2728 if (mv88e6xxx_6320_family(ds) || mv88e6xxx_6352_family(ds))
2729 return mv88e63xx_get_temp(ds, temp);
2731 return mv88e61xx_get_temp(ds, temp);
2734 int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp)
2736 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
2739 if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds))
2744 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
2748 *temp = (((ret >> 8) & 0x1f) * 5) - 25;
2753 int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp)
2755 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
2758 if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds))
2761 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
2764 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
2765 return mv88e6xxx_phy_page_write(ds, phy, 6, 26,
2766 (ret & 0xe0ff) | (temp << 8));
2769 int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm)
2771 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
2774 if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds))
2779 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
2783 *alarm = !!(ret & 0x40);
2787 #endif /* CONFIG_NET_DSA_HWMON */
2789 static int __init mv88e6xxx_init(void)
2791 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
2792 register_switch_driver(&mv88e6131_switch_driver);
2794 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65)
2795 register_switch_driver(&mv88e6123_61_65_switch_driver);
2797 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
2798 register_switch_driver(&mv88e6352_switch_driver);
2800 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
2801 register_switch_driver(&mv88e6171_switch_driver);
2805 module_init(mv88e6xxx_init);
2807 static void __exit mv88e6xxx_cleanup(void)
2809 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
2810 unregister_switch_driver(&mv88e6171_switch_driver);
2812 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
2813 unregister_switch_driver(&mv88e6352_switch_driver);
2815 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65)
2816 unregister_switch_driver(&mv88e6123_61_65_switch_driver);
2818 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
2819 unregister_switch_driver(&mv88e6131_switch_driver);
2822 module_exit(mv88e6xxx_cleanup);
2824 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
2825 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
2826 MODULE_LICENSE("GPL");