2 * net/dsa/mv88e6xxx.h - Marvell 88e6xxx switch chip support
3 * Copyright (c) 2008 Marvell Semiconductor
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
15 #define SMI_CMD_BUSY BIT(15)
16 #define SMI_CMD_CLAUSE_22 BIT(12)
17 #define SMI_CMD_OP_22_WRITE ((1 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22)
18 #define SMI_CMD_OP_22_READ ((2 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22)
19 #define SMI_CMD_OP_45_WRITE_ADDR ((0 << 10) | SMI_CMD_BUSY)
20 #define SMI_CMD_OP_45_WRITE_DATA ((1 << 10) | SMI_CMD_BUSY)
21 #define SMI_CMD_OP_45_READ_DATA ((2 << 10) | SMI_CMD_BUSY)
22 #define SMI_CMD_OP_45_READ_DATA_INC ((3 << 10) | SMI_CMD_BUSY)
25 #define REG_PORT(p) (0x10 + (p))
26 #define PORT_STATUS 0x00
27 #define PORT_STATUS_PAUSE_EN BIT(15)
28 #define PORT_STATUS_MY_PAUSE BIT(14)
29 #define PORT_STATUS_HD_FLOW BIT(13)
30 #define PORT_STATUS_PHY_DETECT BIT(12)
31 #define PORT_STATUS_LINK BIT(11)
32 #define PORT_STATUS_DUPLEX BIT(10)
33 #define PORT_STATUS_SPEED_MASK 0x0300
34 #define PORT_STATUS_SPEED_10 0x0000
35 #define PORT_STATUS_SPEED_100 0x0100
36 #define PORT_STATUS_SPEED_1000 0x0200
37 #define PORT_STATUS_EEE BIT(6) /* 6352 */
38 #define PORT_STATUS_AM_DIS BIT(6) /* 6165 */
39 #define PORT_STATUS_MGMII BIT(6) /* 6185 */
40 #define PORT_STATUS_TX_PAUSED BIT(5)
41 #define PORT_STATUS_FLOW_CTRL BIT(4)
42 #define PORT_PCS_CTRL 0x01
43 #define PORT_PCS_CTRL_FC BIT(7)
44 #define PORT_PCS_CTRL_FORCE_FC BIT(6)
45 #define PORT_PCS_CTRL_LINK_UP BIT(5)
46 #define PORT_PCS_CTRL_FORCE_LINK BIT(4)
47 #define PORT_PCS_CTRL_DUPLEX_FULL BIT(3)
48 #define PORT_PCS_CTRL_FORCE_DUPLEX BIT(2)
49 #define PORT_PCS_CTRL_10 0x00
50 #define PORT_PCS_CTRL_100 0x01
51 #define PORT_PCS_CTRL_1000 0x02
52 #define PORT_PCS_CTRL_UNFORCED 0x03
53 #define PORT_PAUSE_CTRL 0x02
54 #define PORT_SWITCH_ID 0x03
55 #define PORT_SWITCH_ID_6031 0x0310
56 #define PORT_SWITCH_ID_6035 0x0350
57 #define PORT_SWITCH_ID_6046 0x0480
58 #define PORT_SWITCH_ID_6061 0x0610
59 #define PORT_SWITCH_ID_6065 0x0650
60 #define PORT_SWITCH_ID_6085 0x04a0
61 #define PORT_SWITCH_ID_6092 0x0970
62 #define PORT_SWITCH_ID_6095 0x0950
63 #define PORT_SWITCH_ID_6096 0x0980
64 #define PORT_SWITCH_ID_6097 0x0990
65 #define PORT_SWITCH_ID_6108 0x1070
66 #define PORT_SWITCH_ID_6121 0x1040
67 #define PORT_SWITCH_ID_6122 0x1050
68 #define PORT_SWITCH_ID_6123 0x1210
69 #define PORT_SWITCH_ID_6123_A1 0x1212
70 #define PORT_SWITCH_ID_6123_A2 0x1213
71 #define PORT_SWITCH_ID_6131 0x1060
72 #define PORT_SWITCH_ID_6131_B2 0x1066
73 #define PORT_SWITCH_ID_6152 0x1a40
74 #define PORT_SWITCH_ID_6155 0x1a50
75 #define PORT_SWITCH_ID_6161 0x1610
76 #define PORT_SWITCH_ID_6161_A1 0x1612
77 #define PORT_SWITCH_ID_6161_A2 0x1613
78 #define PORT_SWITCH_ID_6165 0x1650
79 #define PORT_SWITCH_ID_6165_A1 0x1652
80 #define PORT_SWITCH_ID_6165_A2 0x1653
81 #define PORT_SWITCH_ID_6171 0x1710
82 #define PORT_SWITCH_ID_6172 0x1720
83 #define PORT_SWITCH_ID_6175 0x1750
84 #define PORT_SWITCH_ID_6176 0x1760
85 #define PORT_SWITCH_ID_6182 0x1a60
86 #define PORT_SWITCH_ID_6185 0x1a70
87 #define PORT_SWITCH_ID_6240 0x2400
88 #define PORT_SWITCH_ID_6320 0x1250
89 #define PORT_SWITCH_ID_6350 0x3710
90 #define PORT_SWITCH_ID_6351 0x3750
91 #define PORT_SWITCH_ID_6352 0x3520
92 #define PORT_SWITCH_ID_6352_A0 0x3521
93 #define PORT_SWITCH_ID_6352_A1 0x3522
94 #define PORT_CONTROL 0x04
95 #define PORT_CONTROL_USE_CORE_TAG BIT(15)
96 #define PORT_CONTROL_DROP_ON_LOCK BIT(14)
97 #define PORT_CONTROL_EGRESS_UNMODIFIED (0x0 << 12)
98 #define PORT_CONTROL_EGRESS_UNTAGGED (0x1 << 12)
99 #define PORT_CONTROL_EGRESS_TAGGED (0x2 << 12)
100 #define PORT_CONTROL_EGRESS_ADD_TAG (0x3 << 12)
101 #define PORT_CONTROL_HEADER BIT(11)
102 #define PORT_CONTROL_IGMP_MLD_SNOOP BIT(10)
103 #define PORT_CONTROL_DOUBLE_TAG BIT(9)
104 #define PORT_CONTROL_FRAME_MODE_NORMAL (0x0 << 8)
105 #define PORT_CONTROL_FRAME_MODE_DSA (0x1 << 8)
106 #define PORT_CONTROL_FRAME_MODE_PROVIDER (0x2 << 8)
107 #define PORT_CONTROL_FRAME_ETHER_TYPE_DSA (0x3 << 8)
108 #define PORT_CONTROL_DSA_TAG BIT(8)
109 #define PORT_CONTROL_VLAN_TUNNEL BIT(7)
110 #define PORT_CONTROL_TAG_IF_BOTH BIT(6)
111 #define PORT_CONTROL_USE_IP BIT(5)
112 #define PORT_CONTROL_USE_TAG BIT(4)
113 #define PORT_CONTROL_FORWARD_UNKNOWN_MC BIT(3)
114 #define PORT_CONTROL_FORWARD_UNKNOWN BIT(2)
115 #define PORT_CONTROL_STATE_MASK 0x03
116 #define PORT_CONTROL_STATE_DISABLED 0x00
117 #define PORT_CONTROL_STATE_BLOCKING 0x01
118 #define PORT_CONTROL_STATE_LEARNING 0x02
119 #define PORT_CONTROL_STATE_FORWARDING 0x03
120 #define PORT_CONTROL_1 0x05
121 #define PORT_BASE_VLAN 0x06
122 #define PORT_DEFAULT_VLAN 0x07
123 #define PORT_CONTROL_2 0x08
124 #define PORT_CONTROL_2_IGNORE_FCS BIT(15)
125 #define PORT_CONTROL_2_VTU_PRI_OVERRIDE BIT(14)
126 #define PORT_CONTROL_2_SA_PRIO_OVERRIDE BIT(13)
127 #define PORT_CONTROL_2_DA_PRIO_OVERRIDE BIT(12)
128 #define PORT_CONTROL_2_JUMBO_1522 (0x00 << 12)
129 #define PORT_CONTROL_2_JUMBO_2048 (0x01 << 12)
130 #define PORT_CONTROL_2_JUMBO_10240 (0x02 << 12)
131 #define PORT_CONTROL_2_DISCARD_TAGGED BIT(9)
132 #define PORT_CONTROL_2_DISCARD_UNTAGGED BIT(8)
133 #define PORT_CONTROL_2_MAP_DA BIT(7)
134 #define PORT_CONTROL_2_DEFAULT_FORWARD BIT(6)
135 #define PORT_CONTROL_2_FORWARD_UNKNOWN BIT(6)
136 #define PORT_CONTROL_2_EGRESS_MONITOR BIT(5)
137 #define PORT_CONTROL_2_INGRESS_MONITOR BIT(4)
138 #define PORT_RATE_CONTROL 0x09
139 #define PORT_RATE_CONTROL_2 0x0a
140 #define PORT_ASSOC_VECTOR 0x0b
141 #define PORT_ATU_CONTROL 0x0c
142 #define PORT_PRI_OVERRIDE 0x0d
143 #define PORT_ETH_TYPE 0x0f
144 #define PORT_IN_DISCARD_LO 0x10
145 #define PORT_IN_DISCARD_HI 0x11
146 #define PORT_IN_FILTERED 0x12
147 #define PORT_OUT_FILTERED 0x13
148 #define PORT_TAG_REGMAP_0123 0x18
149 #define PORT_TAG_REGMAP_4567 0x19
151 #define REG_GLOBAL 0x1b
152 #define GLOBAL_STATUS 0x00
153 #define GLOBAL_STATUS_PPU_STATE BIT(15) /* 6351 and 6171 */
154 /* Two bits for 6165, 6185 etc */
155 #define GLOBAL_STATUS_PPU_MASK (0x3 << 14)
156 #define GLOBAL_STATUS_PPU_DISABLED_RST (0x0 << 14)
157 #define GLOBAL_STATUS_PPU_INITIALIZING (0x1 << 14)
158 #define GLOBAL_STATUS_PPU_DISABLED (0x2 << 14)
159 #define GLOBAL_STATUS_PPU_POLLING (0x3 << 14)
160 #define GLOBAL_MAC_01 0x01
161 #define GLOBAL_MAC_23 0x02
162 #define GLOBAL_MAC_45 0x03
163 #define GLOBAL_CONTROL 0x04
164 #define GLOBAL_CONTROL_SW_RESET BIT(15)
165 #define GLOBAL_CONTROL_PPU_ENABLE BIT(14)
166 #define GLOBAL_CONTROL_DISCARD_EXCESS BIT(13) /* 6352 */
167 #define GLOBAL_CONTROL_SCHED_PRIO BIT(11) /* 6152 */
168 #define GLOBAL_CONTROL_MAX_FRAME_1632 BIT(10) /* 6152 */
169 #define GLOBAL_CONTROL_RELOAD_EEPROM BIT(9) /* 6152 */
170 #define GLOBAL_CONTROL_DEVICE_EN BIT(7)
171 #define GLOBAL_CONTROL_STATS_DONE_EN BIT(6)
172 #define GLOBAL_CONTROL_VTU_PROBLEM_EN BIT(5)
173 #define GLOBAL_CONTROL_VTU_DONE_EN BIT(4)
174 #define GLOBAL_CONTROL_ATU_PROBLEM_EN BIT(3)
175 #define GLOBAL_CONTROL_ATU_DONE_EN BIT(2)
176 #define GLOBAL_CONTROL_TCAM_EN BIT(1)
177 #define GLOBAL_CONTROL_EEPROM_DONE_EN BIT(0)
178 #define GLOBAL_VTU_OP 0x05
179 #define GLOBAL_VTU_VID 0x06
180 #define GLOBAL_VTU_DATA_0_3 0x07
181 #define GLOBAL_VTU_DATA_4_7 0x08
182 #define GLOBAL_VTU_DATA_8_11 0x09
183 #define GLOBAL_ATU_CONTROL 0x0a
184 #define GLOBAL_ATU_CONTROL_LEARN2ALL BIT(3)
185 #define GLOBAL_ATU_OP 0x0b
186 #define GLOBAL_ATU_OP_BUSY BIT(15)
187 #define GLOBAL_ATU_OP_NOP (0 << 12)
188 #define GLOBAL_ATU_OP_FLUSH_ALL ((1 << 12) | GLOBAL_ATU_OP_BUSY)
189 #define GLOBAL_ATU_OP_FLUSH_NON_STATIC ((2 << 12) | GLOBAL_ATU_OP_BUSY)
190 #define GLOBAL_ATU_OP_LOAD_DB ((3 << 12) | GLOBAL_ATU_OP_BUSY)
191 #define GLOBAL_ATU_OP_GET_NEXT_DB ((4 << 12) | GLOBAL_ATU_OP_BUSY)
192 #define GLOBAL_ATU_OP_FLUSH_DB ((5 << 12) | GLOBAL_ATU_OP_BUSY)
193 #define GLOBAL_ATU_OP_FLUSH_NON_STATIC_DB ((6 << 12) | GLOBAL_ATU_OP_BUSY)
194 #define GLOBAL_ATU_OP_GET_CLR_VIOLATION ((7 << 12) | GLOBAL_ATU_OP_BUSY)
195 #define GLOBAL_ATU_DATA 0x0c
196 #define GLOBAL_ATU_DATA_TRUNK BIT(15)
197 #define GLOBAL_ATU_DATA_PORT_VECTOR_MASK 0x3ff0
198 #define GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT 4
199 #define GLOBAL_ATU_DATA_STATE_MASK 0x0f
200 #define GLOBAL_ATU_DATA_STATE_UNUSED 0x00
201 #define GLOBAL_ATU_DATA_STATE_UC_MGMT 0x0d
202 #define GLOBAL_ATU_DATA_STATE_UC_STATIC 0x0e
203 #define GLOBAL_ATU_DATA_STATE_UC_PRIO_OVER 0x0f
204 #define GLOBAL_ATU_DATA_STATE_MC_NONE_RATE 0x05
205 #define GLOBAL_ATU_DATA_STATE_MC_STATIC 0x07
206 #define GLOBAL_ATU_DATA_STATE_MC_MGMT 0x0e
207 #define GLOBAL_ATU_DATA_STATE_MC_PRIO_OVER 0x0f
208 #define GLOBAL_ATU_MAC_01 0x0d
209 #define GLOBAL_ATU_MAC_23 0x0e
210 #define GLOBAL_ATU_MAC_45 0x0f
211 #define GLOBAL_IP_PRI_0 0x10
212 #define GLOBAL_IP_PRI_1 0x11
213 #define GLOBAL_IP_PRI_2 0x12
214 #define GLOBAL_IP_PRI_3 0x13
215 #define GLOBAL_IP_PRI_4 0x14
216 #define GLOBAL_IP_PRI_5 0x15
217 #define GLOBAL_IP_PRI_6 0x16
218 #define GLOBAL_IP_PRI_7 0x17
219 #define GLOBAL_IEEE_PRI 0x18
220 #define GLOBAL_CORE_TAG_TYPE 0x19
221 #define GLOBAL_MONITOR_CONTROL 0x1a
222 #define GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT 12
223 #define GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT 8
224 #define GLOBAL_MONITOR_CONTROL_ARP_SHIFT 4
225 #define GLOBAL_MONITOR_CONTROL_MIRROR_SHIFT 0
226 #define GLOBAL_MONITOR_CONTROL_ARP_DISABLED (0xf0)
227 #define GLOBAL_CONTROL_2 0x1c
228 #define GLOBAL_CONTROL_2_NO_CASCADE 0xe000
229 #define GLOBAL_CONTROL_2_MULTIPLE_CASCADE 0xf000
231 #define GLOBAL_STATS_OP 0x1d
232 #define GLOBAL_STATS_OP_BUSY BIT(15)
233 #define GLOBAL_STATS_OP_NOP (0 << 12)
234 #define GLOBAL_STATS_OP_FLUSH_ALL ((1 << 12) | GLOBAL_STATS_OP_BUSY)
235 #define GLOBAL_STATS_OP_FLUSH_PORT ((2 << 12) | GLOBAL_STATS_OP_BUSY)
236 #define GLOBAL_STATS_OP_READ_CAPTURED ((4 << 12) | GLOBAL_STATS_OP_BUSY)
237 #define GLOBAL_STATS_OP_CAPTURE_PORT ((5 << 12) | GLOBAL_STATS_OP_BUSY)
238 #define GLOBAL_STATS_OP_HIST_RX ((1 << 10) | GLOBAL_STATS_OP_BUSY)
239 #define GLOBAL_STATS_OP_HIST_TX ((2 << 10) | GLOBAL_STATS_OP_BUSY)
240 #define GLOBAL_STATS_OP_HIST_RX_TX ((3 << 10) | GLOBAL_STATS_OP_BUSY)
241 #define GLOBAL_STATS_COUNTER_32 0x1e
242 #define GLOBAL_STATS_COUNTER_01 0x1f
244 #define REG_GLOBAL2 0x1c
245 #define GLOBAL2_INT_SOURCE 0x00
246 #define GLOBAL2_INT_MASK 0x01
247 #define GLOBAL2_MGMT_EN_2X 0x02
248 #define GLOBAL2_MGMT_EN_0X 0x03
249 #define GLOBAL2_FLOW_CONTROL 0x04
250 #define GLOBAL2_SWITCH_MGMT 0x05
251 #define GLOBAL2_SWITCH_MGMT_USE_DOUBLE_TAG_DATA BIT(15)
252 #define GLOBAL2_SWITCH_MGMT_PREVENT_LOOPS BIT(14)
253 #define GLOBAL2_SWITCH_MGMT_FLOW_CONTROL_MSG BIT(13)
254 #define GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI BIT(7)
255 #define GLOBAL2_SWITCH_MGMT_RSVD2CPU BIT(3)
256 #define GLOBAL2_DEVICE_MAPPING 0x06
257 #define GLOBAL2_DEVICE_MAPPING_UPDATE BIT(15)
258 #define GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT 8
259 #define GLOBAL2_TRUNK_MASK 0x07
260 #define GLOBAL2_TRUNK_MASK_UPDATE BIT(15)
261 #define GLOBAL2_TRUNK_MASK_NUM_SHIFT 12
262 #define GLOBAL2_TRUNK_MAPPING 0x08
263 #define GLOBAL2_TRUNK_MAPPING_UPDATE BIT(15)
264 #define GLOBAL2_TRUNK_MAPPING_ID_SHIFT 11
265 #define GLOBAL2_INGRESS_OP 0x09
266 #define GLOBAL2_INGRESS_DATA 0x0a
267 #define GLOBAL2_PVT_ADDR 0x0b
268 #define GLOBAL2_PVT_DATA 0x0c
269 #define GLOBAL2_SWITCH_MAC 0x0d
270 #define GLOBAL2_SWITCH_MAC_BUSY BIT(15)
271 #define GLOBAL2_ATU_STATS 0x0e
272 #define GLOBAL2_PRIO_OVERRIDE 0x0f
273 #define GLOBAL2_PRIO_OVERRIDE_FORCE_SNOOP BIT(7)
274 #define GLOBAL2_PRIO_OVERRIDE_SNOOP_SHIFT 4
275 #define GLOBAL2_PRIO_OVERRIDE_FORCE_ARP BIT(3)
276 #define GLOBAL2_PRIO_OVERRIDE_ARP_SHIFT 0
277 #define GLOBAL2_EEPROM_OP 0x14
278 #define GLOBAL2_EEPROM_OP_BUSY BIT(15)
279 #define GLOBAL2_EEPROM_OP_LOAD BIT(11)
280 #define GLOBAL2_EEPROM_DATA 0x15
281 #define GLOBAL2_PTP_AVB_OP 0x16
282 #define GLOBAL2_PTP_AVB_DATA 0x17
283 #define GLOBAL2_SMI_OP 0x18
284 #define GLOBAL2_SMI_OP_BUSY BIT(15)
285 #define GLOBAL2_SMI_OP_CLAUSE_22 BIT(12)
286 #define GLOBAL2_SMI_OP_22_WRITE ((1 << 10) | GLOBAL2_SMI_OP_BUSY | \
287 GLOBAL2_SMI_OP_CLAUSE_22)
288 #define GLOBAL2_SMI_OP_22_READ ((2 << 10) | GLOBAL2_SMI_OP_BUSY | \
289 GLOBAL2_SMI_OP_CLAUSE_22)
290 #define GLOBAL2_SMI_OP_45_WRITE_ADDR ((0 << 10) | GLOBAL2_SMI_OP_BUSY)
291 #define GLOBAL2_SMI_OP_45_WRITE_DATA ((1 << 10) | GLOBAL2_SMI_OP_BUSY)
292 #define GLOBAL2_SMI_OP_45_READ_DATA ((2 << 10) | GLOBAL2_SMI_OP_BUSY)
293 #define GLOBAL2_SMI_DATA 0x19
294 #define GLOBAL2_SCRATCH_MISC 0x1a
295 #define GLOBAL2_WDOG_CONTROL 0x1b
296 #define GLOBAL2_QOS_WEIGHT 0x1c
297 #define GLOBAL2_MISC 0x1d
299 struct mv88e6xxx_priv_state {
300 /* When using multi-chip addressing, this mutex protects
301 * access to the indirect access registers. (In single-chip
302 * mode, this mutex is effectively useless.)
304 struct mutex smi_mutex;
306 #ifdef CONFIG_NET_DSA_MV88E6XXX_NEED_PPU
307 /* Handles automatic disabling and re-enabling of the PHY
310 struct mutex ppu_mutex;
312 struct work_struct ppu_work;
313 struct timer_list ppu_timer;
316 /* This mutex serialises access to the statistics unit.
317 * Hold this mutex over snapshot + dump sequences.
319 struct mutex stats_mutex;
321 /* This mutex serializes phy access for chips with
322 * indirect phy addressing. It is unused for chips
323 * with direct phy access.
325 struct mutex phy_mutex;
327 /* This mutex serializes eeprom access for chips with
330 struct mutex eeprom_mutex;
332 int id; /* switch product id */
333 int num_ports; /* number of switch ports */
338 u8 fid[DSA_MAX_PORTS];
339 u16 bridge_mask[DSA_MAX_PORTS];
341 unsigned long port_state_update_mask;
342 u8 port_state[DSA_MAX_PORTS];
344 struct work_struct bridge_work;
346 struct dentry *dbgfs;
349 struct mv88e6xxx_hw_stat {
350 char string[ETH_GSTRING_LEN];
355 int mv88e6xxx_switch_reset(struct dsa_switch *ds, bool ppu_active);
356 int mv88e6xxx_setup_ports(struct dsa_switch *ds);
357 int mv88e6xxx_setup_common(struct dsa_switch *ds);
358 int mv88e6xxx_setup_global(struct dsa_switch *ds);
359 int __mv88e6xxx_reg_read(struct mii_bus *bus, int sw_addr, int addr, int reg);
360 int mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg);
361 int __mv88e6xxx_reg_write(struct mii_bus *bus, int sw_addr, int addr,
363 int mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg, u16 val);
364 int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr);
365 int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr);
366 int mv88e6xxx_phy_read(struct dsa_switch *ds, int port, int regnum);
367 int mv88e6xxx_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val);
368 int mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int port, int regnum);
369 int mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int port, int regnum,
371 void mv88e6xxx_ppu_state_init(struct dsa_switch *ds);
372 int mv88e6xxx_phy_read_ppu(struct dsa_switch *ds, int addr, int regnum);
373 int mv88e6xxx_phy_write_ppu(struct dsa_switch *ds, int addr,
374 int regnum, u16 val);
375 void mv88e6xxx_poll_link(struct dsa_switch *ds);
376 void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, uint8_t *data);
377 void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
379 int mv88e6xxx_get_sset_count(struct dsa_switch *ds);
380 int mv88e6xxx_get_sset_count_basic(struct dsa_switch *ds);
381 int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port);
382 void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
383 struct ethtool_regs *regs, void *_p);
384 int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp);
385 int mv88e6xxx_eeprom_load_wait(struct dsa_switch *ds);
386 int mv88e6xxx_eeprom_busy_wait(struct dsa_switch *ds);
387 int mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int addr, int regnum);
388 int mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int addr, int regnum,
390 int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e);
391 int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
392 struct phy_device *phydev, struct ethtool_eee *e);
393 int mv88e6xxx_join_bridge(struct dsa_switch *ds, int port, u32 br_port_mask);
394 int mv88e6xxx_leave_bridge(struct dsa_switch *ds, int port, u32 br_port_mask);
395 int mv88e6xxx_port_stp_update(struct dsa_switch *ds, int port, u8 state);
396 int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
397 const unsigned char *addr, u16 vid);
398 int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
399 const unsigned char *addr, u16 vid);
400 int mv88e6xxx_port_fdb_getnext(struct dsa_switch *ds, int port,
401 unsigned char *addr, bool *is_static);
402 int mv88e6xxx_phy_page_read(struct dsa_switch *ds, int port, int page, int reg);
403 int mv88e6xxx_phy_page_write(struct dsa_switch *ds, int port, int page,
405 extern struct dsa_switch_driver mv88e6131_switch_driver;
406 extern struct dsa_switch_driver mv88e6123_61_65_switch_driver;
407 extern struct dsa_switch_driver mv88e6352_switch_driver;
408 extern struct dsa_switch_driver mv88e6171_switch_driver;
410 #define REG_READ(addr, reg) \
414 __ret = mv88e6xxx_reg_read(ds, addr, reg); \
420 #define REG_WRITE(addr, reg, val) \
424 __ret = mv88e6xxx_reg_write(ds, addr, reg, val); \