2 * net/dsa/mv88e6xxx.h - Marvell 88e6xxx switch chip support
3 * Copyright (c) 2008 Marvell Semiconductor
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
14 /* switch product IDs */
16 #define ID_6085 0x04a0
17 #define ID_6095 0x0950
19 #define ID_6123 0x1210
20 #define ID_6123_A1 0x1212
21 #define ID_6123_A2 0x1213
23 #define ID_6131 0x1060
24 #define ID_6131_B2 0x1066
26 #define ID_6152 0x1a40
27 #define ID_6155 0x1a50
29 #define ID_6161 0x1610
30 #define ID_6161_A1 0x1612
31 #define ID_6161_A2 0x1613
33 #define ID_6165 0x1650
34 #define ID_6165_A1 0x1652
35 #define ID_6165_A2 0x1653
37 #define ID_6171 0x1710
38 #define ID_6172 0x1720
39 #define ID_6176 0x1760
41 #define ID_6182 0x1a60
42 #define ID_6185 0x1a70
44 #define ID_6352 0x3520
45 #define ID_6352_A0 0x3521
46 #define ID_6352_A1 0x3522
50 #define REG_PORT(p) (0x10 + (p))
51 #define REG_GLOBAL 0x1b
52 #define REG_GLOBAL2 0x1c
56 #define ATU_BUSY 0x8000
58 #define ATU_CMD_LOAD_FID (ATU_BUSY | 0x3000)
59 #define ATU_CMD_GETNEXT_FID (ATU_BUSY | 0x4000)
60 #define ATU_CMD_FLUSH_NONSTATIC_FID (ATU_BUSY | 0x6000)
64 #define PSTATE_MASK 0x03
65 #define PSTATE_DISABLED 0x00
66 #define PSTATE_BLOCKING 0x01
67 #define PSTATE_LEARNING 0x02
68 #define PSTATE_FORWARDING 0x03
72 #define FDB_STATE_MASK 0x0f
74 #define FDB_STATE_UNUSED 0x00
75 #define FDB_STATE_MC_STATIC 0x07 /* static multicast */
76 #define FDB_STATE_STATIC 0x0e /* static unicast */
78 struct mv88e6xxx_priv_state {
79 /* When using multi-chip addressing, this mutex protects
80 * access to the indirect access registers. (In single-chip
81 * mode, this mutex is effectively useless.)
83 struct mutex smi_mutex;
85 #ifdef CONFIG_NET_DSA_MV88E6XXX_NEED_PPU
86 /* Handles automatic disabling and re-enabling of the PHY
89 struct mutex ppu_mutex;
91 struct work_struct ppu_work;
92 struct timer_list ppu_timer;
95 /* This mutex serialises access to the statistics unit.
96 * Hold this mutex over snapshot + dump sequences.
98 struct mutex stats_mutex;
100 /* This mutex serializes phy access for chips with
101 * indirect phy addressing. It is unused for chips
102 * with direct phy access.
104 struct mutex phy_mutex;
106 /* This mutex serializes eeprom access for chips with
109 struct mutex eeprom_mutex;
111 int id; /* switch product id */
112 int num_ports; /* number of switch ports */
117 u8 fid[DSA_MAX_PORTS];
118 u16 bridge_mask[DSA_MAX_PORTS];
120 unsigned long port_state_update_mask;
121 u8 port_state[DSA_MAX_PORTS];
123 struct work_struct bridge_work;
126 struct mv88e6xxx_hw_stat {
127 char string[ETH_GSTRING_LEN];
132 int mv88e6xxx_switch_reset(struct dsa_switch *ds, bool ppu_active);
133 int mv88e6xxx_setup_port_common(struct dsa_switch *ds, int port);
134 int mv88e6xxx_setup_common(struct dsa_switch *ds);
135 int __mv88e6xxx_reg_read(struct mii_bus *bus, int sw_addr, int addr, int reg);
136 int mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg);
137 int __mv88e6xxx_reg_write(struct mii_bus *bus, int sw_addr, int addr,
139 int mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg, u16 val);
140 int mv88e6xxx_config_prio(struct dsa_switch *ds);
141 int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr);
142 int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr);
143 int mv88e6xxx_phy_read(struct dsa_switch *ds, int port, int regnum);
144 int mv88e6xxx_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val);
145 int mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int port, int regnum);
146 int mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int port, int regnum,
148 void mv88e6xxx_ppu_state_init(struct dsa_switch *ds);
149 int mv88e6xxx_phy_read_ppu(struct dsa_switch *ds, int addr, int regnum);
150 int mv88e6xxx_phy_write_ppu(struct dsa_switch *ds, int addr,
151 int regnum, u16 val);
152 void mv88e6xxx_poll_link(struct dsa_switch *ds);
153 void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, uint8_t *data);
154 void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
156 int mv88e6xxx_get_sset_count(struct dsa_switch *ds);
157 int mv88e6xxx_get_sset_count_basic(struct dsa_switch *ds);
158 int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port);
159 void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
160 struct ethtool_regs *regs, void *_p);
161 int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp);
162 int mv88e6xxx_phy_wait(struct dsa_switch *ds);
163 int mv88e6xxx_eeprom_load_wait(struct dsa_switch *ds);
164 int mv88e6xxx_eeprom_busy_wait(struct dsa_switch *ds);
165 int mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int addr, int regnum);
166 int mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int addr, int regnum,
168 int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e);
169 int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
170 struct phy_device *phydev, struct ethtool_eee *e);
171 int mv88e6xxx_join_bridge(struct dsa_switch *ds, int port, u32 br_port_mask);
172 int mv88e6xxx_leave_bridge(struct dsa_switch *ds, int port, u32 br_port_mask);
173 int mv88e6xxx_port_stp_update(struct dsa_switch *ds, int port, u8 state);
174 int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
175 const unsigned char *addr, u16 vid);
176 int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
177 const unsigned char *addr, u16 vid);
178 int mv88e6xxx_port_fdb_getnext(struct dsa_switch *ds, int port,
179 unsigned char *addr, bool *is_static);
180 int mv88e6xxx_phy_page_read(struct dsa_switch *ds, int port, int page, int reg);
181 int mv88e6xxx_phy_page_write(struct dsa_switch *ds, int port, int page,
183 extern struct dsa_switch_driver mv88e6131_switch_driver;
184 extern struct dsa_switch_driver mv88e6123_61_65_switch_driver;
185 extern struct dsa_switch_driver mv88e6352_switch_driver;
186 extern struct dsa_switch_driver mv88e6171_switch_driver;
188 #define REG_READ(addr, reg) \
192 __ret = mv88e6xxx_reg_read(ds, addr, reg); \
198 #define REG_WRITE(addr, reg, val) \
202 __ret = mv88e6xxx_reg_write(ds, addr, reg, val); \