drivers/net/e1000e/es2lan.c

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 /*
  30  * 80003ES2LAN Gigabit Ethernet Controller (Copper)
  31  * 80003ES2LAN Gigabit Ethernet Controller (Serdes)
  32  */
  33
  34 #include "e1000.h"
  35
  36 #define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL       0x00
  37 #define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL        0x02
  38 #define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL         0x10
  39 #define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE  0x1F
  40
  41 #define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS    0x0008
  42 #define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS    0x0800
  43 #define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING   0x0010
  44
  45 #define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004
  46 #define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT   0x0000
  47 #define E1000_KMRNCTRLSTA_OPMODE_E_IDLE          0x2000
  48
  49 #define E1000_KMRNCTRLSTA_OPMODE_MASK            0x000C
  50 #define E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO     0x0004
  51
  52 #define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */
  53 #define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN        0x00010000
  54
  55 #define DEFAULT_TIPG_IPGT_1000_80003ES2LAN       0x8
  56 #define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN     0x9
  57
  58 /* GG82563 PHY Specific Status Register (Page 0, Register 16 */
  59 #define GG82563_PSCR_POLARITY_REVERSAL_DISABLE   0x0002 /* 1=Reversal Disab. */
  60 #define GG82563_PSCR_CROSSOVER_MODE_MASK         0x0060
  61 #define GG82563_PSCR_CROSSOVER_MODE_MDI          0x0000 /* 00=Manual MDI */
  62 #define GG82563_PSCR_CROSSOVER_MODE_MDIX         0x0020 /* 01=Manual MDIX */
  63 #define GG82563_PSCR_CROSSOVER_MODE_AUTO         0x0060 /* 11=Auto crossover */
  64
  65 /* PHY Specific Control Register 2 (Page 0, Register 26) */
  66 #define GG82563_PSCR2_REVERSE_AUTO_NEG           0x2000
  67                                                 /* 1=Reverse Auto-Negotiation */
  68
  69 /* MAC Specific Control Register (Page 2, Register 21) */
  70 /* Tx clock speed for Link Down and 1000BASE-T for the following speeds */
  71 #define GG82563_MSCR_TX_CLK_MASK                 0x0007
  72 #define GG82563_MSCR_TX_CLK_10MBPS_2_5           0x0004
  73 #define GG82563_MSCR_TX_CLK_100MBPS_25           0x0005
  74 #define GG82563_MSCR_TX_CLK_1000MBPS_25          0x0007
  75
  76 #define GG82563_MSCR_ASSERT_CRS_ON_TX            0x0010 /* 1=Assert */
  77
  78 /* DSP Distance Register (Page 5, Register 26) */
  79 #define GG82563_DSPD_CABLE_LENGTH                0x0007 /* 0 = <50M
  80                                                            1 = 50-80M
  81                                                            2 = 80-110M
  82                                                            3 = 110-140M
  83                                                            4 = >140M */
  84
  85 /* Kumeran Mode Control Register (Page 193, Register 16) */
  86 #define GG82563_KMCR_PASS_FALSE_CARRIER          0x0800
  87
  88 /* Max number of times Kumeran read/write should be validated */
  89 #define GG82563_MAX_KMRN_RETRY  0x5
  90
  91 /* Power Management Control Register (Page 193, Register 20) */
  92 #define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE      0x0001
  93                                            /* 1=Enable SERDES Electrical Idle */
  94
  95 /* In-Band Control Register (Page 194, Register 18) */
  96 #define GG82563_ICR_DIS_PADDING                  0x0010 /* Disable Padding */
  97
  98 /*
  99  * A table for the GG82563 cable length where the range is defined
 100  * with a lower bound at "index" and the upper bound at
 101  * "index + 5".
 102  */
 103 static const u16 e1000_gg82563_cable_length_table[] =
 104          { 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF };
 105 #define GG82563_CABLE_LENGTH_TABLE_SIZE \
 106                 ARRAY_SIZE(e1000_gg82563_cable_length_table)
 107
 108 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);
 109 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
 110 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
 111 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
 112 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);
 113 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);
 114 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);
 115 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw);
 116 static s32  e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
 117                                             u16 *data);
 118 static s32  e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
 119                                              u16 data);
 120 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw);
 121
 122 /**
 123  *  e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
 124  *  @hw: pointer to the HW structure
 125  **/
 126 static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)
 127 {
 128         struct e1000_phy_info *phy = &hw->phy;
 129         s32 ret_val;
 130
 131         if (hw->phy.media_type != e1000_media_type_copper) {
 132                 phy->type       = e1000_phy_none;
 133                 return 0;
 134         } else {
 135                 phy->ops.power_up = e1000_power_up_phy_copper;
 136                 phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan;
 137         }
 138
 139         phy->addr               = 1;
 140         phy->autoneg_mask       = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 141         phy->reset_delay_us      = 100;
 142         phy->type               = e1000_phy_gg82563;
 143
 144         /* This can only be done after all function pointers are setup. */
 145         ret_val = e1000e_get_phy_id(hw);
 146
 147         /* Verify phy id */
 148         if (phy->id != GG82563_E_PHY_ID)
 149                 return -E1000_ERR_PHY;
 150
 151         return ret_val;
 152 }
 153
 154 /**
 155  *  e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.
 156  *  @hw: pointer to the HW structure
 157  **/
 158 static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
 159 {
 160         struct e1000_nvm_info *nvm = &hw->nvm;
 161         u32 eecd = er32(EECD);
 162         u16 size;
 163
 164         nvm->opcode_bits        = 8;
 165         nvm->delay_usec  = 1;
 166         switch (nvm->override) {
 167         case e1000_nvm_override_spi_large:
 168                 nvm->page_size    = 32;
 169                 nvm->address_bits = 16;
 170                 break;
 171         case e1000_nvm_override_spi_small:
 172                 nvm->page_size    = 8;
 173                 nvm->address_bits = 8;
 174                 break;
 175         default:
 176                 nvm->page_size    = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 177                 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
 178                 break;
 179         }
 180
 181         nvm->type = e1000_nvm_eeprom_spi;
 182
 183         size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
 184                           E1000_EECD_SIZE_EX_SHIFT);
 185
 186         /*
 187          * Added to a constant, "size" becomes the left-shift value
 188          * for setting word_size.
 189          */
 190         size += NVM_WORD_SIZE_BASE_SHIFT;
 191
 192         /* EEPROM access above 16k is unsupported */
 193         if (size > 14)
 194                 size = 14;
 195         nvm->word_size  = 1 << size;
 196
 197         return 0;
 198 }
 199
 200 /**
 201  *  e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.
 202  *  @hw: pointer to the HW structure
 203  **/
 204 static s32 e1000_init_mac_params_80003es2lan(struct e1000_adapter *adapter)
 205 {
 206         struct e1000_hw *hw = &adapter->hw;
 207         struct e1000_mac_info *mac = &hw->mac;
 208         struct e1000_mac_operations *func = &mac->ops;
 209
 210         /* Set media type */
 211         switch (adapter->pdev->device) {
 212         case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
 213                 hw->phy.media_type = e1000_media_type_internal_serdes;
 214                 break;
 215         default:
 216                 hw->phy.media_type = e1000_media_type_copper;
 217                 break;
 218         }
 219
 220         /* Set mta register count */
 221         mac->mta_reg_count = 128;
 222         /* Set rar entry count */
 223         mac->rar_entry_count = E1000_RAR_ENTRIES;
 224         /* Set if manageability features are enabled. */
 225         mac->arc_subsystem_valid = (er32(FWSM) & E1000_FWSM_MODE_MASK)
 226                         ? true : false;
 227
 228         /* check for link */
 229         switch (hw->phy.media_type) {
 230         case e1000_media_type_copper:
 231                 func->setup_physical_interface = e1000_setup_copper_link_80003es2lan;
 232                 func->check_for_link = e1000e_check_for_copper_link;
 233                 break;
 234         case e1000_media_type_fiber:
 235                 func->setup_physical_interface = e1000e_setup_fiber_serdes_link;
 236                 func->check_for_link = e1000e_check_for_fiber_link;
 237                 break;
 238         case e1000_media_type_internal_serdes:
 239                 func->setup_physical_interface = e1000e_setup_fiber_serdes_link;
 240                 func->check_for_link = e1000e_check_for_serdes_link;
 241                 break;
 242         default:
 243                 return -E1000_ERR_CONFIG;
 244                 break;
 245         }
 246
 247         return 0;
 248 }
 249
 250 static s32 e1000_get_variants_80003es2lan(struct e1000_adapter *adapter)
 251 {
 252         struct e1000_hw *hw = &adapter->hw;
 253         s32 rc;
 254
 255         rc = e1000_init_mac_params_80003es2lan(adapter);
 256         if (rc)
 257                 return rc;
 258
 259         rc = e1000_init_nvm_params_80003es2lan(hw);
 260         if (rc)
 261                 return rc;
 262
 263         rc = e1000_init_phy_params_80003es2lan(hw);
 264         if (rc)
 265                 return rc;
 266
 267         return 0;
 268 }
 269
 270 /**
 271  *  e1000_acquire_phy_80003es2lan - Acquire rights to access PHY
 272  *  @hw: pointer to the HW structure
 273  *
 274  *  A wrapper to acquire access rights to the correct PHY.
 275  **/
 276 static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw)
 277 {
 278         u16 mask;
 279
 280         mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
 281         return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
 282 }
 283
 284 /**
 285  *  e1000_release_phy_80003es2lan - Release rights to access PHY
 286  *  @hw: pointer to the HW structure
 287  *
 288  *  A wrapper to release access rights to the correct PHY.
 289  **/
 290 static void e1000_release_phy_80003es2lan(struct e1000_hw *hw)
 291 {
 292         u16 mask;
 293
 294         mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
 295         e1000_release_swfw_sync_80003es2lan(hw, mask);
 296 }
 297
 298 /**
 299  *  e1000_acquire_mac_csr_80003es2lan - Acquire rights to access Kumeran register
 300  *  @hw: pointer to the HW structure
 301  *
 302  *  Acquire the semaphore to access the Kumeran interface.
 303  *
 304  **/
 305 static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw)
 306 {
 307         u16 mask;
 308
 309         mask = E1000_SWFW_CSR_SM;
 310
 311         return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
 312 }
 313
 314 /**
 315  *  e1000_release_mac_csr_80003es2lan - Release rights to access Kumeran Register
 316  *  @hw: pointer to the HW structure
 317  *
 318  *  Release the semaphore used to access the Kumeran interface
 319  **/
 320 static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw)
 321 {
 322         u16 mask;
 323
 324         mask = E1000_SWFW_CSR_SM;
 325
 326         e1000_release_swfw_sync_80003es2lan(hw, mask);
 327 }
 328
 329 /**
 330  *  e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM
 331  *  @hw: pointer to the HW structure
 332  *
 333  *  Acquire the semaphore to access the EEPROM.
 334  **/
 335 static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw)
 336 {
 337         s32 ret_val;
 338
 339         ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
 340         if (ret_val)
 341                 return ret_val;
 342
 343         ret_val = e1000e_acquire_nvm(hw);
 344
 345         if (ret_val)
 346                 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
 347
 348         return ret_val;
 349 }
 350
 351 /**
 352  *  e1000_release_nvm_80003es2lan - Relinquish rights to access NVM
 353  *  @hw: pointer to the HW structure
 354  *
 355  *  Release the semaphore used to access the EEPROM.
 356  **/
 357 static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw)
 358 {
 359         e1000e_release_nvm(hw);
 360         e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
 361 }
 362
 363 /**
 364  *  e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore
 365  *  @hw: pointer to the HW structure
 366  *  @mask: specifies which semaphore to acquire
 367  *
 368  *  Acquire the SW/FW semaphore to access the PHY or NVM.  The mask
 369  *  will also specify which port we're acquiring the lock for.
 370  **/
 371 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
 372 {
 373         u32 swfw_sync;
 374         u32 swmask = mask;
 375         u32 fwmask = mask << 16;
 376         s32 i = 0;
 377         s32 timeout = 50;
 378
 379         while (i < timeout) {
 380                 if (e1000e_get_hw_semaphore(hw))
 381                         return -E1000_ERR_SWFW_SYNC;
 382
 383                 swfw_sync = er32(SW_FW_SYNC);
 384                 if (!(swfw_sync & (fwmask | swmask)))
 385                         break;
 386
 387                 /*
 388                  * Firmware currently using resource (fwmask)
 389                  * or other software thread using resource (swmask)
 390                  */
 391                 e1000e_put_hw_semaphore(hw);
 392                 mdelay(5);
 393                 i++;
 394         }
 395
 396         if (i == timeout) {
 397                 e_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
 398                 return -E1000_ERR_SWFW_SYNC;
 399         }
 400
 401         swfw_sync |= swmask;
 402         ew32(SW_FW_SYNC, swfw_sync);
 403
 404         e1000e_put_hw_semaphore(hw);
 405
 406         return 0;
 407 }
 408
 409 /**
 410  *  e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore
 411  *  @hw: pointer to the HW structure
 412  *  @mask: specifies which semaphore to acquire
 413  *
 414  *  Release the SW/FW semaphore used to access the PHY or NVM.  The mask
 415  *  will also specify which port we're releasing the lock for.
 416  **/
 417 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
 418 {
 419         u32 swfw_sync;
 420
 421         while (e1000e_get_hw_semaphore(hw) != 0);
 422         /* Empty */
 423
 424         swfw_sync = er32(SW_FW_SYNC);
 425         swfw_sync &= ~mask;
 426         ew32(SW_FW_SYNC, swfw_sync);
 427
 428         e1000e_put_hw_semaphore(hw);
 429 }
 430
 431 /**
 432  *  e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register
 433  *  @hw: pointer to the HW structure
 434  *  @offset: offset of the register to read
 435  *  @data: pointer to the data returned from the operation
 436  *
 437  *  Read the GG82563 PHY register.
 438  **/
 439 static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
 440                                                   u32 offset, u16 *data)
 441 {
 442         s32 ret_val;
 443         u32 page_select;
 444         u16 temp;
 445
 446         ret_val = e1000_acquire_phy_80003es2lan(hw);
 447         if (ret_val)
 448                 return ret_val;
 449
 450         /* Select Configuration Page */
 451         if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
 452                 page_select = GG82563_PHY_PAGE_SELECT;
 453         } else {
 454                 /*
 455                  * Use Alternative Page Select register to access
 456                  * registers 30 and 31
 457                  */
 458                 page_select = GG82563_PHY_PAGE_SELECT_ALT;
 459         }
 460
 461         temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
 462         ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
 463         if (ret_val) {
 464                 e1000_release_phy_80003es2lan(hw);
 465                 return ret_val;
 466         }
 467
 468         if (hw->dev_spec.e80003es2lan.mdic_wa_enable == true) {
 469                 /*
 470                  * The "ready" bit in the MDIC register may be incorrectly set
 471                  * before the device has completed the "Page Select" MDI
 472                  * transaction.  So we wait 200us after each MDI command...
 473                  */
 474                 udelay(200);
 475
 476                 /* ...and verify the command was successful. */
 477                 ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
 478
 479                 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
 480                         ret_val = -E1000_ERR_PHY;
 481                         e1000_release_phy_80003es2lan(hw);
 482                         return ret_val;
 483                 }
 484
 485                 udelay(200);
 486
 487                 ret_val = e1000e_read_phy_reg_mdic(hw,
 488                                                   MAX_PHY_REG_ADDRESS & offset,
 489                                                   data);
 490
 491                 udelay(200);
 492         } else {
 493                 ret_val = e1000e_read_phy_reg_mdic(hw,
 494                                                   MAX_PHY_REG_ADDRESS & offset,
 495                                                   data);
 496         }
 497
 498         e1000_release_phy_80003es2lan(hw);
 499
 500         return ret_val;
 501 }
 502
 503 /**
 504  *  e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register
 505  *  @hw: pointer to the HW structure
 506  *  @offset: offset of the register to read
 507  *  @data: value to write to the register
 508  *
 509  *  Write to the GG82563 PHY register.
 510  **/
 511 static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
 512                                                    u32 offset, u16 data)
 513 {
 514         s32 ret_val;
 515         u32 page_select;
 516         u16 temp;
 517
 518         ret_val = e1000_acquire_phy_80003es2lan(hw);
 519         if (ret_val)
 520                 return ret_val;
 521
 522         /* Select Configuration Page */
 523         if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
 524                 page_select = GG82563_PHY_PAGE_SELECT;
 525         } else {
 526                 /*
 527                  * Use Alternative Page Select register to access
 528                  * registers 30 and 31
 529                  */
 530                 page_select = GG82563_PHY_PAGE_SELECT_ALT;
 531         }
 532
 533         temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
 534         ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
 535         if (ret_val) {
 536                 e1000_release_phy_80003es2lan(hw);
 537                 return ret_val;
 538         }
 539
 540         if (hw->dev_spec.e80003es2lan.mdic_wa_enable == true) {
 541                 /*
 542                  * The "ready" bit in the MDIC register may be incorrectly set
 543                  * before the device has completed the "Page Select" MDI
 544                  * transaction.  So we wait 200us after each MDI command...
 545                  */
 546                 udelay(200);
 547
 548                 /* ...and verify the command was successful. */
 549                 ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
 550
 551                 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
 552                         e1000_release_phy_80003es2lan(hw);
 553                         return -E1000_ERR_PHY;
 554                 }
 555
 556                 udelay(200);
 557
 558                 ret_val = e1000e_write_phy_reg_mdic(hw,
 559                                                   MAX_PHY_REG_ADDRESS & offset,
 560                                                   data);
 561
 562                 udelay(200);
 563         } else {
 564                 ret_val = e1000e_write_phy_reg_mdic(hw,
 565                                                   MAX_PHY_REG_ADDRESS & offset,
 566                                                   data);
 567         }
 568
 569         e1000_release_phy_80003es2lan(hw);
 570
 571         return ret_val;
 572 }
 573
 574 /**
 575  *  e1000_write_nvm_80003es2lan - Write to ESB2 NVM
 576  *  @hw: pointer to the HW structure
 577  *  @offset: offset of the register to read
 578  *  @words: number of words to write
 579  *  @data: buffer of data to write to the NVM
 580  *
 581  *  Write "words" of data to the ESB2 NVM.
 582  **/
 583 static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
 584                                        u16 words, u16 *data)
 585 {
 586         return e1000e_write_nvm_spi(hw, offset, words, data);
 587 }
 588
 589 /**
 590  *  e1000_get_cfg_done_80003es2lan - Wait for configuration to complete
 591  *  @hw: pointer to the HW structure
 592  *
 593  *  Wait a specific amount of time for manageability processes to complete.
 594  *  This is a function pointer entry point called by the phy module.
 595  **/
 596 static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw)
 597 {
 598         s32 timeout = PHY_CFG_TIMEOUT;
 599         u32 mask = E1000_NVM_CFG_DONE_PORT_0;
 600
 601         if (hw->bus.func == 1)
 602                 mask = E1000_NVM_CFG_DONE_PORT_1;
 603
 604         while (timeout) {
 605                 if (er32(EEMNGCTL) & mask)
 606                         break;
 607                 msleep(1);
 608                 timeout--;
 609         }
 610         if (!timeout) {
 611                 e_dbg("MNG configuration cycle has not completed.\n");
 612                 return -E1000_ERR_RESET;
 613         }
 614
 615         return 0;
 616 }
 617
 618 /**
 619  *  e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex
 620  *  @hw: pointer to the HW structure
 621  *
 622  *  Force the speed and duplex settings onto the PHY.  This is a
 623  *  function pointer entry point called by the phy module.
 624  **/
 625 static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
 626 {
 627         s32 ret_val;
 628         u16 phy_data;
 629         bool link;
 630
 631         /*
 632          * Clear Auto-Crossover to force MDI manually.  M88E1000 requires MDI
 633          * forced whenever speed and duplex are forced.
 634          */
 635         ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
 636         if (ret_val)
 637                 return ret_val;
 638
 639         phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO;
 640         ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, phy_data);
 641         if (ret_val)
 642                 return ret_val;
 643
 644         e_dbg("GG82563 PSCR: %X\n", phy_data);
 645
 646         ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
 647         if (ret_val)
 648                 return ret_val;
 649
 650         e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
 651
 652         /* Reset the phy to commit changes. */
 653         phy_data |= MII_CR_RESET;
 654
 655         ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
 656         if (ret_val)
 657                 return ret_val;
 658
 659         udelay(1);
 660
 661         if (hw->phy.autoneg_wait_to_complete) {
 662                 e_dbg("Waiting for forced speed/duplex link "
 663                          "on GG82563 phy.\n");
 664
 665                 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
 666                                                      100000, &link);
 667                 if (ret_val)
 668                         return ret_val;
 669
 670                 if (!link) {
 671                         /*
 672                          * We didn't get link.
 673                          * Reset the DSP and cross our fingers.
 674                          */
 675                         ret_val = e1000e_phy_reset_dsp(hw);
 676                         if (ret_val)
 677                                 return ret_val;
 678                 }
 679
 680                 /* Try once more */
 681                 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
 682                                                      100000, &link);
 683                 if (ret_val)
 684                         return ret_val;
 685         }
 686
 687         ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
 688         if (ret_val)
 689                 return ret_val;
 690
 691         /*
 692          * Resetting the phy means we need to verify the TX_CLK corresponds
 693          * to the link speed.  10Mbps -> 2.5MHz, else 25MHz.
 694          */
 695         phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
 696         if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)
 697                 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5;
 698         else
 699                 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25;
 700
 701         /*
 702          * In addition, we must re-enable CRS on Tx for both half and full
 703          * duplex.
 704          */
 705         phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
 706         ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
 707
 708         return ret_val;
 709 }
 710
 711 /**
 712  *  e1000_get_cable_length_80003es2lan - Set approximate cable length
 713  *  @hw: pointer to the HW structure
 714  *
 715  *  Find the approximate cable length as measured by the GG82563 PHY.
 716  *  This is a function pointer entry point called by the phy module.
 717  **/
 718 static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw)
 719 {
 720         struct e1000_phy_info *phy = &hw->phy;
 721         s32 ret_val = 0;
 722         u16 phy_data, index;
 723
 724         ret_val = e1e_rphy(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);
 725         if (ret_val)
 726                 goto out;
 727
 728         index = phy_data & GG82563_DSPD_CABLE_LENGTH;
 729
 730         if (index >= GG82563_CABLE_LENGTH_TABLE_SIZE - 5) {
 731                 ret_val = -E1000_ERR_PHY;
 732                 goto out;
 733         }
 734
 735         phy->min_cable_length = e1000_gg82563_cable_length_table[index];
 736         phy->max_cable_length = e1000_gg82563_cable_length_table[index + 5];
 737
 738         phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
 739
 740 out:
 741         return ret_val;
 742 }
 743
 744 /**
 745  *  e1000_get_link_up_info_80003es2lan - Report speed and duplex
 746  *  @hw: pointer to the HW structure
 747  *  @speed: pointer to speed buffer
 748  *  @duplex: pointer to duplex buffer
 749  *
 750  *  Retrieve the current speed and duplex configuration.
 751  **/
 752 static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
 753                                               u16 *duplex)
 754 {
 755         s32 ret_val;
 756
 757         if (hw->phy.media_type == e1000_media_type_copper) {
 758                 ret_val = e1000e_get_speed_and_duplex_copper(hw,
 759                                                                     speed,
 760                                                                     duplex);
 761                 hw->phy.ops.cfg_on_link_up(hw);
 762         } else {
 763                 ret_val = e1000e_get_speed_and_duplex_fiber_serdes(hw,
 764                                                                   speed,
 765                                                                   duplex);
 766         }
 767
 768         return ret_val;
 769 }
 770
 771 /**
 772  *  e1000_reset_hw_80003es2lan - Reset the ESB2 controller
 773  *  @hw: pointer to the HW structure
 774  *
 775  *  Perform a global reset to the ESB2 controller.
 776  **/
 777 static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
 778 {
 779         u32 ctrl, icr;
 780         s32 ret_val;
 781
 782         /*
 783          * Prevent the PCI-E bus from sticking if there is no TLP connection
 784          * on the last TLP read/write transaction when MAC is reset.
 785          */
 786         ret_val = e1000e_disable_pcie_master(hw);
 787         if (ret_val)
 788                 e_dbg("PCI-E Master disable polling has failed.\n");
 789
 790         e_dbg("Masking off all interrupts\n");
 791         ew32(IMC, 0xffffffff);
 792
 793         ew32(RCTL, 0);
 794         ew32(TCTL, E1000_TCTL_PSP);
 795         e1e_flush();
 796
 797         msleep(10);
 798
 799         ctrl = er32(CTRL);
 800
 801         ret_val = e1000_acquire_phy_80003es2lan(hw);
 802         e_dbg("Issuing a global reset to MAC\n");
 803         ew32(CTRL, ctrl | E1000_CTRL_RST);
 804         e1000_release_phy_80003es2lan(hw);
 805
 806         ret_val = e1000e_get_auto_rd_done(hw);
 807         if (ret_val)
 808                 /* We don't want to continue accessing MAC registers. */
 809                 return ret_val;
 810
 811         /* Clear any pending interrupt events. */
 812         ew32(IMC, 0xffffffff);
 813         icr = er32(ICR);
 814
 815         return 0;
 816 }
 817
 818 /**
 819  *  e1000_init_hw_80003es2lan - Initialize the ESB2 controller
 820  *  @hw: pointer to the HW structure
 821  *
 822  *  Initialize the hw bits, LED, VFTA, MTA, link and hw counters.
 823  **/
 824 static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
 825 {
 826         struct e1000_mac_info *mac = &hw->mac;
 827         u32 reg_data;
 828         s32 ret_val;
 829         u16 i;
 830
 831         e1000_initialize_hw_bits_80003es2lan(hw);
 832
 833         /* Initialize identification LED */
 834         ret_val = e1000e_id_led_init(hw);
 835         if (ret_val)
 836                 e_dbg("Error initializing identification LED\n");
 837                 /* This is not fatal and we should not stop init due to this */
 838
 839         /* Disabling VLAN filtering */
 840         e_dbg("Initializing the IEEE VLAN\n");
 841         mac->ops.clear_vfta(hw);
 842
 843         /* Setup the receive address. */
 844         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
 845
 846         /* Zero out the Multicast HASH table */
 847         e_dbg("Zeroing the MTA\n");
 848         for (i = 0; i < mac->mta_reg_count; i++)
 849                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
 850
 851         /* Setup link and flow control */
 852         ret_val = e1000e_setup_link(hw);
 853
 854         /* Set the transmit descriptor write-back policy */
 855         reg_data = er32(TXDCTL(0));
 856         reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
 857                    E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
 858         ew32(TXDCTL(0), reg_data);
 859
 860         /* ...for both queues. */
 861         reg_data = er32(TXDCTL(1));
 862         reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
 863                    E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
 864         ew32(TXDCTL(1), reg_data);
 865
 866         /* Enable retransmit on late collisions */
 867         reg_data = er32(TCTL);
 868         reg_data |= E1000_TCTL_RTLC;
 869         ew32(TCTL, reg_data);
 870
 871         /* Configure Gigabit Carry Extend Padding */
 872         reg_data = er32(TCTL_EXT);
 873         reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
 874         reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN;
 875         ew32(TCTL_EXT, reg_data);
 876
 877         /* Configure Transmit Inter-Packet Gap */
 878         reg_data = er32(TIPG);
 879         reg_data &= ~E1000_TIPG_IPGT_MASK;
 880         reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
 881         ew32(TIPG, reg_data);
 882
 883         reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);
 884         reg_data &= ~0x00100000;
 885         E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
 886
 887         /* default to true to enable the MDIC W/A */
 888         hw->dev_spec.e80003es2lan.mdic_wa_enable = true;
 889
 890         ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
 891                                       E1000_KMRNCTRLSTA_OFFSET >>
 892                                       E1000_KMRNCTRLSTA_OFFSET_SHIFT,
 893                                       &i);
 894         if (!ret_val) {
 895                 if ((i & E1000_KMRNCTRLSTA_OPMODE_MASK) ==
 896                      E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO)
 897                         hw->dev_spec.e80003es2lan.mdic_wa_enable = false;
 898         }
 899
 900         /*
 901          * Clear all of the statistics registers (clear on read).  It is
 902          * important that we do this after we have tried to establish link
 903          * because the symbol error count will increment wildly if there
 904          * is no link.
 905          */
 906         e1000_clear_hw_cntrs_80003es2lan(hw);
 907
 908         return ret_val;
 909 }
 910
 911 /**
 912  *  e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2
 913  *  @hw: pointer to the HW structure
 914  *
 915  *  Initializes required hardware-dependent bits needed for normal operation.
 916  **/
 917 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)
 918 {
 919         u32 reg;
 920
 921         /* Transmit Descriptor Control 0 */
 922         reg = er32(TXDCTL(0));
 923         reg |= (1 << 22);
 924         ew32(TXDCTL(0), reg);
 925
 926         /* Transmit Descriptor Control 1 */
 927         reg = er32(TXDCTL(1));
 928         reg |= (1 << 22);
 929         ew32(TXDCTL(1), reg);
 930
 931         /* Transmit Arbitration Control 0 */
 932         reg = er32(TARC(0));
 933         reg &= ~(0xF << 27); /* 30:27 */
 934         if (hw->phy.media_type != e1000_media_type_copper)
 935                 reg &= ~(1 << 20);
 936         ew32(TARC(0), reg);
 937
 938         /* Transmit Arbitration Control 1 */
 939         reg = er32(TARC(1));
 940         if (er32(TCTL) & E1000_TCTL_MULR)
 941                 reg &= ~(1 << 28);
 942         else
 943                 reg |= (1 << 28);
 944         ew32(TARC(1), reg);
 945 }
 946
 947 /**
 948  *  e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link
 949  *  @hw: pointer to the HW structure
 950  *
 951  *  Setup some GG82563 PHY registers for obtaining link
 952  **/
 953 static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
 954 {
 955         struct e1000_phy_info *phy = &hw->phy;
 956         s32 ret_val;
 957         u32 ctrl_ext;
 958         u16 data;
 959
 960         ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &data);
 961         if (ret_val)
 962                 return ret_val;
 963
 964         data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
 965         /* Use 25MHz for both link down and 1000Base-T for Tx clock. */
 966         data |= GG82563_MSCR_TX_CLK_1000MBPS_25;
 967
 968         ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, data);
 969         if (ret_val)
 970                 return ret_val;
 971
 972         /*
 973          * Options:
 974          *   MDI/MDI-X = 0 (default)
 975          *   0 - Auto for all speeds
 976          *   1 - MDI mode
 977          *   2 - MDI-X mode
 978          *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
 979          */
 980         ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL, &data);
 981         if (ret_val)
 982                 return ret_val;
 983
 984         data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
 985
 986         switch (phy->mdix) {
 987         case 1:
 988                 data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
 989                 break;
 990         case 2:
 991                 data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
 992                 break;
 993         case 0:
 994         default:
 995                 data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
 996                 break;
 997         }
 998
 999         /*
1000          * Options:
1001          *   disable_polarity_correction = 0 (default)
1002          *       Automatic Correction for Reversed Cable Polarity
1003          *   0 - Disabled
1004          *   1 - Enabled
1005          */
1006         data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1007         if (phy->disable_polarity_correction)
1008                 data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1009
1010         ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, data);
1011         if (ret_val)
1012                 return ret_val;
1013
1014         /* SW Reset the PHY so all changes take effect */
1015         ret_val = e1000e_commit_phy(hw);
1016         if (ret_val) {
1017                 e_dbg("Error Resetting the PHY\n");
1018                 return ret_val;
1019         }
1020
1021         /* Bypass Rx and Tx FIFO's */
1022         ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1023                                         E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL,
1024                                         E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |
1025                                         E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);
1026         if (ret_val)
1027                 return ret_val;
1028
1029         ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
1030                                        E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
1031                                        &data);
1032         if (ret_val)
1033                 return ret_val;
1034         data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE;
1035         ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1036                                         E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
1037                                         data);
1038         if (ret_val)
1039                 return ret_val;
1040
1041         ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL_2, &data);
1042         if (ret_val)
1043                 return ret_val;
1044
1045         data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
1046         ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL_2, data);
1047         if (ret_val)
1048                 return ret_val;
1049
1050         ctrl_ext = er32(CTRL_EXT);
1051         ctrl_ext &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
1052         ew32(CTRL_EXT, ctrl_ext);
1053
1054         ret_val = e1e_rphy(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);
1055         if (ret_val)
1056                 return ret_val;
1057
1058         /*
1059          * Do not init these registers when the HW is in IAMT mode, since the
1060          * firmware will have already initialized them.  We only initialize
1061          * them if the HW is not in IAMT mode.
1062          */
1063         if (!e1000e_check_mng_mode(hw)) {
1064                 /* Enable Electrical Idle on the PHY */
1065                 data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
1066                 ret_val = e1e_wphy(hw, GG82563_PHY_PWR_MGMT_CTRL, data);
1067                 if (ret_val)
1068                         return ret_val;
1069
1070                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &data);
1071                 if (ret_val)
1072                         return ret_val;
1073
1074                 data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1075                 ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, data);
1076                 if (ret_val)
1077                         return ret_val;
1078         }
1079
1080         /*
1081          * Workaround: Disable padding in Kumeran interface in the MAC
1082          * and in the PHY to avoid CRC errors.
1083          */
1084         ret_val = e1e_rphy(hw, GG82563_PHY_INBAND_CTRL, &data);
1085         if (ret_val)
1086                 return ret_val;
1087
1088         data |= GG82563_ICR_DIS_PADDING;
1089         ret_val = e1e_wphy(hw, GG82563_PHY_INBAND_CTRL, data);
1090         if (ret_val)
1091                 return ret_val;
1092
1093         return 0;
1094 }
1095
1096 /**
1097  *  e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2
1098  *  @hw: pointer to the HW structure
1099  *
1100  *  Essentially a wrapper for setting up all things "copper" related.
1101  *  This is a function pointer entry point called by the mac module.
1102  **/
1103 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)
1104 {
1105         u32 ctrl;
1106         s32 ret_val;
1107         u16 reg_data;
1108
1109         ctrl = er32(CTRL);
1110         ctrl |= E1000_CTRL_SLU;
1111         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1112         ew32(CTRL, ctrl);
1113
1114         /*
1115          * Set the mac to wait the maximum time between each
1116          * iteration and increase the max iterations when
1117          * polling the phy; this fixes erroneous timeouts at 10Mbps.
1118          */
1119         ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4),
1120                                                    0xFFFF);
1121         if (ret_val)
1122                 return ret_val;
1123         ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1124                                                   &reg_data);
1125         if (ret_val)
1126                 return ret_val;
1127         reg_data |= 0x3F;
1128         ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1129                                                    reg_data);
1130         if (ret_val)
1131                 return ret_val;
1132         ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
1133                                       E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1134                                       &reg_data);
1135         if (ret_val)
1136                 return ret_val;
1137         reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING;
1138         ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1139                                         E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1140                                         reg_data);
1141         if (ret_val)
1142                 return ret_val;
1143
1144         ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw);
1145         if (ret_val)
1146                 return ret_val;
1147
1148         ret_val = e1000e_setup_copper_link(hw);
1149
1150         return 0;
1151 }
1152
1153 /**
1154  *  e1000_cfg_on_link_up_80003es2lan - es2 link configuration after link-up
1155  *  @hw: pointer to the HW structure
1156  *  @duplex: current duplex setting
1157  *
1158  *  Configure the KMRN interface by applying last minute quirks for
1159  *  10/100 operation.
1160  **/
1161 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw)
1162 {
1163         s32 ret_val = 0;
1164         u16 speed;
1165         u16 duplex;
1166
1167         if (hw->phy.media_type == e1000_media_type_copper) {
1168                 ret_val = e1000e_get_speed_and_duplex_copper(hw, &speed,
1169                                                              &duplex);
1170                 if (ret_val)
1171                         return ret_val;
1172
1173                 if (speed == SPEED_1000)
1174                         ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw);
1175                 else
1176                         ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex);
1177         }
1178
1179         return ret_val;
1180 }
1181
1182 /**
1183  *  e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation
1184  *  @hw: pointer to the HW structure
1185  *  @duplex: current duplex setting
1186  *
1187  *  Configure the KMRN interface by applying last minute quirks for
1188  *  10/100 operation.
1189  **/
1190 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
1191 {
1192         s32 ret_val;
1193         u32 tipg;
1194         u32 i = 0;
1195         u16 reg_data, reg_data2;
1196
1197         reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT;
1198         ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1199                                        E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1200                                        reg_data);
1201         if (ret_val)
1202                 return ret_val;
1203
1204         /* Configure Transmit Inter-Packet Gap */
1205         tipg = er32(TIPG);
1206         tipg &= ~E1000_TIPG_IPGT_MASK;
1207         tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN;
1208         ew32(TIPG, tipg);
1209
1210         do {
1211                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
1212                 if (ret_val)
1213                         return ret_val;
1214
1215                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data2);
1216                 if (ret_val)
1217                         return ret_val;
1218                 i++;
1219         } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1220
1221         if (duplex == HALF_DUPLEX)
1222                 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1223         else
1224                 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1225
1226         ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1227
1228         return 0;
1229 }
1230
1231 /**
1232  *  e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation
1233  *  @hw: pointer to the HW structure
1234  *
1235  *  Configure the KMRN interface by applying last minute quirks for
1236  *  gigabit operation.
1237  **/
1238 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
1239 {
1240         s32 ret_val;
1241         u16 reg_data, reg_data2;
1242         u32 tipg;
1243         u32 i = 0;
1244
1245         reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT;
1246         ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1247                                        E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1248                                        reg_data);
1249         if (ret_val)
1250                 return ret_val;
1251
1252         /* Configure Transmit Inter-Packet Gap */
1253         tipg = er32(TIPG);
1254         tipg &= ~E1000_TIPG_IPGT_MASK;
1255         tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
1256         ew32(TIPG, tipg);
1257
1258         do {
1259                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
1260                 if (ret_val)
1261                         return ret_val;
1262
1263                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data2);
1264                 if (ret_val)
1265                         return ret_val;
1266                 i++;
1267         } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1268
1269         reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1270         ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1271
1272         return ret_val;
1273 }
1274
1275 /**
1276  *  e1000_read_kmrn_reg_80003es2lan - Read kumeran register
1277  *  @hw: pointer to the HW structure
1278  *  @offset: register offset to be read
1279  *  @data: pointer to the read data
1280  *
1281  *  Acquire semaphore, then read the PHY register at offset
1282  *  using the kumeran interface.  The information retrieved is stored in data.
1283  *  Release the semaphore before exiting.
1284  **/
1285 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1286                                            u16 *data)
1287 {
1288         u32 kmrnctrlsta;
1289         s32 ret_val = 0;
1290
1291         ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1292         if (ret_val)
1293                 return ret_val;
1294
1295         kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1296                        E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
1297         ew32(KMRNCTRLSTA, kmrnctrlsta);
1298
1299         udelay(2);
1300
1301         kmrnctrlsta = er32(KMRNCTRLSTA);
1302         *data = (u16)kmrnctrlsta;
1303
1304         e1000_release_mac_csr_80003es2lan(hw);
1305
1306         return ret_val;
1307 }
1308
1309 /**
1310  *  e1000_write_kmrn_reg_80003es2lan - Write kumeran register
1311  *  @hw: pointer to the HW structure
1312  *  @offset: register offset to write to
1313  *  @data: data to write at register offset
1314  *
1315  *  Acquire semaphore, then write the data to PHY register
1316  *  at the offset using the kumeran interface.  Release semaphore
1317  *  before exiting.
1318  **/
1319 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1320                                             u16 data)
1321 {
1322         u32 kmrnctrlsta;
1323         s32 ret_val = 0;
1324
1325         ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1326         if (ret_val)
1327                 return ret_val;
1328
1329         kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1330                        E1000_KMRNCTRLSTA_OFFSET) | data;
1331         ew32(KMRNCTRLSTA, kmrnctrlsta);
1332
1333         udelay(2);
1334
1335         e1000_release_mac_csr_80003es2lan(hw);
1336
1337         return ret_val;
1338 }
1339
1340 /**
1341  * e1000_power_down_phy_copper_80003es2lan - Remove link during PHY power down
1342  * @hw: pointer to the HW structure
1343  *
1344  * In the case of a PHY power down to save power, or to turn off link during a
1345  * driver unload, or wake on lan is not enabled, remove the link.
1346  **/
1347 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw)
1348 {
1349         /* If the management interface is not enabled, then power down */
1350         if (!(hw->mac.ops.check_mng_mode(hw) ||
1351               hw->phy.ops.check_reset_block(hw)))
1352                 e1000_power_down_phy_copper(hw);
1353
1354         return;
1355 }
1356
1357 /**
1358  *  e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters
1359  *  @hw: pointer to the HW structure
1360  *
1361  *  Clears the hardware counters by reading the counter registers.
1362  **/
1363 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw)
1364 {
1365         e1000e_clear_hw_cntrs_base(hw);
1366
1367         er32(PRC64);
1368         er32(PRC127);
1369         er32(PRC255);
1370         er32(PRC511);
1371         er32(PRC1023);
1372         er32(PRC1522);
1373         er32(PTC64);
1374         er32(PTC127);
1375         er32(PTC255);
1376         er32(PTC511);
1377         er32(PTC1023);
1378         er32(PTC1522);
1379
1380         er32(ALGNERRC);
1381         er32(RXERRC);
1382         er32(TNCRS);
1383         er32(CEXTERR);
1384         er32(TSCTC);
1385         er32(TSCTFC);
1386
1387         er32(MGTPRC);
1388         er32(MGTPDC);
1389         er32(MGTPTC);
1390
1391         er32(IAC);
1392         er32(ICRXOC);
1393
1394         er32(ICRXPTC);
1395         er32(ICRXATC);
1396         er32(ICTXPTC);
1397         er32(ICTXATC);
1398         er32(ICTXQEC);
1399         er32(ICTXQMTC);
1400         er32(ICRXDMTC);
1401 }
1402
1403 static struct e1000_mac_operations es2_mac_ops = {
1404         .id_led_init            = e1000e_id_led_init,
1405         .check_mng_mode         = e1000e_check_mng_mode_generic,
1406         /* check_for_link dependent on media type */
1407         .cleanup_led            = e1000e_cleanup_led_generic,
1408         .clear_hw_cntrs         = e1000_clear_hw_cntrs_80003es2lan,
1409         .get_bus_info           = e1000e_get_bus_info_pcie,
1410         .get_link_up_info       = e1000_get_link_up_info_80003es2lan,
1411         .led_on                 = e1000e_led_on_generic,
1412         .led_off                = e1000e_led_off_generic,
1413         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
1414         .write_vfta             = e1000_write_vfta_generic,
1415         .clear_vfta             = e1000_clear_vfta_generic,
1416         .reset_hw               = e1000_reset_hw_80003es2lan,
1417         .init_hw                = e1000_init_hw_80003es2lan,
1418         .setup_link             = e1000e_setup_link,
1419         /* setup_physical_interface dependent on media type */
1420         .setup_led              = e1000e_setup_led_generic,
1421 };
1422
1423 static struct e1000_phy_operations es2_phy_ops = {
1424         .acquire                = e1000_acquire_phy_80003es2lan,
1425         .check_polarity         = e1000_check_polarity_m88,
1426         .check_reset_block      = e1000e_check_reset_block_generic,
1427         .commit                 = e1000e_phy_sw_reset,
1428         .force_speed_duplex     = e1000_phy_force_speed_duplex_80003es2lan,
1429         .get_cfg_done           = e1000_get_cfg_done_80003es2lan,
1430         .get_cable_length       = e1000_get_cable_length_80003es2lan,
1431         .get_info               = e1000e_get_phy_info_m88,
1432         .read_reg               = e1000_read_phy_reg_gg82563_80003es2lan,
1433         .release                = e1000_release_phy_80003es2lan,
1434         .reset                  = e1000e_phy_hw_reset_generic,
1435         .set_d0_lplu_state      = NULL,
1436         .set_d3_lplu_state      = e1000e_set_d3_lplu_state,
1437         .write_reg              = e1000_write_phy_reg_gg82563_80003es2lan,
1438         .cfg_on_link_up         = e1000_cfg_on_link_up_80003es2lan,
1439 };
1440
1441 static struct e1000_nvm_operations es2_nvm_ops = {
1442         .acquire                = e1000_acquire_nvm_80003es2lan,
1443         .read                   = e1000e_read_nvm_eerd,
1444         .release                = e1000_release_nvm_80003es2lan,
1445         .update                 = e1000e_update_nvm_checksum_generic,
1446         .valid_led_default      = e1000e_valid_led_default,
1447         .validate               = e1000e_validate_nvm_checksum_generic,
1448         .write                  = e1000_write_nvm_80003es2lan,
1449 };
1450
1451 struct e1000_info e1000_es2_info = {
1452         .mac                    = e1000_80003es2lan,
1453         .flags                  = FLAG_HAS_HW_VLAN_FILTER
1454                                   | FLAG_HAS_JUMBO_FRAMES
1455                                   | FLAG_HAS_WOL
1456                                   | FLAG_APME_IN_CTRL3
1457                                   | FLAG_RX_CSUM_ENABLED
1458                                   | FLAG_HAS_CTRLEXT_ON_LOAD
1459                                   | FLAG_RX_NEEDS_RESTART /* errata */
1460                                   | FLAG_TARC_SET_BIT_ZERO /* errata */
1461                                   | FLAG_APME_CHECK_PORT_B
1462                                   | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
1463                                   | FLAG_TIPG_MEDIUM_FOR_80003ESLAN,
1464         .pba                    = 38,
1465         .max_hw_frame_size      = DEFAULT_JUMBO,
1466         .get_variants           = e1000_get_variants_80003es2lan,
1467         .mac_ops                = &es2_mac_ops,
1468         .phy_ops                = &es2_phy_ops,
1469         .nvm_ops                = &es2_nvm_ops,
1470 };
1471