2 * AMD 10Gb Ethernet driver
4 * This file is available to you under your choice of the following two
9 * Copyright (c) 2014 Advanced Micro Devices, Inc.
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
24 * This file incorporates work covered by the following copyright and
26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28 * Inc. unless otherwise expressly agreed to in writing between Synopsys
31 * The Software IS NOT an item of Licensed Software or Licensed Product
32 * under any End User Software License Agreement or Agreement for Licensed
33 * Product with Synopsys or any supplement thereto. Permission is hereby
34 * granted, free of charge, to any person obtaining a copy of this software
35 * annotated with this license and the Software, to deal in the Software
36 * without restriction, including without limitation the rights to use,
37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38 * of the Software, and to permit persons to whom the Software is furnished
39 * to do so, subject to the following conditions:
41 * The above copyright notice and this permission notice shall be included
42 * in all copies or substantial portions of the Software.
44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54 * THE POSSIBILITY OF SUCH DAMAGE.
57 * License 2: Modified BSD
59 * Copyright (c) 2014 Advanced Micro Devices, Inc.
60 * All rights reserved.
62 * Redistribution and use in source and binary forms, with or without
63 * modification, are permitted provided that the following conditions are met:
64 * * Redistributions of source code must retain the above copyright
65 * notice, this list of conditions and the following disclaimer.
66 * * Redistributions in binary form must reproduce the above copyright
67 * notice, this list of conditions and the following disclaimer in the
68 * documentation and/or other materials provided with the distribution.
69 * * Neither the name of Advanced Micro Devices, Inc. nor the
70 * names of its contributors may be used to endorse or promote products
71 * derived from this software without specific prior written permission.
73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
84 * This file incorporates work covered by the following copyright and
86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
88 * Inc. unless otherwise expressly agreed to in writing between Synopsys
91 * The Software IS NOT an item of Licensed Software or Licensed Product
92 * under any End User Software License Agreement or Agreement for Licensed
93 * Product with Synopsys or any supplement thereto. Permission is hereby
94 * granted, free of charge, to any person obtaining a copy of this software
95 * annotated with this license and the Software, to deal in the Software
96 * without restriction, including without limitation the rights to use,
97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
98 * of the Software, and to permit persons to whom the Software is furnished
99 * to do so, subject to the following conditions:
101 * The above copyright notice and this permission notice shall be included
102 * in all copies or substantial portions of the Software.
104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
114 * THE POSSIBILITY OF SUCH DAMAGE.
120 #include <linux/dma-mapping.h>
121 #include <linux/netdevice.h>
122 #include <linux/workqueue.h>
123 #include <linux/phy.h>
124 #include <linux/if_vlan.h>
125 #include <linux/bitops.h>
126 #include <linux/ptp_clock_kernel.h>
127 #include <linux/clocksource.h>
128 #include <linux/net_tstamp.h>
129 #include <net/dcbnl.h>
131 #define XGBE_DRV_NAME "amd-xgbe"
132 #define XGBE_DRV_VERSION "1.0.0-a"
133 #define XGBE_DRV_DESC "AMD 10 Gigabit Ethernet Driver"
135 /* Descriptor related defines */
136 #define XGBE_TX_DESC_CNT 512
137 #define XGBE_TX_DESC_MIN_FREE (XGBE_TX_DESC_CNT >> 3)
138 #define XGBE_TX_DESC_MAX_PROC (XGBE_TX_DESC_CNT >> 1)
139 #define XGBE_RX_DESC_CNT 512
141 #define XGBE_TX_MAX_BUF_SIZE (0x3fff & ~(64 - 1))
143 #define XGBE_RX_MIN_BUF_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
144 #define XGBE_RX_BUF_ALIGN 64
145 #define XGBE_SKB_ALLOC_SIZE 256
146 #define XGBE_SPH_HDSMS_SIZE 2 /* Keep in sync with SKB_ALLOC_SIZE */
148 #define XGBE_MAX_DMA_CHANNELS 16
149 #define XGBE_MAX_QUEUES 16
151 /* DMA cache settings - Outer sharable, write-back, write-allocate */
152 #define XGBE_DMA_OS_AXDOMAIN 0x2
153 #define XGBE_DMA_OS_ARCACHE 0xb
154 #define XGBE_DMA_OS_AWCACHE 0xf
156 /* DMA cache settings - System, no caches used */
157 #define XGBE_DMA_SYS_AXDOMAIN 0x3
158 #define XGBE_DMA_SYS_ARCACHE 0x0
159 #define XGBE_DMA_SYS_AWCACHE 0x0
161 #define XGBE_DMA_INTERRUPT_MASK 0x31c7
163 #define XGMAC_MIN_PACKET 60
164 #define XGMAC_STD_PACKET_MTU 1500
165 #define XGMAC_MAX_STD_PACKET 1518
166 #define XGMAC_JUMBO_PACKET_MTU 9000
167 #define XGMAC_MAX_JUMBO_PACKET 9018
169 /* MDIO bus phy name */
170 #define XGBE_PHY_NAME "amd_xgbe_phy"
173 /* Device-tree clock names */
174 #define XGBE_DMA_CLOCK "dma_clk"
175 #define XGBE_PTP_CLOCK "ptp_clk"
176 #define XGBE_DMA_IRQS "amd,per-channel-interrupt"
178 /* Timestamp support - values based on 50MHz PTP clock
181 #define XGBE_TSTAMP_SSINC 20
182 #define XGBE_TSTAMP_SNSINC 0
184 /* Driver PMT macros */
185 #define XGMAC_DRIVER_CONTEXT 1
186 #define XGMAC_IOCTL_CONTEXT 2
188 #define XGBE_FIFO_MAX 81920
189 #define XGBE_FIFO_SIZE_B(x) (x)
190 #define XGBE_FIFO_SIZE_KB(x) (x * 1024)
192 #define XGBE_TC_MIN_QUANTUM 10
194 /* Helper macro for descriptor handling
195 * Always use XGBE_GET_DESC_DATA to access the descriptor data
196 * since the index is free-running and needs to be and-ed
197 * with the descriptor count value of the ring to index to
198 * the proper descriptor data.
200 #define XGBE_GET_DESC_DATA(_ring, _idx) \
202 ((_idx) & ((_ring)->rdesc_count - 1)))
204 /* Default coalescing parameters */
205 #define XGMAC_INIT_DMA_TX_USECS 50
206 #define XGMAC_INIT_DMA_TX_FRAMES 25
208 #define XGMAC_MAX_DMA_RIWT 0xff
209 #define XGMAC_INIT_DMA_RX_USECS 30
210 #define XGMAC_INIT_DMA_RX_FRAMES 25
212 /* Flow control queue count */
213 #define XGMAC_MAX_FLOW_CONTROL_QUEUES 8
215 /* Maximum MAC address hash table size (256 bits = 8 bytes) */
216 #define XGBE_MAC_HASH_TABLE_SIZE 8
218 /* Receive Side Scaling */
219 #define XGBE_RSS_HASH_KEY_SIZE 40
220 #define XGBE_RSS_MAX_TABLE_SIZE 256
221 #define XGBE_RSS_LOOKUP_TABLE_TYPE 0
222 #define XGBE_RSS_HASH_KEY_TYPE 1
224 struct xgbe_prv_data;
226 struct xgbe_packet_data {
227 unsigned int attributes;
231 unsigned int rdesc_count;
234 unsigned int header_len;
235 unsigned int tcp_header_len;
236 unsigned int tcp_payload_len;
239 unsigned short vlan_ctag;
244 enum pkt_hash_types rss_hash_type;
247 /* Common Rx and Tx descriptor mapping */
248 struct xgbe_ring_desc {
255 /* Page allocation related values */
256 struct xgbe_page_alloc {
258 unsigned int pages_len;
259 unsigned int pages_offset;
261 dma_addr_t pages_dma;
264 /* Ring entry buffer data */
265 struct xgbe_buffer_data {
266 struct xgbe_page_alloc pa;
267 struct xgbe_page_alloc pa_unmap;
270 unsigned int dma_len;
273 /* Structure used to hold information related to the descriptor
274 * and the packet associated with the descriptor (always use
275 * use the XGBE_GET_DESC_DATA macro to access this data from the ring)
277 struct xgbe_ring_data {
278 struct xgbe_ring_desc *rdesc; /* Virtual address of descriptor */
279 dma_addr_t rdesc_dma; /* DMA address of descriptor */
281 struct sk_buff *skb; /* Virtual address of SKB */
282 dma_addr_t skb_dma; /* DMA address of SKB data */
283 unsigned int skb_dma_len; /* Length of SKB DMA area */
284 unsigned int tso_header; /* TSO header indicator */
286 struct xgbe_buffer_data rx_hdr; /* Header locations */
287 struct xgbe_buffer_data rx_buf; /* Payload locations */
289 unsigned short hdr_len; /* Length of received header */
290 unsigned short len; /* Length of received Rx packet */
292 unsigned int interrupt; /* Interrupt indicator */
294 unsigned int mapped_as_page;
296 /* Incomplete receive save location. If the budget is exhausted
297 * or the last descriptor (last normal descriptor or a following
298 * context descriptor) has not been DMA'd yet the current state
299 * of the receive processing needs to be saved.
301 unsigned int state_saved;
303 unsigned int incomplete;
304 unsigned int context_next;
312 /* Ring lock - used just for TX rings at the moment */
315 /* Per packet related information */
316 struct xgbe_packet_data packet_data;
318 /* Virtual/DMA addresses and count of allocated descriptor memory */
319 struct xgbe_ring_desc *rdesc;
320 dma_addr_t rdesc_dma;
321 unsigned int rdesc_count;
323 /* Array of descriptor data corresponding the descriptor memory
324 * (always use the XGBE_GET_DESC_DATA macro to access this data)
326 struct xgbe_ring_data *rdata;
328 /* Page allocation for RX buffers */
329 struct xgbe_page_alloc rx_hdr_pa;
330 struct xgbe_page_alloc rx_buf_pa;
333 * cur - Tx: index of descriptor to be used for current transfer
334 * Rx: index of descriptor to check for packet availability
335 * dirty - Tx: index of descriptor to check for transfer complete
336 * Rx: count of descriptors in which a packet has been received
337 * (used with skb_realloc_index to refresh the ring)
342 /* Coalesce frame count used for interrupt bit setting */
343 unsigned int coalesce_count;
347 unsigned int queue_stopped;
348 unsigned short cur_mss;
349 unsigned short cur_vlan_ctag;
353 unsigned int realloc_index;
354 unsigned int realloc_threshold;
357 } ____cacheline_aligned;
359 /* Structure used to describe the descriptor rings associated with
362 struct xgbe_channel {
365 /* Address of private data area for device */
366 struct xgbe_prv_data *pdata;
368 /* Queue index and base address of queue's DMA registers */
369 unsigned int queue_index;
370 void __iomem *dma_regs;
372 /* Per channel interrupt irq number */
375 /* Netdev related settings */
376 struct napi_struct napi;
378 unsigned int saved_ier;
380 unsigned int tx_timer_active;
381 struct hrtimer tx_timer;
383 struct xgbe_ring *tx_ring;
384 struct xgbe_ring *rx_ring;
385 } ____cacheline_aligned;
388 XGMAC_INT_DMA_CH_SR_TI,
389 XGMAC_INT_DMA_CH_SR_TPS,
390 XGMAC_INT_DMA_CH_SR_TBU,
391 XGMAC_INT_DMA_CH_SR_RI,
392 XGMAC_INT_DMA_CH_SR_RBU,
393 XGMAC_INT_DMA_CH_SR_RPS,
394 XGMAC_INT_DMA_CH_SR_TI_RI,
395 XGMAC_INT_DMA_CH_SR_FBE,
399 enum xgbe_int_state {
400 XGMAC_INT_STATE_SAVE,
401 XGMAC_INT_STATE_RESTORE,
404 enum xgbe_mtl_fifo_size {
405 XGMAC_MTL_FIFO_SIZE_256 = 0x00,
406 XGMAC_MTL_FIFO_SIZE_512 = 0x01,
407 XGMAC_MTL_FIFO_SIZE_1K = 0x03,
408 XGMAC_MTL_FIFO_SIZE_2K = 0x07,
409 XGMAC_MTL_FIFO_SIZE_4K = 0x0f,
410 XGMAC_MTL_FIFO_SIZE_8K = 0x1f,
411 XGMAC_MTL_FIFO_SIZE_16K = 0x3f,
412 XGMAC_MTL_FIFO_SIZE_32K = 0x7f,
413 XGMAC_MTL_FIFO_SIZE_64K = 0xff,
414 XGMAC_MTL_FIFO_SIZE_128K = 0x1ff,
415 XGMAC_MTL_FIFO_SIZE_256K = 0x3ff,
418 struct xgbe_mmc_stats {
422 u64 txbroadcastframes_g;
423 u64 txmulticastframes_g;
425 u64 tx65to127octets_gb;
426 u64 tx128to255octets_gb;
427 u64 tx256to511octets_gb;
428 u64 tx512to1023octets_gb;
429 u64 tx1024tomaxoctets_gb;
430 u64 txunicastframes_gb;
431 u64 txmulticastframes_gb;
432 u64 txbroadcastframes_gb;
433 u64 txunderflowerror;
443 u64 rxbroadcastframes_g;
444 u64 rxmulticastframes_g;
451 u64 rx65to127octets_gb;
452 u64 rx128to255octets_gb;
453 u64 rx256to511octets_gb;
454 u64 rx512to1023octets_gb;
455 u64 rx1024tomaxoctets_gb;
456 u64 rxunicastframes_g;
458 u64 rxoutofrangetype;
466 int (*tx_complete)(struct xgbe_ring_desc *);
468 int (*set_promiscuous_mode)(struct xgbe_prv_data *, unsigned int);
469 int (*set_all_multicast_mode)(struct xgbe_prv_data *, unsigned int);
470 int (*add_mac_addresses)(struct xgbe_prv_data *);
471 int (*set_mac_address)(struct xgbe_prv_data *, u8 *addr);
473 int (*enable_rx_csum)(struct xgbe_prv_data *);
474 int (*disable_rx_csum)(struct xgbe_prv_data *);
476 int (*enable_rx_vlan_stripping)(struct xgbe_prv_data *);
477 int (*disable_rx_vlan_stripping)(struct xgbe_prv_data *);
478 int (*enable_rx_vlan_filtering)(struct xgbe_prv_data *);
479 int (*disable_rx_vlan_filtering)(struct xgbe_prv_data *);
480 int (*update_vlan_hash_table)(struct xgbe_prv_data *);
482 int (*read_mmd_regs)(struct xgbe_prv_data *, int, int);
483 void (*write_mmd_regs)(struct xgbe_prv_data *, int, int, int);
484 int (*set_gmii_speed)(struct xgbe_prv_data *);
485 int (*set_gmii_2500_speed)(struct xgbe_prv_data *);
486 int (*set_xgmii_speed)(struct xgbe_prv_data *);
488 void (*enable_tx)(struct xgbe_prv_data *);
489 void (*disable_tx)(struct xgbe_prv_data *);
490 void (*enable_rx)(struct xgbe_prv_data *);
491 void (*disable_rx)(struct xgbe_prv_data *);
493 void (*powerup_tx)(struct xgbe_prv_data *);
494 void (*powerdown_tx)(struct xgbe_prv_data *);
495 void (*powerup_rx)(struct xgbe_prv_data *);
496 void (*powerdown_rx)(struct xgbe_prv_data *);
498 int (*init)(struct xgbe_prv_data *);
499 int (*exit)(struct xgbe_prv_data *);
501 int (*enable_int)(struct xgbe_channel *, enum xgbe_int);
502 int (*disable_int)(struct xgbe_channel *, enum xgbe_int);
503 void (*dev_xmit)(struct xgbe_channel *);
504 int (*dev_read)(struct xgbe_channel *);
505 void (*tx_desc_init)(struct xgbe_channel *);
506 void (*rx_desc_init)(struct xgbe_channel *);
507 void (*rx_desc_reset)(struct xgbe_ring_data *);
508 void (*tx_desc_reset)(struct xgbe_ring_data *);
509 int (*is_last_desc)(struct xgbe_ring_desc *);
510 int (*is_context_desc)(struct xgbe_ring_desc *);
513 int (*config_tx_flow_control)(struct xgbe_prv_data *);
514 int (*config_rx_flow_control)(struct xgbe_prv_data *);
516 /* For RX coalescing */
517 int (*config_rx_coalesce)(struct xgbe_prv_data *);
518 int (*config_tx_coalesce)(struct xgbe_prv_data *);
519 unsigned int (*usec_to_riwt)(struct xgbe_prv_data *, unsigned int);
520 unsigned int (*riwt_to_usec)(struct xgbe_prv_data *, unsigned int);
522 /* For RX and TX threshold config */
523 int (*config_rx_threshold)(struct xgbe_prv_data *, unsigned int);
524 int (*config_tx_threshold)(struct xgbe_prv_data *, unsigned int);
526 /* For RX and TX Store and Forward Mode config */
527 int (*config_rsf_mode)(struct xgbe_prv_data *, unsigned int);
528 int (*config_tsf_mode)(struct xgbe_prv_data *, unsigned int);
530 /* For TX DMA Operate on Second Frame config */
531 int (*config_osp_mode)(struct xgbe_prv_data *);
533 /* For RX and TX PBL config */
534 int (*config_rx_pbl_val)(struct xgbe_prv_data *);
535 int (*get_rx_pbl_val)(struct xgbe_prv_data *);
536 int (*config_tx_pbl_val)(struct xgbe_prv_data *);
537 int (*get_tx_pbl_val)(struct xgbe_prv_data *);
538 int (*config_pblx8)(struct xgbe_prv_data *);
540 /* For MMC statistics */
541 void (*rx_mmc_int)(struct xgbe_prv_data *);
542 void (*tx_mmc_int)(struct xgbe_prv_data *);
543 void (*read_mmc_stats)(struct xgbe_prv_data *);
545 /* For Timestamp config */
546 int (*config_tstamp)(struct xgbe_prv_data *, unsigned int);
547 void (*update_tstamp_addend)(struct xgbe_prv_data *, unsigned int);
548 void (*set_tstamp_time)(struct xgbe_prv_data *, unsigned int sec,
550 u64 (*get_tstamp_time)(struct xgbe_prv_data *);
551 u64 (*get_tx_tstamp)(struct xgbe_prv_data *);
553 /* For Data Center Bridging config */
554 void (*config_dcb_tc)(struct xgbe_prv_data *);
555 void (*config_dcb_pfc)(struct xgbe_prv_data *);
557 /* For Receive Side Scaling */
558 int (*enable_rss)(struct xgbe_prv_data *);
559 int (*disable_rss)(struct xgbe_prv_data *);
562 struct xgbe_desc_if {
563 int (*alloc_ring_resources)(struct xgbe_prv_data *);
564 void (*free_ring_resources)(struct xgbe_prv_data *);
565 int (*map_tx_skb)(struct xgbe_channel *, struct sk_buff *);
566 void (*realloc_rx_buffer)(struct xgbe_channel *);
567 void (*unmap_rdata)(struct xgbe_prv_data *, struct xgbe_ring_data *);
568 void (*wrapper_tx_desc_init)(struct xgbe_prv_data *);
569 void (*wrapper_rx_desc_init)(struct xgbe_prv_data *);
572 /* This structure contains flags that indicate what hardware features
573 * or configurations are present in the device.
575 struct xgbe_hw_features {
577 unsigned int version;
579 /* HW Feature Register0 */
580 unsigned int gmii; /* 1000 Mbps support */
581 unsigned int vlhash; /* VLAN Hash Filter */
582 unsigned int sma; /* SMA(MDIO) Interface */
583 unsigned int rwk; /* PMT remote wake-up packet */
584 unsigned int mgk; /* PMT magic packet */
585 unsigned int mmc; /* RMON module */
586 unsigned int aoe; /* ARP Offload */
587 unsigned int ts; /* IEEE 1588-2008 Adavanced Timestamp */
588 unsigned int eee; /* Energy Efficient Ethernet */
589 unsigned int tx_coe; /* Tx Checksum Offload */
590 unsigned int rx_coe; /* Rx Checksum Offload */
591 unsigned int addn_mac; /* Additional MAC Addresses */
592 unsigned int ts_src; /* Timestamp Source */
593 unsigned int sa_vlan_ins; /* Source Address or VLAN Insertion */
595 /* HW Feature Register1 */
596 unsigned int rx_fifo_size; /* MTL Receive FIFO Size */
597 unsigned int tx_fifo_size; /* MTL Transmit FIFO Size */
598 unsigned int adv_ts_hi; /* Advance Timestamping High Word */
599 unsigned int dcb; /* DCB Feature */
600 unsigned int sph; /* Split Header Feature */
601 unsigned int tso; /* TCP Segmentation Offload */
602 unsigned int dma_debug; /* DMA Debug Registers */
603 unsigned int rss; /* Receive Side Scaling */
604 unsigned int tc_cnt; /* Number of Traffic Classes */
605 unsigned int hash_table_size; /* Hash Table Size */
606 unsigned int l3l4_filter_num; /* Number of L3-L4 Filters */
608 /* HW Feature Register2 */
609 unsigned int rx_q_cnt; /* Number of MTL Receive Queues */
610 unsigned int tx_q_cnt; /* Number of MTL Transmit Queues */
611 unsigned int rx_ch_cnt; /* Number of DMA Receive Channels */
612 unsigned int tx_ch_cnt; /* Number of DMA Transmit Channels */
613 unsigned int pps_out_num; /* Number of PPS outputs */
614 unsigned int aux_snap_num; /* Number of Aux snapshot inputs */
617 struct xgbe_prv_data {
618 struct net_device *netdev;
619 struct platform_device *pdev;
622 /* XGMAC/XPCS related mmio registers */
623 void __iomem *xgmac_regs; /* XGMAC CSRs */
624 void __iomem *xpcs_regs; /* XPCS MMD registers */
626 /* Overall device lock */
629 /* XPCS indirect addressing mutex */
630 struct mutex xpcs_mutex;
632 /* RSS addressing mutex */
633 struct mutex rss_mutex;
636 unsigned int per_channel_irq;
638 struct xgbe_hw_if hw_if;
639 struct xgbe_desc_if desc_if;
641 /* AXI DMA settings */
642 unsigned int axdomain;
643 unsigned int arcache;
644 unsigned int awcache;
646 /* Rings for Tx/Rx on a DMA channel */
647 struct xgbe_channel *channel;
648 unsigned int channel_count;
649 unsigned int tx_ring_count;
650 unsigned int tx_desc_count;
651 unsigned int rx_ring_count;
652 unsigned int rx_desc_count;
654 unsigned int tx_q_count;
655 unsigned int rx_q_count;
657 /* Tx/Rx common settings */
661 unsigned int tx_sf_mode;
662 unsigned int tx_threshold;
664 unsigned int tx_osp_mode;
667 unsigned int rx_sf_mode;
668 unsigned int rx_threshold;
671 /* Tx coalescing settings */
672 unsigned int tx_usecs;
673 unsigned int tx_frames;
675 /* Rx coalescing settings */
676 unsigned int rx_riwt;
677 unsigned int rx_frames;
679 /* Current Rx buffer size */
680 unsigned int rx_buf_size;
682 /* Flow control settings */
683 unsigned int pause_autoneg;
684 unsigned int tx_pause;
685 unsigned int rx_pause;
687 /* Receive Side Scaling settings */
688 u8 rss_key[XGBE_RSS_HASH_KEY_SIZE];
689 u32 rss_table[XGBE_RSS_MAX_TABLE_SIZE];
693 struct module *phy_module;
697 struct phy_device *phydev;
701 /* Current PHY settings */
702 phy_interface_t phy_mode;
705 unsigned int phy_tx_pause;
706 unsigned int phy_rx_pause;
708 /* Netdev related settings */
709 netdev_features_t netdev_features;
710 struct napi_struct napi;
711 struct xgbe_mmc_stats mmc_stats;
713 /* Filtering support */
714 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
720 /* Timestamp support */
721 spinlock_t tstamp_lock;
722 struct ptp_clock_info ptp_clock_info;
723 struct ptp_clock *ptp_clock;
724 struct hwtstamp_config tstamp_config;
725 struct cyclecounter tstamp_cc;
726 struct timecounter tstamp_tc;
727 unsigned int tstamp_addend;
728 struct work_struct tx_tstamp_work;
729 struct sk_buff *tx_tstamp_skb;
733 struct ieee_ets *ets;
734 struct ieee_pfc *pfc;
735 unsigned int q2tc_map[XGBE_MAX_QUEUES];
736 unsigned int prio2q_map[IEEE_8021QAZ_MAX_TCS];
738 /* Hardware features of the device */
739 struct xgbe_hw_features hw_feat;
741 /* Device restart work structure */
742 struct work_struct restart_work;
744 /* Keeps track of power mode */
745 unsigned int power_down;
747 #ifdef CONFIG_DEBUG_FS
748 struct dentry *xgbe_debugfs;
750 unsigned int debugfs_xgmac_reg;
752 unsigned int debugfs_xpcs_mmd;
753 unsigned int debugfs_xpcs_reg;
757 /* Function prototypes*/
759 void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *);
760 void xgbe_init_function_ptrs_desc(struct xgbe_desc_if *);
761 struct net_device_ops *xgbe_get_netdev_ops(void);
762 struct ethtool_ops *xgbe_get_ethtool_ops(void);
763 #ifdef CONFIG_AMD_XGBE_DCB
764 const struct dcbnl_rtnl_ops *xgbe_get_dcbnl_ops(void);
767 int xgbe_mdio_register(struct xgbe_prv_data *);
768 void xgbe_mdio_unregister(struct xgbe_prv_data *);
769 void xgbe_dump_phy_registers(struct xgbe_prv_data *);
770 void xgbe_ptp_register(struct xgbe_prv_data *);
771 void xgbe_ptp_unregister(struct xgbe_prv_data *);
772 void xgbe_dump_tx_desc(struct xgbe_ring *, unsigned int, unsigned int,
774 void xgbe_dump_rx_desc(struct xgbe_ring *, struct xgbe_ring_desc *,
776 void xgbe_print_pkt(struct net_device *, struct sk_buff *, bool);
777 void xgbe_get_all_hw_features(struct xgbe_prv_data *);
778 int xgbe_powerup(struct net_device *, unsigned int);
779 int xgbe_powerdown(struct net_device *, unsigned int);
780 void xgbe_init_rx_coalesce(struct xgbe_prv_data *);
781 void xgbe_init_tx_coalesce(struct xgbe_prv_data *);
783 #ifdef CONFIG_DEBUG_FS
784 void xgbe_debugfs_init(struct xgbe_prv_data *);
785 void xgbe_debugfs_exit(struct xgbe_prv_data *);
787 static inline void xgbe_debugfs_init(struct xgbe_prv_data *pdata) {}
788 static inline void xgbe_debugfs_exit(struct xgbe_prv_data *pdata) {}
789 #endif /* CONFIG_DEBUG_FS */
791 /* NOTE: Uncomment for TX and RX DESCRIPTOR DUMP in KERNEL LOG */
793 #define XGMAC_ENABLE_TX_DESC_DUMP
794 #define XGMAC_ENABLE_RX_DESC_DUMP
797 /* NOTE: Uncomment for TX and RX PACKET DUMP in KERNEL LOG */
799 #define XGMAC_ENABLE_TX_PKT_DUMP
800 #define XGMAC_ENABLE_RX_PKT_DUMP
803 /* NOTE: Uncomment for function trace log messages in KERNEL LOG */
809 /* For debug prints */
811 #define DBGPR(x...) pr_alert(x)
812 #define DBGPHY_REGS(x...) xgbe_dump_phy_registers(x)
814 #define DBGPR(x...) do { } while (0)
815 #define DBGPHY_REGS(x...) do { } while (0)
819 #define DBGPR_MDIO(x...) pr_alert(x)
821 #define DBGPR_MDIO(x...) do { } while (0)