drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c

   1 /* Copyright 2008-2013 Broadcom Corporation
   2  * Copyright (c) 2014 QLogic Corporation
   3  * All rights reserved
   4  *
   5  * Unless you and QLogic execute a separate written software license
   6  * agreement governing use of this software, this software is licensed to you
   7  * under the terms of the GNU General Public License version 2, available
   8  * at http://www.gnu.org/licenses/gpl-2.0.html (the "GPL").
   9  *
  10  * Notwithstanding the above, under no circumstances may you combine this
  11  * software in any way with any other Qlogic software provided under a
  12  * license other than the GPL, without Qlogic's express prior written
  13  * consent.
  14  *
  15  * Written by Yaniv Rosner
  16  *
  17  */
  18
  19 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  20
  21 #include <linux/kernel.h>
  22 #include <linux/errno.h>
  23 #include <linux/pci.h>
  24 #include <linux/netdevice.h>
  25 #include <linux/delay.h>
  26 #include <linux/ethtool.h>
  27 #include <linux/mutex.h>
  28
  29 #include "bnx2x.h"
  30 #include "bnx2x_cmn.h"
  31
  32 typedef int (*read_sfp_module_eeprom_func_p)(struct bnx2x_phy *phy,
  33                                              struct link_params *params,
  34                                              u8 dev_addr, u16 addr, u8 byte_cnt,
  35                                              u8 *o_buf, u8);
  36 /********************************************************/
  37 #define ETH_HLEN                        14
  38 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
  39 #define ETH_OVREHEAD                    (ETH_HLEN + 8 + 8)
  40 #define ETH_MIN_PACKET_SIZE             60
  41 #define ETH_MAX_PACKET_SIZE             1500
  42 #define ETH_MAX_JUMBO_PACKET_SIZE       9600
  43 #define MDIO_ACCESS_TIMEOUT             1000
  44 #define WC_LANE_MAX                     4
  45 #define I2C_SWITCH_WIDTH                2
  46 #define I2C_BSC0                        0
  47 #define I2C_BSC1                        1
  48 #define I2C_WA_RETRY_CNT                3
  49 #define I2C_WA_PWR_ITER                 (I2C_WA_RETRY_CNT - 1)
  50 #define MCPR_IMC_COMMAND_READ_OP        1
  51 #define MCPR_IMC_COMMAND_WRITE_OP       2
  52
  53 /* LED Blink rate that will achieve ~15.9Hz */
  54 #define LED_BLINK_RATE_VAL_E3           354
  55 #define LED_BLINK_RATE_VAL_E1X_E2       480
  56 /***********************************************************/
  57 /*                      Shortcut definitions               */
  58 /***********************************************************/
  59
  60 #define NIG_LATCH_BC_ENABLE_MI_INT 0
  61
  62 #define NIG_STATUS_EMAC0_MI_INT \
  63                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
  64 #define NIG_STATUS_XGXS0_LINK10G \
  65                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
  66 #define NIG_STATUS_XGXS0_LINK_STATUS \
  67                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
  68 #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
  69                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
  70 #define NIG_STATUS_SERDES0_LINK_STATUS \
  71                 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
  72 #define NIG_MASK_MI_INT \
  73                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
  74 #define NIG_MASK_XGXS0_LINK10G \
  75                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
  76 #define NIG_MASK_XGXS0_LINK_STATUS \
  77                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
  78 #define NIG_MASK_SERDES0_LINK_STATUS \
  79                 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
  80
  81 #define MDIO_AN_CL73_OR_37_COMPLETE \
  82                 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
  83                  MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
  84
  85 #define XGXS_RESET_BITS \
  86         (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW |   \
  87          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ |      \
  88          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN |    \
  89          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
  90          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
  91
  92 #define SERDES_RESET_BITS \
  93         (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
  94          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ |    \
  95          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN |  \
  96          MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
  97
  98 #define AUTONEG_CL37            SHARED_HW_CFG_AN_ENABLE_CL37
  99 #define AUTONEG_CL73            SHARED_HW_CFG_AN_ENABLE_CL73
 100 #define AUTONEG_BAM             SHARED_HW_CFG_AN_ENABLE_BAM
 101 #define AUTONEG_PARALLEL \
 102                                 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
 103 #define AUTONEG_SGMII_FIBER_AUTODET \
 104                                 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
 105 #define AUTONEG_REMOTE_PHY      SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
 106
 107 #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
 108                         MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
 109 #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
 110                         MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
 111 #define GP_STATUS_SPEED_MASK \
 112                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
 113 #define GP_STATUS_10M   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
 114 #define GP_STATUS_100M  MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
 115 #define GP_STATUS_1G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
 116 #define GP_STATUS_2_5G  MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
 117 #define GP_STATUS_5G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
 118 #define GP_STATUS_6G    MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
 119 #define GP_STATUS_10G_HIG \
 120                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
 121 #define GP_STATUS_10G_CX4 \
 122                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
 123 #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
 124 #define GP_STATUS_10G_KX4 \
 125                         MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
 126 #define GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR
 127 #define GP_STATUS_10G_XFI   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI
 128 #define GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS
 129 #define GP_STATUS_10G_SFI   MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI
 130 #define GP_STATUS_20G_KR2 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2
 131 #define LINK_10THD              LINK_STATUS_SPEED_AND_DUPLEX_10THD
 132 #define LINK_10TFD              LINK_STATUS_SPEED_AND_DUPLEX_10TFD
 133 #define LINK_100TXHD            LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
 134 #define LINK_100T4              LINK_STATUS_SPEED_AND_DUPLEX_100T4
 135 #define LINK_100TXFD            LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
 136 #define LINK_1000THD            LINK_STATUS_SPEED_AND_DUPLEX_1000THD
 137 #define LINK_1000TFD            LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
 138 #define LINK_1000XFD            LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
 139 #define LINK_2500THD            LINK_STATUS_SPEED_AND_DUPLEX_2500THD
 140 #define LINK_2500TFD            LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
 141 #define LINK_2500XFD            LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
 142 #define LINK_10GTFD             LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
 143 #define LINK_10GXFD             LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
 144 #define LINK_20GTFD             LINK_STATUS_SPEED_AND_DUPLEX_20GTFD
 145 #define LINK_20GXFD             LINK_STATUS_SPEED_AND_DUPLEX_20GXFD
 146
 147 #define LINK_UPDATE_MASK \
 148                         (LINK_STATUS_SPEED_AND_DUPLEX_MASK | \
 149                          LINK_STATUS_LINK_UP | \
 150                          LINK_STATUS_PHYSICAL_LINK_FLAG | \
 151                          LINK_STATUS_AUTO_NEGOTIATE_COMPLETE | \
 152                          LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK | \
 153                          LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK | \
 154                          LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK | \
 155                          LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE | \
 156                          LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
 157
 158 #define SFP_EEPROM_CON_TYPE_ADDR                0x2
 159         #define SFP_EEPROM_CON_TYPE_VAL_UNKNOWN 0x0
 160         #define SFP_EEPROM_CON_TYPE_VAL_LC      0x7
 161         #define SFP_EEPROM_CON_TYPE_VAL_COPPER  0x21
 162         #define SFP_EEPROM_CON_TYPE_VAL_RJ45    0x22
 163
 164
 165 #define SFP_EEPROM_10G_COMP_CODE_ADDR           0x3
 166         #define SFP_EEPROM_10G_COMP_CODE_SR_MASK        (1<<4)
 167         #define SFP_EEPROM_10G_COMP_CODE_LR_MASK        (1<<5)
 168         #define SFP_EEPROM_10G_COMP_CODE_LRM_MASK       (1<<6)
 169
 170 #define SFP_EEPROM_1G_COMP_CODE_ADDR            0x6
 171         #define SFP_EEPROM_1G_COMP_CODE_SX      (1<<0)
 172         #define SFP_EEPROM_1G_COMP_CODE_LX      (1<<1)
 173         #define SFP_EEPROM_1G_COMP_CODE_CX      (1<<2)
 174         #define SFP_EEPROM_1G_COMP_CODE_BASE_T  (1<<3)
 175
 176 #define SFP_EEPROM_FC_TX_TECH_ADDR              0x8
 177         #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
 178         #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE  0x8
 179
 180 #define SFP_EEPROM_OPTIONS_ADDR                 0x40
 181         #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
 182 #define SFP_EEPROM_OPTIONS_SIZE                 2
 183
 184 #define EDC_MODE_LINEAR                         0x0022
 185 #define EDC_MODE_LIMITING                               0x0044
 186 #define EDC_MODE_PASSIVE_DAC                    0x0055
 187 #define EDC_MODE_ACTIVE_DAC                     0x0066
 188
 189 /* ETS defines*/
 190 #define DCBX_INVALID_COS                                        (0xFF)
 191
 192 #define ETS_BW_LIMIT_CREDIT_UPPER_BOUND         (0x5000)
 193 #define ETS_BW_LIMIT_CREDIT_WEIGHT              (0x5000)
 194 #define ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS             (1360)
 195 #define ETS_E3B0_NIG_MIN_W_VAL_20GBPS                   (2720)
 196 #define ETS_E3B0_PBF_MIN_W_VAL                          (10000)
 197
 198 #define MAX_PACKET_SIZE                                 (9700)
 199 #define MAX_KR_LINK_RETRY                               4
 200 #define DEFAULT_TX_DRV_BRDCT            2
 201 #define DEFAULT_TX_DRV_IFIR             0
 202 #define DEFAULT_TX_DRV_POST2            3
 203 #define DEFAULT_TX_DRV_IPRE_DRIVER      6
 204
 205 /**********************************************************/
 206 /*                     INTERFACE                          */
 207 /**********************************************************/
 208
 209 #define CL22_WR_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
 210         bnx2x_cl45_write(_bp, _phy, \
 211                 (_phy)->def_md_devad, \
 212                 (_bank + (_addr & 0xf)), \
 213                 _val)
 214
 215 #define CL22_RD_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
 216         bnx2x_cl45_read(_bp, _phy, \
 217                 (_phy)->def_md_devad, \
 218                 (_bank + (_addr & 0xf)), \
 219                 _val)
 220
 221 static int bnx2x_check_half_open_conn(struct link_params *params,
 222                                       struct link_vars *vars, u8 notify);
 223 static int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
 224                                       struct link_params *params);
 225
 226 static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
 227 {
 228         u32 val = REG_RD(bp, reg);
 229
 230         val |= bits;
 231         REG_WR(bp, reg, val);
 232         return val;
 233 }
 234
 235 static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
 236 {
 237         u32 val = REG_RD(bp, reg);
 238
 239         val &= ~bits;
 240         REG_WR(bp, reg, val);
 241         return val;
 242 }
 243
 244 /*
 245  * bnx2x_check_lfa - This function checks if link reinitialization is required,
 246  *                   or link flap can be avoided.
 247  *
 248  * @params:     link parameters
 249  * Returns 0 if Link Flap Avoidance conditions are met otherwise, the failed
 250  *         condition code.
 251  */
 252 static int bnx2x_check_lfa(struct link_params *params)
 253 {
 254         u32 link_status, cfg_idx, lfa_mask, cfg_size;
 255         u32 cur_speed_cap_mask, cur_req_fc_auto_adv, additional_config;
 256         u32 saved_val, req_val, eee_status;
 257         struct bnx2x *bp = params->bp;
 258
 259         additional_config =
 260                 REG_RD(bp, params->lfa_base +
 261                            offsetof(struct shmem_lfa, additional_config));
 262
 263         /* NOTE: must be first condition checked -
 264         * to verify DCC bit is cleared in any case!
 265         */
 266         if (additional_config & NO_LFA_DUE_TO_DCC_MASK) {
 267                 DP(NETIF_MSG_LINK, "No LFA due to DCC flap after clp exit\n");
 268                 REG_WR(bp, params->lfa_base +
 269                            offsetof(struct shmem_lfa, additional_config),
 270                        additional_config & ~NO_LFA_DUE_TO_DCC_MASK);
 271                 return LFA_DCC_LFA_DISABLED;
 272         }
 273
 274         /* Verify that link is up */
 275         link_status = REG_RD(bp, params->shmem_base +
 276                              offsetof(struct shmem_region,
 277                                       port_mb[params->port].link_status));
 278         if (!(link_status & LINK_STATUS_LINK_UP))
 279                 return LFA_LINK_DOWN;
 280
 281         /* if loaded after BOOT from SAN, don't flap the link in any case and
 282          * rely on link set by preboot driver
 283          */
 284         if (params->feature_config_flags & FEATURE_CONFIG_BOOT_FROM_SAN)
 285                 return 0;
 286
 287         /* Verify that loopback mode is not set */
 288         if (params->loopback_mode)
 289                 return LFA_LOOPBACK_ENABLED;
 290
 291         /* Verify that MFW supports LFA */
 292         if (!params->lfa_base)
 293                 return LFA_MFW_IS_TOO_OLD;
 294
 295         if (params->num_phys == 3) {
 296                 cfg_size = 2;
 297                 lfa_mask = 0xffffffff;
 298         } else {
 299                 cfg_size = 1;
 300                 lfa_mask = 0xffff;
 301         }
 302
 303         /* Compare Duplex */
 304         saved_val = REG_RD(bp, params->lfa_base +
 305                            offsetof(struct shmem_lfa, req_duplex));
 306         req_val = params->req_duplex[0] | (params->req_duplex[1] << 16);
 307         if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
 308                 DP(NETIF_MSG_LINK, "Duplex mismatch %x vs. %x\n",
 309                                (saved_val & lfa_mask), (req_val & lfa_mask));
 310                 return LFA_DUPLEX_MISMATCH;
 311         }
 312         /* Compare Flow Control */
 313         saved_val = REG_RD(bp, params->lfa_base +
 314                            offsetof(struct shmem_lfa, req_flow_ctrl));
 315         req_val = params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16);
 316         if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
 317                 DP(NETIF_MSG_LINK, "Flow control mismatch %x vs. %x\n",
 318                                (saved_val & lfa_mask), (req_val & lfa_mask));
 319                 return LFA_FLOW_CTRL_MISMATCH;
 320         }
 321         /* Compare Link Speed */
 322         saved_val = REG_RD(bp, params->lfa_base +
 323                            offsetof(struct shmem_lfa, req_line_speed));
 324         req_val = params->req_line_speed[0] | (params->req_line_speed[1] << 16);
 325         if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
 326                 DP(NETIF_MSG_LINK, "Link speed mismatch %x vs. %x\n",
 327                                (saved_val & lfa_mask), (req_val & lfa_mask));
 328                 return LFA_LINK_SPEED_MISMATCH;
 329         }
 330
 331         for (cfg_idx = 0; cfg_idx < cfg_size; cfg_idx++) {
 332                 cur_speed_cap_mask = REG_RD(bp, params->lfa_base +
 333                                             offsetof(struct shmem_lfa,
 334                                                      speed_cap_mask[cfg_idx]));
 335
 336                 if (cur_speed_cap_mask != params->speed_cap_mask[cfg_idx]) {
 337                         DP(NETIF_MSG_LINK, "Speed Cap mismatch %x vs. %x\n",
 338                                        cur_speed_cap_mask,
 339                                        params->speed_cap_mask[cfg_idx]);
 340                         return LFA_SPEED_CAP_MISMATCH;
 341                 }
 342         }
 343
 344         cur_req_fc_auto_adv =
 345                 REG_RD(bp, params->lfa_base +
 346                        offsetof(struct shmem_lfa, additional_config)) &
 347                 REQ_FC_AUTO_ADV_MASK;
 348
 349         if ((u16)cur_req_fc_auto_adv != params->req_fc_auto_adv) {
 350                 DP(NETIF_MSG_LINK, "Flow Ctrl AN mismatch %x vs. %x\n",
 351                                cur_req_fc_auto_adv, params->req_fc_auto_adv);
 352                 return LFA_FLOW_CTRL_MISMATCH;
 353         }
 354
 355         eee_status = REG_RD(bp, params->shmem2_base +
 356                             offsetof(struct shmem2_region,
 357                                      eee_status[params->port]));
 358
 359         if (((eee_status & SHMEM_EEE_LPI_REQUESTED_BIT) ^
 360              (params->eee_mode & EEE_MODE_ENABLE_LPI)) ||
 361             ((eee_status & SHMEM_EEE_REQUESTED_BIT) ^
 362              (params->eee_mode & EEE_MODE_ADV_LPI))) {
 363                 DP(NETIF_MSG_LINK, "EEE mismatch %x vs. %x\n", params->eee_mode,
 364                                eee_status);
 365                 return LFA_EEE_MISMATCH;
 366         }
 367
 368         /* LFA conditions are met */
 369         return 0;
 370 }
 371 /******************************************************************/
 372 /*                      EPIO/GPIO section                         */
 373 /******************************************************************/
 374 static void bnx2x_get_epio(struct bnx2x *bp, u32 epio_pin, u32 *en)
 375 {
 376         u32 epio_mask, gp_oenable;
 377         *en = 0;
 378         /* Sanity check */
 379         if (epio_pin > 31) {
 380                 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to get\n", epio_pin);
 381                 return;
 382         }
 383
 384         epio_mask = 1 << epio_pin;
 385         /* Set this EPIO to output */
 386         gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
 387         REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask);
 388
 389         *en = (REG_RD(bp, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin;
 390 }
 391 static void bnx2x_set_epio(struct bnx2x *bp, u32 epio_pin, u32 en)
 392 {
 393         u32 epio_mask, gp_output, gp_oenable;
 394
 395         /* Sanity check */
 396         if (epio_pin > 31) {
 397                 DP(NETIF_MSG_LINK, "Invalid EPIO pin %d to set\n", epio_pin);
 398                 return;
 399         }
 400         DP(NETIF_MSG_LINK, "Setting EPIO pin %d to %d\n", epio_pin, en);
 401         epio_mask = 1 << epio_pin;
 402         /* Set this EPIO to output */
 403         gp_output = REG_RD(bp, MCP_REG_MCPR_GP_OUTPUTS);
 404         if (en)
 405                 gp_output |= epio_mask;
 406         else
 407                 gp_output &= ~epio_mask;
 408
 409         REG_WR(bp, MCP_REG_MCPR_GP_OUTPUTS, gp_output);
 410
 411         /* Set the value for this EPIO */
 412         gp_oenable = REG_RD(bp, MCP_REG_MCPR_GP_OENABLE);
 413         REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask);
 414 }
 415
 416 static void bnx2x_set_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 val)
 417 {
 418         if (pin_cfg == PIN_CFG_NA)
 419                 return;
 420         if (pin_cfg >= PIN_CFG_EPIO0) {
 421                 bnx2x_set_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
 422         } else {
 423                 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
 424                 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
 425                 bnx2x_set_gpio(bp, gpio_num, (u8)val, gpio_port);
 426         }
 427 }
 428
 429 static u32 bnx2x_get_cfg_pin(struct bnx2x *bp, u32 pin_cfg, u32 *val)
 430 {
 431         if (pin_cfg == PIN_CFG_NA)
 432                 return -EINVAL;
 433         if (pin_cfg >= PIN_CFG_EPIO0) {
 434                 bnx2x_get_epio(bp, pin_cfg - PIN_CFG_EPIO0, val);
 435         } else {
 436                 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
 437                 u8 gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
 438                 *val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
 439         }
 440         return 0;
 441
 442 }
 443 /******************************************************************/
 444 /*                              ETS section                       */
 445 /******************************************************************/
 446 static void bnx2x_ets_e2e3a0_disabled(struct link_params *params)
 447 {
 448         /* ETS disabled configuration*/
 449         struct bnx2x *bp = params->bp;
 450
 451         DP(NETIF_MSG_LINK, "ETS E2E3 disabled configuration\n");
 452
 453         /* mapping between entry  priority to client number (0,1,2 -debug and
 454          * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
 455          * 3bits client num.
 456          *   PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
 457          * cos1-100     cos0-011     dbg1-010     dbg0-001     MCP-000
 458          */
 459
 460         REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688);
 461         /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
 462          * as strict.  Bits 0,1,2 - debug and management entries, 3 -
 463          * COS0 entry, 4 - COS1 entry.
 464          * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
 465          * bit4   bit3    bit2   bit1     bit0
 466          * MCP and debug are strict
 467          */
 468
 469         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
 470         /* defines which entries (clients) are subjected to WFQ arbitration */
 471         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
 472         /* For strict priority entries defines the number of consecutive
 473          * slots for the highest priority.
 474          */
 475         REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
 476         /* mapping between the CREDIT_WEIGHT registers and actual client
 477          * numbers
 478          */
 479         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0);
 480         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0);
 481         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0);
 482
 483         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0);
 484         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0);
 485         REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0);
 486         /* ETS mode disable */
 487         REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
 488         /* If ETS mode is enabled (there is no strict priority) defines a WFQ
 489          * weight for COS0/COS1.
 490          */
 491         REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710);
 492         REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710);
 493         /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */
 494         REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680);
 495         REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680);
 496         /* Defines the number of consecutive slots for the strict priority */
 497         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
 498 }
 499 /******************************************************************************
 500 * Description:
 501 *       Getting min_w_val will be set according to line speed .
 502 *.
 503 ******************************************************************************/
 504 static u32 bnx2x_ets_get_min_w_val_nig(const struct link_vars *vars)
 505 {
 506         u32 min_w_val = 0;
 507         /* Calculate min_w_val.*/
 508         if (vars->link_up) {
 509                 if (vars->line_speed == SPEED_20000)
 510                         min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
 511                 else
 512                         min_w_val = ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS;
 513         } else
 514                 min_w_val = ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
 515         /* If the link isn't up (static configuration for example ) The
 516          * link will be according to 20GBPS.
 517          */
 518         return min_w_val;
 519 }
 520 /******************************************************************************
 521 * Description:
 522 *       Getting credit upper bound form min_w_val.
 523 *.
 524 ******************************************************************************/
 525 static u32 bnx2x_ets_get_credit_upper_bound(const u32 min_w_val)
 526 {
 527         const u32 credit_upper_bound = (u32)MAXVAL((150 * min_w_val),
 528                                                 MAX_PACKET_SIZE);
 529         return credit_upper_bound;
 530 }
 531 /******************************************************************************
 532 * Description:
 533 *       Set credit upper bound for NIG.
 534 *.
 535 ******************************************************************************/
 536 static void bnx2x_ets_e3b0_set_credit_upper_bound_nig(
 537         const struct link_params *params,
 538         const u32 min_w_val)
 539 {
 540         struct bnx2x *bp = params->bp;
 541         const u8 port = params->port;
 542         const u32 credit_upper_bound =
 543             bnx2x_ets_get_credit_upper_bound(min_w_val);
 544
 545         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 :
 546                 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, credit_upper_bound);
 547         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 :
 548                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, credit_upper_bound);
 549         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 :
 550                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2, credit_upper_bound);
 551         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 :
 552                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3, credit_upper_bound);
 553         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 :
 554                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4, credit_upper_bound);
 555         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 :
 556                    NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5, credit_upper_bound);
 557
 558         if (!port) {
 559                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6,
 560                         credit_upper_bound);
 561                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7,
 562                         credit_upper_bound);
 563                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8,
 564                         credit_upper_bound);
 565         }
 566 }
 567 /******************************************************************************
 568 * Description:
 569 *       Will return the NIG ETS registers to init values.Except
 570 *       credit_upper_bound.
 571 *       That isn't used in this configuration (No WFQ is enabled) and will be
 572 *       configured according to spec
 573 *.
 574 ******************************************************************************/
 575 static void bnx2x_ets_e3b0_nig_disabled(const struct link_params *params,
 576                                         const struct link_vars *vars)
 577 {
 578         struct bnx2x *bp = params->bp;
 579         const u8 port = params->port;
 580         const u32 min_w_val = bnx2x_ets_get_min_w_val_nig(vars);
 581         /* Mapping between entry  priority to client number (0,1,2 -debug and
 582          * management clients, 3 - COS0 client, 4 - COS1, ... 8 -
 583          * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by
 584          * reset value or init tool
 585          */
 586         if (port) {
 587                 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210);
 588                 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0);
 589         } else {
 590                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210);
 591                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8);
 592         }
 593         /* For strict priority entries defines the number of consecutive
 594          * slots for the highest priority.
 595          */
 596         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS :
 597                    NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
 598         /* Mapping between the CREDIT_WEIGHT registers and actual client
 599          * numbers
 600          */
 601         if (port) {
 602                 /*Port 1 has 6 COS*/
 603                 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543);
 604                 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0);
 605         } else {
 606                 /*Port 0 has 9 COS*/
 607                 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB,
 608                        0x43210876);
 609                 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5);
 610         }
 611
 612         /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
 613          * as strict.  Bits 0,1,2 - debug and management entries, 3 -
 614          * COS0 entry, 4 - COS1 entry.
 615          * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
 616          * bit4   bit3    bit2   bit1     bit0
 617          * MCP and debug are strict
 618          */
 619         if (port)
 620                 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f);
 621         else
 622                 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff);
 623         /* defines which entries (clients) are subjected to WFQ arbitration */
 624         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
 625                    NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
 626
 627         /* Please notice the register address are note continuous and a
 628          * for here is note appropriate.In 2 port mode port0 only COS0-5
 629          * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4
 630          * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT
 631          * are never used for WFQ
 632          */
 633         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
 634                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0);
 635         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
 636                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0x0);
 637         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
 638                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2, 0x0);
 639         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 :
 640                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3, 0x0);
 641         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 :
 642                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4, 0x0);
 643         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 :
 644                    NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5, 0x0);
 645         if (!port) {
 646                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0);
 647                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0);
 648                 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0);
 649         }
 650
 651         bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val);
 652 }
 653 /******************************************************************************
 654 * Description:
 655 *       Set credit upper bound for PBF.
 656 *.
 657 ******************************************************************************/
 658 static void bnx2x_ets_e3b0_set_credit_upper_bound_pbf(
 659         const struct link_params *params,
 660         const u32 min_w_val)
 661 {
 662         struct bnx2x *bp = params->bp;
 663         const u32 credit_upper_bound =
 664             bnx2x_ets_get_credit_upper_bound(min_w_val);
 665         const u8 port = params->port;
 666         u32 base_upper_bound = 0;
 667         u8 max_cos = 0;
 668         u8 i = 0;
 669         /* In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4
 670          * port mode port1 has COS0-2 that can be used for WFQ.
 671          */
 672         if (!port) {
 673                 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P0;
 674                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
 675         } else {
 676                 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P1;
 677                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
 678         }
 679
 680         for (i = 0; i < max_cos; i++)
 681                 REG_WR(bp, base_upper_bound + (i << 2), credit_upper_bound);
 682 }
 683
 684 /******************************************************************************
 685 * Description:
 686 *       Will return the PBF ETS registers to init values.Except
 687 *       credit_upper_bound.
 688 *       That isn't used in this configuration (No WFQ is enabled) and will be
 689 *       configured according to spec
 690 *.
 691 ******************************************************************************/
 692 static void bnx2x_ets_e3b0_pbf_disabled(const struct link_params *params)
 693 {
 694         struct bnx2x *bp = params->bp;
 695         const u8 port = params->port;
 696         const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
 697         u8 i = 0;
 698         u32 base_weight = 0;
 699         u8 max_cos = 0;
 700
 701         /* Mapping between entry  priority to client number 0 - COS0
 702          * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num.
 703          * TODO_ETS - Should be done by reset value or init tool
 704          */
 705         if (port)
 706                 /*  0x688 (|011|0 10|00 1|000) */
 707                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688);
 708         else
 709                 /*  (10 1|100 |011|0 10|00 1|000) */
 710                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688);
 711
 712         /* TODO_ETS - Should be done by reset value or init tool */
 713         if (port)
 714                 /* 0x688 (|011|0 10|00 1|000)*/
 715                 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688);
 716         else
 717         /* 0x2C688 (10 1|100 |011|0 10|00 1|000) */
 718         REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688);
 719
 720         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 :
 721                    PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 , 0x100);
 722
 723
 724         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
 725                    PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , 0);
 726
 727         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
 728                    PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 , 0);
 729         /* In 2 port mode port0 has COS0-5 that can be used for WFQ.
 730          * In 4 port mode port1 has COS0-2 that can be used for WFQ.
 731          */
 732         if (!port) {
 733                 base_weight = PBF_REG_COS0_WEIGHT_P0;
 734                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT0;
 735         } else {
 736                 base_weight = PBF_REG_COS0_WEIGHT_P1;
 737                 max_cos = DCBX_E3B0_MAX_NUM_COS_PORT1;
 738         }
 739
 740         for (i = 0; i < max_cos; i++)
 741                 REG_WR(bp, base_weight + (0x4 * i), 0);
 742
 743         bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
 744 }
 745 /******************************************************************************
 746 * Description:
 747 *       E3B0 disable will return basically the values to init values.
 748 *.
 749 ******************************************************************************/
 750 static int bnx2x_ets_e3b0_disabled(const struct link_params *params,
 751                                    const struct link_vars *vars)
 752 {
 753         struct bnx2x *bp = params->bp;
 754
 755         if (!CHIP_IS_E3B0(bp)) {
 756                 DP(NETIF_MSG_LINK,
 757                    "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n");
 758                 return -EINVAL;
 759         }
 760
 761         bnx2x_ets_e3b0_nig_disabled(params, vars);
 762
 763         bnx2x_ets_e3b0_pbf_disabled(params);
 764
 765         return 0;
 766 }
 767
 768 /******************************************************************************
 769 * Description:
 770 *       Disable will return basically the values to init values.
 771 *
 772 ******************************************************************************/
 773 int bnx2x_ets_disabled(struct link_params *params,
 774                       struct link_vars *vars)
 775 {
 776         struct bnx2x *bp = params->bp;
 777         int bnx2x_status = 0;
 778
 779         if ((CHIP_IS_E2(bp)) || (CHIP_IS_E3A0(bp)))
 780                 bnx2x_ets_e2e3a0_disabled(params);
 781         else if (CHIP_IS_E3B0(bp))
 782                 bnx2x_status = bnx2x_ets_e3b0_disabled(params, vars);
 783         else {
 784                 DP(NETIF_MSG_LINK, "bnx2x_ets_disabled - chip not supported\n");
 785                 return -EINVAL;
 786         }
 787
 788         return bnx2x_status;
 789 }
 790
 791 /******************************************************************************
 792 * Description
 793 *       Set the COS mappimg to SP and BW until this point all the COS are not
 794 *       set as SP or BW.
 795 ******************************************************************************/
 796 static int bnx2x_ets_e3b0_cli_map(const struct link_params *params,
 797                                   const struct bnx2x_ets_params *ets_params,
 798                                   const u8 cos_sp_bitmap,
 799                                   const u8 cos_bw_bitmap)
 800 {
 801         struct bnx2x *bp = params->bp;
 802         const u8 port = params->port;
 803         const u8 nig_cli_sp_bitmap = 0x7 | (cos_sp_bitmap << 3);
 804         const u8 pbf_cli_sp_bitmap = cos_sp_bitmap;
 805         const u8 nig_cli_subject2wfq_bitmap = cos_bw_bitmap << 3;
 806         const u8 pbf_cli_subject2wfq_bitmap = cos_bw_bitmap;
 807
 808         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT :
 809                NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, nig_cli_sp_bitmap);
 810
 811         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
 812                PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , pbf_cli_sp_bitmap);
 813
 814         REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
 815                NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ,
 816                nig_cli_subject2wfq_bitmap);
 817
 818         REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
 819                PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0,
 820                pbf_cli_subject2wfq_bitmap);
 821
 822         return 0;
 823 }
 824
 825 /******************************************************************************
 826 * Description:
 827 *       This function is needed because NIG ARB_CREDIT_WEIGHT_X are
 828 *       not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
 829 ******************************************************************************/
 830 static int bnx2x_ets_e3b0_set_cos_bw(struct bnx2x *bp,
 831                                      const u8 cos_entry,
 832                                      const u32 min_w_val_nig,
 833                                      const u32 min_w_val_pbf,
 834                                      const u16 total_bw,
 835                                      const u8 bw,
 836                                      const u8 port)
 837 {
 838         u32 nig_reg_adress_crd_weight = 0;
 839         u32 pbf_reg_adress_crd_weight = 0;
 840         /* Calculate and set BW for this COS - use 1 instead of 0 for BW */
 841         const u32 cos_bw_nig = ((bw ? bw : 1) * min_w_val_nig) / total_bw;
 842         const u32 cos_bw_pbf = ((bw ? bw : 1) * min_w_val_pbf) / total_bw;
 843
 844         switch (cos_entry) {
 845         case 0:
 846             nig_reg_adress_crd_weight =
 847                  (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
 848                      NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0;
 849              pbf_reg_adress_crd_weight = (port) ?
 850                  PBF_REG_COS0_WEIGHT_P1 : PBF_REG_COS0_WEIGHT_P0;
 851              break;
 852         case 1:
 853              nig_reg_adress_crd_weight = (port) ?
 854                  NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
 855                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1;
 856              pbf_reg_adress_crd_weight = (port) ?
 857                  PBF_REG_COS1_WEIGHT_P1 : PBF_REG_COS1_WEIGHT_P0;
 858              break;
 859         case 2:
 860              nig_reg_adress_crd_weight = (port) ?
 861                  NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
 862                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2;
 863
 864                  pbf_reg_adress_crd_weight = (port) ?
 865                      PBF_REG_COS2_WEIGHT_P1 : PBF_REG_COS2_WEIGHT_P0;
 866              break;
 867         case 3:
 868             if (port)
 869                         return -EINVAL;
 870              nig_reg_adress_crd_weight =
 871                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3;
 872              pbf_reg_adress_crd_weight =
 873                  PBF_REG_COS3_WEIGHT_P0;
 874              break;
 875         case 4:
 876             if (port)
 877                 return -EINVAL;
 878              nig_reg_adress_crd_weight =
 879                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4;
 880              pbf_reg_adress_crd_weight = PBF_REG_COS4_WEIGHT_P0;
 881              break;
 882         case 5:
 883             if (port)
 884                 return -EINVAL;
 885              nig_reg_adress_crd_weight =
 886                  NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5;
 887              pbf_reg_adress_crd_weight = PBF_REG_COS5_WEIGHT_P0;
 888              break;
 889         }
 890
 891         REG_WR(bp, nig_reg_adress_crd_weight, cos_bw_nig);
 892
 893         REG_WR(bp, pbf_reg_adress_crd_weight, cos_bw_pbf);
 894
 895         return 0;
 896 }
 897 /******************************************************************************
 898 * Description:
 899 *       Calculate the total BW.A value of 0 isn't legal.
 900 *
 901 ******************************************************************************/
 902 static int bnx2x_ets_e3b0_get_total_bw(
 903         const struct link_params *params,
 904         struct bnx2x_ets_params *ets_params,
 905         u16 *total_bw)
 906 {
 907         struct bnx2x *bp = params->bp;
 908         u8 cos_idx = 0;
 909         u8 is_bw_cos_exist = 0;
 910
 911         *total_bw = 0 ;
 912         /* Calculate total BW requested */
 913         for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) {
 914                 if (ets_params->cos[cos_idx].state == bnx2x_cos_state_bw) {
 915                         is_bw_cos_exist = 1;
 916                         if (!ets_params->cos[cos_idx].params.bw_params.bw) {
 917                                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config BW"
 918                                                    "was set to 0\n");
 919                                 /* This is to prevent a state when ramrods
 920                                  * can't be sent
 921                                  */
 922                                 ets_params->cos[cos_idx].params.bw_params.bw
 923                                          = 1;
 924                         }
 925                         *total_bw +=
 926                                 ets_params->cos[cos_idx].params.bw_params.bw;
 927                 }
 928         }
 929
 930         /* Check total BW is valid */
 931         if ((is_bw_cos_exist == 1) && (*total_bw != 100)) {
 932                 if (*total_bw == 0) {
 933                         DP(NETIF_MSG_LINK,
 934                            "bnx2x_ets_E3B0_config total BW shouldn't be 0\n");
 935                         return -EINVAL;
 936                 }
 937                 DP(NETIF_MSG_LINK,
 938                    "bnx2x_ets_E3B0_config total BW should be 100\n");
 939                 /* We can handle a case whre the BW isn't 100 this can happen
 940                  * if the TC are joined.
 941                  */
 942         }
 943         return 0;
 944 }
 945
 946 /******************************************************************************
 947 * Description:
 948 *       Invalidate all the sp_pri_to_cos.
 949 *
 950 ******************************************************************************/
 951 static void bnx2x_ets_e3b0_sp_pri_to_cos_init(u8 *sp_pri_to_cos)
 952 {
 953         u8 pri = 0;
 954         for (pri = 0; pri < DCBX_MAX_NUM_COS; pri++)
 955                 sp_pri_to_cos[pri] = DCBX_INVALID_COS;
 956 }
 957 /******************************************************************************
 958 * Description:
 959 *       Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
 960 *       according to sp_pri_to_cos.
 961 *
 962 ******************************************************************************/
 963 static int bnx2x_ets_e3b0_sp_pri_to_cos_set(const struct link_params *params,
 964                                             u8 *sp_pri_to_cos, const u8 pri,
 965                                             const u8 cos_entry)
 966 {
 967         struct bnx2x *bp = params->bp;
 968         const u8 port = params->port;
 969         const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
 970                 DCBX_E3B0_MAX_NUM_COS_PORT0;
 971
 972         if (pri >= max_num_of_cos) {
 973                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
 974                    "parameter Illegal strict priority\n");
 975             return -EINVAL;
 976         }
 977
 978         if (sp_pri_to_cos[pri] != DCBX_INVALID_COS) {
 979                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
 980                                    "parameter There can't be two COS's with "
 981                                    "the same strict pri\n");
 982                 return -EINVAL;
 983         }
 984
 985         sp_pri_to_cos[pri] = cos_entry;
 986         return 0;
 987
 988 }
 989
 990 /******************************************************************************
 991 * Description:
 992 *       Returns the correct value according to COS and priority in
 993 *       the sp_pri_cli register.
 994 *
 995 ******************************************************************************/
 996 static u64 bnx2x_e3b0_sp_get_pri_cli_reg(const u8 cos, const u8 cos_offset,
 997                                          const u8 pri_set,
 998                                          const u8 pri_offset,
 999                                          const u8 entry_size)
1000 {
1001         u64 pri_cli_nig = 0;
1002         pri_cli_nig = ((u64)(cos + cos_offset)) << (entry_size *
1003                                                     (pri_set + pri_offset));
1004
1005         return pri_cli_nig;
1006 }
1007 /******************************************************************************
1008 * Description:
1009 *       Returns the correct value according to COS and priority in the
1010 *       sp_pri_cli register for NIG.
1011 *
1012 ******************************************************************************/
1013 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_nig(const u8 cos, const u8 pri_set)
1014 {
1015         /* MCP Dbg0 and dbg1 are always with higher strict pri*/
1016         const u8 nig_cos_offset = 3;
1017         const u8 nig_pri_offset = 3;
1018
1019         return bnx2x_e3b0_sp_get_pri_cli_reg(cos, nig_cos_offset, pri_set,
1020                 nig_pri_offset, 4);
1021
1022 }
1023 /******************************************************************************
1024 * Description:
1025 *       Returns the correct value according to COS and priority in the
1026 *       sp_pri_cli register for PBF.
1027 *
1028 ******************************************************************************/
1029 static u64 bnx2x_e3b0_sp_get_pri_cli_reg_pbf(const u8 cos, const u8 pri_set)
1030 {
1031         const u8 pbf_cos_offset = 0;
1032         const u8 pbf_pri_offset = 0;
1033
1034         return bnx2x_e3b0_sp_get_pri_cli_reg(cos, pbf_cos_offset, pri_set,
1035                 pbf_pri_offset, 3);
1036
1037 }
1038
1039 /******************************************************************************
1040 * Description:
1041 *       Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
1042 *       according to sp_pri_to_cos.(which COS has higher priority)
1043 *
1044 ******************************************************************************/
1045 static int bnx2x_ets_e3b0_sp_set_pri_cli_reg(const struct link_params *params,
1046                                              u8 *sp_pri_to_cos)
1047 {
1048         struct bnx2x *bp = params->bp;
1049         u8 i = 0;
1050         const u8 port = params->port;
1051         /* MCP Dbg0 and dbg1 are always with higher strict pri*/
1052         u64 pri_cli_nig = 0x210;
1053         u32 pri_cli_pbf = 0x0;
1054         u8 pri_set = 0;
1055         u8 pri_bitmask = 0;
1056         const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
1057                 DCBX_E3B0_MAX_NUM_COS_PORT0;
1058
1059         u8 cos_bit_to_set = (1 << max_num_of_cos) - 1;
1060
1061         /* Set all the strict priority first */
1062         for (i = 0; i < max_num_of_cos; i++) {
1063                 if (sp_pri_to_cos[i] != DCBX_INVALID_COS) {
1064                         if (sp_pri_to_cos[i] >= DCBX_MAX_NUM_COS) {
1065                                 DP(NETIF_MSG_LINK,
1066                                            "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1067                                            "invalid cos entry\n");
1068                                 return -EINVAL;
1069                         }
1070
1071                         pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1072                             sp_pri_to_cos[i], pri_set);
1073
1074                         pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1075                             sp_pri_to_cos[i], pri_set);
1076                         pri_bitmask = 1 << sp_pri_to_cos[i];
1077                         /* COS is used remove it from bitmap.*/
1078                         if (!(pri_bitmask & cos_bit_to_set)) {
1079                                 DP(NETIF_MSG_LINK,
1080                                         "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1081                                         "invalid There can't be two COS's with"
1082                                         " the same strict pri\n");
1083                                 return -EINVAL;
1084                         }
1085                         cos_bit_to_set &= ~pri_bitmask;
1086                         pri_set++;
1087                 }
1088         }
1089
1090         /* Set all the Non strict priority i= COS*/
1091         for (i = 0; i < max_num_of_cos; i++) {
1092                 pri_bitmask = 1 << i;
1093                 /* Check if COS was already used for SP */
1094                 if (pri_bitmask & cos_bit_to_set) {
1095                         /* COS wasn't used for SP */
1096                         pri_cli_nig |= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1097                             i, pri_set);
1098
1099                         pri_cli_pbf |= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1100                             i, pri_set);
1101                         /* COS is used remove it from bitmap.*/
1102                         cos_bit_to_set &= ~pri_bitmask;
1103                         pri_set++;
1104                 }
1105         }
1106
1107         if (pri_set != max_num_of_cos) {
1108                 DP(NETIF_MSG_LINK, "bnx2x_ets_e3b0_sp_set_pri_cli_reg not all "
1109                                    "entries were set\n");
1110                 return -EINVAL;
1111         }
1112
1113         if (port) {
1114                 /* Only 6 usable clients*/
1115                 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB,
1116                        (u32)pri_cli_nig);
1117
1118                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf);
1119         } else {
1120                 /* Only 9 usable clients*/
1121                 const u32 pri_cli_nig_lsb = (u32) (pri_cli_nig);
1122                 const u32 pri_cli_nig_msb = (u32) ((pri_cli_nig >> 32) & 0xF);
1123
1124                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB,
1125                        pri_cli_nig_lsb);
1126                 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB,
1127                        pri_cli_nig_msb);
1128
1129                 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf);
1130         }
1131         return 0;
1132 }
1133
1134 /******************************************************************************
1135 * Description:
1136 *       Configure the COS to ETS according to BW and SP settings.
1137 ******************************************************************************/
1138 int bnx2x_ets_e3b0_config(const struct link_params *params,
1139                          const struct link_vars *vars,
1140                          struct bnx2x_ets_params *ets_params)
1141 {
1142         struct bnx2x *bp = params->bp;
1143         int bnx2x_status = 0;
1144         const u8 port = params->port;
1145         u16 total_bw = 0;
1146         const u32 min_w_val_nig = bnx2x_ets_get_min_w_val_nig(vars);
1147         const u32 min_w_val_pbf = ETS_E3B0_PBF_MIN_W_VAL;
1148         u8 cos_bw_bitmap = 0;
1149         u8 cos_sp_bitmap = 0;
1150         u8 sp_pri_to_cos[DCBX_MAX_NUM_COS] = {0};
1151         const u8 max_num_of_cos = (port) ? DCBX_E3B0_MAX_NUM_COS_PORT1 :
1152                 DCBX_E3B0_MAX_NUM_COS_PORT0;
1153         u8 cos_entry = 0;
1154
1155         if (!CHIP_IS_E3B0(bp)) {
1156                 DP(NETIF_MSG_LINK,
1157                    "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n");
1158                 return -EINVAL;
1159         }
1160
1161         if ((ets_params->num_of_cos > max_num_of_cos)) {
1162                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config the number of COS "
1163                                    "isn't supported\n");
1164                 return -EINVAL;
1165         }
1166
1167         /* Prepare sp strict priority parameters*/
1168         bnx2x_ets_e3b0_sp_pri_to_cos_init(sp_pri_to_cos);
1169
1170         /* Prepare BW parameters*/
1171         bnx2x_status = bnx2x_ets_e3b0_get_total_bw(params, ets_params,
1172                                                    &total_bw);
1173         if (bnx2x_status) {
1174                 DP(NETIF_MSG_LINK,
1175                    "bnx2x_ets_E3B0_config get_total_bw failed\n");
1176                 return -EINVAL;
1177         }
1178
1179         /* Upper bound is set according to current link speed (min_w_val
1180          * should be the same for upper bound and COS credit val).
1181          */
1182         bnx2x_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig);
1183         bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
1184
1185
1186         for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) {
1187                 if (bnx2x_cos_state_bw == ets_params->cos[cos_entry].state) {
1188                         cos_bw_bitmap |= (1 << cos_entry);
1189                         /* The function also sets the BW in HW(not the mappin
1190                          * yet)
1191                          */
1192                         bnx2x_status = bnx2x_ets_e3b0_set_cos_bw(
1193                                 bp, cos_entry, min_w_val_nig, min_w_val_pbf,
1194                                 total_bw,
1195                                 ets_params->cos[cos_entry].params.bw_params.bw,
1196                                  port);
1197                 } else if (bnx2x_cos_state_strict ==
1198                         ets_params->cos[cos_entry].state){
1199                         cos_sp_bitmap |= (1 << cos_entry);
1200
1201                         bnx2x_status = bnx2x_ets_e3b0_sp_pri_to_cos_set(
1202                                 params,
1203                                 sp_pri_to_cos,
1204                                 ets_params->cos[cos_entry].params.sp_params.pri,
1205                                 cos_entry);
1206
1207                 } else {
1208                         DP(NETIF_MSG_LINK,
1209                            "bnx2x_ets_e3b0_config cos state not valid\n");
1210                         return -EINVAL;
1211                 }
1212                 if (bnx2x_status) {
1213                         DP(NETIF_MSG_LINK,
1214                            "bnx2x_ets_e3b0_config set cos bw failed\n");
1215                         return bnx2x_status;
1216                 }
1217         }
1218
1219         /* Set SP register (which COS has higher priority) */
1220         bnx2x_status = bnx2x_ets_e3b0_sp_set_pri_cli_reg(params,
1221                                                          sp_pri_to_cos);
1222
1223         if (bnx2x_status) {
1224                 DP(NETIF_MSG_LINK,
1225                    "bnx2x_ets_E3B0_config set_pri_cli_reg failed\n");
1226                 return bnx2x_status;
1227         }
1228
1229         /* Set client mapping of BW and strict */
1230         bnx2x_status = bnx2x_ets_e3b0_cli_map(params, ets_params,
1231                                               cos_sp_bitmap,
1232                                               cos_bw_bitmap);
1233
1234         if (bnx2x_status) {
1235                 DP(NETIF_MSG_LINK, "bnx2x_ets_E3B0_config SP failed\n");
1236                 return bnx2x_status;
1237         }
1238         return 0;
1239 }
1240 static void bnx2x_ets_bw_limit_common(const struct link_params *params)
1241 {
1242         /* ETS disabled configuration */
1243         struct bnx2x *bp = params->bp;
1244         DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1245         /* Defines which entries (clients) are subjected to WFQ arbitration
1246          * COS0 0x8
1247          * COS1 0x10
1248          */
1249         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18);
1250         /* Mapping between the ARB_CREDIT_WEIGHT registers and actual
1251          * client numbers (WEIGHT_0 does not actually have to represent
1252          * client 0)
1253          *    PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
1254          *  cos1-001     cos0-000     dbg1-100     dbg0-011     MCP-010
1255          */
1256         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A);
1257
1258         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0,
1259                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1260         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1,
1261                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1262
1263         /* ETS mode enabled*/
1264         REG_WR(bp, PBF_REG_ETS_ENABLED, 1);
1265
1266         /* Defines the number of consecutive slots for the strict priority */
1267         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
1268         /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
1269          * as strict.  Bits 0,1,2 - debug and management entries, 3 - COS0
1270          * entry, 4 - COS1 entry.
1271          * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1272          * bit4   bit3    bit2     bit1    bit0
1273          * MCP and debug are strict
1274          */
1275         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
1276
1277         /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/
1278         REG_WR(bp, PBF_REG_COS0_UPPER_BOUND,
1279                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1280         REG_WR(bp, PBF_REG_COS1_UPPER_BOUND,
1281                ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1282 }
1283
1284 void bnx2x_ets_bw_limit(const struct link_params *params, const u32 cos0_bw,
1285                         const u32 cos1_bw)
1286 {
1287         /* ETS disabled configuration*/
1288         struct bnx2x *bp = params->bp;
1289         const u32 total_bw = cos0_bw + cos1_bw;
1290         u32 cos0_credit_weight = 0;
1291         u32 cos1_credit_weight = 0;
1292
1293         DP(NETIF_MSG_LINK, "ETS enabled BW limit configuration\n");
1294
1295         if ((!total_bw) ||
1296             (!cos0_bw) ||
1297             (!cos1_bw)) {
1298                 DP(NETIF_MSG_LINK, "Total BW can't be zero\n");
1299                 return;
1300         }
1301
1302         cos0_credit_weight = (cos0_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1303                 total_bw;
1304         cos1_credit_weight = (cos1_bw * ETS_BW_LIMIT_CREDIT_WEIGHT)/
1305                 total_bw;
1306
1307         bnx2x_ets_bw_limit_common(params);
1308
1309         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight);
1310         REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight);
1311
1312         REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight);
1313         REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight);
1314 }
1315
1316 int bnx2x_ets_strict(const struct link_params *params, const u8 strict_cos)
1317 {
1318         /* ETS disabled configuration*/
1319         struct bnx2x *bp = params->bp;
1320         u32 val = 0;
1321
1322         DP(NETIF_MSG_LINK, "ETS enabled strict configuration\n");
1323         /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
1324          * as strict.  Bits 0,1,2 - debug and management entries,
1325          * 3 - COS0 entry, 4 - COS1 entry.
1326          *  COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1327          *  bit4   bit3   bit2      bit1     bit0
1328          * MCP and debug are strict
1329          */
1330         REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F);
1331         /* For strict priority entries defines the number of consecutive slots
1332          * for the highest priority.
1333          */
1334         REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
1335         /* ETS mode disable */
1336         REG_WR(bp, PBF_REG_ETS_ENABLED, 0);
1337         /* Defines the number of consecutive slots for the strict priority */
1338         REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100);
1339
1340         /* Defines the number of consecutive slots for the strict priority */
1341         REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos);
1342
1343         /* Mapping between entry  priority to client number (0,1,2 -debug and
1344          * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
1345          * 3bits client num.
1346          *   PRI4    |    PRI3    |    PRI2    |    PRI1    |    PRI0
1347          * dbg0-010     dbg1-001     cos1-100     cos0-011     MCP-000
1348          * dbg0-010     dbg1-001     cos0-011     cos1-100     MCP-000
1349          */
1350         val = (!strict_cos) ? 0x2318 : 0x22E0;
1351         REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val);
1352
1353         return 0;
1354 }
1355
1356 /******************************************************************/
1357 /*                      PFC section                               */
1358 /******************************************************************/
1359 static void bnx2x_update_pfc_xmac(struct link_params *params,
1360                                   struct link_vars *vars,
1361                                   u8 is_lb)
1362 {
1363         struct bnx2x *bp = params->bp;
1364         u32 xmac_base;
1365         u32 pause_val, pfc0_val, pfc1_val;
1366
1367         /* XMAC base adrr */
1368         xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1369
1370         /* Initialize pause and pfc registers */
1371         pause_val = 0x18000;
1372         pfc0_val = 0xFFFF8000;
1373         pfc1_val = 0x2;
1374
1375         /* No PFC support */
1376         if (!(params->feature_config_flags &
1377               FEATURE_CONFIG_PFC_ENABLED)) {
1378
1379                 /* RX flow control - Process pause frame in receive direction
1380                  */
1381                 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1382                         pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN;
1383
1384                 /* TX flow control - Send pause packet when buffer is full */
1385                 if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1386                         pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN;
1387         } else {/* PFC support */
1388                 pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN |
1389                         XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN |
1390                         XMAC_PFC_CTRL_HI_REG_RX_PFC_EN |
1391                         XMAC_PFC_CTRL_HI_REG_TX_PFC_EN |
1392                         XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
1393                 /* Write pause and PFC registers */
1394                 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1395                 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1396                 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1397                 pfc1_val &= ~XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
1398
1399         }
1400
1401         /* Write pause and PFC registers */
1402         REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
1403         REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
1404         REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
1405
1406
1407         /* Set MAC address for source TX Pause/PFC frames */
1408         REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_LO,
1409                ((params->mac_addr[2] << 24) |
1410                 (params->mac_addr[3] << 16) |
1411                 (params->mac_addr[4] << 8) |
1412                 (params->mac_addr[5])));
1413         REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_HI,
1414                ((params->mac_addr[0] << 8) |
1415                 (params->mac_addr[1])));
1416
1417         udelay(30);
1418 }
1419
1420 /******************************************************************/
1421 /*                      MAC/PBF section                           */
1422 /******************************************************************/
1423 static void bnx2x_set_mdio_clk(struct bnx2x *bp, u32 chip_id,
1424                                u32 emac_base)
1425 {
1426         u32 new_mode, cur_mode;
1427         u32 clc_cnt;
1428         /* Set clause 45 mode, slow down the MDIO clock to 2.5MHz
1429          * (a value of 49==0x31) and make sure that the AUTO poll is off
1430          */
1431         cur_mode = REG_RD(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE);
1432
1433         if (USES_WARPCORE(bp))
1434                 clc_cnt = 74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT;
1435         else
1436                 clc_cnt = 49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT;
1437
1438         if (((cur_mode & EMAC_MDIO_MODE_CLOCK_CNT) == clc_cnt) &&
1439             (cur_mode & (EMAC_MDIO_MODE_CLAUSE_45)))
1440                 return;
1441
1442         new_mode = cur_mode &
1443                 ~(EMAC_MDIO_MODE_AUTO_POLL | EMAC_MDIO_MODE_CLOCK_CNT);
1444         new_mode |= clc_cnt;
1445         new_mode |= (EMAC_MDIO_MODE_CLAUSE_45);
1446
1447         DP(NETIF_MSG_LINK, "Changing emac_mode from 0x%x to 0x%x\n",
1448            cur_mode, new_mode);
1449         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE, new_mode);
1450         udelay(40);
1451 }
1452
1453 static void bnx2x_set_mdio_emac_per_phy(struct bnx2x *bp,
1454                                         struct link_params *params)
1455 {
1456         u8 phy_index;
1457         /* Set mdio clock per phy */
1458         for (phy_index = INT_PHY; phy_index < params->num_phys;
1459               phy_index++)
1460                 bnx2x_set_mdio_clk(bp, params->chip_id,
1461                                    params->phy[phy_index].mdio_ctrl);
1462 }
1463
1464 static u8 bnx2x_is_4_port_mode(struct bnx2x *bp)
1465 {
1466         u32 port4mode_ovwr_val;
1467         /* Check 4-port override enabled */
1468         port4mode_ovwr_val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
1469         if (port4mode_ovwr_val & (1<<0)) {
1470                 /* Return 4-port mode override value */
1471                 return ((port4mode_ovwr_val & (1<<1)) == (1<<1));
1472         }
1473         /* Return 4-port mode from input pin */
1474         return (u8)REG_RD(bp, MISC_REG_PORT4MODE_EN);
1475 }
1476
1477 static void bnx2x_emac_init(struct link_params *params,
1478                             struct link_vars *vars)
1479 {
1480         /* reset and unreset the emac core */
1481         struct bnx2x *bp = params->bp;
1482         u8 port = params->port;
1483         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1484         u32 val;
1485         u16 timeout;
1486
1487         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1488                (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1489         udelay(5);
1490         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1491                (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
1492
1493         /* init emac - use read-modify-write */
1494         /* self clear reset */
1495         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1496         EMAC_WR(bp, EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
1497
1498         timeout = 200;
1499         do {
1500                 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1501                 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
1502                 if (!timeout) {
1503                         DP(NETIF_MSG_LINK, "EMAC timeout!\n");
1504                         return;
1505                 }
1506                 timeout--;
1507         } while (val & EMAC_MODE_RESET);
1508
1509         bnx2x_set_mdio_emac_per_phy(bp, params);
1510         /* Set mac address */
1511         val = ((params->mac_addr[0] << 8) |
1512                 params->mac_addr[1]);
1513         EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH, val);
1514
1515         val = ((params->mac_addr[2] << 24) |
1516                (params->mac_addr[3] << 16) |
1517                (params->mac_addr[4] << 8) |
1518                 params->mac_addr[5]);
1519         EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + 4, val);
1520 }
1521
1522 static void bnx2x_set_xumac_nig(struct link_params *params,
1523                                 u16 tx_pause_en,
1524                                 u8 enable)
1525 {
1526         struct bnx2x *bp = params->bp;
1527
1528         REG_WR(bp, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN,
1529                enable);
1530         REG_WR(bp, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN,
1531                enable);
1532         REG_WR(bp, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN :
1533                NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en);
1534 }
1535
1536 static void bnx2x_set_umac_rxtx(struct link_params *params, u8 en)
1537 {
1538         u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1539         u32 val;
1540         struct bnx2x *bp = params->bp;
1541         if (!(REG_RD(bp, MISC_REG_RESET_REG_2) &
1542                    (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)))
1543                 return;
1544         val = REG_RD(bp, umac_base + UMAC_REG_COMMAND_CONFIG);
1545         if (en)
1546                 val |= (UMAC_COMMAND_CONFIG_REG_TX_ENA |
1547                         UMAC_COMMAND_CONFIG_REG_RX_ENA);
1548         else
1549                 val &= ~(UMAC_COMMAND_CONFIG_REG_TX_ENA |
1550                          UMAC_COMMAND_CONFIG_REG_RX_ENA);
1551         /* Disable RX and TX */
1552         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1553 }
1554
1555 static void bnx2x_umac_enable(struct link_params *params,
1556                             struct link_vars *vars, u8 lb)
1557 {
1558         u32 val;
1559         u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1560         struct bnx2x *bp = params->bp;
1561         /* Reset UMAC */
1562         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1563                (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1564         usleep_range(1000, 2000);
1565
1566         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1567                (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
1568
1569         DP(NETIF_MSG_LINK, "enabling UMAC\n");
1570
1571         /* This register opens the gate for the UMAC despite its name */
1572         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
1573
1574         val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN |
1575                 UMAC_COMMAND_CONFIG_REG_PAD_EN |
1576                 UMAC_COMMAND_CONFIG_REG_SW_RESET |
1577                 UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK;
1578         switch (vars->line_speed) {
1579         case SPEED_10:
1580                 val |= (0<<2);
1581                 break;
1582         case SPEED_100:
1583                 val |= (1<<2);
1584                 break;
1585         case SPEED_1000:
1586                 val |= (2<<2);
1587                 break;
1588         case SPEED_2500:
1589                 val |= (3<<2);
1590                 break;
1591         default:
1592                 DP(NETIF_MSG_LINK, "Invalid speed for UMAC %d\n",
1593                                vars->line_speed);
1594                 break;
1595         }
1596         if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1597                 val |= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE;
1598
1599         if (!(vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1600                 val |= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE;
1601
1602         if (vars->duplex == DUPLEX_HALF)
1603                 val |= UMAC_COMMAND_CONFIG_REG_HD_ENA;
1604
1605         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1606         udelay(50);
1607
1608         /* Configure UMAC for EEE */
1609         if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {
1610                 DP(NETIF_MSG_LINK, "configured UMAC for EEE\n");
1611                 REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL,
1612                        UMAC_UMAC_EEE_CTRL_REG_EEE_EN);
1613                 REG_WR(bp, umac_base + UMAC_REG_EEE_WAKE_TIMER, 0x11);
1614         } else {
1615                 REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL, 0x0);
1616         }
1617
1618         /* Set MAC address for source TX Pause/PFC frames (under SW reset) */
1619         REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR0,
1620                ((params->mac_addr[2] << 24) |
1621                 (params->mac_addr[3] << 16) |
1622                 (params->mac_addr[4] << 8) |
1623                 (params->mac_addr[5])));
1624         REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR1,
1625                ((params->mac_addr[0] << 8) |
1626                 (params->mac_addr[1])));
1627
1628         /* Enable RX and TX */
1629         val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN;
1630         val |= UMAC_COMMAND_CONFIG_REG_TX_ENA |
1631                 UMAC_COMMAND_CONFIG_REG_RX_ENA;
1632         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1633         udelay(50);
1634
1635         /* Remove SW Reset */
1636         val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET;
1637
1638         /* Check loopback mode */
1639         if (lb)
1640                 val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA;
1641         REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val);
1642
1643         /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
1644          * length used by the MAC receive logic to check frames.
1645          */
1646         REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
1647         bnx2x_set_xumac_nig(params,
1648                             ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1649         vars->mac_type = MAC_TYPE_UMAC;
1650
1651 }
1652
1653 /* Define the XMAC mode */
1654 static void bnx2x_xmac_init(struct link_params *params, u32 max_speed)
1655 {
1656         struct bnx2x *bp = params->bp;
1657         u32 is_port4mode = bnx2x_is_4_port_mode(bp);
1658
1659         /* In 4-port mode, need to set the mode only once, so if XMAC is
1660          * already out of reset, it means the mode has already been set,
1661          * and it must not* reset the XMAC again, since it controls both
1662          * ports of the path
1663          */
1664
1665         if (((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) ||
1666              (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) ||
1667              (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE)) &&
1668             is_port4mode &&
1669             (REG_RD(bp, MISC_REG_RESET_REG_2) &
1670              MISC_REGISTERS_RESET_REG_2_XMAC)) {
1671                 DP(NETIF_MSG_LINK,
1672                    "XMAC already out of reset in 4-port mode\n");
1673                 return;
1674         }
1675
1676         /* Hard reset */
1677         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1678                MISC_REGISTERS_RESET_REG_2_XMAC);
1679         usleep_range(1000, 2000);
1680
1681         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1682                MISC_REGISTERS_RESET_REG_2_XMAC);
1683         if (is_port4mode) {
1684                 DP(NETIF_MSG_LINK, "Init XMAC to 2 ports x 10G per path\n");
1685
1686                 /* Set the number of ports on the system side to up to 2 */
1687                 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 1);
1688
1689                 /* Set the number of ports on the Warp Core to 10G */
1690                 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1691         } else {
1692                 /* Set the number of ports on the system side to 1 */
1693                 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 0);
1694                 if (max_speed == SPEED_10000) {
1695                         DP(NETIF_MSG_LINK,
1696                            "Init XMAC to 10G x 1 port per path\n");
1697                         /* Set the number of ports on the Warp Core to 10G */
1698                         REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3);
1699                 } else {
1700                         DP(NETIF_MSG_LINK,
1701                            "Init XMAC to 20G x 2 ports per path\n");
1702                         /* Set the number of ports on the Warp Core to 20G */
1703                         REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 1);
1704                 }
1705         }
1706         /* Soft reset */
1707         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1708                MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1709         usleep_range(1000, 2000);
1710
1711         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
1712                MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
1713
1714 }
1715
1716 static void bnx2x_set_xmac_rxtx(struct link_params *params, u8 en)
1717 {
1718         u8 port = params->port;
1719         struct bnx2x *bp = params->bp;
1720         u32 pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1721         u32 val;
1722
1723         if (REG_RD(bp, MISC_REG_RESET_REG_2) &
1724             MISC_REGISTERS_RESET_REG_2_XMAC) {
1725                 /* Send an indication to change the state in the NIG back to XON
1726                  * Clearing this bit enables the next set of this bit to get
1727                  * rising edge
1728                  */
1729                 pfc_ctrl = REG_RD(bp, xmac_base + XMAC_REG_PFC_CTRL_HI);
1730                 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI,
1731                        (pfc_ctrl & ~(1<<1)));
1732                 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI,
1733                        (pfc_ctrl | (1<<1)));
1734                 DP(NETIF_MSG_LINK, "Disable XMAC on port %x\n", port);
1735                 val = REG_RD(bp, xmac_base + XMAC_REG_CTRL);
1736                 if (en)
1737                         val |= (XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN);
1738                 else
1739                         val &= ~(XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN);
1740                 REG_WR(bp, xmac_base + XMAC_REG_CTRL, val);
1741         }
1742 }
1743
1744 static int bnx2x_xmac_enable(struct link_params *params,
1745                              struct link_vars *vars, u8 lb)
1746 {
1747         u32 val, xmac_base;
1748         struct bnx2x *bp = params->bp;
1749         DP(NETIF_MSG_LINK, "enabling XMAC\n");
1750
1751         xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1752
1753         bnx2x_xmac_init(params, vars->line_speed);
1754
1755         /* This register determines on which events the MAC will assert
1756          * error on the i/f to the NIG along w/ EOP.
1757          */
1758
1759         /* This register tells the NIG whether to send traffic to UMAC
1760          * or XMAC
1761          */
1762         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0);
1763
1764         /* When XMAC is in XLGMII mode, disable sending idles for fault
1765          * detection.
1766          */
1767         if (!(params->phy[INT_PHY].flags & FLAGS_TX_ERROR_CHECK)) {
1768                 REG_WR(bp, xmac_base + XMAC_REG_RX_LSS_CTRL,
1769                        (XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE |
1770                         XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE));
1771                 REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
1772                 REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
1773                        XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
1774                        XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
1775         }
1776         /* Set Max packet size */
1777         REG_WR(bp, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710);
1778
1779         /* CRC append for Tx packets */
1780         REG_WR(bp, xmac_base + XMAC_REG_TX_CTRL, 0xC800);
1781
1782         /* update PFC */
1783         bnx2x_update_pfc_xmac(params, vars, 0);
1784
1785         if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {
1786                 DP(NETIF_MSG_LINK, "Setting XMAC for EEE\n");
1787                 REG_WR(bp, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008);
1788                 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x1);
1789         } else {
1790                 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x0);
1791         }
1792
1793         /* Enable TX and RX */
1794         val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN;
1795
1796         /* Set MAC in XLGMII mode for dual-mode */
1797         if ((vars->line_speed == SPEED_20000) &&
1798             (params->phy[INT_PHY].supported &
1799              SUPPORTED_20000baseKR2_Full))
1800                 val |= XMAC_CTRL_REG_XLGMII_ALIGN_ENB;
1801
1802         /* Check loopback mode */
1803         if (lb)
1804                 val |= XMAC_CTRL_REG_LINE_LOCAL_LPBK;
1805         REG_WR(bp, xmac_base + XMAC_REG_CTRL, val);
1806         bnx2x_set_xumac_nig(params,
1807                             ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1);
1808
1809         vars->mac_type = MAC_TYPE_XMAC;
1810
1811         return 0;
1812 }
1813
1814 static int bnx2x_emac_enable(struct link_params *params,
1815                              struct link_vars *vars, u8 lb)
1816 {
1817         struct bnx2x *bp = params->bp;
1818         u8 port = params->port;
1819         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
1820         u32 val;
1821
1822         DP(NETIF_MSG_LINK, "enabling EMAC\n");
1823
1824         /* Disable BMAC */
1825         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
1826                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
1827
1828         /* enable emac and not bmac */
1829         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
1830
1831         /* ASIC */
1832         if (vars->phy_flags & PHY_XGXS_FLAG) {
1833                 u32 ser_lane = ((params->lane_config &
1834                                  PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1835                                 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1836
1837                 DP(NETIF_MSG_LINK, "XGXS\n");
1838                 /* select the master lanes (out of 0-3) */
1839                 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane);
1840                 /* select XGXS */
1841                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
1842
1843         } else { /* SerDes */
1844                 DP(NETIF_MSG_LINK, "SerDes\n");
1845                 /* select SerDes */
1846                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
1847         }
1848
1849         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1850                       EMAC_RX_MODE_RESET);
1851         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1852                       EMAC_TX_MODE_RESET);
1853
1854                 /* pause enable/disable */
1855                 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
1856                                EMAC_RX_MODE_FLOW_EN);
1857
1858                 bnx2x_bits_dis(bp,  emac_base + EMAC_REG_EMAC_TX_MODE,
1859                                (EMAC_TX_MODE_EXT_PAUSE_EN |
1860                                 EMAC_TX_MODE_FLOW_EN));
1861                 if (!(params->feature_config_flags &
1862                       FEATURE_CONFIG_PFC_ENABLED)) {
1863                         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
1864                                 bnx2x_bits_en(bp, emac_base +
1865                                               EMAC_REG_EMAC_RX_MODE,
1866                                               EMAC_RX_MODE_FLOW_EN);
1867
1868                         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
1869                                 bnx2x_bits_en(bp, emac_base +
1870                                               EMAC_REG_EMAC_TX_MODE,
1871                                               (EMAC_TX_MODE_EXT_PAUSE_EN |
1872                                                EMAC_TX_MODE_FLOW_EN));
1873                 } else
1874                         bnx2x_bits_en(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
1875                                       EMAC_TX_MODE_FLOW_EN);
1876
1877         /* KEEP_VLAN_TAG, promiscuous */
1878         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
1879         val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
1880
1881         /* Setting this bit causes MAC control frames (except for pause
1882          * frames) to be passed on for processing. This setting has no
1883          * affect on the operation of the pause frames. This bit effects
1884          * all packets regardless of RX Parser packet sorting logic.
1885          * Turn the PFC off to make sure we are in Xon state before
1886          * enabling it.
1887          */
1888         EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0);
1889         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
1890                 DP(NETIF_MSG_LINK, "PFC is enabled\n");
1891                 /* Enable PFC again */
1892                 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE,
1893                         EMAC_REG_RX_PFC_MODE_RX_EN |
1894                         EMAC_REG_RX_PFC_MODE_TX_EN |
1895                         EMAC_REG_RX_PFC_MODE_PRIORITIES);
1896
1897                 EMAC_WR(bp, EMAC_REG_RX_PFC_PARAM,
1898                         ((0x0101 <<
1899                           EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |
1900                          (0x00ff <<
1901                           EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
1902                 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL;
1903         }
1904         EMAC_WR(bp, EMAC_REG_EMAC_RX_MODE, val);
1905
1906         /* Set Loopback */
1907         val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
1908         if (lb)
1909                 val |= 0x810;
1910         else
1911                 val &= ~0x810;
1912         EMAC_WR(bp, EMAC_REG_EMAC_MODE, val);
1913
1914         /* Enable emac */
1915         REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1);
1916
1917         /* Enable emac for jumbo packets */
1918         EMAC_WR(bp, EMAC_REG_EMAC_RX_MTU_SIZE,
1919                 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
1920                  (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)));
1921
1922         /* Strip CRC */
1923         REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
1924
1925         /* Disable the NIG in/out to the bmac */
1926         REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
1927         REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
1928         REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
1929
1930         /* Enable the NIG in/out to the emac */
1931         REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
1932         val = 0;
1933         if ((params->feature_config_flags &
1934               FEATURE_CONFIG_PFC_ENABLED) ||
1935             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1936                 val = 1;
1937
1938         REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
1939         REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
1940
1941         REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);
1942
1943         vars->mac_type = MAC_TYPE_EMAC;
1944         return 0;
1945 }
1946
1947 static void bnx2x_update_pfc_bmac1(struct link_params *params,
1948                                    struct link_vars *vars)
1949 {
1950         u32 wb_data[2];
1951         struct bnx2x *bp = params->bp;
1952         u32 bmac_addr =  params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1953                 NIG_REG_INGRESS_BMAC0_MEM;
1954
1955         u32 val = 0x14;
1956         if ((!(params->feature_config_flags &
1957               FEATURE_CONFIG_PFC_ENABLED)) &&
1958                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1959                 /* Enable BigMAC to react on received Pause packets */
1960                 val |= (1<<5);
1961         wb_data[0] = val;
1962         wb_data[1] = 0;
1963         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);
1964
1965         /* TX control */
1966         val = 0xc0;
1967         if (!(params->feature_config_flags &
1968               FEATURE_CONFIG_PFC_ENABLED) &&
1969                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
1970                 val |= 0x800000;
1971         wb_data[0] = val;
1972         wb_data[1] = 0;
1973         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);
1974 }
1975
1976 static void bnx2x_update_pfc_bmac2(struct link_params *params,
1977                                    struct link_vars *vars,
1978                                    u8 is_lb)
1979 {
1980         /* Set rx control: Strip CRC and enable BigMAC to relay
1981          * control packets to the system as well
1982          */
1983         u32 wb_data[2];
1984         struct bnx2x *bp = params->bp;
1985         u32 bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
1986                 NIG_REG_INGRESS_BMAC0_MEM;
1987         u32 val = 0x14;
1988
1989         if ((!(params->feature_config_flags &
1990               FEATURE_CONFIG_PFC_ENABLED)) &&
1991                 (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX))
1992                 /* Enable BigMAC to react on received Pause packets */
1993                 val |= (1<<5);
1994         wb_data[0] = val;
1995         wb_data[1] = 0;
1996         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2);
1997         udelay(30);
1998
1999         /* Tx control */
2000         val = 0xc0;
2001         if (!(params->feature_config_flags &
2002                                 FEATURE_CONFIG_PFC_ENABLED) &&
2003             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2004                 val |= 0x800000;
2005         wb_data[0] = val;
2006         wb_data[1] = 0;
2007         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);
2008
2009         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED) {
2010                 DP(NETIF_MSG_LINK, "PFC is enabled\n");
2011                 /* Enable PFC RX & TX & STATS and set 8 COS  */
2012                 wb_data[0] = 0x0;
2013                 wb_data[0] |= (1<<0);  /* RX */
2014                 wb_data[0] |= (1<<1);  /* TX */
2015                 wb_data[0] |= (1<<2);  /* Force initial Xon */
2016                 wb_data[0] |= (1<<3);  /* 8 cos */
2017                 wb_data[0] |= (1<<5);  /* STATS */
2018                 wb_data[1] = 0;
2019                 REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL,
2020                             wb_data, 2);
2021                 /* Clear the force Xon */
2022                 wb_data[0] &= ~(1<<2);
2023         } else {
2024                 DP(NETIF_MSG_LINK, "PFC is disabled\n");
2025                 /* Disable PFC RX & TX & STATS and set 8 COS */
2026                 wb_data[0] = 0x8;
2027                 wb_data[1] = 0;
2028         }
2029
2030         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);
2031
2032         /* Set Time (based unit is 512 bit time) between automatic
2033          * re-sending of PP packets amd enable automatic re-send of
2034          * Per-Priroity Packet as long as pp_gen is asserted and
2035          * pp_disable is low.
2036          */
2037         val = 0x8000;
2038         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2039                 val |= (1<<16); /* enable automatic re-send */
2040
2041         wb_data[0] = val;
2042         wb_data[1] = 0;
2043         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL,
2044                     wb_data, 2);
2045
2046         /* mac control */
2047         val = 0x3; /* Enable RX and TX */
2048         if (is_lb) {
2049                 val |= 0x4; /* Local loopback */
2050                 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
2051         }
2052         /* When PFC enabled, Pass pause frames towards the NIG. */
2053         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2054                 val |= ((1<<6)|(1<<5));
2055
2056         wb_data[0] = val;
2057         wb_data[1] = 0;
2058         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2059 }
2060
2061 /******************************************************************************
2062 * Description:
2063 *  This function is needed because NIG ARB_CREDIT_WEIGHT_X are
2064 *  not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
2065 ******************************************************************************/
2066 static int bnx2x_pfc_nig_rx_priority_mask(struct bnx2x *bp,
2067                                            u8 cos_entry,
2068                                            u32 priority_mask, u8 port)
2069 {
2070         u32 nig_reg_rx_priority_mask_add = 0;
2071
2072         switch (cos_entry) {
2073         case 0:
2074              nig_reg_rx_priority_mask_add = (port) ?
2075                  NIG_REG_P1_RX_COS0_PRIORITY_MASK :
2076                  NIG_REG_P0_RX_COS0_PRIORITY_MASK;
2077              break;
2078         case 1:
2079             nig_reg_rx_priority_mask_add = (port) ?
2080                 NIG_REG_P1_RX_COS1_PRIORITY_MASK :
2081                 NIG_REG_P0_RX_COS1_PRIORITY_MASK;
2082             break;
2083         case 2:
2084             nig_reg_rx_priority_mask_add = (port) ?
2085                 NIG_REG_P1_RX_COS2_PRIORITY_MASK :
2086                 NIG_REG_P0_RX_COS2_PRIORITY_MASK;
2087             break;
2088         case 3:
2089             if (port)
2090                 return -EINVAL;
2091             nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK;
2092             break;
2093         case 4:
2094             if (port)
2095                 return -EINVAL;
2096             nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK;
2097             break;
2098         case 5:
2099             if (port)
2100                 return -EINVAL;
2101             nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK;
2102             break;
2103         }
2104
2105         REG_WR(bp, nig_reg_rx_priority_mask_add, priority_mask);
2106
2107         return 0;
2108 }
2109 static void bnx2x_update_mng(struct link_params *params, u32 link_status)
2110 {
2111         struct bnx2x *bp = params->bp;
2112
2113         REG_WR(bp, params->shmem_base +
2114                offsetof(struct shmem_region,
2115                         port_mb[params->port].link_status), link_status);
2116 }
2117
2118 static void bnx2x_update_link_attr(struct link_params *params, u32 link_attr)
2119 {
2120         struct bnx2x *bp = params->bp;
2121
2122         if (SHMEM2_HAS(bp, link_attr_sync))
2123                 REG_WR(bp, params->shmem2_base +
2124                        offsetof(struct shmem2_region,
2125                                 link_attr_sync[params->port]), link_attr);
2126 }
2127
2128 static void bnx2x_update_pfc_nig(struct link_params *params,
2129                 struct link_vars *vars,
2130                 struct bnx2x_nig_brb_pfc_port_params *nig_params)
2131 {
2132         u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0;
2133         u32 llfc_enable = 0, xcm_out_en = 0, hwpfc_enable = 0;
2134         u32 pkt_priority_to_cos = 0;
2135         struct bnx2x *bp = params->bp;
2136         u8 port = params->port;
2137
2138         int set_pfc = params->feature_config_flags &
2139                 FEATURE_CONFIG_PFC_ENABLED;
2140         DP(NETIF_MSG_LINK, "updating pfc nig parameters\n");
2141
2142         /* When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
2143          * MAC control frames (that are not pause packets)
2144          * will be forwarded to the XCM.
2145          */
2146         xcm_mask = REG_RD(bp, port ? NIG_REG_LLH1_XCM_MASK :
2147                           NIG_REG_LLH0_XCM_MASK);
2148         /* NIG params will override non PFC params, since it's possible to
2149          * do transition from PFC to SAFC
2150          */
2151         if (set_pfc) {
2152                 pause_enable = 0;
2153                 llfc_out_en = 0;
2154                 llfc_enable = 0;
2155                 if (CHIP_IS_E3(bp))
2156                         ppp_enable = 0;
2157                 else
2158                         ppp_enable = 1;
2159                 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2160                                      NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2161                 xcm_out_en = 0;
2162                 hwpfc_enable = 1;
2163         } else  {
2164                 if (nig_params) {
2165                         llfc_out_en = nig_params->llfc_out_en;
2166                         llfc_enable = nig_params->llfc_enable;
2167                         pause_enable = nig_params->pause_enable;
2168                 } else  /* Default non PFC mode - PAUSE */
2169                         pause_enable = 1;
2170
2171                 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2172                         NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2173                 xcm_out_en = 1;
2174         }
2175
2176         if (CHIP_IS_E3(bp))
2177                 REG_WR(bp, port ? NIG_REG_BRB1_PAUSE_IN_EN :
2178                        NIG_REG_BRB0_PAUSE_IN_EN, pause_enable);
2179         REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 :
2180                NIG_REG_LLFC_OUT_EN_0, llfc_out_en);
2181         REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 :
2182                NIG_REG_LLFC_ENABLE_0, llfc_enable);
2183         REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 :
2184                NIG_REG_PAUSE_ENABLE_0, pause_enable);
2185
2186         REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 :
2187                NIG_REG_PPP_ENABLE_0, ppp_enable);
2188
2189         REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK :
2190                NIG_REG_LLH0_XCM_MASK, xcm_mask);
2191
2192         REG_WR(bp, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 :
2193                NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7);
2194
2195         /* Output enable for RX_XCM # IF */
2196         REG_WR(bp, port ? NIG_REG_XCM1_OUT_EN :
2197                NIG_REG_XCM0_OUT_EN, xcm_out_en);
2198
2199         /* HW PFC TX enable */
2200         REG_WR(bp, port ? NIG_REG_P1_HWPFC_ENABLE :
2201                NIG_REG_P0_HWPFC_ENABLE, hwpfc_enable);
2202
2203         if (nig_params) {
2204                 u8 i = 0;
2205                 pkt_priority_to_cos = nig_params->pkt_priority_to_cos;
2206
2207                 for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++)
2208                         bnx2x_pfc_nig_rx_priority_mask(bp, i,
2209                 nig_params->rx_cos_priority_mask[i], port);
2210
2211                 REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :
2212                        NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0,
2213                        nig_params->llfc_high_priority_classes);
2214
2215                 REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 :
2216                        NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0,
2217                        nig_params->llfc_low_priority_classes);
2218         }
2219         REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :
2220                NIG_REG_P0_PKT_PRIORITY_TO_COS,
2221                pkt_priority_to_cos);
2222 }
2223
2224 int bnx2x_update_pfc(struct link_params *params,
2225                       struct link_vars *vars,
2226                       struct bnx2x_nig_brb_pfc_port_params *pfc_params)
2227 {
2228         /* The PFC and pause are orthogonal to one another, meaning when
2229          * PFC is enabled, the pause are disabled, and when PFC is
2230          * disabled, pause are set according to the pause result.
2231          */
2232         u32 val;
2233         struct bnx2x *bp = params->bp;
2234         u8 bmac_loopback = (params->loopback_mode == LOOPBACK_BMAC);
2235
2236         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
2237                 vars->link_status |= LINK_STATUS_PFC_ENABLED;
2238         else
2239                 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
2240
2241         bnx2x_update_mng(params, vars->link_status);
2242
2243         /* Update NIG params */
2244         bnx2x_update_pfc_nig(params, vars, pfc_params);
2245
2246         if (!vars->link_up)
2247                 return 0;
2248
2249         DP(NETIF_MSG_LINK, "About to update PFC in BMAC\n");
2250
2251         if (CHIP_IS_E3(bp)) {
2252                 if (vars->mac_type == MAC_TYPE_XMAC)
2253                         bnx2x_update_pfc_xmac(params, vars, 0);
2254         } else {
2255                 val = REG_RD(bp, MISC_REG_RESET_REG_2);
2256                 if ((val &
2257                      (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
2258                     == 0) {
2259                         DP(NETIF_MSG_LINK, "About to update PFC in EMAC\n");
2260                         bnx2x_emac_enable(params, vars, 0);
2261                         return 0;
2262                 }
2263                 if (CHIP_IS_E2(bp))
2264                         bnx2x_update_pfc_bmac2(params, vars, bmac_loopback);
2265                 else
2266                         bnx2x_update_pfc_bmac1(params, vars);
2267
2268                 val = 0;
2269                 if ((params->feature_config_flags &
2270                      FEATURE_CONFIG_PFC_ENABLED) ||
2271                     (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2272                         val = 1;
2273                 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val);
2274         }
2275         return 0;
2276 }
2277
2278 static int bnx2x_bmac1_enable(struct link_params *params,
2279                               struct link_vars *vars,
2280                               u8 is_lb)
2281 {
2282         struct bnx2x *bp = params->bp;
2283         u8 port = params->port;
2284         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2285                                NIG_REG_INGRESS_BMAC0_MEM;
2286         u32 wb_data[2];
2287         u32 val;
2288
2289         DP(NETIF_MSG_LINK, "Enabling BigMAC1\n");
2290
2291         /* XGXS control */
2292         wb_data[0] = 0x3c;
2293         wb_data[1] = 0;
2294         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
2295                     wb_data, 2);
2296
2297         /* TX MAC SA */
2298         wb_data[0] = ((params->mac_addr[2] << 24) |
2299                        (params->mac_addr[3] << 16) |
2300                        (params->mac_addr[4] << 8) |
2301                         params->mac_addr[5]);
2302         wb_data[1] = ((params->mac_addr[0] << 8) |
2303                         params->mac_addr[1]);
2304         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);
2305
2306         /* MAC control */
2307         val = 0x3;
2308         if (is_lb) {
2309                 val |= 0x4;
2310                 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
2311         }
2312         wb_data[0] = val;
2313         wb_data[1] = 0;
2314         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2);
2315
2316         /* Set rx mtu */
2317         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2318         wb_data[1] = 0;
2319         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2);
2320
2321         bnx2x_update_pfc_bmac1(params, vars);
2322
2323         /* Set tx mtu */
2324         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2325         wb_data[1] = 0;
2326         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2);
2327
2328         /* Set cnt max size */
2329         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2330         wb_data[1] = 0;
2331         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2332
2333         /* Configure SAFC */
2334         wb_data[0] = 0x1000200;
2335         wb_data[1] = 0;
2336         REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
2337                     wb_data, 2);
2338
2339         return 0;
2340 }
2341
2342 static int bnx2x_bmac2_enable(struct link_params *params,
2343                               struct link_vars *vars,
2344                               u8 is_lb)
2345 {
2346         struct bnx2x *bp = params->bp;
2347         u8 port = params->port;
2348         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2349                                NIG_REG_INGRESS_BMAC0_MEM;
2350         u32 wb_data[2];
2351
2352         DP(NETIF_MSG_LINK, "Enabling BigMAC2\n");
2353
2354         wb_data[0] = 0;
2355         wb_data[1] = 0;
2356         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2357         udelay(30);
2358
2359         /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
2360         wb_data[0] = 0x3c;
2361         wb_data[1] = 0;
2362         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL,
2363                     wb_data, 2);
2364
2365         udelay(30);
2366
2367         /* TX MAC SA */
2368         wb_data[0] = ((params->mac_addr[2] << 24) |
2369                        (params->mac_addr[3] << 16) |
2370                        (params->mac_addr[4] << 8) |
2371                         params->mac_addr[5]);
2372         wb_data[1] = ((params->mac_addr[0] << 8) |
2373                         params->mac_addr[1]);
2374         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR,
2375                     wb_data, 2);
2376
2377         udelay(30);
2378
2379         /* Configure SAFC */
2380         wb_data[0] = 0x1000200;
2381         wb_data[1] = 0;
2382         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS,
2383                     wb_data, 2);
2384         udelay(30);
2385
2386         /* Set RX MTU */
2387         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2388         wb_data[1] = 0;
2389         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2);
2390         udelay(30);
2391
2392         /* Set TX MTU */
2393         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
2394         wb_data[1] = 0;
2395         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2);
2396         udelay(30);
2397         /* Set cnt max size */
2398         wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD - 2;
2399         wb_data[1] = 0;
2400         REG_WR_DMAE(bp, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2);
2401         udelay(30);
2402         bnx2x_update_pfc_bmac2(params, vars, is_lb);
2403
2404         return 0;
2405 }
2406
2407 static int bnx2x_bmac_enable(struct link_params *params,
2408                              struct link_vars *vars,
2409                              u8 is_lb, u8 reset_bmac)
2410 {
2411         int rc = 0;
2412         u8 port = params->port;
2413         struct bnx2x *bp = params->bp;
2414         u32 val;
2415         /* Reset and unreset the BigMac */
2416         if (reset_bmac) {
2417                 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2418                        (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2419                 usleep_range(1000, 2000);
2420         }
2421
2422         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2423                (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2424
2425         /* Enable access for bmac registers */
2426         REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
2427
2428         /* Enable BMAC according to BMAC type*/
2429         if (CHIP_IS_E2(bp))
2430                 rc = bnx2x_bmac2_enable(params, vars, is_lb);
2431         else
2432                 rc = bnx2x_bmac1_enable(params, vars, is_lb);
2433         REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
2434         REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
2435         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
2436         val = 0;
2437         if ((params->feature_config_flags &
2438               FEATURE_CONFIG_PFC_ENABLED) ||
2439             (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX))
2440                 val = 1;
2441         REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
2442         REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
2443         REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
2444         REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
2445         REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
2446         REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
2447
2448         vars->mac_type = MAC_TYPE_BMAC;
2449         return rc;
2450 }
2451
2452 static void bnx2x_set_bmac_rx(struct bnx2x *bp, u32 chip_id, u8 port, u8 en)
2453 {
2454         u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
2455                         NIG_REG_INGRESS_BMAC0_MEM;
2456         u32 wb_data[2];
2457         u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
2458
2459         if (CHIP_IS_E2(bp))
2460                 bmac_addr += BIGMAC2_REGISTER_BMAC_CONTROL;
2461         else
2462                 bmac_addr += BIGMAC_REGISTER_BMAC_CONTROL;
2463         /* Only if the bmac is out of reset */
2464         if (REG_RD(bp, MISC_REG_RESET_REG_2) &
2465                         (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
2466             nig_bmac_enable) {
2467                 /* Clear Rx Enable bit in BMAC_CONTROL register */
2468                 REG_RD_DMAE(bp, bmac_addr, wb_data, 2);
2469                 if (en)
2470                         wb_data[0] |= BMAC_CONTROL_RX_ENABLE;
2471                 else
2472                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
2473                 REG_WR_DMAE(bp, bmac_addr, wb_data, 2);
2474                 usleep_range(1000, 2000);
2475         }
2476 }
2477
2478 static int bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
2479                             u32 line_speed)
2480 {
2481         struct bnx2x *bp = params->bp;
2482         u8 port = params->port;
2483         u32 init_crd, crd;
2484         u32 count = 1000;
2485
2486         /* Disable port */
2487         REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
2488
2489         /* Wait for init credit */
2490         init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);
2491         crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2492         DP(NETIF_MSG_LINK, "init_crd 0x%x  crd 0x%x\n", init_crd, crd);
2493
2494         while ((init_crd != crd) && count) {
2495                 usleep_range(5000, 10000);
2496                 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2497                 count--;
2498         }
2499         crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
2500         if (init_crd != crd) {
2501                 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n",
2502                           init_crd, crd);
2503                 return -EINVAL;
2504         }
2505
2506         if (flow_ctrl & BNX2X_FLOW_CTRL_RX ||
2507             line_speed == SPEED_10 ||
2508             line_speed == SPEED_100 ||
2509             line_speed == SPEED_1000 ||
2510             line_speed == SPEED_2500) {
2511                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
2512                 /* Update threshold */
2513                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
2514                 /* Update init credit */
2515                 init_crd = 778;         /* (800-18-4) */
2516
2517         } else {
2518                 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE +
2519                               ETH_OVREHEAD)/16;
2520                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
2521                 /* Update threshold */
2522                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
2523                 /* Update init credit */
2524                 switch (line_speed) {
2525                 case SPEED_10000:
2526                         init_crd = thresh + 553 - 22;
2527                         break;
2528                 default:
2529                         DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
2530                                   line_speed);
2531                         return -EINVAL;
2532                 }
2533         }
2534         REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd);
2535         DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",
2536                  line_speed, init_crd);
2537
2538         /* Probe the credit changes */
2539         REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1);
2540         usleep_range(5000, 10000);
2541         REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0);
2542
2543         /* Enable port */
2544         REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
2545         return 0;
2546 }
2547
2548 /**
2549  * bnx2x_get_emac_base - retrive emac base address
2550  *
2551  * @bp:                 driver handle
2552  * @mdc_mdio_access:    access type
2553  * @port:               port id
2554  *
2555  * This function selects the MDC/MDIO access (through emac0 or
2556  * emac1) depend on the mdc_mdio_access, port, port swapped. Each
2557  * phy has a default access mode, which could also be overridden
2558  * by nvram configuration. This parameter, whether this is the
2559  * default phy configuration, or the nvram overrun
2560  * configuration, is passed here as mdc_mdio_access and selects
2561  * the emac_base for the CL45 read/writes operations
2562  */
2563 static u32 bnx2x_get_emac_base(struct bnx2x *bp,
2564                                u32 mdc_mdio_access, u8 port)
2565 {
2566         u32 emac_base = 0;
2567         switch (mdc_mdio_access) {
2568         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE:
2569                 break;
2570         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0:
2571                 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2572                         emac_base = GRCBASE_EMAC1;
2573                 else
2574                         emac_base = GRCBASE_EMAC0;
2575                 break;
2576         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1:
2577                 if (REG_RD(bp, NIG_REG_PORT_SWAP))
2578                         emac_base = GRCBASE_EMAC0;
2579                 else
2580                         emac_base = GRCBASE_EMAC1;
2581                 break;
2582         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH:
2583                 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
2584                 break;
2585         case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED:
2586                 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
2587                 break;
2588         default:
2589                 break;
2590         }
2591         return emac_base;
2592
2593 }
2594
2595 /******************************************************************/
2596 /*                      CL22 access functions                     */
2597 /******************************************************************/
2598 static int bnx2x_cl22_write(struct bnx2x *bp,
2599                                        struct bnx2x_phy *phy,
2600                                        u16 reg, u16 val)
2601 {
2602         u32 tmp, mode;
2603         u8 i;
2604         int rc = 0;
2605         /* Switch to CL22 */
2606         mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2607         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2608                mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2609
2610         /* Address */
2611         tmp = ((phy->addr << 21) | (reg << 16) | val |
2612                EMAC_MDIO_COMM_COMMAND_WRITE_22 |
2613                EMAC_MDIO_COMM_START_BUSY);
2614         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2615
2616         for (i = 0; i < 50; i++) {
2617                 udelay(10);
2618
2619                 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2620                 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2621                         udelay(5);
2622                         break;
2623                 }
2624         }
2625         if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2626                 DP(NETIF_MSG_LINK, "write phy register failed\n");
2627                 rc = -EFAULT;
2628         }
2629         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2630         return rc;
2631 }
2632
2633 static int bnx2x_cl22_read(struct bnx2x *bp,
2634                                       struct bnx2x_phy *phy,
2635                                       u16 reg, u16 *ret_val)
2636 {
2637         u32 val, mode;
2638         u16 i;
2639         int rc = 0;
2640
2641         /* Switch to CL22 */
2642         mode = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
2643         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
2644                mode & ~EMAC_MDIO_MODE_CLAUSE_45);
2645
2646         /* Address */
2647         val = ((phy->addr << 21) | (reg << 16) |
2648                EMAC_MDIO_COMM_COMMAND_READ_22 |
2649                EMAC_MDIO_COMM_START_BUSY);
2650         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2651
2652         for (i = 0; i < 50; i++) {
2653                 udelay(10);
2654
2655                 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2656                 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2657                         *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
2658                         udelay(5);
2659                         break;
2660                 }
2661         }
2662         if (val & EMAC_MDIO_COMM_START_BUSY) {
2663                 DP(NETIF_MSG_LINK, "read phy register failed\n");
2664
2665                 *ret_val = 0;
2666                 rc = -EFAULT;
2667         }
2668         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
2669         return rc;
2670 }
2671
2672 /******************************************************************/
2673 /*                      CL45 access functions                     */
2674 /******************************************************************/
2675 static int bnx2x_cl45_read(struct bnx2x *bp, struct bnx2x_phy *phy,
2676                            u8 devad, u16 reg, u16 *ret_val)
2677 {
2678         u32 val;
2679         u16 i;
2680         int rc = 0;
2681         u32 chip_id;
2682         if (phy->flags & FLAGS_MDC_MDIO_WA_G) {
2683                 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |
2684                           ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);
2685                 bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl);
2686         }
2687
2688         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2689                 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2690                               EMAC_MDIO_STATUS_10MB);
2691         /* Address */
2692         val = ((phy->addr << 21) | (devad << 16) | reg |
2693                EMAC_MDIO_COMM_COMMAND_ADDRESS |
2694                EMAC_MDIO_COMM_START_BUSY);
2695         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2696
2697         for (i = 0; i < 50; i++) {
2698                 udelay(10);
2699
2700                 val = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2701                 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2702                         udelay(5);
2703                         break;
2704                 }
2705         }
2706         if (val & EMAC_MDIO_COMM_START_BUSY) {
2707                 DP(NETIF_MSG_LINK, "read phy register failed\n");
2708                 netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
2709                 *ret_val = 0;
2710                 rc = -EFAULT;
2711         } else {
2712                 /* Data */
2713                 val = ((phy->addr << 21) | (devad << 16) |
2714                        EMAC_MDIO_COMM_COMMAND_READ_45 |
2715                        EMAC_MDIO_COMM_START_BUSY);
2716                 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
2717
2718                 for (i = 0; i < 50; i++) {
2719                         udelay(10);
2720
2721                         val = REG_RD(bp, phy->mdio_ctrl +
2722                                      EMAC_REG_EMAC_MDIO_COMM);
2723                         if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
2724                                 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
2725                                 break;
2726                         }
2727                 }
2728                 if (val & EMAC_MDIO_COMM_START_BUSY) {
2729                         DP(NETIF_MSG_LINK, "read phy register failed\n");
2730                         netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
2731                         *ret_val = 0;
2732                         rc = -EFAULT;
2733                 }
2734         }
2735         /* Work around for E3 A0 */
2736         if (phy->flags & FLAGS_MDC_MDIO_WA) {
2737                 phy->flags ^= FLAGS_DUMMY_READ;
2738                 if (phy->flags & FLAGS_DUMMY_READ) {
2739                         u16 temp_val;
2740                         bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
2741                 }
2742         }
2743
2744         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2745                 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2746                                EMAC_MDIO_STATUS_10MB);
2747         return rc;
2748 }
2749
2750 static int bnx2x_cl45_write(struct bnx2x *bp, struct bnx2x_phy *phy,
2751                             u8 devad, u16 reg, u16 val)
2752 {
2753         u32 tmp;
2754         u8 i;
2755         int rc = 0;
2756         u32 chip_id;
2757         if (phy->flags & FLAGS_MDC_MDIO_WA_G) {
2758                 chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |
2759                           ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);
2760                 bnx2x_set_mdio_clk(bp, chip_id, phy->mdio_ctrl);
2761         }
2762
2763         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2764                 bnx2x_bits_en(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2765                               EMAC_MDIO_STATUS_10MB);
2766
2767         /* Address */
2768         tmp = ((phy->addr << 21) | (devad << 16) | reg |
2769                EMAC_MDIO_COMM_COMMAND_ADDRESS |
2770                EMAC_MDIO_COMM_START_BUSY);
2771         REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2772
2773         for (i = 0; i < 50; i++) {
2774                 udelay(10);
2775
2776                 tmp = REG_RD(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
2777                 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2778                         udelay(5);
2779                         break;
2780                 }
2781         }
2782         if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2783                 DP(NETIF_MSG_LINK, "write phy register failed\n");
2784                 netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
2785                 rc = -EFAULT;
2786         } else {
2787                 /* Data */
2788                 tmp = ((phy->addr << 21) | (devad << 16) | val |
2789                        EMAC_MDIO_COMM_COMMAND_WRITE_45 |
2790                        EMAC_MDIO_COMM_START_BUSY);
2791                 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
2792
2793                 for (i = 0; i < 50; i++) {
2794                         udelay(10);
2795
2796                         tmp = REG_RD(bp, phy->mdio_ctrl +
2797                                      EMAC_REG_EMAC_MDIO_COMM);
2798                         if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
2799                                 udelay(5);
2800                                 break;
2801                         }
2802                 }
2803                 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
2804                         DP(NETIF_MSG_LINK, "write phy register failed\n");
2805                         netdev_err(bp->dev,  "MDC/MDIO access timeout\n");
2806                         rc = -EFAULT;
2807                 }
2808         }
2809         /* Work around for E3 A0 */
2810         if (phy->flags & FLAGS_MDC_MDIO_WA) {
2811                 phy->flags ^= FLAGS_DUMMY_READ;
2812                 if (phy->flags & FLAGS_DUMMY_READ) {
2813                         u16 temp_val;
2814                         bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val);
2815                 }
2816         }
2817         if (phy->flags & FLAGS_MDC_MDIO_WA_B0)
2818                 bnx2x_bits_dis(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
2819                                EMAC_MDIO_STATUS_10MB);
2820         return rc;
2821 }
2822
2823 /******************************************************************/
2824 /*                      EEE section                                */
2825 /******************************************************************/
2826 static u8 bnx2x_eee_has_cap(struct link_params *params)
2827 {
2828         struct bnx2x *bp = params->bp;
2829
2830         if (REG_RD(bp, params->shmem2_base) <=
2831                    offsetof(struct shmem2_region, eee_status[params->port]))
2832                 return 0;
2833
2834         return 1;
2835 }
2836
2837 static int bnx2x_eee_nvram_to_time(u32 nvram_mode, u32 *idle_timer)
2838 {
2839         switch (nvram_mode) {
2840         case PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED:
2841                 *idle_timer = EEE_MODE_NVRAM_BALANCED_TIME;
2842                 break;
2843         case PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE:
2844                 *idle_timer = EEE_MODE_NVRAM_AGGRESSIVE_TIME;
2845                 break;
2846         case PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY:
2847                 *idle_timer = EEE_MODE_NVRAM_LATENCY_TIME;
2848                 break;
2849         default:
2850                 *idle_timer = 0;
2851                 break;
2852         }
2853
2854         return 0;
2855 }
2856
2857 static int bnx2x_eee_time_to_nvram(u32 idle_timer, u32 *nvram_mode)
2858 {
2859         switch (idle_timer) {
2860         case EEE_MODE_NVRAM_BALANCED_TIME:
2861                 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED;
2862                 break;
2863         case EEE_MODE_NVRAM_AGGRESSIVE_TIME:
2864                 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE;
2865                 break;
2866         case EEE_MODE_NVRAM_LATENCY_TIME:
2867                 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY;
2868                 break;
2869         default:
2870                 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED;
2871                 break;
2872         }
2873
2874         return 0;
2875 }
2876
2877 static u32 bnx2x_eee_calc_timer(struct link_params *params)
2878 {
2879         u32 eee_mode, eee_idle;
2880         struct bnx2x *bp = params->bp;
2881
2882         if (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) {
2883                 if (params->eee_mode & EEE_MODE_OUTPUT_TIME) {
2884                         /* time value in eee_mode --> used directly*/
2885                         eee_idle = params->eee_mode & EEE_MODE_TIMER_MASK;
2886                 } else {
2887                         /* hsi value in eee_mode --> time */
2888                         if (bnx2x_eee_nvram_to_time(params->eee_mode &
2889                                                     EEE_MODE_NVRAM_MASK,
2890                                                     &eee_idle))
2891                                 return 0;
2892                 }
2893         } else {
2894                 /* hsi values in nvram --> time*/
2895                 eee_mode = ((REG_RD(bp, params->shmem_base +
2896                                     offsetof(struct shmem_region, dev_info.
2897                                     port_feature_config[params->port].
2898                                     eee_power_mode)) &
2899                              PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
2900                             PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
2901
2902                 if (bnx2x_eee_nvram_to_time(eee_mode, &eee_idle))
2903                         return 0;
2904         }
2905
2906         return eee_idle;
2907 }
2908
2909 static int bnx2x_eee_set_timers(struct link_params *params,
2910                                    struct link_vars *vars)
2911 {
2912         u32 eee_idle = 0, eee_mode;
2913         struct bnx2x *bp = params->bp;
2914
2915         eee_idle = bnx2x_eee_calc_timer(params);
2916
2917         if (eee_idle) {
2918                 REG_WR(bp, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2),
2919                        eee_idle);
2920         } else if ((params->eee_mode & EEE_MODE_ENABLE_LPI) &&
2921                    (params->eee_mode & EEE_MODE_OVERRIDE_NVRAM) &&
2922                    (params->eee_mode & EEE_MODE_OUTPUT_TIME)) {
2923                 DP(NETIF_MSG_LINK, "Error: Tx LPI is enabled with timer 0\n");
2924                 return -EINVAL;
2925         }
2926
2927         vars->eee_status &= ~(SHMEM_EEE_TIMER_MASK | SHMEM_EEE_TIME_OUTPUT_BIT);
2928         if (params->eee_mode & EEE_MODE_OUTPUT_TIME) {
2929                 /* eee_idle in 1u --> eee_status in 16u */
2930                 eee_idle >>= 4;
2931                 vars->eee_status |= (eee_idle & SHMEM_EEE_TIMER_MASK) |
2932                                     SHMEM_EEE_TIME_OUTPUT_BIT;
2933         } else {
2934                 if (bnx2x_eee_time_to_nvram(eee_idle, &eee_mode))
2935                         return -EINVAL;
2936                 vars->eee_status |= eee_mode;
2937         }
2938
2939         return 0;
2940 }
2941
2942 static int bnx2x_eee_initial_config(struct link_params *params,
2943                                      struct link_vars *vars, u8 mode)
2944 {
2945         vars->eee_status |= ((u32) mode) << SHMEM_EEE_SUPPORTED_SHIFT;
2946
2947         /* Propagate params' bits --> vars (for migration exposure) */
2948         if (params->eee_mode & EEE_MODE_ENABLE_LPI)
2949                 vars->eee_status |= SHMEM_EEE_LPI_REQUESTED_BIT;
2950         else
2951                 vars->eee_status &= ~SHMEM_EEE_LPI_REQUESTED_BIT;
2952
2953         if (params->eee_mode & EEE_MODE_ADV_LPI)
2954                 vars->eee_status |= SHMEM_EEE_REQUESTED_BIT;
2955         else
2956                 vars->eee_status &= ~SHMEM_EEE_REQUESTED_BIT;
2957
2958         return bnx2x_eee_set_timers(params, vars);
2959 }
2960
2961 static int bnx2x_eee_disable(struct bnx2x_phy *phy,
2962                                 struct link_params *params,
2963                                 struct link_vars *vars)
2964 {
2965         struct bnx2x *bp = params->bp;
2966
2967         /* Make Certain LPI is disabled */
2968         REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0);
2969
2970         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0x0);
2971
2972         vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK;
2973
2974         return 0;
2975 }
2976
2977 static int bnx2x_eee_advertise(struct bnx2x_phy *phy,
2978                                   struct link_params *params,
2979                                   struct link_vars *vars, u8 modes)
2980 {
2981         struct bnx2x *bp = params->bp;
2982         u16 val = 0;
2983
2984         /* Mask events preventing LPI generation */
2985         REG_WR(bp, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20);
2986
2987         if (modes & SHMEM_EEE_10G_ADV) {
2988                 DP(NETIF_MSG_LINK, "Advertise 10GBase-T EEE\n");
2989                 val |= 0x8;
2990         }
2991         if (modes & SHMEM_EEE_1G_ADV) {
2992                 DP(NETIF_MSG_LINK, "Advertise 1GBase-T EEE\n");
2993                 val |= 0x4;
2994         }
2995
2996         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, val);
2997
2998         vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK;
2999         vars->eee_status |= (modes << SHMEM_EEE_ADV_STATUS_SHIFT);
3000
3001         return 0;
3002 }
3003
3004 static void bnx2x_update_mng_eee(struct link_params *params, u32 eee_status)
3005 {
3006         struct bnx2x *bp = params->bp;
3007
3008         if (bnx2x_eee_has_cap(params))
3009                 REG_WR(bp, params->shmem2_base +
3010                        offsetof(struct shmem2_region,
3011                                 eee_status[params->port]), eee_status);
3012 }
3013
3014 static void bnx2x_eee_an_resolve(struct bnx2x_phy *phy,
3015                                   struct link_params *params,
3016                                   struct link_vars *vars)
3017 {
3018         struct bnx2x *bp = params->bp;
3019         u16 adv = 0, lp = 0;
3020         u32 lp_adv = 0;
3021         u8 neg = 0;
3022
3023         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, &adv);
3024         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LP_EEE_ADV, &lp);
3025
3026         if (lp & 0x2) {
3027                 lp_adv |= SHMEM_EEE_100M_ADV;
3028                 if (adv & 0x2) {
3029                         if (vars->line_speed == SPEED_100)
3030                                 neg = 1;
3031                         DP(NETIF_MSG_LINK, "EEE negotiated - 100M\n");
3032                 }
3033         }
3034         if (lp & 0x14) {
3035                 lp_adv |= SHMEM_EEE_1G_ADV;
3036                 if (adv & 0x14) {
3037                         if (vars->line_speed == SPEED_1000)
3038                                 neg = 1;
3039                         DP(NETIF_MSG_LINK, "EEE negotiated - 1G\n");
3040                 }
3041         }
3042         if (lp & 0x68) {
3043                 lp_adv |= SHMEM_EEE_10G_ADV;
3044                 if (adv & 0x68) {
3045                         if (vars->line_speed == SPEED_10000)
3046                                 neg = 1;
3047                         DP(NETIF_MSG_LINK, "EEE negotiated - 10G\n");
3048                 }
3049         }
3050
3051         vars->eee_status &= ~SHMEM_EEE_LP_ADV_STATUS_MASK;
3052         vars->eee_status |= (lp_adv << SHMEM_EEE_LP_ADV_STATUS_SHIFT);
3053
3054         if (neg) {
3055                 DP(NETIF_MSG_LINK, "EEE is active\n");
3056                 vars->eee_status |= SHMEM_EEE_ACTIVE_BIT;
3057         }
3058
3059 }
3060
3061 /******************************************************************/
3062 /*                      BSC access functions from E3              */
3063 /******************************************************************/
3064 static void bnx2x_bsc_module_sel(struct link_params *params)
3065 {
3066         int idx;
3067         u32 board_cfg, sfp_ctrl;
3068         u32 i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH];
3069         struct bnx2x *bp = params->bp;
3070         u8 port = params->port;
3071         /* Read I2C output PINs */
3072         board_cfg = REG_RD(bp, params->shmem_base +
3073                            offsetof(struct shmem_region,
3074                                     dev_info.shared_hw_config.board));
3075         i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK;
3076         i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >>
3077                         SHARED_HW_CFG_E3_I2C_MUX1_SHIFT;
3078
3079         /* Read I2C output value */
3080         sfp_ctrl = REG_RD(bp, params->shmem_base +
3081                           offsetof(struct shmem_region,
3082                                  dev_info.port_hw_config[port].e3_cmn_pin_cfg));
3083         i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0;
3084         i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0;
3085         DP(NETIF_MSG_LINK, "Setting BSC switch\n");
3086         for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++)
3087                 bnx2x_set_cfg_pin(bp, i2c_pins[idx], i2c_val[idx]);
3088 }
3089
3090 static int bnx2x_bsc_read(struct link_params *params,
3091                           struct bnx2x *bp,
3092                           u8 sl_devid,
3093                           u16 sl_addr,
3094                           u8 lc_addr,
3095                           u8 xfer_cnt,
3096                           u32 *data_array)
3097 {
3098         u32 val, i;
3099         int rc = 0;
3100
3101         if (xfer_cnt > 16) {
3102                 DP(NETIF_MSG_LINK, "invalid xfer_cnt %d. Max is 16 bytes\n",
3103                                         xfer_cnt);
3104                 return -EINVAL;
3105         }
3106         bnx2x_bsc_module_sel(params);
3107
3108         xfer_cnt = 16 - lc_addr;
3109
3110         /* Enable the engine */
3111         val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3112         val |= MCPR_IMC_COMMAND_ENABLE;
3113         REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3114
3115         /* Program slave device ID */
3116         val = (sl_devid << 16) | sl_addr;
3117         REG_WR(bp, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val);
3118
3119         /* Start xfer with 0 byte to update the address pointer ???*/
3120         val = (MCPR_IMC_COMMAND_ENABLE) |
3121               (MCPR_IMC_COMMAND_WRITE_OP <<
3122                 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3123                 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0);
3124         REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3125
3126         /* Poll for completion */
3127         i = 0;
3128         val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3129         while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3130                 udelay(10);
3131                 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3132                 if (i++ > 1000) {
3133                         DP(NETIF_MSG_LINK, "wr 0 byte timed out after %d try\n",
3134                                                                 i);
3135                         rc = -EFAULT;
3136                         break;
3137                 }
3138         }
3139         if (rc == -EFAULT)
3140                 return rc;
3141
3142         /* Start xfer with read op */
3143         val = (MCPR_IMC_COMMAND_ENABLE) |
3144                 (MCPR_IMC_COMMAND_READ_OP <<
3145                 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3146                 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) |
3147                   (xfer_cnt);
3148         REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val);
3149
3150         /* Poll for completion */
3151         i = 0;
3152         val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3153         while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3154                 udelay(10);
3155                 val = REG_RD(bp, MCP_REG_MCPR_IMC_COMMAND);
3156                 if (i++ > 1000) {
3157                         DP(NETIF_MSG_LINK, "rd op timed out after %d try\n", i);
3158                         rc = -EFAULT;
3159                         break;
3160                 }
3161         }
3162         if (rc == -EFAULT)
3163                 return rc;
3164
3165         for (i = (lc_addr >> 2); i < 4; i++) {
3166                 data_array[i] = REG_RD(bp, (MCP_REG_MCPR_IMC_DATAREG0 + i*4));
3167 #ifdef __BIG_ENDIAN
3168                 data_array[i] = ((data_array[i] & 0x000000ff) << 24) |
3169                                 ((data_array[i] & 0x0000ff00) << 8) |
3170                                 ((data_array[i] & 0x00ff0000) >> 8) |
3171                                 ((data_array[i] & 0xff000000) >> 24);
3172 #endif
3173         }
3174         return rc;
3175 }
3176
3177 static void bnx2x_cl45_read_or_write(struct bnx2x *bp, struct bnx2x_phy *phy,
3178                                      u8 devad, u16 reg, u16 or_val)
3179 {
3180         u16 val;
3181         bnx2x_cl45_read(bp, phy, devad, reg, &val);
3182         bnx2x_cl45_write(bp, phy, devad, reg, val | or_val);
3183 }
3184
3185 static void bnx2x_cl45_read_and_write(struct bnx2x *bp,
3186                                       struct bnx2x_phy *phy,
3187                                       u8 devad, u16 reg, u16 and_val)
3188 {
3189         u16 val;
3190         bnx2x_cl45_read(bp, phy, devad, reg, &val);
3191         bnx2x_cl45_write(bp, phy, devad, reg, val & and_val);
3192 }
3193
3194 int bnx2x_phy_read(struct link_params *params, u8 phy_addr,
3195                    u8 devad, u16 reg, u16 *ret_val)
3196 {
3197         u8 phy_index;
3198         /* Probe for the phy according to the given phy_addr, and execute
3199          * the read request on it
3200          */
3201         for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3202                 if (params->phy[phy_index].addr == phy_addr) {
3203                         return bnx2x_cl45_read(params->bp,
3204                                                &params->phy[phy_index], devad,
3205                                                reg, ret_val);
3206                 }
3207         }
3208         return -EINVAL;
3209 }
3210
3211 int bnx2x_phy_write(struct link_params *params, u8 phy_addr,
3212                     u8 devad, u16 reg, u16 val)
3213 {
3214         u8 phy_index;
3215         /* Probe for the phy according to the given phy_addr, and execute
3216          * the write request on it
3217          */
3218         for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3219                 if (params->phy[phy_index].addr == phy_addr) {
3220                         return bnx2x_cl45_write(params->bp,
3221                                                 &params->phy[phy_index], devad,
3222                                                 reg, val);
3223                 }
3224         }
3225         return -EINVAL;
3226 }
3227 static u8 bnx2x_get_warpcore_lane(struct bnx2x_phy *phy,
3228                                   struct link_params *params)
3229 {
3230         u8 lane = 0;
3231         struct bnx2x *bp = params->bp;
3232         u32 path_swap, path_swap_ovr;
3233         u8 path, port;
3234
3235         path = BP_PATH(bp);
3236         port = params->port;
3237
3238         if (bnx2x_is_4_port_mode(bp)) {
3239                 u32 port_swap, port_swap_ovr;
3240
3241                 /* Figure out path swap value */
3242                 path_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR);
3243                 if (path_swap_ovr & 0x1)
3244                         path_swap = (path_swap_ovr & 0x2);
3245                 else
3246                         path_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PATH_SWAP);
3247
3248                 if (path_swap)
3249                         path = path ^ 1;
3250
3251                 /* Figure out port swap value */
3252                 port_swap_ovr = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR);
3253                 if (port_swap_ovr & 0x1)
3254                         port_swap = (port_swap_ovr & 0x2);
3255                 else
3256                         port_swap = REG_RD(bp, MISC_REG_FOUR_PORT_PORT_SWAP);
3257
3258                 if (port_swap)
3259                         port = port ^ 1;
3260
3261                 lane = (port<<1) + path;
3262         } else { /* Two port mode - no port swap */
3263
3264                 /* Figure out path swap value */
3265                 path_swap_ovr =
3266                         REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP_OVWR);
3267                 if (path_swap_ovr & 0x1) {
3268                         path_swap = (path_swap_ovr & 0x2);
3269                 } else {
3270                         path_swap =
3271                                 REG_RD(bp, MISC_REG_TWO_PORT_PATH_SWAP);
3272                 }
3273                 if (path_swap)
3274                         path = path ^ 1;
3275
3276                 lane = path << 1 ;
3277         }
3278         return lane;
3279 }
3280
3281 static void bnx2x_set_aer_mmd(struct link_params *params,
3282                               struct bnx2x_phy *phy)
3283 {
3284         u32 ser_lane;
3285         u16 offset, aer_val;
3286         struct bnx2x *bp = params->bp;
3287         ser_lane = ((params->lane_config &
3288                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
3289                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
3290
3291         offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ?
3292                 (phy->addr + ser_lane) : 0;
3293
3294         if (USES_WARPCORE(bp)) {
3295                 aer_val = bnx2x_get_warpcore_lane(phy, params);
3296                 /* In Dual-lane mode, two lanes are joined together,
3297                  * so in order to configure them, the AER broadcast method is
3298                  * used here.
3299                  * 0x200 is the broadcast address for lanes 0,1
3300                  * 0x201 is the broadcast address for lanes 2,3
3301                  */
3302                 if (phy->flags & FLAGS_WC_DUAL_MODE)
3303                         aer_val = (aer_val >> 1) | 0x200;
3304         } else if (CHIP_IS_E2(bp))
3305                 aer_val = 0x3800 + offset - 1;
3306         else
3307                 aer_val = 0x3800 + offset;
3308
3309         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3310                           MDIO_AER_BLOCK_AER_REG, aer_val);
3311
3312 }
3313
3314 /******************************************************************/
3315 /*                      Internal phy section                      */
3316 /******************************************************************/
3317
3318 static void bnx2x_set_serdes_access(struct bnx2x *bp, u8 port)
3319 {
3320         u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
3321
3322         /* Set Clause 22 */
3323         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1);
3324         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
3325         udelay(500);
3326         REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
3327         udelay(500);
3328          /* Set Clause 45 */
3329         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0);
3330 }
3331
3332 static void bnx2x_serdes_deassert(struct bnx2x *bp, u8 port)
3333 {
3334         u32 val;
3335
3336         DP(NETIF_MSG_LINK, "bnx2x_serdes_deassert\n");
3337
3338         val = SERDES_RESET_BITS << (port*16);
3339
3340         /* Reset and unreset the SerDes/XGXS */
3341         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3342         udelay(500);
3343         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3344
3345         bnx2x_set_serdes_access(bp, port);
3346
3347         REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10,
3348                DEFAULT_PHY_DEV_ADDR);
3349 }
3350
3351 static void bnx2x_xgxs_specific_func(struct bnx2x_phy *phy,
3352                                      struct link_params *params,
3353                                      u32 action)
3354 {
3355         struct bnx2x *bp = params->bp;
3356         switch (action) {
3357         case PHY_INIT:
3358                 /* Set correct devad */
3359                 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + params->port*0x18, 0);
3360                 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18,
3361                        phy->def_md_devad);
3362                 break;
3363         }
3364 }
3365
3366 static void bnx2x_xgxs_deassert(struct link_params *params)
3367 {
3368         struct bnx2x *bp = params->bp;
3369         u8 port;
3370         u32 val;
3371         DP(NETIF_MSG_LINK, "bnx2x_xgxs_deassert\n");
3372         port = params->port;
3373
3374         val = XGXS_RESET_BITS << (port*16);
3375
3376         /* Reset and unreset the SerDes/XGXS */
3377         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
3378         udelay(500);
3379         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
3380         bnx2x_xgxs_specific_func(&params->phy[INT_PHY], params,
3381                                  PHY_INIT);
3382 }
3383
3384 static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy *phy,
3385                                      struct link_params *params, u16 *ieee_fc)
3386 {
3387         struct bnx2x *bp = params->bp;
3388         *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
3389         /* Resolve pause mode and advertisement Please refer to Table
3390          * 28B-3 of the 802.3ab-1999 spec
3391          */
3392
3393         switch (phy->req_flow_ctrl) {
3394         case BNX2X_FLOW_CTRL_AUTO:
3395                 switch (params->req_fc_auto_adv) {
3396                 case BNX2X_FLOW_CTRL_BOTH:
3397                 case BNX2X_FLOW_CTRL_RX:
3398                         *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3399                         break;
3400                 case BNX2X_FLOW_CTRL_TX:
3401                         *ieee_fc |=
3402                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3403                         break;
3404                 default:
3405                         break;
3406                 }
3407                 break;
3408         case BNX2X_FLOW_CTRL_TX:
3409                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
3410                 break;
3411
3412         case BNX2X_FLOW_CTRL_RX:
3413         case BNX2X_FLOW_CTRL_BOTH:
3414                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
3415                 break;
3416
3417         case BNX2X_FLOW_CTRL_NONE:
3418         default:
3419                 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
3420                 break;
3421         }
3422         DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc);
3423 }
3424
3425 static void set_phy_vars(struct link_params *params,
3426                          struct link_vars *vars)
3427 {
3428         struct bnx2x *bp = params->bp;
3429         u8 actual_phy_idx, phy_index, link_cfg_idx;
3430         u8 phy_config_swapped = params->multi_phy_config &
3431                         PORT_HW_CFG_PHY_SWAPPED_ENABLED;
3432         for (phy_index = INT_PHY; phy_index < params->num_phys;
3433               phy_index++) {
3434                 link_cfg_idx = LINK_CONFIG_IDX(phy_index);
3435                 actual_phy_idx = phy_index;
3436                 if (phy_config_swapped) {
3437                         if (phy_index == EXT_PHY1)
3438                                 actual_phy_idx = EXT_PHY2;
3439                         else if (phy_index == EXT_PHY2)
3440                                 actual_phy_idx = EXT_PHY1;
3441                 }
3442                 params->phy[actual_phy_idx].req_flow_ctrl =
3443                         params->req_flow_ctrl[link_cfg_idx];
3444
3445                 params->phy[actual_phy_idx].req_line_speed =
3446                         params->req_line_speed[link_cfg_idx];
3447
3448                 params->phy[actual_phy_idx].speed_cap_mask =
3449                         params->speed_cap_mask[link_cfg_idx];
3450
3451                 params->phy[actual_phy_idx].req_duplex =
3452                         params->req_duplex[link_cfg_idx];
3453
3454                 if (params->req_line_speed[link_cfg_idx] ==
3455                     SPEED_AUTO_NEG)
3456                         vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
3457
3458                 DP(NETIF_MSG_LINK, "req_flow_ctrl %x, req_line_speed %x,"
3459                            " speed_cap_mask %x\n",
3460                            params->phy[actual_phy_idx].req_flow_ctrl,
3461                            params->phy[actual_phy_idx].req_line_speed,
3462                            params->phy[actual_phy_idx].speed_cap_mask);
3463         }
3464 }
3465
3466 static void bnx2x_ext_phy_set_pause(struct link_params *params,
3467                                     struct bnx2x_phy *phy,
3468                                     struct link_vars *vars)
3469 {
3470         u16 val;
3471         struct bnx2x *bp = params->bp;
3472         /* Read modify write pause advertizing */
3473         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);
3474
3475         val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
3476
3477         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3478         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
3479         if ((vars->ieee_fc &
3480             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
3481             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
3482                 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
3483         }
3484         if ((vars->ieee_fc &
3485             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
3486             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
3487                 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
3488         }
3489         DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val);
3490         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
3491 }
3492
3493 static void bnx2x_pause_resolve(struct bnx2x_phy *phy,
3494                                 struct link_params *params,
3495                                 struct link_vars *vars,
3496                                 u32 pause_result)
3497 {
3498         struct bnx2x *bp = params->bp;
3499                                                 /*  LD      LP   */
3500         switch (pause_result) {                 /* ASYM P ASYM P */
3501         case 0xb:                               /*   1  0   1  1 */
3502                 DP(NETIF_MSG_LINK, "Flow Control: TX only\n");
3503                 vars->flow_ctrl = BNX2X_FLOW_CTRL_TX;
3504                 break;
3505
3506         case 0xe:                               /*   1  1   1  0 */
3507                 DP(NETIF_MSG_LINK, "Flow Control: RX only\n");
3508                 vars->flow_ctrl = BNX2X_FLOW_CTRL_RX;
3509                 break;
3510
3511         case 0x5:                               /*   0  1   0  1 */
3512         case 0x7:                               /*   0  1   1  1 */
3513         case 0xd:                               /*   1  1   0  1 */
3514         case 0xf:                               /*   1  1   1  1 */
3515                 /* If the user selected to advertise RX ONLY,
3516                  * although we advertised both, need to enable
3517                  * RX only.
3518                  */
3519                 if (params->req_fc_auto_adv == BNX2X_FLOW_CTRL_BOTH) {
3520                         DP(NETIF_MSG_LINK, "Flow Control: RX & TX\n");
3521                         vars->flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
3522                 } else {
3523                         DP(NETIF_MSG_LINK, "Flow Control: RX only\n");
3524                         vars->flow_ctrl = BNX2X_FLOW_CTRL_RX;
3525                 }
3526                 break;
3527
3528         default:
3529                 DP(NETIF_MSG_LINK, "Flow Control: None\n");
3530                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
3531                 break;
3532         }
3533         if (pause_result & (1<<0))
3534                 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;
3535         if (pause_result & (1<<1))
3536                 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;
3537
3538 }
3539
3540 static void bnx2x_ext_phy_update_adv_fc(struct bnx2x_phy *phy,
3541                                         struct link_params *params,
3542                                         struct link_vars *vars)
3543 {
3544         u16 ld_pause;           /* local */
3545         u16 lp_pause;           /* link partner */
3546         u16 pause_result;
3547         struct bnx2x *bp = params->bp;
3548         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) {
3549                 bnx2x_cl22_read(bp, phy, 0x4, &ld_pause);
3550                 bnx2x_cl22_read(bp, phy, 0x5, &lp_pause);
3551         } else if (CHIP_IS_E3(bp) &&
3552                 SINGLE_MEDIA_DIRECT(params)) {
3553                 u8 lane = bnx2x_get_warpcore_lane(phy, params);
3554                 u16 gp_status, gp_mask;
3555                 bnx2x_cl45_read(bp, phy,
3556                                 MDIO_AN_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_4,
3557                                 &gp_status);
3558                 gp_mask = (MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL |
3559                            MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP) <<
3560                         lane;
3561                 if ((gp_status & gp_mask) == gp_mask) {
3562                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3563                                         MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3564                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3565                                         MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3566                 } else {
3567                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3568                                         MDIO_AN_REG_CL37_FC_LD, &ld_pause);
3569                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
3570                                         MDIO_AN_REG_CL37_FC_LP, &lp_pause);
3571                         ld_pause = ((ld_pause &
3572                                      MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
3573                                     << 3);
3574                         lp_pause = ((lp_pause &
3575                                      MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
3576                                     << 3);
3577                 }
3578         } else {
3579                 bnx2x_cl45_read(bp, phy,
3580                                 MDIO_AN_DEVAD,
3581                                 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
3582                 bnx2x_cl45_read(bp, phy,
3583                                 MDIO_AN_DEVAD,
3584                                 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
3585         }
3586         pause_result = (ld_pause &
3587                         MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
3588         pause_result |= (lp_pause &
3589                          MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
3590         DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n", pause_result);
3591         bnx2x_pause_resolve(phy, params, vars, pause_result);
3592
3593 }
3594
3595 static u8 bnx2x_ext_phy_resolve_fc(struct bnx2x_phy *phy,
3596                                    struct link_params *params,
3597                                    struct link_vars *vars)
3598 {
3599         u8 ret = 0;
3600         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
3601         if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) {
3602                 /* Update the advertised flow-controled of LD/LP in AN */
3603                 if (phy->req_line_speed == SPEED_AUTO_NEG)
3604                         bnx2x_ext_phy_update_adv_fc(phy, params, vars);
3605                 /* But set the flow-control result as the requested one */
3606                 vars->flow_ctrl = phy->req_flow_ctrl;
3607         } else if (phy->req_line_speed != SPEED_AUTO_NEG)
3608                 vars->flow_ctrl = params->req_fc_auto_adv;
3609         else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
3610                 ret = 1;
3611                 bnx2x_ext_phy_update_adv_fc(phy, params, vars);
3612         }
3613         return ret;
3614 }
3615 /******************************************************************/
3616 /*                      Warpcore section                          */
3617 /******************************************************************/
3618 /* The init_internal_warpcore should mirror the xgxs,
3619  * i.e. reset the lane (if needed), set aer for the
3620  * init configuration, and set/clear SGMII flag. Internal
3621  * phy init is done purely in phy_init stage.
3622  */
3623 #define WC_TX_DRIVER(post2, idriver, ipre, ifir) \
3624         ((post2 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | \
3625          (idriver << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | \
3626          (ipre << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET) | \
3627          (ifir << MDIO_WC_REG_TX0_TX_DRIVER_IFIR_OFFSET))
3628
3629 #define WC_TX_FIR(post, main, pre) \
3630         ((post << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | \
3631          (main << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | \
3632          (pre << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET))
3633
3634 static void bnx2x_warpcore_enable_AN_KR2(struct bnx2x_phy *phy,
3635                                          struct link_params *params,
3636                                          struct link_vars *vars)
3637 {
3638         struct bnx2x *bp = params->bp;
3639         u16 i;
3640         static struct bnx2x_reg_set reg_set[] = {
3641                 /* Step 1 - Program the TX/RX alignment markers */
3642                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0xa157},
3643                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xcbe2},
3644                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0x7537},
3645                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0xa157},
3646                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xcbe2},
3647                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0x7537},
3648                 /* Step 2 - Configure the NP registers */
3649                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000a},
3650                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6400},
3651                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0620},
3652                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0157},
3653                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x6464},
3654                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x3150},
3655                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x3150},
3656                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0157},
3657                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0620}
3658         };
3659         DP(NETIF_MSG_LINK, "Enabling 20G-KR2\n");
3660
3661         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3662                                  MDIO_WC_REG_CL49_USERB0_CTRL, (3<<6));
3663
3664         for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3665                 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
3666                                  reg_set[i].val);
3667
3668         /* Start KR2 work-around timer which handles BCM8073 link-parner */
3669         params->link_attr_sync |= LINK_ATTR_SYNC_KR2_ENABLE;
3670         bnx2x_update_link_attr(params, params->link_attr_sync);
3671 }
3672
3673 static void bnx2x_disable_kr2(struct link_params *params,
3674                               struct link_vars *vars,
3675                               struct bnx2x_phy *phy)
3676 {
3677         struct bnx2x *bp = params->bp;
3678         int i;
3679         static struct bnx2x_reg_set reg_set[] = {
3680                 /* Step 1 - Program the TX/RX alignment markers */
3681                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0x7690},
3682                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xe647},
3683                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0xc4f0},
3684                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0x7690},
3685                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xe647},
3686                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0xc4f0},
3687                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000c},
3688                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6000},
3689                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0000},
3690                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0002},
3691                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x0000},
3692                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x0af7},
3693                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x0af7},
3694                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0002},
3695                 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0000}
3696         };
3697         DP(NETIF_MSG_LINK, "Disabling 20G-KR2\n");
3698
3699         for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3700                 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
3701                                  reg_set[i].val);
3702         params->link_attr_sync &= ~LINK_ATTR_SYNC_KR2_ENABLE;
3703         bnx2x_update_link_attr(params, params->link_attr_sync);
3704
3705         vars->check_kr2_recovery_cnt = CHECK_KR2_RECOVERY_CNT;
3706 }
3707
3708 static void bnx2x_warpcore_set_lpi_passthrough(struct bnx2x_phy *phy,
3709                                                struct link_params *params)
3710 {
3711         struct bnx2x *bp = params->bp;
3712
3713         DP(NETIF_MSG_LINK, "Configure WC for LPI pass through\n");
3714         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3715                          MDIO_WC_REG_EEE_COMBO_CONTROL0, 0x7c);
3716         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3717                                  MDIO_WC_REG_DIGITAL4_MISC5, 0xc000);
3718 }
3719
3720 static void bnx2x_warpcore_restart_AN_KR(struct bnx2x_phy *phy,
3721                                          struct link_params *params)
3722 {
3723         /* Restart autoneg on the leading lane only */
3724         struct bnx2x *bp = params->bp;
3725         u16 lane = bnx2x_get_warpcore_lane(phy, params);
3726         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3727                           MDIO_AER_BLOCK_AER_REG, lane);
3728         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3729                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
3730
3731         /* Restore AER */
3732         bnx2x_set_aer_mmd(params, phy);
3733 }
3734
3735 static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy,
3736                                         struct link_params *params,
3737                                         struct link_vars *vars) {
3738         u16 lane, i, cl72_ctrl, an_adv = 0, val;
3739         u32 wc_lane_config;
3740         struct bnx2x *bp = params->bp;
3741         static struct bnx2x_reg_set reg_set[] = {
3742                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
3743                 {MDIO_PMA_DEVAD, MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0x0},
3744                 {MDIO_WC_DEVAD, MDIO_WC_REG_RX66_CONTROL, 0x7415},
3745                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x6190},
3746                 /* Disable Autoneg: re-enable it after adv is done. */
3747                 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0},
3748                 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2},
3749                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0},
3750         };
3751         DP(NETIF_MSG_LINK, "Enable Auto Negotiation for KR\n");
3752         /* Set to default registers that may be overriden by 10G force */
3753         for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3754                 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
3755                                  reg_set[i].val);
3756
3757         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3758                         MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &cl72_ctrl);
3759         cl72_ctrl &= 0x08ff;
3760         cl72_ctrl |= 0x3800;
3761         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3762                          MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, cl72_ctrl);
3763
3764         /* Check adding advertisement for 1G KX */
3765         if (((vars->line_speed == SPEED_AUTO_NEG) &&
3766              (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
3767             (vars->line_speed == SPEED_1000)) {
3768                 u16 addr = MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2;
3769                 an_adv |= (1<<5);
3770
3771                 /* Enable CL37 1G Parallel Detect */
3772                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, addr, 0x1);
3773                 DP(NETIF_MSG_LINK, "Advertize 1G\n");
3774         }
3775         if (((vars->line_speed == SPEED_AUTO_NEG) &&
3776              (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
3777             (vars->line_speed ==  SPEED_10000)) {
3778                 /* Check adding advertisement for 10G KR */
3779                 an_adv |= (1<<7);
3780                 /* Enable 10G Parallel Detect */
3781                 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3782                                   MDIO_AER_BLOCK_AER_REG, 0);
3783
3784                 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3785                                  MDIO_WC_REG_PAR_DET_10G_CTRL, 1);
3786                 bnx2x_set_aer_mmd(params, phy);
3787                 DP(NETIF_MSG_LINK, "Advertize 10G\n");
3788         }
3789
3790         /* Set Transmit PMD settings */
3791         lane = bnx2x_get_warpcore_lane(phy, params);
3792         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3793                          MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
3794                          WC_TX_DRIVER(0x02, 0x06, 0x09, 0));
3795         /* Configure the next lane if dual mode */
3796         if (phy->flags & FLAGS_WC_DUAL_MODE)
3797                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3798                                  MDIO_WC_REG_TX0_TX_DRIVER + 0x10*(lane+1),
3799                                  WC_TX_DRIVER(0x02, 0x06, 0x09, 0));
3800         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3801                          MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL,
3802                          0x03f0);
3803         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3804                          MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL,
3805                          0x03f0);
3806
3807         /* Advertised speeds */
3808         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3809                          MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, an_adv);
3810
3811         /* Advertised and set FEC (Forward Error Correction) */
3812         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3813                          MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2,
3814                          (MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY |
3815                           MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ));
3816
3817         /* Enable CL37 BAM */
3818         if (REG_RD(bp, params->shmem_base +
3819                    offsetof(struct shmem_region, dev_info.
3820                             port_hw_config[params->port].default_cfg)) &
3821             PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
3822                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3823                                          MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL,
3824                                          1);
3825                 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
3826         }
3827
3828         /* Advertise pause */
3829         bnx2x_ext_phy_set_pause(params, phy, vars);
3830         vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
3831         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3832                                  MDIO_WC_REG_DIGITAL5_MISC7, 0x100);
3833
3834         /* Over 1G - AN local device user page 1 */
3835         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3836                         MDIO_WC_REG_DIGITAL3_UP1, 0x1f);
3837
3838         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
3839              (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) ||
3840             (phy->req_line_speed == SPEED_20000)) {
3841
3842                 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3843                                   MDIO_AER_BLOCK_AER_REG, lane);
3844
3845                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3846                                          MDIO_WC_REG_RX1_PCI_CTRL + (0x10*lane),
3847                                          (1<<11));
3848
3849                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3850                                  MDIO_WC_REG_XGXS_X2_CONTROL3, 0x7);
3851                 bnx2x_set_aer_mmd(params, phy);
3852
3853                 bnx2x_warpcore_enable_AN_KR2(phy, params, vars);
3854         } else {
3855                 /* Enable Auto-Detect to support 1G over CL37 as well */
3856                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3857                                  MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0x10);
3858                 wc_lane_config = REG_RD(bp, params->shmem_base +
3859                                         offsetof(struct shmem_region, dev_info.
3860                                         shared_hw_config.wc_lane_config));
3861                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3862                                 MDIO_WC_REG_RX0_PCI_CTRL + (lane << 4), &val);
3863                 /* Force cl48 sync_status LOW to avoid getting stuck in CL73
3864                  * parallel-detect loop when CL73 and CL37 are enabled.
3865                  */
3866                 val |= 1 << 11;
3867
3868                 /* Restore Polarity settings in case it was run over by
3869                  * previous link owner
3870                  */
3871                 if (wc_lane_config &
3872                     (SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED << lane))
3873                         val |= 3 << 2;
3874                 else
3875                         val &= ~(3 << 2);
3876                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3877                                  MDIO_WC_REG_RX0_PCI_CTRL + (lane << 4),
3878                                  val);
3879
3880                 bnx2x_disable_kr2(params, vars, phy);
3881         }
3882
3883         /* Enable Autoneg: only on the main lane */
3884         bnx2x_warpcore_restart_AN_KR(phy, params);
3885 }
3886
3887 static void bnx2x_warpcore_set_10G_KR(struct bnx2x_phy *phy,
3888                                       struct link_params *params,
3889                                       struct link_vars *vars)
3890 {
3891         struct bnx2x *bp = params->bp;
3892         u16 val16, i, lane;
3893         static struct bnx2x_reg_set reg_set[] = {
3894                 /* Disable Autoneg */
3895                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
3896                 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3897                         0x3f00},
3898                 {MDIO_AN_DEVAD, MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0},
3899                 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0},
3900                 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL3_UP1, 0x1},
3901                 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL5_MISC7, 0xa},
3902                 /* Leave cl72 training enable, needed for KR */
3903                 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2}
3904         };
3905
3906         for (i = 0; i < ARRAY_SIZE(reg_set); i++)
3907                 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
3908                                  reg_set[i].val);
3909
3910         lane = bnx2x_get_warpcore_lane(phy, params);
3911         /* Global registers */
3912         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
3913                           MDIO_AER_BLOCK_AER_REG, 0);
3914         /* Disable CL36 PCS Tx */
3915         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3916                         MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16);
3917         val16 &= ~(0x0011 << lane);
3918         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3919                          MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16);
3920
3921         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3922                         MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16);
3923         val16 |= (0x0303 << (lane << 1));
3924         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3925                          MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16);
3926         /* Restore AER */
3927         bnx2x_set_aer_mmd(params, phy);
3928         /* Set speed via PMA/PMD register */
3929         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3930                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);
3931
3932         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD,
3933                          MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB);
3934
3935         /* Enable encoded forced speed */
3936         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3937                          MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30);
3938
3939         /* Turn TX scramble payload only the 64/66 scrambler */
3940         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3941                          MDIO_WC_REG_TX66_CONTROL, 0x9);
3942
3943         /* Turn RX scramble payload only the 64/66 scrambler */
3944         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3945                                  MDIO_WC_REG_RX66_CONTROL, 0xF9);
3946
3947         /* Set and clear loopback to cause a reset to 64/66 decoder */
3948         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3949                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000);
3950         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3951                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);
3952
3953 }
3954
3955 static void bnx2x_warpcore_set_10G_XFI(struct bnx2x_phy *phy,
3956                                        struct link_params *params,
3957                                        u8 is_xfi)
3958 {
3959         struct bnx2x *bp = params->bp;
3960         u16 misc1_val, tap_val, tx_driver_val, lane, val;
3961         u32 cfg_tap_val, tx_drv_brdct, tx_equal;
3962         u32 ifir_val, ipost2_val, ipre_driver_val;
3963
3964         /* Hold rxSeqStart */
3965         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3966                                  MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x8000);
3967
3968         /* Hold tx_fifo_reset */
3969         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3970                                  MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x1);
3971
3972         /* Disable CL73 AN */
3973         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
3974
3975         /* Disable 100FX Enable and Auto-Detect */
3976         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
3977                                   MDIO_WC_REG_FX100_CTRL1, 0xFFFA);
3978
3979         /* Disable 100FX Idle detect */
3980         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
3981                                  MDIO_WC_REG_FX100_CTRL3, 0x0080);
3982
3983         /* Set Block address to Remote PHY & Clear forced_speed[5] */
3984         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
3985                                   MDIO_WC_REG_DIGITAL4_MISC3, 0xFF7F);
3986
3987         /* Turn off auto-detect & fiber mode */
3988         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
3989                                   MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
3990                                   0xFFEE);
3991
3992         /* Set filter_force_link, disable_false_link and parallel_detect */
3993         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3994                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val);
3995         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3996                          MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
3997                          ((val | 0x0006) & 0xFFFE));
3998
3999         /* Set XFI / SFI */
4000         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4001                         MDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val);
4002
4003         misc1_val &= ~(0x1f);
4004
4005         if (is_xfi) {
4006                 misc1_val |= 0x5;
4007                 tap_val = WC_TX_FIR(0x08, 0x37, 0x00);
4008                 tx_driver_val = WC_TX_DRIVER(0x00, 0x02, 0x03, 0);
4009         } else {
4010                 cfg_tap_val = REG_RD(bp, params->shmem_base +
4011                                      offsetof(struct shmem_region, dev_info.
4012                                               port_hw_config[params->port].
4013                                               sfi_tap_values));
4014
4015                 tx_equal = cfg_tap_val & PORT_HW_CFG_TX_EQUALIZATION_MASK;
4016
4017                 misc1_val |= 0x9;
4018
4019                 /* TAP values are controlled by nvram, if value there isn't 0 */
4020                 if (tx_equal)
4021                         tap_val = (u16)tx_equal;
4022                 else
4023                         tap_val = WC_TX_FIR(0x0f, 0x2b, 0x02);
4024
4025                 ifir_val = DEFAULT_TX_DRV_IFIR;
4026                 ipost2_val = DEFAULT_TX_DRV_POST2;
4027                 ipre_driver_val = DEFAULT_TX_DRV_IPRE_DRIVER;
4028                 tx_drv_brdct = DEFAULT_TX_DRV_BRDCT;
4029
4030                 /* If any of the IFIR/IPRE_DRIVER/POST@ is set, apply all
4031                  * configuration.
4032                  */
4033                 if (cfg_tap_val & (PORT_HW_CFG_TX_DRV_IFIR_MASK |
4034                                    PORT_HW_CFG_TX_DRV_IPREDRIVER_MASK |
4035                                    PORT_HW_CFG_TX_DRV_POST2_MASK)) {
4036                         ifir_val = (cfg_tap_val &
4037                                     PORT_HW_CFG_TX_DRV_IFIR_MASK) >>
4038                                 PORT_HW_CFG_TX_DRV_IFIR_SHIFT;
4039                         ipre_driver_val = (cfg_tap_val &
4040                                            PORT_HW_CFG_TX_DRV_IPREDRIVER_MASK)
4041                         >> PORT_HW_CFG_TX_DRV_IPREDRIVER_SHIFT;
4042                         ipost2_val = (cfg_tap_val &
4043                                       PORT_HW_CFG_TX_DRV_POST2_MASK) >>
4044                                 PORT_HW_CFG_TX_DRV_POST2_SHIFT;
4045                 }
4046
4047                 if (cfg_tap_val & PORT_HW_CFG_TX_DRV_BROADCAST_MASK) {
4048                         tx_drv_brdct = (cfg_tap_val &
4049                                         PORT_HW_CFG_TX_DRV_BROADCAST_MASK) >>
4050                                 PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT;
4051                 }
4052
4053                 tx_driver_val = WC_TX_DRIVER(ipost2_val, tx_drv_brdct,
4054                                              ipre_driver_val, ifir_val);
4055         }
4056         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4057                          MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val);
4058
4059         /* Set Transmit PMD settings */
4060         lane = bnx2x_get_warpcore_lane(phy, params);
4061         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4062                          MDIO_WC_REG_TX_FIR_TAP,
4063                          tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE);
4064         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4065                          MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
4066                          tx_driver_val);
4067
4068         /* Enable fiber mode, enable and invert sig_det */
4069         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4070                                  MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0xd);
4071
4072         /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */
4073         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4074                                  MDIO_WC_REG_DIGITAL4_MISC3, 0x8080);
4075
4076         bnx2x_warpcore_set_lpi_passthrough(phy, params);
4077
4078         /* 10G XFI Full Duplex */
4079         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4080                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100);
4081
4082         /* Release tx_fifo_reset */
4083         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4084                                   MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3,
4085                                   0xFFFE);
4086         /* Release rxSeqStart */
4087         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4088                                   MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x7FFF);
4089 }
4090
4091 static void bnx2x_warpcore_set_20G_force_KR2(struct bnx2x_phy *phy,
4092                                              struct link_params *params)
4093 {
4094         u16 val;
4095         struct bnx2x *bp = params->bp;
4096         /* Set global registers, so set AER lane to 0 */
4097         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4098                           MDIO_AER_BLOCK_AER_REG, 0);
4099
4100         /* Disable sequencer */
4101         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4102                                   MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, ~(1<<13));
4103
4104         bnx2x_set_aer_mmd(params, phy);
4105
4106         bnx2x_cl45_read_and_write(bp, phy, MDIO_PMA_DEVAD,
4107                                   MDIO_WC_REG_PMD_KR_CONTROL, ~(1<<1));
4108         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
4109                          MDIO_AN_REG_CTRL, 0);
4110         /* Turn off CL73 */
4111         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4112                         MDIO_WC_REG_CL73_USERB0_CTRL, &val);
4113         val &= ~(1<<5);
4114         val |= (1<<6);
4115         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4116                          MDIO_WC_REG_CL73_USERB0_CTRL, val);
4117
4118         /* Set 20G KR2 force speed */
4119         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4120                                  MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x1f);
4121
4122         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4123                                  MDIO_WC_REG_DIGITAL4_MISC3, (1<<7));
4124
4125         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4126                         MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &val);
4127         val &= ~(3<<14);
4128         val |= (1<<15);
4129         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4130                          MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, val);
4131         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4132                          MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0x835A);
4133
4134         /* Enable sequencer (over lane 0) */
4135         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4136                           MDIO_AER_BLOCK_AER_REG, 0);
4137
4138         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4139                                  MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, (1<<13));
4140
4141         bnx2x_set_aer_mmd(params, phy);
4142 }
4143
4144 static void bnx2x_warpcore_set_20G_DXGXS(struct bnx2x *bp,
4145                                          struct bnx2x_phy *phy,
4146                                          u16 lane)
4147 {
4148         /* Rx0 anaRxControl1G */
4149         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4150                          MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90);
4151
4152         /* Rx2 anaRxControl1G */
4153         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4154                          MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90);
4155
4156         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4157                          MDIO_WC_REG_RX66_SCW0, 0xE070);
4158
4159         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4160                          MDIO_WC_REG_RX66_SCW1, 0xC0D0);
4161
4162         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4163                          MDIO_WC_REG_RX66_SCW2, 0xA0B0);
4164
4165         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4166                          MDIO_WC_REG_RX66_SCW3, 0x8090);
4167
4168         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4169                          MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0);
4170
4171         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4172                          MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0);
4173
4174         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4175                          MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0);
4176
4177         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4178                          MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0);
4179
4180         /* Serdes Digital Misc1 */
4181         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4182                          MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008);
4183
4184         /* Serdes Digital4 Misc3 */
4185         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4186                          MDIO_WC_REG_DIGITAL4_MISC3, 0x8088);
4187
4188         /* Set Transmit PMD settings */
4189         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4190                          MDIO_WC_REG_TX_FIR_TAP,
4191                          (WC_TX_FIR(0x12, 0x2d, 0x00) |
4192                           MDIO_WC_REG_TX_FIR_TAP_ENABLE));
4193         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4194                          MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
4195                          WC_TX_DRIVER(0x02, 0x02, 0x02, 0));
4196 }
4197
4198 static void bnx2x_warpcore_set_sgmii_speed(struct bnx2x_phy *phy,
4199                                            struct link_params *params,
4200                                            u8 fiber_mode,
4201                                            u8 always_autoneg)
4202 {
4203         struct bnx2x *bp = params->bp;
4204         u16 val16, digctrl_kx1, digctrl_kx2;
4205
4206         /* Clear XFI clock comp in non-10G single lane mode. */
4207         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4208                                   MDIO_WC_REG_RX66_CONTROL, ~(3<<13));
4209
4210         bnx2x_warpcore_set_lpi_passthrough(phy, params);
4211
4212         if (always_autoneg || phy->req_line_speed == SPEED_AUTO_NEG) {
4213                 /* SGMII Autoneg */
4214                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4215                                          MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
4216                                          0x1000);
4217                 DP(NETIF_MSG_LINK, "set SGMII AUTONEG\n");
4218         } else {
4219                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4220                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4221                 val16 &= 0xcebf;
4222                 switch (phy->req_line_speed) {
4223                 case SPEED_10:
4224                         break;
4225                 case SPEED_100:
4226                         val16 |= 0x2000;
4227                         break;
4228                 case SPEED_1000:
4229                         val16 |= 0x0040;
4230                         break;
4231                 default:
4232                         DP(NETIF_MSG_LINK,
4233                            "Speed not supported: 0x%x\n", phy->req_line_speed);
4234                         return;
4235                 }
4236
4237                 if (phy->req_duplex == DUPLEX_FULL)
4238                         val16 |= 0x0100;
4239
4240                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4241                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16);
4242
4243                 DP(NETIF_MSG_LINK, "set SGMII force speed %d\n",
4244                                phy->req_line_speed);
4245                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4246                                 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4247                 DP(NETIF_MSG_LINK, "  (readback) %x\n", val16);
4248         }
4249
4250         /* SGMII Slave mode and disable signal detect */
4251         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4252                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1);
4253         if (fiber_mode)
4254                 digctrl_kx1 = 1;
4255         else
4256                 digctrl_kx1 &= 0xff4a;
4257
4258         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4259                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4260                         digctrl_kx1);
4261
4262         /* Turn off parallel detect */
4263         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4264                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2);
4265         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4266                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4267                         (digctrl_kx2 & ~(1<<2)));
4268
4269         /* Re-enable parallel detect */
4270         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4271                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4272                         (digctrl_kx2 | (1<<2)));
4273
4274         /* Enable autodet */
4275         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4276                         MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4277                         (digctrl_kx1 | 0x10));
4278 }
4279
4280 static void bnx2x_warpcore_reset_lane(struct bnx2x *bp,
4281                                       struct bnx2x_phy *phy,
4282                                       u8 reset)
4283 {
4284         u16 val;
4285         /* Take lane out of reset after configuration is finished */
4286         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4287                         MDIO_WC_REG_DIGITAL5_MISC6, &val);
4288         if (reset)
4289                 val |= 0xC000;
4290         else
4291                 val &= 0x3FFF;
4292         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4293                          MDIO_WC_REG_DIGITAL5_MISC6, val);
4294         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4295                          MDIO_WC_REG_DIGITAL5_MISC6, &val);
4296 }
4297 /* Clear SFI/XFI link settings registers */
4298 static void bnx2x_warpcore_clear_regs(struct bnx2x_phy *phy,
4299                                       struct link_params *params,
4300                                       u16 lane)
4301 {
4302         struct bnx2x *bp = params->bp;
4303         u16 i;
4304         static struct bnx2x_reg_set wc_regs[] = {
4305                 {MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0},
4306                 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL1, 0x014a},
4307                 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL3, 0x0800},
4308                 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL4_MISC3, 0x8008},
4309                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4310                         0x0195},
4311                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4312                         0x0007},
4313                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3,
4314                         0x0002},
4315                 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000},
4316                 {MDIO_WC_DEVAD, MDIO_WC_REG_TX_FIR_TAP, 0x0000},
4317                 {MDIO_WC_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040},
4318                 {MDIO_WC_DEVAD, MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140}
4319         };
4320         /* Set XFI clock comp as default. */
4321         bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4322                                  MDIO_WC_REG_RX66_CONTROL, (3<<13));
4323
4324         for (i = 0; i < ARRAY_SIZE(wc_regs); i++)
4325                 bnx2x_cl45_write(bp, phy, wc_regs[i].devad, wc_regs[i].reg,
4326                                  wc_regs[i].val);
4327
4328         lane = bnx2x_get_warpcore_lane(phy, params);
4329         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4330                          MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990);
4331
4332 }
4333
4334 static int bnx2x_get_mod_abs_int_cfg(struct bnx2x *bp,
4335                                                 u32 chip_id,
4336                                                 u32 shmem_base, u8 port,
4337                                                 u8 *gpio_num, u8 *gpio_port)
4338 {
4339         u32 cfg_pin;
4340         *gpio_num = 0;
4341         *gpio_port = 0;
4342         if (CHIP_IS_E3(bp)) {
4343                 cfg_pin = (REG_RD(bp, shmem_base +
4344                                 offsetof(struct shmem_region,
4345                                 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4346                                 PORT_HW_CFG_E3_MOD_ABS_MASK) >>
4347                                 PORT_HW_CFG_E3_MOD_ABS_SHIFT;
4348
4349                 /* Should not happen. This function called upon interrupt
4350                  * triggered by GPIO ( since EPIO can only generate interrupts
4351                  * to MCP).
4352                  * So if this function was called and none of the GPIOs was set,
4353                  * it means the shit hit the fan.
4354                  */
4355                 if ((cfg_pin < PIN_CFG_GPIO0_P0) ||
4356                     (cfg_pin > PIN_CFG_GPIO3_P1)) {
4357                         DP(NETIF_MSG_LINK,
4358                            "No cfg pin %x for module detect indication\n",
4359                            cfg_pin);
4360                         return -EINVAL;
4361                 }
4362
4363                 *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3;
4364                 *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2;
4365         } else {
4366                 *gpio_num = MISC_REGISTERS_GPIO_3;
4367                 *gpio_port = port;
4368         }
4369
4370         return 0;
4371 }
4372
4373 static int bnx2x_is_sfp_module_plugged(struct bnx2x_phy *phy,
4374                                        struct link_params *params)
4375 {
4376         struct bnx2x *bp = params->bp;
4377         u8 gpio_num, gpio_port;
4378         u32 gpio_val;
4379         if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id,
4380                                       params->shmem_base, params->port,
4381                                       &gpio_num, &gpio_port) != 0)
4382                 return 0;
4383         gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
4384
4385         /* Call the handling function in case module is detected */
4386         if (gpio_val == 0)
4387                 return 1;
4388         else
4389                 return 0;
4390 }
4391 static int bnx2x_warpcore_get_sigdet(struct bnx2x_phy *phy,
4392                                      struct link_params *params)
4393 {
4394         u16 gp2_status_reg0, lane;
4395         struct bnx2x *bp = params->bp;
4396
4397         lane = bnx2x_get_warpcore_lane(phy, params);
4398
4399         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0,
4400                                  &gp2_status_reg0);
4401
4402         return (gp2_status_reg0 >> (8+lane)) & 0x1;
4403 }
4404
4405 static void bnx2x_warpcore_config_runtime(struct bnx2x_phy *phy,
4406                                           struct link_params *params,
4407                                           struct link_vars *vars)
4408 {
4409         struct bnx2x *bp = params->bp;
4410         u32 serdes_net_if;
4411         u16 gp_status1 = 0, lnkup = 0, lnkup_kr = 0;
4412
4413         vars->turn_to_run_wc_rt = vars->turn_to_run_wc_rt ? 0 : 1;
4414
4415         if (!vars->turn_to_run_wc_rt)
4416                 return;
4417
4418         if (vars->rx_tx_asic_rst) {
4419                 u16 lane = bnx2x_get_warpcore_lane(phy, params);
4420                 serdes_net_if = (REG_RD(bp, params->shmem_base +
4421                                 offsetof(struct shmem_region, dev_info.
4422                                 port_hw_config[params->port].default_cfg)) &
4423                                 PORT_HW_CFG_NET_SERDES_IF_MASK);
4424
4425                 switch (serdes_net_if) {
4426                 case PORT_HW_CFG_NET_SERDES_IF_KR:
4427                         /* Do we get link yet? */
4428                         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 0x81d1,
4429                                         &gp_status1);
4430                         lnkup = (gp_status1 >> (8+lane)) & 0x1;/* 1G */
4431                                 /*10G KR*/
4432                         lnkup_kr = (gp_status1 >> (12+lane)) & 0x1;
4433
4434                         if (lnkup_kr || lnkup) {
4435                                 vars->rx_tx_asic_rst = 0;
4436                         } else {
4437                                 /* Reset the lane to see if link comes up.*/
4438                                 bnx2x_warpcore_reset_lane(bp, phy, 1);
4439                                 bnx2x_warpcore_reset_lane(bp, phy, 0);
4440
4441                                 /* Restart Autoneg */
4442                                 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
4443                                         MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
4444
4445                                 vars->rx_tx_asic_rst--;
4446                                 DP(NETIF_MSG_LINK, "0x%x retry left\n",
4447                                 vars->rx_tx_asic_rst);
4448                         }
4449                         break;
4450
4451                 default:
4452                         break;
4453                 }
4454
4455         } /*params->rx_tx_asic_rst*/
4456
4457 }
4458 static void bnx2x_warpcore_config_sfi(struct bnx2x_phy *phy,
4459                                       struct link_params *params)
4460 {
4461         u16 lane = bnx2x_get_warpcore_lane(phy, params);
4462         struct bnx2x *bp = params->bp;
4463         bnx2x_warpcore_clear_regs(phy, params, lane);
4464         if ((params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)] ==
4465              SPEED_10000) &&
4466             (phy->media_type != ETH_PHY_SFP_1G_FIBER)) {
4467                 DP(NETIF_MSG_LINK, "Setting 10G SFI\n");
4468                 bnx2x_warpcore_set_10G_XFI(phy, params, 0);
4469         } else {
4470                 DP(NETIF_MSG_LINK, "Setting 1G Fiber\n");
4471                 bnx2x_warpcore_set_sgmii_speed(phy, params, 1, 0);
4472         }
4473 }
4474
4475 static void bnx2x_sfp_e3_set_transmitter(struct link_params *params,
4476                                          struct bnx2x_phy *phy,
4477                                          u8 tx_en)
4478 {
4479         struct bnx2x *bp = params->bp;
4480         u32 cfg_pin;
4481         u8 port = params->port;
4482
4483         cfg_pin = REG_RD(bp, params->shmem_base +
4484                          offsetof(struct shmem_region,
4485                                   dev_info.port_hw_config[port].e3_sfp_ctrl)) &
4486                 PORT_HW_CFG_E3_TX_LASER_MASK;
4487         /* Set the !tx_en since this pin is DISABLE_TX_LASER */
4488         DP(NETIF_MSG_LINK, "Setting WC TX to %d\n", tx_en);
4489
4490         /* For 20G, the expected pin to be used is 3 pins after the current */
4491         bnx2x_set_cfg_pin(bp, cfg_pin, tx_en ^ 1);
4492         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
4493                 bnx2x_set_cfg_pin(bp, cfg_pin + 3, tx_en ^ 1);
4494 }
4495
4496 static void bnx2x_warpcore_config_init(struct bnx2x_phy *phy,
4497                                        struct link_params *params,
4498                                        struct link_vars *vars)
4499 {
4500         struct bnx2x *bp = params->bp;
4501         u32 serdes_net_if;
4502         u8 fiber_mode;
4503         u16 lane = bnx2x_get_warpcore_lane(phy, params);
4504         serdes_net_if = (REG_RD(bp, params->shmem_base +
4505                          offsetof(struct shmem_region, dev_info.
4506                                   port_hw_config[params->port].default_cfg)) &
4507                          PORT_HW_CFG_NET_SERDES_IF_MASK);
4508         DP(NETIF_MSG_LINK, "Begin Warpcore init, link_speed %d, "
4509                            "serdes_net_if = 0x%x\n",
4510                        vars->line_speed, serdes_net_if);
4511         bnx2x_set_aer_mmd(params, phy);
4512         bnx2x_warpcore_reset_lane(bp, phy, 1);
4513         vars->phy_flags |= PHY_XGXS_FLAG;
4514         if ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) ||
4515             (phy->req_line_speed &&
4516              ((phy->req_line_speed == SPEED_100) ||
4517               (phy->req_line_speed == SPEED_10)))) {
4518                 vars->phy_flags |= PHY_SGMII_FLAG;
4519                 DP(NETIF_MSG_LINK, "Setting SGMII mode\n");
4520                 bnx2x_warpcore_clear_regs(phy, params, lane);
4521                 bnx2x_warpcore_set_sgmii_speed(phy, params, 0, 1);
4522         } else {
4523                 switch (serdes_net_if) {
4524                 case PORT_HW_CFG_NET_SERDES_IF_KR:
4525                         /* Enable KR Auto Neg */
4526                         if (params->loopback_mode != LOOPBACK_EXT)
4527                                 bnx2x_warpcore_enable_AN_KR(phy, params, vars);
4528                         else {
4529                                 DP(NETIF_MSG_LINK, "Setting KR 10G-Force\n");
4530                                 bnx2x_warpcore_set_10G_KR(phy, params, vars);
4531                         }
4532                         break;
4533
4534                 case PORT_HW_CFG_NET_SERDES_IF_XFI:
4535                         bnx2x_warpcore_clear_regs(phy, params, lane);
4536                         if (vars->line_speed == SPEED_10000) {
4537                                 DP(NETIF_MSG_LINK, "Setting 10G XFI\n");
4538                                 bnx2x_warpcore_set_10G_XFI(phy, params, 1);
4539                         } else {
4540                                 if (SINGLE_MEDIA_DIRECT(params)) {
4541                                         DP(NETIF_MSG_LINK, "1G Fiber\n");
4542                                         fiber_mode = 1;
4543                                 } else {
4544                                         DP(NETIF_MSG_LINK, "10/100/1G SGMII\n");
4545                                         fiber_mode = 0;
4546                                 }
4547                                 bnx2x_warpcore_set_sgmii_speed(phy,
4548                                                                 params,
4549                                                                 fiber_mode,
4550                                                                 0);
4551                         }
4552
4553                         break;
4554
4555                 case PORT_HW_CFG_NET_SERDES_IF_SFI:
4556                         /* Issue Module detection if module is plugged, or
4557                          * enabled transmitter to avoid current leakage in case
4558                          * no module is connected
4559                          */
4560                         if ((params->loopback_mode == LOOPBACK_NONE) ||
4561                             (params->loopback_mode == LOOPBACK_EXT)) {
4562                                 if (bnx2x_is_sfp_module_plugged(phy, params))
4563                                         bnx2x_sfp_module_detection(phy, params);
4564                                 else
4565                                         bnx2x_sfp_e3_set_transmitter(params,
4566                                                                      phy, 1);
4567                         }
4568
4569                         bnx2x_warpcore_config_sfi(phy, params);
4570                         break;
4571
4572                 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
4573                         if (vars->line_speed != SPEED_20000) {
4574                                 DP(NETIF_MSG_LINK, "Speed not supported yet\n");
4575                                 return;
4576                         }
4577                         DP(NETIF_MSG_LINK, "Setting 20G DXGXS\n");
4578                         bnx2x_warpcore_set_20G_DXGXS(bp, phy, lane);
4579                         /* Issue Module detection */
4580
4581                         bnx2x_sfp_module_detection(phy, params);
4582                         break;
4583                 case PORT_HW_CFG_NET_SERDES_IF_KR2:
4584                         if (!params->loopback_mode) {
4585                                 bnx2x_warpcore_enable_AN_KR(phy, params, vars);
4586                         } else {
4587                                 DP(NETIF_MSG_LINK, "Setting KR 20G-Force\n");
4588                                 bnx2x_warpcore_set_20G_force_KR2(phy, params);
4589                         }
4590                         break;
4591                 default:
4592                         DP(NETIF_MSG_LINK,
4593                            "Unsupported Serdes Net Interface 0x%x\n",
4594                            serdes_net_if);
4595                         return;
4596                 }
4597         }
4598
4599         /* Take lane out of reset after configuration is finished */
4600         bnx2x_warpcore_reset_lane(bp, phy, 0);
4601         DP(NETIF_MSG_LINK, "Exit config init\n");
4602 }
4603
4604 static void bnx2x_warpcore_link_reset(struct bnx2x_phy *phy,
4605                                       struct link_params *params)
4606 {
4607         struct bnx2x *bp = params->bp;
4608         u16 val16, lane;
4609         bnx2x_sfp_e3_set_transmitter(params, phy, 0);
4610         bnx2x_set_mdio_emac_per_phy(bp, params);
4611         bnx2x_set_aer_mmd(params, phy);
4612         /* Global register */
4613         bnx2x_warpcore_reset_lane(bp, phy, 1);
4614
4615         /* Clear loopback settings (if any) */
4616         /* 10G & 20G */
4617         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4618                                   MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0xBFFF);
4619
4620         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4621                                   MDIO_WC_REG_IEEE0BLK_MIICNTL, 0xfffe);
4622
4623         /* Update those 1-copy registers */
4624         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4625                           MDIO_AER_BLOCK_AER_REG, 0);
4626         /* Enable 1G MDIO (1-copy) */
4627         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4628                                   MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4629                                   ~0x10);
4630
4631         bnx2x_cl45_read_and_write(bp, phy, MDIO_WC_DEVAD,
4632                                   MDIO_WC_REG_XGXSBLK1_LANECTRL2, 0xff00);
4633         lane = bnx2x_get_warpcore_lane(phy, params);
4634         /* Disable CL36 PCS Tx */
4635         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4636                         MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16);
4637         val16 |= (0x11 << lane);
4638         if (phy->flags & FLAGS_WC_DUAL_MODE)
4639                 val16 |= (0x22 << lane);
4640         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4641                          MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16);
4642
4643         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4644                         MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16);
4645         val16 &= ~(0x0303 << (lane << 1));
4646         val16 |= (0x0101 << (lane << 1));
4647         if (phy->flags & FLAGS_WC_DUAL_MODE) {
4648                 val16 &= ~(0x0c0c << (lane << 1));
4649                 val16 |= (0x0404 << (lane << 1));
4650         }
4651
4652         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4653                          MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16);
4654         /* Restore AER */
4655         bnx2x_set_aer_mmd(params, phy);
4656
4657 }
4658
4659 static void bnx2x_set_warpcore_loopback(struct bnx2x_phy *phy,
4660                                         struct link_params *params)
4661 {
4662         struct bnx2x *bp = params->bp;
4663         u16 val16;
4664         u32 lane;
4665         DP(NETIF_MSG_LINK, "Setting Warpcore loopback type %x, speed %d\n",
4666                        params->loopback_mode, phy->req_line_speed);
4667
4668         if (phy->req_line_speed < SPEED_10000 ||
4669             phy->supported & SUPPORTED_20000baseKR2_Full) {
4670                 /* 10/100/1000/20G-KR2 */
4671
4672                 /* Update those 1-copy registers */
4673                 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
4674                                   MDIO_AER_BLOCK_AER_REG, 0);
4675                 /* Enable 1G MDIO (1-copy) */
4676                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4677                                          MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
4678                                          0x10);
4679                 /* Set 1G loopback based on lane (1-copy) */
4680                 lane = bnx2x_get_warpcore_lane(phy, params);
4681                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
4682                                 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
4683                 val16 |= (1<<lane);
4684                 if (phy->flags & FLAGS_WC_DUAL_MODE)
4685                         val16 |= (2<<lane);
4686                 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
4687                                  MDIO_WC_REG_XGXSBLK1_LANECTRL2,
4688                                  val16);
4689
4690                 /* Switch back to 4-copy registers */
4691                 bnx2x_set_aer_mmd(params, phy);
4692         } else {
4693                 /* 10G / 20G-DXGXS */
4694                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4695                                          MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
4696                                          0x4000);
4697                 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD,
4698                                          MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1);
4699         }
4700 }
4701
4702
4703
4704 static void bnx2x_sync_link(struct link_params *params,
4705                              struct link_vars *vars)
4706 {
4707         struct bnx2x *bp = params->bp;
4708         u8 link_10g_plus;
4709         if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4710                 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
4711         vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
4712         if (vars->link_up) {
4713                 DP(NETIF_MSG_LINK, "phy link up\n");
4714
4715                 vars->phy_link_up = 1;
4716                 vars->duplex = DUPLEX_FULL;
4717                 switch (vars->link_status &
4718                         LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
4719                 case LINK_10THD:
4720                         vars->duplex = DUPLEX_HALF;
4721                         /* Fall thru */
4722                 case LINK_10TFD:
4723                         vars->line_speed = SPEED_10;
4724                         break;
4725
4726                 case LINK_100TXHD:
4727                         vars->duplex = DUPLEX_HALF;
4728                         /* Fall thru */
4729                 case LINK_100T4:
4730                 case LINK_100TXFD:
4731                         vars->line_speed = SPEED_100;
4732                         break;
4733
4734                 case LINK_1000THD:
4735                         vars->duplex = DUPLEX_HALF;
4736                         /* Fall thru */
4737                 case LINK_1000TFD:
4738                         vars->line_speed = SPEED_1000;
4739                         break;
4740
4741                 case LINK_2500THD:
4742                         vars->duplex = DUPLEX_HALF;
4743                         /* Fall thru */
4744                 case LINK_2500TFD:
4745                         vars->line_speed = SPEED_2500;
4746                         break;
4747
4748                 case LINK_10GTFD:
4749                         vars->line_speed = SPEED_10000;
4750                         break;
4751                 case LINK_20GTFD:
4752                         vars->line_speed = SPEED_20000;
4753                         break;
4754                 default:
4755                         break;
4756                 }
4757                 vars->flow_ctrl = 0;
4758                 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
4759                         vars->flow_ctrl |= BNX2X_FLOW_CTRL_TX;
4760
4761                 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
4762                         vars->flow_ctrl |= BNX2X_FLOW_CTRL_RX;
4763
4764                 if (!vars->flow_ctrl)
4765                         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4766
4767                 if (vars->line_speed &&
4768                     ((vars->line_speed == SPEED_10) ||
4769                      (vars->line_speed == SPEED_100))) {
4770                         vars->phy_flags |= PHY_SGMII_FLAG;
4771                 } else {
4772                         vars->phy_flags &= ~PHY_SGMII_FLAG;
4773                 }
4774                 if (vars->line_speed &&
4775                     USES_WARPCORE(bp) &&
4776                     (vars->line_speed == SPEED_1000))
4777                         vars->phy_flags |= PHY_SGMII_FLAG;
4778                 /* Anything 10 and over uses the bmac */
4779                 link_10g_plus = (vars->line_speed >= SPEED_10000);
4780
4781                 if (link_10g_plus) {
4782                         if (USES_WARPCORE(bp))
4783                                 vars->mac_type = MAC_TYPE_XMAC;
4784                         else
4785                                 vars->mac_type = MAC_TYPE_BMAC;
4786                 } else {
4787                         if (USES_WARPCORE(bp))
4788                                 vars->mac_type = MAC_TYPE_UMAC;
4789                         else
4790                                 vars->mac_type = MAC_TYPE_EMAC;
4791                 }
4792         } else { /* Link down */
4793                 DP(NETIF_MSG_LINK, "phy link down\n");
4794
4795                 vars->phy_link_up = 0;
4796
4797                 vars->line_speed = 0;
4798                 vars->duplex = DUPLEX_FULL;
4799                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
4800
4801                 /* Indicate no mac active */
4802                 vars->mac_type = MAC_TYPE_NONE;
4803                 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
4804                         vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
4805                 if (vars->link_status & LINK_STATUS_SFP_TX_FAULT)
4806                         vars->phy_flags |= PHY_SFP_TX_FAULT_FLAG;
4807         }
4808 }
4809
4810 void bnx2x_link_status_update(struct link_params *params,
4811                               struct link_vars *vars)
4812 {
4813         struct bnx2x *bp = params->bp;
4814         u8 port = params->port;
4815         u32 sync_offset, media_types;
4816         /* Update PHY configuration */
4817         set_phy_vars(params, vars);
4818
4819         vars->link_status = REG_RD(bp, params->shmem_base +
4820                                    offsetof(struct shmem_region,
4821                                             port_mb[port].link_status));
4822
4823         /* Force link UP in non LOOPBACK_EXT loopback mode(s) */
4824         if (params->loopback_mode != LOOPBACK_NONE &&
4825             params->loopback_mode != LOOPBACK_EXT)
4826                 vars->link_status |= LINK_STATUS_LINK_UP;
4827
4828         if (bnx2x_eee_has_cap(params))
4829                 vars->eee_status = REG_RD(bp, params->shmem2_base +
4830                                           offsetof(struct shmem2_region,
4831                                                    eee_status[params->port]));
4832
4833         vars->phy_flags = PHY_XGXS_FLAG;
4834         bnx2x_sync_link(params, vars);
4835         /* Sync media type */
4836         sync_offset = params->shmem_base +
4837                         offsetof(struct shmem_region,
4838                                  dev_info.port_hw_config[port].media_type);
4839         media_types = REG_RD(bp, sync_offset);
4840
4841         params->phy[INT_PHY].media_type =
4842                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >>
4843                 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT;
4844         params->phy[EXT_PHY1].media_type =
4845                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >>
4846                 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT;
4847         params->phy[EXT_PHY2].media_type =
4848                 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >>
4849                 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT;
4850         DP(NETIF_MSG_LINK, "media_types = 0x%x\n", media_types);
4851
4852         /* Sync AEU offset */
4853         sync_offset = params->shmem_base +
4854                         offsetof(struct shmem_region,
4855                                  dev_info.port_hw_config[port].aeu_int_mask);
4856
4857         vars->aeu_int_mask = REG_RD(bp, sync_offset);
4858
4859         /* Sync PFC status */
4860         if (vars->link_status & LINK_STATUS_PFC_ENABLED)
4861                 params->feature_config_flags |=
4862                                         FEATURE_CONFIG_PFC_ENABLED;
4863         else
4864                 params->feature_config_flags &=
4865                                         ~FEATURE_CONFIG_PFC_ENABLED;
4866
4867         if (SHMEM2_HAS(bp, link_attr_sync))
4868                 params->link_attr_sync = SHMEM2_RD(bp,
4869                                                  link_attr_sync[params->port]);
4870
4871         DP(NETIF_MSG_LINK, "link_status 0x%x  phy_link_up %x int_mask 0x%x\n",
4872                  vars->link_status, vars->phy_link_up, vars->aeu_int_mask);
4873         DP(NETIF_MSG_LINK, "line_speed %x  duplex %x  flow_ctrl 0x%x\n",
4874                  vars->line_speed, vars->duplex, vars->flow_ctrl);
4875 }
4876
4877 static void bnx2x_set_master_ln(struct link_params *params,
4878                                 struct bnx2x_phy *phy)
4879 {
4880         struct bnx2x *bp = params->bp;
4881         u16 new_master_ln, ser_lane;
4882         ser_lane = ((params->lane_config &
4883                      PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
4884                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
4885
4886         /* Set the master_ln for AN */
4887         CL22_RD_OVER_CL45(bp, phy,
4888                           MDIO_REG_BANK_XGXS_BLOCK2,
4889                           MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4890                           &new_master_ln);
4891
4892         CL22_WR_OVER_CL45(bp, phy,
4893                           MDIO_REG_BANK_XGXS_BLOCK2 ,
4894                           MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
4895                           (new_master_ln | ser_lane));
4896 }
4897
4898 static int bnx2x_reset_unicore(struct link_params *params,
4899                                struct bnx2x_phy *phy,
4900                                u8 set_serdes)
4901 {
4902         struct bnx2x *bp = params->bp;
4903         u16 mii_control;
4904         u16 i;
4905         CL22_RD_OVER_CL45(bp, phy,
4906                           MDIO_REG_BANK_COMBO_IEEE0,
4907                           MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
4908
4909         /* Reset the unicore */
4910         CL22_WR_OVER_CL45(bp, phy,
4911                           MDIO_REG_BANK_COMBO_IEEE0,
4912                           MDIO_COMBO_IEEE0_MII_CONTROL,
4913                           (mii_control |
4914                            MDIO_COMBO_IEEO_MII_CONTROL_RESET));
4915         if (set_serdes)
4916                 bnx2x_set_serdes_access(bp, params->port);
4917
4918         /* Wait for the reset to self clear */
4919         for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
4920                 udelay(5);
4921
4922                 /* The reset erased the previous bank value */
4923                 CL22_RD_OVER_CL45(bp, phy,
4924                                   MDIO_REG_BANK_COMBO_IEEE0,
4925                                   MDIO_COMBO_IEEE0_MII_CONTROL,
4926                                   &mii_control);
4927
4928                 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
4929                         udelay(5);
4930                         return 0;
4931                 }
4932         }
4933
4934         netdev_err(bp->dev,  "Warning: PHY was not initialized,"
4935                               " Port %d\n",
4936                          params->port);
4937         DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n");
4938         return -EINVAL;
4939
4940 }
4941
4942 static void bnx2x_set_swap_lanes(struct link_params *params,
4943                                  struct bnx2x_phy *phy)
4944 {
4945         struct bnx2x *bp = params->bp;
4946         /* Each two bits represents a lane number:
4947          * No swap is 0123 => 0x1b no need to enable the swap
4948          */
4949         u16 rx_lane_swap, tx_lane_swap;
4950
4951         rx_lane_swap = ((params->lane_config &
4952                          PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
4953                         PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
4954         tx_lane_swap = ((params->lane_config &
4955                          PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
4956                         PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
4957
4958         if (rx_lane_swap != 0x1b) {
4959                 CL22_WR_OVER_CL45(bp, phy,
4960                                   MDIO_REG_BANK_XGXS_BLOCK2,
4961                                   MDIO_XGXS_BLOCK2_RX_LN_SWAP,
4962                                   (rx_lane_swap |
4963                                    MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
4964                                    MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
4965         } else {
4966                 CL22_WR_OVER_CL45(bp, phy,
4967                                   MDIO_REG_BANK_XGXS_BLOCK2,
4968                                   MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
4969         }
4970
4971         if (tx_lane_swap != 0x1b) {
4972                 CL22_WR_OVER_CL45(bp, phy,
4973                                   MDIO_REG_BANK_XGXS_BLOCK2,
4974                                   MDIO_XGXS_BLOCK2_TX_LN_SWAP,
4975                                   (tx_lane_swap |
4976                                    MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
4977         } else {
4978                 CL22_WR_OVER_CL45(bp, phy,
4979                                   MDIO_REG_BANK_XGXS_BLOCK2,
4980                                   MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
4981         }
4982 }
4983
4984 static void bnx2x_set_parallel_detection(struct bnx2x_phy *phy,
4985                                          struct link_params *params)
4986 {
4987         struct bnx2x *bp = params->bp;
4988         u16 control2;
4989         CL22_RD_OVER_CL45(bp, phy,
4990                           MDIO_REG_BANK_SERDES_DIGITAL,
4991                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
4992                           &control2);
4993         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
4994                 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4995         else
4996                 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
4997         DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n",
4998                 phy->speed_cap_mask, control2);
4999         CL22_WR_OVER_CL45(bp, phy,
5000                           MDIO_REG_BANK_SERDES_DIGITAL,
5001                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
5002                           control2);
5003
5004         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
5005              (phy->speed_cap_mask &
5006                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
5007                 DP(NETIF_MSG_LINK, "XGXS\n");
5008
5009                 CL22_WR_OVER_CL45(bp, phy,
5010                                  MDIO_REG_BANK_10G_PARALLEL_DETECT,
5011                                  MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
5012                                  MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
5013
5014                 CL22_RD_OVER_CL45(bp, phy,
5015                                   MDIO_REG_BANK_10G_PARALLEL_DETECT,
5016                                   MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
5017                                   &control2);
5018
5019
5020                 control2 |=
5021                     MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
5022
5023                 CL22_WR_OVER_CL45(bp, phy,
5024                                   MDIO_REG_BANK_10G_PARALLEL_DETECT,
5025                                   MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
5026                                   control2);
5027
5028                 /* Disable parallel detection of HiG */
5029                 CL22_WR_OVER_CL45(bp, phy,
5030                                   MDIO_REG_BANK_XGXS_BLOCK2,
5031                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
5032                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
5033                                   MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
5034         }
5035 }
5036
5037 static void bnx2x_set_autoneg(struct bnx2x_phy *phy,
5038                               struct link_params *params,
5039                               struct link_vars *vars,
5040                               u8 enable_cl73)
5041 {
5042         struct bnx2x *bp = params->bp;
5043         u16 reg_val;
5044
5045         /* CL37 Autoneg */
5046         CL22_RD_OVER_CL45(bp, phy,
5047                           MDIO_REG_BANK_COMBO_IEEE0,
5048                           MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
5049
5050         /* CL37 Autoneg Enabled */
5051         if (vars->line_speed == SPEED_AUTO_NEG)
5052                 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
5053         else /* CL37 Autoneg Disabled */
5054                 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5055                              MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
5056
5057         CL22_WR_OVER_CL45(bp, phy,
5058                           MDIO_REG_BANK_COMBO_IEEE0,
5059                           MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
5060
5061         /* Enable/Disable Autodetection */
5062
5063         CL22_RD_OVER_CL45(bp, phy,
5064                           MDIO_REG_BANK_SERDES_DIGITAL,
5065                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, &reg_val);
5066         reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
5067                     MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
5068         reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
5069         if (vars->line_speed == SPEED_AUTO_NEG)
5070                 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
5071         else
5072                 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
5073
5074         CL22_WR_OVER_CL45(bp, phy,
5075                           MDIO_REG_BANK_SERDES_DIGITAL,
5076                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
5077
5078         /* Enable TetonII and BAM autoneg */
5079         CL22_RD_OVER_CL45(bp, phy,
5080                           MDIO_REG_BANK_BAM_NEXT_PAGE,
5081                           MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
5082                           &reg_val);
5083         if (vars->line_speed == SPEED_AUTO_NEG) {
5084                 /* Enable BAM aneg Mode and TetonII aneg Mode */
5085                 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
5086                             MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
5087         } else {
5088                 /* TetonII and BAM Autoneg Disabled */
5089                 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
5090                              MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
5091         }
5092         CL22_WR_OVER_CL45(bp, phy,
5093                           MDIO_REG_BANK_BAM_NEXT_PAGE,
5094                           MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
5095                           reg_val);
5096
5097         if (enable_cl73) {
5098                 /* Enable Cl73 FSM status bits */
5099                 CL22_WR_OVER_CL45(bp, phy,
5100                                   MDIO_REG_BANK_CL73_USERB0,
5101                                   MDIO_CL73_USERB0_CL73_UCTRL,
5102                                   0xe);
5103
5104                 /* Enable BAM Station Manager*/
5105                 CL22_WR_OVER_CL45(bp, phy,
5106                         MDIO_REG_BANK_CL73_USERB0,
5107                         MDIO_CL73_USERB0_CL73_BAM_CTRL1,
5108                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
5109                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
5110                         MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
5111
5112                 /* Advertise CL73 link speeds */
5113                 CL22_RD_OVER_CL45(bp, phy,
5114                                   MDIO_REG_BANK_CL73_IEEEB1,
5115                                   MDIO_CL73_IEEEB1_AN_ADV2,
5116                                   &reg_val);
5117                 if (phy->speed_cap_mask &
5118                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
5119                         reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
5120                 if (phy->speed_cap_mask &
5121                     PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
5122                         reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
5123
5124                 CL22_WR_OVER_CL45(bp, phy,
5125                                   MDIO_REG_BANK_CL73_IEEEB1,
5126                                   MDIO_CL73_IEEEB1_AN_ADV2,
5127                                   reg_val);
5128
5129                 /* CL73 Autoneg Enabled */
5130                 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
5131
5132         } else /* CL73 Autoneg Disabled */
5133                 reg_val = 0;
5134
5135         CL22_WR_OVER_CL45(bp, phy,
5136                           MDIO_REG_BANK_CL73_IEEEB0,
5137                           MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
5138 }
5139
5140 /* Program SerDes, forced speed */
5141 static void bnx2x_program_serdes(struct bnx2x_phy *phy,
5142                                  struct link_params *params,
5143                                  struct link_vars *vars)
5144 {
5145         struct bnx2x *bp = params->bp;
5146         u16 reg_val;
5147
5148         /* Program duplex, disable autoneg and sgmii*/
5149         CL22_RD_OVER_CL45(bp, phy,
5150                           MDIO_REG_BANK_COMBO_IEEE0,
5151                           MDIO_COMBO_IEEE0_MII_CONTROL, &reg_val);
5152         reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
5153                      MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5154                      MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
5155         if (phy->req_duplex == DUPLEX_FULL)
5156                 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
5157         CL22_WR_OVER_CL45(bp, phy,
5158                           MDIO_REG_BANK_COMBO_IEEE0,
5159                           MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
5160
5161         /* Program speed
5162          *  - needed only if the speed is greater than 1G (2.5G or 10G)
5163          */
5164         CL22_RD_OVER_CL45(bp, phy,
5165                           MDIO_REG_BANK_SERDES_DIGITAL,
5166                           MDIO_SERDES_DIGITAL_MISC1, &reg_val);
5167         /* Clearing the speed value before setting the right speed */
5168         DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
5169
5170         reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
5171                      MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
5172
5173         if (!((vars->line_speed == SPEED_1000) ||
5174               (vars->line_speed == SPEED_100) ||
5175               (vars->line_speed == SPEED_10))) {
5176
5177                 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
5178                             MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
5179                 if (vars->line_speed == SPEED_10000)
5180                         reg_val |=
5181                                 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
5182         }
5183
5184         CL22_WR_OVER_CL45(bp, phy,
5185                           MDIO_REG_BANK_SERDES_DIGITAL,
5186                           MDIO_SERDES_DIGITAL_MISC1, reg_val);
5187
5188 }
5189
5190 static void bnx2x_set_brcm_cl37_advertisement(struct bnx2x_phy *phy,
5191                                               struct link_params *params)
5192 {
5193         struct bnx2x *bp = params->bp;
5194         u16 val = 0;
5195
5196         /* Set extended capabilities */
5197         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
5198                 val |= MDIO_OVER_1G_UP1_2_5G;
5199         if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
5200                 val |= MDIO_OVER_1G_UP1_10G;
5201         CL22_WR_OVER_CL45(bp, phy,
5202                           MDIO_REG_BANK_OVER_1G,
5203                           MDIO_OVER_1G_UP1, val);
5204
5205         CL22_WR_OVER_CL45(bp, phy,
5206                           MDIO_REG_BANK_OVER_1G,
5207                           MDIO_OVER_1G_UP3, 0x400);
5208 }
5209
5210 static void bnx2x_set_ieee_aneg_advertisement(struct bnx2x_phy *phy,
5211                                               struct link_params *params,
5212                                               u16 ieee_fc)
5213 {
5214         struct bnx2x *bp = params->bp;
5215         u16 val;
5216         /* For AN, we are always publishing full duplex */
5217
5218         CL22_WR_OVER_CL45(bp, phy,
5219                           MDIO_REG_BANK_COMBO_IEEE0,
5220                           MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
5221         CL22_RD_OVER_CL45(bp, phy,
5222                           MDIO_REG_BANK_CL73_IEEEB1,
5223                           MDIO_CL73_IEEEB1_AN_ADV1, &val);
5224         val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
5225         val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
5226         CL22_WR_OVER_CL45(bp, phy,
5227                           MDIO_REG_BANK_CL73_IEEEB1,
5228                           MDIO_CL73_IEEEB1_AN_ADV1, val);
5229 }
5230
5231 static void bnx2x_restart_autoneg(struct bnx2x_phy *phy,
5232                                   struct link_params *params,
5233                                   u8 enable_cl73)
5234 {
5235         struct bnx2x *bp = params->bp;
5236         u16 mii_control;
5237
5238         DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n");
5239         /* Enable and restart BAM/CL37 aneg */
5240
5241         if (enable_cl73) {
5242                 CL22_RD_OVER_CL45(bp, phy,
5243                                   MDIO_REG_BANK_CL73_IEEEB0,
5244                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5245                                   &mii_control);
5246
5247                 CL22_WR_OVER_CL45(bp, phy,
5248                                   MDIO_REG_BANK_CL73_IEEEB0,
5249                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5250                                   (mii_control |
5251                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
5252                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
5253         } else {
5254
5255                 CL22_RD_OVER_CL45(bp, phy,
5256                                   MDIO_REG_BANK_COMBO_IEEE0,
5257                                   MDIO_COMBO_IEEE0_MII_CONTROL,
5258                                   &mii_control);
5259                 DP(NETIF_MSG_LINK,
5260                          "bnx2x_restart_autoneg mii_control before = 0x%x\n",
5261                          mii_control);
5262                 CL22_WR_OVER_CL45(bp, phy,
5263                                   MDIO_REG_BANK_COMBO_IEEE0,
5264                                   MDIO_COMBO_IEEE0_MII_CONTROL,
5265                                   (mii_control |
5266                                    MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5267                                    MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
5268         }
5269 }
5270
5271 static void bnx2x_initialize_sgmii_process(struct bnx2x_phy *phy,
5272                                            struct link_params *params,
5273                                            struct link_vars *vars)
5274 {
5275         struct bnx2x *bp = params->bp;
5276         u16 control1;
5277
5278         /* In SGMII mode, the unicore is always slave */
5279
5280         CL22_RD_OVER_CL45(bp, phy,
5281                           MDIO_REG_BANK_SERDES_DIGITAL,
5282                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
5283                           &control1);
5284         control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
5285         /* Set sgmii mode (and not fiber) */
5286         control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
5287                       MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
5288                       MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
5289         CL22_WR_OVER_CL45(bp, phy,
5290                           MDIO_REG_BANK_SERDES_DIGITAL,
5291                           MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
5292                           control1);
5293
5294         /* If forced speed */
5295         if (!(vars->line_speed == SPEED_AUTO_NEG)) {
5296                 /* Set speed, disable autoneg */
5297                 u16 mii_control;
5298
5299                 CL22_RD_OVER_CL45(bp, phy,
5300                                   MDIO_REG_BANK_COMBO_IEEE0,
5301                                   MDIO_COMBO_IEEE0_MII_CONTROL,
5302                                   &mii_control);
5303                 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5304                                  MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
5305                                  MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
5306
5307                 switch (vars->line_speed) {
5308                 case SPEED_100:
5309                         mii_control |=
5310                                 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
5311                         break;
5312                 case SPEED_1000:
5313                         mii_control |=
5314                                 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
5315                         break;
5316                 case SPEED_10:
5317                         /* There is nothing to set for 10M */
5318                         break;
5319                 default:
5320                         /* Invalid speed for SGMII */
5321                         DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
5322                                   vars->line_speed);
5323                         break;
5324                 }
5325
5326                 /* Setting the full duplex */
5327                 if (phy->req_duplex == DUPLEX_FULL)
5328                         mii_control |=
5329                                 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
5330                 CL22_WR_OVER_CL45(bp, phy,
5331                                   MDIO_REG_BANK_COMBO_IEEE0,
5332                                   MDIO_COMBO_IEEE0_MII_CONTROL,
5333                                   mii_control);
5334
5335         } else { /* AN mode */
5336                 /* Enable and restart AN */
5337                 bnx2x_restart_autoneg(phy, params, 0);
5338         }
5339 }
5340
5341 /* Link management
5342  */
5343 static int bnx2x_direct_parallel_detect_used(struct bnx2x_phy *phy,
5344                                              struct link_params *params)
5345 {
5346         struct bnx2x *bp = params->bp;
5347         u16 pd_10g, status2_1000x;
5348         if (phy->req_line_speed != SPEED_AUTO_NEG)
5349                 return 0;
5350         CL22_RD_OVER_CL45(bp, phy,
5351                           MDIO_REG_BANK_SERDES_DIGITAL,
5352                           MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
5353                           &status2_1000x);
5354         CL22_RD_OVER_CL45(bp, phy,
5355                           MDIO_REG_BANK_SERDES_DIGITAL,
5356                           MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
5357                           &status2_1000x);
5358         if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
5359                 DP(NETIF_MSG_LINK, "1G parallel detect link on port %d\n",
5360                          params->port);
5361                 return 1;
5362         }
5363
5364         CL22_RD_OVER_CL45(bp, phy,
5365                           MDIO_REG_BANK_10G_PARALLEL_DETECT,
5366                           MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
5367                           &pd_10g);
5368
5369         if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
5370                 DP(NETIF_MSG_LINK, "10G parallel detect link on port %d\n",
5371                          params->port);
5372                 return 1;
5373         }
5374         return 0;
5375 }
5376
5377 static void bnx2x_update_adv_fc(struct bnx2x_phy *phy,
5378                                 struct link_params *params,
5379                                 struct link_vars *vars,
5380                                 u32 gp_status)
5381 {
5382         u16 ld_pause;   /* local driver */
5383         u16 lp_pause;   /* link partner */
5384         u16 pause_result;
5385         struct bnx2x *bp = params->bp;
5386         if ((gp_status &
5387              (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5388               MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
5389             (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
5390              MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
5391
5392                 CL22_RD_OVER_CL45(bp, phy,
5393                                   MDIO_REG_BANK_CL73_IEEEB1,
5394                                   MDIO_CL73_IEEEB1_AN_ADV1,
5395                                   &ld_pause);
5396                 CL22_RD_OVER_CL45(bp, phy,
5397                                   MDIO_REG_BANK_CL73_IEEEB1,
5398                                   MDIO_CL73_IEEEB1_AN_LP_ADV1,
5399                                   &lp_pause);
5400                 pause_result = (ld_pause &
5401                                 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK) >> 8;
5402                 pause_result |= (lp_pause &
5403                                  MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK) >> 10;
5404                 DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n", pause_result);
5405         } else {
5406                 CL22_RD_OVER_CL45(bp, phy,
5407                                   MDIO_REG_BANK_COMBO_IEEE0,
5408                                   MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
5409                                   &ld_pause);
5410                 CL22_RD_OVER_CL45(bp, phy,
5411                         MDIO_REG_BANK_COMBO_IEEE0,
5412                         MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
5413                         &lp_pause);
5414                 pause_result = (ld_pause &
5415                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
5416                 pause_result |= (lp_pause &
5417                                  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
5418                 DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n", pause_result);
5419         }
5420         bnx2x_pause_resolve(phy, params, vars, pause_result);
5421
5422 }
5423
5424 static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy *phy,
5425                                     struct link_params *params,
5426                                     struct link_vars *vars,
5427                                     u32 gp_status)
5428 {
5429         struct bnx2x *bp = params->bp;
5430         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5431
5432         /* Resolve from gp_status in case of AN complete and not sgmii */
5433         if (phy->req_flow_ctrl != BNX2X_FLOW_CTRL_AUTO) {
5434                 /* Update the advertised flow-controled of LD/LP in AN */
5435                 if (phy->req_line_speed == SPEED_AUTO_NEG)
5436                         bnx2x_update_adv_fc(phy, params, vars, gp_status);
5437                 /* But set the flow-control result as the requested one */
5438                 vars->flow_ctrl = phy->req_flow_ctrl;
5439         } else if (phy->req_line_speed != SPEED_AUTO_NEG)
5440                 vars->flow_ctrl = params->req_fc_auto_adv;
5441         else if ((gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
5442                  (!(vars->phy_flags & PHY_SGMII_FLAG))) {
5443                 if (bnx2x_direct_parallel_detect_used(phy, params)) {
5444                         vars->flow_ctrl = params->req_fc_auto_adv;
5445                         return;
5446                 }
5447                 bnx2x_update_adv_fc(phy, params, vars, gp_status);
5448         }
5449         DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl);
5450 }
5451
5452 static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy *phy,
5453                                          struct link_params *params)
5454 {
5455         struct bnx2x *bp = params->bp;
5456         u16 rx_status, ustat_val, cl37_fsm_received;
5457         DP(NETIF_MSG_LINK, "bnx2x_check_fallback_to_cl37\n");
5458         /* Step 1: Make sure signal is detected */
5459         CL22_RD_OVER_CL45(bp, phy,
5460                           MDIO_REG_BANK_RX0,
5461                           MDIO_RX0_RX_STATUS,
5462                           &rx_status);
5463         if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
5464             (MDIO_RX0_RX_STATUS_SIGDET)) {
5465                 DP(NETIF_MSG_LINK, "Signal is not detected. Restoring CL73."
5466                              "rx_status(0x80b0) = 0x%x\n", rx_status);
5467                 CL22_WR_OVER_CL45(bp, phy,
5468                                   MDIO_REG_BANK_CL73_IEEEB0,
5469                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5470                                   MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
5471                 return;
5472         }
5473         /* Step 2: Check CL73 state machine */
5474         CL22_RD_OVER_CL45(bp, phy,
5475                           MDIO_REG_BANK_CL73_USERB0,
5476                           MDIO_CL73_USERB0_CL73_USTAT1,
5477                           &ustat_val);
5478         if ((ustat_val &
5479              (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5480               MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
5481             (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
5482               MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
5483                 DP(NETIF_MSG_LINK, "CL73 state-machine is not stable. "
5484                              "ustat_val(0x8371) = 0x%x\n", ustat_val);
5485                 return;
5486         }
5487         /* Step 3: Check CL37 Message Pages received to indicate LP
5488          * supports only CL37
5489          */
5490         CL22_RD_OVER_CL45(bp, phy,
5491                           MDIO_REG_BANK_REMOTE_PHY,
5492                           MDIO_REMOTE_PHY_MISC_RX_STATUS,
5493                           &cl37_fsm_received);
5494         if ((cl37_fsm_received &
5495              (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5496              MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
5497             (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
5498               MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
5499                 DP(NETIF_MSG_LINK, "No CL37 FSM were received. "
5500                              "misc_rx_status(0x8330) = 0x%x\n",
5501                          cl37_fsm_received);
5502                 return;
5503         }
5504         /* The combined cl37/cl73 fsm state information indicating that
5505          * we are connected to a device which does not support cl73, but
5506          * does support cl37 BAM. In this case we disable cl73 and
5507          * restart cl37 auto-neg
5508          */
5509
5510         /* Disable CL73 */
5511         CL22_WR_OVER_CL45(bp, phy,
5512                           MDIO_REG_BANK_CL73_IEEEB0,
5513                           MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5514                           0);
5515         /* Restart CL37 autoneg */
5516         bnx2x_restart_autoneg(phy, params, 0);
5517         DP(NETIF_MSG_LINK, "Disabling CL73, and restarting CL37 autoneg\n");
5518 }
5519
5520 static void bnx2x_xgxs_an_resolve(struct bnx2x_phy *phy,
5521                                   struct link_params *params,
5522                                   struct link_vars *vars,
5523                                   u32 gp_status)
5524 {
5525         if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE)
5526                 vars->link_status |=
5527                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5528
5529         if (bnx2x_direct_parallel_detect_used(phy, params))
5530                 vars->link_status |=
5531                         LINK_STATUS_PARALLEL_DETECTION_USED;
5532 }
5533 static int bnx2x_get_link_speed_duplex(struct bnx2x_phy *phy,
5534                                      struct link_params *params,
5535                                       struct link_vars *vars,
5536                                       u16 is_link_up,
5537                                       u16 speed_mask,
5538                                       u16 is_duplex)
5539 {
5540         struct bnx2x *bp = params->bp;
5541         if (phy->req_line_speed == SPEED_AUTO_NEG)
5542                 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
5543         if (is_link_up) {
5544                 DP(NETIF_MSG_LINK, "phy link up\n");
5545
5546                 vars->phy_link_up = 1;
5547                 vars->link_status |= LINK_STATUS_LINK_UP;
5548
5549                 switch (speed_mask) {
5550                 case GP_STATUS_10M:
5551                         vars->line_speed = SPEED_10;
5552                         if (is_duplex == DUPLEX_FULL)
5553                                 vars->link_status |= LINK_10TFD;
5554                         else
5555                                 vars->link_status |= LINK_10THD;
5556                         break;
5557
5558                 case GP_STATUS_100M:
5559                         vars->line_speed = SPEED_100;
5560                         if (is_duplex == DUPLEX_FULL)
5561                                 vars->link_status |= LINK_100TXFD;
5562                         else
5563                                 vars->link_status |= LINK_100TXHD;
5564                         break;
5565
5566                 case GP_STATUS_1G:
5567                 case GP_STATUS_1G_KX:
5568                         vars->line_speed = SPEED_1000;
5569                         if (is_duplex == DUPLEX_FULL)
5570                                 vars->link_status |= LINK_1000TFD;
5571                         else
5572                                 vars->link_status |= LINK_1000THD;
5573                         break;
5574
5575                 case GP_STATUS_2_5G:
5576                         vars->line_speed = SPEED_2500;
5577                         if (is_duplex == DUPLEX_FULL)
5578                                 vars->link_status |= LINK_2500TFD;
5579                         else
5580                                 vars->link_status |= LINK_2500THD;
5581                         break;
5582
5583                 case GP_STATUS_5G:
5584                 case GP_STATUS_6G:
5585                         DP(NETIF_MSG_LINK,
5586                                  "link speed unsupported  gp_status 0x%x\n",
5587                                   speed_mask);
5588                         return -EINVAL;
5589
5590                 case GP_STATUS_10G_KX4:
5591                 case GP_STATUS_10G_HIG:
5592                 case GP_STATUS_10G_CX4:
5593                 case GP_STATUS_10G_KR:
5594                 case GP_STATUS_10G_SFI:
5595                 case GP_STATUS_10G_XFI:
5596                         vars->line_speed = SPEED_10000;
5597                         vars->link_status |= LINK_10GTFD;
5598                         break;
5599                 case GP_STATUS_20G_DXGXS:
5600                 case GP_STATUS_20G_KR2:
5601                         vars->line_speed = SPEED_20000;
5602                         vars->link_status |= LINK_20GTFD;
5603                         break;
5604                 default:
5605                         DP(NETIF_MSG_LINK,
5606                                   "link speed unsupported gp_status 0x%x\n",
5607                                   speed_mask);
5608                         return -EINVAL;
5609                 }
5610         } else { /* link_down */
5611                 DP(NETIF_MSG_LINK, "phy link down\n");
5612
5613                 vars->phy_link_up = 0;
5614
5615                 vars->duplex = DUPLEX_FULL;
5616                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
5617                 vars->mac_type = MAC_TYPE_NONE;
5618         }
5619         DP(NETIF_MSG_LINK, " phy_link_up %x line_speed %d\n",
5620                     vars->phy_link_up, vars->line_speed);
5621         return 0;
5622 }
5623
5624 static int bnx2x_link_settings_status(struct bnx2x_phy *phy,
5625                                       struct link_params *params,
5626                                       struct link_vars *vars)
5627 {
5628         struct bnx2x *bp = params->bp;
5629
5630         u16 gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask;
5631         int rc = 0;
5632
5633         /* Read gp_status */
5634         CL22_RD_OVER_CL45(bp, phy,
5635                           MDIO_REG_BANK_GP_STATUS,
5636                           MDIO_GP_STATUS_TOP_AN_STATUS1,
5637                           &gp_status);
5638         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
5639                 duplex = DUPLEX_FULL;
5640         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)
5641                 link_up = 1;
5642         speed_mask = gp_status & GP_STATUS_SPEED_MASK;
5643         DP(NETIF_MSG_LINK, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x\n",
5644                        gp_status, link_up, speed_mask);
5645         rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, speed_mask,
5646                                          duplex);
5647         if (rc == -EINVAL)
5648                 return rc;
5649
5650         if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
5651                 if (SINGLE_MEDIA_DIRECT(params)) {
5652                         vars->duplex = duplex;
5653                         bnx2x_flow_ctrl_resolve(phy, params, vars, gp_status);
5654                         if (phy->req_line_speed == SPEED_AUTO_NEG)
5655                                 bnx2x_xgxs_an_resolve(phy, params, vars,
5656                                                       gp_status);
5657                 }
5658         } else { /* Link_down */
5659                 if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
5660                     SINGLE_MEDIA_DIRECT(params)) {
5661                         /* Check signal is detected */
5662                         bnx2x_check_fallback_to_cl37(phy, params);
5663                 }
5664         }
5665
5666         /* Read LP advertised speeds*/
5667         if (SINGLE_MEDIA_DIRECT(params) &&
5668             (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)) {
5669                 u16 val;
5670
5671                 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_CL73_IEEEB1,
5672                                   MDIO_CL73_IEEEB1_AN_LP_ADV2, &val);
5673
5674                 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
5675                         vars->link_status |=
5676                                 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
5677                 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
5678                            MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
5679                         vars->link_status |=
5680                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5681
5682                 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_OVER_1G,
5683                                   MDIO_OVER_1G_LP_UP1, &val);
5684
5685                 if (val & MDIO_OVER_1G_UP1_2_5G)
5686                         vars->link_status |=
5687                                 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
5688                 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
5689                         vars->link_status |=
5690                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5691         }
5692
5693         DP(NETIF_MSG_LINK, "duplex %x  flow_ctrl 0x%x link_status 0x%x\n",
5694                    vars->duplex, vars->flow_ctrl, vars->link_status);
5695         return rc;
5696 }
5697
5698 static int bnx2x_warpcore_read_status(struct bnx2x_phy *phy,
5699                                      struct link_params *params,
5700                                      struct link_vars *vars)
5701 {
5702         struct bnx2x *bp = params->bp;
5703         u8 lane;
5704         u16 gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL;
5705         int rc = 0;
5706         lane = bnx2x_get_warpcore_lane(phy, params);
5707         /* Read gp_status */
5708         if ((params->loopback_mode) &&
5709             (phy->flags & FLAGS_WC_DUAL_MODE)) {
5710                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5711                                 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up);
5712                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5713                                 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up);
5714                 link_up &= 0x1;
5715         } else if ((phy->req_line_speed > SPEED_10000) &&
5716                 (phy->supported & SUPPORTED_20000baseMLD2_Full)) {
5717                 u16 temp_link_up;
5718                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5719                                 1, &temp_link_up);
5720                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5721                                 1, &link_up);
5722                 DP(NETIF_MSG_LINK, "PCS RX link status = 0x%x-->0x%x\n",
5723                                temp_link_up, link_up);
5724                 link_up &= (1<<2);
5725                 if (link_up)
5726                         bnx2x_ext_phy_resolve_fc(phy, params, vars);
5727         } else {
5728                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5729                                 MDIO_WC_REG_GP2_STATUS_GP_2_1,
5730                                 &gp_status1);
5731                 DP(NETIF_MSG_LINK, "0x81d1 = 0x%x\n", gp_status1);
5732                 /* Check for either KR, 1G, or AN up. */
5733                 link_up = ((gp_status1 >> 8) |
5734                            (gp_status1 >> 12) |
5735                            (gp_status1)) &
5736                         (1 << lane);
5737                 if (phy->supported & SUPPORTED_20000baseKR2_Full) {
5738                         u16 an_link;
5739                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
5740                                         MDIO_AN_REG_STATUS, &an_link);
5741                         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
5742                                         MDIO_AN_REG_STATUS, &an_link);
5743                         link_up |= (an_link & (1<<2));
5744                 }
5745                 if (link_up && SINGLE_MEDIA_DIRECT(params)) {
5746                         u16 pd, gp_status4;
5747                         if (phy->req_line_speed == SPEED_AUTO_NEG) {
5748                                 /* Check Autoneg complete */
5749                                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5750                                                 MDIO_WC_REG_GP2_STATUS_GP_2_4,
5751                                                 &gp_status4);
5752                                 if (gp_status4 & ((1<<12)<<lane))
5753                                         vars->link_status |=
5754                                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
5755
5756                                 /* Check parallel detect used */
5757                                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5758                                                 MDIO_WC_REG_PAR_DET_10G_STATUS,
5759                                                 &pd);
5760                                 if (pd & (1<<15))
5761                                         vars->link_status |=
5762                                         LINK_STATUS_PARALLEL_DETECTION_USED;
5763                         }
5764                         bnx2x_ext_phy_resolve_fc(phy, params, vars);
5765                         vars->duplex = duplex;
5766                 }
5767         }
5768
5769         if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) &&
5770             SINGLE_MEDIA_DIRECT(params)) {
5771                 u16 val;
5772
5773                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
5774                                 MDIO_AN_REG_LP_AUTO_NEG2, &val);
5775
5776                 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
5777                         vars->link_status |=
5778                                 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
5779                 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
5780                            MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
5781                         vars->link_status |=
5782                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5783
5784                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5785                                 MDIO_WC_REG_DIGITAL3_LP_UP1, &val);
5786
5787                 if (val & MDIO_OVER_1G_UP1_2_5G)
5788                         vars->link_status |=
5789                                 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
5790                 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
5791                         vars->link_status |=
5792                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
5793
5794         }
5795
5796
5797         if (lane < 2) {
5798                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5799                                 MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed);
5800         } else {
5801                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
5802                                 MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed);
5803         }
5804         DP(NETIF_MSG_LINK, "lane %d gp_speed 0x%x\n", lane, gp_speed);
5805
5806         if ((lane & 1) == 0)
5807                 gp_speed <<= 8;
5808         gp_speed &= 0x3f00;
5809         link_up = !!link_up;
5810
5811         rc = bnx2x_get_link_speed_duplex(phy, params, vars, link_up, gp_speed,
5812                                          duplex);
5813
5814         /* In case of KR link down, start up the recovering procedure */
5815         if ((!link_up) && (phy->media_type == ETH_PHY_KR) &&
5816             (!(phy->flags & FLAGS_WC_DUAL_MODE)))
5817                 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
5818
5819         DP(NETIF_MSG_LINK, "duplex %x  flow_ctrl 0x%x link_status 0x%x\n",
5820                    vars->duplex, vars->flow_ctrl, vars->link_status);
5821         return rc;
5822 }
5823 static void bnx2x_set_gmii_tx_driver(struct link_params *params)
5824 {
5825         struct bnx2x *bp = params->bp;
5826         struct bnx2x_phy *phy = &params->phy[INT_PHY];
5827         u16 lp_up2;
5828         u16 tx_driver;
5829         u16 bank;
5830
5831         /* Read precomp */
5832         CL22_RD_OVER_CL45(bp, phy,
5833                           MDIO_REG_BANK_OVER_1G,
5834                           MDIO_OVER_1G_LP_UP2, &lp_up2);
5835
5836         /* Bits [10:7] at lp_up2, positioned at [15:12] */
5837         lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
5838                    MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
5839                   MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
5840
5841         if (lp_up2 == 0)
5842                 return;
5843
5844         for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
5845               bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
5846                 CL22_RD_OVER_CL45(bp, phy,
5847                                   bank,
5848                                   MDIO_TX0_TX_DRIVER, &tx_driver);
5849
5850                 /* Replace tx_driver bits [15:12] */
5851                 if (lp_up2 !=
5852                     (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
5853                         tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
5854                         tx_driver |= lp_up2;
5855                         CL22_WR_OVER_CL45(bp, phy,
5856                                           bank,
5857                                           MDIO_TX0_TX_DRIVER, tx_driver);
5858                 }
5859         }
5860 }
5861
5862 static int bnx2x_emac_program(struct link_params *params,
5863                               struct link_vars *vars)
5864 {
5865         struct bnx2x *bp = params->bp;
5866         u8 port = params->port;
5867         u16 mode = 0;
5868
5869         DP(NETIF_MSG_LINK, "setting link speed & duplex\n");
5870         bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 +
5871                        EMAC_REG_EMAC_MODE,
5872                        (EMAC_MODE_25G_MODE |
5873                         EMAC_MODE_PORT_MII_10M |
5874                         EMAC_MODE_HALF_DUPLEX));
5875         switch (vars->line_speed) {
5876         case SPEED_10:
5877                 mode |= EMAC_MODE_PORT_MII_10M;
5878                 break;
5879
5880         case SPEED_100:
5881                 mode |= EMAC_MODE_PORT_MII;
5882                 break;
5883
5884         case SPEED_1000:
5885                 mode |= EMAC_MODE_PORT_GMII;
5886                 break;
5887
5888         case SPEED_2500:
5889                 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
5890                 break;
5891
5892         default:
5893                 /* 10G not valid for EMAC */
5894                 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
5895                            vars->line_speed);
5896                 return -EINVAL;
5897         }
5898
5899         if (vars->duplex == DUPLEX_HALF)
5900                 mode |= EMAC_MODE_HALF_DUPLEX;
5901         bnx2x_bits_en(bp,
5902                       GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
5903                       mode);
5904
5905         bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
5906         return 0;
5907 }
5908
5909 static void bnx2x_set_preemphasis(struct bnx2x_phy *phy,
5910                                   struct link_params *params)
5911 {
5912
5913         u16 bank, i = 0;
5914         struct bnx2x *bp = params->bp;
5915
5916         for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
5917               bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
5918                         CL22_WR_OVER_CL45(bp, phy,
5919                                           bank,
5920                                           MDIO_RX0_RX_EQ_BOOST,
5921                                           phy->rx_preemphasis[i]);
5922         }
5923
5924         for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
5925                       bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
5926                         CL22_WR_OVER_CL45(bp, phy,
5927                                           bank,
5928                                           MDIO_TX0_TX_DRIVER,
5929                                           phy->tx_preemphasis[i]);
5930         }
5931 }
5932
5933 static void bnx2x_xgxs_config_init(struct bnx2x_phy *phy,
5934                                    struct link_params *params,
5935                                    struct link_vars *vars)
5936 {
5937         struct bnx2x *bp = params->bp;
5938         u8 enable_cl73 = (SINGLE_MEDIA_DIRECT(params) ||
5939                           (params->loopback_mode == LOOPBACK_XGXS));
5940         if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
5941                 if (SINGLE_MEDIA_DIRECT(params) &&
5942                     (params->feature_config_flags &
5943                      FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
5944                         bnx2x_set_preemphasis(phy, params);
5945
5946                 /* Forced speed requested? */
5947                 if (vars->line_speed != SPEED_AUTO_NEG ||
5948                     (SINGLE_MEDIA_DIRECT(params) &&
5949                      params->loopback_mode == LOOPBACK_EXT)) {
5950                         DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
5951
5952                         /* Disable autoneg */
5953                         bnx2x_set_autoneg(phy, params, vars, 0);
5954
5955                         /* Program speed and duplex */
5956                         bnx2x_program_serdes(phy, params, vars);
5957
5958                 } else { /* AN_mode */
5959                         DP(NETIF_MSG_LINK, "not SGMII, AN\n");
5960
5961                         /* AN enabled */
5962                         bnx2x_set_brcm_cl37_advertisement(phy, params);
5963
5964                         /* Program duplex & pause advertisement (for aneg) */
5965                         bnx2x_set_ieee_aneg_advertisement(phy, params,
5966                                                           vars->ieee_fc);
5967
5968                         /* Enable autoneg */
5969                         bnx2x_set_autoneg(phy, params, vars, enable_cl73);
5970
5971                         /* Enable and restart AN */
5972                         bnx2x_restart_autoneg(phy, params, enable_cl73);
5973                 }
5974
5975         } else { /* SGMII mode */
5976                 DP(NETIF_MSG_LINK, "SGMII\n");
5977
5978                 bnx2x_initialize_sgmii_process(phy, params, vars);
5979         }
5980 }
5981
5982 static int bnx2x_prepare_xgxs(struct bnx2x_phy *phy,
5983                           struct link_params *params,
5984                           struct link_vars *vars)
5985 {
5986         int rc;
5987         vars->phy_flags |= PHY_XGXS_FLAG;
5988         if ((phy->req_line_speed &&
5989              ((phy->req_line_speed == SPEED_100) ||
5990               (phy->req_line_speed == SPEED_10))) ||
5991             (!phy->req_line_speed &&
5992              (phy->speed_cap_mask >=
5993               PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
5994              (phy->speed_cap_mask <
5995               PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
5996             (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD))
5997                 vars->phy_flags |= PHY_SGMII_FLAG;
5998         else
5999                 vars->phy_flags &= ~PHY_SGMII_FLAG;
6000
6001         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
6002         bnx2x_set_aer_mmd(params, phy);
6003         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
6004                 bnx2x_set_master_ln(params, phy);
6005
6006         rc = bnx2x_reset_unicore(params, phy, 0);
6007         /* Reset the SerDes and wait for reset bit return low */
6008         if (rc)
6009                 return rc;
6010
6011         bnx2x_set_aer_mmd(params, phy);
6012         /* Setting the masterLn_def again after the reset */
6013         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
6014                 bnx2x_set_master_ln(params, phy);
6015                 bnx2x_set_swap_lanes(params, phy);
6016         }
6017
6018         return rc;
6019 }
6020
6021 static u16 bnx2x_wait_reset_complete(struct bnx2x *bp,
6022                                      struct bnx2x_phy *phy,
6023                                      struct link_params *params)
6024 {
6025         u16 cnt, ctrl;
6026         /* Wait for soft reset to get cleared up to 1 sec */
6027         for (cnt = 0; cnt < 1000; cnt++) {
6028                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
6029                         bnx2x_cl22_read(bp, phy,
6030                                 MDIO_PMA_REG_CTRL, &ctrl);
6031                 else
6032                         bnx2x_cl45_read(bp, phy,
6033                                 MDIO_PMA_DEVAD,
6034                                 MDIO_PMA_REG_CTRL, &ctrl);
6035                 if (!(ctrl & (1<<15)))
6036                         break;
6037                 usleep_range(1000, 2000);
6038         }
6039
6040         if (cnt == 1000)
6041                 netdev_err(bp->dev,  "Warning: PHY was not initialized,"
6042                                       " Port %d\n",
6043                          params->port);
6044         DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt);
6045         return cnt;
6046 }
6047
6048 static void bnx2x_link_int_enable(struct link_params *params)
6049 {
6050         u8 port = params->port;
6051         u32 mask;
6052         struct bnx2x *bp = params->bp;
6053
6054         /* Setting the status to report on link up for either XGXS or SerDes */
6055         if (CHIP_IS_E3(bp)) {
6056                 mask = NIG_MASK_XGXS0_LINK_STATUS;
6057                 if (!(SINGLE_MEDIA_DIRECT(params)))
6058                         mask |= NIG_MASK_MI_INT;
6059         } else if (params->switch_cfg == SWITCH_CFG_10G) {
6060                 mask = (NIG_MASK_XGXS0_LINK10G |
6061                         NIG_MASK_XGXS0_LINK_STATUS);
6062                 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n");
6063                 if (!(SINGLE_MEDIA_DIRECT(params)) &&
6064                         params->phy[INT_PHY].type !=
6065                                 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
6066                         mask |= NIG_MASK_MI_INT;
6067                         DP(NETIF_MSG_LINK, "enabled external phy int\n");
6068                 }
6069
6070         } else { /* SerDes */
6071                 mask = NIG_MASK_SERDES0_LINK_STATUS;
6072                 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n");
6073                 if (!(SINGLE_MEDIA_DIRECT(params)) &&
6074                         params->phy[INT_PHY].type !=
6075                                 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
6076                         mask |= NIG_MASK_MI_INT;
6077                         DP(NETIF_MSG_LINK, "enabled external phy int\n");
6078                 }
6079         }
6080         bnx2x_bits_en(bp,
6081                       NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
6082                       mask);
6083
6084         DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port,
6085                  (params->switch_cfg == SWITCH_CFG_10G),
6086                  REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
6087         DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
6088                  REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6089                  REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
6090                  REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
6091         DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
6092            REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6093            REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6094 }
6095
6096 static void bnx2x_rearm_latch_signal(struct bnx2x *bp, u8 port,
6097                                      u8 exp_mi_int)
6098 {
6099         u32 latch_status = 0;
6100
6101         /* Disable the MI INT ( external phy int ) by writing 1 to the
6102          * status register. Link down indication is high-active-signal,
6103          * so in this case we need to write the status to clear the XOR
6104          */
6105         /* Read Latched signals */
6106         latch_status = REG_RD(bp,
6107                                     NIG_REG_LATCH_STATUS_0 + port*8);
6108         DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status);
6109         /* Handle only those with latched-signal=up.*/
6110         if (exp_mi_int)
6111                 bnx2x_bits_en(bp,
6112                               NIG_REG_STATUS_INTERRUPT_PORT0
6113                               + port*4,
6114                               NIG_STATUS_EMAC0_MI_INT);
6115         else
6116                 bnx2x_bits_dis(bp,
6117                                NIG_REG_STATUS_INTERRUPT_PORT0
6118                                + port*4,
6119                                NIG_STATUS_EMAC0_MI_INT);
6120
6121         if (latch_status & 1) {
6122
6123                 /* For all latched-signal=up : Re-Arm Latch signals */
6124                 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8,
6125                        (latch_status & 0xfffe) | (latch_status & 1));
6126         }
6127         /* For all latched-signal=up,Write original_signal to status */
6128 }
6129
6130 static void bnx2x_link_int_ack(struct link_params *params,
6131                                struct link_vars *vars, u8 is_10g_plus)
6132 {
6133         struct bnx2x *bp = params->bp;
6134         u8 port = params->port;
6135         u32 mask;
6136         /* First reset all status we assume only one line will be
6137          * change at a time
6138          */
6139         bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
6140                        (NIG_STATUS_XGXS0_LINK10G |
6141                         NIG_STATUS_XGXS0_LINK_STATUS |
6142                         NIG_STATUS_SERDES0_LINK_STATUS));
6143         if (vars->phy_link_up) {
6144                 if (USES_WARPCORE(bp))
6145                         mask = NIG_STATUS_XGXS0_LINK_STATUS;
6146                 else {
6147                         if (is_10g_plus)
6148                                 mask = NIG_STATUS_XGXS0_LINK10G;
6149                         else if (params->switch_cfg == SWITCH_CFG_10G) {
6150                                 /* Disable the link interrupt by writing 1 to
6151                                  * the relevant lane in the status register
6152                                  */
6153                                 u32 ser_lane =
6154                                         ((params->lane_config &
6155                                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
6156                                     PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
6157                                 mask = ((1 << ser_lane) <<
6158                                        NIG_STATUS_XGXS0_LINK_STATUS_SIZE);
6159                         } else
6160                                 mask = NIG_STATUS_SERDES0_LINK_STATUS;
6161                 }
6162                 DP(NETIF_MSG_LINK, "Ack link up interrupt with mask 0x%x\n",
6163                                mask);
6164                 bnx2x_bits_en(bp,
6165                               NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
6166                               mask);
6167         }
6168 }
6169
6170 static int bnx2x_format_ver(u32 num, u8 *str, u16 *len)
6171 {
6172         u8 *str_ptr = str;
6173         u32 mask = 0xf0000000;
6174         u8 shift = 8*4;
6175         u8 digit;
6176         u8 remove_leading_zeros = 1;
6177         if (*len < 10) {
6178                 /* Need more than 10chars for this format */
6179                 *str_ptr = '\0';
6180                 (*len)--;
6181                 return -EINVAL;
6182         }
6183         while (shift > 0) {
6184
6185                 shift -= 4;
6186                 digit = ((num & mask) >> shift);
6187                 if (digit == 0 && remove_leading_zeros) {
6188                         *str_ptr = '0';
6189                 } else {
6190                         if (digit < 0xa)
6191                                 *str_ptr = digit + '0';
6192                         else
6193                                 *str_ptr = digit - 0xa + 'a';
6194
6195                         remove_leading_zeros = 0;
6196                         str_ptr++;
6197                         (*len)--;
6198                 }
6199                 mask = mask >> 4;
6200                 if (shift == 4*4) {
6201                         if (remove_leading_zeros) {
6202                                 str_ptr++;
6203                                 (*len)--;
6204                         }
6205                         *str_ptr = '.';
6206                         str_ptr++;
6207                         (*len)--;
6208                         remove_leading_zeros = 1;
6209                 }
6210         }
6211         if (remove_leading_zeros)
6212                 (*len)--;
6213         return 0;
6214 }
6215
6216 static int bnx2x_3_seq_format_ver(u32 num, u8 *str, u16 *len)
6217 {
6218         u8 *str_ptr = str;
6219         u32 mask = 0x00f00000;
6220         u8 shift = 8*3;
6221         u8 digit;
6222         u8 remove_leading_zeros = 1;
6223
6224         if (*len < 10) {
6225                 /* Need more than 10chars for this format */
6226                 *str_ptr = '\0';
6227                 (*len)--;
6228                 return -EINVAL;
6229         }
6230
6231         while (shift > 0) {
6232                 shift -= 4;
6233                 digit = ((num & mask) >> shift);
6234                 if (digit == 0 && remove_leading_zeros) {
6235                         *str_ptr = '0';
6236                 } else {
6237                         if (digit < 0xa)
6238                                 *str_ptr = digit + '0';
6239                         else
6240                                 *str_ptr = digit - 0xa + 'a';
6241
6242                         remove_leading_zeros = 0;
6243                         str_ptr++;
6244                         (*len)--;
6245                 }
6246                 mask = mask >> 4;
6247                 if ((shift == 4*4) || (shift == 4*2)) {
6248                         if (remove_leading_zeros) {
6249                                 str_ptr++;
6250                                 (*len)--;
6251                         }
6252                         *str_ptr = '.';
6253                         str_ptr++;
6254                         (*len)--;
6255                         remove_leading_zeros = 1;
6256                 }
6257         }
6258         if (remove_leading_zeros)
6259                 (*len)--;
6260         return 0;
6261 }
6262
6263 static int bnx2x_null_format_ver(u32 spirom_ver, u8 *str, u16 *len)
6264 {
6265         str[0] = '\0';
6266         (*len)--;
6267         return 0;
6268 }
6269
6270 int bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 *version,
6271                                  u16 len)
6272 {
6273         struct bnx2x *bp;
6274         u32 spirom_ver = 0;
6275         int status = 0;
6276         u8 *ver_p = version;
6277         u16 remain_len = len;
6278         if (version == NULL || params == NULL)
6279                 return -EINVAL;
6280         bp = params->bp;
6281
6282         /* Extract first external phy*/
6283         version[0] = '\0';
6284         spirom_ver = REG_RD(bp, params->phy[EXT_PHY1].ver_addr);
6285
6286         if (params->phy[EXT_PHY1].format_fw_ver) {
6287                 status |= params->phy[EXT_PHY1].format_fw_ver(spirom_ver,
6288                                                               ver_p,
6289                                                               &remain_len);
6290                 ver_p += (len - remain_len);
6291         }
6292         if ((params->num_phys == MAX_PHYS) &&
6293             (params->phy[EXT_PHY2].ver_addr != 0)) {
6294                 spirom_ver = REG_RD(bp, params->phy[EXT_PHY2].ver_addr);
6295                 if (params->phy[EXT_PHY2].format_fw_ver) {
6296                         *ver_p = '/';
6297                         ver_p++;
6298                         remain_len--;
6299                         status |= params->phy[EXT_PHY2].format_fw_ver(
6300                                 spirom_ver,
6301                                 ver_p,
6302                                 &remain_len);
6303                         ver_p = version + (len - remain_len);
6304                 }
6305         }
6306         *ver_p = '\0';
6307         return status;
6308 }
6309
6310 static void bnx2x_set_xgxs_loopback(struct bnx2x_phy *phy,
6311                                     struct link_params *params)
6312 {
6313         u8 port = params->port;
6314         struct bnx2x *bp = params->bp;
6315
6316         if (phy->req_line_speed != SPEED_1000) {
6317                 u32 md_devad = 0;
6318
6319                 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
6320
6321                 if (!CHIP_IS_E3(bp)) {
6322                         /* Change the uni_phy_addr in the nig */
6323                         md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
6324                                                port*0x18));
6325
6326                         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
6327                                0x5);
6328                 }
6329
6330                 bnx2x_cl45_write(bp, phy,
6331                                  5,
6332                                  (MDIO_REG_BANK_AER_BLOCK +
6333                                   (MDIO_AER_BLOCK_AER_REG & 0xf)),
6334                                  0x2800);
6335
6336                 bnx2x_cl45_write(bp, phy,
6337                                  5,
6338                                  (MDIO_REG_BANK_CL73_IEEEB0 +
6339                                   (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
6340                                  0x6041);
6341                 msleep(200);
6342                 /* Set aer mmd back */
6343                 bnx2x_set_aer_mmd(params, phy);
6344
6345                 if (!CHIP_IS_E3(bp)) {
6346                         /* And md_devad */
6347                         REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
6348                                md_devad);
6349                 }
6350         } else {
6351                 u16 mii_ctrl;
6352                 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");
6353                 bnx2x_cl45_read(bp, phy, 5,
6354                                 (MDIO_REG_BANK_COMBO_IEEE0 +
6355                                 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
6356                                 &mii_ctrl);
6357                 bnx2x_cl45_write(bp, phy, 5,
6358                                  (MDIO_REG_BANK_COMBO_IEEE0 +
6359                                  (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
6360                                  mii_ctrl |
6361                                  MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
6362         }
6363 }
6364
6365 int bnx2x_set_led(struct link_params *params,
6366                   struct link_vars *vars, u8 mode, u32 speed)
6367 {
6368         u8 port = params->port;
6369         u16 hw_led_mode = params->hw_led_mode;
6370         int rc = 0;
6371         u8 phy_idx;
6372         u32 tmp;
6373         u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
6374         struct bnx2x *bp = params->bp;
6375         DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
6376         DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
6377                  speed, hw_led_mode);
6378         /* In case */
6379         for (phy_idx = EXT_PHY1; phy_idx < MAX_PHYS; phy_idx++) {
6380                 if (params->phy[phy_idx].set_link_led) {
6381                         params->phy[phy_idx].set_link_led(
6382                                 &params->phy[phy_idx], params, mode);
6383                 }
6384         }
6385
6386         switch (mode) {
6387         case LED_MODE_FRONT_PANEL_OFF:
6388         case LED_MODE_OFF:
6389                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0);
6390                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6391                        SHARED_HW_CFG_LED_MAC1);
6392
6393                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6394                 if (params->phy[EXT_PHY1].type ==
6395                         PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
6396                         tmp &= ~(EMAC_LED_1000MB_OVERRIDE |
6397                                 EMAC_LED_100MB_OVERRIDE |
6398                                 EMAC_LED_10MB_OVERRIDE);
6399                 else
6400                         tmp |= EMAC_LED_OVERRIDE;
6401
6402                 EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp);
6403                 break;
6404
6405         case LED_MODE_OPER:
6406                 /* For all other phys, OPER mode is same as ON, so in case
6407                  * link is down, do nothing
6408                  */
6409                 if (!vars->link_up)
6410                         break;
6411         case LED_MODE_ON:
6412                 if (((params->phy[EXT_PHY1].type ==
6413                           PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) ||
6414                          (params->phy[EXT_PHY1].type ==
6415                           PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) &&
6416                     CHIP_IS_E2(bp) && params->num_phys == 2) {
6417                         /* This is a work-around for E2+8727 Configurations */
6418                         if (mode == LED_MODE_ON ||
6419                                 speed == SPEED_10000){
6420                                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6421                                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
6422
6423                                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6424                                 EMAC_WR(bp, EMAC_REG_EMAC_LED,
6425                                         (tmp | EMAC_LED_OVERRIDE));
6426                                 /* Return here without enabling traffic
6427                                  * LED blink and setting rate in ON mode.
6428                                  * In oper mode, enabling LED blink
6429                                  * and setting rate is needed.
6430                                  */
6431                                 if (mode == LED_MODE_ON)
6432                                         return rc;
6433                         }
6434                 } else if (SINGLE_MEDIA_DIRECT(params)) {
6435                         /* This is a work-around for HW issue found when link
6436                          * is up in CL73
6437                          */
6438                         if ((!CHIP_IS_E3(bp)) ||
6439                             (CHIP_IS_E3(bp) &&
6440                              mode == LED_MODE_ON))
6441                                 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1);
6442
6443                         if (CHIP_IS_E1x(bp) ||
6444                             CHIP_IS_E2(bp) ||
6445                             (mode == LED_MODE_ON))
6446                                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6447                         else
6448                                 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6449                                        hw_led_mode);
6450                 } else if ((params->phy[EXT_PHY1].type ==
6451                             PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) &&
6452                            (mode == LED_MODE_ON)) {
6453                         REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6454                         tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6455                         EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp |
6456                                 EMAC_LED_OVERRIDE | EMAC_LED_1000MB_OVERRIDE);
6457                         /* Break here; otherwise, it'll disable the
6458                          * intended override.
6459                          */
6460                         break;
6461                 } else {
6462                         u32 nig_led_mode = ((params->hw_led_mode <<
6463                                              SHARED_HW_CFG_LED_MODE_SHIFT) ==
6464                                             SHARED_HW_CFG_LED_EXTPHY2) ?
6465                                 (SHARED_HW_CFG_LED_PHY1 >>
6466                                  SHARED_HW_CFG_LED_MODE_SHIFT) : hw_led_mode;
6467                         REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6468                                nig_led_mode);
6469                 }
6470
6471                 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0);
6472                 /* Set blinking rate to ~15.9Hz */
6473                 if (CHIP_IS_E3(bp))
6474                         REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
6475                                LED_BLINK_RATE_VAL_E3);
6476                 else
6477                         REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
6478                                LED_BLINK_RATE_VAL_E1X_E2);
6479                 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
6480                        port*4, 1);
6481                 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6482                 EMAC_WR(bp, EMAC_REG_EMAC_LED,
6483                         (tmp & (~EMAC_LED_OVERRIDE)));
6484
6485                 if (CHIP_IS_E1(bp) &&
6486                     ((speed == SPEED_2500) ||
6487                      (speed == SPEED_1000) ||
6488                      (speed == SPEED_100) ||
6489                      (speed == SPEED_10))) {
6490                         /* For speeds less than 10G LED scheme is different */
6491                         REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
6492                                + port*4, 1);
6493                         REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
6494                                port*4, 0);
6495                         REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
6496                                port*4, 1);
6497                 }
6498                 break;
6499
6500         default:
6501                 rc = -EINVAL;
6502                 DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n",
6503                          mode);
6504                 break;
6505         }
6506         return rc;
6507
6508 }
6509
6510 /* This function comes to reflect the actual link state read DIRECTLY from the
6511  * HW
6512  */
6513 int bnx2x_test_link(struct link_params *params, struct link_vars *vars,
6514                     u8 is_serdes)
6515 {
6516         struct bnx2x *bp = params->bp;
6517         u16 gp_status = 0, phy_index = 0;
6518         u8 ext_phy_link_up = 0, serdes_phy_type;
6519         struct link_vars temp_vars;
6520         struct bnx2x_phy *int_phy = &params->phy[INT_PHY];
6521
6522         if (CHIP_IS_E3(bp)) {
6523                 u16 link_up;
6524                 if (params->req_line_speed[LINK_CONFIG_IDX(INT_PHY)]
6525                     > SPEED_10000) {
6526                         /* Check 20G link */
6527                         bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6528                                         1, &link_up);
6529                         bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6530                                         1, &link_up);
6531                         link_up &= (1<<2);
6532                 } else {
6533                         /* Check 10G link and below*/
6534                         u8 lane = bnx2x_get_warpcore_lane(int_phy, params);
6535                         bnx2x_cl45_read(bp, int_phy, MDIO_WC_DEVAD,
6536                                         MDIO_WC_REG_GP2_STATUS_GP_2_1,
6537                                         &gp_status);
6538                         gp_status = ((gp_status >> 8) & 0xf) |
6539                                 ((gp_status >> 12) & 0xf);
6540                         link_up = gp_status & (1 << lane);
6541                 }
6542                 if (!link_up)
6543                         return -ESRCH;
6544         } else {
6545                 CL22_RD_OVER_CL45(bp, int_phy,
6546                           MDIO_REG_BANK_GP_STATUS,
6547                           MDIO_GP_STATUS_TOP_AN_STATUS1,
6548                           &gp_status);
6549         /* Link is up only if both local phy and external phy are up */
6550         if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS))
6551                 return -ESRCH;
6552         }
6553         /* In XGXS loopback mode, do not check external PHY */
6554         if (params->loopback_mode == LOOPBACK_XGXS)
6555                 return 0;
6556
6557         switch (params->num_phys) {
6558         case 1:
6559                 /* No external PHY */
6560                 return 0;
6561         case 2:
6562                 ext_phy_link_up = params->phy[EXT_PHY1].read_status(
6563                         &params->phy[EXT_PHY1],
6564                         params, &temp_vars);
6565                 break;
6566         case 3: /* Dual Media */
6567                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6568                       phy_index++) {
6569                         serdes_phy_type = ((params->phy[phy_index].media_type ==
6570                                             ETH_PHY_SFPP_10G_FIBER) ||
6571                                            (params->phy[phy_index].media_type ==
6572                                             ETH_PHY_SFP_1G_FIBER) ||
6573                                            (params->phy[phy_index].media_type ==
6574                                             ETH_PHY_XFP_FIBER) ||
6575                                            (params->phy[phy_index].media_type ==
6576                                             ETH_PHY_DA_TWINAX));
6577
6578                         if (is_serdes != serdes_phy_type)
6579                                 continue;
6580                         if (params->phy[phy_index].read_status) {
6581                                 ext_phy_link_up |=
6582                                         params->phy[phy_index].read_status(
6583                                                 &params->phy[phy_index],
6584                                                 params, &temp_vars);
6585                         }
6586                 }
6587                 break;
6588         }
6589         if (ext_phy_link_up)
6590                 return 0;
6591         return -ESRCH;
6592 }
6593
6594 static int bnx2x_link_initialize(struct link_params *params,
6595                                  struct link_vars *vars)
6596 {
6597         u8 phy_index, non_ext_phy;
6598         struct bnx2x *bp = params->bp;
6599         /* In case of external phy existence, the line speed would be the
6600          * line speed linked up by the external phy. In case it is direct
6601          * only, then the line_speed during initialization will be
6602          * equal to the req_line_speed
6603          */
6604         vars->line_speed = params->phy[INT_PHY].req_line_speed;
6605
6606         /* Initialize the internal phy in case this is a direct board
6607          * (no external phys), or this board has external phy which requires
6608          * to first.
6609          */
6610         if (!USES_WARPCORE(bp))
6611                 bnx2x_prepare_xgxs(&params->phy[INT_PHY], params, vars);
6612         /* init ext phy and enable link state int */
6613         non_ext_phy = (SINGLE_MEDIA_DIRECT(params) ||
6614                        (params->loopback_mode == LOOPBACK_XGXS));
6615
6616         if (non_ext_phy ||
6617             (params->phy[EXT_PHY1].flags & FLAGS_INIT_XGXS_FIRST) ||
6618             (params->loopback_mode == LOOPBACK_EXT_PHY)) {
6619                 struct bnx2x_phy *phy = &params->phy[INT_PHY];
6620                 if (vars->line_speed == SPEED_AUTO_NEG &&
6621                     (CHIP_IS_E1x(bp) ||
6622                      CHIP_IS_E2(bp)))
6623                         bnx2x_set_parallel_detection(phy, params);
6624                 if (params->phy[INT_PHY].config_init)
6625                         params->phy[INT_PHY].config_init(phy, params, vars);
6626         }
6627
6628         /* Re-read this value in case it was changed inside config_init due to
6629          * limitations of optic module
6630          */
6631         vars->line_speed = params->phy[INT_PHY].req_line_speed;
6632
6633         /* Init external phy*/
6634         if (non_ext_phy) {
6635                 if (params->phy[INT_PHY].supported &
6636                     SUPPORTED_FIBRE)
6637                         vars->link_status |= LINK_STATUS_SERDES_LINK;
6638         } else {
6639                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6640                       phy_index++) {
6641                         /* No need to initialize second phy in case of first
6642                          * phy only selection. In case of second phy, we do
6643                          * need to initialize the first phy, since they are
6644                          * connected.
6645                          */
6646                         if (params->phy[phy_index].supported &
6647                             SUPPORTED_FIBRE)
6648                                 vars->link_status |= LINK_STATUS_SERDES_LINK;
6649
6650                         if (phy_index == EXT_PHY2 &&
6651                             (bnx2x_phy_selection(params) ==
6652                              PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {
6653                                 DP(NETIF_MSG_LINK,
6654                                    "Not initializing second phy\n");
6655                                 continue;
6656                         }
6657                         params->phy[phy_index].config_init(
6658                                 &params->phy[phy_index],
6659                                 params, vars);
6660                 }
6661         }
6662         /* Reset the interrupt indication after phy was initialized */
6663         bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 +
6664                        params->port*4,
6665                        (NIG_STATUS_XGXS0_LINK10G |
6666                         NIG_STATUS_XGXS0_LINK_STATUS |
6667                         NIG_STATUS_SERDES0_LINK_STATUS |
6668                         NIG_MASK_MI_INT));
6669         return 0;
6670 }
6671
6672 static void bnx2x_int_link_reset(struct bnx2x_phy *phy,
6673                                  struct link_params *params)
6674 {
6675         /* Reset the SerDes/XGXS */
6676         REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
6677                (0x1ff << (params->port*16)));
6678 }
6679
6680 static void bnx2x_common_ext_link_reset(struct bnx2x_phy *phy,
6681                                         struct link_params *params)
6682 {
6683         struct bnx2x *bp = params->bp;
6684         u8 gpio_port;
6685         /* HW reset */
6686         if (CHIP_IS_E2(bp))
6687                 gpio_port = BP_PATH(bp);
6688         else
6689                 gpio_port = params->port;
6690         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
6691                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
6692                        gpio_port);
6693         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
6694                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
6695                        gpio_port);
6696         DP(NETIF_MSG_LINK, "reset external PHY\n");
6697 }
6698
6699 static int bnx2x_update_link_down(struct link_params *params,
6700                                   struct link_vars *vars)
6701 {
6702         struct bnx2x *bp = params->bp;
6703         u8 port = params->port;
6704
6705         DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
6706         bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
6707         vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG;
6708         /* Indicate no mac active */
6709         vars->mac_type = MAC_TYPE_NONE;
6710
6711         /* Update shared memory */
6712         vars->link_status &= ~LINK_UPDATE_MASK;
6713         vars->line_speed = 0;
6714         bnx2x_update_mng(params, vars->link_status);
6715
6716         /* Activate nig drain */
6717         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
6718
6719         /* Disable emac */
6720         if (!CHIP_IS_E3(bp))
6721                 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6722
6723         usleep_range(10000, 20000);
6724         /* Reset BigMac/Xmac */
6725         if (CHIP_IS_E1x(bp) ||
6726             CHIP_IS_E2(bp))
6727                 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0);
6728
6729         if (CHIP_IS_E3(bp)) {
6730                 /* Prevent LPI Generation by chip */
6731                 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2),
6732                        0);
6733                 REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 + (params->port << 2),
6734                        0);
6735                 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |
6736                                       SHMEM_EEE_ACTIVE_BIT);
6737
6738                 bnx2x_update_mng_eee(params, vars->eee_status);
6739                 bnx2x_set_xmac_rxtx(params, 0);
6740                 bnx2x_set_umac_rxtx(params, 0);
6741         }
6742
6743         return 0;
6744 }
6745
6746 static int bnx2x_update_link_up(struct link_params *params,
6747                                 struct link_vars *vars,
6748                                 u8 link_10g)
6749 {
6750         struct bnx2x *bp = params->bp;
6751         u8 phy_idx, port = params->port;
6752         int rc = 0;
6753
6754         vars->link_status |= (LINK_STATUS_LINK_UP |
6755                               LINK_STATUS_PHYSICAL_LINK_FLAG);
6756         vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
6757
6758         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_TX)
6759                 vars->link_status |=
6760                         LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
6761
6762         if (vars->flow_ctrl & BNX2X_FLOW_CTRL_RX)
6763                 vars->link_status |=
6764                         LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
6765         if (USES_WARPCORE(bp)) {
6766                 if (link_10g) {
6767                         if (bnx2x_xmac_enable(params, vars, 0) ==
6768                             -ESRCH) {
6769                                 DP(NETIF_MSG_LINK, "Found errors on XMAC\n");
6770                                 vars->link_up = 0;
6771                                 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6772                                 vars->link_status &= ~LINK_STATUS_LINK_UP;
6773                         }
6774                 } else
6775                         bnx2x_umac_enable(params, vars, 0);
6776                 bnx2x_set_led(params, vars,
6777                               LED_MODE_OPER, vars->line_speed);
6778
6779                 if ((vars->eee_status & SHMEM_EEE_ACTIVE_BIT) &&
6780                     (vars->eee_status & SHMEM_EEE_LPI_REQUESTED_BIT)) {
6781                         DP(NETIF_MSG_LINK, "Enabling LPI assertion\n");
6782                         REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 +
6783                                (params->port << 2), 1);
6784                         REG_WR(bp, MISC_REG_CPMU_LP_DR_ENABLE, 1);
6785                         REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 +
6786                                (params->port << 2), 0xfc20);
6787                 }
6788         }
6789         if ((CHIP_IS_E1x(bp) ||
6790              CHIP_IS_E2(bp))) {
6791                 if (link_10g) {
6792                         if (bnx2x_bmac_enable(params, vars, 0, 1) ==
6793                             -ESRCH) {
6794                                 DP(NETIF_MSG_LINK, "Found errors on BMAC\n");
6795                                 vars->link_up = 0;
6796                                 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
6797                                 vars->link_status &= ~LINK_STATUS_LINK_UP;
6798                         }
6799
6800                         bnx2x_set_led(params, vars,
6801                                       LED_MODE_OPER, SPEED_10000);
6802                 } else {
6803                         rc = bnx2x_emac_program(params, vars);
6804                         bnx2x_emac_enable(params, vars, 0);
6805
6806                         /* AN complete? */
6807                         if ((vars->link_status &
6808                              LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
6809                             && (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
6810                             SINGLE_MEDIA_DIRECT(params))
6811                                 bnx2x_set_gmii_tx_driver(params);
6812                 }
6813         }
6814
6815         /* PBF - link up */
6816         if (CHIP_IS_E1x(bp))
6817                 rc |= bnx2x_pbf_update(params, vars->flow_ctrl,
6818                                        vars->line_speed);
6819
6820         /* Disable drain */
6821         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
6822
6823         /* Update shared memory */
6824         bnx2x_update_mng(params, vars->link_status);
6825         bnx2x_update_mng_eee(params, vars->eee_status);
6826         /* Check remote fault */
6827         for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
6828                 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) {
6829                         bnx2x_check_half_open_conn(params, vars, 0);
6830                         break;
6831                 }
6832         }
6833         msleep(20);
6834         return rc;
6835 }
6836
6837 static void bnx2x_chng_link_count(struct link_params *params, bool clear)
6838 {
6839         struct bnx2x *bp = params->bp;
6840         u32 addr, val;
6841
6842         /* Verify the link_change_count is supported by the MFW */
6843         if (!(SHMEM2_HAS(bp, link_change_count)))
6844                 return;
6845
6846         addr = params->shmem2_base +
6847                 offsetof(struct shmem2_region, link_change_count[params->port]);
6848         if (clear)
6849                 val = 0;
6850         else
6851                 val = REG_RD(bp, addr) + 1;
6852         REG_WR(bp, addr, val);
6853 }
6854
6855 /* The bnx2x_link_update function should be called upon link
6856  * interrupt.
6857  * Link is considered up as follows:
6858  * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
6859  *   to be up
6860  * - SINGLE_MEDIA - The link between the 577xx and the external
6861  *   phy (XGXS) need to up as well as the external link of the
6862  *   phy (PHY_EXT1)
6863  * - DUAL_MEDIA - The link between the 577xx and the first
6864  *   external phy needs to be up, and at least one of the 2
6865  *   external phy link must be up.
6866  */
6867 int bnx2x_link_update(struct link_params *params, struct link_vars *vars)
6868 {
6869         struct bnx2x *bp = params->bp;
6870         struct link_vars phy_vars[MAX_PHYS];
6871         u8 port = params->port;
6872         u8 link_10g_plus, phy_index;
6873         u32 prev_link_status = vars->link_status;
6874         u8 ext_phy_link_up = 0, cur_link_up;
6875         int rc = 0;
6876         u8 is_mi_int = 0;
6877         u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;
6878         u8 active_external_phy = INT_PHY;
6879         vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
6880         vars->link_status &= ~LINK_UPDATE_MASK;
6881         for (phy_index = INT_PHY; phy_index < params->num_phys;
6882               phy_index++) {
6883                 phy_vars[phy_index].flow_ctrl = 0;
6884                 phy_vars[phy_index].link_status = 0;
6885                 phy_vars[phy_index].line_speed = 0;
6886                 phy_vars[phy_index].duplex = DUPLEX_FULL;
6887                 phy_vars[phy_index].phy_link_up = 0;
6888                 phy_vars[phy_index].link_up = 0;
6889                 phy_vars[phy_index].fault_detected = 0;
6890                 /* different consideration, since vars holds inner state */
6891                 phy_vars[phy_index].eee_status = vars->eee_status;
6892         }
6893
6894         if (USES_WARPCORE(bp))
6895                 bnx2x_set_aer_mmd(params, &params->phy[INT_PHY]);
6896
6897         DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n",
6898                  port, (vars->phy_flags & PHY_XGXS_FLAG),
6899                  REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
6900
6901         is_mi_int = (u8)(REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
6902                                 port*0x18) > 0);
6903         DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
6904                  REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6905                  is_mi_int,
6906                  REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
6907
6908         DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
6909           REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6910           REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6911
6912         /* Disable emac */
6913         if (!CHIP_IS_E3(bp))
6914                 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
6915
6916         /* Step 1:
6917          * Check external link change only for external phys, and apply
6918          * priority selection between them in case the link on both phys
6919          * is up. Note that instead of the common vars, a temporary
6920          * vars argument is used since each phy may have different link/
6921          * speed/duplex result
6922          */
6923         for (phy_index = EXT_PHY1; phy_index < params->num_phys;
6924               phy_index++) {
6925                 struct bnx2x_phy *phy = &params->phy[phy_index];
6926                 if (!phy->read_status)
6927                         continue;
6928                 /* Read link status and params of this ext phy */
6929                 cur_link_up = phy->read_status(phy, params,
6930                                                &phy_vars[phy_index]);
6931                 if (cur_link_up) {
6932                         DP(NETIF_MSG_LINK, "phy in index %d link is up\n",
6933                                    phy_index);
6934                 } else {
6935                         DP(NETIF_MSG_LINK, "phy in index %d link is down\n",
6936                                    phy_index);
6937                         continue;
6938                 }
6939
6940                 if (!ext_phy_link_up) {
6941                         ext_phy_link_up = 1;
6942                         active_external_phy = phy_index;
6943                 } else {
6944                         switch (bnx2x_phy_selection(params)) {
6945                         case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
6946                         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
6947                         /* In this option, the first PHY makes sure to pass the
6948                          * traffic through itself only.
6949                          * Its not clear how to reset the link on the second phy
6950                          */
6951                                 active_external_phy = EXT_PHY1;
6952                                 break;
6953                         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
6954                         /* In this option, the first PHY makes sure to pass the
6955                          * traffic through the second PHY.
6956                          */
6957                                 active_external_phy = EXT_PHY2;
6958                                 break;
6959                         default:
6960                         /* Link indication on both PHYs with the following cases
6961                          * is invalid:
6962                          * - FIRST_PHY means that second phy wasn't initialized,
6963                          * hence its link is expected to be down
6964                          * - SECOND_PHY means that first phy should not be able
6965                          * to link up by itself (using configuration)
6966                          * - DEFAULT should be overriden during initialiazation
6967                          */
6968                                 DP(NETIF_MSG_LINK, "Invalid link indication"
6969                                            "mpc=0x%x. DISABLING LINK !!!\n",
6970                                            params->multi_phy_config);
6971                                 ext_phy_link_up = 0;
6972                                 break;
6973                         }
6974                 }
6975         }
6976         prev_line_speed = vars->line_speed;
6977         /* Step 2:
6978          * Read the status of the internal phy. In case of
6979          * DIRECT_SINGLE_MEDIA board, this link is the external link,
6980          * otherwise this is the link between the 577xx and the first
6981          * external phy
6982          */
6983         if (params->phy[INT_PHY].read_status)
6984                 params->phy[INT_PHY].read_status(
6985                         &params->phy[INT_PHY],
6986                         params, vars);
6987         /* The INT_PHY flow control reside in the vars. This include the
6988          * case where the speed or flow control are not set to AUTO.
6989          * Otherwise, the active external phy flow control result is set
6990          * to the vars. The ext_phy_line_speed is needed to check if the
6991          * speed is different between the internal phy and external phy.
6992          * This case may be result of intermediate link speed change.
6993          */
6994         if (active_external_phy > INT_PHY) {
6995                 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl;
6996                 /* Link speed is taken from the XGXS. AN and FC result from
6997                  * the external phy.
6998                  */
6999                 vars->link_status |= phy_vars[active_external_phy].link_status;
7000
7001                 /* if active_external_phy is first PHY and link is up - disable
7002                  * disable TX on second external PHY
7003                  */
7004                 if (active_external_phy == EXT_PHY1) {
7005                         if (params->phy[EXT_PHY2].phy_specific_func) {
7006                                 DP(NETIF_MSG_LINK,
7007                                    "Disabling TX on EXT_PHY2\n");
7008                                 params->phy[EXT_PHY2].phy_specific_func(
7009                                         &params->phy[EXT_PHY2],
7010                                         params, DISABLE_TX);
7011                         }
7012                 }
7013
7014                 ext_phy_line_speed = phy_vars[active_external_phy].line_speed;
7015                 vars->duplex = phy_vars[active_external_phy].duplex;
7016                 if (params->phy[active_external_phy].supported &
7017                     SUPPORTED_FIBRE)
7018                         vars->link_status |= LINK_STATUS_SERDES_LINK;
7019                 else
7020                         vars->link_status &= ~LINK_STATUS_SERDES_LINK;
7021
7022                 vars->eee_status = phy_vars[active_external_phy].eee_status;
7023
7024                 DP(NETIF_MSG_LINK, "Active external phy selected: %x\n",
7025                            active_external_phy);
7026         }
7027
7028         for (phy_index = EXT_PHY1; phy_index < params->num_phys;
7029               phy_index++) {
7030                 if (params->phy[phy_index].flags &
7031                     FLAGS_REARM_LATCH_SIGNAL) {
7032                         bnx2x_rearm_latch_signal(bp, port,
7033                                                  phy_index ==
7034                                                  active_external_phy);
7035                         break;
7036                 }
7037         }
7038         DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
7039                    " ext_phy_line_speed = %d\n", vars->flow_ctrl,
7040                    vars->link_status, ext_phy_line_speed);
7041         /* Upon link speed change set the NIG into drain mode. Comes to
7042          * deals with possible FIFO glitch due to clk change when speed
7043          * is decreased without link down indicator
7044          */
7045
7046         if (vars->phy_link_up) {
7047                 if (!(SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&
7048                     (ext_phy_line_speed != vars->line_speed)) {
7049                         DP(NETIF_MSG_LINK, "Internal link speed %d is"
7050                                    " different than the external"
7051                                    " link speed %d\n", vars->line_speed,
7052                                    ext_phy_line_speed);
7053                         vars->phy_link_up = 0;
7054                 } else if (prev_line_speed != vars->line_speed) {
7055                         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4,
7056                                0);
7057                         usleep_range(1000, 2000);
7058                 }
7059         }
7060
7061         /* Anything 10 and over uses the bmac */
7062         link_10g_plus = (vars->line_speed >= SPEED_10000);
7063
7064         bnx2x_link_int_ack(params, vars, link_10g_plus);
7065
7066         /* In case external phy link is up, and internal link is down
7067          * (not initialized yet probably after link initialization, it
7068          * needs to be initialized.
7069          * Note that after link down-up as result of cable plug, the xgxs
7070          * link would probably become up again without the need
7071          * initialize it
7072          */
7073         if (!(SINGLE_MEDIA_DIRECT(params))) {
7074                 DP(NETIF_MSG_LINK, "ext_phy_link_up = %d, int_link_up = %d,"
7075                            " init_preceding = %d\n", ext_phy_link_up,
7076                            vars->phy_link_up,
7077                            params->phy[EXT_PHY1].flags &
7078                            FLAGS_INIT_XGXS_FIRST);
7079                 if (!(params->phy[EXT_PHY1].flags &
7080                       FLAGS_INIT_XGXS_FIRST)
7081                     && ext_phy_link_up && !vars->phy_link_up) {
7082                         vars->line_speed = ext_phy_line_speed;
7083                         if (vars->line_speed < SPEED_1000)
7084                                 vars->phy_flags |= PHY_SGMII_FLAG;
7085                         else
7086                                 vars->phy_flags &= ~PHY_SGMII_FLAG;
7087
7088                         if (params->phy[INT_PHY].config_init)
7089                                 params->phy[INT_PHY].config_init(
7090                                         &params->phy[INT_PHY], params,
7091                                                 vars);
7092                 }
7093         }
7094         /* Link is up only if both local phy and external phy (in case of
7095          * non-direct board) are up and no fault detected on active PHY.
7096          */
7097         vars->link_up = (vars->phy_link_up &&
7098                          (ext_phy_link_up ||
7099                           SINGLE_MEDIA_DIRECT(params)) &&
7100                          (phy_vars[active_external_phy].fault_detected == 0));
7101
7102         /* Update the PFC configuration in case it was changed */
7103         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
7104                 vars->link_status |= LINK_STATUS_PFC_ENABLED;
7105         else
7106                 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
7107
7108         if (vars->link_up)
7109                 rc = bnx2x_update_link_up(params, vars, link_10g_plus);
7110         else
7111                 rc = bnx2x_update_link_down(params, vars);
7112
7113         if ((prev_link_status ^ vars->link_status) & LINK_STATUS_LINK_UP)
7114                 bnx2x_chng_link_count(params, false);
7115
7116         /* Update MCP link status was changed */
7117         if (params->feature_config_flags & FEATURE_CONFIG_BC_SUPPORTS_AFEX)
7118                 bnx2x_fw_command(bp, DRV_MSG_CODE_LINK_STATUS_CHANGED, 0);
7119
7120         return rc;
7121 }
7122
7123 /*****************************************************************************/
7124 /*                          External Phy section                             */
7125 /*****************************************************************************/
7126 void bnx2x_ext_phy_hw_reset(struct bnx2x *bp, u8 port)
7127 {
7128         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
7129                        MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
7130         usleep_range(1000, 2000);
7131         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
7132                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
7133 }
7134
7135 static void bnx2x_save_spirom_version(struct bnx2x *bp, u8 port,
7136                                       u32 spirom_ver, u32 ver_addr)
7137 {
7138         DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n",
7139                  (u16)(spirom_ver>>16), (u16)spirom_ver, port);
7140
7141         if (ver_addr)
7142                 REG_WR(bp, ver_addr, spirom_ver);
7143 }
7144
7145 static void bnx2x_save_bcm_spirom_ver(struct bnx2x *bp,
7146                                       struct bnx2x_phy *phy,
7147                                       u8 port)
7148 {
7149         u16 fw_ver1, fw_ver2;
7150
7151         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
7152                         MDIO_PMA_REG_ROM_VER1, &fw_ver1);
7153         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
7154                         MDIO_PMA_REG_ROM_VER2, &fw_ver2);
7155         bnx2x_save_spirom_version(bp, port, (u32)(fw_ver1<<16 | fw_ver2),
7156                                   phy->ver_addr);
7157 }
7158
7159 static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x *bp,
7160                                        struct bnx2x_phy *phy,
7161                                        struct link_vars *vars)
7162 {
7163         u16 val;
7164         bnx2x_cl45_read(bp, phy,
7165                         MDIO_AN_DEVAD,
7166                         MDIO_AN_REG_STATUS, &val);
7167         bnx2x_cl45_read(bp, phy,
7168                         MDIO_AN_DEVAD,
7169                         MDIO_AN_REG_STATUS, &val);
7170         if (val & (1<<5))
7171                 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
7172         if ((val & (1<<0)) == 0)
7173                 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
7174 }
7175
7176 /******************************************************************/
7177 /*              common BCM8073/BCM8727 PHY SECTION                */
7178 /******************************************************************/
7179 static void bnx2x_8073_resolve_fc(struct bnx2x_phy *phy,
7180                                   struct link_params *params,
7181                                   struct link_vars *vars)
7182 {
7183         struct bnx2x *bp = params->bp;
7184         if (phy->req_line_speed == SPEED_10 ||
7185             phy->req_line_speed == SPEED_100) {
7186                 vars->flow_ctrl = phy->req_flow_ctrl;
7187                 return;
7188         }
7189
7190         if (bnx2x_ext_phy_resolve_fc(phy, params, vars) &&
7191             (vars->flow_ctrl == BNX2X_FLOW_CTRL_NONE)) {
7192                 u16 pause_result;
7193                 u16 ld_pause;           /* local */
7194                 u16 lp_pause;           /* link partner */
7195                 bnx2x_cl45_read(bp, phy,
7196                                 MDIO_AN_DEVAD,
7197                                 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
7198
7199                 bnx2x_cl45_read(bp, phy,
7200                                 MDIO_AN_DEVAD,
7201                                 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
7202                 pause_result = (ld_pause &
7203                                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
7204                 pause_result |= (lp_pause &
7205                                  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
7206
7207                 bnx2x_pause_resolve(phy, params, vars, pause_result);
7208                 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n",
7209                            pause_result);
7210         }
7211 }
7212 static int bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp,
7213                                              struct bnx2x_phy *phy,
7214                                              u8 port)
7215 {
7216         u32 count = 0;
7217         u16 fw_ver1, fw_msgout;
7218         int rc = 0;
7219
7220         /* Boot port from external ROM  */
7221         /* EDC grst */
7222         bnx2x_cl45_write(bp, phy,
7223                          MDIO_PMA_DEVAD,
7224                          MDIO_PMA_REG_GEN_CTRL,
7225                          0x0001);
7226
7227         /* Ucode reboot and rst */
7228         bnx2x_cl45_write(bp, phy,
7229                          MDIO_PMA_DEVAD,
7230                          MDIO_PMA_REG_GEN_CTRL,
7231                          0x008c);
7232
7233         bnx2x_cl45_write(bp, phy,
7234                          MDIO_PMA_DEVAD,
7235                          MDIO_PMA_REG_MISC_CTRL1, 0x0001);
7236
7237         /* Reset internal microprocessor */
7238         bnx2x_cl45_write(bp, phy,
7239                          MDIO_PMA_DEVAD,
7240                          MDIO_PMA_REG_GEN_CTRL,
7241                          MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
7242
7243         /* Release srst bit */
7244         bnx2x_cl45_write(bp, phy,
7245                          MDIO_PMA_DEVAD,
7246                          MDIO_PMA_REG_GEN_CTRL,
7247                          MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
7248
7249         /* Delay 100ms per the PHY specifications */
7250         msleep(100);
7251
7252         /* 8073 sometimes taking longer to download */
7253         do {
7254                 count++;
7255                 if (count > 300) {
7256                         DP(NETIF_MSG_LINK,
7257                                  "bnx2x_8073_8727_external_rom_boot port %x:"
7258                                  "Download failed. fw version = 0x%x\n",
7259                                  port, fw_ver1);
7260                         rc = -EINVAL;
7261                         break;
7262                 }
7263
7264                 bnx2x_cl45_read(bp, phy,
7265                                 MDIO_PMA_DEVAD,
7266                                 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
7267                 bnx2x_cl45_read(bp, phy,
7268                                 MDIO_PMA_DEVAD,
7269                                 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout);
7270
7271                 usleep_range(1000, 2000);
7272         } while (fw_ver1 == 0 || fw_ver1 == 0x4321 ||
7273                         ((fw_msgout & 0xff) != 0x03 && (phy->type ==
7274                         PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)));
7275
7276         /* Clear ser_boot_ctl bit */
7277         bnx2x_cl45_write(bp, phy,
7278                          MDIO_PMA_DEVAD,
7279                          MDIO_PMA_REG_MISC_CTRL1, 0x0000);
7280         bnx2x_save_bcm_spirom_ver(bp, phy, port);
7281
7282         DP(NETIF_MSG_LINK,
7283                  "bnx2x_8073_8727_external_rom_boot port %x:"
7284                  "Download complete. fw version = 0x%x\n",
7285                  port, fw_ver1);
7286
7287         return rc;
7288 }
7289
7290 /******************************************************************/
7291 /*                      BCM8073 PHY SECTION                       */
7292 /******************************************************************/
7293 static int bnx2x_8073_is_snr_needed(struct bnx2x *bp, struct bnx2x_phy *phy)
7294 {
7295         /* This is only required for 8073A1, version 102 only */
7296         u16 val;
7297
7298         /* Read 8073 HW revision*/
7299         bnx2x_cl45_read(bp, phy,
7300                         MDIO_PMA_DEVAD,
7301                         MDIO_PMA_REG_8073_CHIP_REV, &val);
7302
7303         if (val != 1) {
7304                 /* No need to workaround in 8073 A1 */
7305                 return 0;
7306         }
7307
7308         bnx2x_cl45_read(bp, phy,
7309                         MDIO_PMA_DEVAD,
7310                         MDIO_PMA_REG_ROM_VER2, &val);
7311
7312         /* SNR should be applied only for version 0x102 */
7313         if (val != 0x102)
7314                 return 0;
7315
7316         return 1;
7317 }
7318
7319 static int bnx2x_8073_xaui_wa(struct bnx2x *bp, struct bnx2x_phy *phy)
7320 {
7321         u16 val, cnt, cnt1 ;
7322
7323         bnx2x_cl45_read(bp, phy,
7324                         MDIO_PMA_DEVAD,
7325                         MDIO_PMA_REG_8073_CHIP_REV, &val);
7326
7327         if (val > 0) {
7328                 /* No need to workaround in 8073 A1 */
7329                 return 0;
7330         }
7331         /* XAUI workaround in 8073 A0: */
7332
7333         /* After loading the boot ROM and restarting Autoneg, poll
7334          * Dev1, Reg $C820:
7335          */
7336
7337         for (cnt = 0; cnt < 1000; cnt++) {
7338                 bnx2x_cl45_read(bp, phy,
7339                                 MDIO_PMA_DEVAD,
7340                                 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7341                                 &val);
7342                   /* If bit [14] = 0 or bit [13] = 0, continue on with
7343                    * system initialization (XAUI work-around not required, as
7344                    * these bits indicate 2.5G or 1G link up).
7345                    */
7346                 if (!(val & (1<<14)) || !(val & (1<<13))) {
7347                         DP(NETIF_MSG_LINK, "XAUI work-around not required\n");
7348                         return 0;
7349                 } else if (!(val & (1<<15))) {
7350                         DP(NETIF_MSG_LINK, "bit 15 went off\n");
7351                         /* If bit 15 is 0, then poll Dev1, Reg $C841 until it's
7352                          * MSB (bit15) goes to 1 (indicating that the XAUI
7353                          * workaround has completed), then continue on with
7354                          * system initialization.
7355                          */
7356                         for (cnt1 = 0; cnt1 < 1000; cnt1++) {
7357                                 bnx2x_cl45_read(bp, phy,
7358                                         MDIO_PMA_DEVAD,
7359                                         MDIO_PMA_REG_8073_XAUI_WA, &val);
7360                                 if (val & (1<<15)) {
7361                                         DP(NETIF_MSG_LINK,
7362                                           "XAUI workaround has completed\n");
7363                                         return 0;
7364                                  }
7365                                  usleep_range(3000, 6000);
7366                         }
7367                         break;
7368                 }
7369                 usleep_range(3000, 6000);
7370         }
7371         DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n");
7372         return -EINVAL;
7373 }
7374
7375 static void bnx2x_807x_force_10G(struct bnx2x *bp, struct bnx2x_phy *phy)
7376 {
7377         /* Force KR or KX */
7378         bnx2x_cl45_write(bp, phy,
7379                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
7380         bnx2x_cl45_write(bp, phy,
7381                          MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);
7382         bnx2x_cl45_write(bp, phy,
7383                          MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000);
7384         bnx2x_cl45_write(bp, phy,
7385                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
7386 }
7387
7388 static void bnx2x_8073_set_pause_cl37(struct link_params *params,
7389                                       struct bnx2x_phy *phy,
7390                                       struct link_vars *vars)
7391 {
7392         u16 cl37_val;
7393         struct bnx2x *bp = params->bp;
7394         bnx2x_cl45_read(bp, phy,
7395                         MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val);
7396
7397         cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
7398         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
7399         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
7400         if ((vars->ieee_fc &
7401             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
7402             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
7403                 cl37_val |=  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
7404         }
7405         if ((vars->ieee_fc &
7406             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
7407             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
7408                 cl37_val |=  MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
7409         }
7410         if ((vars->ieee_fc &
7411             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
7412             MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
7413                 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
7414         }
7415         DP(NETIF_MSG_LINK,
7416                  "Ext phy AN advertize cl37 0x%x\n", cl37_val);
7417
7418         bnx2x_cl45_write(bp, phy,
7419                          MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);
7420         msleep(500);
7421 }
7422
7423 static void bnx2x_8073_specific_func(struct bnx2x_phy *phy,
7424                                      struct link_params *params,
7425                                      u32 action)
7426 {
7427         struct bnx2x *bp = params->bp;
7428         switch (action) {
7429         case PHY_INIT:
7430                 /* Enable LASI */
7431                 bnx2x_cl45_write(bp, phy,
7432                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, (1<<2));
7433                 bnx2x_cl45_write(bp, phy,
7434                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,  0x0004);
7435                 break;
7436         }
7437 }
7438
7439 static int bnx2x_8073_config_init(struct bnx2x_phy *phy,
7440                                   struct link_params *params,
7441                                   struct link_vars *vars)
7442 {
7443         struct bnx2x *bp = params->bp;
7444         u16 val = 0, tmp1;
7445         u8 gpio_port;
7446         DP(NETIF_MSG_LINK, "Init 8073\n");
7447
7448         if (CHIP_IS_E2(bp))
7449                 gpio_port = BP_PATH(bp);
7450         else
7451                 gpio_port = params->port;
7452         /* Restore normal power mode*/
7453         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7454                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
7455
7456         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
7457                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
7458
7459         bnx2x_8073_specific_func(phy, params, PHY_INIT);
7460         bnx2x_8073_set_pause_cl37(params, phy, vars);
7461
7462         bnx2x_cl45_read(bp, phy,
7463                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
7464
7465         bnx2x_cl45_read(bp, phy,
7466                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
7467
7468         DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1);
7469
7470         /* Swap polarity if required - Must be done only in non-1G mode */
7471         if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7472                 /* Configure the 8073 to swap _P and _N of the KR lines */
7473                 DP(NETIF_MSG_LINK, "Swapping polarity for the 8073\n");
7474                 /* 10G Rx/Tx and 1G Tx signal polarity swap */
7475                 bnx2x_cl45_read(bp, phy,
7476                                 MDIO_PMA_DEVAD,
7477                                 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val);
7478                 bnx2x_cl45_write(bp, phy,
7479                                  MDIO_PMA_DEVAD,
7480                                  MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL,
7481                                  (val | (3<<9)));
7482         }
7483
7484
7485         /* Enable CL37 BAM */
7486         if (REG_RD(bp, params->shmem_base +
7487                          offsetof(struct shmem_region, dev_info.
7488                                   port_hw_config[params->port].default_cfg)) &
7489             PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
7490
7491                 bnx2x_cl45_read(bp, phy,
7492                                 MDIO_AN_DEVAD,
7493                                 MDIO_AN_REG_8073_BAM, &val);
7494                 bnx2x_cl45_write(bp, phy,
7495                                  MDIO_AN_DEVAD,
7496                                  MDIO_AN_REG_8073_BAM, val | 1);
7497                 DP(NETIF_MSG_LINK, "Enable CL37 BAM on KR\n");
7498         }
7499         if (params->loopback_mode == LOOPBACK_EXT) {
7500                 bnx2x_807x_force_10G(bp, phy);
7501                 DP(NETIF_MSG_LINK, "Forced speed 10G on 807X\n");
7502                 return 0;
7503         } else {
7504                 bnx2x_cl45_write(bp, phy,
7505                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002);
7506         }
7507         if (phy->req_line_speed != SPEED_AUTO_NEG) {
7508                 if (phy->req_line_speed == SPEED_10000) {
7509                         val = (1<<7);
7510                 } else if (phy->req_line_speed ==  SPEED_2500) {
7511                         val = (1<<5);
7512                         /* Note that 2.5G works only when used with 1G
7513                          * advertisement
7514                          */
7515                 } else
7516                         val = (1<<5);
7517         } else {
7518                 val = 0;
7519                 if (phy->speed_cap_mask &
7520                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
7521                         val |= (1<<7);
7522
7523                 /* Note that 2.5G works only when used with 1G advertisement */
7524                 if (phy->speed_cap_mask &
7525                         (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
7526                          PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
7527                         val |= (1<<5);
7528                 DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val);
7529         }
7530
7531         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
7532         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);
7533
7534         if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
7535              (phy->req_line_speed == SPEED_AUTO_NEG)) ||
7536             (phy->req_line_speed == SPEED_2500)) {
7537                 u16 phy_ver;
7538                 /* Allow 2.5G for A1 and above */
7539                 bnx2x_cl45_read(bp, phy,
7540                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,
7541                                 &phy_ver);
7542                 DP(NETIF_MSG_LINK, "Add 2.5G\n");
7543                 if (phy_ver > 0)
7544                         tmp1 |= 1;
7545                 else
7546                         tmp1 &= 0xfffe;
7547         } else {
7548                 DP(NETIF_MSG_LINK, "Disable 2.5G\n");
7549                 tmp1 &= 0xfffe;
7550         }
7551
7552         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);
7553         /* Add support for CL37 (passive mode) II */
7554
7555         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);
7556         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,
7557                          (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?
7558                                   0x20 : 0x40)));
7559
7560         /* Add support for CL37 (passive mode) III */
7561         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
7562
7563         /* The SNR will improve about 2db by changing BW and FEE main
7564          * tap. Rest commands are executed after link is up
7565          * Change FFE main cursor to 5 in EDC register
7566          */
7567         if (bnx2x_8073_is_snr_needed(bp, phy))
7568                 bnx2x_cl45_write(bp, phy,
7569                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN,
7570                                  0xFB0C);
7571
7572         /* Enable FEC (Forware Error Correction) Request in the AN */
7573         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);
7574         tmp1 |= (1<<15);
7575         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);
7576
7577         bnx2x_ext_phy_set_pause(params, phy, vars);
7578
7579         /* Restart autoneg */
7580         msleep(500);
7581         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
7582         DP(NETIF_MSG_LINK, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n",
7583                    ((val & (1<<5)) > 0), ((val & (1<<7)) > 0));
7584         return 0;
7585 }
7586
7587 static u8 bnx2x_8073_read_status(struct bnx2x_phy *phy,
7588                                  struct link_params *params,
7589                                  struct link_vars *vars)
7590 {
7591         struct bnx2x *bp = params->bp;
7592         u8 link_up = 0;
7593         u16 val1, val2;
7594         u16 link_status = 0;
7595         u16 an1000_status = 0;
7596
7597         bnx2x_cl45_read(bp, phy,
7598                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
7599
7600         DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1);
7601
7602         /* Clear the interrupt LASI status register */
7603         bnx2x_cl45_read(bp, phy,
7604                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7605         bnx2x_cl45_read(bp, phy,
7606                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
7607         DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1);
7608         /* Clear MSG-OUT */
7609         bnx2x_cl45_read(bp, phy,
7610                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
7611
7612         /* Check the LASI */
7613         bnx2x_cl45_read(bp, phy,
7614                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
7615
7616         DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2);
7617
7618         /* Check the link status */
7619         bnx2x_cl45_read(bp, phy,
7620                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
7621         DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);
7622
7623         bnx2x_cl45_read(bp, phy,
7624                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7625         bnx2x_cl45_read(bp, phy,
7626                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7627         link_up = ((val1 & 4) == 4);
7628         DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1);
7629
7630         if (link_up &&
7631              ((phy->req_line_speed != SPEED_10000))) {
7632                 if (bnx2x_8073_xaui_wa(bp, phy) != 0)
7633                         return 0;
7634         }
7635         bnx2x_cl45_read(bp, phy,
7636                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7637         bnx2x_cl45_read(bp, phy,
7638                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
7639
7640         /* Check the link status on 1.1.2 */
7641         bnx2x_cl45_read(bp, phy,
7642                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
7643         bnx2x_cl45_read(bp, phy,
7644                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
7645         DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x,"
7646                    "an_link_status=0x%x\n", val2, val1, an1000_status);
7647
7648         link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1)));
7649         if (link_up && bnx2x_8073_is_snr_needed(bp, phy)) {
7650                 /* The SNR will improve about 2dbby changing the BW and FEE main
7651                  * tap. The 1st write to change FFE main tap is set before
7652                  * restart AN. Change PLL Bandwidth in EDC register
7653                  */
7654                 bnx2x_cl45_write(bp, phy,
7655                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH,
7656                                  0x26BC);
7657
7658                 /* Change CDR Bandwidth in EDC register */
7659                 bnx2x_cl45_write(bp, phy,
7660                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH,
7661                                  0x0333);
7662         }
7663         bnx2x_cl45_read(bp, phy,
7664                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
7665                         &link_status);
7666
7667         /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
7668         if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
7669                 link_up = 1;
7670                 vars->line_speed = SPEED_10000;
7671                 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
7672                            params->port);
7673         } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) {
7674                 link_up = 1;
7675                 vars->line_speed = SPEED_2500;
7676                 DP(NETIF_MSG_LINK, "port %x: External link up in 2.5G\n",
7677                            params->port);
7678         } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
7679                 link_up = 1;
7680                 vars->line_speed = SPEED_1000;
7681                 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
7682                            params->port);
7683         } else {
7684                 link_up = 0;
7685                 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
7686                            params->port);
7687         }
7688
7689         if (link_up) {
7690                 /* Swap polarity if required */
7691                 if (params->lane_config &
7692                     PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
7693                         /* Configure the 8073 to swap P and N of the KR lines */
7694                         bnx2x_cl45_read(bp, phy,
7695                                         MDIO_XS_DEVAD,
7696                                         MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1);
7697                         /* Set bit 3 to invert Rx in 1G mode and clear this bit
7698                          * when it`s in 10G mode.
7699                          */
7700                         if (vars->line_speed == SPEED_1000) {
7701                                 DP(NETIF_MSG_LINK, "Swapping 1G polarity for"
7702                                               "the 8073\n");
7703                                 val1 |= (1<<3);
7704                         } else
7705                                 val1 &= ~(1<<3);
7706
7707                         bnx2x_cl45_write(bp, phy,
7708                                          MDIO_XS_DEVAD,
7709                                          MDIO_XS_REG_8073_RX_CTRL_PCIE,
7710                                          val1);
7711                 }
7712                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
7713                 bnx2x_8073_resolve_fc(phy, params, vars);
7714                 vars->duplex = DUPLEX_FULL;
7715         }
7716
7717         if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
7718                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
7719                                 MDIO_AN_REG_LP_AUTO_NEG2, &val1);
7720
7721                 if (val1 & (1<<5))
7722                         vars->link_status |=
7723                                 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
7724                 if (val1 & (1<<7))
7725                         vars->link_status |=
7726                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
7727         }
7728
7729         return link_up;
7730 }
7731
7732 static void bnx2x_8073_link_reset(struct bnx2x_phy *phy,
7733                                   struct link_params *params)
7734 {
7735         struct bnx2x *bp = params->bp;
7736         u8 gpio_port;
7737         if (CHIP_IS_E2(bp))
7738                 gpio_port = BP_PATH(bp);
7739         else
7740                 gpio_port = params->port;
7741         DP(NETIF_MSG_LINK, "Setting 8073 port %d into low power mode\n",
7742            gpio_port);
7743         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7744                        MISC_REGISTERS_GPIO_OUTPUT_LOW,
7745                        gpio_port);
7746 }
7747
7748 /******************************************************************/
7749 /*                      BCM8705 PHY SECTION                       */
7750 /******************************************************************/
7751 static int bnx2x_8705_config_init(struct bnx2x_phy *phy,
7752                                   struct link_params *params,
7753                                   struct link_vars *vars)
7754 {
7755         struct bnx2x *bp = params->bp;
7756         DP(NETIF_MSG_LINK, "init 8705\n");
7757         /* Restore normal power mode*/
7758         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
7759                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
7760         /* HW reset */
7761         bnx2x_ext_phy_hw_reset(bp, params->port);
7762         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
7763         bnx2x_wait_reset_complete(bp, phy, params);
7764
7765         bnx2x_cl45_write(bp, phy,
7766                          MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288);
7767         bnx2x_cl45_write(bp, phy,
7768                          MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);
7769         bnx2x_cl45_write(bp, phy,
7770                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);
7771         bnx2x_cl45_write(bp, phy,
7772                          MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
7773         /* BCM8705 doesn't have microcode, hence the 0 */
7774         bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0);
7775         return 0;
7776 }
7777
7778 static u8 bnx2x_8705_read_status(struct bnx2x_phy *phy,
7779                                  struct link_params *params,
7780                                  struct link_vars *vars)
7781 {
7782         u8 link_up = 0;
7783         u16 val1, rx_sd;
7784         struct bnx2x *bp = params->bp;
7785         DP(NETIF_MSG_LINK, "read status 8705\n");
7786         bnx2x_cl45_read(bp, phy,
7787                       MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7788         DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7789
7790         bnx2x_cl45_read(bp, phy,
7791                       MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
7792         DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
7793
7794         bnx2x_cl45_read(bp, phy,
7795                       MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
7796
7797         bnx2x_cl45_read(bp, phy,
7798                       MDIO_PMA_DEVAD, 0xc809, &val1);
7799         bnx2x_cl45_read(bp, phy,
7800                       MDIO_PMA_DEVAD, 0xc809, &val1);
7801
7802         DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1);
7803         link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0));
7804         if (link_up) {
7805                 vars->line_speed = SPEED_10000;
7806                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
7807         }
7808         return link_up;
7809 }
7810
7811 /******************************************************************/
7812 /*                      SFP+ module Section                       */
7813 /******************************************************************/
7814 static void bnx2x_set_disable_pmd_transmit(struct link_params *params,
7815                                            struct bnx2x_phy *phy,
7816                                            u8 pmd_dis)
7817 {
7818         struct bnx2x *bp = params->bp;
7819         /* Disable transmitter only for bootcodes which can enable it afterwards
7820          * (for D3 link)
7821          */
7822         if (pmd_dis) {
7823                 if (params->feature_config_flags &
7824                      FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED)
7825                         DP(NETIF_MSG_LINK, "Disabling PMD transmitter\n");
7826                 else {
7827                         DP(NETIF_MSG_LINK, "NOT disabling PMD transmitter\n");
7828                         return;
7829                 }
7830         } else
7831                 DP(NETIF_MSG_LINK, "Enabling PMD transmitter\n");
7832         bnx2x_cl45_write(bp, phy,
7833                          MDIO_PMA_DEVAD,
7834                          MDIO_PMA_REG_TX_DISABLE, pmd_dis);
7835 }
7836
7837 static u8 bnx2x_get_gpio_port(struct link_params *params)
7838 {
7839         u8 gpio_port;
7840         u32 swap_val, swap_override;
7841         struct bnx2x *bp = params->bp;
7842         if (CHIP_IS_E2(bp))
7843                 gpio_port = BP_PATH(bp);
7844         else
7845                 gpio_port = params->port;
7846         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
7847         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
7848         return gpio_port ^ (swap_val && swap_override);
7849 }
7850
7851 static void bnx2x_sfp_e1e2_set_transmitter(struct link_params *params,
7852                                            struct bnx2x_phy *phy,
7853                                            u8 tx_en)
7854 {
7855         u16 val;
7856         u8 port = params->port;
7857         struct bnx2x *bp = params->bp;
7858         u32 tx_en_mode;
7859
7860         /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
7861         tx_en_mode = REG_RD(bp, params->shmem_base +
7862                             offsetof(struct shmem_region,
7863                                      dev_info.port_hw_config[port].sfp_ctrl)) &
7864                 PORT_HW_CFG_TX_LASER_MASK;
7865         DP(NETIF_MSG_LINK, "Setting transmitter tx_en=%x for port %x "
7866                            "mode = %x\n", tx_en, port, tx_en_mode);
7867         switch (tx_en_mode) {
7868         case PORT_HW_CFG_TX_LASER_MDIO:
7869
7870                 bnx2x_cl45_read(bp, phy,
7871                                 MDIO_PMA_DEVAD,
7872                                 MDIO_PMA_REG_PHY_IDENTIFIER,
7873                                 &val);
7874
7875                 if (tx_en)
7876                         val &= ~(1<<15);
7877                 else
7878                         val |= (1<<15);
7879
7880                 bnx2x_cl45_write(bp, phy,
7881                                  MDIO_PMA_DEVAD,
7882                                  MDIO_PMA_REG_PHY_IDENTIFIER,
7883                                  val);
7884         break;
7885         case PORT_HW_CFG_TX_LASER_GPIO0:
7886         case PORT_HW_CFG_TX_LASER_GPIO1:
7887         case PORT_HW_CFG_TX_LASER_GPIO2:
7888         case PORT_HW_CFG_TX_LASER_GPIO3:
7889         {
7890                 u16 gpio_pin;
7891                 u8 gpio_port, gpio_mode;
7892                 if (tx_en)
7893                         gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH;
7894                 else
7895                         gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW;
7896
7897                 gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0;
7898                 gpio_port = bnx2x_get_gpio_port(params);
7899                 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
7900                 break;
7901         }
7902         default:
7903                 DP(NETIF_MSG_LINK, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode);
7904                 break;
7905         }
7906 }
7907
7908 static void bnx2x_sfp_set_transmitter(struct link_params *params,
7909                                       struct bnx2x_phy *phy,
7910                                       u8 tx_en)
7911 {
7912         struct bnx2x *bp = params->bp;
7913         DP(NETIF_MSG_LINK, "Setting SFP+ transmitter to %d\n", tx_en);
7914         if (CHIP_IS_E3(bp))
7915                 bnx2x_sfp_e3_set_transmitter(params, phy, tx_en);
7916         else
7917                 bnx2x_sfp_e1e2_set_transmitter(params, phy, tx_en);
7918 }
7919
7920 static int bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy *phy,
7921                                              struct link_params *params,
7922                                              u8 dev_addr, u16 addr, u8 byte_cnt,
7923                                              u8 *o_buf, u8 is_init)
7924 {
7925         struct bnx2x *bp = params->bp;
7926         u16 val = 0;
7927         u16 i;
7928         if (byte_cnt > SFP_EEPROM_PAGE_SIZE) {
7929                 DP(NETIF_MSG_LINK,
7930                    "Reading from eeprom is limited to 0xf\n");
7931                 return -EINVAL;
7932         }
7933         /* Set the read command byte count */
7934         bnx2x_cl45_write(bp, phy,
7935                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
7936                          (byte_cnt | (dev_addr << 8)));
7937
7938         /* Set the read command address */
7939         bnx2x_cl45_write(bp, phy,
7940                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
7941                          addr);
7942
7943         /* Activate read command */
7944         bnx2x_cl45_write(bp, phy,
7945                          MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
7946                          0x2c0f);
7947
7948         /* Wait up to 500us for command complete status */
7949         for (i = 0; i < 100; i++) {
7950                 bnx2x_cl45_read(bp, phy,
7951                                 MDIO_PMA_DEVAD,
7952                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7953                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7954                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
7955                         break;
7956                 udelay(5);
7957         }
7958
7959         if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
7960                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
7961                 DP(NETIF_MSG_LINK,
7962                          "Got bad status 0x%x when reading from SFP+ EEPROM\n",
7963                          (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
7964                 return -EINVAL;
7965         }
7966
7967         /* Read the buffer */
7968         for (i = 0; i < byte_cnt; i++) {
7969                 bnx2x_cl45_read(bp, phy,
7970                                 MDIO_PMA_DEVAD,
7971                                 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
7972                 o_buf[i] = (u8)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
7973         }
7974
7975         for (i = 0; i < 100; i++) {
7976                 bnx2x_cl45_read(bp, phy,
7977                                 MDIO_PMA_DEVAD,
7978                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
7979                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
7980                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
7981                         return 0;
7982                 usleep_range(1000, 2000);
7983         }
7984         return -EINVAL;
7985 }
7986
7987 static void bnx2x_warpcore_power_module(struct link_params *params,
7988                                         u8 power)
7989 {
7990         u32 pin_cfg;
7991         struct bnx2x *bp = params->bp;
7992
7993         pin_cfg = (REG_RD(bp, params->shmem_base +
7994                           offsetof(struct shmem_region,
7995                         dev_info.port_hw_config[params->port].e3_sfp_ctrl)) &
7996                         PORT_HW_CFG_E3_PWR_DIS_MASK) >>
7997                         PORT_HW_CFG_E3_PWR_DIS_SHIFT;
7998
7999         if (pin_cfg == PIN_CFG_NA)
8000                 return;
8001         DP(NETIF_MSG_LINK, "Setting SFP+ module power to %d using pin cfg %d\n",
8002                        power, pin_cfg);
8003         /* Low ==> corresponding SFP+ module is powered
8004          * high ==> the SFP+ module is powered down
8005          */
8006         bnx2x_set_cfg_pin(bp, pin_cfg, power ^ 1);
8007 }
8008 static int bnx2x_warpcore_read_sfp_module_eeprom(struct bnx2x_phy *phy,
8009                                                  struct link_params *params,
8010                                                  u8 dev_addr,
8011                                                  u16 addr, u8 byte_cnt,
8012                                                  u8 *o_buf, u8 is_init)
8013 {
8014         int rc = 0;
8015         u8 i, j = 0, cnt = 0;
8016         u32 data_array[4];
8017         u16 addr32;
8018         struct bnx2x *bp = params->bp;
8019
8020         if (byte_cnt > SFP_EEPROM_PAGE_SIZE) {
8021                 DP(NETIF_MSG_LINK,
8022                    "Reading from eeprom is limited to 16 bytes\n");
8023                 return -EINVAL;
8024         }
8025
8026         /* 4 byte aligned address */
8027         addr32 = addr & (~0x3);
8028         do {
8029                 if ((!is_init) && (cnt == I2C_WA_PWR_ITER)) {
8030                         bnx2x_warpcore_power_module(params, 0);
8031                         /* Note that 100us are not enough here */
8032                         usleep_range(1000, 2000);
8033                         bnx2x_warpcore_power_module(params, 1);
8034                 }
8035                 rc = bnx2x_bsc_read(params, bp, dev_addr, addr32, 0, byte_cnt,
8036                                     data_array);
8037         } while ((rc != 0) && (++cnt < I2C_WA_RETRY_CNT));
8038
8039         if (rc == 0) {
8040                 for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) {
8041                         o_buf[j] = *((u8 *)data_array + i);
8042                         j++;
8043                 }
8044         }
8045
8046         return rc;
8047 }
8048
8049 static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy *phy,
8050                                              struct link_params *params,
8051                                              u8 dev_addr, u16 addr, u8 byte_cnt,
8052                                              u8 *o_buf, u8 is_init)
8053 {
8054         struct bnx2x *bp = params->bp;
8055         u16 val, i;
8056
8057         if (byte_cnt > SFP_EEPROM_PAGE_SIZE) {
8058                 DP(NETIF_MSG_LINK,
8059                    "Reading from eeprom is limited to 0xf\n");
8060                 return -EINVAL;
8061         }
8062
8063         /* Set 2-wire transfer rate of SFP+ module EEPROM
8064          * to 100Khz since some DACs(direct attached cables) do
8065          * not work at 400Khz.
8066          */
8067         bnx2x_cl45_write(bp, phy,
8068                          MDIO_PMA_DEVAD,
8069                          MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
8070                          ((dev_addr << 8) | 1));
8071
8072         /* Need to read from 1.8000 to clear it */
8073         bnx2x_cl45_read(bp, phy,
8074                         MDIO_PMA_DEVAD,
8075                         MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
8076                         &val);
8077
8078         /* Set the read command byte count */
8079         bnx2x_cl45_write(bp, phy,
8080                          MDIO_PMA_DEVAD,
8081                          MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
8082                          ((byte_cnt < 2) ? 2 : byte_cnt));
8083
8084         /* Set the read command address */
8085         bnx2x_cl45_write(bp, phy,
8086                          MDIO_PMA_DEVAD,
8087                          MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
8088                          addr);
8089         /* Set the destination address */
8090         bnx2x_cl45_write(bp, phy,
8091                          MDIO_PMA_DEVAD,
8092                          0x8004,
8093                          MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
8094
8095         /* Activate read command */
8096         bnx2x_cl45_write(bp, phy,
8097                          MDIO_PMA_DEVAD,
8098                          MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
8099                          0x8002);
8100         /* Wait appropriate time for two-wire command to finish before
8101          * polling the status register
8102          */
8103         usleep_range(1000, 2000);
8104
8105         /* Wait up to 500us for command complete status */
8106         for (i = 0; i < 100; i++) {
8107                 bnx2x_cl45_read(bp, phy,
8108                                 MDIO_PMA_DEVAD,
8109                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
8110                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
8111                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
8112                         break;
8113                 udelay(5);
8114         }
8115
8116         if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
8117                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
8118                 DP(NETIF_MSG_LINK,
8119                          "Got bad status 0x%x when reading from SFP+ EEPROM\n",
8120                          (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
8121                 return -EFAULT;
8122         }
8123
8124         /* Read the buffer */
8125         for (i = 0; i < byte_cnt; i++) {
8126                 bnx2x_cl45_read(bp, phy,
8127                                 MDIO_PMA_DEVAD,
8128                                 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
8129                 o_buf[i] = (u8)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
8130         }
8131
8132         for (i = 0; i < 100; i++) {
8133                 bnx2x_cl45_read(bp, phy,
8134                                 MDIO_PMA_DEVAD,
8135                                 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
8136                 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
8137                     MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
8138                         return 0;
8139                 usleep_range(1000, 2000);
8140         }
8141
8142         return -EINVAL;
8143 }
8144 int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy *phy,
8145                                  struct link_params *params, u8 dev_addr,
8146                                  u16 addr, u16 byte_cnt, u8 *o_buf)
8147 {
8148         int rc = 0;
8149         struct bnx2x *bp = params->bp;
8150         u8 xfer_size;
8151         u8 *user_data = o_buf;
8152         read_sfp_module_eeprom_func_p read_func;
8153
8154         if ((dev_addr != 0xa0) && (dev_addr != 0xa2)) {
8155                 DP(NETIF_MSG_LINK, "invalid dev_addr 0x%x\n", dev_addr);
8156                 return -EINVAL;
8157         }
8158
8159         switch (phy->type) {
8160         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
8161                 read_func = bnx2x_8726_read_sfp_module_eeprom;
8162                 break;
8163         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8164         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8165                 read_func = bnx2x_8727_read_sfp_module_eeprom;
8166                 break;
8167         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8168                 read_func = bnx2x_warpcore_read_sfp_module_eeprom;
8169                 break;
8170         default:
8171                 return -EOPNOTSUPP;
8172         }
8173
8174         while (!rc && (byte_cnt > 0)) {
8175                 xfer_size = (byte_cnt > SFP_EEPROM_PAGE_SIZE) ?
8176                         SFP_EEPROM_PAGE_SIZE : byte_cnt;
8177                 rc = read_func(phy, params, dev_addr, addr, xfer_size,
8178                                user_data, 0);
8179                 byte_cnt -= xfer_size;
8180                 user_data += xfer_size;
8181                 addr += xfer_size;
8182         }
8183         return rc;
8184 }
8185
8186 static int bnx2x_get_edc_mode(struct bnx2x_phy *phy,
8187                               struct link_params *params,
8188                               u16 *edc_mode)
8189 {
8190         struct bnx2x *bp = params->bp;
8191         u32 sync_offset = 0, phy_idx, media_types;
8192         u8 val[SFP_EEPROM_FC_TX_TECH_ADDR + 1], check_limiting_mode = 0;
8193         *edc_mode = EDC_MODE_LIMITING;
8194         phy->media_type = ETH_PHY_UNSPECIFIED;
8195         /* First check for copper cable */
8196         if (bnx2x_read_sfp_module_eeprom(phy,
8197                                          params,
8198                                          I2C_DEV_ADDR_A0,
8199                                          0,
8200                                          SFP_EEPROM_FC_TX_TECH_ADDR + 1,
8201                                          (u8 *)val) != 0) {
8202                 DP(NETIF_MSG_LINK, "Failed to read from SFP+ module EEPROM\n");
8203                 return -EINVAL;
8204         }
8205         params->link_attr_sync &= ~LINK_SFP_EEPROM_COMP_CODE_MASK;
8206         params->link_attr_sync |= val[SFP_EEPROM_10G_COMP_CODE_ADDR] <<
8207                 LINK_SFP_EEPROM_COMP_CODE_SHIFT;
8208         bnx2x_update_link_attr(params, params->link_attr_sync);
8209         switch (val[SFP_EEPROM_CON_TYPE_ADDR]) {
8210         case SFP_EEPROM_CON_TYPE_VAL_COPPER:
8211         {
8212                 u8 copper_module_type;
8213                 phy->media_type = ETH_PHY_DA_TWINAX;
8214                 /* Check if its active cable (includes SFP+ module)
8215                  * of passive cable
8216                  */
8217                 copper_module_type = val[SFP_EEPROM_FC_TX_TECH_ADDR];
8218
8219                 if (copper_module_type &
8220                     SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
8221                         DP(NETIF_MSG_LINK, "Active Copper cable detected\n");
8222                         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
8223                                 *edc_mode = EDC_MODE_ACTIVE_DAC;
8224                         else
8225                                 check_limiting_mode = 1;
8226                 } else {
8227                         *edc_mode = EDC_MODE_PASSIVE_DAC;
8228                         /* Even in case PASSIVE_DAC indication is not set,
8229                          * treat it as a passive DAC cable, since some cables
8230                          * don't have this indication.
8231                          */
8232                         if (copper_module_type &
8233                             SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
8234                                 DP(NETIF_MSG_LINK,
8235                                    "Passive Copper cable detected\n");
8236                         } else {
8237                                 DP(NETIF_MSG_LINK,
8238                                    "Unknown copper-cable-type\n");
8239                         }
8240                 }
8241                 break;
8242         }
8243         case SFP_EEPROM_CON_TYPE_VAL_UNKNOWN:
8244         case SFP_EEPROM_CON_TYPE_VAL_LC:
8245         case SFP_EEPROM_CON_TYPE_VAL_RJ45:
8246                 check_limiting_mode = 1;
8247                 if (((val[SFP_EEPROM_10G_COMP_CODE_ADDR] &
8248                      (SFP_EEPROM_10G_COMP_CODE_SR_MASK |
8249                       SFP_EEPROM_10G_COMP_CODE_LR_MASK |
8250                        SFP_EEPROM_10G_COMP_CODE_LRM_MASK)) == 0) &&
8251                     (val[SFP_EEPROM_1G_COMP_CODE_ADDR] != 0)) {
8252                         DP(NETIF_MSG_LINK, "1G SFP module detected\n");
8253                         phy->media_type = ETH_PHY_SFP_1G_FIBER;
8254                         if (phy->req_line_speed != SPEED_1000) {
8255                                 u8 gport = params->port;
8256                                 phy->req_line_speed = SPEED_1000;
8257                                 if (!CHIP_IS_E1x(bp)) {
8258                                         gport = BP_PATH(bp) +
8259                                         (params->port << 1);
8260                                 }
8261                                 netdev_err(bp->dev,
8262                                            "Warning: Link speed was forced to 1000Mbps. Current SFP module in port %d is not compliant with 10G Ethernet\n",
8263                                            gport);
8264                         }
8265                         if (val[SFP_EEPROM_1G_COMP_CODE_ADDR] &
8266                             SFP_EEPROM_1G_COMP_CODE_BASE_T) {
8267                                 bnx2x_sfp_set_transmitter(params, phy, 0);
8268                                 msleep(40);
8269                                 bnx2x_sfp_set_transmitter(params, phy, 1);
8270                         }
8271                 } else {
8272                         int idx, cfg_idx = 0;
8273                         DP(NETIF_MSG_LINK, "10G Optic module detected\n");
8274                         for (idx = INT_PHY; idx < MAX_PHYS; idx++) {
8275                                 if (params->phy[idx].type == phy->type) {
8276                                         cfg_idx = LINK_CONFIG_IDX(idx);
8277                                         break;
8278                                 }
8279                         }
8280                         phy->media_type = ETH_PHY_SFPP_10G_FIBER;
8281                         phy->req_line_speed = params->req_line_speed[cfg_idx];
8282                 }
8283                 break;
8284         default:
8285                 DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n",
8286                          val[SFP_EEPROM_CON_TYPE_ADDR]);
8287                 return -EINVAL;
8288         }
8289         sync_offset = params->shmem_base +
8290                 offsetof(struct shmem_region,
8291                          dev_info.port_hw_config[params->port].media_type);
8292         media_types = REG_RD(bp, sync_offset);
8293         /* Update media type for non-PMF sync */
8294         for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
8295                 if (&(params->phy[phy_idx]) == phy) {
8296                         media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
8297                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
8298                         media_types |= ((phy->media_type &
8299                                         PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
8300                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
8301                         break;
8302                 }
8303         }
8304         REG_WR(bp, sync_offset, media_types);
8305         if (check_limiting_mode) {
8306                 u8 options[SFP_EEPROM_OPTIONS_SIZE];
8307                 if (bnx2x_read_sfp_module_eeprom(phy,
8308                                                  params,
8309                                                  I2C_DEV_ADDR_A0,
8310                                                  SFP_EEPROM_OPTIONS_ADDR,
8311                                                  SFP_EEPROM_OPTIONS_SIZE,
8312                                                  options) != 0) {
8313                         DP(NETIF_MSG_LINK,
8314                            "Failed to read Option field from module EEPROM\n");
8315                         return -EINVAL;
8316                 }
8317                 if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
8318                         *edc_mode = EDC_MODE_LINEAR;
8319                 else
8320                         *edc_mode = EDC_MODE_LIMITING;
8321         }
8322         DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode);
8323         return 0;
8324 }
8325 /* This function read the relevant field from the module (SFP+), and verify it
8326  * is compliant with this board
8327  */
8328 static int bnx2x_verify_sfp_module(struct bnx2x_phy *phy,
8329                                    struct link_params *params)
8330 {
8331         struct bnx2x *bp = params->bp;
8332         u32 val, cmd;
8333         u32 fw_resp, fw_cmd_param;
8334         char vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE+1];
8335         char vendor_pn[SFP_EEPROM_PART_NO_SIZE+1];
8336         phy->flags &= ~FLAGS_SFP_NOT_APPROVED;
8337         val = REG_RD(bp, params->shmem_base +
8338                          offsetof(struct shmem_region, dev_info.
8339                                   port_feature_config[params->port].config));
8340         if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8341             PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
8342                 DP(NETIF_MSG_LINK, "NOT enforcing module verification\n");
8343                 return 0;
8344         }
8345
8346         if (params->feature_config_flags &
8347             FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) {
8348                 /* Use specific phy request */
8349                 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL;
8350         } else if (params->feature_config_flags &
8351                    FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
8352                 /* Use first phy request only in case of non-dual media*/
8353                 if (DUAL_MEDIA(params)) {
8354                         DP(NETIF_MSG_LINK,
8355                            "FW does not support OPT MDL verification\n");
8356                         return -EINVAL;
8357                 }
8358                 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL;
8359         } else {
8360                 /* No support in OPT MDL detection */
8361                 DP(NETIF_MSG_LINK,
8362                    "FW does not support OPT MDL verification\n");
8363                 return -EINVAL;
8364         }
8365
8366         fw_cmd_param = FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);
8367         fw_resp = bnx2x_fw_command(bp, cmd, fw_cmd_param);
8368         if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
8369                 DP(NETIF_MSG_LINK, "Approved module\n");
8370                 return 0;
8371         }
8372
8373         /* Format the warning message */
8374         if (bnx2x_read_sfp_module_eeprom(phy,
8375                                          params,
8376                                          I2C_DEV_ADDR_A0,
8377                                          SFP_EEPROM_VENDOR_NAME_ADDR,
8378                                          SFP_EEPROM_VENDOR_NAME_SIZE,
8379                                          (u8 *)vendor_name))
8380                 vendor_name[0] = '\0';
8381         else
8382                 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
8383         if (bnx2x_read_sfp_module_eeprom(phy,
8384                                          params,
8385                                          I2C_DEV_ADDR_A0,
8386                                          SFP_EEPROM_PART_NO_ADDR,
8387                                          SFP_EEPROM_PART_NO_SIZE,
8388                                          (u8 *)vendor_pn))
8389                 vendor_pn[0] = '\0';
8390         else
8391                 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0';
8392
8393         netdev_err(bp->dev,  "Warning: Unqualified SFP+ module detected,"
8394                               " Port %d from %s part number %s\n",
8395                          params->port, vendor_name, vendor_pn);
8396         if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
8397             PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG)
8398                 phy->flags |= FLAGS_SFP_NOT_APPROVED;
8399         return -EINVAL;
8400 }
8401
8402 static int bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy *phy,
8403                                                  struct link_params *params)
8404
8405 {
8406         u8 val;
8407         int rc;
8408         struct bnx2x *bp = params->bp;
8409         u16 timeout;
8410         /* Initialization time after hot-plug may take up to 300ms for
8411          * some phys type ( e.g. JDSU )
8412          */
8413
8414         for (timeout = 0; timeout < 60; timeout++) {
8415                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
8416                         rc = bnx2x_warpcore_read_sfp_module_eeprom(
8417                                 phy, params, I2C_DEV_ADDR_A0, 1, 1, &val,
8418                                 1);
8419                 else
8420                         rc = bnx2x_read_sfp_module_eeprom(phy, params,
8421                                                           I2C_DEV_ADDR_A0,
8422                                                           1, 1, &val);
8423                 if (rc == 0) {
8424                         DP(NETIF_MSG_LINK,
8425                            "SFP+ module initialization took %d ms\n",
8426                            timeout * 5);
8427                         return 0;
8428                 }
8429                 usleep_range(5000, 10000);
8430         }
8431         rc = bnx2x_read_sfp_module_eeprom(phy, params, I2C_DEV_ADDR_A0,
8432                                           1, 1, &val);
8433         return rc;
8434 }
8435
8436 static void bnx2x_8727_power_module(struct bnx2x *bp,
8437                                     struct bnx2x_phy *phy,
8438                                     u8 is_power_up) {
8439         /* Make sure GPIOs are not using for LED mode */
8440         u16 val;
8441         /* In the GPIO register, bit 4 is use to determine if the GPIOs are
8442          * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
8443          * output
8444          * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0
8445          * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1
8446          * where the 1st bit is the over-current(only input), and 2nd bit is
8447          * for power( only output )
8448          *
8449          * In case of NOC feature is disabled and power is up, set GPIO control
8450          *  as input to enable listening of over-current indication
8451          */
8452         if (phy->flags & FLAGS_NOC)
8453                 return;
8454         if (is_power_up)
8455                 val = (1<<4);
8456         else
8457                 /* Set GPIO control to OUTPUT, and set the power bit
8458                  * to according to the is_power_up
8459                  */
8460                 val = (1<<1);
8461
8462         bnx2x_cl45_write(bp, phy,
8463                          MDIO_PMA_DEVAD,
8464                          MDIO_PMA_REG_8727_GPIO_CTRL,
8465                          val);
8466 }
8467
8468 static int bnx2x_8726_set_limiting_mode(struct bnx2x *bp,
8469                                         struct bnx2x_phy *phy,
8470                                         u16 edc_mode)
8471 {
8472         u16 cur_limiting_mode;
8473
8474         bnx2x_cl45_read(bp, phy,
8475                         MDIO_PMA_DEVAD,
8476                         MDIO_PMA_REG_ROM_VER2,
8477                         &cur_limiting_mode);
8478         DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n",
8479                  cur_limiting_mode);
8480
8481         if (edc_mode == EDC_MODE_LIMITING) {
8482                 DP(NETIF_MSG_LINK, "Setting LIMITING MODE\n");
8483                 bnx2x_cl45_write(bp, phy,
8484                                  MDIO_PMA_DEVAD,
8485                                  MDIO_PMA_REG_ROM_VER2,
8486                                  EDC_MODE_LIMITING);
8487         } else { /* LRM mode ( default )*/
8488
8489                 DP(NETIF_MSG_LINK, "Setting LRM MODE\n");
8490
8491                 /* Changing to LRM mode takes quite few seconds. So do it only
8492                  * if current mode is limiting (default is LRM)
8493                  */
8494                 if (cur_limiting_mode != EDC_MODE_LIMITING)
8495                         return 0;
8496
8497                 bnx2x_cl45_write(bp, phy,
8498                                  MDIO_PMA_DEVAD,
8499                                  MDIO_PMA_REG_LRM_MODE,
8500                                  0);
8501                 bnx2x_cl45_write(bp, phy,
8502                                  MDIO_PMA_DEVAD,
8503                                  MDIO_PMA_REG_ROM_VER2,
8504                                  0x128);
8505                 bnx2x_cl45_write(bp, phy,
8506                                  MDIO_PMA_DEVAD,
8507                                  MDIO_PMA_REG_MISC_CTRL0,
8508                                  0x4008);
8509                 bnx2x_cl45_write(bp, phy,
8510                                  MDIO_PMA_DEVAD,
8511                                  MDIO_PMA_REG_LRM_MODE,
8512                                  0xaaaa);
8513         }
8514         return 0;
8515 }
8516
8517 static int bnx2x_8727_set_limiting_mode(struct bnx2x *bp,
8518                                         struct bnx2x_phy *phy,
8519                                         u16 edc_mode)
8520 {
8521         u16 phy_identifier;
8522         u16 rom_ver2_val;
8523         bnx2x_cl45_read(bp, phy,
8524                         MDIO_PMA_DEVAD,
8525                         MDIO_PMA_REG_PHY_IDENTIFIER,
8526                         &phy_identifier);
8527
8528         bnx2x_cl45_write(bp, phy,
8529                          MDIO_PMA_DEVAD,
8530                          MDIO_PMA_REG_PHY_IDENTIFIER,
8531                          (phy_identifier & ~(1<<9)));
8532
8533         bnx2x_cl45_read(bp, phy,
8534                         MDIO_PMA_DEVAD,
8535                         MDIO_PMA_REG_ROM_VER2,
8536                         &rom_ver2_val);
8537         /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
8538         bnx2x_cl45_write(bp, phy,
8539                          MDIO_PMA_DEVAD,
8540                          MDIO_PMA_REG_ROM_VER2,
8541                          (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
8542
8543         bnx2x_cl45_write(bp, phy,
8544                          MDIO_PMA_DEVAD,
8545                          MDIO_PMA_REG_PHY_IDENTIFIER,
8546                          (phy_identifier | (1<<9)));
8547
8548         return 0;
8549 }
8550
8551 static void bnx2x_8727_specific_func(struct bnx2x_phy *phy,
8552                                      struct link_params *params,
8553                                      u32 action)
8554 {
8555         struct bnx2x *bp = params->bp;
8556         u16 val;
8557         switch (action) {
8558         case DISABLE_TX:
8559                 bnx2x_sfp_set_transmitter(params, phy, 0);
8560                 break;
8561         case ENABLE_TX:
8562                 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED))
8563                         bnx2x_sfp_set_transmitter(params, phy, 1);
8564                 break;
8565         case PHY_INIT:
8566                 bnx2x_cl45_write(bp, phy,
8567                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
8568                                  (1<<2) | (1<<5));
8569                 bnx2x_cl45_write(bp, phy,
8570                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
8571                                  0);
8572                 bnx2x_cl45_write(bp, phy,
8573                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0006);
8574                 /* Make MOD_ABS give interrupt on change */
8575                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8576                                 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8577                                 &val);
8578                 val |= (1<<12);
8579                 if (phy->flags & FLAGS_NOC)
8580                         val |= (3<<5);
8581                 /* Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
8582                  * status which reflect SFP+ module over-current
8583                  */
8584                 if (!(phy->flags & FLAGS_NOC))
8585                         val &= 0xff8f; /* Reset bits 4-6 */
8586                 bnx2x_cl45_write(bp, phy,
8587                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
8588                                  val);
8589                 break;
8590         default:
8591                 DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n",
8592                    action);
8593                 return;
8594         }
8595 }
8596
8597 static void bnx2x_set_e1e2_module_fault_led(struct link_params *params,
8598                                            u8 gpio_mode)
8599 {
8600         struct bnx2x *bp = params->bp;
8601
8602         u32 fault_led_gpio = REG_RD(bp, params->shmem_base +
8603                             offsetof(struct shmem_region,
8604                         dev_info.port_hw_config[params->port].sfp_ctrl)) &
8605                 PORT_HW_CFG_FAULT_MODULE_LED_MASK;
8606         switch (fault_led_gpio) {
8607         case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED:
8608                 return;
8609         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0:
8610         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1:
8611         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2:
8612         case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3:
8613         {
8614                 u8 gpio_port = bnx2x_get_gpio_port(params);
8615                 u16 gpio_pin = fault_led_gpio -
8616                         PORT_HW_CFG_FAULT_MODULE_LED_GPIO0;
8617                 DP(NETIF_MSG_LINK, "Set fault module-detected led "
8618                                    "pin %x port %x mode %x\n",
8619                                gpio_pin, gpio_port, gpio_mode);
8620                 bnx2x_set_gpio(bp, gpio_pin, gpio_mode, gpio_port);
8621         }
8622         break;
8623         default:
8624                 DP(NETIF_MSG_LINK, "Error: Invalid fault led mode 0x%x\n",
8625                                fault_led_gpio);
8626         }
8627 }
8628
8629 static void bnx2x_set_e3_module_fault_led(struct link_params *params,
8630                                           u8 gpio_mode)
8631 {
8632         u32 pin_cfg;
8633         u8 port = params->port;
8634         struct bnx2x *bp = params->bp;
8635         pin_cfg = (REG_RD(bp, params->shmem_base +
8636                          offsetof(struct shmem_region,
8637                                   dev_info.port_hw_config[port].e3_sfp_ctrl)) &
8638                 PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >>
8639                 PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT;
8640         DP(NETIF_MSG_LINK, "Setting Fault LED to %d using pin cfg %d\n",
8641                        gpio_mode, pin_cfg);
8642         bnx2x_set_cfg_pin(bp, pin_cfg, gpio_mode);
8643 }
8644
8645 static void bnx2x_set_sfp_module_fault_led(struct link_params *params,
8646                                            u8 gpio_mode)
8647 {
8648         struct bnx2x *bp = params->bp;
8649         DP(NETIF_MSG_LINK, "Setting SFP+ module fault LED to %d\n", gpio_mode);
8650         if (CHIP_IS_E3(bp)) {
8651                 /* Low ==> if SFP+ module is supported otherwise
8652                  * High ==> if SFP+ module is not on the approved vendor list
8653                  */
8654                 bnx2x_set_e3_module_fault_led(params, gpio_mode);
8655         } else
8656                 bnx2x_set_e1e2_module_fault_led(params, gpio_mode);
8657 }
8658
8659 static void bnx2x_warpcore_hw_reset(struct bnx2x_phy *phy,
8660                                     struct link_params *params)
8661 {
8662         struct bnx2x *bp = params->bp;
8663         bnx2x_warpcore_power_module(params, 0);
8664         /* Put Warpcore in low power mode */
8665         REG_WR(bp, MISC_REG_WC0_RESET, 0x0c0e);
8666
8667         /* Put LCPLL in low power mode */
8668         REG_WR(bp, MISC_REG_LCPLL_E40_PWRDWN, 1);
8669         REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_ANA, 0);
8670         REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_DIG, 0);
8671 }
8672
8673 static void bnx2x_power_sfp_module(struct link_params *params,
8674                                    struct bnx2x_phy *phy,
8675                                    u8 power)
8676 {
8677         struct bnx2x *bp = params->bp;
8678         DP(NETIF_MSG_LINK, "Setting SFP+ power to %x\n", power);
8679
8680         switch (phy->type) {
8681         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8682         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8683                 bnx2x_8727_power_module(params->bp, phy, power);
8684                 break;
8685         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8686                 bnx2x_warpcore_power_module(params, power);
8687                 break;
8688         default:
8689                 break;
8690         }
8691 }
8692 static void bnx2x_warpcore_set_limiting_mode(struct link_params *params,
8693                                              struct bnx2x_phy *phy,
8694                                              u16 edc_mode)
8695 {
8696         u16 val = 0;
8697         u16 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8698         struct bnx2x *bp = params->bp;
8699
8700         u8 lane = bnx2x_get_warpcore_lane(phy, params);
8701         /* This is a global register which controls all lanes */
8702         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
8703                         MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8704         val &= ~(0xf << (lane << 2));
8705
8706         switch (edc_mode) {
8707         case EDC_MODE_LINEAR:
8708         case EDC_MODE_LIMITING:
8709                 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
8710                 break;
8711         case EDC_MODE_PASSIVE_DAC:
8712         case EDC_MODE_ACTIVE_DAC:
8713                 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC;
8714                 break;
8715         default:
8716                 break;
8717         }
8718
8719         val |= (mode << (lane << 2));
8720         bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
8721                          MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val);
8722         /* A must read */
8723         bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
8724                         MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
8725
8726         /* Restart microcode to re-read the new mode */
8727         bnx2x_warpcore_reset_lane(bp, phy, 1);
8728         bnx2x_warpcore_reset_lane(bp, phy, 0);
8729
8730 }
8731
8732 static void bnx2x_set_limiting_mode(struct link_params *params,
8733                                     struct bnx2x_phy *phy,
8734                                     u16 edc_mode)
8735 {
8736         switch (phy->type) {
8737         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
8738                 bnx2x_8726_set_limiting_mode(params->bp, phy, edc_mode);
8739                 break;
8740         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8741         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8742                 bnx2x_8727_set_limiting_mode(params->bp, phy, edc_mode);
8743                 break;
8744         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8745                 bnx2x_warpcore_set_limiting_mode(params, phy, edc_mode);
8746                 break;
8747         }
8748 }
8749
8750 static int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
8751                                       struct link_params *params)
8752 {
8753         struct bnx2x *bp = params->bp;
8754         u16 edc_mode;
8755         int rc = 0;
8756
8757         u32 val = REG_RD(bp, params->shmem_base +
8758                              offsetof(struct shmem_region, dev_info.
8759                                      port_feature_config[params->port].config));
8760         /* Enabled transmitter by default */
8761         bnx2x_sfp_set_transmitter(params, phy, 1);
8762         DP(NETIF_MSG_LINK, "SFP+ module plugged in/out detected on port %d\n",
8763                  params->port);
8764         /* Power up module */
8765         bnx2x_power_sfp_module(params, phy, 1);
8766         if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) {
8767                 DP(NETIF_MSG_LINK, "Failed to get valid module type\n");
8768                 return -EINVAL;
8769         } else if (bnx2x_verify_sfp_module(phy, params) != 0) {
8770                 /* Check SFP+ module compatibility */
8771                 DP(NETIF_MSG_LINK, "Module verification failed!!\n");
8772                 rc = -EINVAL;
8773                 /* Turn on fault module-detected led */
8774                 bnx2x_set_sfp_module_fault_led(params,
8775                                                MISC_REGISTERS_GPIO_HIGH);
8776
8777                 /* Check if need to power down the SFP+ module */
8778                 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8779                      PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) {
8780                         DP(NETIF_MSG_LINK, "Shutdown SFP+ module!!\n");
8781                         bnx2x_power_sfp_module(params, phy, 0);
8782                         return rc;
8783                 }
8784         } else {
8785                 /* Turn off fault module-detected led */
8786                 bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW);
8787         }
8788
8789         /* Check and set limiting mode / LRM mode on 8726. On 8727 it
8790          * is done automatically
8791          */
8792         bnx2x_set_limiting_mode(params, phy, edc_mode);
8793
8794         /* Disable transmit for this module if the module is not approved, and
8795          * laser needs to be disabled.
8796          */
8797         if ((rc) &&
8798             ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
8799              PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER))
8800                 bnx2x_sfp_set_transmitter(params, phy, 0);
8801
8802         return rc;
8803 }
8804
8805 void bnx2x_handle_module_detect_int(struct link_params *params)
8806 {
8807         struct bnx2x *bp = params->bp;
8808         struct bnx2x_phy *phy;
8809         u32 gpio_val;
8810         u8 gpio_num, gpio_port;
8811         if (CHIP_IS_E3(bp)) {
8812                 phy = &params->phy[INT_PHY];
8813                 /* Always enable TX laser,will be disabled in case of fault */
8814                 bnx2x_sfp_set_transmitter(params, phy, 1);
8815         } else {
8816                 phy = &params->phy[EXT_PHY1];
8817         }
8818         if (bnx2x_get_mod_abs_int_cfg(bp, params->chip_id, params->shmem_base,
8819                                       params->port, &gpio_num, &gpio_port) ==
8820             -EINVAL) {
8821                 DP(NETIF_MSG_LINK, "Failed to get MOD_ABS interrupt config\n");
8822                 return;
8823         }
8824
8825         /* Set valid module led off */
8826         bnx2x_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH);
8827
8828         /* Get current gpio val reflecting module plugged in / out*/
8829         gpio_val = bnx2x_get_gpio(bp, gpio_num, gpio_port);
8830
8831         /* Call the handling function in case module is detected */
8832         if (gpio_val == 0) {
8833                 bnx2x_set_mdio_emac_per_phy(bp, params);
8834                 bnx2x_set_aer_mmd(params, phy);
8835
8836                 bnx2x_power_sfp_module(params, phy, 1);
8837                 bnx2x_set_gpio_int(bp, gpio_num,
8838                                    MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
8839                                    gpio_port);
8840                 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0) {
8841                         bnx2x_sfp_module_detection(phy, params);
8842                         if (CHIP_IS_E3(bp)) {
8843                                 u16 rx_tx_in_reset;
8844                                 /* In case WC is out of reset, reconfigure the
8845                                  * link speed while taking into account 1G
8846                                  * module limitation.
8847                                  */
8848                                 bnx2x_cl45_read(bp, phy,
8849                                                 MDIO_WC_DEVAD,
8850                                                 MDIO_WC_REG_DIGITAL5_MISC6,
8851                                                 &rx_tx_in_reset);
8852                                 if ((!rx_tx_in_reset) &&
8853                                     (params->link_flags &
8854                                      PHY_INITIALIZED)) {
8855                                         bnx2x_warpcore_reset_lane(bp, phy, 1);
8856                                         bnx2x_warpcore_config_sfi(phy, params);
8857                                         bnx2x_warpcore_reset_lane(bp, phy, 0);
8858                                 }
8859                         }
8860                 } else {
8861                         DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
8862                 }
8863         } else {
8864                 bnx2x_set_gpio_int(bp, gpio_num,
8865                                    MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
8866                                    gpio_port);
8867                 /* Module was plugged out.
8868                  * Disable transmit for this module
8869                  */
8870                 phy->media_type = ETH_PHY_NOT_PRESENT;
8871         }
8872 }
8873
8874 /******************************************************************/
8875 /*              Used by 8706 and 8727                             */
8876 /******************************************************************/
8877 static void bnx2x_sfp_mask_fault(struct bnx2x *bp,
8878                                  struct bnx2x_phy *phy,
8879                                  u16 alarm_status_offset,
8880                                  u16 alarm_ctrl_offset)
8881 {
8882         u16 alarm_status, val;
8883         bnx2x_cl45_read(bp, phy,
8884                         MDIO_PMA_DEVAD, alarm_status_offset,
8885                         &alarm_status);
8886         bnx2x_cl45_read(bp, phy,
8887                         MDIO_PMA_DEVAD, alarm_status_offset,
8888                         &alarm_status);
8889         /* Mask or enable the fault event. */
8890         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val);
8891         if (alarm_status & (1<<0))
8892                 val &= ~(1<<0);
8893         else
8894                 val |= (1<<0);
8895         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val);
8896 }
8897 /******************************************************************/
8898 /*              common BCM8706/BCM8726 PHY SECTION                */
8899 /******************************************************************/
8900 static u8 bnx2x_8706_8726_read_status(struct bnx2x_phy *phy,
8901                                       struct link_params *params,
8902                                       struct link_vars *vars)
8903 {
8904         u8 link_up = 0;
8905         u16 val1, val2, rx_sd, pcs_status;
8906         struct bnx2x *bp = params->bp;
8907         DP(NETIF_MSG_LINK, "XGXS 8706/8726\n");
8908         /* Clear RX Alarm*/
8909         bnx2x_cl45_read(bp, phy,
8910                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
8911
8912         bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
8913                              MDIO_PMA_LASI_TXCTRL);
8914
8915         /* Clear LASI indication*/
8916         bnx2x_cl45_read(bp, phy,
8917                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
8918         bnx2x_cl45_read(bp, phy,
8919                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
8920         DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2);
8921
8922         bnx2x_cl45_read(bp, phy,
8923                         MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
8924         bnx2x_cl45_read(bp, phy,
8925                         MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status);
8926         bnx2x_cl45_read(bp, phy,
8927                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8928         bnx2x_cl45_read(bp, phy,
8929                         MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
8930
8931         DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
8932                         " link_status 0x%x\n", rx_sd, pcs_status, val2);
8933         /* Link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
8934          * are set, or if the autoneg bit 1 is set
8935          */
8936         link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1)));
8937         if (link_up) {
8938                 if (val2 & (1<<1))
8939                         vars->line_speed = SPEED_1000;
8940                 else
8941                         vars->line_speed = SPEED_10000;
8942                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
8943                 vars->duplex = DUPLEX_FULL;
8944         }
8945
8946         /* Capture 10G link fault. Read twice to clear stale value. */
8947         if (vars->line_speed == SPEED_10000) {
8948                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8949                             MDIO_PMA_LASI_TXSTAT, &val1);
8950                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
8951                             MDIO_PMA_LASI_TXSTAT, &val1);
8952                 if (val1 & (1<<0))
8953                         vars->fault_detected = 1;
8954         }
8955
8956         return link_up;
8957 }
8958
8959 /******************************************************************/
8960 /*                      BCM8706 PHY SECTION                       */
8961 /******************************************************************/
8962 static u8 bnx2x_8706_config_init(struct bnx2x_phy *phy,
8963                                  struct link_params *params,
8964                                  struct link_vars *vars)
8965 {
8966         u32 tx_en_mode;
8967         u16 cnt, val, tmp1;
8968         struct bnx2x *bp = params->bp;
8969
8970         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
8971                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
8972         /* HW reset */
8973         bnx2x_ext_phy_hw_reset(bp, params->port);
8974         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
8975         bnx2x_wait_reset_complete(bp, phy, params);
8976
8977         /* Wait until fw is loaded */
8978         for (cnt = 0; cnt < 100; cnt++) {
8979                 bnx2x_cl45_read(bp, phy,
8980                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val);
8981                 if (val)
8982                         break;
8983                 usleep_range(10000, 20000);
8984         }
8985         DP(NETIF_MSG_LINK, "XGXS 8706 is initialized after %d ms\n", cnt);
8986         if ((params->feature_config_flags &
8987              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
8988                 u8 i;
8989                 u16 reg;
8990                 for (i = 0; i < 4; i++) {
8991                         reg = MDIO_XS_8706_REG_BANK_RX0 +
8992                                 i*(MDIO_XS_8706_REG_BANK_RX1 -
8993                                    MDIO_XS_8706_REG_BANK_RX0);
8994                         bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, reg, &val);
8995                         /* Clear first 3 bits of the control */
8996                         val &= ~0x7;
8997                         /* Set control bits according to configuration */
8998                         val |= (phy->rx_preemphasis[i] & 0x7);
8999                         DP(NETIF_MSG_LINK, "Setting RX Equalizer to BCM8706"
9000                                    " reg 0x%x <-- val 0x%x\n", reg, val);
9001                         bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, reg, val);
9002                 }
9003         }
9004         /* Force speed */
9005         if (phy->req_line_speed == SPEED_10000) {
9006                 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n");
9007
9008                 bnx2x_cl45_write(bp, phy,
9009                                  MDIO_PMA_DEVAD,
9010                                  MDIO_PMA_REG_DIGITAL_CTRL, 0x400);
9011                 bnx2x_cl45_write(bp, phy,
9012                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
9013                                  0);
9014                 /* Arm LASI for link and Tx fault. */
9015                 bnx2x_cl45_write(bp, phy,
9016                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3);
9017         } else {
9018                 /* Force 1Gbps using autoneg with 1G advertisement */
9019
9020                 /* Allow CL37 through CL73 */
9021                 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
9022                 bnx2x_cl45_write(bp, phy,
9023                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
9024
9025                 /* Enable Full-Duplex advertisement on CL37 */
9026                 bnx2x_cl45_write(bp, phy,
9027                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020);
9028                 /* Enable CL37 AN */
9029                 bnx2x_cl45_write(bp, phy,
9030                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
9031                 /* 1G support */
9032                 bnx2x_cl45_write(bp, phy,
9033                                  MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5));
9034
9035                 /* Enable clause 73 AN */
9036                 bnx2x_cl45_write(bp, phy,
9037                                  MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
9038                 bnx2x_cl45_write(bp, phy,
9039                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9040                                  0x0400);
9041                 bnx2x_cl45_write(bp, phy,
9042                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
9043                                  0x0004);
9044         }
9045         bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
9046
9047         /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
9048          * power mode, if TX Laser is disabled
9049          */
9050
9051         tx_en_mode = REG_RD(bp, params->shmem_base +
9052                             offsetof(struct shmem_region,
9053                                 dev_info.port_hw_config[params->port].sfp_ctrl))
9054                         & PORT_HW_CFG_TX_LASER_MASK;
9055
9056         if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
9057                 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
9058                 bnx2x_cl45_read(bp, phy,
9059                         MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1);
9060                 tmp1 |= 0x1;
9061                 bnx2x_cl45_write(bp, phy,
9062                         MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1);
9063         }
9064
9065         return 0;
9066 }
9067
9068 static int bnx2x_8706_read_status(struct bnx2x_phy *phy,
9069                                   struct link_params *params,
9070                                   struct link_vars *vars)
9071 {
9072         return bnx2x_8706_8726_read_status(phy, params, vars);
9073 }
9074
9075 /******************************************************************/
9076 /*                      BCM8726 PHY SECTION                       */
9077 /******************************************************************/
9078 static void bnx2x_8726_config_loopback(struct bnx2x_phy *phy,
9079                                        struct link_params *params)
9080 {
9081         struct bnx2x *bp = params->bp;
9082         DP(NETIF_MSG_LINK, "PMA/PMD ext_phy_loopback: 8726\n");
9083         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);
9084 }
9085
9086 static void bnx2x_8726_external_rom_boot(struct bnx2x_phy *phy,
9087                                          struct link_params *params)
9088 {
9089         struct bnx2x *bp = params->bp;
9090         /* Need to wait 100ms after reset */
9091         msleep(100);
9092
9093         /* Micro controller re-boot */
9094         bnx2x_cl45_write(bp, phy,
9095                          MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B);
9096
9097         /* Set soft reset */
9098         bnx2x_cl45_write(bp, phy,
9099                          MDIO_PMA_DEVAD,
9100                          MDIO_PMA_REG_GEN_CTRL,
9101                          MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
9102
9103         bnx2x_cl45_write(bp, phy,
9104                          MDIO_PMA_DEVAD,
9105                          MDIO_PMA_REG_MISC_CTRL1, 0x0001);
9106
9107         bnx2x_cl45_write(bp, phy,
9108                          MDIO_PMA_DEVAD,
9109                          MDIO_PMA_REG_GEN_CTRL,
9110                          MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
9111
9112         /* Wait for 150ms for microcode load */
9113         msleep(150);
9114
9115         /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
9116         bnx2x_cl45_write(bp, phy,
9117                          MDIO_PMA_DEVAD,
9118                          MDIO_PMA_REG_MISC_CTRL1, 0x0000);
9119
9120         msleep(200);
9121         bnx2x_save_bcm_spirom_ver(bp, phy, params->port);
9122 }
9123
9124 static u8 bnx2x_8726_read_status(struct bnx2x_phy *phy,
9125                                  struct link_params *params,
9126                                  struct link_vars *vars)
9127 {
9128         struct bnx2x *bp = params->bp;
9129         u16 val1;
9130         u8 link_up = bnx2x_8706_8726_read_status(phy, params, vars);
9131         if (link_up) {
9132                 bnx2x_cl45_read(bp, phy,
9133                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
9134                                 &val1);
9135                 if (val1 & (1<<15)) {
9136                         DP(NETIF_MSG_LINK, "Tx is disabled\n");
9137                         link_up = 0;
9138                         vars->line_speed = 0;
9139                 }
9140         }
9141         return link_up;
9142 }
9143
9144
9145 static int bnx2x_8726_config_init(struct bnx2x_phy *phy,
9146                                   struct link_params *params,
9147                                   struct link_vars *vars)
9148 {
9149         struct bnx2x *bp = params->bp;
9150         DP(NETIF_MSG_LINK, "Initializing BCM8726\n");
9151
9152         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
9153         bnx2x_wait_reset_complete(bp, phy, params);
9154
9155         bnx2x_8726_external_rom_boot(phy, params);
9156
9157         /* Need to call module detected on initialization since the module
9158          * detection triggered by actual module insertion might occur before
9159          * driver is loaded, and when driver is loaded, it reset all
9160          * registers, including the transmitter
9161          */
9162         bnx2x_sfp_module_detection(phy, params);
9163
9164         if (phy->req_line_speed == SPEED_1000) {
9165                 DP(NETIF_MSG_LINK, "Setting 1G force\n");
9166                 bnx2x_cl45_write(bp, phy,
9167                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
9168                 bnx2x_cl45_write(bp, phy,
9169                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
9170                 bnx2x_cl45_write(bp, phy,
9171                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5);
9172                 bnx2x_cl45_write(bp, phy,
9173                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9174                                  0x400);
9175         } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
9176                    (phy->speed_cap_mask &
9177                       PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
9178                    ((phy->speed_cap_mask &
9179                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
9180                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
9181                 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
9182                 /* Set Flow control */
9183                 bnx2x_ext_phy_set_pause(params, phy, vars);
9184                 bnx2x_cl45_write(bp, phy,
9185                                  MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);
9186                 bnx2x_cl45_write(bp, phy,
9187                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
9188                 bnx2x_cl45_write(bp, phy,
9189                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020);
9190                 bnx2x_cl45_write(bp, phy,
9191                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
9192                 bnx2x_cl45_write(bp, phy,
9193                                 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
9194                 /* Enable RX-ALARM control to receive interrupt for 1G speed
9195                  * change
9196                  */
9197                 bnx2x_cl45_write(bp, phy,
9198                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4);
9199                 bnx2x_cl45_write(bp, phy,
9200                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9201                                  0x400);
9202
9203         } else { /* Default 10G. Set only LASI control */
9204                 bnx2x_cl45_write(bp, phy,
9205                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1);
9206         }
9207
9208         /* Set TX PreEmphasis if needed */
9209         if ((params->feature_config_flags &
9210              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
9211                 DP(NETIF_MSG_LINK,
9212                    "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
9213                          phy->tx_preemphasis[0],
9214                          phy->tx_preemphasis[1]);
9215                 bnx2x_cl45_write(bp, phy,
9216                                  MDIO_PMA_DEVAD,
9217                                  MDIO_PMA_REG_8726_TX_CTRL1,
9218                                  phy->tx_preemphasis[0]);
9219
9220                 bnx2x_cl45_write(bp, phy,
9221                                  MDIO_PMA_DEVAD,
9222                                  MDIO_PMA_REG_8726_TX_CTRL2,
9223                                  phy->tx_preemphasis[1]);
9224         }
9225
9226         return 0;
9227
9228 }
9229
9230 static void bnx2x_8726_link_reset(struct bnx2x_phy *phy,
9231                                   struct link_params *params)
9232 {
9233         struct bnx2x *bp = params->bp;
9234         DP(NETIF_MSG_LINK, "bnx2x_8726_link_reset port %d\n", params->port);
9235         /* Set serial boot control for external load */
9236         bnx2x_cl45_write(bp, phy,
9237                          MDIO_PMA_DEVAD,
9238                          MDIO_PMA_REG_GEN_CTRL, 0x0001);
9239 }
9240
9241 /******************************************************************/
9242 /*                      BCM8727 PHY SECTION                       */
9243 /******************************************************************/
9244
9245 static void bnx2x_8727_set_link_led(struct bnx2x_phy *phy,
9246                                     struct link_params *params, u8 mode)
9247 {
9248         struct bnx2x *bp = params->bp;
9249         u16 led_mode_bitmask = 0;
9250         u16 gpio_pins_bitmask = 0;
9251         u16 val;
9252         /* Only NOC flavor requires to set the LED specifically */
9253         if (!(phy->flags & FLAGS_NOC))
9254                 return;
9255         switch (mode) {
9256         case LED_MODE_FRONT_PANEL_OFF:
9257         case LED_MODE_OFF:
9258                 led_mode_bitmask = 0;
9259                 gpio_pins_bitmask = 0x03;
9260                 break;
9261         case LED_MODE_ON:
9262                 led_mode_bitmask = 0;
9263                 gpio_pins_bitmask = 0x02;
9264                 break;
9265         case LED_MODE_OPER:
9266                 led_mode_bitmask = 0x60;
9267                 gpio_pins_bitmask = 0x11;
9268                 break;
9269         }
9270         bnx2x_cl45_read(bp, phy,
9271                         MDIO_PMA_DEVAD,
9272                         MDIO_PMA_REG_8727_PCS_OPT_CTRL,
9273                         &val);
9274         val &= 0xff8f;
9275         val |= led_mode_bitmask;
9276         bnx2x_cl45_write(bp, phy,
9277                          MDIO_PMA_DEVAD,
9278                          MDIO_PMA_REG_8727_PCS_OPT_CTRL,
9279                          val);
9280         bnx2x_cl45_read(bp, phy,
9281                         MDIO_PMA_DEVAD,
9282                         MDIO_PMA_REG_8727_GPIO_CTRL,
9283                         &val);
9284         val &= 0xffe0;
9285         val |= gpio_pins_bitmask;
9286         bnx2x_cl45_write(bp, phy,
9287                          MDIO_PMA_DEVAD,
9288                          MDIO_PMA_REG_8727_GPIO_CTRL,
9289                          val);
9290 }
9291 static void bnx2x_8727_hw_reset(struct bnx2x_phy *phy,
9292                                 struct link_params *params) {
9293         u32 swap_val, swap_override;
9294         u8 port;
9295         /* The PHY reset is controlled by GPIO 1. Fake the port number
9296          * to cancel the swap done in set_gpio()
9297          */
9298         struct bnx2x *bp = params->bp;
9299         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
9300         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
9301         port = (swap_val && swap_override) ^ 1;
9302         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
9303                        MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
9304 }
9305
9306 static void bnx2x_8727_config_speed(struct bnx2x_phy *phy,
9307                                     struct link_params *params)
9308 {
9309         struct bnx2x *bp = params->bp;
9310         u16 tmp1, val;
9311         /* Set option 1G speed */
9312         if ((phy->req_line_speed == SPEED_1000) ||
9313             (phy->media_type == ETH_PHY_SFP_1G_FIBER)) {
9314                 DP(NETIF_MSG_LINK, "Setting 1G force\n");
9315                 bnx2x_cl45_write(bp, phy,
9316                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
9317                 bnx2x_cl45_write(bp, phy,
9318                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
9319                 bnx2x_cl45_read(bp, phy,
9320                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
9321                 DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1);
9322                 /* Power down the XAUI until link is up in case of dual-media
9323                  * and 1G
9324                  */
9325                 if (DUAL_MEDIA(params)) {
9326                         bnx2x_cl45_read(bp, phy,
9327                                         MDIO_PMA_DEVAD,
9328                                         MDIO_PMA_REG_8727_PCS_GP, &val);
9329                         val |= (3<<10);
9330                         bnx2x_cl45_write(bp, phy,
9331                                          MDIO_PMA_DEVAD,
9332                                          MDIO_PMA_REG_8727_PCS_GP, val);
9333                 }
9334         } else if ((phy->req_line_speed == SPEED_AUTO_NEG) &&
9335                    ((phy->speed_cap_mask &
9336                      PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
9337                    ((phy->speed_cap_mask &
9338                       PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
9339                    PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
9340
9341                 DP(NETIF_MSG_LINK, "Setting 1G clause37\n");
9342                 bnx2x_cl45_write(bp, phy,
9343                                  MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
9344                 bnx2x_cl45_write(bp, phy,
9345                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
9346         } else {
9347                 /* Since the 8727 has only single reset pin, need to set the 10G
9348                  * registers although it is default
9349                  */
9350                 bnx2x_cl45_write(bp, phy,
9351                                  MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL,
9352                                  0x0020);
9353                 bnx2x_cl45_write(bp, phy,
9354                                  MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);
9355                 bnx2x_cl45_write(bp, phy,
9356                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
9357                 bnx2x_cl45_write(bp, phy,
9358                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2,
9359                                  0x0008);
9360         }
9361 }
9362
9363 static int bnx2x_8727_config_init(struct bnx2x_phy *phy,
9364                                   struct link_params *params,
9365                                   struct link_vars *vars)
9366 {
9367         u32 tx_en_mode;
9368         u16 tmp1, mod_abs, tmp2;
9369         struct bnx2x *bp = params->bp;
9370         /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
9371
9372         bnx2x_wait_reset_complete(bp, phy, params);
9373
9374         DP(NETIF_MSG_LINK, "Initializing BCM8727\n");
9375
9376         bnx2x_8727_specific_func(phy, params, PHY_INIT);
9377         /* Initially configure MOD_ABS to interrupt when module is
9378          * presence( bit 8)
9379          */
9380         bnx2x_cl45_read(bp, phy,
9381                         MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
9382         /* Set EDC off by setting OPTXLOS signal input to low (bit 9).
9383          * When the EDC is off it locks onto a reference clock and avoids
9384          * becoming 'lost'
9385          */
9386         mod_abs &= ~(1<<8);
9387         if (!(phy->flags & FLAGS_NOC))
9388                 mod_abs &= ~(1<<9);
9389         bnx2x_cl45_write(bp, phy,
9390                          MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9391
9392         /* Enable/Disable PHY transmitter output */
9393         bnx2x_set_disable_pmd_transmit(params, phy, 0);
9394
9395         bnx2x_8727_power_module(bp, phy, 1);
9396
9397         bnx2x_cl45_read(bp, phy,
9398                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
9399
9400         bnx2x_cl45_read(bp, phy,
9401                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
9402
9403         bnx2x_8727_config_speed(phy, params);
9404
9405
9406         /* Set TX PreEmphasis if needed */
9407         if ((params->feature_config_flags &
9408              FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
9409                 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
9410                            phy->tx_preemphasis[0],
9411                            phy->tx_preemphasis[1]);
9412                 bnx2x_cl45_write(bp, phy,
9413                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1,
9414                                  phy->tx_preemphasis[0]);
9415
9416                 bnx2x_cl45_write(bp, phy,
9417                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2,
9418                                  phy->tx_preemphasis[1]);
9419         }
9420
9421         /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
9422          * power mode, if TX Laser is disabled
9423          */
9424         tx_en_mode = REG_RD(bp, params->shmem_base +
9425                             offsetof(struct shmem_region,
9426                                 dev_info.port_hw_config[params->port].sfp_ctrl))
9427                         & PORT_HW_CFG_TX_LASER_MASK;
9428
9429         if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
9430
9431                 DP(NETIF_MSG_LINK, "Enabling TXONOFF_PWRDN_DIS\n");
9432                 bnx2x_cl45_read(bp, phy,
9433                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2);
9434                 tmp2 |= 0x1000;
9435                 tmp2 &= 0xFFEF;
9436                 bnx2x_cl45_write(bp, phy,
9437                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2);
9438                 bnx2x_cl45_read(bp, phy,
9439                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
9440                                 &tmp2);
9441                 bnx2x_cl45_write(bp, phy,
9442                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
9443                                  (tmp2 & 0x7fff));
9444         }
9445
9446         return 0;
9447 }
9448
9449 static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy *phy,
9450                                       struct link_params *params)
9451 {
9452         struct bnx2x *bp = params->bp;
9453         u16 mod_abs, rx_alarm_status;
9454         u32 val = REG_RD(bp, params->shmem_base +
9455                              offsetof(struct shmem_region, dev_info.
9456                                       port_feature_config[params->port].
9457                                       config));
9458         bnx2x_cl45_read(bp, phy,
9459                         MDIO_PMA_DEVAD,
9460                         MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
9461         if (mod_abs & (1<<8)) {
9462
9463                 /* Module is absent */
9464                 DP(NETIF_MSG_LINK,
9465                    "MOD_ABS indication show module is absent\n");
9466                 phy->media_type = ETH_PHY_NOT_PRESENT;
9467                 /* 1. Set mod_abs to detect next module
9468                  *    presence event
9469                  * 2. Set EDC off by setting OPTXLOS signal input to low
9470                  *    (bit 9).
9471                  *    When the EDC is off it locks onto a reference clock and
9472                  *    avoids becoming 'lost'.
9473                  */
9474                 mod_abs &= ~(1<<8);
9475                 if (!(phy->flags & FLAGS_NOC))
9476                         mod_abs &= ~(1<<9);
9477                 bnx2x_cl45_write(bp, phy,
9478                                  MDIO_PMA_DEVAD,
9479                                  MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9480
9481                 /* Clear RX alarm since it stays up as long as
9482                  * the mod_abs wasn't changed
9483                  */
9484                 bnx2x_cl45_read(bp, phy,
9485                                 MDIO_PMA_DEVAD,
9486                                 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9487
9488         } else {
9489                 /* Module is present */
9490                 DP(NETIF_MSG_LINK,
9491                    "MOD_ABS indication show module is present\n");
9492                 /* First disable transmitter, and if the module is ok, the
9493                  * module_detection will enable it
9494                  * 1. Set mod_abs to detect next module absent event ( bit 8)
9495                  * 2. Restore the default polarity of the OPRXLOS signal and
9496                  * this signal will then correctly indicate the presence or
9497                  * absence of the Rx signal. (bit 9)
9498                  */
9499                 mod_abs |= (1<<8);
9500                 if (!(phy->flags & FLAGS_NOC))
9501                         mod_abs |= (1<<9);
9502                 bnx2x_cl45_write(bp, phy,
9503                                  MDIO_PMA_DEVAD,
9504                                  MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
9505
9506                 /* Clear RX alarm since it stays up as long as the mod_abs
9507                  * wasn't changed. This is need to be done before calling the
9508                  * module detection, otherwise it will clear* the link update
9509                  * alarm
9510                  */
9511                 bnx2x_cl45_read(bp, phy,
9512                                 MDIO_PMA_DEVAD,
9513                                 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9514
9515
9516                 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
9517                     PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
9518                         bnx2x_sfp_set_transmitter(params, phy, 0);
9519
9520                 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0)
9521                         bnx2x_sfp_module_detection(phy, params);
9522                 else
9523                         DP(NETIF_MSG_LINK, "SFP+ module is not initialized\n");
9524
9525                 /* Reconfigure link speed based on module type limitations */
9526                 bnx2x_8727_config_speed(phy, params);
9527         }
9528
9529         DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n",
9530                    rx_alarm_status);
9531         /* No need to check link status in case of module plugged in/out */
9532 }
9533
9534 static u8 bnx2x_8727_read_status(struct bnx2x_phy *phy,
9535                                  struct link_params *params,
9536                                  struct link_vars *vars)
9537
9538 {
9539         struct bnx2x *bp = params->bp;
9540         u8 link_up = 0, oc_port = params->port;
9541         u16 link_status = 0;
9542         u16 rx_alarm_status, lasi_ctrl, val1;
9543
9544         /* If PHY is not initialized, do not check link status */
9545         bnx2x_cl45_read(bp, phy,
9546                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
9547                         &lasi_ctrl);
9548         if (!lasi_ctrl)
9549                 return 0;
9550
9551         /* Check the LASI on Rx */
9552         bnx2x_cl45_read(bp, phy,
9553                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT,
9554                         &rx_alarm_status);
9555         vars->line_speed = 0;
9556         DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS  0x%x\n", rx_alarm_status);
9557
9558         bnx2x_sfp_mask_fault(bp, phy, MDIO_PMA_LASI_TXSTAT,
9559                              MDIO_PMA_LASI_TXCTRL);
9560
9561         bnx2x_cl45_read(bp, phy,
9562                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
9563
9564         DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1);
9565
9566         /* Clear MSG-OUT */
9567         bnx2x_cl45_read(bp, phy,
9568                         MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
9569
9570         /* If a module is present and there is need to check
9571          * for over current
9572          */
9573         if (!(phy->flags & FLAGS_NOC) && !(rx_alarm_status & (1<<5))) {
9574                 /* Check over-current using 8727 GPIO0 input*/
9575                 bnx2x_cl45_read(bp, phy,
9576                                 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL,
9577                                 &val1);
9578
9579                 if ((val1 & (1<<8)) == 0) {
9580                         if (!CHIP_IS_E1x(bp))
9581                                 oc_port = BP_PATH(bp) + (params->port << 1);
9582                         DP(NETIF_MSG_LINK,
9583                            "8727 Power fault has been detected on port %d\n",
9584                            oc_port);
9585                         netdev_err(bp->dev, "Error: Power fault on Port %d has "
9586                                             "been detected and the power to "
9587                                             "that SFP+ module has been removed "
9588                                             "to prevent failure of the card. "
9589                                             "Please remove the SFP+ module and "
9590                                             "restart the system to clear this "
9591                                             "error.\n",
9592                          oc_port);
9593                         /* Disable all RX_ALARMs except for mod_abs */
9594                         bnx2x_cl45_write(bp, phy,
9595                                          MDIO_PMA_DEVAD,
9596                                          MDIO_PMA_LASI_RXCTRL, (1<<5));
9597
9598                         bnx2x_cl45_read(bp, phy,
9599                                         MDIO_PMA_DEVAD,
9600                                         MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
9601                         /* Wait for module_absent_event */
9602                         val1 |= (1<<8);
9603                         bnx2x_cl45_write(bp, phy,
9604                                          MDIO_PMA_DEVAD,
9605                                          MDIO_PMA_REG_PHY_IDENTIFIER, val1);
9606                         /* Clear RX alarm */
9607                         bnx2x_cl45_read(bp, phy,
9608                                 MDIO_PMA_DEVAD,
9609                                 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
9610                         bnx2x_8727_power_module(params->bp, phy, 0);
9611                         return 0;
9612                 }
9613         } /* Over current check */
9614
9615         /* When module absent bit is set, check module */
9616         if (rx_alarm_status & (1<<5)) {
9617                 bnx2x_8727_handle_mod_abs(phy, params);
9618                 /* Enable all mod_abs and link detection bits */
9619                 bnx2x_cl45_write(bp, phy,
9620                                  MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9621                                  ((1<<5) | (1<<2)));
9622         }
9623
9624         if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) {
9625                 DP(NETIF_MSG_LINK, "Enabling 8727 TX laser\n");
9626                 bnx2x_sfp_set_transmitter(params, phy, 1);
9627         } else {
9628                 DP(NETIF_MSG_LINK, "Tx is disabled\n");
9629                 return 0;
9630         }
9631
9632         bnx2x_cl45_read(bp, phy,
9633                         MDIO_PMA_DEVAD,
9634                         MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status);
9635
9636         /* Bits 0..2 --> speed detected,
9637          * Bits 13..15--> link is down
9638          */
9639         if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
9640                 link_up = 1;
9641                 vars->line_speed = SPEED_10000;
9642                 DP(NETIF_MSG_LINK, "port %x: External link up in 10G\n",
9643                            params->port);
9644         } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
9645                 link_up = 1;
9646                 vars->line_speed = SPEED_1000;
9647                 DP(NETIF_MSG_LINK, "port %x: External link up in 1G\n",
9648                            params->port);
9649         } else {
9650                 link_up = 0;
9651                 DP(NETIF_MSG_LINK, "port %x: External link is down\n",
9652                            params->port);
9653         }
9654
9655         /* Capture 10G link fault. */
9656         if (vars->line_speed == SPEED_10000) {
9657                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
9658                             MDIO_PMA_LASI_TXSTAT, &val1);
9659
9660                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD,
9661                             MDIO_PMA_LASI_TXSTAT, &val1);
9662
9663                 if (val1 & (1<<0)) {
9664                         vars->fault_detected = 1;
9665                 }
9666         }
9667
9668         if (link_up) {
9669                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
9670                 vars->duplex = DUPLEX_FULL;
9671                 DP(NETIF_MSG_LINK, "duplex = 0x%x\n", vars->duplex);
9672         }
9673
9674         if ((DUAL_MEDIA(params)) &&
9675             (phy->req_line_speed == SPEED_1000)) {
9676                 bnx2x_cl45_read(bp, phy,
9677                                 MDIO_PMA_DEVAD,
9678                                 MDIO_PMA_REG_8727_PCS_GP, &val1);
9679                 /* In case of dual-media board and 1G, power up the XAUI side,
9680                  * otherwise power it down. For 10G it is done automatically
9681                  */
9682                 if (link_up)
9683                         val1 &= ~(3<<10);
9684                 else
9685                         val1 |= (3<<10);
9686                 bnx2x_cl45_write(bp, phy,
9687                                  MDIO_PMA_DEVAD,
9688                                  MDIO_PMA_REG_8727_PCS_GP, val1);
9689         }
9690         return link_up;
9691 }
9692
9693 static void bnx2x_8727_link_reset(struct bnx2x_phy *phy,
9694                                   struct link_params *params)
9695 {
9696         struct bnx2x *bp = params->bp;
9697
9698         /* Enable/Disable PHY transmitter output */
9699         bnx2x_set_disable_pmd_transmit(params, phy, 1);
9700
9701         /* Disable Transmitter */
9702         bnx2x_sfp_set_transmitter(params, phy, 0);
9703         /* Clear LASI */
9704         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0);
9705
9706 }
9707
9708 /******************************************************************/
9709 /*              BCM8481/BCM84823/BCM84833 PHY SECTION             */
9710 /******************************************************************/
9711 static int bnx2x_is_8483x_8485x(struct bnx2x_phy *phy)
9712 {
9713         return ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
9714                 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) ||
9715                 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858));
9716 }
9717
9718 static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy *phy,
9719                                             struct bnx2x *bp,
9720                                             u8 port)
9721 {
9722         u16 val, fw_ver2, cnt, i;
9723         static struct bnx2x_reg_set reg_set[] = {
9724                 {MDIO_PMA_DEVAD, 0xA819, 0x0014},
9725                 {MDIO_PMA_DEVAD, 0xA81A, 0xc200},
9726                 {MDIO_PMA_DEVAD, 0xA81B, 0x0000},
9727                 {MDIO_PMA_DEVAD, 0xA81C, 0x0300},
9728                 {MDIO_PMA_DEVAD, 0xA817, 0x0009}
9729         };
9730         u16 fw_ver1;
9731
9732         if (bnx2x_is_8483x_8485x(phy)) {
9733                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1);
9734                 if (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858)
9735                         fw_ver1 &= 0xfff;
9736                 bnx2x_save_spirom_version(bp, port, fw_ver1, phy->ver_addr);
9737         } else {
9738                 /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */
9739                 /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
9740                 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
9741                         bnx2x_cl45_write(bp, phy, reg_set[i].devad,
9742                                          reg_set[i].reg, reg_set[i].val);
9743
9744                 for (cnt = 0; cnt < 100; cnt++) {
9745                         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9746                         if (val & 1)
9747                                 break;
9748                         udelay(5);
9749                 }
9750                 if (cnt == 100) {
9751                         DP(NETIF_MSG_LINK, "Unable to read 848xx "
9752                                         "phy fw version(1)\n");
9753                         bnx2x_save_spirom_version(bp, port, 0,
9754                                                   phy->ver_addr);
9755                         return;
9756                 }
9757
9758
9759                 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
9760                 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);
9761                 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
9762                 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);
9763                 for (cnt = 0; cnt < 100; cnt++) {
9764                         bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val);
9765                         if (val & 1)
9766                                 break;
9767                         udelay(5);
9768                 }
9769                 if (cnt == 100) {
9770                         DP(NETIF_MSG_LINK, "Unable to read 848xx phy fw "
9771                                         "version(2)\n");
9772                         bnx2x_save_spirom_version(bp, port, 0,
9773                                                   phy->ver_addr);
9774                         return;
9775                 }
9776
9777                 /* lower 16 bits of the register SPI_FW_STATUS */
9778                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);
9779                 /* upper 16 bits of register SPI_FW_STATUS */
9780                 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);
9781
9782                 bnx2x_save_spirom_version(bp, port, (fw_ver2<<16) | fw_ver1,
9783                                           phy->ver_addr);
9784         }
9785
9786 }
9787 static void bnx2x_848xx_set_led(struct bnx2x *bp,
9788                                 struct bnx2x_phy *phy)
9789 {
9790         u16 val, led3_blink_rate, offset, i;
9791         static struct bnx2x_reg_set reg_set[] = {
9792                 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED1_MASK, 0x0080},
9793                 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED2_MASK, 0x0018},
9794                 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_MASK, 0x0006},
9795                 {MDIO_PMA_DEVAD, MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH,
9796                         MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ},
9797                 {MDIO_AN_DEVAD, 0xFFFB, 0xFFFD}
9798         };
9799
9800         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) {
9801                 /* Set LED5 source */
9802                 bnx2x_cl45_write(bp, phy,
9803                                  MDIO_PMA_DEVAD,
9804                                  MDIO_PMA_REG_8481_LED5_MASK,
9805                                  0x90);
9806                 led3_blink_rate = 0x000f;
9807         } else {
9808                 led3_blink_rate = 0x0000;
9809         }
9810         /* Set LED3 BLINK */
9811         bnx2x_cl45_write(bp, phy,
9812                          MDIO_PMA_DEVAD,
9813                          MDIO_PMA_REG_8481_LED3_BLINK,
9814                          led3_blink_rate);
9815
9816         /* PHYC_CTL_LED_CTL */
9817         bnx2x_cl45_read(bp, phy,
9818                         MDIO_PMA_DEVAD,
9819                         MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
9820         val &= 0xFE00;
9821         val |= 0x0092;
9822
9823         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858)
9824                 val |= 2 << 12; /* LED5 ON based on source */
9825
9826         bnx2x_cl45_write(bp, phy,
9827                          MDIO_PMA_DEVAD,
9828                          MDIO_PMA_REG_8481_LINK_SIGNAL, val);
9829
9830         for (i = 0; i < ARRAY_SIZE(reg_set); i++)
9831                 bnx2x_cl45_write(bp, phy, reg_set[i].devad, reg_set[i].reg,
9832                                  reg_set[i].val);
9833
9834         if (bnx2x_is_8483x_8485x(phy))
9835                 offset = MDIO_PMA_REG_84833_CTL_LED_CTL_1;
9836         else
9837                 offset = MDIO_PMA_REG_84823_CTL_LED_CTL_1;
9838
9839         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858)
9840                 val = MDIO_PMA_REG_84858_ALLOW_GPHY_ACT |
9841                       MDIO_PMA_REG_84823_LED3_STRETCH_EN;
9842         else
9843                 val = MDIO_PMA_REG_84823_LED3_STRETCH_EN;
9844
9845         /* stretch_en for LEDs */
9846         bnx2x_cl45_read_or_write(bp, phy,
9847                                  MDIO_PMA_DEVAD,
9848                                  offset,
9849                                  val);
9850 }
9851
9852 static void bnx2x_848xx_specific_func(struct bnx2x_phy *phy,
9853                                       struct link_params *params,
9854                                       u32 action)
9855 {
9856         struct bnx2x *bp = params->bp;
9857         switch (action) {
9858         case PHY_INIT:
9859                 if (bnx2x_is_8483x_8485x(phy)) {
9860                         /* Save spirom version */
9861                         bnx2x_save_848xx_spirom_version(phy, bp, params->port);
9862                 }
9863                 /* This phy uses the NIG latch mechanism since link indication
9864                  * arrives through its LED4 and not via its LASI signal, so we
9865                  * get steady signal instead of clear on read
9866                  */
9867                 bnx2x_bits_en(bp, NIG_REG_LATCH_BC_0 + params->port*4,
9868                               1 << NIG_LATCH_BC_ENABLE_MI_INT);
9869
9870                 bnx2x_848xx_set_led(bp, phy);
9871                 break;
9872         }
9873 }
9874
9875 static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy *phy,
9876                                        struct link_params *params,
9877                                        struct link_vars *vars)
9878 {
9879         struct bnx2x *bp = params->bp;
9880         u16 autoneg_val, an_1000_val, an_10_100_val;
9881
9882         bnx2x_848xx_specific_func(phy, params, PHY_INIT);
9883         bnx2x_cl45_write(bp, phy,
9884                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);
9885
9886         /* set 1000 speed advertisement */
9887         bnx2x_cl45_read(bp, phy,
9888                         MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9889                         &an_1000_val);
9890
9891         bnx2x_ext_phy_set_pause(params, phy, vars);
9892         bnx2x_cl45_read(bp, phy,
9893                         MDIO_AN_DEVAD,
9894                         MDIO_AN_REG_8481_LEGACY_AN_ADV,
9895                         &an_10_100_val);
9896         bnx2x_cl45_read(bp, phy,
9897                         MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL,
9898                         &autoneg_val);
9899         /* Disable forced speed */
9900         autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
9901         an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8));
9902
9903         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9904              (phy->speed_cap_mask &
9905              PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
9906             (phy->req_line_speed == SPEED_1000)) {
9907                 an_1000_val |= (1<<8);
9908                 autoneg_val |= (1<<9 | 1<<12);
9909                 if (phy->req_duplex == DUPLEX_FULL)
9910                         an_1000_val |= (1<<9);
9911                 DP(NETIF_MSG_LINK, "Advertising 1G\n");
9912         } else
9913                 an_1000_val &= ~((1<<8) | (1<<9));
9914
9915         bnx2x_cl45_write(bp, phy,
9916                          MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
9917                          an_1000_val);
9918
9919         /* Set 10/100 speed advertisement */
9920         if (phy->req_line_speed == SPEED_AUTO_NEG) {
9921                 if (phy->speed_cap_mask &
9922                     PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) {
9923                         /* Enable autoneg and restart autoneg for legacy speeds
9924                          */
9925                         autoneg_val |= (1<<9 | 1<<12);
9926                         an_10_100_val |= (1<<8);
9927                         DP(NETIF_MSG_LINK, "Advertising 100M-FD\n");
9928                 }
9929
9930                 if (phy->speed_cap_mask &
9931                     PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) {
9932                         /* Enable autoneg and restart autoneg for legacy speeds
9933                          */
9934                         autoneg_val |= (1<<9 | 1<<12);
9935                         an_10_100_val |= (1<<7);
9936                         DP(NETIF_MSG_LINK, "Advertising 100M-HD\n");
9937                 }
9938
9939                 if ((phy->speed_cap_mask &
9940                      PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
9941                     (phy->supported & SUPPORTED_10baseT_Full)) {
9942                         an_10_100_val |= (1<<6);
9943                         autoneg_val |= (1<<9 | 1<<12);
9944                         DP(NETIF_MSG_LINK, "Advertising 10M-FD\n");
9945                 }
9946
9947                 if ((phy->speed_cap_mask &
9948                      PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) &&
9949                     (phy->supported & SUPPORTED_10baseT_Half)) {
9950                         an_10_100_val |= (1<<5);
9951                         autoneg_val |= (1<<9 | 1<<12);
9952                         DP(NETIF_MSG_LINK, "Advertising 10M-HD\n");
9953                 }
9954         }
9955
9956         /* Only 10/100 are allowed to work in FORCE mode */
9957         if ((phy->req_line_speed == SPEED_100) &&
9958             (phy->supported &
9959              (SUPPORTED_100baseT_Half |
9960               SUPPORTED_100baseT_Full))) {
9961                 autoneg_val |= (1<<13);
9962                 /* Enabled AUTO-MDIX when autoneg is disabled */
9963                 bnx2x_cl45_write(bp, phy,
9964                                  MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9965                                  (1<<15 | 1<<9 | 7<<0));
9966                 /* The PHY needs this set even for forced link. */
9967                 an_10_100_val |= (1<<8) | (1<<7);
9968                 DP(NETIF_MSG_LINK, "Setting 100M force\n");
9969         }
9970         if ((phy->req_line_speed == SPEED_10) &&
9971             (phy->supported &
9972              (SUPPORTED_10baseT_Half |
9973               SUPPORTED_10baseT_Full))) {
9974                 /* Enabled AUTO-MDIX when autoneg is disabled */
9975                 bnx2x_cl45_write(bp, phy,
9976                                  MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
9977                                  (1<<15 | 1<<9 | 7<<0));
9978                 DP(NETIF_MSG_LINK, "Setting 10M force\n");
9979         }
9980
9981         bnx2x_cl45_write(bp, phy,
9982                          MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV,
9983                          an_10_100_val);
9984
9985         if (phy->req_duplex == DUPLEX_FULL)
9986                 autoneg_val |= (1<<8);
9987
9988         /* Always write this if this is not 84833/4.
9989          * For 84833/4, write it only when it's a forced speed.
9990          */
9991         if (!bnx2x_is_8483x_8485x(phy) ||
9992             ((autoneg_val & (1<<12)) == 0))
9993                 bnx2x_cl45_write(bp, phy,
9994                          MDIO_AN_DEVAD,
9995                          MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);
9996
9997         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
9998             (phy->speed_cap_mask &
9999              PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
10000                 (phy->req_line_speed == SPEED_10000)) {
10001                         DP(NETIF_MSG_LINK, "Advertising 10G\n");
10002                         /* Restart autoneg for 10G*/
10003
10004                         bnx2x_cl45_read_or_write(
10005                                 bp, phy,
10006                                 MDIO_AN_DEVAD,
10007                                 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
10008                                 0x1000);
10009                         bnx2x_cl45_write(bp, phy,
10010                                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL,
10011                                          0x3200);
10012         } else
10013                 bnx2x_cl45_write(bp, phy,
10014                                  MDIO_AN_DEVAD,
10015                                  MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
10016                                  1);
10017
10018         return 0;
10019 }
10020
10021 static int bnx2x_8481_config_init(struct bnx2x_phy *phy,
10022                                   struct link_params *params,
10023                                   struct link_vars *vars)
10024 {
10025         struct bnx2x *bp = params->bp;
10026         /* Restore normal power mode*/
10027         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
10028                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
10029
10030         /* HW reset */
10031         bnx2x_ext_phy_hw_reset(bp, params->port);
10032         bnx2x_wait_reset_complete(bp, phy, params);
10033
10034         bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
10035         return bnx2x_848xx_cmn_config_init(phy, params, vars);
10036 }
10037
10038 #define PHY848xx_CMDHDLR_WAIT 300
10039 #define PHY848xx_CMDHDLR_MAX_ARGS 5
10040
10041 static int bnx2x_84858_cmd_hdlr(struct bnx2x_phy *phy,
10042                                 struct link_params *params,
10043                                 u16 fw_cmd,
10044                                 u16 cmd_args[], int argc)
10045 {
10046         int idx;
10047         u16 val;
10048         struct bnx2x *bp = params->bp;
10049
10050         /* Step 1: Poll the STATUS register to see whether the previous command
10051          * is in progress or the system is busy (CMD_IN_PROGRESS or
10052          * SYSTEM_BUSY). If previous command is in progress or system is busy,
10053          * check again until the previous command finishes execution and the
10054          * system is available for taking command
10055          */
10056
10057         for (idx = 0; idx < PHY848xx_CMDHDLR_WAIT; idx++) {
10058                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10059                                 MDIO_848xx_CMD_HDLR_STATUS, &val);
10060                 if ((val != PHY84858_STATUS_CMD_IN_PROGRESS) &&
10061                     (val != PHY84858_STATUS_CMD_SYSTEM_BUSY))
10062                         break;
10063                 usleep_range(1000, 2000);
10064         }
10065         if (idx >= PHY848xx_CMDHDLR_WAIT) {
10066                 DP(NETIF_MSG_LINK, "FW cmd: FW not ready.\n");
10067                 return -EINVAL;
10068         }
10069
10070         /* Step2: If any parameters are required for the function, write them
10071          * to the required DATA registers
10072          */
10073
10074         for (idx = 0; idx < argc; idx++) {
10075                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10076                                  MDIO_848xx_CMD_HDLR_DATA1 + idx,
10077                                  cmd_args[idx]);
10078         }
10079
10080         /* Step3: When the firmware is ready for commands, write the 'Command
10081          * code' to the CMD register
10082          */
10083         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10084                          MDIO_848xx_CMD_HDLR_COMMAND, fw_cmd);
10085
10086         /* Step4: Once the command has been written, poll the STATUS register
10087          * to check whether the command has completed (CMD_COMPLETED_PASS/
10088          * CMD_FOR_CMDS or CMD_COMPLETED_ERROR).
10089          */
10090
10091         for (idx = 0; idx < PHY848xx_CMDHDLR_WAIT; idx++) {
10092                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10093                                 MDIO_848xx_CMD_HDLR_STATUS, &val);
10094                 if ((val == PHY84858_STATUS_CMD_COMPLETE_PASS) ||
10095                     (val == PHY84858_STATUS_CMD_COMPLETE_ERROR))
10096                         break;
10097                 usleep_range(1000, 2000);
10098         }
10099         if ((idx >= PHY848xx_CMDHDLR_WAIT) ||
10100             (val == PHY84858_STATUS_CMD_COMPLETE_ERROR)) {
10101                 DP(NETIF_MSG_LINK, "FW cmd failed.\n");
10102                 return -EINVAL;
10103         }
10104         /* Step5: Once the command has completed, read the specficied DATA
10105          * registers for any saved results for the command, if applicable
10106          */
10107
10108         /* Gather returning data */
10109         for (idx = 0; idx < argc; idx++) {
10110                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10111                                 MDIO_848xx_CMD_HDLR_DATA1 + idx,
10112                                 &cmd_args[idx]);
10113         }
10114
10115         return 0;
10116 }
10117
10118 static int bnx2x_84833_cmd_hdlr(struct bnx2x_phy *phy,
10119                                 struct link_params *params, u16 fw_cmd,
10120                                 u16 cmd_args[], int argc, int process)
10121 {
10122         int idx;
10123         u16 val;
10124         struct bnx2x *bp = params->bp;
10125         int rc = 0;
10126
10127         if (process == PHY84833_MB_PROCESS2) {
10128                 /* Write CMD_OPEN_OVERRIDE to STATUS reg */
10129                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10130                                  MDIO_848xx_CMD_HDLR_STATUS,
10131                                  PHY84833_STATUS_CMD_OPEN_OVERRIDE);
10132         }
10133
10134         for (idx = 0; idx < PHY848xx_CMDHDLR_WAIT; idx++) {
10135                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10136                                 MDIO_848xx_CMD_HDLR_STATUS, &val);
10137                 if (val == PHY84833_STATUS_CMD_OPEN_FOR_CMDS)
10138                         break;
10139                 usleep_range(1000, 2000);
10140         }
10141         if (idx >= PHY848xx_CMDHDLR_WAIT) {
10142                 DP(NETIF_MSG_LINK, "FW cmd: FW not ready.\n");
10143                 /* if the status is CMD_COMPLETE_PASS or CMD_COMPLETE_ERROR
10144                  * clear the status to CMD_CLEAR_COMPLETE
10145                  */
10146                 if (val == PHY84833_STATUS_CMD_COMPLETE_PASS ||
10147                     val == PHY84833_STATUS_CMD_COMPLETE_ERROR) {
10148                         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10149                                          MDIO_848xx_CMD_HDLR_STATUS,
10150                                          PHY84833_STATUS_CMD_CLEAR_COMPLETE);
10151                 }
10152                 return -EINVAL;
10153         }
10154         if (process == PHY84833_MB_PROCESS1 ||
10155             process == PHY84833_MB_PROCESS2) {
10156                 /* Prepare argument(s) */
10157                 for (idx = 0; idx < argc; idx++) {
10158                         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10159                                          MDIO_848xx_CMD_HDLR_DATA1 + idx,
10160                                          cmd_args[idx]);
10161                 }
10162         }
10163
10164         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10165                         MDIO_848xx_CMD_HDLR_COMMAND, fw_cmd);
10166         for (idx = 0; idx < PHY848xx_CMDHDLR_WAIT; idx++) {
10167                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10168                                 MDIO_848xx_CMD_HDLR_STATUS, &val);
10169                 if ((val == PHY84833_STATUS_CMD_COMPLETE_PASS) ||
10170                     (val == PHY84833_STATUS_CMD_COMPLETE_ERROR))
10171                         break;
10172                 usleep_range(1000, 2000);
10173         }
10174         if ((idx >= PHY848xx_CMDHDLR_WAIT) ||
10175             (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) {
10176                 DP(NETIF_MSG_LINK, "FW cmd failed.\n");
10177                 rc = -EINVAL;
10178         }
10179         if (process == PHY84833_MB_PROCESS3 && rc == 0) {
10180                 /* Gather returning data */
10181                 for (idx = 0; idx < argc; idx++) {
10182                         bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10183                                         MDIO_848xx_CMD_HDLR_DATA1 + idx,
10184                                         &cmd_args[idx]);
10185                 }
10186         }
10187         if (val == PHY84833_STATUS_CMD_COMPLETE_ERROR ||
10188             val == PHY84833_STATUS_CMD_COMPLETE_PASS) {
10189                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10190                                  MDIO_848xx_CMD_HDLR_STATUS,
10191                                  PHY84833_STATUS_CMD_CLEAR_COMPLETE);
10192         }
10193         return rc;
10194 }
10195
10196 static int bnx2x_848xx_cmd_hdlr(struct bnx2x_phy *phy,
10197                                 struct link_params *params,
10198                                 u16 fw_cmd,
10199                                            u16 cmd_args[], int argc,
10200                                            int process)
10201 {
10202         struct bnx2x *bp = params->bp;
10203
10204         if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) ||
10205             (REG_RD(bp, params->shmem2_base +
10206                     offsetof(struct shmem2_region,
10207                              link_attr_sync[params->port])) &
10208              LINK_ATTR_84858)) {
10209                 return bnx2x_84858_cmd_hdlr(phy, params, fw_cmd, cmd_args,
10210                                             argc);
10211         } else {
10212                 return bnx2x_84833_cmd_hdlr(phy, params, fw_cmd, cmd_args,
10213                                             argc, process);
10214         }
10215 }
10216
10217 static int bnx2x_848xx_pair_swap_cfg(struct bnx2x_phy *phy,
10218                                      struct link_params *params,
10219                                      struct link_vars *vars)
10220 {
10221         u32 pair_swap;
10222         u16 data[PHY848xx_CMDHDLR_MAX_ARGS];
10223         int status;
10224         struct bnx2x *bp = params->bp;
10225
10226         /* Check for configuration. */
10227         pair_swap = REG_RD(bp, params->shmem_base +
10228                            offsetof(struct shmem_region,
10229                         dev_info.port_hw_config[params->port].xgbt_phy_cfg)) &
10230                 PORT_HW_CFG_RJ45_PAIR_SWAP_MASK;
10231
10232         if (pair_swap == 0)
10233                 return 0;
10234
10235         /* Only the second argument is used for this command */
10236         data[1] = (u16)pair_swap;
10237
10238         status = bnx2x_848xx_cmd_hdlr(phy, params,
10239                                       PHY848xx_CMD_SET_PAIR_SWAP, data,
10240                                       2, PHY84833_MB_PROCESS2);
10241         if (status == 0)
10242                 DP(NETIF_MSG_LINK, "Pairswap OK, val=0x%x\n", data[1]);
10243
10244         return status;
10245 }
10246
10247 static u8 bnx2x_84833_get_reset_gpios(struct bnx2x *bp,
10248                                       u32 shmem_base_path[],
10249                                       u32 chip_id)
10250 {
10251         u32 reset_pin[2];
10252         u32 idx;
10253         u8 reset_gpios;
10254         if (CHIP_IS_E3(bp)) {
10255                 /* Assume that these will be GPIOs, not EPIOs. */
10256                 for (idx = 0; idx < 2; idx++) {
10257                         /* Map config param to register bit. */
10258                         reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
10259                                 offsetof(struct shmem_region,
10260                                 dev_info.port_hw_config[0].e3_cmn_pin_cfg));
10261                         reset_pin[idx] = (reset_pin[idx] &
10262                                 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10263                                 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10264                         reset_pin[idx] -= PIN_CFG_GPIO0_P0;
10265                         reset_pin[idx] = (1 << reset_pin[idx]);
10266                 }
10267                 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
10268         } else {
10269                 /* E2, look from diff place of shmem. */
10270                 for (idx = 0; idx < 2; idx++) {
10271                         reset_pin[idx] = REG_RD(bp, shmem_base_path[idx] +
10272                                 offsetof(struct shmem_region,
10273                                 dev_info.port_hw_config[0].default_cfg));
10274                         reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK;
10275                         reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0;
10276                         reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT;
10277                         reset_pin[idx] = (1 << reset_pin[idx]);
10278                 }
10279                 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]);
10280         }
10281
10282         return reset_gpios;
10283 }
10284
10285 static int bnx2x_84833_hw_reset_phy(struct bnx2x_phy *phy,
10286                                 struct link_params *params)
10287 {
10288         struct bnx2x *bp = params->bp;
10289         u8 reset_gpios;
10290         u32 other_shmem_base_addr = REG_RD(bp, params->shmem2_base +
10291                                 offsetof(struct shmem2_region,
10292                                 other_shmem_base_addr));
10293
10294         u32 shmem_base_path[2];
10295
10296         /* Work around for 84833 LED failure inside RESET status */
10297         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
10298                 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
10299                 MDIO_AN_REG_8481_MII_CTRL_FORCE_1G);
10300         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
10301                 MDIO_AN_REG_8481_1G_100T_EXT_CTRL,
10302                 MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF);
10303
10304         shmem_base_path[0] = params->shmem_base;
10305         shmem_base_path[1] = other_shmem_base_addr;
10306
10307         reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path,
10308                                                   params->chip_id);
10309
10310         bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
10311         udelay(10);
10312         DP(NETIF_MSG_LINK, "84833 hw reset on pin values 0x%x\n",
10313                 reset_gpios);
10314
10315         return 0;
10316 }
10317
10318 static int bnx2x_8483x_disable_eee(struct bnx2x_phy *phy,
10319                                    struct link_params *params,
10320                                    struct link_vars *vars)
10321 {
10322         int rc;
10323         struct bnx2x *bp = params->bp;
10324         u16 cmd_args = 0;
10325
10326         DP(NETIF_MSG_LINK, "Don't Advertise 10GBase-T EEE\n");
10327
10328         /* Prevent Phy from working in EEE and advertising it */
10329         rc = bnx2x_848xx_cmd_hdlr(phy, params, PHY848xx_CMD_SET_EEE_MODE,
10330                                   &cmd_args, 1, PHY84833_MB_PROCESS1);
10331         if (rc) {
10332                 DP(NETIF_MSG_LINK, "EEE disable failed.\n");
10333                 return rc;
10334         }
10335
10336         return bnx2x_eee_disable(phy, params, vars);
10337 }
10338
10339 static int bnx2x_8483x_enable_eee(struct bnx2x_phy *phy,
10340                                    struct link_params *params,
10341                                    struct link_vars *vars)
10342 {
10343         int rc;
10344         struct bnx2x *bp = params->bp;
10345         u16 cmd_args = 1;
10346
10347         rc = bnx2x_848xx_cmd_hdlr(phy, params, PHY848xx_CMD_SET_EEE_MODE,
10348                                   &cmd_args, 1, PHY84833_MB_PROCESS1);
10349         if (rc) {
10350                 DP(NETIF_MSG_LINK, "EEE enable failed.\n");
10351                 return rc;
10352         }
10353
10354         return bnx2x_eee_advertise(phy, params, vars, SHMEM_EEE_10G_ADV);
10355 }
10356
10357 #define PHY84833_CONSTANT_LATENCY 1193
10358 static int bnx2x_848x3_config_init(struct bnx2x_phy *phy,
10359                                    struct link_params *params,
10360                                    struct link_vars *vars)
10361 {
10362         struct bnx2x *bp = params->bp;
10363         u8 port, initialize = 1;
10364         u16 val;
10365         u32 actual_phy_selection;
10366         u16 cmd_args[PHY848xx_CMDHDLR_MAX_ARGS];
10367         int rc = 0;
10368
10369         usleep_range(1000, 2000);
10370
10371         if (!(CHIP_IS_E1x(bp)))
10372                 port = BP_PATH(bp);
10373         else
10374                 port = params->port;
10375
10376         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
10377                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
10378                                MISC_REGISTERS_GPIO_OUTPUT_HIGH,
10379                                port);
10380         } else {
10381                 /* MDIO reset */
10382                 bnx2x_cl45_write(bp, phy,
10383                                 MDIO_PMA_DEVAD,
10384                                 MDIO_PMA_REG_CTRL, 0x8000);
10385         }
10386
10387         bnx2x_wait_reset_complete(bp, phy, params);
10388
10389         /* Wait for GPHY to come out of reset */
10390         msleep(50);
10391         if (!bnx2x_is_8483x_8485x(phy)) {
10392                 /* BCM84823 requires that XGXS links up first @ 10G for normal
10393                  * behavior.
10394                  */
10395                 u16 temp;
10396                 temp = vars->line_speed;
10397                 vars->line_speed = SPEED_10000;
10398                 bnx2x_set_autoneg(&params->phy[INT_PHY], params, vars, 0);
10399                 bnx2x_program_serdes(&params->phy[INT_PHY], params, vars);
10400                 vars->line_speed = temp;
10401         }
10402         /* Check if this is actually BCM84858 */
10403         if (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) {
10404                 u16 hw_rev;
10405
10406                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10407                                 MDIO_AN_REG_848xx_ID_MSB, &hw_rev);
10408                 if (hw_rev == BCM84858_PHY_ID) {
10409                         params->link_attr_sync |= LINK_ATTR_84858;
10410                         bnx2x_update_link_attr(params, params->link_attr_sync);
10411                 }
10412         }
10413
10414         /* Set dual-media configuration according to configuration */
10415         bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10416                         MDIO_CTL_REG_84823_MEDIA, &val);
10417         val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
10418                  MDIO_CTL_REG_84823_MEDIA_LINE_MASK |
10419                  MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN |
10420                  MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK |
10421                  MDIO_CTL_REG_84823_MEDIA_FIBER_1G);
10422
10423         if (CHIP_IS_E3(bp)) {
10424                 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
10425                          MDIO_CTL_REG_84823_MEDIA_LINE_MASK);
10426         } else {
10427                 val |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI |
10428                         MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L);
10429         }
10430
10431         actual_phy_selection = bnx2x_phy_selection(params);
10432
10433         switch (actual_phy_selection) {
10434         case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
10435                 /* Do nothing. Essentially this is like the priority copper */
10436                 break;
10437         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
10438                 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER;
10439                 break;
10440         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
10441                 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER;
10442                 break;
10443         case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
10444                 /* Do nothing here. The first PHY won't be initialized at all */
10445                 break;
10446         case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
10447                 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN;
10448                 initialize = 0;
10449                 break;
10450         }
10451         if (params->phy[EXT_PHY2].req_line_speed == SPEED_1000)
10452                 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G;
10453
10454         bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10455                          MDIO_CTL_REG_84823_MEDIA, val);
10456         DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n",
10457                    params->multi_phy_config, val);
10458
10459         if (bnx2x_is_8483x_8485x(phy)) {
10460                 bnx2x_848xx_pair_swap_cfg(phy, params, vars);
10461
10462                 /* Keep AutogrEEEn disabled. */
10463                 cmd_args[0] = 0x0;
10464                 cmd_args[1] = 0x0;
10465                 cmd_args[2] = PHY84833_CONSTANT_LATENCY + 1;
10466                 cmd_args[3] = PHY84833_CONSTANT_LATENCY;
10467                 rc = bnx2x_848xx_cmd_hdlr(phy, params,
10468                                           PHY848xx_CMD_SET_EEE_MODE, cmd_args,
10469                                           4, PHY84833_MB_PROCESS1);
10470                 if (rc)
10471                         DP(NETIF_MSG_LINK, "Cfg AutogrEEEn failed.\n");
10472         }
10473         if (initialize)
10474                 rc = bnx2x_848xx_cmn_config_init(phy, params, vars);
10475         else
10476                 bnx2x_save_848xx_spirom_version(phy, bp, params->port);
10477         /* 84833 PHY has a better feature and doesn't need to support this. */
10478         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
10479                 u32 cms_enable = REG_RD(bp, params->shmem_base +
10480                         offsetof(struct shmem_region,
10481                         dev_info.port_hw_config[params->port].default_cfg)) &
10482                         PORT_HW_CFG_ENABLE_CMS_MASK;
10483
10484                 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10485                                 MDIO_CTL_REG_84823_USER_CTRL_REG, &val);
10486                 if (cms_enable)
10487                         val |= MDIO_CTL_REG_84823_USER_CTRL_CMS;
10488                 else
10489                         val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS;
10490                 bnx2x_cl45_write(bp, phy, MDIO_CTL_DEVAD,
10491                                  MDIO_CTL_REG_84823_USER_CTRL_REG, val);
10492         }
10493
10494         bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD,
10495                         MDIO_84833_TOP_CFG_FW_REV, &val);
10496
10497         /* Configure EEE support */
10498         if ((val >= MDIO_84833_TOP_CFG_FW_EEE) &&
10499             (val != MDIO_84833_TOP_CFG_FW_NO_EEE) &&
10500             bnx2x_eee_has_cap(params)) {
10501                 rc = bnx2x_eee_initial_config(params, vars, SHMEM_EEE_10G_ADV);
10502                 if (rc) {
10503                         DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n");
10504                         bnx2x_8483x_disable_eee(phy, params, vars);
10505                         return rc;
10506                 }
10507
10508                 if ((phy->req_duplex == DUPLEX_FULL) &&
10509                     (params->eee_mode & EEE_MODE_ADV_LPI) &&
10510                     (bnx2x_eee_calc_timer(params) ||
10511                      !(params->eee_mode & EEE_MODE_ENABLE_LPI)))
10512                         rc = bnx2x_8483x_enable_eee(phy, params, vars);
10513                 else
10514                         rc = bnx2x_8483x_disable_eee(phy, params, vars);
10515                 if (rc) {
10516                         DP(NETIF_MSG_LINK, "Failed to set EEE advertisement\n");
10517                         return rc;
10518                 }
10519         } else {
10520                 vars->eee_status &= ~SHMEM_EEE_SUPPORTED_MASK;
10521         }
10522
10523         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) {
10524                 /* Additional settings for jumbo packets in 1000BASE-T mode */
10525                 /* Allow rx extended length */
10526                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10527                                 MDIO_AN_REG_8481_AUX_CTRL, &val);
10528                 val |= 0x4000;
10529                 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
10530                                  MDIO_AN_REG_8481_AUX_CTRL, val);
10531                 /* TX FIFO Elasticity LSB */
10532                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10533                                 MDIO_AN_REG_8481_1G_100T_EXT_CTRL, &val);
10534                 val |= 0x1;
10535                 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
10536                                  MDIO_AN_REG_8481_1G_100T_EXT_CTRL, val);
10537                 /* TX FIFO Elasticity MSB */
10538                 /* Enable expansion register 0x46 (Pattern Generator status) */
10539                 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
10540                                  MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf46);
10541
10542                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10543                                 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW, &val);
10544                 val |= 0x4000;
10545                 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
10546                                  MDIO_AN_REG_8481_EXPANSION_REG_RD_RW, val);
10547         }
10548
10549         if (bnx2x_is_8483x_8485x(phy)) {
10550                 /* Bring PHY out of super isolate mode as the final step. */
10551                 bnx2x_cl45_read_and_write(bp, phy,
10552                                           MDIO_CTL_DEVAD,
10553                                           MDIO_84833_TOP_CFG_XGPHY_STRAP1,
10554                                           (u16)~MDIO_84833_SUPER_ISOLATE);
10555         }
10556         return rc;
10557 }
10558
10559 static u8 bnx2x_848xx_read_status(struct bnx2x_phy *phy,
10560                                   struct link_params *params,
10561                                   struct link_vars *vars)
10562 {
10563         struct bnx2x *bp = params->bp;
10564         u16 val, val1, val2;
10565         u8 link_up = 0;
10566
10567
10568         /* Check 10G-BaseT link status */
10569         /* Check PMD signal ok */
10570         bnx2x_cl45_read(bp, phy,
10571                         MDIO_AN_DEVAD, 0xFFFA, &val1);
10572         bnx2x_cl45_read(bp, phy,
10573                         MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL,
10574                         &val2);
10575         DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2);
10576
10577         /* Check link 10G */
10578         if (val2 & (1<<11)) {
10579                 vars->line_speed = SPEED_10000;
10580                 vars->duplex = DUPLEX_FULL;
10581                 link_up = 1;
10582                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
10583         } else { /* Check Legacy speed link */
10584                 u16 legacy_status, legacy_speed;
10585
10586                 /* Enable expansion register 0x42 (Operation mode status) */
10587                 bnx2x_cl45_write(bp, phy,
10588                                  MDIO_AN_DEVAD,
10589                                  MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42);
10590
10591                 /* Get legacy speed operation status */
10592                 bnx2x_cl45_read(bp, phy,
10593                                 MDIO_AN_DEVAD,
10594                                 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
10595                                 &legacy_status);
10596
10597                 DP(NETIF_MSG_LINK, "Legacy speed status = 0x%x\n",
10598                    legacy_status);
10599                 link_up = ((legacy_status & (1<<11)) == (1<<11));
10600                 legacy_speed = (legacy_status & (3<<9));
10601                 if (legacy_speed == (0<<9))
10602                         vars->line_speed = SPEED_10;
10603                 else if (legacy_speed == (1<<9))
10604                         vars->line_speed = SPEED_100;
10605                 else if (legacy_speed == (2<<9))
10606                         vars->line_speed = SPEED_1000;
10607                 else { /* Should not happen: Treat as link down */
10608                         vars->line_speed = 0;
10609                         link_up = 0;
10610                 }
10611
10612                 if (link_up) {
10613                         if (legacy_status & (1<<8))
10614                                 vars->duplex = DUPLEX_FULL;
10615                         else
10616                                 vars->duplex = DUPLEX_HALF;
10617
10618                         DP(NETIF_MSG_LINK,
10619                            "Link is up in %dMbps, is_duplex_full= %d\n",
10620                            vars->line_speed,
10621                            (vars->duplex == DUPLEX_FULL));
10622                         /* Check legacy speed AN resolution */
10623                         bnx2x_cl45_read(bp, phy,
10624                                         MDIO_AN_DEVAD,
10625                                         MDIO_AN_REG_8481_LEGACY_MII_STATUS,
10626                                         &val);
10627                         if (val & (1<<5))
10628                                 vars->link_status |=
10629                                         LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
10630                         bnx2x_cl45_read(bp, phy,
10631                                         MDIO_AN_DEVAD,
10632                                         MDIO_AN_REG_8481_LEGACY_AN_EXPANSION,
10633                                         &val);
10634                         if ((val & (1<<0)) == 0)
10635                                 vars->link_status |=
10636                                         LINK_STATUS_PARALLEL_DETECTION_USED;
10637                 }
10638         }
10639         if (link_up) {
10640                 DP(NETIF_MSG_LINK, "BCM848x3: link speed is %d\n",
10641                            vars->line_speed);
10642                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
10643
10644                 /* Read LP advertised speeds */
10645                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10646                                 MDIO_AN_REG_CL37_FC_LP, &val);
10647                 if (val & (1<<5))
10648                         vars->link_status |=
10649                                 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
10650                 if (val & (1<<6))
10651                         vars->link_status |=
10652                                 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
10653                 if (val & (1<<7))
10654                         vars->link_status |=
10655                                 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
10656                 if (val & (1<<8))
10657                         vars->link_status |=
10658                                 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
10659                 if (val & (1<<9))
10660                         vars->link_status |=
10661                                 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
10662
10663                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10664                                 MDIO_AN_REG_1000T_STATUS, &val);
10665
10666                 if (val & (1<<10))
10667                         vars->link_status |=
10668                                 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
10669                 if (val & (1<<11))
10670                         vars->link_status |=
10671                                 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
10672
10673                 bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
10674                                 MDIO_AN_REG_MASTER_STATUS, &val);
10675
10676                 if (val & (1<<11))
10677                         vars->link_status |=
10678                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
10679
10680                 /* Determine if EEE was negotiated */
10681                 if (bnx2x_is_8483x_8485x(phy))
10682                         bnx2x_eee_an_resolve(phy, params, vars);
10683         }
10684
10685         return link_up;
10686 }
10687
10688 static int bnx2x_8485x_format_ver(u32 raw_ver, u8 *str, u16 *len)
10689 {
10690         int status = 0;
10691         u32 num;
10692
10693         num = ((raw_ver & 0xF80) >> 7) << 16 | ((raw_ver & 0x7F) << 8) |
10694               ((raw_ver & 0xF000) >> 12);
10695         status = bnx2x_3_seq_format_ver(num, str, len);
10696         return status;
10697 }
10698
10699 static int bnx2x_848xx_format_ver(u32 raw_ver, u8 *str, u16 *len)
10700 {
10701         int status = 0;
10702         u32 spirom_ver;
10703         spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F);
10704         status = bnx2x_format_ver(spirom_ver, str, len);
10705         return status;
10706 }
10707
10708 static void bnx2x_8481_hw_reset(struct bnx2x_phy *phy,
10709                                 struct link_params *params)
10710 {
10711         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
10712                        MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);
10713         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
10714                        MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);
10715 }
10716
10717 static void bnx2x_8481_link_reset(struct bnx2x_phy *phy,
10718                                         struct link_params *params)
10719 {
10720         bnx2x_cl45_write(params->bp, phy,
10721                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
10722         bnx2x_cl45_write(params->bp, phy,
10723                          MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);
10724 }
10725
10726 static void bnx2x_848x3_link_reset(struct bnx2x_phy *phy,
10727                                    struct link_params *params)
10728 {
10729         struct bnx2x *bp = params->bp;
10730         u8 port;
10731         u16 val16;
10732
10733         if (!(CHIP_IS_E1x(bp)))
10734                 port = BP_PATH(bp);
10735         else
10736                 port = params->port;
10737
10738         if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
10739                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_3,
10740                                MISC_REGISTERS_GPIO_OUTPUT_LOW,
10741                                port);
10742         } else {
10743                 bnx2x_cl45_read(bp, phy,
10744                                 MDIO_CTL_DEVAD,
10745                                 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val16);
10746                 val16 |= MDIO_84833_SUPER_ISOLATE;
10747                 bnx2x_cl45_write(bp, phy,
10748                                  MDIO_CTL_DEVAD,
10749                                  MDIO_84833_TOP_CFG_XGPHY_STRAP1, val16);
10750         }
10751 }
10752
10753 static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy,
10754                                      struct link_params *params, u8 mode)
10755 {
10756         struct bnx2x *bp = params->bp;
10757         u16 val;
10758         u8 port;
10759
10760         if (!(CHIP_IS_E1x(bp)))
10761                 port = BP_PATH(bp);
10762         else
10763                 port = params->port;
10764
10765         switch (mode) {
10766         case LED_MODE_OFF:
10767
10768                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", port);
10769
10770                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10771                     SHARED_HW_CFG_LED_EXTPHY1) {
10772
10773                         /* Set LED masks */
10774                         bnx2x_cl45_write(bp, phy,
10775                                         MDIO_PMA_DEVAD,
10776                                         MDIO_PMA_REG_8481_LED1_MASK,
10777                                         0x0);
10778
10779                         bnx2x_cl45_write(bp, phy,
10780                                         MDIO_PMA_DEVAD,
10781                                         MDIO_PMA_REG_8481_LED2_MASK,
10782                                         0x0);
10783
10784                         bnx2x_cl45_write(bp, phy,
10785                                         MDIO_PMA_DEVAD,
10786                                         MDIO_PMA_REG_8481_LED3_MASK,
10787                                         0x0);
10788
10789                         bnx2x_cl45_write(bp, phy,
10790                                         MDIO_PMA_DEVAD,
10791                                         MDIO_PMA_REG_8481_LED5_MASK,
10792                                         0x0);
10793
10794                 } else {
10795                         /* LED 1 OFF */
10796                         bnx2x_cl45_write(bp, phy,
10797                                          MDIO_PMA_DEVAD,
10798                                          MDIO_PMA_REG_8481_LED1_MASK,
10799                                          0x0);
10800
10801                         if (phy->type ==
10802                                 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) {
10803                                 /* LED 2 OFF */
10804                                 bnx2x_cl45_write(bp, phy,
10805                                                  MDIO_PMA_DEVAD,
10806                                                  MDIO_PMA_REG_8481_LED2_MASK,
10807                                                  0x0);
10808                                 /* LED 3 OFF */
10809                                 bnx2x_cl45_write(bp, phy,
10810                                                  MDIO_PMA_DEVAD,
10811                                                  MDIO_PMA_REG_8481_LED3_MASK,
10812                                                  0x0);
10813                         }
10814                 }
10815                 break;
10816         case LED_MODE_FRONT_PANEL_OFF:
10817
10818                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n",
10819                    port);
10820
10821                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10822                     SHARED_HW_CFG_LED_EXTPHY1) {
10823
10824                         /* Set LED masks */
10825                         bnx2x_cl45_write(bp, phy,
10826                                          MDIO_PMA_DEVAD,
10827                                          MDIO_PMA_REG_8481_LED1_MASK,
10828                                          0x0);
10829
10830                         bnx2x_cl45_write(bp, phy,
10831                                          MDIO_PMA_DEVAD,
10832                                          MDIO_PMA_REG_8481_LED2_MASK,
10833                                          0x0);
10834
10835                         bnx2x_cl45_write(bp, phy,
10836                                          MDIO_PMA_DEVAD,
10837                                          MDIO_PMA_REG_8481_LED3_MASK,
10838                                          0x0);
10839
10840                         bnx2x_cl45_write(bp, phy,
10841                                          MDIO_PMA_DEVAD,
10842                                          MDIO_PMA_REG_8481_LED5_MASK,
10843                                          0x20);
10844
10845                 } else {
10846                         bnx2x_cl45_write(bp, phy,
10847                                          MDIO_PMA_DEVAD,
10848                                          MDIO_PMA_REG_8481_LED1_MASK,
10849                                          0x0);
10850                         if (phy->type ==
10851                             PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
10852                                 /* Disable MI_INT interrupt before setting LED4
10853                                  * source to constant off.
10854                                  */
10855                                 if (REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
10856                                            params->port*4) &
10857                                     NIG_MASK_MI_INT) {
10858                                         params->link_flags |=
10859                                         LINK_FLAGS_INT_DISABLED;
10860
10861                                         bnx2x_bits_dis(
10862                                                 bp,
10863                                                 NIG_REG_MASK_INTERRUPT_PORT0 +
10864                                                 params->port*4,
10865                                                 NIG_MASK_MI_INT);
10866                                 }
10867                                 bnx2x_cl45_write(bp, phy,
10868                                                  MDIO_PMA_DEVAD,
10869                                                  MDIO_PMA_REG_8481_SIGNAL_MASK,
10870                                                  0x0);
10871                         }
10872                         if (phy->type ==
10873                                 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) {
10874                                 /* LED 2 OFF */
10875                                 bnx2x_cl45_write(bp, phy,
10876                                                  MDIO_PMA_DEVAD,
10877                                                  MDIO_PMA_REG_8481_LED2_MASK,
10878                                                  0x0);
10879                                 /* LED 3 OFF */
10880                                 bnx2x_cl45_write(bp, phy,
10881                                                  MDIO_PMA_DEVAD,
10882                                                  MDIO_PMA_REG_8481_LED3_MASK,
10883                                                  0x0);
10884                         }
10885                 }
10886                 break;
10887         case LED_MODE_ON:
10888
10889                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", port);
10890
10891                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10892                     SHARED_HW_CFG_LED_EXTPHY1) {
10893                         /* Set control reg */
10894                         bnx2x_cl45_read(bp, phy,
10895                                         MDIO_PMA_DEVAD,
10896                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
10897                                         &val);
10898                         val &= 0x8000;
10899                         val |= 0x2492;
10900
10901                         bnx2x_cl45_write(bp, phy,
10902                                          MDIO_PMA_DEVAD,
10903                                          MDIO_PMA_REG_8481_LINK_SIGNAL,
10904                                          val);
10905
10906                         /* Set LED masks */
10907                         bnx2x_cl45_write(bp, phy,
10908                                          MDIO_PMA_DEVAD,
10909                                          MDIO_PMA_REG_8481_LED1_MASK,
10910                                          0x0);
10911
10912                         bnx2x_cl45_write(bp, phy,
10913                                          MDIO_PMA_DEVAD,
10914                                          MDIO_PMA_REG_8481_LED2_MASK,
10915                                          0x20);
10916
10917                         bnx2x_cl45_write(bp, phy,
10918                                          MDIO_PMA_DEVAD,
10919                                          MDIO_PMA_REG_8481_LED3_MASK,
10920                                          0x20);
10921
10922                         bnx2x_cl45_write(bp, phy,
10923                                          MDIO_PMA_DEVAD,
10924                                          MDIO_PMA_REG_8481_LED5_MASK,
10925                                          0x0);
10926                 } else {
10927                         bnx2x_cl45_write(bp, phy,
10928                                          MDIO_PMA_DEVAD,
10929                                          MDIO_PMA_REG_8481_LED1_MASK,
10930                                          0x20);
10931                         if (phy->type ==
10932                             PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
10933                                 /* Disable MI_INT interrupt before setting LED4
10934                                  * source to constant on.
10935                                  */
10936                                 if (REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
10937                                            params->port*4) &
10938                                     NIG_MASK_MI_INT) {
10939                                         params->link_flags |=
10940                                         LINK_FLAGS_INT_DISABLED;
10941
10942                                         bnx2x_bits_dis(
10943                                                 bp,
10944                                                 NIG_REG_MASK_INTERRUPT_PORT0 +
10945                                                 params->port*4,
10946                                                 NIG_MASK_MI_INT);
10947                                 }
10948                         }
10949                         if (phy->type ==
10950                             PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) {
10951                                 /* Tell LED3 to constant on */
10952                                 bnx2x_cl45_read(bp, phy,
10953                                                 MDIO_PMA_DEVAD,
10954                                                 MDIO_PMA_REG_8481_LINK_SIGNAL,
10955                                                 &val);
10956                                 val &= ~(7<<6);
10957                                 val |= (2<<6);  /* A83B[8:6]= 2 */
10958                                 bnx2x_cl45_write(bp, phy,
10959                                                  MDIO_PMA_DEVAD,
10960                                                  MDIO_PMA_REG_8481_LINK_SIGNAL,
10961                                                  val);
10962                                 bnx2x_cl45_write(bp, phy,
10963                                                  MDIO_PMA_DEVAD,
10964                                                  MDIO_PMA_REG_8481_LED3_MASK,
10965                                                  0x20);
10966                         } else {
10967                                 bnx2x_cl45_write(bp, phy,
10968                                                  MDIO_PMA_DEVAD,
10969                                                  MDIO_PMA_REG_8481_SIGNAL_MASK,
10970                                                  0x20);
10971                         }
10972                 }
10973                 break;
10974
10975         case LED_MODE_OPER:
10976
10977                 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", port);
10978
10979                 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
10980                     SHARED_HW_CFG_LED_EXTPHY1) {
10981
10982                         /* Set control reg */
10983                         bnx2x_cl45_read(bp, phy,
10984                                         MDIO_PMA_DEVAD,
10985                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
10986                                         &val);
10987
10988                         if (!((val &
10989                                MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)
10990                           >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) {
10991                                 DP(NETIF_MSG_LINK, "Setting LINK_SIGNAL\n");
10992                                 bnx2x_cl45_write(bp, phy,
10993                                                  MDIO_PMA_DEVAD,
10994                                                  MDIO_PMA_REG_8481_LINK_SIGNAL,
10995                                                  0xa492);
10996                         }
10997
10998                         /* Set LED masks */
10999                         bnx2x_cl45_write(bp, phy,
11000                                          MDIO_PMA_DEVAD,
11001                                          MDIO_PMA_REG_8481_LED1_MASK,
11002                                          0x10);
11003
11004                         bnx2x_cl45_write(bp, phy,
11005                                          MDIO_PMA_DEVAD,
11006                                          MDIO_PMA_REG_8481_LED2_MASK,
11007                                          0x80);
11008
11009                         bnx2x_cl45_write(bp, phy,
11010                                          MDIO_PMA_DEVAD,
11011                                          MDIO_PMA_REG_8481_LED3_MASK,
11012                                          0x98);
11013
11014                         bnx2x_cl45_write(bp, phy,
11015                                          MDIO_PMA_DEVAD,
11016                                          MDIO_PMA_REG_8481_LED5_MASK,
11017                                          0x40);
11018
11019                 } else {
11020                         /* EXTPHY2 LED mode indicate that the 100M/1G/10G LED
11021                          * sources are all wired through LED1, rather than only
11022                          * 10G in other modes.
11023                          */
11024                         val = ((params->hw_led_mode <<
11025                                 SHARED_HW_CFG_LED_MODE_SHIFT) ==
11026                                SHARED_HW_CFG_LED_EXTPHY2) ? 0x98 : 0x80;
11027
11028                         bnx2x_cl45_write(bp, phy,
11029                                          MDIO_PMA_DEVAD,
11030                                          MDIO_PMA_REG_8481_LED1_MASK,
11031                                          val);
11032
11033                         /* Tell LED3 to blink on source */
11034                         bnx2x_cl45_read(bp, phy,
11035                                         MDIO_PMA_DEVAD,
11036                                         MDIO_PMA_REG_8481_LINK_SIGNAL,
11037                                         &val);
11038                         val &= ~(7<<6);
11039                         val |= (1<<6); /* A83B[8:6]= 1 */
11040                         bnx2x_cl45_write(bp, phy,
11041                                          MDIO_PMA_DEVAD,
11042                                          MDIO_PMA_REG_8481_LINK_SIGNAL,
11043                                          val);
11044                         if (phy->type ==
11045                             PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) {
11046                                 bnx2x_cl45_write(bp, phy,
11047                                                  MDIO_PMA_DEVAD,
11048                                                  MDIO_PMA_REG_8481_LED2_MASK,
11049                                                  0x18);
11050                                 bnx2x_cl45_write(bp, phy,
11051                                                  MDIO_PMA_DEVAD,
11052                                                  MDIO_PMA_REG_8481_LED3_MASK,
11053                                                  0x06);
11054                         }
11055                         if (phy->type ==
11056                             PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
11057                                 /* Restore LED4 source to external link,
11058                                  * and re-enable interrupts.
11059                                  */
11060                                 bnx2x_cl45_write(bp, phy,
11061                                                  MDIO_PMA_DEVAD,
11062                                                  MDIO_PMA_REG_8481_SIGNAL_MASK,
11063                                                  0x40);
11064                                 if (params->link_flags &
11065                                     LINK_FLAGS_INT_DISABLED) {
11066                                         bnx2x_link_int_enable(params);
11067                                         params->link_flags &=
11068                                                 ~LINK_FLAGS_INT_DISABLED;
11069                                 }
11070                         }
11071                 }
11072                 break;
11073         }
11074
11075         /* This is a workaround for E3+84833 until autoneg
11076          * restart is fixed in f/w
11077          */
11078         if (CHIP_IS_E3(bp)) {
11079                 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
11080                                 MDIO_WC_REG_GP2_STATUS_GP_2_1, &val);
11081         }
11082 }
11083
11084 /******************************************************************/
11085 /*                      54618SE PHY SECTION                       */
11086 /******************************************************************/
11087 static void bnx2x_54618se_specific_func(struct bnx2x_phy *phy,
11088                                         struct link_params *params,
11089                                         u32 action)
11090 {
11091         struct bnx2x *bp = params->bp;
11092         u16 temp;
11093         switch (action) {
11094         case PHY_INIT:
11095                 /* Configure LED4: set to INTR (0x6). */
11096                 /* Accessing shadow register 0xe. */
11097                 bnx2x_cl22_write(bp, phy,
11098                                  MDIO_REG_GPHY_SHADOW,
11099                                  MDIO_REG_GPHY_SHADOW_LED_SEL2);
11100                 bnx2x_cl22_read(bp, phy,
11101                                 MDIO_REG_GPHY_SHADOW,
11102                                 &temp);
11103                 temp &= ~(0xf << 4);
11104                 temp |= (0x6 << 4);
11105                 bnx2x_cl22_write(bp, phy,
11106                                  MDIO_REG_GPHY_SHADOW,
11107                                  MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
11108                 /* Configure INTR based on link status change. */
11109                 bnx2x_cl22_write(bp, phy,
11110                                  MDIO_REG_INTR_MASK,
11111                                  ~MDIO_REG_INTR_MASK_LINK_STATUS);
11112                 break;
11113         }
11114 }
11115
11116 static int bnx2x_54618se_config_init(struct bnx2x_phy *phy,
11117                                                struct link_params *params,
11118                                                struct link_vars *vars)
11119 {
11120         struct bnx2x *bp = params->bp;
11121         u8 port;
11122         u16 autoneg_val, an_1000_val, an_10_100_val, fc_val, temp;
11123         u32 cfg_pin;
11124
11125         DP(NETIF_MSG_LINK, "54618SE cfg init\n");
11126         usleep_range(1000, 2000);
11127
11128         /* This works with E3 only, no need to check the chip
11129          * before determining the port.
11130          */
11131         port = params->port;
11132
11133         cfg_pin = (REG_RD(bp, params->shmem_base +
11134                         offsetof(struct shmem_region,
11135                         dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
11136                         PORT_HW_CFG_E3_PHY_RESET_MASK) >>
11137                         PORT_HW_CFG_E3_PHY_RESET_SHIFT;
11138
11139         /* Drive pin high to bring the GPHY out of reset. */
11140         bnx2x_set_cfg_pin(bp, cfg_pin, 1);
11141
11142         /* wait for GPHY to reset */
11143         msleep(50);
11144
11145         /* reset phy */
11146         bnx2x_cl22_write(bp, phy,
11147                          MDIO_PMA_REG_CTRL, 0x8000);
11148         bnx2x_wait_reset_complete(bp, phy, params);
11149
11150         /* Wait for GPHY to reset */
11151         msleep(50);
11152
11153
11154         bnx2x_54618se_specific_func(phy, params, PHY_INIT);
11155         /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */
11156         bnx2x_cl22_write(bp, phy,
11157                         MDIO_REG_GPHY_SHADOW,
11158                         MDIO_REG_GPHY_SHADOW_AUTO_DET_MED);
11159         bnx2x_cl22_read(bp, phy,
11160                         MDIO_REG_GPHY_SHADOW,
11161                         &temp);
11162         temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD;
11163         bnx2x_cl22_write(bp, phy,
11164                         MDIO_REG_GPHY_SHADOW,
11165                         MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
11166
11167         /* Set up fc */
11168         /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
11169         bnx2x_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
11170         fc_val = 0;
11171         if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
11172                         MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC)
11173                 fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
11174
11175         if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
11176                         MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
11177                 fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
11178
11179         /* Read all advertisement */
11180         bnx2x_cl22_read(bp, phy,
11181                         0x09,
11182                         &an_1000_val);
11183
11184         bnx2x_cl22_read(bp, phy,
11185                         0x04,
11186                         &an_10_100_val);
11187
11188         bnx2x_cl22_read(bp, phy,
11189                         MDIO_PMA_REG_CTRL,
11190                         &autoneg_val);
11191
11192         /* Disable forced speed */
11193         autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
11194         an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8) | (1<<10) |
11195                            (1<<11));
11196
11197         if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
11198              (phy->speed_cap_mask &
11199               PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
11200             (phy->req_line_speed == SPEED_1000)) {
11201                 an_1000_val |= (1<<8);
11202                 autoneg_val |= (1<<9 | 1<<12);
11203                 if (phy->req_duplex == DUPLEX_FULL)
11204                         an_1000_val |= (1<<9);
11205                 DP(NETIF_MSG_LINK, "Advertising 1G\n");
11206         } else
11207                 an_1000_val &= ~((1<<8) | (1<<9));
11208
11209         bnx2x_cl22_write(bp, phy,
11210                         0x09,
11211                         an_1000_val);
11212         bnx2x_cl22_read(bp, phy,
11213                         0x09,
11214                         &an_1000_val);
11215
11216         /* Advertise 10/100 link speed */
11217         if (phy->req_line_speed == SPEED_AUTO_NEG) {
11218                 if (phy->speed_cap_mask &
11219                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) {
11220                         an_10_100_val |= (1<<5);
11221                         autoneg_val |= (1<<9 | 1<<12);
11222                         DP(NETIF_MSG_LINK, "Advertising 10M-HD\n");
11223                 }
11224                 if (phy->speed_cap_mask &
11225                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) {
11226                         an_10_100_val |= (1<<6);
11227                         autoneg_val |= (1<<9 | 1<<12);
11228                         DP(NETIF_MSG_LINK, "Advertising 10M-FD\n");
11229                 }
11230                 if (phy->speed_cap_mask &
11231                     PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) {
11232                         an_10_100_val |= (1<<7);
11233                         autoneg_val |= (1<<9 | 1<<12);
11234                         DP(NETIF_MSG_LINK, "Advertising 100M-HD\n");
11235                 }
11236                 if (phy->speed_cap_mask &
11237                     PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) {
11238                         an_10_100_val |= (1<<8);
11239                         autoneg_val |= (1<<9 | 1<<12);
11240                         DP(NETIF_MSG_LINK, "Advertising 100M-FD\n");
11241                 }
11242         }
11243
11244         /* Only 10/100 are allowed to work in FORCE mode */
11245         if (phy->req_line_speed == SPEED_100) {
11246                 autoneg_val |= (1<<13);
11247                 /* Enabled AUTO-MDIX when autoneg is disabled */
11248                 bnx2x_cl22_write(bp, phy,
11249                                 0x18,
11250                                 (1<<15 | 1<<9 | 7<<0));
11251                 DP(NETIF_MSG_LINK, "Setting 100M force\n");
11252         }
11253         if (phy->req_line_speed == SPEED_10) {
11254                 /* Enabled AUTO-MDIX when autoneg is disabled */
11255                 bnx2x_cl22_write(bp, phy,
11256                                 0x18,
11257                                 (1<<15 | 1<<9 | 7<<0));
11258                 DP(NETIF_MSG_LINK, "Setting 10M force\n");
11259         }
11260
11261         if ((phy->flags & FLAGS_EEE) && bnx2x_eee_has_cap(params)) {
11262                 int rc;
11263
11264                 bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS,
11265                                  MDIO_REG_GPHY_EXP_ACCESS_TOP |
11266                                  MDIO_REG_GPHY_EXP_TOP_2K_BUF);
11267                 bnx2x_cl22_read(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, &temp);
11268                 temp &= 0xfffe;
11269                 bnx2x_cl22_write(bp, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, temp);
11270
11271                 rc = bnx2x_eee_initial_config(params, vars, SHMEM_EEE_1G_ADV);
11272                 if (rc) {
11273                         DP(NETIF_MSG_LINK, "Failed to configure EEE timers\n");
11274                         bnx2x_eee_disable(phy, params, vars);
11275                 } else if ((params->eee_mode & EEE_MODE_ADV_LPI) &&
11276                            (phy->req_duplex == DUPLEX_FULL) &&
11277                            (bnx2x_eee_calc_timer(params) ||
11278                             !(params->eee_mode & EEE_MODE_ENABLE_LPI))) {
11279                         /* Need to advertise EEE only when requested,
11280                          * and either no LPI assertion was requested,
11281                          * or it was requested and a valid timer was set.
11282                          * Also notice full duplex is required for EEE.
11283                          */
11284                         bnx2x_eee_advertise(phy, params, vars,
11285                                             SHMEM_EEE_1G_ADV);
11286                 } else {
11287                         DP(NETIF_MSG_LINK, "Don't Advertise 1GBase-T EEE\n");
11288                         bnx2x_eee_disable(phy, params, vars);
11289                 }
11290         } else {
11291                 vars->eee_status &= ~SHMEM_EEE_1G_ADV <<
11292                                     SHMEM_EEE_SUPPORTED_SHIFT;
11293
11294                 if (phy->flags & FLAGS_EEE) {
11295                         /* Handle legacy auto-grEEEn */
11296                         if (params->feature_config_flags &
11297                             FEATURE_CONFIG_AUTOGREEEN_ENABLED) {
11298                                 temp = 6;
11299                                 DP(NETIF_MSG_LINK, "Enabling Auto-GrEEEn\n");
11300                         } else {
11301                                 temp = 0;
11302                                 DP(NETIF_MSG_LINK, "Don't Adv. EEE\n");
11303                         }
11304                         bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
11305                                          MDIO_AN_REG_EEE_ADV, temp);
11306                 }
11307         }
11308
11309         bnx2x_cl22_write(bp, phy,
11310                         0x04,
11311                         an_10_100_val | fc_val);
11312
11313         if (phy->req_duplex == DUPLEX_FULL)
11314                 autoneg_val |= (1<<8);
11315
11316         bnx2x_cl22_write(bp, phy,
11317                         MDIO_PMA_REG_CTRL, autoneg_val);
11318
11319         return 0;
11320 }
11321
11322
11323 static void bnx2x_5461x_set_link_led(struct bnx2x_phy *phy,
11324                                        struct link_params *params, u8 mode)
11325 {
11326         struct bnx2x *bp = params->bp;
11327         u16 temp;
11328
11329         bnx2x_cl22_write(bp, phy,
11330                 MDIO_REG_GPHY_SHADOW,
11331                 MDIO_REG_GPHY_SHADOW_LED_SEL1);
11332         bnx2x_cl22_read(bp, phy,
11333                 MDIO_REG_GPHY_SHADOW,
11334                 &temp);
11335         temp &= 0xff00;
11336
11337         DP(NETIF_MSG_LINK, "54618x set link led (mode=%x)\n", mode);
11338         switch (mode) {
11339         case LED_MODE_FRONT_PANEL_OFF:
11340         case LED_MODE_OFF:
11341                 temp |= 0x00ee;
11342                 break;
11343         case LED_MODE_OPER:
11344                 temp |= 0x0001;
11345                 break;
11346         case LED_MODE_ON:
11347                 temp |= 0x00ff;
11348                 break;
11349         default:
11350                 break;
11351         }
11352         bnx2x_cl22_write(bp, phy,
11353                 MDIO_REG_GPHY_SHADOW,
11354                 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
11355         return;
11356 }
11357
11358
11359 static void bnx2x_54618se_link_reset(struct bnx2x_phy *phy,
11360                                      struct link_params *params)
11361 {
11362         struct bnx2x *bp = params->bp;
11363         u32 cfg_pin;
11364         u8 port;
11365
11366         /* In case of no EPIO routed to reset the GPHY, put it
11367          * in low power mode.
11368          */
11369         bnx2x_cl22_write(bp, phy, MDIO_PMA_REG_CTRL, 0x800);
11370         /* This works with E3 only, no need to check the chip
11371          * before determining the port.
11372          */
11373         port = params->port;
11374         cfg_pin = (REG_RD(bp, params->shmem_base +
11375                         offsetof(struct shmem_region,
11376                         dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
11377                         PORT_HW_CFG_E3_PHY_RESET_MASK) >>
11378                         PORT_HW_CFG_E3_PHY_RESET_SHIFT;
11379
11380         /* Drive pin low to put GPHY in reset. */
11381         bnx2x_set_cfg_pin(bp, cfg_pin, 0);
11382 }
11383
11384 static u8 bnx2x_54618se_read_status(struct bnx2x_phy *phy,
11385                                     struct link_params *params,
11386                                     struct link_vars *vars)
11387 {
11388         struct bnx2x *bp = params->bp;
11389         u16 val;
11390         u8 link_up = 0;
11391         u16 legacy_status, legacy_speed;
11392
11393         /* Get speed operation status */
11394         bnx2x_cl22_read(bp, phy,
11395                         MDIO_REG_GPHY_AUX_STATUS,
11396                         &legacy_status);
11397         DP(NETIF_MSG_LINK, "54618SE read_status: 0x%x\n", legacy_status);
11398
11399         /* Read status to clear the PHY interrupt. */
11400         bnx2x_cl22_read(bp, phy,
11401                         MDIO_REG_INTR_STATUS,
11402                         &val);
11403
11404         link_up = ((legacy_status & (1<<2)) == (1<<2));
11405
11406         if (link_up) {
11407                 legacy_speed = (legacy_status & (7<<8));
11408                 if (legacy_speed == (7<<8)) {
11409                         vars->line_speed = SPEED_1000;
11410                         vars->duplex = DUPLEX_FULL;
11411                 } else if (legacy_speed == (6<<8)) {
11412                         vars->line_speed = SPEED_1000;
11413                         vars->duplex = DUPLEX_HALF;
11414                 } else if (legacy_speed == (5<<8)) {
11415                         vars->line_speed = SPEED_100;
11416                         vars->duplex = DUPLEX_FULL;
11417                 }
11418                 /* Omitting 100Base-T4 for now */
11419                 else if (legacy_speed == (3<<8)) {
11420                         vars->line_speed = SPEED_100;
11421                         vars->duplex = DUPLEX_HALF;
11422                 } else if (legacy_speed == (2<<8)) {
11423                         vars->line_speed = SPEED_10;
11424                         vars->duplex = DUPLEX_FULL;
11425                 } else if (legacy_speed == (1<<8)) {
11426                         vars->line_speed = SPEED_10;
11427                         vars->duplex = DUPLEX_HALF;
11428                 } else /* Should not happen */
11429                         vars->line_speed = 0;
11430
11431                 DP(NETIF_MSG_LINK,
11432                    "Link is up in %dMbps, is_duplex_full= %d\n",
11433                    vars->line_speed,
11434                    (vars->duplex == DUPLEX_FULL));
11435
11436                 /* Check legacy speed AN resolution */
11437                 bnx2x_cl22_read(bp, phy,
11438                                 0x01,
11439                                 &val);
11440                 if (val & (1<<5))
11441                         vars->link_status |=
11442                                 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
11443                 bnx2x_cl22_read(bp, phy,
11444                                 0x06,
11445                                 &val);
11446                 if ((val & (1<<0)) == 0)
11447                         vars->link_status |=
11448                                 LINK_STATUS_PARALLEL_DETECTION_USED;
11449
11450                 DP(NETIF_MSG_LINK, "BCM54618SE: link speed is %d\n",
11451                            vars->line_speed);
11452
11453                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
11454
11455                 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
11456                         /* Report LP advertised speeds */
11457                         bnx2x_cl22_read(bp, phy, 0x5, &val);
11458
11459                         if (val & (1<<5))
11460                                 vars->link_status |=
11461                                   LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
11462                         if (val & (1<<6))
11463                                 vars->link_status |=
11464                                   LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
11465                         if (val & (1<<7))
11466                                 vars->link_status |=
11467                                   LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
11468                         if (val & (1<<8))
11469                                 vars->link_status |=
11470                                   LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
11471                         if (val & (1<<9))
11472                                 vars->link_status |=
11473                                   LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
11474
11475                         bnx2x_cl22_read(bp, phy, 0xa, &val);
11476                         if (val & (1<<10))
11477                                 vars->link_status |=
11478                                   LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
11479                         if (val & (1<<11))
11480                                 vars->link_status |=
11481                                   LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
11482
11483                         if ((phy->flags & FLAGS_EEE) &&
11484                             bnx2x_eee_has_cap(params))
11485                                 bnx2x_eee_an_resolve(phy, params, vars);
11486                 }
11487         }
11488         return link_up;
11489 }
11490
11491 static void bnx2x_54618se_config_loopback(struct bnx2x_phy *phy,
11492                                           struct link_params *params)
11493 {
11494         struct bnx2x *bp = params->bp;
11495         u16 val;
11496         u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
11497
11498         DP(NETIF_MSG_LINK, "2PMA/PMD ext_phy_loopback: 54618se\n");
11499
11500         /* Enable master/slave manual mmode and set to master */
11501         /* mii write 9 [bits set 11 12] */
11502         bnx2x_cl22_write(bp, phy, 0x09, 3<<11);
11503
11504         /* forced 1G and disable autoneg */
11505         /* set val [mii read 0] */
11506         /* set val [expr $val & [bits clear 6 12 13]] */
11507         /* set val [expr $val | [bits set 6 8]] */
11508         /* mii write 0 $val */
11509         bnx2x_cl22_read(bp, phy, 0x00, &val);
11510         val &= ~((1<<6) | (1<<12) | (1<<13));
11511         val |= (1<<6) | (1<<8);
11512         bnx2x_cl22_write(bp, phy, 0x00, val);
11513
11514         /* Set external loopback and Tx using 6dB coding */
11515         /* mii write 0x18 7 */
11516         /* set val [mii read 0x18] */
11517         /* mii write 0x18 [expr $val | [bits set 10 15]] */
11518         bnx2x_cl22_write(bp, phy, 0x18, 7);
11519         bnx2x_cl22_read(bp, phy, 0x18, &val);
11520         bnx2x_cl22_write(bp, phy, 0x18, val | (1<<10) | (1<<15));
11521
11522         /* This register opens the gate for the UMAC despite its name */
11523         REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
11524
11525         /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
11526          * length used by the MAC receive logic to check frames.
11527          */
11528         REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710);
11529 }
11530
11531 /******************************************************************/
11532 /*                      SFX7101 PHY SECTION                       */
11533 /******************************************************************/
11534 static void bnx2x_7101_config_loopback(struct bnx2x_phy *phy,
11535                                        struct link_params *params)
11536 {
11537         struct bnx2x *bp = params->bp;
11538         /* SFX7101_XGXS_TEST1 */
11539         bnx2x_cl45_write(bp, phy,
11540                          MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100);
11541 }
11542
11543 static int bnx2x_7101_config_init(struct bnx2x_phy *phy,
11544                                   struct link_params *params,
11545                                   struct link_vars *vars)
11546 {
11547         u16 fw_ver1, fw_ver2, val;
11548         struct bnx2x *bp = params->bp;
11549         DP(NETIF_MSG_LINK, "Setting the SFX7101 LASI indication\n");
11550
11551         /* Restore normal power mode*/
11552         bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
11553                        MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
11554         /* HW reset */
11555         bnx2x_ext_phy_hw_reset(bp, params->port);
11556         bnx2x_wait_reset_complete(bp, phy, params);
11557
11558         bnx2x_cl45_write(bp, phy,
11559                          MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1);
11560         DP(NETIF_MSG_LINK, "Setting the SFX7101 LED to blink on traffic\n");
11561         bnx2x_cl45_write(bp, phy,
11562                          MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
11563
11564         bnx2x_ext_phy_set_pause(params, phy, vars);
11565         /* Restart autoneg */
11566         bnx2x_cl45_read(bp, phy,
11567                         MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);
11568         val |= 0x200;
11569         bnx2x_cl45_write(bp, phy,
11570                          MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);
11571
11572         /* Save spirom version */
11573         bnx2x_cl45_read(bp, phy,
11574                         MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1);
11575
11576         bnx2x_cl45_read(bp, phy,
11577                         MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2);
11578         bnx2x_save_spirom_version(bp, params->port,
11579                                   (u32)(fw_ver1<<16 | fw_ver2), phy->ver_addr);
11580         return 0;
11581 }
11582
11583 static u8 bnx2x_7101_read_status(struct bnx2x_phy *phy,
11584                                  struct link_params *params,
11585                                  struct link_vars *vars)
11586 {
11587         struct bnx2x *bp = params->bp;
11588         u8 link_up;
11589         u16 val1, val2;
11590         bnx2x_cl45_read(bp, phy,
11591                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
11592         bnx2x_cl45_read(bp, phy,
11593                         MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
11594         DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n",
11595                    val2, val1);
11596         bnx2x_cl45_read(bp, phy,
11597                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
11598         bnx2x_cl45_read(bp, phy,
11599                         MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
11600         DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n",
11601                    val2, val1);
11602         link_up = ((val1 & 4) == 4);
11603         /* If link is up print the AN outcome of the SFX7101 PHY */
11604         if (link_up) {
11605                 bnx2x_cl45_read(bp, phy,
11606                                 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS,
11607                                 &val2);
11608                 vars->line_speed = SPEED_10000;
11609                 vars->duplex = DUPLEX_FULL;
11610                 DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n",
11611                            val2, (val2 & (1<<14)));
11612                 bnx2x_ext_phy_10G_an_resolve(bp, phy, vars);
11613                 bnx2x_ext_phy_resolve_fc(phy, params, vars);
11614
11615                 /* Read LP advertised speeds */
11616                 if (val2 & (1<<11))
11617                         vars->link_status |=
11618                                 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
11619         }
11620         return link_up;
11621 }
11622
11623 static int bnx2x_7101_format_ver(u32 spirom_ver, u8 *str, u16 *len)
11624 {
11625         if (*len < 5)
11626                 return -EINVAL;
11627         str[0] = (spirom_ver & 0xFF);
11628         str[1] = (spirom_ver & 0xFF00) >> 8;
11629         str[2] = (spirom_ver & 0xFF0000) >> 16;
11630         str[3] = (spirom_ver & 0xFF000000) >> 24;
11631         str[4] = '\0';
11632         *len -= 5;
11633         return 0;
11634 }
11635
11636 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, struct bnx2x_phy *phy)
11637 {
11638         u16 val, cnt;
11639
11640         bnx2x_cl45_read(bp, phy,
11641                         MDIO_PMA_DEVAD,
11642                         MDIO_PMA_REG_7101_RESET, &val);
11643
11644         for (cnt = 0; cnt < 10; cnt++) {
11645                 msleep(50);
11646                 /* Writes a self-clearing reset */
11647                 bnx2x_cl45_write(bp, phy,
11648                                  MDIO_PMA_DEVAD,
11649                                  MDIO_PMA_REG_7101_RESET,
11650                                  (val | (1<<15)));
11651                 /* Wait for clear */
11652                 bnx2x_cl45_read(bp, phy,
11653                                 MDIO_PMA_DEVAD,
11654                                 MDIO_PMA_REG_7101_RESET, &val);
11655
11656                 if ((val & (1<<15)) == 0)
11657                         break;
11658         }
11659 }
11660
11661 static void bnx2x_7101_hw_reset(struct bnx2x_phy *phy,
11662                                 struct link_params *params) {
11663         /* Low power mode is controlled by GPIO 2 */
11664         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_2,
11665                        MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
11666         /* The PHY reset is controlled by GPIO 1 */
11667         bnx2x_set_gpio(params->bp, MISC_REGISTERS_GPIO_1,
11668                        MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
11669 }
11670
11671 static void bnx2x_7101_set_link_led(struct bnx2x_phy *phy,
11672                                     struct link_params *params, u8 mode)
11673 {
11674         u16 val = 0;
11675         struct bnx2x *bp = params->bp;
11676         switch (mode) {
11677         case LED_MODE_FRONT_PANEL_OFF:
11678         case LED_MODE_OFF:
11679                 val = 2;
11680                 break;
11681         case LED_MODE_ON:
11682                 val = 1;
11683                 break;
11684         case LED_MODE_OPER:
11685                 val = 0;
11686                 break;
11687         }
11688         bnx2x_cl45_write(bp, phy,
11689                          MDIO_PMA_DEVAD,
11690                          MDIO_PMA_REG_7107_LINK_LED_CNTL,
11691                          val);
11692 }
11693
11694 /******************************************************************/
11695 /*                      STATIC PHY DECLARATION                    */
11696 /******************************************************************/
11697
11698 static const struct bnx2x_phy phy_null = {
11699         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,
11700         .addr           = 0,
11701         .def_md_devad   = 0,
11702         .flags          = FLAGS_INIT_XGXS_FIRST,
11703         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11704         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11705         .mdio_ctrl      = 0,
11706         .supported      = 0,
11707         .media_type     = ETH_PHY_NOT_PRESENT,
11708         .ver_addr       = 0,
11709         .req_flow_ctrl  = 0,
11710         .req_line_speed = 0,
11711         .speed_cap_mask = 0,
11712         .req_duplex     = 0,
11713         .rsrv           = 0,
11714         .config_init    = (config_init_t)NULL,
11715         .read_status    = (read_status_t)NULL,
11716         .link_reset     = (link_reset_t)NULL,
11717         .config_loopback = (config_loopback_t)NULL,
11718         .format_fw_ver  = (format_fw_ver_t)NULL,
11719         .hw_reset       = (hw_reset_t)NULL,
11720         .set_link_led   = (set_link_led_t)NULL,
11721         .phy_specific_func = (phy_specific_func_t)NULL
11722 };
11723
11724 static const struct bnx2x_phy phy_serdes = {
11725         .type           = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,
11726         .addr           = 0xff,
11727         .def_md_devad   = 0,
11728         .flags          = 0,
11729         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11730         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11731         .mdio_ctrl      = 0,
11732         .supported      = (SUPPORTED_10baseT_Half |
11733                            SUPPORTED_10baseT_Full |
11734                            SUPPORTED_100baseT_Half |
11735                            SUPPORTED_100baseT_Full |
11736                            SUPPORTED_1000baseT_Full |
11737                            SUPPORTED_2500baseX_Full |
11738                            SUPPORTED_TP |
11739                            SUPPORTED_Autoneg |
11740                            SUPPORTED_Pause |
11741                            SUPPORTED_Asym_Pause),
11742         .media_type     = ETH_PHY_BASE_T,
11743         .ver_addr       = 0,
11744         .req_flow_ctrl  = 0,
11745         .req_line_speed = 0,
11746         .speed_cap_mask = 0,
11747         .req_duplex     = 0,
11748         .rsrv           = 0,
11749         .config_init    = (config_init_t)bnx2x_xgxs_config_init,
11750         .read_status    = (read_status_t)bnx2x_link_settings_status,
11751         .link_reset     = (link_reset_t)bnx2x_int_link_reset,
11752         .config_loopback = (config_loopback_t)NULL,
11753         .format_fw_ver  = (format_fw_ver_t)NULL,
11754         .hw_reset       = (hw_reset_t)NULL,
11755         .set_link_led   = (set_link_led_t)NULL,
11756         .phy_specific_func = (phy_specific_func_t)NULL
11757 };
11758
11759 static const struct bnx2x_phy phy_xgxs = {
11760         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
11761         .addr           = 0xff,
11762         .def_md_devad   = 0,
11763         .flags          = 0,
11764         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11765         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11766         .mdio_ctrl      = 0,
11767         .supported      = (SUPPORTED_10baseT_Half |
11768                            SUPPORTED_10baseT_Full |
11769                            SUPPORTED_100baseT_Half |
11770                            SUPPORTED_100baseT_Full |
11771                            SUPPORTED_1000baseT_Full |
11772                            SUPPORTED_2500baseX_Full |
11773                            SUPPORTED_10000baseT_Full |
11774                            SUPPORTED_FIBRE |
11775                            SUPPORTED_Autoneg |
11776                            SUPPORTED_Pause |
11777                            SUPPORTED_Asym_Pause),
11778         .media_type     = ETH_PHY_CX4,
11779         .ver_addr       = 0,
11780         .req_flow_ctrl  = 0,
11781         .req_line_speed = 0,
11782         .speed_cap_mask = 0,
11783         .req_duplex     = 0,
11784         .rsrv           = 0,
11785         .config_init    = (config_init_t)bnx2x_xgxs_config_init,
11786         .read_status    = (read_status_t)bnx2x_link_settings_status,
11787         .link_reset     = (link_reset_t)bnx2x_int_link_reset,
11788         .config_loopback = (config_loopback_t)bnx2x_set_xgxs_loopback,
11789         .format_fw_ver  = (format_fw_ver_t)NULL,
11790         .hw_reset       = (hw_reset_t)NULL,
11791         .set_link_led   = (set_link_led_t)NULL,
11792         .phy_specific_func = (phy_specific_func_t)bnx2x_xgxs_specific_func
11793 };
11794 static const struct bnx2x_phy phy_warpcore = {
11795         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
11796         .addr           = 0xff,
11797         .def_md_devad   = 0,
11798         .flags          = FLAGS_TX_ERROR_CHECK,
11799         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11800         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11801         .mdio_ctrl      = 0,
11802         .supported      = (SUPPORTED_10baseT_Half |
11803                            SUPPORTED_10baseT_Full |
11804                            SUPPORTED_100baseT_Half |
11805                            SUPPORTED_100baseT_Full |
11806                            SUPPORTED_1000baseT_Full |
11807                            SUPPORTED_1000baseKX_Full |
11808                            SUPPORTED_10000baseT_Full |
11809                            SUPPORTED_10000baseKR_Full |
11810                            SUPPORTED_20000baseKR2_Full |
11811                            SUPPORTED_20000baseMLD2_Full |
11812                            SUPPORTED_FIBRE |
11813                            SUPPORTED_Autoneg |
11814                            SUPPORTED_Pause |
11815                            SUPPORTED_Asym_Pause),
11816         .media_type     = ETH_PHY_UNSPECIFIED,
11817         .ver_addr       = 0,
11818         .req_flow_ctrl  = 0,
11819         .req_line_speed = 0,
11820         .speed_cap_mask = 0,
11821         /* req_duplex = */0,
11822         /* rsrv = */0,
11823         .config_init    = (config_init_t)bnx2x_warpcore_config_init,
11824         .read_status    = (read_status_t)bnx2x_warpcore_read_status,
11825         .link_reset     = (link_reset_t)bnx2x_warpcore_link_reset,
11826         .config_loopback = (config_loopback_t)bnx2x_set_warpcore_loopback,
11827         .format_fw_ver  = (format_fw_ver_t)NULL,
11828         .hw_reset       = (hw_reset_t)bnx2x_warpcore_hw_reset,
11829         .set_link_led   = (set_link_led_t)NULL,
11830         .phy_specific_func = (phy_specific_func_t)NULL
11831 };
11832
11833
11834 static const struct bnx2x_phy phy_7101 = {
11835         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
11836         .addr           = 0xff,
11837         .def_md_devad   = 0,
11838         .flags          = FLAGS_FAN_FAILURE_DET_REQ,
11839         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11840         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11841         .mdio_ctrl      = 0,
11842         .supported      = (SUPPORTED_10000baseT_Full |
11843                            SUPPORTED_TP |
11844                            SUPPORTED_Autoneg |
11845                            SUPPORTED_Pause |
11846                            SUPPORTED_Asym_Pause),
11847         .media_type     = ETH_PHY_BASE_T,
11848         .ver_addr       = 0,
11849         .req_flow_ctrl  = 0,
11850         .req_line_speed = 0,
11851         .speed_cap_mask = 0,
11852         .req_duplex     = 0,
11853         .rsrv           = 0,
11854         .config_init    = (config_init_t)bnx2x_7101_config_init,
11855         .read_status    = (read_status_t)bnx2x_7101_read_status,
11856         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
11857         .config_loopback = (config_loopback_t)bnx2x_7101_config_loopback,
11858         .format_fw_ver  = (format_fw_ver_t)bnx2x_7101_format_ver,
11859         .hw_reset       = (hw_reset_t)bnx2x_7101_hw_reset,
11860         .set_link_led   = (set_link_led_t)bnx2x_7101_set_link_led,
11861         .phy_specific_func = (phy_specific_func_t)NULL
11862 };
11863 static const struct bnx2x_phy phy_8073 = {
11864         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
11865         .addr           = 0xff,
11866         .def_md_devad   = 0,
11867         .flags          = 0,
11868         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11869         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11870         .mdio_ctrl      = 0,
11871         .supported      = (SUPPORTED_10000baseT_Full |
11872                            SUPPORTED_2500baseX_Full |
11873                            SUPPORTED_1000baseT_Full |
11874                            SUPPORTED_FIBRE |
11875                            SUPPORTED_Autoneg |
11876                            SUPPORTED_Pause |
11877                            SUPPORTED_Asym_Pause),
11878         .media_type     = ETH_PHY_KR,
11879         .ver_addr       = 0,
11880         .req_flow_ctrl  = 0,
11881         .req_line_speed = 0,
11882         .speed_cap_mask = 0,
11883         .req_duplex     = 0,
11884         .rsrv           = 0,
11885         .config_init    = (config_init_t)bnx2x_8073_config_init,
11886         .read_status    = (read_status_t)bnx2x_8073_read_status,
11887         .link_reset     = (link_reset_t)bnx2x_8073_link_reset,
11888         .config_loopback = (config_loopback_t)NULL,
11889         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
11890         .hw_reset       = (hw_reset_t)NULL,
11891         .set_link_led   = (set_link_led_t)NULL,
11892         .phy_specific_func = (phy_specific_func_t)bnx2x_8073_specific_func
11893 };
11894 static const struct bnx2x_phy phy_8705 = {
11895         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705,
11896         .addr           = 0xff,
11897         .def_md_devad   = 0,
11898         .flags          = FLAGS_INIT_XGXS_FIRST,
11899         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11900         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11901         .mdio_ctrl      = 0,
11902         .supported      = (SUPPORTED_10000baseT_Full |
11903                            SUPPORTED_FIBRE |
11904                            SUPPORTED_Pause |
11905                            SUPPORTED_Asym_Pause),
11906         .media_type     = ETH_PHY_XFP_FIBER,
11907         .ver_addr       = 0,
11908         .req_flow_ctrl  = 0,
11909         .req_line_speed = 0,
11910         .speed_cap_mask = 0,
11911         .req_duplex     = 0,
11912         .rsrv           = 0,
11913         .config_init    = (config_init_t)bnx2x_8705_config_init,
11914         .read_status    = (read_status_t)bnx2x_8705_read_status,
11915         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
11916         .config_loopback = (config_loopback_t)NULL,
11917         .format_fw_ver  = (format_fw_ver_t)bnx2x_null_format_ver,
11918         .hw_reset       = (hw_reset_t)NULL,
11919         .set_link_led   = (set_link_led_t)NULL,
11920         .phy_specific_func = (phy_specific_func_t)NULL
11921 };
11922 static const struct bnx2x_phy phy_8706 = {
11923         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706,
11924         .addr           = 0xff,
11925         .def_md_devad   = 0,
11926         .flags          = FLAGS_INIT_XGXS_FIRST,
11927         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11928         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11929         .mdio_ctrl      = 0,
11930         .supported      = (SUPPORTED_10000baseT_Full |
11931                            SUPPORTED_1000baseT_Full |
11932                            SUPPORTED_FIBRE |
11933                            SUPPORTED_Pause |
11934                            SUPPORTED_Asym_Pause),
11935         .media_type     = ETH_PHY_SFPP_10G_FIBER,
11936         .ver_addr       = 0,
11937         .req_flow_ctrl  = 0,
11938         .req_line_speed = 0,
11939         .speed_cap_mask = 0,
11940         .req_duplex     = 0,
11941         .rsrv           = 0,
11942         .config_init    = (config_init_t)bnx2x_8706_config_init,
11943         .read_status    = (read_status_t)bnx2x_8706_read_status,
11944         .link_reset     = (link_reset_t)bnx2x_common_ext_link_reset,
11945         .config_loopback = (config_loopback_t)NULL,
11946         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
11947         .hw_reset       = (hw_reset_t)NULL,
11948         .set_link_led   = (set_link_led_t)NULL,
11949         .phy_specific_func = (phy_specific_func_t)NULL
11950 };
11951
11952 static const struct bnx2x_phy phy_8726 = {
11953         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
11954         .addr           = 0xff,
11955         .def_md_devad   = 0,
11956         .flags          = (FLAGS_INIT_XGXS_FIRST |
11957                            FLAGS_TX_ERROR_CHECK),
11958         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11959         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11960         .mdio_ctrl      = 0,
11961         .supported      = (SUPPORTED_10000baseT_Full |
11962                            SUPPORTED_1000baseT_Full |
11963                            SUPPORTED_Autoneg |
11964                            SUPPORTED_FIBRE |
11965                            SUPPORTED_Pause |
11966                            SUPPORTED_Asym_Pause),
11967         .media_type     = ETH_PHY_NOT_PRESENT,
11968         .ver_addr       = 0,
11969         .req_flow_ctrl  = 0,
11970         .req_line_speed = 0,
11971         .speed_cap_mask = 0,
11972         .req_duplex     = 0,
11973         .rsrv           = 0,
11974         .config_init    = (config_init_t)bnx2x_8726_config_init,
11975         .read_status    = (read_status_t)bnx2x_8726_read_status,
11976         .link_reset     = (link_reset_t)bnx2x_8726_link_reset,
11977         .config_loopback = (config_loopback_t)bnx2x_8726_config_loopback,
11978         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
11979         .hw_reset       = (hw_reset_t)NULL,
11980         .set_link_led   = (set_link_led_t)NULL,
11981         .phy_specific_func = (phy_specific_func_t)NULL
11982 };
11983
11984 static const struct bnx2x_phy phy_8727 = {
11985         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
11986         .addr           = 0xff,
11987         .def_md_devad   = 0,
11988         .flags          = (FLAGS_FAN_FAILURE_DET_REQ |
11989                            FLAGS_TX_ERROR_CHECK),
11990         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11991         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11992         .mdio_ctrl      = 0,
11993         .supported      = (SUPPORTED_10000baseT_Full |
11994                            SUPPORTED_1000baseT_Full |
11995                            SUPPORTED_FIBRE |
11996                            SUPPORTED_Pause |
11997                            SUPPORTED_Asym_Pause),
11998         .media_type     = ETH_PHY_NOT_PRESENT,
11999         .ver_addr       = 0,
12000         .req_flow_ctrl  = 0,
12001         .req_line_speed = 0,
12002         .speed_cap_mask = 0,
12003         .req_duplex     = 0,
12004         .rsrv           = 0,
12005         .config_init    = (config_init_t)bnx2x_8727_config_init,
12006         .read_status    = (read_status_t)bnx2x_8727_read_status,
12007         .link_reset     = (link_reset_t)bnx2x_8727_link_reset,
12008         .config_loopback = (config_loopback_t)NULL,
12009         .format_fw_ver  = (format_fw_ver_t)bnx2x_format_ver,
12010         .hw_reset       = (hw_reset_t)bnx2x_8727_hw_reset,
12011         .set_link_led   = (set_link_led_t)bnx2x_8727_set_link_led,
12012         .phy_specific_func = (phy_specific_func_t)bnx2x_8727_specific_func
12013 };
12014 static const struct bnx2x_phy phy_8481 = {
12015         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
12016         .addr           = 0xff,
12017         .def_md_devad   = 0,
12018         .flags          = FLAGS_FAN_FAILURE_DET_REQ |
12019                           FLAGS_REARM_LATCH_SIGNAL,
12020         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12021         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12022         .mdio_ctrl      = 0,
12023         .supported      = (SUPPORTED_10baseT_Half |
12024                            SUPPORTED_10baseT_Full |
12025                            SUPPORTED_100baseT_Half |
12026                            SUPPORTED_100baseT_Full |
12027                            SUPPORTED_1000baseT_Full |
12028                            SUPPORTED_10000baseT_Full |
12029                            SUPPORTED_TP |
12030                            SUPPORTED_Autoneg |
12031                            SUPPORTED_Pause |
12032                            SUPPORTED_Asym_Pause),
12033         .media_type     = ETH_PHY_BASE_T,
12034         .ver_addr       = 0,
12035         .req_flow_ctrl  = 0,
12036         .req_line_speed = 0,
12037         .speed_cap_mask = 0,
12038         .req_duplex     = 0,
12039         .rsrv           = 0,
12040         .config_init    = (config_init_t)bnx2x_8481_config_init,
12041         .read_status    = (read_status_t)bnx2x_848xx_read_status,
12042         .link_reset     = (link_reset_t)bnx2x_8481_link_reset,
12043         .config_loopback = (config_loopback_t)NULL,
12044         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
12045         .hw_reset       = (hw_reset_t)bnx2x_8481_hw_reset,
12046         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
12047         .phy_specific_func = (phy_specific_func_t)NULL
12048 };
12049
12050 static const struct bnx2x_phy phy_84823 = {
12051         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823,
12052         .addr           = 0xff,
12053         .def_md_devad   = 0,
12054         .flags          = (FLAGS_FAN_FAILURE_DET_REQ |
12055                            FLAGS_REARM_LATCH_SIGNAL |
12056                            FLAGS_TX_ERROR_CHECK),
12057         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12058         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12059         .mdio_ctrl      = 0,
12060         .supported      = (SUPPORTED_10baseT_Half |
12061                            SUPPORTED_10baseT_Full |
12062                            SUPPORTED_100baseT_Half |
12063                            SUPPORTED_100baseT_Full |
12064                            SUPPORTED_1000baseT_Full |
12065                            SUPPORTED_10000baseT_Full |
12066                            SUPPORTED_TP |
12067                            SUPPORTED_Autoneg |
12068                            SUPPORTED_Pause |
12069                            SUPPORTED_Asym_Pause),
12070         .media_type     = ETH_PHY_BASE_T,
12071         .ver_addr       = 0,
12072         .req_flow_ctrl  = 0,
12073         .req_line_speed = 0,
12074         .speed_cap_mask = 0,
12075         .req_duplex     = 0,
12076         .rsrv           = 0,
12077         .config_init    = (config_init_t)bnx2x_848x3_config_init,
12078         .read_status    = (read_status_t)bnx2x_848xx_read_status,
12079         .link_reset     = (link_reset_t)bnx2x_848x3_link_reset,
12080         .config_loopback = (config_loopback_t)NULL,
12081         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
12082         .hw_reset       = (hw_reset_t)NULL,
12083         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
12084         .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func
12085 };
12086
12087 static const struct bnx2x_phy phy_84833 = {
12088         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833,
12089         .addr           = 0xff,
12090         .def_md_devad   = 0,
12091         .flags          = (FLAGS_FAN_FAILURE_DET_REQ |
12092                            FLAGS_REARM_LATCH_SIGNAL |
12093                            FLAGS_TX_ERROR_CHECK),
12094         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12095         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12096         .mdio_ctrl      = 0,
12097         .supported      = (SUPPORTED_100baseT_Half |
12098                            SUPPORTED_100baseT_Full |
12099                            SUPPORTED_1000baseT_Full |
12100                            SUPPORTED_10000baseT_Full |
12101                            SUPPORTED_TP |
12102                            SUPPORTED_Autoneg |
12103                            SUPPORTED_Pause |
12104                            SUPPORTED_Asym_Pause),
12105         .media_type     = ETH_PHY_BASE_T,
12106         .ver_addr       = 0,
12107         .req_flow_ctrl  = 0,
12108         .req_line_speed = 0,
12109         .speed_cap_mask = 0,
12110         .req_duplex     = 0,
12111         .rsrv           = 0,
12112         .config_init    = (config_init_t)bnx2x_848x3_config_init,
12113         .read_status    = (read_status_t)bnx2x_848xx_read_status,
12114         .link_reset     = (link_reset_t)bnx2x_848x3_link_reset,
12115         .config_loopback = (config_loopback_t)NULL,
12116         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
12117         .hw_reset       = (hw_reset_t)bnx2x_84833_hw_reset_phy,
12118         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
12119         .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func
12120 };
12121
12122 static const struct bnx2x_phy phy_84834 = {
12123         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834,
12124         .addr           = 0xff,
12125         .def_md_devad   = 0,
12126         .flags          = FLAGS_FAN_FAILURE_DET_REQ |
12127                             FLAGS_REARM_LATCH_SIGNAL,
12128         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12129         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12130         .mdio_ctrl      = 0,
12131         .supported      = (SUPPORTED_100baseT_Half |
12132                            SUPPORTED_100baseT_Full |
12133                            SUPPORTED_1000baseT_Full |
12134                            SUPPORTED_10000baseT_Full |
12135                            SUPPORTED_TP |
12136                            SUPPORTED_Autoneg |
12137                            SUPPORTED_Pause |
12138                            SUPPORTED_Asym_Pause),
12139         .media_type     = ETH_PHY_BASE_T,
12140         .ver_addr       = 0,
12141         .req_flow_ctrl  = 0,
12142         .req_line_speed = 0,
12143         .speed_cap_mask = 0,
12144         .req_duplex     = 0,
12145         .rsrv           = 0,
12146         .config_init    = (config_init_t)bnx2x_848x3_config_init,
12147         .read_status    = (read_status_t)bnx2x_848xx_read_status,
12148         .link_reset     = (link_reset_t)bnx2x_848x3_link_reset,
12149         .config_loopback = (config_loopback_t)NULL,
12150         .format_fw_ver  = (format_fw_ver_t)bnx2x_848xx_format_ver,
12151         .hw_reset       = (hw_reset_t)bnx2x_84833_hw_reset_phy,
12152         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
12153         .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func
12154 };
12155
12156 static const struct bnx2x_phy phy_84858 = {
12157         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858,
12158         .addr           = 0xff,
12159         .def_md_devad   = 0,
12160         .flags          = FLAGS_FAN_FAILURE_DET_REQ |
12161                             FLAGS_REARM_LATCH_SIGNAL,
12162         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12163         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12164         .mdio_ctrl      = 0,
12165         .supported      = (SUPPORTED_100baseT_Half |
12166                            SUPPORTED_100baseT_Full |
12167                            SUPPORTED_1000baseT_Full |
12168                            SUPPORTED_10000baseT_Full |
12169                            SUPPORTED_TP |
12170                            SUPPORTED_Autoneg |
12171                            SUPPORTED_Pause |
12172                            SUPPORTED_Asym_Pause),
12173         .media_type     = ETH_PHY_BASE_T,
12174         .ver_addr       = 0,
12175         .req_flow_ctrl  = 0,
12176         .req_line_speed = 0,
12177         .speed_cap_mask = 0,
12178         .req_duplex     = 0,
12179         .rsrv           = 0,
12180         .config_init    = (config_init_t)bnx2x_848x3_config_init,
12181         .read_status    = (read_status_t)bnx2x_848xx_read_status,
12182         .link_reset     = (link_reset_t)bnx2x_848x3_link_reset,
12183         .config_loopback = (config_loopback_t)NULL,
12184         .format_fw_ver  = (format_fw_ver_t)bnx2x_8485x_format_ver,
12185         .hw_reset       = (hw_reset_t)bnx2x_84833_hw_reset_phy,
12186         .set_link_led   = (set_link_led_t)bnx2x_848xx_set_link_led,
12187         .phy_specific_func = (phy_specific_func_t)bnx2x_848xx_specific_func
12188 };
12189
12190 static const struct bnx2x_phy phy_54618se = {
12191         .type           = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE,
12192         .addr           = 0xff,
12193         .def_md_devad   = 0,
12194         .flags          = FLAGS_INIT_XGXS_FIRST,
12195         .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12196         .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12197         .mdio_ctrl      = 0,
12198         .supported      = (SUPPORTED_10baseT_Half |
12199                            SUPPORTED_10baseT_Full |
12200                            SUPPORTED_100baseT_Half |
12201                            SUPPORTED_100baseT_Full |
12202                            SUPPORTED_1000baseT_Full |
12203                            SUPPORTED_TP |
12204                            SUPPORTED_Autoneg |
12205                            SUPPORTED_Pause |
12206                            SUPPORTED_Asym_Pause),
12207         .media_type     = ETH_PHY_BASE_T,
12208         .ver_addr       = 0,
12209         .req_flow_ctrl  = 0,
12210         .req_line_speed = 0,
12211         .speed_cap_mask = 0,
12212         /* req_duplex = */0,
12213         /* rsrv = */0,
12214         .config_init    = (config_init_t)bnx2x_54618se_config_init,
12215         .read_status    = (read_status_t)bnx2x_54618se_read_status,
12216         .link_reset     = (link_reset_t)bnx2x_54618se_link_reset,
12217         .config_loopback = (config_loopback_t)bnx2x_54618se_config_loopback,
12218         .format_fw_ver  = (format_fw_ver_t)NULL,
12219         .hw_reset       = (hw_reset_t)NULL,
12220         .set_link_led   = (set_link_led_t)bnx2x_5461x_set_link_led,
12221         .phy_specific_func = (phy_specific_func_t)bnx2x_54618se_specific_func
12222 };
12223 /*****************************************************************/
12224 /*                                                               */
12225 /* Populate the phy according. Main function: bnx2x_populate_phy   */
12226 /*                                                               */
12227 /*****************************************************************/
12228
12229 static void bnx2x_populate_preemphasis(struct bnx2x *bp, u32 shmem_base,
12230                                      struct bnx2x_phy *phy, u8 port,
12231                                      u8 phy_index)
12232 {
12233         /* Get the 4 lanes xgxs config rx and tx */
12234         u32 rx = 0, tx = 0, i;
12235         for (i = 0; i < 2; i++) {
12236                 /* INT_PHY and EXT_PHY1 share the same value location in
12237                  * the shmem. When num_phys is greater than 1, than this value
12238                  * applies only to EXT_PHY1
12239                  */
12240                 if (phy_index == INT_PHY || phy_index == EXT_PHY1) {
12241                         rx = REG_RD(bp, shmem_base +
12242                                     offsetof(struct shmem_region,
12243                           dev_info.port_hw_config[port].xgxs_config_rx[i<<1]));
12244
12245                         tx = REG_RD(bp, shmem_base +
12246                                     offsetof(struct shmem_region,
12247                           dev_info.port_hw_config[port].xgxs_config_tx[i<<1]));
12248                 } else {
12249                         rx = REG_RD(bp, shmem_base +
12250                                     offsetof(struct shmem_region,
12251                          dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
12252
12253                         tx = REG_RD(bp, shmem_base +
12254                                     offsetof(struct shmem_region,
12255                          dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
12256                 }
12257
12258                 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff);
12259                 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);
12260
12261                 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff);
12262                 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);
12263         }
12264 }
12265
12266 static u32 bnx2x_get_ext_phy_config(struct bnx2x *bp, u32 shmem_base,
12267                                     u8 phy_index, u8 port)
12268 {
12269         u32 ext_phy_config = 0;
12270         switch (phy_index) {
12271         case EXT_PHY1:
12272                 ext_phy_config = REG_RD(bp, shmem_base +
12273                                               offsetof(struct shmem_region,
12274                         dev_info.port_hw_config[port].external_phy_config));
12275                 break;
12276         case EXT_PHY2:
12277                 ext_phy_config = REG_RD(bp, shmem_base +
12278                                               offsetof(struct shmem_region,
12279                         dev_info.port_hw_config[port].external_phy_config2));
12280                 break;
12281         default:
12282                 DP(NETIF_MSG_LINK, "Invalid phy_index %d\n", phy_index);
12283                 return -EINVAL;
12284         }
12285
12286         return ext_phy_config;
12287 }
12288 static int bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port,
12289                                   struct bnx2x_phy *phy)
12290 {
12291         u32 phy_addr;
12292         u32 chip_id;
12293         u32 switch_cfg = (REG_RD(bp, shmem_base +
12294                                        offsetof(struct shmem_region,
12295                         dev_info.port_feature_config[port].link_config)) &
12296                           PORT_FEATURE_CONNECTED_SWITCH_MASK);
12297         chip_id = (REG_RD(bp, MISC_REG_CHIP_NUM) << 16) |
12298                 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12);
12299
12300         DP(NETIF_MSG_LINK, ":chip_id = 0x%x\n", chip_id);
12301         if (USES_WARPCORE(bp)) {
12302                 u32 serdes_net_if;
12303                 phy_addr = REG_RD(bp,
12304                                   MISC_REG_WC0_CTRL_PHY_ADDR);
12305                 *phy = phy_warpcore;
12306                 if (REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR) == 0x3)
12307                         phy->flags |= FLAGS_4_PORT_MODE;
12308                 else
12309                         phy->flags &= ~FLAGS_4_PORT_MODE;
12310                         /* Check Dual mode */
12311                 serdes_net_if = (REG_RD(bp, shmem_base +
12312                                         offsetof(struct shmem_region, dev_info.
12313                                         port_hw_config[port].default_cfg)) &
12314                                  PORT_HW_CFG_NET_SERDES_IF_MASK);
12315                 /* Set the appropriate supported and flags indications per
12316                  * interface type of the chip
12317                  */
12318                 switch (serdes_net_if) {
12319                 case PORT_HW_CFG_NET_SERDES_IF_SGMII:
12320                         phy->supported &= (SUPPORTED_10baseT_Half |
12321                                            SUPPORTED_10baseT_Full |
12322                                            SUPPORTED_100baseT_Half |
12323                                            SUPPORTED_100baseT_Full |
12324                                            SUPPORTED_1000baseT_Full |
12325                                            SUPPORTED_FIBRE |
12326                                            SUPPORTED_Autoneg |
12327                                            SUPPORTED_Pause |
12328                                            SUPPORTED_Asym_Pause);
12329                         phy->media_type = ETH_PHY_BASE_T;
12330                         break;
12331                 case PORT_HW_CFG_NET_SERDES_IF_XFI:
12332                         phy->supported &= (SUPPORTED_1000baseT_Full |
12333                                            SUPPORTED_10000baseT_Full |
12334                                            SUPPORTED_FIBRE |
12335                                            SUPPORTED_Pause |
12336                                            SUPPORTED_Asym_Pause);
12337                         phy->media_type = ETH_PHY_XFP_FIBER;
12338                         break;
12339                 case PORT_HW_CFG_NET_SERDES_IF_SFI:
12340                         phy->supported &= (SUPPORTED_1000baseT_Full |
12341                                            SUPPORTED_10000baseT_Full |
12342                                            SUPPORTED_FIBRE |
12343                                            SUPPORTED_Pause |
12344                                            SUPPORTED_Asym_Pause);
12345                         phy->media_type = ETH_PHY_SFPP_10G_FIBER;
12346                         break;
12347                 case PORT_HW_CFG_NET_SERDES_IF_KR:
12348                         phy->media_type = ETH_PHY_KR;
12349                         phy->supported &= (SUPPORTED_1000baseKX_Full |
12350                                            SUPPORTED_10000baseKR_Full |
12351                                            SUPPORTED_FIBRE |
12352                                            SUPPORTED_Autoneg |
12353                                            SUPPORTED_Pause |
12354                                            SUPPORTED_Asym_Pause);
12355                         break;
12356                 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
12357                         phy->media_type = ETH_PHY_KR;
12358                         phy->flags |= FLAGS_WC_DUAL_MODE;
12359                         phy->supported &= (SUPPORTED_20000baseMLD2_Full |
12360                                            SUPPORTED_FIBRE |
12361                                            SUPPORTED_Pause |
12362                                            SUPPORTED_Asym_Pause);
12363                         break;
12364                 case PORT_HW_CFG_NET_SERDES_IF_KR2:
12365                         phy->media_type = ETH_PHY_KR;
12366                         phy->flags |= FLAGS_WC_DUAL_MODE;
12367                         phy->supported &= (SUPPORTED_20000baseKR2_Full |
12368                                            SUPPORTED_10000baseKR_Full |
12369                                            SUPPORTED_1000baseKX_Full |
12370                                            SUPPORTED_Autoneg |
12371                                            SUPPORTED_FIBRE |
12372                                            SUPPORTED_Pause |
12373                                            SUPPORTED_Asym_Pause);
12374                         phy->flags &= ~FLAGS_TX_ERROR_CHECK;
12375                         break;
12376                 default:
12377                         DP(NETIF_MSG_LINK, "Unknown WC interface type 0x%x\n",
12378                                        serdes_net_if);
12379                         break;
12380                 }
12381
12382                 /* Enable MDC/MDIO work-around for E3 A0 since free running MDC
12383                  * was not set as expected. For B0, ECO will be enabled so there
12384                  * won't be an issue there
12385                  */
12386                 if (CHIP_REV(bp) == CHIP_REV_Ax)
12387                         phy->flags |= FLAGS_MDC_MDIO_WA;
12388                 else
12389                         phy->flags |= FLAGS_MDC_MDIO_WA_B0;
12390         } else {
12391                 switch (switch_cfg) {
12392                 case SWITCH_CFG_1G:
12393                         phy_addr = REG_RD(bp,
12394                                           NIG_REG_SERDES0_CTRL_PHY_ADDR +
12395                                           port * 0x10);
12396                         *phy = phy_serdes;
12397                         break;
12398                 case SWITCH_CFG_10G:
12399                         phy_addr = REG_RD(bp,
12400                                           NIG_REG_XGXS0_CTRL_PHY_ADDR +
12401                                           port * 0x18);
12402                         *phy = phy_xgxs;
12403                         break;
12404                 default:
12405                         DP(NETIF_MSG_LINK, "Invalid switch_cfg\n");
12406                         return -EINVAL;
12407                 }
12408         }
12409         phy->addr = (u8)phy_addr;
12410         phy->mdio_ctrl = bnx2x_get_emac_base(bp,
12411                                             SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
12412                                             port);
12413         if (CHIP_IS_E2(bp))
12414                 phy->def_md_devad = E2_DEFAULT_PHY_DEV_ADDR;
12415         else
12416                 phy->def_md_devad = DEFAULT_PHY_DEV_ADDR;
12417
12418         DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n",
12419                    port, phy->addr, phy->mdio_ctrl);
12420
12421         bnx2x_populate_preemphasis(bp, shmem_base, phy, port, INT_PHY);
12422         return 0;
12423 }
12424
12425 static int bnx2x_populate_ext_phy(struct bnx2x *bp,
12426                                   u8 phy_index,
12427                                   u32 shmem_base,
12428                                   u32 shmem2_base,
12429                                   u8 port,
12430                                   struct bnx2x_phy *phy)
12431 {
12432         u32 ext_phy_config, phy_type, config2;
12433         u32 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH;
12434         ext_phy_config = bnx2x_get_ext_phy_config(bp, shmem_base,
12435                                                   phy_index, port);
12436         phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
12437         /* Select the phy type */
12438         switch (phy_type) {
12439         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
12440                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED;
12441                 *phy = phy_8073;
12442                 break;
12443         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
12444                 *phy = phy_8705;
12445                 break;
12446         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
12447                 *phy = phy_8706;
12448                 break;
12449         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
12450                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
12451                 *phy = phy_8726;
12452                 break;
12453         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
12454                 /* BCM8727_NOC => BCM8727 no over current */
12455                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
12456                 *phy = phy_8727;
12457                 phy->flags |= FLAGS_NOC;
12458                 break;
12459         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
12460         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
12461                 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
12462                 *phy = phy_8727;
12463                 break;
12464         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
12465                 *phy = phy_8481;
12466                 break;
12467         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
12468                 *phy = phy_84823;
12469                 break;
12470         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
12471                 *phy = phy_84833;
12472                 break;
12473         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834:
12474                 *phy = phy_84834;
12475                 break;
12476         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858:
12477                 *phy = phy_84858;
12478                 break;
12479         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616:
12480         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE:
12481                 *phy = phy_54618se;
12482                 if (phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
12483                         phy->flags |= FLAGS_EEE;
12484                 break;
12485         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
12486                 *phy = phy_7101;
12487                 break;
12488         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
12489                 *phy = phy_null;
12490                 return -EINVAL;
12491         default:
12492                 *phy = phy_null;
12493                 /* In case external PHY wasn't found */
12494                 if ((phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
12495                     (phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
12496                         return -EINVAL;
12497                 return 0;
12498         }
12499
12500         phy->addr = XGXS_EXT_PHY_ADDR(ext_phy_config);
12501         bnx2x_populate_preemphasis(bp, shmem_base, phy, port, phy_index);
12502
12503         /* The shmem address of the phy version is located on different
12504          * structures. In case this structure is too old, do not set
12505          * the address
12506          */
12507         config2 = REG_RD(bp, shmem_base + offsetof(struct shmem_region,
12508                                         dev_info.shared_hw_config.config2));
12509         if (phy_index == EXT_PHY1) {
12510                 phy->ver_addr = shmem_base + offsetof(struct shmem_region,
12511                                 port_mb[port].ext_phy_fw_version);
12512
12513                 /* Check specific mdc mdio settings */
12514                 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK)
12515                         mdc_mdio_access = config2 &
12516                         SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
12517         } else {
12518                 u32 size = REG_RD(bp, shmem2_base);
12519
12520                 if (size >
12521                     offsetof(struct shmem2_region, ext_phy_fw_version2)) {
12522                         phy->ver_addr = shmem2_base +
12523                             offsetof(struct shmem2_region,
12524                                      ext_phy_fw_version2[port]);
12525                 }
12526                 /* Check specific mdc mdio settings */
12527                 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
12528                         mdc_mdio_access = (config2 &
12529                         SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >>
12530                         (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT -
12531                          SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);
12532         }
12533         phy->mdio_ctrl = bnx2x_get_emac_base(bp, mdc_mdio_access, port);
12534
12535         if (bnx2x_is_8483x_8485x(phy) && (phy->ver_addr)) {
12536                 /* Remove 100Mb link supported for BCM84833/4 when phy fw
12537                  * version lower than or equal to 1.39
12538                  */
12539                 u32 raw_ver = REG_RD(bp, phy->ver_addr);
12540                 if (((raw_ver & 0x7F) <= 39) &&
12541                     (((raw_ver & 0xF80) >> 7) <= 1))
12542                         phy->supported &= ~(SUPPORTED_100baseT_Half |
12543                                             SUPPORTED_100baseT_Full);
12544         }
12545
12546         DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n",
12547                    phy_type, port, phy_index);
12548         DP(NETIF_MSG_LINK, "             addr=0x%x, mdio_ctl=0x%x\n",
12549                    phy->addr, phy->mdio_ctrl);
12550         return 0;
12551 }
12552
12553 static int bnx2x_populate_phy(struct bnx2x *bp, u8 phy_index, u32 shmem_base,
12554                               u32 shmem2_base, u8 port, struct bnx2x_phy *phy)
12555 {
12556         int status = 0;
12557         phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;
12558         if (phy_index == INT_PHY)
12559                 return bnx2x_populate_int_phy(bp, shmem_base, port, phy);
12560         status = bnx2x_populate_ext_phy(bp, phy_index, shmem_base, shmem2_base,
12561                                         port, phy);
12562         return status;
12563 }
12564
12565 static void bnx2x_phy_def_cfg(struct link_params *params,
12566                               struct bnx2x_phy *phy,
12567                               u8 phy_index)
12568 {
12569         struct bnx2x *bp = params->bp;
12570         u32 link_config;
12571         /* Populate the default phy configuration for MF mode */
12572         if (phy_index == EXT_PHY2) {
12573                 link_config = REG_RD(bp, params->shmem_base +
12574                                      offsetof(struct shmem_region, dev_info.
12575                         port_feature_config[params->port].link_config2));
12576                 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
12577                                              offsetof(struct shmem_region,
12578                                                       dev_info.
12579                         port_hw_config[params->port].speed_capability_mask2));
12580         } else {
12581                 link_config = REG_RD(bp, params->shmem_base +
12582                                      offsetof(struct shmem_region, dev_info.
12583                                 port_feature_config[params->port].link_config));
12584                 phy->speed_cap_mask = REG_RD(bp, params->shmem_base +
12585                                              offsetof(struct shmem_region,
12586                                                       dev_info.
12587                         port_hw_config[params->port].speed_capability_mask));
12588         }
12589         DP(NETIF_MSG_LINK,
12590            "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x\n",
12591            phy_index, link_config, phy->speed_cap_mask);
12592
12593         phy->req_duplex = DUPLEX_FULL;
12594         switch (link_config  & PORT_FEATURE_LINK_SPEED_MASK) {
12595         case PORT_FEATURE_LINK_SPEED_10M_HALF:
12596                 phy->req_duplex = DUPLEX_HALF;
12597         case PORT_FEATURE_LINK_SPEED_10M_FULL:
12598                 phy->req_line_speed = SPEED_10;
12599                 break;
12600         case PORT_FEATURE_LINK_SPEED_100M_HALF:
12601                 phy->req_duplex = DUPLEX_HALF;
12602         case PORT_FEATURE_LINK_SPEED_100M_FULL:
12603                 phy->req_line_speed = SPEED_100;
12604                 break;
12605         case PORT_FEATURE_LINK_SPEED_1G:
12606                 phy->req_line_speed = SPEED_1000;
12607                 break;
12608         case PORT_FEATURE_LINK_SPEED_2_5G:
12609                 phy->req_line_speed = SPEED_2500;
12610                 break;
12611         case PORT_FEATURE_LINK_SPEED_10G_CX4:
12612                 phy->req_line_speed = SPEED_10000;
12613                 break;
12614         default:
12615                 phy->req_line_speed = SPEED_AUTO_NEG;
12616                 break;
12617         }
12618
12619         switch (link_config  & PORT_FEATURE_FLOW_CONTROL_MASK) {
12620         case PORT_FEATURE_FLOW_CONTROL_AUTO:
12621                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_AUTO;
12622                 break;
12623         case PORT_FEATURE_FLOW_CONTROL_TX:
12624                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_TX;
12625                 break;
12626         case PORT_FEATURE_FLOW_CONTROL_RX:
12627                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_RX;
12628                 break;
12629         case PORT_FEATURE_FLOW_CONTROL_BOTH:
12630                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_BOTH;
12631                 break;
12632         default:
12633                 phy->req_flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12634                 break;
12635         }
12636 }
12637
12638 u32 bnx2x_phy_selection(struct link_params *params)
12639 {
12640         u32 phy_config_swapped, prio_cfg;
12641         u32 return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT;
12642
12643         phy_config_swapped = params->multi_phy_config &
12644                 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
12645
12646         prio_cfg = params->multi_phy_config &
12647                         PORT_HW_CFG_PHY_SELECTION_MASK;
12648
12649         if (phy_config_swapped) {
12650                 switch (prio_cfg) {
12651                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
12652                      return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY;
12653                      break;
12654                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
12655                      return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY;
12656                      break;
12657                 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
12658                      return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
12659                      break;
12660                 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
12661                      return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
12662                      break;
12663                 }
12664         } else
12665                 return_cfg = prio_cfg;
12666
12667         return return_cfg;
12668 }
12669
12670 int bnx2x_phy_probe(struct link_params *params)
12671 {
12672         u8 phy_index, actual_phy_idx;
12673         u32 phy_config_swapped, sync_offset, media_types;
12674         struct bnx2x *bp = params->bp;
12675         struct bnx2x_phy *phy;
12676         params->num_phys = 0;
12677         DP(NETIF_MSG_LINK, "Begin phy probe\n");
12678         phy_config_swapped = params->multi_phy_config &
12679                 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
12680
12681         for (phy_index = INT_PHY; phy_index < MAX_PHYS;
12682               phy_index++) {
12683                 actual_phy_idx = phy_index;
12684                 if (phy_config_swapped) {
12685                         if (phy_index == EXT_PHY1)
12686                                 actual_phy_idx = EXT_PHY2;
12687                         else if (phy_index == EXT_PHY2)
12688                                 actual_phy_idx = EXT_PHY1;
12689                 }
12690                 DP(NETIF_MSG_LINK, "phy_config_swapped %x, phy_index %x,"
12691                                " actual_phy_idx %x\n", phy_config_swapped,
12692                            phy_index, actual_phy_idx);
12693                 phy = &params->phy[actual_phy_idx];
12694                 if (bnx2x_populate_phy(bp, phy_index, params->shmem_base,
12695                                        params->shmem2_base, params->port,
12696                                        phy) != 0) {
12697                         params->num_phys = 0;
12698                         DP(NETIF_MSG_LINK, "phy probe failed in phy index %d\n",
12699                                    phy_index);
12700                         for (phy_index = INT_PHY;
12701                               phy_index < MAX_PHYS;
12702                               phy_index++)
12703                                 *phy = phy_null;
12704                         return -EINVAL;
12705                 }
12706                 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)
12707                         break;
12708
12709                 if (params->feature_config_flags &
12710                     FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET)
12711                         phy->flags &= ~FLAGS_TX_ERROR_CHECK;
12712
12713                 if (!(params->feature_config_flags &
12714                       FEATURE_CONFIG_MT_SUPPORT))
12715                         phy->flags |= FLAGS_MDC_MDIO_WA_G;
12716
12717                 sync_offset = params->shmem_base +
12718                         offsetof(struct shmem_region,
12719                         dev_info.port_hw_config[params->port].media_type);
12720                 media_types = REG_RD(bp, sync_offset);
12721
12722                 /* Update media type for non-PMF sync only for the first time
12723                  * In case the media type changes afterwards, it will be updated
12724                  * using the update_status function
12725                  */
12726                 if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
12727                                     (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
12728                                      actual_phy_idx))) == 0) {
12729                         media_types |= ((phy->media_type &
12730                                         PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
12731                                 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
12732                                  actual_phy_idx));
12733                 }
12734                 REG_WR(bp, sync_offset, media_types);
12735
12736                 bnx2x_phy_def_cfg(params, phy, phy_index);
12737                 params->num_phys++;
12738         }
12739
12740         DP(NETIF_MSG_LINK, "End phy probe. #phys found %x\n", params->num_phys);
12741         return 0;
12742 }
12743
12744 static void bnx2x_init_bmac_loopback(struct link_params *params,
12745                                      struct link_vars *vars)
12746 {
12747         struct bnx2x *bp = params->bp;
12748                 vars->link_up = 1;
12749                 vars->line_speed = SPEED_10000;
12750                 vars->duplex = DUPLEX_FULL;
12751                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12752                 vars->mac_type = MAC_TYPE_BMAC;
12753
12754                 vars->phy_flags = PHY_XGXS_FLAG;
12755
12756                 bnx2x_xgxs_deassert(params);
12757
12758                 /* Set bmac loopback */
12759                 bnx2x_bmac_enable(params, vars, 1, 1);
12760
12761                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12762 }
12763
12764 static void bnx2x_init_emac_loopback(struct link_params *params,
12765                                      struct link_vars *vars)
12766 {
12767         struct bnx2x *bp = params->bp;
12768                 vars->link_up = 1;
12769                 vars->line_speed = SPEED_1000;
12770                 vars->duplex = DUPLEX_FULL;
12771                 vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12772                 vars->mac_type = MAC_TYPE_EMAC;
12773
12774                 vars->phy_flags = PHY_XGXS_FLAG;
12775
12776                 bnx2x_xgxs_deassert(params);
12777                 /* Set bmac loopback */
12778                 bnx2x_emac_enable(params, vars, 1);
12779                 bnx2x_emac_program(params, vars);
12780                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12781 }
12782
12783 static void bnx2x_init_xmac_loopback(struct link_params *params,
12784                                      struct link_vars *vars)
12785 {
12786         struct bnx2x *bp = params->bp;
12787         vars->link_up = 1;
12788         if (!params->req_line_speed[0])
12789                 vars->line_speed = SPEED_10000;
12790         else
12791                 vars->line_speed = params->req_line_speed[0];
12792         vars->duplex = DUPLEX_FULL;
12793         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12794         vars->mac_type = MAC_TYPE_XMAC;
12795         vars->phy_flags = PHY_XGXS_FLAG;
12796         /* Set WC to loopback mode since link is required to provide clock
12797          * to the XMAC in 20G mode
12798          */
12799         bnx2x_set_aer_mmd(params, &params->phy[0]);
12800         bnx2x_warpcore_reset_lane(bp, &params->phy[0], 0);
12801         params->phy[INT_PHY].config_loopback(
12802                         &params->phy[INT_PHY],
12803                         params);
12804
12805         bnx2x_xmac_enable(params, vars, 1);
12806         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12807 }
12808
12809 static void bnx2x_init_umac_loopback(struct link_params *params,
12810                                      struct link_vars *vars)
12811 {
12812         struct bnx2x *bp = params->bp;
12813         vars->link_up = 1;
12814         vars->line_speed = SPEED_1000;
12815         vars->duplex = DUPLEX_FULL;
12816         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12817         vars->mac_type = MAC_TYPE_UMAC;
12818         vars->phy_flags = PHY_XGXS_FLAG;
12819         bnx2x_umac_enable(params, vars, 1);
12820
12821         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12822 }
12823
12824 static void bnx2x_init_xgxs_loopback(struct link_params *params,
12825                                      struct link_vars *vars)
12826 {
12827         struct bnx2x *bp = params->bp;
12828         struct bnx2x_phy *int_phy = &params->phy[INT_PHY];
12829         vars->link_up = 1;
12830         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
12831         vars->duplex = DUPLEX_FULL;
12832         if (params->req_line_speed[0] == SPEED_1000)
12833                 vars->line_speed = SPEED_1000;
12834         else if ((params->req_line_speed[0] == SPEED_20000) ||
12835                  (int_phy->flags & FLAGS_WC_DUAL_MODE))
12836                 vars->line_speed = SPEED_20000;
12837         else
12838                 vars->line_speed = SPEED_10000;
12839
12840         if (!USES_WARPCORE(bp))
12841                 bnx2x_xgxs_deassert(params);
12842         bnx2x_link_initialize(params, vars);
12843
12844         if (params->req_line_speed[0] == SPEED_1000) {
12845                 if (USES_WARPCORE(bp))
12846                         bnx2x_umac_enable(params, vars, 0);
12847                 else {
12848                         bnx2x_emac_program(params, vars);
12849                         bnx2x_emac_enable(params, vars, 0);
12850                 }
12851         } else {
12852                 if (USES_WARPCORE(bp))
12853                         bnx2x_xmac_enable(params, vars, 0);
12854                 else
12855                         bnx2x_bmac_enable(params, vars, 0, 1);
12856         }
12857
12858         if (params->loopback_mode == LOOPBACK_XGXS) {
12859                 /* Set 10G XGXS loopback */
12860                 int_phy->config_loopback(int_phy, params);
12861         } else {
12862                 /* Set external phy loopback */
12863                 u8 phy_index;
12864                 for (phy_index = EXT_PHY1;
12865                       phy_index < params->num_phys; phy_index++)
12866                         if (params->phy[phy_index].config_loopback)
12867                                 params->phy[phy_index].config_loopback(
12868                                         &params->phy[phy_index],
12869                                         params);
12870         }
12871         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12872
12873         bnx2x_set_led(params, vars, LED_MODE_OPER, vars->line_speed);
12874 }
12875
12876 void bnx2x_set_rx_filter(struct link_params *params, u8 en)
12877 {
12878         struct bnx2x *bp = params->bp;
12879         u8 val = en * 0x1F;
12880
12881         /* Open / close the gate between the NIG and the BRB */
12882         if (!CHIP_IS_E1x(bp))
12883                 val |= en * 0x20;
12884         REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + params->port*4, val);
12885
12886         if (!CHIP_IS_E1(bp)) {
12887                 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port*4,
12888                        en*0x3);
12889         }
12890
12891         REG_WR(bp, (params->port ? NIG_REG_LLH1_BRB1_NOT_MCP :
12892                     NIG_REG_LLH0_BRB1_NOT_MCP), en);
12893 }
12894 static int bnx2x_avoid_link_flap(struct link_params *params,
12895                                             struct link_vars *vars)
12896 {
12897         u32 phy_idx;
12898         u32 dont_clear_stat, lfa_sts;
12899         struct bnx2x *bp = params->bp;
12900
12901         bnx2x_set_mdio_emac_per_phy(bp, params);
12902         /* Sync the link parameters */
12903         bnx2x_link_status_update(params, vars);
12904
12905         /*
12906          * The module verification was already done by previous link owner,
12907          * so this call is meant only to get warning message
12908          */
12909
12910         for (phy_idx = INT_PHY; phy_idx < params->num_phys; phy_idx++) {
12911                 struct bnx2x_phy *phy = &params->phy[phy_idx];
12912                 if (phy->phy_specific_func) {
12913                         DP(NETIF_MSG_LINK, "Calling PHY specific func\n");
12914                         phy->phy_specific_func(phy, params, PHY_INIT);
12915                 }
12916                 if ((phy->media_type == ETH_PHY_SFPP_10G_FIBER) ||
12917                     (phy->media_type == ETH_PHY_SFP_1G_FIBER) ||
12918                     (phy->media_type == ETH_PHY_DA_TWINAX))
12919                         bnx2x_verify_sfp_module(phy, params);
12920         }
12921         lfa_sts = REG_RD(bp, params->lfa_base +
12922                          offsetof(struct shmem_lfa,
12923                                   lfa_sts));
12924
12925         dont_clear_stat = lfa_sts & SHMEM_LFA_DONT_CLEAR_STAT;
12926
12927         /* Re-enable the NIG/MAC */
12928         if (CHIP_IS_E3(bp)) {
12929                 if (!dont_clear_stat) {
12930                         REG_WR(bp, GRCBASE_MISC +
12931                                MISC_REGISTERS_RESET_REG_2_CLEAR,
12932                                (MISC_REGISTERS_RESET_REG_2_MSTAT0 <<
12933                                 params->port));
12934                         REG_WR(bp, GRCBASE_MISC +
12935                                MISC_REGISTERS_RESET_REG_2_SET,
12936                                (MISC_REGISTERS_RESET_REG_2_MSTAT0 <<
12937                                 params->port));
12938                 }
12939                 if (vars->line_speed < SPEED_10000)
12940                         bnx2x_umac_enable(params, vars, 0);
12941                 else
12942                         bnx2x_xmac_enable(params, vars, 0);
12943         } else {
12944                 if (vars->line_speed < SPEED_10000)
12945                         bnx2x_emac_enable(params, vars, 0);
12946                 else
12947                         bnx2x_bmac_enable(params, vars, 0, !dont_clear_stat);
12948         }
12949
12950         /* Increment LFA count */
12951         lfa_sts = ((lfa_sts & ~LINK_FLAP_AVOIDANCE_COUNT_MASK) |
12952                    (((((lfa_sts & LINK_FLAP_AVOIDANCE_COUNT_MASK) >>
12953                        LINK_FLAP_AVOIDANCE_COUNT_OFFSET) + 1) & 0xff)
12954                     << LINK_FLAP_AVOIDANCE_COUNT_OFFSET));
12955         /* Clear link flap reason */
12956         lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK;
12957
12958         REG_WR(bp, params->lfa_base +
12959                offsetof(struct shmem_lfa, lfa_sts), lfa_sts);
12960
12961         /* Disable NIG DRAIN */
12962         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
12963
12964         /* Enable interrupts */
12965         bnx2x_link_int_enable(params);
12966         return 0;
12967 }
12968
12969 static void bnx2x_cannot_avoid_link_flap(struct link_params *params,
12970                                          struct link_vars *vars,
12971                                          int lfa_status)
12972 {
12973         u32 lfa_sts, cfg_idx, tmp_val;
12974         struct bnx2x *bp = params->bp;
12975
12976         bnx2x_link_reset(params, vars, 1);
12977
12978         if (!params->lfa_base)
12979                 return;
12980         /* Store the new link parameters */
12981         REG_WR(bp, params->lfa_base +
12982                offsetof(struct shmem_lfa, req_duplex),
12983                params->req_duplex[0] | (params->req_duplex[1] << 16));
12984
12985         REG_WR(bp, params->lfa_base +
12986                offsetof(struct shmem_lfa, req_flow_ctrl),
12987                params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16));
12988
12989         REG_WR(bp, params->lfa_base +
12990                offsetof(struct shmem_lfa, req_line_speed),
12991                params->req_line_speed[0] | (params->req_line_speed[1] << 16));
12992
12993         for (cfg_idx = 0; cfg_idx < SHMEM_LINK_CONFIG_SIZE; cfg_idx++) {
12994                 REG_WR(bp, params->lfa_base +
12995                        offsetof(struct shmem_lfa,
12996                                 speed_cap_mask[cfg_idx]),
12997                        params->speed_cap_mask[cfg_idx]);
12998         }
12999
13000         tmp_val = REG_RD(bp, params->lfa_base +
13001                          offsetof(struct shmem_lfa, additional_config));
13002         tmp_val &= ~REQ_FC_AUTO_ADV_MASK;
13003         tmp_val |= params->req_fc_auto_adv;
13004
13005         REG_WR(bp, params->lfa_base +
13006                offsetof(struct shmem_lfa, additional_config), tmp_val);
13007
13008         lfa_sts = REG_RD(bp, params->lfa_base +
13009                          offsetof(struct shmem_lfa, lfa_sts));
13010
13011         /* Clear the "Don't Clear Statistics" bit, and set reason */
13012         lfa_sts &= ~SHMEM_LFA_DONT_CLEAR_STAT;
13013
13014         /* Set link flap reason */
13015         lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK;
13016         lfa_sts |= ((lfa_status & LFA_LINK_FLAP_REASON_MASK) <<
13017                     LFA_LINK_FLAP_REASON_OFFSET);
13018
13019         /* Increment link flap counter */
13020         lfa_sts = ((lfa_sts & ~LINK_FLAP_COUNT_MASK) |
13021                    (((((lfa_sts & LINK_FLAP_COUNT_MASK) >>
13022                        LINK_FLAP_COUNT_OFFSET) + 1) & 0xff)
13023                     << LINK_FLAP_COUNT_OFFSET));
13024         REG_WR(bp, params->lfa_base +
13025                offsetof(struct shmem_lfa, lfa_sts), lfa_sts);
13026         /* Proceed with regular link initialization */
13027 }
13028
13029 int bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
13030 {
13031         int lfa_status;
13032         struct bnx2x *bp = params->bp;
13033         DP(NETIF_MSG_LINK, "Phy Initialization started\n");
13034         DP(NETIF_MSG_LINK, "(1) req_speed %d, req_flowctrl %d\n",
13035                    params->req_line_speed[0], params->req_flow_ctrl[0]);
13036         DP(NETIF_MSG_LINK, "(2) req_speed %d, req_flowctrl %d\n",
13037                    params->req_line_speed[1], params->req_flow_ctrl[1]);
13038         DP(NETIF_MSG_LINK, "req_adv_flow_ctrl 0x%x\n", params->req_fc_auto_adv);
13039         vars->link_status = 0;
13040         vars->phy_link_up = 0;
13041         vars->link_up = 0;
13042         vars->line_speed = 0;
13043         vars->duplex = DUPLEX_FULL;
13044         vars->flow_ctrl = BNX2X_FLOW_CTRL_NONE;
13045         vars->mac_type = MAC_TYPE_NONE;
13046         vars->phy_flags = 0;
13047         vars->check_kr2_recovery_cnt = 0;
13048         params->link_flags = PHY_INITIALIZED;
13049         /* Driver opens NIG-BRB filters */
13050         bnx2x_set_rx_filter(params, 1);
13051         bnx2x_chng_link_count(params, true);
13052         /* Check if link flap can be avoided */
13053         lfa_status = bnx2x_check_lfa(params);
13054
13055         if (lfa_status == 0) {
13056                 DP(NETIF_MSG_LINK, "Link Flap Avoidance in progress\n");
13057                 return bnx2x_avoid_link_flap(params, vars);
13058         }
13059
13060         DP(NETIF_MSG_LINK, "Cannot avoid link flap lfa_sta=0x%x\n",
13061                        lfa_status);
13062         bnx2x_cannot_avoid_link_flap(params, vars, lfa_status);
13063
13064         /* Disable attentions */
13065         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
13066                        (NIG_MASK_XGXS0_LINK_STATUS |
13067                         NIG_MASK_XGXS0_LINK10G |
13068                         NIG_MASK_SERDES0_LINK_STATUS |
13069                         NIG_MASK_MI_INT));
13070
13071         bnx2x_emac_init(params, vars);
13072
13073         if (params->feature_config_flags & FEATURE_CONFIG_PFC_ENABLED)
13074                 vars->link_status |= LINK_STATUS_PFC_ENABLED;
13075
13076         if (params->num_phys == 0) {
13077                 DP(NETIF_MSG_LINK, "No phy found for initialization !!\n");
13078                 return -EINVAL;
13079         }
13080         set_phy_vars(params, vars);
13081
13082         DP(NETIF_MSG_LINK, "Num of phys on board: %d\n", params->num_phys);
13083         switch (params->loopback_mode) {
13084         case LOOPBACK_BMAC:
13085                 bnx2x_init_bmac_loopback(params, vars);
13086                 break;
13087         case LOOPBACK_EMAC:
13088                 bnx2x_init_emac_loopback(params, vars);
13089                 break;
13090         case LOOPBACK_XMAC:
13091                 bnx2x_init_xmac_loopback(params, vars);
13092                 break;
13093         case LOOPBACK_UMAC:
13094                 bnx2x_init_umac_loopback(params, vars);
13095                 break;
13096         case LOOPBACK_XGXS:
13097         case LOOPBACK_EXT_PHY:
13098                 bnx2x_init_xgxs_loopback(params, vars);
13099                 break;
13100         default:
13101                 if (!CHIP_IS_E3(bp)) {
13102                         if (params->switch_cfg == SWITCH_CFG_10G)
13103                                 bnx2x_xgxs_deassert(params);
13104                         else
13105                                 bnx2x_serdes_deassert(bp, params->port);
13106                 }
13107                 bnx2x_link_initialize(params, vars);
13108                 msleep(30);
13109                 bnx2x_link_int_enable(params);
13110                 break;
13111         }
13112         bnx2x_update_mng(params, vars->link_status);
13113
13114         bnx2x_update_mng_eee(params, vars->eee_status);
13115         return 0;
13116 }
13117
13118 int bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
13119                      u8 reset_ext_phy)
13120 {
13121         struct bnx2x *bp = params->bp;
13122         u8 phy_index, port = params->port, clear_latch_ind = 0;
13123         DP(NETIF_MSG_LINK, "Resetting the link of port %d\n", port);
13124         /* Disable attentions */
13125         vars->link_status = 0;
13126         bnx2x_chng_link_count(params, true);
13127         bnx2x_update_mng(params, vars->link_status);
13128         vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |
13129                               SHMEM_EEE_ACTIVE_BIT);
13130         bnx2x_update_mng_eee(params, vars->eee_status);
13131         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
13132                        (NIG_MASK_XGXS0_LINK_STATUS |
13133                         NIG_MASK_XGXS0_LINK10G |
13134                         NIG_MASK_SERDES0_LINK_STATUS |
13135                         NIG_MASK_MI_INT));
13136
13137         /* Activate nig drain */
13138         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
13139
13140         /* Disable nig egress interface */
13141         if (!CHIP_IS_E3(bp)) {
13142                 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
13143                 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
13144         }
13145
13146                 if (!CHIP_IS_E3(bp)) {
13147                         bnx2x_set_bmac_rx(bp, params->chip_id, port, 0);
13148                 } else {
13149                         bnx2x_set_xmac_rxtx(params, 0);
13150                         bnx2x_set_umac_rxtx(params, 0);
13151                 }
13152         /* Disable emac */
13153         if (!CHIP_IS_E3(bp))
13154                 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
13155
13156         usleep_range(10000, 20000);
13157         /* The PHY reset is controlled by GPIO 1
13158          * Hold it as vars low
13159          */
13160          /* Clear link led */
13161         bnx2x_set_mdio_emac_per_phy(bp, params);
13162         bnx2x_set_led(params, vars, LED_MODE_OFF, 0);
13163
13164         if (reset_ext_phy) {
13165                 for (phy_index = EXT_PHY1; phy_index < params->num_phys;
13166                       phy_index++) {
13167                         if (params->phy[phy_index].link_reset) {
13168                                 bnx2x_set_aer_mmd(params,
13169                                                   &params->phy[phy_index]);
13170                                 params->phy[phy_index].link_reset(
13171                                         &params->phy[phy_index],
13172                                         params);
13173                         }
13174                         if (params->phy[phy_index].flags &
13175                             FLAGS_REARM_LATCH_SIGNAL)
13176                                 clear_latch_ind = 1;
13177                 }
13178         }
13179
13180         if (clear_latch_ind) {
13181                 /* Clear latching indication */
13182                 bnx2x_rearm_latch_signal(bp, port, 0);
13183                 bnx2x_bits_dis(bp, NIG_REG_LATCH_BC_0 + port*4,
13184                                1 << NIG_LATCH_BC_ENABLE_MI_INT);
13185         }
13186         if (params->phy[INT_PHY].link_reset)
13187                 params->phy[INT_PHY].link_reset(
13188                         &params->phy[INT_PHY], params);
13189
13190         /* Disable nig ingress interface */
13191         if (!CHIP_IS_E3(bp)) {
13192                 /* Reset BigMac */
13193                 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
13194                        (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
13195                 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0);
13196                 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0);
13197         } else {
13198                 u32 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
13199                 bnx2x_set_xumac_nig(params, 0, 0);
13200                 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
13201                     MISC_REGISTERS_RESET_REG_2_XMAC)
13202                         REG_WR(bp, xmac_base + XMAC_REG_CTRL,
13203                                XMAC_CTRL_REG_SOFT_RESET);
13204         }
13205         vars->link_up = 0;
13206         vars->phy_flags = 0;
13207         return 0;
13208 }
13209 int bnx2x_lfa_reset(struct link_params *params,
13210                                struct link_vars *vars)
13211 {
13212         struct bnx2x *bp = params->bp;
13213         vars->link_up = 0;
13214         vars->phy_flags = 0;
13215         params->link_flags &= ~PHY_INITIALIZED;
13216         if (!params->lfa_base)
13217                 return bnx2x_link_reset(params, vars, 1);
13218         /*
13219          * Activate NIG drain so that during this time the device won't send
13220          * anything while it is unable to response.
13221          */
13222         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1);
13223
13224         /*
13225          * Close gracefully the gate from BMAC to NIG such that no half packets
13226          * are passed.
13227          */
13228         if (!CHIP_IS_E3(bp))
13229                 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0);
13230
13231         if (CHIP_IS_E3(bp)) {
13232                 bnx2x_set_xmac_rxtx(params, 0);
13233                 bnx2x_set_umac_rxtx(params, 0);
13234         }
13235         /* Wait 10ms for the pipe to clean up*/
13236         usleep_range(10000, 20000);
13237
13238         /* Clean the NIG-BRB using the network filters in a way that will
13239          * not cut a packet in the middle.
13240          */
13241         bnx2x_set_rx_filter(params, 0);
13242
13243         /*
13244          * Re-open the gate between the BMAC and the NIG, after verifying the
13245          * gate to the BRB is closed, otherwise packets may arrive to the
13246          * firmware before driver had initialized it. The target is to achieve
13247          * minimum management protocol down time.
13248          */
13249         if (!CHIP_IS_E3(bp))
13250                 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 1);
13251
13252         if (CHIP_IS_E3(bp)) {
13253                 bnx2x_set_xmac_rxtx(params, 1);
13254                 bnx2x_set_umac_rxtx(params, 1);
13255         }
13256         /* Disable NIG drain */
13257         REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13258         return 0;
13259 }
13260
13261 /****************************************************************************/
13262 /*                              Common function                             */
13263 /****************************************************************************/
13264 static int bnx2x_8073_common_init_phy(struct bnx2x *bp,
13265                                       u32 shmem_base_path[],
13266                                       u32 shmem2_base_path[], u8 phy_index,
13267                                       u32 chip_id)
13268 {
13269         struct bnx2x_phy phy[PORT_MAX];
13270         struct bnx2x_phy *phy_blk[PORT_MAX];
13271         u16 val;
13272         s8 port = 0;
13273         s8 port_of_path = 0;
13274         u32 swap_val, swap_override;
13275         swap_val = REG_RD(bp,  NIG_REG_PORT_SWAP);
13276         swap_override = REG_RD(bp,  NIG_REG_STRAP_OVERRIDE);
13277         port ^= (swap_val && swap_override);
13278         bnx2x_ext_phy_hw_reset(bp, port);
13279         /* PART1 - Reset both phys */
13280         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
13281                 u32 shmem_base, shmem2_base;
13282                 /* In E2, same phy is using for port0 of the two paths */
13283                 if (CHIP_IS_E1x(bp)) {
13284                         shmem_base = shmem_base_path[0];
13285                         shmem2_base = shmem2_base_path[0];
13286                         port_of_path = port;
13287                 } else {
13288                         shmem_base = shmem_base_path[port];
13289                         shmem2_base = shmem2_base_path[port];
13290                         port_of_path = 0;
13291                 }
13292
13293                 /* Extract the ext phy address for the port */
13294                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
13295                                        port_of_path, &phy[port]) !=
13296                     0) {
13297                         DP(NETIF_MSG_LINK, "populate_phy failed\n");
13298                         return -EINVAL;
13299                 }
13300                 /* Disable attentions */
13301                 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
13302                                port_of_path*4,
13303                                (NIG_MASK_XGXS0_LINK_STATUS |
13304                                 NIG_MASK_XGXS0_LINK10G |
13305                                 NIG_MASK_SERDES0_LINK_STATUS |
13306                                 NIG_MASK_MI_INT));
13307
13308                 /* Need to take the phy out of low power mode in order
13309                  * to write to access its registers
13310                  */
13311                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
13312                                MISC_REGISTERS_GPIO_OUTPUT_HIGH,
13313                                port);
13314
13315                 /* Reset the phy */
13316                 bnx2x_cl45_write(bp, &phy[port],
13317                                  MDIO_PMA_DEVAD,
13318                                  MDIO_PMA_REG_CTRL,
13319                                  1<<15);
13320         }
13321
13322         /* Add delay of 150ms after reset */
13323         msleep(150);
13324
13325         if (phy[PORT_0].addr & 0x1) {
13326                 phy_blk[PORT_0] = &(phy[PORT_1]);
13327                 phy_blk[PORT_1] = &(phy[PORT_0]);
13328         } else {
13329                 phy_blk[PORT_0] = &(phy[PORT_0]);
13330                 phy_blk[PORT_1] = &(phy[PORT_1]);
13331         }
13332
13333         /* PART2 - Download firmware to both phys */
13334         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
13335                 if (CHIP_IS_E1x(bp))
13336                         port_of_path = port;
13337                 else
13338                         port_of_path = 0;
13339
13340                 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
13341                            phy_blk[port]->addr);
13342                 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
13343                                                       port_of_path))
13344                         return -EINVAL;
13345
13346                 /* Only set bit 10 = 1 (Tx power down) */
13347                 bnx2x_cl45_read(bp, phy_blk[port],
13348                                 MDIO_PMA_DEVAD,
13349                                 MDIO_PMA_REG_TX_POWER_DOWN, &val);
13350
13351                 /* Phase1 of TX_POWER_DOWN reset */
13352                 bnx2x_cl45_write(bp, phy_blk[port],
13353                                  MDIO_PMA_DEVAD,
13354                                  MDIO_PMA_REG_TX_POWER_DOWN,
13355                                  (val | 1<<10));
13356         }
13357
13358         /* Toggle Transmitter: Power down and then up with 600ms delay
13359          * between
13360          */
13361         msleep(600);
13362
13363         /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
13364         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
13365                 /* Phase2 of POWER_DOWN_RESET */
13366                 /* Release bit 10 (Release Tx power down) */
13367                 bnx2x_cl45_read(bp, phy_blk[port],
13368                                 MDIO_PMA_DEVAD,
13369                                 MDIO_PMA_REG_TX_POWER_DOWN, &val);
13370
13371                 bnx2x_cl45_write(bp, phy_blk[port],
13372                                 MDIO_PMA_DEVAD,
13373                                 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
13374                 usleep_range(15000, 30000);
13375
13376                 /* Read modify write the SPI-ROM version select register */
13377                 bnx2x_cl45_read(bp, phy_blk[port],
13378                                 MDIO_PMA_DEVAD,
13379                                 MDIO_PMA_REG_EDC_FFE_MAIN, &val);
13380                 bnx2x_cl45_write(bp, phy_blk[port],
13381                                  MDIO_PMA_DEVAD,
13382                                  MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12)));
13383
13384                 /* set GPIO2 back to LOW */
13385                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
13386                                MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
13387         }
13388         return 0;
13389 }
13390 static int bnx2x_8726_common_init_phy(struct bnx2x *bp,
13391                                       u32 shmem_base_path[],
13392                                       u32 shmem2_base_path[], u8 phy_index,
13393                                       u32 chip_id)
13394 {
13395         u32 val;
13396         s8 port;
13397         struct bnx2x_phy phy;
13398         /* Use port1 because of the static port-swap */
13399         /* Enable the module detection interrupt */
13400         val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
13401         val |= ((1<<MISC_REGISTERS_GPIO_3)|
13402                 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
13403         REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
13404
13405         bnx2x_ext_phy_hw_reset(bp, 0);
13406         usleep_range(5000, 10000);
13407         for (port = 0; port < PORT_MAX; port++) {
13408                 u32 shmem_base, shmem2_base;
13409
13410                 /* In E2, same phy is using for port0 of the two paths */
13411                 if (CHIP_IS_E1x(bp)) {
13412                         shmem_base = shmem_base_path[0];
13413                         shmem2_base = shmem2_base_path[0];
13414                 } else {
13415                         shmem_base = shmem_base_path[port];
13416                         shmem2_base = shmem2_base_path[port];
13417                 }
13418                 /* Extract the ext phy address for the port */
13419                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
13420                                        port, &phy) !=
13421                     0) {
13422                         DP(NETIF_MSG_LINK, "populate phy failed\n");
13423                         return -EINVAL;
13424                 }
13425
13426                 /* Reset phy*/
13427                 bnx2x_cl45_write(bp, &phy,
13428                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
13429
13430
13431                 /* Set fault module detected LED on */
13432                 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
13433                                MISC_REGISTERS_GPIO_HIGH,
13434                                port);
13435         }
13436
13437         return 0;
13438 }
13439 static void bnx2x_get_ext_phy_reset_gpio(struct bnx2x *bp, u32 shmem_base,
13440                                          u8 *io_gpio, u8 *io_port)
13441 {
13442
13443         u32 phy_gpio_reset = REG_RD(bp, shmem_base +
13444                                           offsetof(struct shmem_region,
13445                                 dev_info.port_hw_config[PORT_0].default_cfg));
13446         switch (phy_gpio_reset) {
13447         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0:
13448                 *io_gpio = 0;
13449                 *io_port = 0;
13450                 break;
13451         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0:
13452                 *io_gpio = 1;
13453                 *io_port = 0;
13454                 break;
13455         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0:
13456                 *io_gpio = 2;
13457                 *io_port = 0;
13458                 break;
13459         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0:
13460                 *io_gpio = 3;
13461                 *io_port = 0;
13462                 break;
13463         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1:
13464                 *io_gpio = 0;
13465                 *io_port = 1;
13466                 break;
13467         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1:
13468                 *io_gpio = 1;
13469                 *io_port = 1;
13470                 break;
13471         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1:
13472                 *io_gpio = 2;
13473                 *io_port = 1;
13474                 break;
13475         case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1:
13476                 *io_gpio = 3;
13477                 *io_port = 1;
13478                 break;
13479         default:
13480                 /* Don't override the io_gpio and io_port */
13481                 break;
13482         }
13483 }
13484
13485 static int bnx2x_8727_common_init_phy(struct bnx2x *bp,
13486                                       u32 shmem_base_path[],
13487                                       u32 shmem2_base_path[], u8 phy_index,
13488                                       u32 chip_id)
13489 {
13490         s8 port, reset_gpio;
13491         u32 swap_val, swap_override;
13492         struct bnx2x_phy phy[PORT_MAX];
13493         struct bnx2x_phy *phy_blk[PORT_MAX];
13494         s8 port_of_path;
13495         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
13496         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
13497
13498         reset_gpio = MISC_REGISTERS_GPIO_1;
13499         port = 1;
13500
13501         /* Retrieve the reset gpio/port which control the reset.
13502          * Default is GPIO1, PORT1
13503          */
13504         bnx2x_get_ext_phy_reset_gpio(bp, shmem_base_path[0],
13505                                      (u8 *)&reset_gpio, (u8 *)&port);
13506
13507         /* Calculate the port based on port swap */
13508         port ^= (swap_val && swap_override);
13509
13510         /* Initiate PHY reset*/
13511         bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW,
13512                        port);
13513         usleep_range(1000, 2000);
13514         bnx2x_set_gpio(bp, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH,
13515                        port);
13516
13517         usleep_range(5000, 10000);
13518
13519         /* PART1 - Reset both phys */
13520         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
13521                 u32 shmem_base, shmem2_base;
13522
13523                 /* In E2, same phy is using for port0 of the two paths */
13524                 if (CHIP_IS_E1x(bp)) {
13525                         shmem_base = shmem_base_path[0];
13526                         shmem2_base = shmem2_base_path[0];
13527                         port_of_path = port;
13528                 } else {
13529                         shmem_base = shmem_base_path[port];
13530                         shmem2_base = shmem2_base_path[port];
13531                         port_of_path = 0;
13532                 }
13533
13534                 /* Extract the ext phy address for the port */
13535                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
13536                                        port_of_path, &phy[port]) !=
13537                                        0) {
13538                         DP(NETIF_MSG_LINK, "populate phy failed\n");
13539                         return -EINVAL;
13540                 }
13541                 /* disable attentions */
13542                 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
13543                                port_of_path*4,
13544                                (NIG_MASK_XGXS0_LINK_STATUS |
13545                                 NIG_MASK_XGXS0_LINK10G |
13546                                 NIG_MASK_SERDES0_LINK_STATUS |
13547                                 NIG_MASK_MI_INT));
13548
13549
13550                 /* Reset the phy */
13551                 bnx2x_cl45_write(bp, &phy[port],
13552                                  MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
13553         }
13554
13555         /* Add delay of 150ms after reset */
13556         msleep(150);
13557         if (phy[PORT_0].addr & 0x1) {
13558                 phy_blk[PORT_0] = &(phy[PORT_1]);
13559                 phy_blk[PORT_1] = &(phy[PORT_0]);
13560         } else {
13561                 phy_blk[PORT_0] = &(phy[PORT_0]);
13562                 phy_blk[PORT_1] = &(phy[PORT_1]);
13563         }
13564         /* PART2 - Download firmware to both phys */
13565         for (port = PORT_MAX - 1; port >= PORT_0; port--) {
13566                 if (CHIP_IS_E1x(bp))
13567                         port_of_path = port;
13568                 else
13569                         port_of_path = 0;
13570                 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n",
13571                            phy_blk[port]->addr);
13572                 if (bnx2x_8073_8727_external_rom_boot(bp, phy_blk[port],
13573                                                       port_of_path))
13574                         return -EINVAL;
13575                 /* Disable PHY transmitter output */
13576                 bnx2x_cl45_write(bp, phy_blk[port],
13577                                  MDIO_PMA_DEVAD,
13578                                  MDIO_PMA_REG_TX_DISABLE, 1);
13579
13580         }
13581         return 0;
13582 }
13583
13584 static int bnx2x_84833_common_init_phy(struct bnx2x *bp,
13585                                                 u32 shmem_base_path[],
13586                                                 u32 shmem2_base_path[],
13587                                                 u8 phy_index,
13588                                                 u32 chip_id)
13589 {
13590         u8 reset_gpios;
13591         reset_gpios = bnx2x_84833_get_reset_gpios(bp, shmem_base_path, chip_id);
13592         bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
13593         udelay(10);
13594         bnx2x_set_mult_gpio(bp, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_HIGH);
13595         DP(NETIF_MSG_LINK, "84833 reset pulse on pin values 0x%x\n",
13596                 reset_gpios);
13597         return 0;
13598 }
13599
13600 static int bnx2x_ext_phy_common_init(struct bnx2x *bp, u32 shmem_base_path[],
13601                                      u32 shmem2_base_path[], u8 phy_index,
13602                                      u32 ext_phy_type, u32 chip_id)
13603 {
13604         int rc = 0;
13605
13606         switch (ext_phy_type) {
13607         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
13608                 rc = bnx2x_8073_common_init_phy(bp, shmem_base_path,
13609                                                 shmem2_base_path,
13610                                                 phy_index, chip_id);
13611                 break;
13612         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
13613         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
13614         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
13615                 rc = bnx2x_8727_common_init_phy(bp, shmem_base_path,
13616                                                 shmem2_base_path,
13617                                                 phy_index, chip_id);
13618                 break;
13619
13620         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
13621                 /* GPIO1 affects both ports, so there's need to pull
13622                  * it for single port alone
13623                  */
13624                 rc = bnx2x_8726_common_init_phy(bp, shmem_base_path,
13625                                                 shmem2_base_path,
13626                                                 phy_index, chip_id);
13627                 break;
13628         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
13629         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834:
13630         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858:
13631                 /* GPIO3's are linked, and so both need to be toggled
13632                  * to obtain required 2us pulse.
13633                  */
13634                 rc = bnx2x_84833_common_init_phy(bp, shmem_base_path,
13635                                                 shmem2_base_path,
13636                                                 phy_index, chip_id);
13637                 break;
13638         case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
13639                 rc = -EINVAL;
13640                 break;
13641         default:
13642                 DP(NETIF_MSG_LINK,
13643                            "ext_phy 0x%x common init not required\n",
13644                            ext_phy_type);
13645                 break;
13646         }
13647
13648         if (rc)
13649                 netdev_err(bp->dev,  "Warning: PHY was not initialized,"
13650                                       " Port %d\n",
13651                          0);
13652         return rc;
13653 }
13654
13655 int bnx2x_common_init_phy(struct bnx2x *bp, u32 shmem_base_path[],
13656                           u32 shmem2_base_path[], u32 chip_id)
13657 {
13658         int rc = 0;
13659         u32 phy_ver, val;
13660         u8 phy_index = 0;
13661         u32 ext_phy_type, ext_phy_config;
13662
13663         bnx2x_set_mdio_clk(bp, chip_id, GRCBASE_EMAC0);
13664         bnx2x_set_mdio_clk(bp, chip_id, GRCBASE_EMAC1);
13665         DP(NETIF_MSG_LINK, "Begin common phy init\n");
13666         if (CHIP_IS_E3(bp)) {
13667                 /* Enable EPIO */
13668                 val = REG_RD(bp, MISC_REG_GEN_PURP_HWG);
13669                 REG_WR(bp, MISC_REG_GEN_PURP_HWG, val | 1);
13670         }
13671         /* Check if common init was already done */
13672         phy_ver = REG_RD(bp, shmem_base_path[0] +
13673                          offsetof(struct shmem_region,
13674                                   port_mb[PORT_0].ext_phy_fw_version));
13675         if (phy_ver) {
13676                 DP(NETIF_MSG_LINK, "Not doing common init; phy ver is 0x%x\n",
13677                                phy_ver);
13678                 return 0;
13679         }
13680
13681         /* Read the ext_phy_type for arbitrary port(0) */
13682         for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
13683               phy_index++) {
13684                 ext_phy_config = bnx2x_get_ext_phy_config(bp,
13685                                                           shmem_base_path[0],
13686                                                           phy_index, 0);
13687                 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
13688                 rc |= bnx2x_ext_phy_common_init(bp, shmem_base_path,
13689                                                 shmem2_base_path,
13690                                                 phy_index, ext_phy_type,
13691                                                 chip_id);
13692         }
13693         return rc;
13694 }
13695
13696 static void bnx2x_check_over_curr(struct link_params *params,
13697                                   struct link_vars *vars)
13698 {
13699         struct bnx2x *bp = params->bp;
13700         u32 cfg_pin;
13701         u8 port = params->port;
13702         u32 pin_val;
13703
13704         cfg_pin = (REG_RD(bp, params->shmem_base +
13705                           offsetof(struct shmem_region,
13706                                dev_info.port_hw_config[port].e3_cmn_pin_cfg1)) &
13707                    PORT_HW_CFG_E3_OVER_CURRENT_MASK) >>
13708                 PORT_HW_CFG_E3_OVER_CURRENT_SHIFT;
13709
13710         /* Ignore check if no external input PIN available */
13711         if (bnx2x_get_cfg_pin(bp, cfg_pin, &pin_val) != 0)
13712                 return;
13713
13714         if (!pin_val) {
13715                 if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) {
13716                         netdev_err(bp->dev, "Error:  Power fault on Port %d has"
13717                                             " been detected and the power to "
13718                                             "that SFP+ module has been removed"
13719                                             " to prevent failure of the card."
13720                                             " Please remove the SFP+ module and"
13721                                             " restart the system to clear this"
13722                                             " error.\n",
13723                          params->port);
13724                         vars->phy_flags |= PHY_OVER_CURRENT_FLAG;
13725                         bnx2x_warpcore_power_module(params, 0);
13726                 }
13727         } else
13728                 vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG;
13729 }
13730
13731 /* Returns 0 if no change occurred since last check; 1 otherwise. */
13732 static u8 bnx2x_analyze_link_error(struct link_params *params,
13733                                     struct link_vars *vars, u32 status,
13734                                     u32 phy_flag, u32 link_flag, u8 notify)
13735 {
13736         struct bnx2x *bp = params->bp;
13737         /* Compare new value with previous value */
13738         u8 led_mode;
13739         u32 old_status = (vars->phy_flags & phy_flag) ? 1 : 0;
13740
13741         if ((status ^ old_status) == 0)
13742                 return 0;
13743
13744         /* If values differ */
13745         switch (phy_flag) {
13746         case PHY_HALF_OPEN_CONN_FLAG:
13747                 DP(NETIF_MSG_LINK, "Analyze Remote Fault\n");
13748                 break;
13749         case PHY_SFP_TX_FAULT_FLAG:
13750                 DP(NETIF_MSG_LINK, "Analyze TX Fault\n");
13751                 break;
13752         default:
13753                 DP(NETIF_MSG_LINK, "Analyze UNKNOWN\n");
13754         }
13755         DP(NETIF_MSG_LINK, "Link changed:[%x %x]->%x\n", vars->link_up,
13756            old_status, status);
13757
13758         /* Do not touch the link in case physical link down */
13759         if ((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0)
13760                 return 1;
13761
13762         /* a. Update shmem->link_status accordingly
13763          * b. Update link_vars->link_up
13764          */
13765         if (status) {
13766                 vars->link_status &= ~LINK_STATUS_LINK_UP;
13767                 vars->link_status |= link_flag;
13768                 vars->link_up = 0;
13769                 vars->phy_flags |= phy_flag;
13770
13771                 /* activate nig drain */
13772                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1);
13773                 /* Set LED mode to off since the PHY doesn't know about these
13774                  * errors
13775                  */
13776                 led_mode = LED_MODE_OFF;
13777         } else {
13778                 vars->link_status |= LINK_STATUS_LINK_UP;
13779                 vars->link_status &= ~link_flag;
13780                 vars->link_up = 1;
13781                 vars->phy_flags &= ~phy_flag;
13782                 led_mode = LED_MODE_OPER;
13783
13784                 /* Clear nig drain */
13785                 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13786         }
13787         bnx2x_sync_link(params, vars);
13788         /* Update the LED according to the link state */
13789         bnx2x_set_led(params, vars, led_mode, SPEED_10000);
13790
13791         /* Update link status in the shared memory */
13792         bnx2x_update_mng(params, vars->link_status);
13793
13794         /* C. Trigger General Attention */
13795         vars->periodic_flags |= PERIODIC_FLAGS_LINK_EVENT;
13796         if (notify)
13797                 bnx2x_notify_link_changed(bp);
13798
13799         return 1;
13800 }
13801
13802 /******************************************************************************
13803 * Description:
13804 *       This function checks for half opened connection change indication.
13805 *       When such change occurs, it calls the bnx2x_analyze_link_error
13806 *       to check if Remote Fault is set or cleared. Reception of remote fault
13807 *       status message in the MAC indicates that the peer's MAC has detected
13808 *       a fault, for example, due to break in the TX side of fiber.
13809 *
13810 ******************************************************************************/
13811 static int bnx2x_check_half_open_conn(struct link_params *params,
13812                                       struct link_vars *vars,
13813                                       u8 notify)
13814 {
13815         struct bnx2x *bp = params->bp;
13816         u32 lss_status = 0;
13817         u32 mac_base;
13818         /* In case link status is physically up @ 10G do */
13819         if (((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) ||
13820             (REG_RD(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4)))
13821                 return 0;
13822
13823         if (CHIP_IS_E3(bp) &&
13824             (REG_RD(bp, MISC_REG_RESET_REG_2) &
13825               (MISC_REGISTERS_RESET_REG_2_XMAC))) {
13826                 /* Check E3 XMAC */
13827                 /* Note that link speed cannot be queried here, since it may be
13828                  * zero while link is down. In case UMAC is active, LSS will
13829                  * simply not be set
13830                  */
13831                 mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
13832
13833                 /* Clear stick bits (Requires rising edge) */
13834                 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
13835                 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
13836                        XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
13837                        XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
13838                 if (REG_RD(bp, mac_base + XMAC_REG_RX_LSS_STATUS))
13839                         lss_status = 1;
13840
13841                 bnx2x_analyze_link_error(params, vars, lss_status,
13842                                          PHY_HALF_OPEN_CONN_FLAG,
13843                                          LINK_STATUS_NONE, notify);
13844         } else if (REG_RD(bp, MISC_REG_RESET_REG_2) &
13845                    (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) {
13846                 /* Check E1X / E2 BMAC */
13847                 u32 lss_status_reg;
13848                 u32 wb_data[2];
13849                 mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
13850                         NIG_REG_INGRESS_BMAC0_MEM;
13851                 /*  Read BIGMAC_REGISTER_RX_LSS_STATUS */
13852                 if (CHIP_IS_E2(bp))
13853                         lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT;
13854                 else
13855                         lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS;
13856
13857                 REG_RD_DMAE(bp, mac_base + lss_status_reg, wb_data, 2);
13858                 lss_status = (wb_data[0] > 0);
13859
13860                 bnx2x_analyze_link_error(params, vars, lss_status,
13861                                          PHY_HALF_OPEN_CONN_FLAG,
13862                                          LINK_STATUS_NONE, notify);
13863         }
13864         return 0;
13865 }
13866 static void bnx2x_sfp_tx_fault_detection(struct bnx2x_phy *phy,
13867                                          struct link_params *params,
13868                                          struct link_vars *vars)
13869 {
13870         struct bnx2x *bp = params->bp;
13871         u32 cfg_pin, value = 0;
13872         u8 led_change, port = params->port;
13873
13874         /* Get The SFP+ TX_Fault controlling pin ([eg]pio) */
13875         cfg_pin = (REG_RD(bp, params->shmem_base + offsetof(struct shmem_region,
13876                           dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
13877                    PORT_HW_CFG_E3_TX_FAULT_MASK) >>
13878                   PORT_HW_CFG_E3_TX_FAULT_SHIFT;
13879
13880         if (bnx2x_get_cfg_pin(bp, cfg_pin, &value)) {
13881                 DP(NETIF_MSG_LINK, "Failed to read pin 0x%02x\n", cfg_pin);
13882                 return;
13883         }
13884
13885         led_change = bnx2x_analyze_link_error(params, vars, value,
13886                                               PHY_SFP_TX_FAULT_FLAG,
13887                                               LINK_STATUS_SFP_TX_FAULT, 1);
13888
13889         if (led_change) {
13890                 /* Change TX_Fault led, set link status for further syncs */
13891                 u8 led_mode;
13892
13893                 if (vars->phy_flags & PHY_SFP_TX_FAULT_FLAG) {
13894                         led_mode = MISC_REGISTERS_GPIO_HIGH;
13895                         vars->link_status |= LINK_STATUS_SFP_TX_FAULT;
13896                 } else {
13897                         led_mode = MISC_REGISTERS_GPIO_LOW;
13898                         vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT;
13899                 }
13900
13901                 /* If module is unapproved, led should be on regardless */
13902                 if (!(phy->flags & FLAGS_SFP_NOT_APPROVED)) {
13903                         DP(NETIF_MSG_LINK, "Change TX_Fault LED: ->%x\n",
13904                            led_mode);
13905                         bnx2x_set_e3_module_fault_led(params, led_mode);
13906                 }
13907         }
13908 }
13909 static void bnx2x_kr2_recovery(struct link_params *params,
13910                                struct link_vars *vars,
13911                                struct bnx2x_phy *phy)
13912 {
13913         struct bnx2x *bp = params->bp;
13914         DP(NETIF_MSG_LINK, "KR2 recovery\n");
13915         bnx2x_warpcore_enable_AN_KR2(phy, params, vars);
13916         bnx2x_warpcore_restart_AN_KR(phy, params);
13917 }
13918
13919 static void bnx2x_check_kr2_wa(struct link_params *params,
13920                                struct link_vars *vars,
13921                                struct bnx2x_phy *phy)
13922 {
13923         struct bnx2x *bp = params->bp;
13924         u16 base_page, next_page, not_kr2_device, lane;
13925         int sigdet;
13926
13927         /* Once KR2 was disabled, wait 5 seconds before checking KR2 recovery
13928          * Since some switches tend to reinit the AN process and clear the
13929          * the advertised BP/NP after ~2 seconds causing the KR2 to be disabled
13930          * and recovered many times
13931          */
13932         if (vars->check_kr2_recovery_cnt > 0) {
13933                 vars->check_kr2_recovery_cnt--;
13934                 return;
13935         }
13936
13937         sigdet = bnx2x_warpcore_get_sigdet(phy, params);
13938         if (!sigdet) {
13939                 if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
13940                         bnx2x_kr2_recovery(params, vars, phy);
13941                         DP(NETIF_MSG_LINK, "No sigdet\n");
13942                 }
13943                 return;
13944         }
13945
13946         lane = bnx2x_get_warpcore_lane(phy, params);
13947         CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK,
13948                           MDIO_AER_BLOCK_AER_REG, lane);
13949         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
13950                         MDIO_AN_REG_LP_AUTO_NEG, &base_page);
13951         bnx2x_cl45_read(bp, phy, MDIO_AN_DEVAD,
13952                         MDIO_AN_REG_LP_AUTO_NEG2, &next_page);
13953         bnx2x_set_aer_mmd(params, phy);
13954
13955         /* CL73 has not begun yet */
13956         if (base_page == 0) {
13957                 if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
13958                         bnx2x_kr2_recovery(params, vars, phy);
13959                         DP(NETIF_MSG_LINK, "No BP\n");
13960                 }
13961                 return;
13962         }
13963
13964         /* In case NP bit is not set in the BasePage, or it is set,
13965          * but only KX is advertised, declare this link partner as non-KR2
13966          * device.
13967          */
13968         not_kr2_device = (((base_page & 0x8000) == 0) ||
13969                           (((base_page & 0x8000) &&
13970                             ((next_page & 0xe0) == 0x20))));
13971
13972         /* In case KR2 is already disabled, check if we need to re-enable it */
13973         if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
13974                 if (!not_kr2_device) {
13975                         DP(NETIF_MSG_LINK, "BP=0x%x, NP=0x%x\n", base_page,
13976                            next_page);
13977                         bnx2x_kr2_recovery(params, vars, phy);
13978                 }
13979                 return;
13980         }
13981         /* KR2 is enabled, but not KR2 device */
13982         if (not_kr2_device) {
13983                 /* Disable KR2 on both lanes */
13984                 DP(NETIF_MSG_LINK, "BP=0x%x, NP=0x%x\n", base_page, next_page);
13985                 bnx2x_disable_kr2(params, vars, phy);
13986                 /* Restart AN on leading lane */
13987                 bnx2x_warpcore_restart_AN_KR(phy, params);
13988                 return;
13989         }
13990 }
13991
13992 void bnx2x_period_func(struct link_params *params, struct link_vars *vars)
13993 {
13994         u16 phy_idx;
13995         struct bnx2x *bp = params->bp;
13996         for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
13997                 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) {
13998                         bnx2x_set_aer_mmd(params, &params->phy[phy_idx]);
13999                         if (bnx2x_check_half_open_conn(params, vars, 1) !=
14000                             0)
14001                                 DP(NETIF_MSG_LINK, "Fault detection failed\n");
14002                         break;
14003                 }
14004         }
14005
14006         if (CHIP_IS_E3(bp)) {
14007                 struct bnx2x_phy *phy = &params->phy[INT_PHY];
14008                 bnx2x_set_aer_mmd(params, phy);
14009                 if (((phy->req_line_speed == SPEED_AUTO_NEG) &&
14010                      (phy->speed_cap_mask &
14011                       PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) ||
14012                     (phy->req_line_speed == SPEED_20000))
14013                         bnx2x_check_kr2_wa(params, vars, phy);
14014                 bnx2x_check_over_curr(params, vars);
14015                 if (vars->rx_tx_asic_rst)
14016                         bnx2x_warpcore_config_runtime(phy, params, vars);
14017
14018                 if ((REG_RD(bp, params->shmem_base +
14019                             offsetof(struct shmem_region, dev_info.
14020                                 port_hw_config[params->port].default_cfg))
14021                     & PORT_HW_CFG_NET_SERDES_IF_MASK) ==
14022                     PORT_HW_CFG_NET_SERDES_IF_SFI) {
14023                         if (bnx2x_is_sfp_module_plugged(phy, params)) {
14024                                 bnx2x_sfp_tx_fault_detection(phy, params, vars);
14025                         } else if (vars->link_status &
14026                                 LINK_STATUS_SFP_TX_FAULT) {
14027                                 /* Clean trail, interrupt corrects the leds */
14028                                 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT;
14029                                 vars->phy_flags &= ~PHY_SFP_TX_FAULT_FLAG;
14030                                 /* Update link status in the shared memory */
14031                                 bnx2x_update_mng(params, vars->link_status);
14032                         }
14033                 }
14034         }
14035 }
14036
14037 u8 bnx2x_fan_failure_det_req(struct bnx2x *bp,
14038                              u32 shmem_base,
14039                              u32 shmem2_base,
14040                              u8 port)
14041 {
14042         u8 phy_index, fan_failure_det_req = 0;
14043         struct bnx2x_phy phy;
14044         for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
14045               phy_index++) {
14046                 if (bnx2x_populate_phy(bp, phy_index, shmem_base, shmem2_base,
14047                                        port, &phy)
14048                     != 0) {
14049                         DP(NETIF_MSG_LINK, "populate phy failed\n");
14050                         return 0;
14051                 }
14052                 fan_failure_det_req |= (phy.flags &
14053                                         FLAGS_FAN_FAILURE_DET_REQ);
14054         }
14055         return fan_failure_det_req;
14056 }
14057
14058 void bnx2x_hw_reset_phy(struct link_params *params)
14059 {
14060         u8 phy_index;
14061         struct bnx2x *bp = params->bp;
14062         bnx2x_update_mng(params, 0);
14063         bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
14064                        (NIG_MASK_XGXS0_LINK_STATUS |
14065                         NIG_MASK_XGXS0_LINK10G |
14066                         NIG_MASK_SERDES0_LINK_STATUS |
14067                         NIG_MASK_MI_INT));
14068
14069         for (phy_index = INT_PHY; phy_index < MAX_PHYS;
14070               phy_index++) {
14071                 if (params->phy[phy_index].hw_reset) {
14072                         params->phy[phy_index].hw_reset(
14073                                 &params->phy[phy_index],
14074                                 params);
14075                         params->phy[phy_index] = phy_null;
14076                 }
14077         }
14078 }
14079
14080 void bnx2x_init_mod_abs_int(struct bnx2x *bp, struct link_vars *vars,
14081                             u32 chip_id, u32 shmem_base, u32 shmem2_base,
14082                             u8 port)
14083 {
14084         u8 gpio_num = 0xff, gpio_port = 0xff, phy_index;
14085         u32 val;
14086         u32 offset, aeu_mask, swap_val, swap_override, sync_offset;
14087         if (CHIP_IS_E3(bp)) {
14088                 if (bnx2x_get_mod_abs_int_cfg(bp, chip_id,
14089                                               shmem_base,
14090                                               port,
14091                                               &gpio_num,
14092                                               &gpio_port) != 0)
14093                         return;
14094         } else {
14095                 struct bnx2x_phy phy;
14096                 for (phy_index = EXT_PHY1; phy_index < MAX_PHYS;
14097                       phy_index++) {
14098                         if (bnx2x_populate_phy(bp, phy_index, shmem_base,
14099                                                shmem2_base, port, &phy)
14100                             != 0) {
14101                                 DP(NETIF_MSG_LINK, "populate phy failed\n");
14102                                 return;
14103                         }
14104                         if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) {
14105                                 gpio_num = MISC_REGISTERS_GPIO_3;
14106                                 gpio_port = port;
14107                                 break;
14108                         }
14109                 }
14110         }
14111
14112         if (gpio_num == 0xff)
14113                 return;
14114
14115         /* Set GPIO3 to trigger SFP+ module insertion/removal */
14116         bnx2x_set_gpio(bp, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, gpio_port);
14117
14118         swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
14119         swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
14120         gpio_port ^= (swap_val && swap_override);
14121
14122         vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 <<
14123                 (gpio_num + (gpio_port << 2));
14124
14125         sync_offset = shmem_base +
14126                 offsetof(struct shmem_region,
14127                          dev_info.port_hw_config[port].aeu_int_mask);
14128         REG_WR(bp, sync_offset, vars->aeu_int_mask);
14129
14130         DP(NETIF_MSG_LINK, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n",
14131                        gpio_num, gpio_port, vars->aeu_int_mask);
14132
14133         if (port == 0)
14134                 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
14135         else
14136                 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
14137
14138         /* Open appropriate AEU for interrupts */
14139         aeu_mask = REG_RD(bp, offset);
14140         aeu_mask |= vars->aeu_int_mask;
14141         REG_WR(bp, offset, aeu_mask);
14142
14143         /* Enable the GPIO to trigger interrupt */
14144         val = REG_RD(bp, MISC_REG_GPIO_EVENT_EN);
14145         val |= 1 << (gpio_num + (gpio_port << 2));
14146         REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val);
14147 }