drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c

   1 /* bnx2x_main.c: Broadcom Everest network driver.
   2  *
   3  * Copyright (c) 2007-2013 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  *
   9  * Maintained by: Eilon Greenstein <eilong@broadcom.com>
  10  * Written by: Eliezer Tamir
  11  * Based on code from Michael Chan's bnx2 driver
  12  * UDP CSUM errata workaround by Arik Gendelman
  13  * Slowpath and fastpath rework by Vladislav Zolotarov
  14  * Statistics and Link management by Yitchak Gertner
  15  *
  16  */
  17
  18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  19
  20 #include <linux/module.h>
  21 #include <linux/moduleparam.h>
  22 #include <linux/kernel.h>
  23 #include <linux/device.h>  /* for dev_info() */
  24 #include <linux/timer.h>
  25 #include <linux/errno.h>
  26 #include <linux/ioport.h>
  27 #include <linux/slab.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/pci.h>
  30 #include <linux/aer.h>
  31 #include <linux/init.h>
  32 #include <linux/netdevice.h>
  33 #include <linux/etherdevice.h>
  34 #include <linux/skbuff.h>
  35 #include <linux/dma-mapping.h>
  36 #include <linux/bitops.h>
  37 #include <linux/irq.h>
  38 #include <linux/delay.h>
  39 #include <asm/byteorder.h>
  40 #include <linux/time.h>
  41 #include <linux/ethtool.h>
  42 #include <linux/mii.h>
  43 #include <linux/if_vlan.h>
  44 #include <net/ip.h>
  45 #include <net/ipv6.h>
  46 #include <net/tcp.h>
  47 #include <net/checksum.h>
  48 #include <net/ip6_checksum.h>
  49 #include <linux/workqueue.h>
  50 #include <linux/crc32.h>
  51 #include <linux/crc32c.h>
  52 #include <linux/prefetch.h>
  53 #include <linux/zlib.h>
  54 #include <linux/io.h>
  55 #include <linux/semaphore.h>
  56 #include <linux/stringify.h>
  57 #include <linux/vmalloc.h>
  58
  59 #include "bnx2x.h"
  60 #include "bnx2x_init.h"
  61 #include "bnx2x_init_ops.h"
  62 #include "bnx2x_cmn.h"
  63 #include "bnx2x_vfpf.h"
  64 #include "bnx2x_dcb.h"
  65 #include "bnx2x_sp.h"
  66
  67 #include <linux/firmware.h>
  68 #include "bnx2x_fw_file_hdr.h"
  69 /* FW files */
  70 #define FW_FILE_VERSION                                 \
  71         __stringify(BCM_5710_FW_MAJOR_VERSION) "."      \
  72         __stringify(BCM_5710_FW_MINOR_VERSION) "."      \
  73         __stringify(BCM_5710_FW_REVISION_VERSION) "."   \
  74         __stringify(BCM_5710_FW_ENGINEERING_VERSION)
  75 #define FW_FILE_NAME_E1         "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
  76 #define FW_FILE_NAME_E1H        "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
  77 #define FW_FILE_NAME_E2         "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
  78
  79 /* Time in jiffies before concluding the transmitter is hung */
  80 #define TX_TIMEOUT              (5*HZ)
  81
  82 static char version[] =
  83         "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
  84         DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  85
  86 MODULE_AUTHOR("Eliezer Tamir");
  87 MODULE_DESCRIPTION("Broadcom NetXtreme II "
  88                    "BCM57710/57711/57711E/"
  89                    "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
  90                    "57840/57840_MF Driver");
  91 MODULE_LICENSE("GPL");
  92 MODULE_VERSION(DRV_MODULE_VERSION);
  93 MODULE_FIRMWARE(FW_FILE_NAME_E1);
  94 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
  95 MODULE_FIRMWARE(FW_FILE_NAME_E2);
  96
  97 int num_queues;
  98 module_param(num_queues, int, 0);
  99 MODULE_PARM_DESC(num_queues,
 100                  " Set number of queues (default is as a number of CPUs)");
 101
 102 static int disable_tpa;
 103 module_param(disable_tpa, int, 0);
 104 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
 105
 106 int int_mode;
 107 module_param(int_mode, int, 0);
 108 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
 109                                 "(1 INT#x; 2 MSI)");
 110
 111 static int dropless_fc;
 112 module_param(dropless_fc, int, 0);
 113 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
 114
 115 static int mrrs = -1;
 116 module_param(mrrs, int, 0);
 117 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
 118
 119 static int debug;
 120 module_param(debug, int, 0);
 121 MODULE_PARM_DESC(debug, " Default debug msglevel");
 122
 123 struct workqueue_struct *bnx2x_wq;
 124
 125 struct bnx2x_mac_vals {
 126         u32 xmac_addr;
 127         u32 xmac_val;
 128         u32 emac_addr;
 129         u32 emac_val;
 130         u32 umac_addr;
 131         u32 umac_val;
 132         u32 bmac_addr;
 133         u32 bmac_val[2];
 134 };
 135
 136 enum bnx2x_board_type {
 137         BCM57710 = 0,
 138         BCM57711,
 139         BCM57711E,
 140         BCM57712,
 141         BCM57712_MF,
 142         BCM57712_VF,
 143         BCM57800,
 144         BCM57800_MF,
 145         BCM57800_VF,
 146         BCM57810,
 147         BCM57810_MF,
 148         BCM57810_VF,
 149         BCM57840_4_10,
 150         BCM57840_2_20,
 151         BCM57840_MF,
 152         BCM57840_VF,
 153         BCM57811,
 154         BCM57811_MF,
 155         BCM57840_O,
 156         BCM57840_MFO,
 157         BCM57811_VF
 158 };
 159
 160 /* indexed by board_type, above */
 161 static struct {
 162         char *name;
 163 } board_info[] = {
 164         [BCM57710]      = { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
 165         [BCM57711]      = { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
 166         [BCM57711E]     = { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
 167         [BCM57712]      = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
 168         [BCM57712_MF]   = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
 169         [BCM57712_VF]   = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Virtual Function" },
 170         [BCM57800]      = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
 171         [BCM57800_MF]   = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
 172         [BCM57800_VF]   = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Virtual Function" },
 173         [BCM57810]      = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
 174         [BCM57810_MF]   = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
 175         [BCM57810_VF]   = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Virtual Function" },
 176         [BCM57840_4_10] = { "Broadcom NetXtreme II BCM57840 10 Gigabit Ethernet" },
 177         [BCM57840_2_20] = { "Broadcom NetXtreme II BCM57840 20 Gigabit Ethernet" },
 178         [BCM57840_MF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
 179         [BCM57840_VF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" },
 180         [BCM57811]      = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet" },
 181         [BCM57811_MF]   = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet Multi Function" },
 182         [BCM57840_O]    = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
 183         [BCM57840_MFO]  = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
 184         [BCM57811_VF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" }
 185 };
 186
 187 #ifndef PCI_DEVICE_ID_NX2_57710
 188 #define PCI_DEVICE_ID_NX2_57710         CHIP_NUM_57710
 189 #endif
 190 #ifndef PCI_DEVICE_ID_NX2_57711
 191 #define PCI_DEVICE_ID_NX2_57711         CHIP_NUM_57711
 192 #endif
 193 #ifndef PCI_DEVICE_ID_NX2_57711E
 194 #define PCI_DEVICE_ID_NX2_57711E        CHIP_NUM_57711E
 195 #endif
 196 #ifndef PCI_DEVICE_ID_NX2_57712
 197 #define PCI_DEVICE_ID_NX2_57712         CHIP_NUM_57712
 198 #endif
 199 #ifndef PCI_DEVICE_ID_NX2_57712_MF
 200 #define PCI_DEVICE_ID_NX2_57712_MF      CHIP_NUM_57712_MF
 201 #endif
 202 #ifndef PCI_DEVICE_ID_NX2_57712_VF
 203 #define PCI_DEVICE_ID_NX2_57712_VF      CHIP_NUM_57712_VF
 204 #endif
 205 #ifndef PCI_DEVICE_ID_NX2_57800
 206 #define PCI_DEVICE_ID_NX2_57800         CHIP_NUM_57800
 207 #endif
 208 #ifndef PCI_DEVICE_ID_NX2_57800_MF
 209 #define PCI_DEVICE_ID_NX2_57800_MF      CHIP_NUM_57800_MF
 210 #endif
 211 #ifndef PCI_DEVICE_ID_NX2_57800_VF
 212 #define PCI_DEVICE_ID_NX2_57800_VF      CHIP_NUM_57800_VF
 213 #endif
 214 #ifndef PCI_DEVICE_ID_NX2_57810
 215 #define PCI_DEVICE_ID_NX2_57810         CHIP_NUM_57810
 216 #endif
 217 #ifndef PCI_DEVICE_ID_NX2_57810_MF
 218 #define PCI_DEVICE_ID_NX2_57810_MF      CHIP_NUM_57810_MF
 219 #endif
 220 #ifndef PCI_DEVICE_ID_NX2_57840_O
 221 #define PCI_DEVICE_ID_NX2_57840_O       CHIP_NUM_57840_OBSOLETE
 222 #endif
 223 #ifndef PCI_DEVICE_ID_NX2_57810_VF
 224 #define PCI_DEVICE_ID_NX2_57810_VF      CHIP_NUM_57810_VF
 225 #endif
 226 #ifndef PCI_DEVICE_ID_NX2_57840_4_10
 227 #define PCI_DEVICE_ID_NX2_57840_4_10    CHIP_NUM_57840_4_10
 228 #endif
 229 #ifndef PCI_DEVICE_ID_NX2_57840_2_20
 230 #define PCI_DEVICE_ID_NX2_57840_2_20    CHIP_NUM_57840_2_20
 231 #endif
 232 #ifndef PCI_DEVICE_ID_NX2_57840_MFO
 233 #define PCI_DEVICE_ID_NX2_57840_MFO     CHIP_NUM_57840_MF_OBSOLETE
 234 #endif
 235 #ifndef PCI_DEVICE_ID_NX2_57840_MF
 236 #define PCI_DEVICE_ID_NX2_57840_MF      CHIP_NUM_57840_MF
 237 #endif
 238 #ifndef PCI_DEVICE_ID_NX2_57840_VF
 239 #define PCI_DEVICE_ID_NX2_57840_VF      CHIP_NUM_57840_VF
 240 #endif
 241 #ifndef PCI_DEVICE_ID_NX2_57811
 242 #define PCI_DEVICE_ID_NX2_57811         CHIP_NUM_57811
 243 #endif
 244 #ifndef PCI_DEVICE_ID_NX2_57811_MF
 245 #define PCI_DEVICE_ID_NX2_57811_MF      CHIP_NUM_57811_MF
 246 #endif
 247 #ifndef PCI_DEVICE_ID_NX2_57811_VF
 248 #define PCI_DEVICE_ID_NX2_57811_VF      CHIP_NUM_57811_VF
 249 #endif
 250
 251 static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
 252         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
 253         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
 254         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
 255         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
 256         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
 257         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF },
 258         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
 259         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
 260         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF },
 261         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
 262         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
 263         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O },
 264         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
 265         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 },
 266         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF },
 267         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO },
 268         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
 269         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
 270         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
 271         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
 272         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF },
 273         { 0 }
 274 };
 275
 276 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
 277
 278 /* Global resources for unloading a previously loaded device */
 279 #define BNX2X_PREV_WAIT_NEEDED 1
 280 static DEFINE_SEMAPHORE(bnx2x_prev_sem);
 281 static LIST_HEAD(bnx2x_prev_list);
 282 /****************************************************************************
 283 * General service functions
 284 ****************************************************************************/
 285
 286 static void __storm_memset_dma_mapping(struct bnx2x *bp,
 287                                        u32 addr, dma_addr_t mapping)
 288 {
 289         REG_WR(bp,  addr, U64_LO(mapping));
 290         REG_WR(bp,  addr + 4, U64_HI(mapping));
 291 }
 292
 293 static void storm_memset_spq_addr(struct bnx2x *bp,
 294                                   dma_addr_t mapping, u16 abs_fid)
 295 {
 296         u32 addr = XSEM_REG_FAST_MEMORY +
 297                         XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
 298
 299         __storm_memset_dma_mapping(bp, addr, mapping);
 300 }
 301
 302 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
 303                                   u16 pf_id)
 304 {
 305         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
 306                 pf_id);
 307         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
 308                 pf_id);
 309         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
 310                 pf_id);
 311         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
 312                 pf_id);
 313 }
 314
 315 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
 316                                  u8 enable)
 317 {
 318         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
 319                 enable);
 320         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
 321                 enable);
 322         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
 323                 enable);
 324         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
 325                 enable);
 326 }
 327
 328 static void storm_memset_eq_data(struct bnx2x *bp,
 329                                  struct event_ring_data *eq_data,
 330                                 u16 pfid)
 331 {
 332         size_t size = sizeof(struct event_ring_data);
 333
 334         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
 335
 336         __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
 337 }
 338
 339 static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
 340                                  u16 pfid)
 341 {
 342         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
 343         REG_WR16(bp, addr, eq_prod);
 344 }
 345
 346 /* used only at init
 347  * locking is done by mcp
 348  */
 349 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
 350 {
 351         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
 352         pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
 353         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
 354                                PCICFG_VENDOR_ID_OFFSET);
 355 }
 356
 357 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
 358 {
 359         u32 val;
 360
 361         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
 362         pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
 363         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
 364                                PCICFG_VENDOR_ID_OFFSET);
 365
 366         return val;
 367 }
 368
 369 #define DMAE_DP_SRC_GRC         "grc src_addr [%08x]"
 370 #define DMAE_DP_SRC_PCI         "pci src_addr [%x:%08x]"
 371 #define DMAE_DP_DST_GRC         "grc dst_addr [%08x]"
 372 #define DMAE_DP_DST_PCI         "pci dst_addr [%x:%08x]"
 373 #define DMAE_DP_DST_NONE        "dst_addr [none]"
 374
 375 static void bnx2x_dp_dmae(struct bnx2x *bp,
 376                           struct dmae_command *dmae, int msglvl)
 377 {
 378         u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
 379         int i;
 380
 381         switch (dmae->opcode & DMAE_COMMAND_DST) {
 382         case DMAE_CMD_DST_PCI:
 383                 if (src_type == DMAE_CMD_SRC_PCI)
 384                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 385                            "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
 386                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 387                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 388                            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
 389                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 390                            dmae->comp_val);
 391                 else
 392                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 393                            "src [%08x], len [%d*4], dst [%x:%08x]\n"
 394                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 395                            dmae->opcode, dmae->src_addr_lo >> 2,
 396                            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
 397                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 398                            dmae->comp_val);
 399                 break;
 400         case DMAE_CMD_DST_GRC:
 401                 if (src_type == DMAE_CMD_SRC_PCI)
 402                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 403                            "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
 404                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 405                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 406                            dmae->len, dmae->dst_addr_lo >> 2,
 407                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 408                            dmae->comp_val);
 409                 else
 410                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 411                            "src [%08x], len [%d*4], dst [%08x]\n"
 412                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 413                            dmae->opcode, dmae->src_addr_lo >> 2,
 414                            dmae->len, dmae->dst_addr_lo >> 2,
 415                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 416                            dmae->comp_val);
 417                 break;
 418         default:
 419                 if (src_type == DMAE_CMD_SRC_PCI)
 420                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 421                            "src_addr [%x:%08x]  len [%d * 4]  dst_addr [none]\n"
 422                            "comp_addr [%x:%08x]  comp_val 0x%08x\n",
 423                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 424                            dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
 425                            dmae->comp_val);
 426                 else
 427                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 428                            "src_addr [%08x]  len [%d * 4]  dst_addr [none]\n"
 429                            "comp_addr [%x:%08x]  comp_val 0x%08x\n",
 430                            dmae->opcode, dmae->src_addr_lo >> 2,
 431                            dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
 432                            dmae->comp_val);
 433                 break;
 434         }
 435
 436         for (i = 0; i < (sizeof(struct dmae_command)/4); i++)
 437                 DP(msglvl, "DMAE RAW [%02d]: 0x%08x\n",
 438                    i, *(((u32 *)dmae) + i));
 439 }
 440
 441 /* copy command into DMAE command memory and set DMAE command go */
 442 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
 443 {
 444         u32 cmd_offset;
 445         int i;
 446
 447         cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
 448         for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
 449                 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
 450         }
 451         REG_WR(bp, dmae_reg_go_c[idx], 1);
 452 }
 453
 454 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
 455 {
 456         return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
 457                            DMAE_CMD_C_ENABLE);
 458 }
 459
 460 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
 461 {
 462         return opcode & ~DMAE_CMD_SRC_RESET;
 463 }
 464
 465 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
 466                              bool with_comp, u8 comp_type)
 467 {
 468         u32 opcode = 0;
 469
 470         opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
 471                    (dst_type << DMAE_COMMAND_DST_SHIFT));
 472
 473         opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
 474
 475         opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
 476         opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
 477                    (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
 478         opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
 479
 480 #ifdef __BIG_ENDIAN
 481         opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
 482 #else
 483         opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
 484 #endif
 485         if (with_comp)
 486                 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
 487         return opcode;
 488 }
 489
 490 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
 491                                       struct dmae_command *dmae,
 492                                       u8 src_type, u8 dst_type)
 493 {
 494         memset(dmae, 0, sizeof(struct dmae_command));
 495
 496         /* set the opcode */
 497         dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
 498                                          true, DMAE_COMP_PCI);
 499
 500         /* fill in the completion parameters */
 501         dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
 502         dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
 503         dmae->comp_val = DMAE_COMP_VAL;
 504 }
 505
 506 /* issue a dmae command over the init-channel and wait for completion */
 507 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
 508                                u32 *comp)
 509 {
 510         int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
 511         int rc = 0;
 512
 513         bnx2x_dp_dmae(bp, dmae, BNX2X_MSG_DMAE);
 514
 515         /* Lock the dmae channel. Disable BHs to prevent a dead-lock
 516          * as long as this code is called both from syscall context and
 517          * from ndo_set_rx_mode() flow that may be called from BH.
 518          */
 519         spin_lock_bh(&bp->dmae_lock);
 520
 521         /* reset completion */
 522         *comp = 0;
 523
 524         /* post the command on the channel used for initializations */
 525         bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
 526
 527         /* wait for completion */
 528         udelay(5);
 529         while ((*comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
 530
 531                 if (!cnt ||
 532                     (bp->recovery_state != BNX2X_RECOVERY_DONE &&
 533                      bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
 534                         BNX2X_ERR("DMAE timeout!\n");
 535                         rc = DMAE_TIMEOUT;
 536                         goto unlock;
 537                 }
 538                 cnt--;
 539                 udelay(50);
 540         }
 541         if (*comp & DMAE_PCI_ERR_FLAG) {
 542                 BNX2X_ERR("DMAE PCI error!\n");
 543                 rc = DMAE_PCI_ERROR;
 544         }
 545
 546 unlock:
 547         spin_unlock_bh(&bp->dmae_lock);
 548         return rc;
 549 }
 550
 551 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
 552                       u32 len32)
 553 {
 554         int rc;
 555         struct dmae_command dmae;
 556
 557         if (!bp->dmae_ready) {
 558                 u32 *data = bnx2x_sp(bp, wb_data[0]);
 559
 560                 if (CHIP_IS_E1(bp))
 561                         bnx2x_init_ind_wr(bp, dst_addr, data, len32);
 562                 else
 563                         bnx2x_init_str_wr(bp, dst_addr, data, len32);
 564                 return;
 565         }
 566
 567         /* set opcode and fixed command fields */
 568         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
 569
 570         /* fill in addresses and len */
 571         dmae.src_addr_lo = U64_LO(dma_addr);
 572         dmae.src_addr_hi = U64_HI(dma_addr);
 573         dmae.dst_addr_lo = dst_addr >> 2;
 574         dmae.dst_addr_hi = 0;
 575         dmae.len = len32;
 576
 577         /* issue the command and wait for completion */
 578         rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
 579         if (rc) {
 580                 BNX2X_ERR("DMAE returned failure %d\n", rc);
 581 #ifdef BNX2X_STOP_ON_ERROR
 582                 bnx2x_panic();
 583 #endif
 584         }
 585 }
 586
 587 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
 588 {
 589         int rc;
 590         struct dmae_command dmae;
 591
 592         if (!bp->dmae_ready) {
 593                 u32 *data = bnx2x_sp(bp, wb_data[0]);
 594                 int i;
 595
 596                 if (CHIP_IS_E1(bp))
 597                         for (i = 0; i < len32; i++)
 598                                 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
 599                 else
 600                         for (i = 0; i < len32; i++)
 601                                 data[i] = REG_RD(bp, src_addr + i*4);
 602
 603                 return;
 604         }
 605
 606         /* set opcode and fixed command fields */
 607         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
 608
 609         /* fill in addresses and len */
 610         dmae.src_addr_lo = src_addr >> 2;
 611         dmae.src_addr_hi = 0;
 612         dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
 613         dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
 614         dmae.len = len32;
 615
 616         /* issue the command and wait for completion */
 617         rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
 618         if (rc) {
 619                 BNX2X_ERR("DMAE returned failure %d\n", rc);
 620 #ifdef BNX2X_STOP_ON_ERROR
 621                 bnx2x_panic();
 622 #endif
 623         }
 624 }
 625
 626 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
 627                                       u32 addr, u32 len)
 628 {
 629         int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
 630         int offset = 0;
 631
 632         while (len > dmae_wr_max) {
 633                 bnx2x_write_dmae(bp, phys_addr + offset,
 634                                  addr + offset, dmae_wr_max);
 635                 offset += dmae_wr_max * 4;
 636                 len -= dmae_wr_max;
 637         }
 638
 639         bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
 640 }
 641
 642 static int bnx2x_mc_assert(struct bnx2x *bp)
 643 {
 644         char last_idx;
 645         int i, rc = 0;
 646         u32 row0, row1, row2, row3;
 647
 648         /* XSTORM */
 649         last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
 650                            XSTORM_ASSERT_LIST_INDEX_OFFSET);
 651         if (last_idx)
 652                 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
 653
 654         /* print the asserts */
 655         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 656
 657                 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
 658                               XSTORM_ASSERT_LIST_OFFSET(i));
 659                 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
 660                               XSTORM_ASSERT_LIST_OFFSET(i) + 4);
 661                 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
 662                               XSTORM_ASSERT_LIST_OFFSET(i) + 8);
 663                 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
 664                               XSTORM_ASSERT_LIST_OFFSET(i) + 12);
 665
 666                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 667                         BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
 668                                   i, row3, row2, row1, row0);
 669                         rc++;
 670                 } else {
 671                         break;
 672                 }
 673         }
 674
 675         /* TSTORM */
 676         last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
 677                            TSTORM_ASSERT_LIST_INDEX_OFFSET);
 678         if (last_idx)
 679                 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
 680
 681         /* print the asserts */
 682         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 683
 684                 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
 685                               TSTORM_ASSERT_LIST_OFFSET(i));
 686                 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
 687                               TSTORM_ASSERT_LIST_OFFSET(i) + 4);
 688                 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
 689                               TSTORM_ASSERT_LIST_OFFSET(i) + 8);
 690                 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
 691                               TSTORM_ASSERT_LIST_OFFSET(i) + 12);
 692
 693                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 694                         BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
 695                                   i, row3, row2, row1, row0);
 696                         rc++;
 697                 } else {
 698                         break;
 699                 }
 700         }
 701
 702         /* CSTORM */
 703         last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
 704                            CSTORM_ASSERT_LIST_INDEX_OFFSET);
 705         if (last_idx)
 706                 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
 707
 708         /* print the asserts */
 709         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 710
 711                 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
 712                               CSTORM_ASSERT_LIST_OFFSET(i));
 713                 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
 714                               CSTORM_ASSERT_LIST_OFFSET(i) + 4);
 715                 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
 716                               CSTORM_ASSERT_LIST_OFFSET(i) + 8);
 717                 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
 718                               CSTORM_ASSERT_LIST_OFFSET(i) + 12);
 719
 720                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 721                         BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
 722                                   i, row3, row2, row1, row0);
 723                         rc++;
 724                 } else {
 725                         break;
 726                 }
 727         }
 728
 729         /* USTORM */
 730         last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
 731                            USTORM_ASSERT_LIST_INDEX_OFFSET);
 732         if (last_idx)
 733                 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
 734
 735         /* print the asserts */
 736         for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 737
 738                 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
 739                               USTORM_ASSERT_LIST_OFFSET(i));
 740                 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
 741                               USTORM_ASSERT_LIST_OFFSET(i) + 4);
 742                 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
 743                               USTORM_ASSERT_LIST_OFFSET(i) + 8);
 744                 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
 745                               USTORM_ASSERT_LIST_OFFSET(i) + 12);
 746
 747                 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 748                         BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
 749                                   i, row3, row2, row1, row0);
 750                         rc++;
 751                 } else {
 752                         break;
 753                 }
 754         }
 755
 756         return rc;
 757 }
 758
 759 #define MCPR_TRACE_BUFFER_SIZE  (0x800)
 760 #define SCRATCH_BUFFER_SIZE(bp) \
 761         (CHIP_IS_E1(bp) ? 0x10000 : (CHIP_IS_E1H(bp) ? 0x20000 : 0x28000))
 762
 763 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
 764 {
 765         u32 addr, val;
 766         u32 mark, offset;
 767         __be32 data[9];
 768         int word;
 769         u32 trace_shmem_base;
 770         if (BP_NOMCP(bp)) {
 771                 BNX2X_ERR("NO MCP - can not dump\n");
 772                 return;
 773         }
 774         netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
 775                 (bp->common.bc_ver & 0xff0000) >> 16,
 776                 (bp->common.bc_ver & 0xff00) >> 8,
 777                 (bp->common.bc_ver & 0xff));
 778
 779         val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
 780         if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
 781                 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
 782
 783         if (BP_PATH(bp) == 0)
 784                 trace_shmem_base = bp->common.shmem_base;
 785         else
 786                 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
 787
 788         /* sanity */
 789         if (trace_shmem_base < MCPR_SCRATCH_BASE(bp) + MCPR_TRACE_BUFFER_SIZE ||
 790             trace_shmem_base >= MCPR_SCRATCH_BASE(bp) +
 791                                 SCRATCH_BUFFER_SIZE(bp)) {
 792                 BNX2X_ERR("Unable to dump trace buffer (mark %x)\n",
 793                           trace_shmem_base);
 794                 return;
 795         }
 796
 797         addr = trace_shmem_base - MCPR_TRACE_BUFFER_SIZE;
 798
 799         /* validate TRCB signature */
 800         mark = REG_RD(bp, addr);
 801         if (mark != MFW_TRACE_SIGNATURE) {
 802                 BNX2X_ERR("Trace buffer signature is missing.");
 803                 return ;
 804         }
 805
 806         /* read cyclic buffer pointer */
 807         addr += 4;
 808         mark = REG_RD(bp, addr);
 809         mark = MCPR_SCRATCH_BASE(bp) + ((mark + 0x3) & ~0x3) - 0x08000000;
 810         if (mark >= trace_shmem_base || mark < addr + 4) {
 811                 BNX2X_ERR("Mark doesn't fall inside Trace Buffer\n");
 812                 return;
 813         }
 814         printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
 815
 816         printk("%s", lvl);
 817
 818         /* dump buffer after the mark */
 819         for (offset = mark; offset < trace_shmem_base; offset += 0x8*4) {
 820                 for (word = 0; word < 8; word++)
 821                         data[word] = htonl(REG_RD(bp, offset + 4*word));
 822                 data[8] = 0x0;
 823                 pr_cont("%s", (char *)data);
 824         }
 825
 826         /* dump buffer before the mark */
 827         for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
 828                 for (word = 0; word < 8; word++)
 829                         data[word] = htonl(REG_RD(bp, offset + 4*word));
 830                 data[8] = 0x0;
 831                 pr_cont("%s", (char *)data);
 832         }
 833         printk("%s" "end of fw dump\n", lvl);
 834 }
 835
 836 static void bnx2x_fw_dump(struct bnx2x *bp)
 837 {
 838         bnx2x_fw_dump_lvl(bp, KERN_ERR);
 839 }
 840
 841 static void bnx2x_hc_int_disable(struct bnx2x *bp)
 842 {
 843         int port = BP_PORT(bp);
 844         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
 845         u32 val = REG_RD(bp, addr);
 846
 847         /* in E1 we must use only PCI configuration space to disable
 848          * MSI/MSIX capability
 849          * It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
 850          */
 851         if (CHIP_IS_E1(bp)) {
 852                 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
 853                  * Use mask register to prevent from HC sending interrupts
 854                  * after we exit the function
 855                  */
 856                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
 857
 858                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
 859                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
 860                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
 861         } else
 862                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
 863                          HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
 864                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
 865                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
 866
 867         DP(NETIF_MSG_IFDOWN,
 868            "write %x to HC %d (addr 0x%x)\n",
 869            val, port, addr);
 870
 871         /* flush all outstanding writes */
 872         mmiowb();
 873
 874         REG_WR(bp, addr, val);
 875         if (REG_RD(bp, addr) != val)
 876                 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
 877 }
 878
 879 static void bnx2x_igu_int_disable(struct bnx2x *bp)
 880 {
 881         u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
 882
 883         val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
 884                  IGU_PF_CONF_INT_LINE_EN |
 885                  IGU_PF_CONF_ATTN_BIT_EN);
 886
 887         DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
 888
 889         /* flush all outstanding writes */
 890         mmiowb();
 891
 892         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
 893         if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
 894                 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
 895 }
 896
 897 static void bnx2x_int_disable(struct bnx2x *bp)
 898 {
 899         if (bp->common.int_block == INT_BLOCK_HC)
 900                 bnx2x_hc_int_disable(bp);
 901         else
 902                 bnx2x_igu_int_disable(bp);
 903 }
 904
 905 void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int)
 906 {
 907         int i;
 908         u16 j;
 909         struct hc_sp_status_block_data sp_sb_data;
 910         int func = BP_FUNC(bp);
 911 #ifdef BNX2X_STOP_ON_ERROR
 912         u16 start = 0, end = 0;
 913         u8 cos;
 914 #endif
 915         if (disable_int)
 916                 bnx2x_int_disable(bp);
 917
 918         bp->stats_state = STATS_STATE_DISABLED;
 919         bp->eth_stats.unrecoverable_error++;
 920         DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
 921
 922         BNX2X_ERR("begin crash dump -----------------\n");
 923
 924         /* Indices */
 925         /* Common */
 926         BNX2X_ERR("def_idx(0x%x)  def_att_idx(0x%x)  attn_state(0x%x)  spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
 927                   bp->def_idx, bp->def_att_idx, bp->attn_state,
 928                   bp->spq_prod_idx, bp->stats_counter);
 929         BNX2X_ERR("DSB: attn bits(0x%x)  ack(0x%x)  id(0x%x)  idx(0x%x)\n",
 930                   bp->def_status_blk->atten_status_block.attn_bits,
 931                   bp->def_status_blk->atten_status_block.attn_bits_ack,
 932                   bp->def_status_blk->atten_status_block.status_block_id,
 933                   bp->def_status_blk->atten_status_block.attn_bits_index);
 934         BNX2X_ERR("     def (");
 935         for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
 936                 pr_cont("0x%x%s",
 937                         bp->def_status_blk->sp_sb.index_values[i],
 938                         (i == HC_SP_SB_MAX_INDICES - 1) ? ")  " : " ");
 939
 940         for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
 941                 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM +
 942                         CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
 943                         i*sizeof(u32));
 944
 945         pr_cont("igu_sb_id(0x%x)  igu_seg_id(0x%x) pf_id(0x%x)  vnic_id(0x%x)  vf_id(0x%x)  vf_valid (0x%x) state(0x%x)\n",
 946                sp_sb_data.igu_sb_id,
 947                sp_sb_data.igu_seg_id,
 948                sp_sb_data.p_func.pf_id,
 949                sp_sb_data.p_func.vnic_id,
 950                sp_sb_data.p_func.vf_id,
 951                sp_sb_data.p_func.vf_valid,
 952                sp_sb_data.state);
 953
 954         for_each_eth_queue(bp, i) {
 955                 struct bnx2x_fastpath *fp = &bp->fp[i];
 956                 int loop;
 957                 struct hc_status_block_data_e2 sb_data_e2;
 958                 struct hc_status_block_data_e1x sb_data_e1x;
 959                 struct hc_status_block_sm  *hc_sm_p =
 960                         CHIP_IS_E1x(bp) ?
 961                         sb_data_e1x.common.state_machine :
 962                         sb_data_e2.common.state_machine;
 963                 struct hc_index_data *hc_index_p =
 964                         CHIP_IS_E1x(bp) ?
 965                         sb_data_e1x.index_data :
 966                         sb_data_e2.index_data;
 967                 u8 data_size, cos;
 968                 u32 *sb_data_p;
 969                 struct bnx2x_fp_txdata txdata;
 970
 971                 /* Rx */
 972                 BNX2X_ERR("fp%d: rx_bd_prod(0x%x)  rx_bd_cons(0x%x)  rx_comp_prod(0x%x)  rx_comp_cons(0x%x)  *rx_cons_sb(0x%x)\n",
 973                           i, fp->rx_bd_prod, fp->rx_bd_cons,
 974                           fp->rx_comp_prod,
 975                           fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
 976                 BNX2X_ERR("     rx_sge_prod(0x%x)  last_max_sge(0x%x)  fp_hc_idx(0x%x)\n",
 977                           fp->rx_sge_prod, fp->last_max_sge,
 978                           le16_to_cpu(fp->fp_hc_idx));
 979
 980                 /* Tx */
 981                 for_each_cos_in_tx_queue(fp, cos)
 982                 {
 983                         txdata = *fp->txdata_ptr[cos];
 984                         BNX2X_ERR("fp%d: tx_pkt_prod(0x%x)  tx_pkt_cons(0x%x)  tx_bd_prod(0x%x)  tx_bd_cons(0x%x)  *tx_cons_sb(0x%x)\n",
 985                                   i, txdata.tx_pkt_prod,
 986                                   txdata.tx_pkt_cons, txdata.tx_bd_prod,
 987                                   txdata.tx_bd_cons,
 988                                   le16_to_cpu(*txdata.tx_cons_sb));
 989                 }
 990
 991                 loop = CHIP_IS_E1x(bp) ?
 992                         HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
 993
 994                 /* host sb data */
 995
 996                 if (IS_FCOE_FP(fp))
 997                         continue;
 998
 999                 BNX2X_ERR("     run indexes (");
1000                 for (j = 0; j < HC_SB_MAX_SM; j++)
1001                         pr_cont("0x%x%s",
1002                                fp->sb_running_index[j],
1003                                (j == HC_SB_MAX_SM - 1) ? ")" : " ");
1004
1005                 BNX2X_ERR("     indexes (");
1006                 for (j = 0; j < loop; j++)
1007                         pr_cont("0x%x%s",
1008                                fp->sb_index_values[j],
1009                                (j == loop - 1) ? ")" : " ");
1010                 /* fw sb data */
1011                 data_size = CHIP_IS_E1x(bp) ?
1012                         sizeof(struct hc_status_block_data_e1x) :
1013                         sizeof(struct hc_status_block_data_e2);
1014                 data_size /= sizeof(u32);
1015                 sb_data_p = CHIP_IS_E1x(bp) ?
1016                         (u32 *)&sb_data_e1x :
1017                         (u32 *)&sb_data_e2;
1018                 /* copy sb data in here */
1019                 for (j = 0; j < data_size; j++)
1020                         *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
1021                                 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
1022                                 j * sizeof(u32));
1023
1024                 if (!CHIP_IS_E1x(bp)) {
1025                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
1026                                 sb_data_e2.common.p_func.pf_id,
1027                                 sb_data_e2.common.p_func.vf_id,
1028                                 sb_data_e2.common.p_func.vf_valid,
1029                                 sb_data_e2.common.p_func.vnic_id,
1030                                 sb_data_e2.common.same_igu_sb_1b,
1031                                 sb_data_e2.common.state);
1032                 } else {
1033                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
1034                                 sb_data_e1x.common.p_func.pf_id,
1035                                 sb_data_e1x.common.p_func.vf_id,
1036                                 sb_data_e1x.common.p_func.vf_valid,
1037                                 sb_data_e1x.common.p_func.vnic_id,
1038                                 sb_data_e1x.common.same_igu_sb_1b,
1039                                 sb_data_e1x.common.state);
1040                 }
1041
1042                 /* SB_SMs data */
1043                 for (j = 0; j < HC_SB_MAX_SM; j++) {
1044                         pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x)  igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
1045                                 j, hc_sm_p[j].__flags,
1046                                 hc_sm_p[j].igu_sb_id,
1047                                 hc_sm_p[j].igu_seg_id,
1048                                 hc_sm_p[j].time_to_expire,
1049                                 hc_sm_p[j].timer_value);
1050                 }
1051
1052                 /* Indices data */
1053                 for (j = 0; j < loop; j++) {
1054                         pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
1055                                hc_index_p[j].flags,
1056                                hc_index_p[j].timeout);
1057                 }
1058         }
1059
1060 #ifdef BNX2X_STOP_ON_ERROR
1061
1062         /* event queue */
1063         BNX2X_ERR("eq cons %x prod %x\n", bp->eq_cons, bp->eq_prod);
1064         for (i = 0; i < NUM_EQ_DESC; i++) {
1065                 u32 *data = (u32 *)&bp->eq_ring[i].message.data;
1066
1067                 BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n",
1068                           i, bp->eq_ring[i].message.opcode,
1069                           bp->eq_ring[i].message.error);
1070                 BNX2X_ERR("data: %x %x %x\n", data[0], data[1], data[2]);
1071         }
1072
1073         /* Rings */
1074         /* Rx */
1075         for_each_valid_rx_queue(bp, i) {
1076                 struct bnx2x_fastpath *fp = &bp->fp[i];
1077
1078                 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
1079                 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
1080                 for (j = start; j != end; j = RX_BD(j + 1)) {
1081                         u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
1082                         struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
1083
1084                         BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x]  sw_bd=[%p]\n",
1085                                   i, j, rx_bd[1], rx_bd[0], sw_bd->data);
1086                 }
1087
1088                 start = RX_SGE(fp->rx_sge_prod);
1089                 end = RX_SGE(fp->last_max_sge);
1090                 for (j = start; j != end; j = RX_SGE(j + 1)) {
1091                         u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
1092                         struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
1093
1094                         BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x]  sw_page=[%p]\n",
1095                                   i, j, rx_sge[1], rx_sge[0], sw_page->page);
1096                 }
1097
1098                 start = RCQ_BD(fp->rx_comp_cons - 10);
1099                 end = RCQ_BD(fp->rx_comp_cons + 503);
1100                 for (j = start; j != end; j = RCQ_BD(j + 1)) {
1101                         u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
1102
1103                         BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1104                                   i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
1105                 }
1106         }
1107
1108         /* Tx */
1109         for_each_valid_tx_queue(bp, i) {
1110                 struct bnx2x_fastpath *fp = &bp->fp[i];
1111                 for_each_cos_in_tx_queue(fp, cos) {
1112                         struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
1113
1114                         start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
1115                         end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
1116                         for (j = start; j != end; j = TX_BD(j + 1)) {
1117                                 struct sw_tx_bd *sw_bd =
1118                                         &txdata->tx_buf_ring[j];
1119
1120                                 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
1121                                           i, cos, j, sw_bd->skb,
1122                                           sw_bd->first_bd);
1123                         }
1124
1125                         start = TX_BD(txdata->tx_bd_cons - 10);
1126                         end = TX_BD(txdata->tx_bd_cons + 254);
1127                         for (j = start; j != end; j = TX_BD(j + 1)) {
1128                                 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
1129
1130                                 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
1131                                           i, cos, j, tx_bd[0], tx_bd[1],
1132                                           tx_bd[2], tx_bd[3]);
1133                         }
1134                 }
1135         }
1136 #endif
1137         bnx2x_fw_dump(bp);
1138         bnx2x_mc_assert(bp);
1139         BNX2X_ERR("end crash dump -----------------\n");
1140 }
1141
1142 /*
1143  * FLR Support for E2
1144  *
1145  * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1146  * initialization.
1147  */
1148 #define FLR_WAIT_USEC           10000   /* 10 milliseconds */
1149 #define FLR_WAIT_INTERVAL       50      /* usec */
1150 #define FLR_POLL_CNT            (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
1151
1152 struct pbf_pN_buf_regs {
1153         int pN;
1154         u32 init_crd;
1155         u32 crd;
1156         u32 crd_freed;
1157 };
1158
1159 struct pbf_pN_cmd_regs {
1160         int pN;
1161         u32 lines_occup;
1162         u32 lines_freed;
1163 };
1164
1165 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1166                                      struct pbf_pN_buf_regs *regs,
1167                                      u32 poll_count)
1168 {
1169         u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1170         u32 cur_cnt = poll_count;
1171
1172         crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1173         crd = crd_start = REG_RD(bp, regs->crd);
1174         init_crd = REG_RD(bp, regs->init_crd);
1175
1176         DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1177         DP(BNX2X_MSG_SP, "CREDIT[%d]      : s:%x\n", regs->pN, crd);
1178         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1179
1180         while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1181                (init_crd - crd_start))) {
1182                 if (cur_cnt--) {
1183                         udelay(FLR_WAIT_INTERVAL);
1184                         crd = REG_RD(bp, regs->crd);
1185                         crd_freed = REG_RD(bp, regs->crd_freed);
1186                 } else {
1187                         DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1188                            regs->pN);
1189                         DP(BNX2X_MSG_SP, "CREDIT[%d]      : c:%x\n",
1190                            regs->pN, crd);
1191                         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1192                            regs->pN, crd_freed);
1193                         break;
1194                 }
1195         }
1196         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1197            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1198 }
1199
1200 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1201                                      struct pbf_pN_cmd_regs *regs,
1202                                      u32 poll_count)
1203 {
1204         u32 occup, to_free, freed, freed_start;
1205         u32 cur_cnt = poll_count;
1206
1207         occup = to_free = REG_RD(bp, regs->lines_occup);
1208         freed = freed_start = REG_RD(bp, regs->lines_freed);
1209
1210         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n", regs->pN, occup);
1211         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1212
1213         while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1214                 if (cur_cnt--) {
1215                         udelay(FLR_WAIT_INTERVAL);
1216                         occup = REG_RD(bp, regs->lines_occup);
1217                         freed = REG_RD(bp, regs->lines_freed);
1218                 } else {
1219                         DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1220                            regs->pN);
1221                         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n",
1222                            regs->pN, occup);
1223                         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1224                            regs->pN, freed);
1225                         break;
1226                 }
1227         }
1228         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1229            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1230 }
1231
1232 static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1233                                     u32 expected, u32 poll_count)
1234 {
1235         u32 cur_cnt = poll_count;
1236         u32 val;
1237
1238         while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1239                 udelay(FLR_WAIT_INTERVAL);
1240
1241         return val;
1242 }
1243
1244 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1245                                     char *msg, u32 poll_cnt)
1246 {
1247         u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1248         if (val != 0) {
1249                 BNX2X_ERR("%s usage count=%d\n", msg, val);
1250                 return 1;
1251         }
1252         return 0;
1253 }
1254
1255 /* Common routines with VF FLR cleanup */
1256 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1257 {
1258         /* adjust polling timeout */
1259         if (CHIP_REV_IS_EMUL(bp))
1260                 return FLR_POLL_CNT * 2000;
1261
1262         if (CHIP_REV_IS_FPGA(bp))
1263                 return FLR_POLL_CNT * 120;
1264
1265         return FLR_POLL_CNT;
1266 }
1267
1268 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1269 {
1270         struct pbf_pN_cmd_regs cmd_regs[] = {
1271                 {0, (CHIP_IS_E3B0(bp)) ?
1272                         PBF_REG_TQ_OCCUPANCY_Q0 :
1273                         PBF_REG_P0_TQ_OCCUPANCY,
1274                     (CHIP_IS_E3B0(bp)) ?
1275                         PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1276                         PBF_REG_P0_TQ_LINES_FREED_CNT},
1277                 {1, (CHIP_IS_E3B0(bp)) ?
1278                         PBF_REG_TQ_OCCUPANCY_Q1 :
1279                         PBF_REG_P1_TQ_OCCUPANCY,
1280                     (CHIP_IS_E3B0(bp)) ?
1281                         PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1282                         PBF_REG_P1_TQ_LINES_FREED_CNT},
1283                 {4, (CHIP_IS_E3B0(bp)) ?
1284                         PBF_REG_TQ_OCCUPANCY_LB_Q :
1285                         PBF_REG_P4_TQ_OCCUPANCY,
1286                     (CHIP_IS_E3B0(bp)) ?
1287                         PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1288                         PBF_REG_P4_TQ_LINES_FREED_CNT}
1289         };
1290
1291         struct pbf_pN_buf_regs buf_regs[] = {
1292                 {0, (CHIP_IS_E3B0(bp)) ?
1293                         PBF_REG_INIT_CRD_Q0 :
1294                         PBF_REG_P0_INIT_CRD ,
1295                     (CHIP_IS_E3B0(bp)) ?
1296                         PBF_REG_CREDIT_Q0 :
1297                         PBF_REG_P0_CREDIT,
1298                     (CHIP_IS_E3B0(bp)) ?
1299                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1300                         PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1301                 {1, (CHIP_IS_E3B0(bp)) ?
1302                         PBF_REG_INIT_CRD_Q1 :
1303                         PBF_REG_P1_INIT_CRD,
1304                     (CHIP_IS_E3B0(bp)) ?
1305                         PBF_REG_CREDIT_Q1 :
1306                         PBF_REG_P1_CREDIT,
1307                     (CHIP_IS_E3B0(bp)) ?
1308                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1309                         PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1310                 {4, (CHIP_IS_E3B0(bp)) ?
1311                         PBF_REG_INIT_CRD_LB_Q :
1312                         PBF_REG_P4_INIT_CRD,
1313                     (CHIP_IS_E3B0(bp)) ?
1314                         PBF_REG_CREDIT_LB_Q :
1315                         PBF_REG_P4_CREDIT,
1316                     (CHIP_IS_E3B0(bp)) ?
1317                         PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1318                         PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1319         };
1320
1321         int i;
1322
1323         /* Verify the command queues are flushed P0, P1, P4 */
1324         for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1325                 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1326
1327         /* Verify the transmission buffers are flushed P0, P1, P4 */
1328         for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1329                 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1330 }
1331
1332 #define OP_GEN_PARAM(param) \
1333         (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1334
1335 #define OP_GEN_TYPE(type) \
1336         (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1337
1338 #define OP_GEN_AGG_VECT(index) \
1339         (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1340
1341 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt)
1342 {
1343         u32 op_gen_command = 0;
1344         u32 comp_addr = BAR_CSTRORM_INTMEM +
1345                         CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1346         int ret = 0;
1347
1348         if (REG_RD(bp, comp_addr)) {
1349                 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
1350                 return 1;
1351         }
1352
1353         op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1354         op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1355         op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
1356         op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1357
1358         DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
1359         REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command);
1360
1361         if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1362                 BNX2X_ERR("FW final cleanup did not succeed\n");
1363                 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1364                    (REG_RD(bp, comp_addr)));
1365                 bnx2x_panic();
1366                 return 1;
1367         }
1368         /* Zero completion for next FLR */
1369         REG_WR(bp, comp_addr, 0);
1370
1371         return ret;
1372 }
1373
1374 u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1375 {
1376         u16 status;
1377
1378         pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
1379         return status & PCI_EXP_DEVSTA_TRPND;
1380 }
1381
1382 /* PF FLR specific routines
1383 */
1384 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1385 {
1386         /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1387         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1388                         CFC_REG_NUM_LCIDS_INSIDE_PF,
1389                         "CFC PF usage counter timed out",
1390                         poll_cnt))
1391                 return 1;
1392
1393         /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1394         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1395                         DORQ_REG_PF_USAGE_CNT,
1396                         "DQ PF usage counter timed out",
1397                         poll_cnt))
1398                 return 1;
1399
1400         /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1401         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1402                         QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1403                         "QM PF usage counter timed out",
1404                         poll_cnt))
1405                 return 1;
1406
1407         /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1408         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1409                         TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1410                         "Timers VNIC usage counter timed out",
1411                         poll_cnt))
1412                 return 1;
1413         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1414                         TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1415                         "Timers NUM_SCANS usage counter timed out",
1416                         poll_cnt))
1417                 return 1;
1418
1419         /* Wait DMAE PF usage counter to zero */
1420         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1421                         dmae_reg_go_c[INIT_DMAE_C(bp)],
1422                         "DMAE command register timed out",
1423                         poll_cnt))
1424                 return 1;
1425
1426         return 0;
1427 }
1428
1429 static void bnx2x_hw_enable_status(struct bnx2x *bp)
1430 {
1431         u32 val;
1432
1433         val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1434         DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1435
1436         val = REG_RD(bp, PBF_REG_DISABLE_PF);
1437         DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1438
1439         val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1440         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1441
1442         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1443         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1444
1445         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1446         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1447
1448         val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1449         DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1450
1451         val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1452         DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1453
1454         val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1455         DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1456            val);
1457 }
1458
1459 static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1460 {
1461         u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1462
1463         DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1464
1465         /* Re-enable PF target read access */
1466         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1467
1468         /* Poll HW usage counters */
1469         DP(BNX2X_MSG_SP, "Polling usage counters\n");
1470         if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1471                 return -EBUSY;
1472
1473         /* Zero the igu 'trailing edge' and 'leading edge' */
1474
1475         /* Send the FW cleanup command */
1476         if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1477                 return -EBUSY;
1478
1479         /* ATC cleanup */
1480
1481         /* Verify TX hw is flushed */
1482         bnx2x_tx_hw_flushed(bp, poll_cnt);
1483
1484         /* Wait 100ms (not adjusted according to platform) */
1485         msleep(100);
1486
1487         /* Verify no pending pci transactions */
1488         if (bnx2x_is_pcie_pending(bp->pdev))
1489                 BNX2X_ERR("PCIE Transactions still pending\n");
1490
1491         /* Debug */
1492         bnx2x_hw_enable_status(bp);
1493
1494         /*
1495          * Master enable - Due to WB DMAE writes performed before this
1496          * register is re-initialized as part of the regular function init
1497          */
1498         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1499
1500         return 0;
1501 }
1502
1503 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1504 {
1505         int port = BP_PORT(bp);
1506         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1507         u32 val = REG_RD(bp, addr);
1508         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1509         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1510         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1511
1512         if (msix) {
1513                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1514                          HC_CONFIG_0_REG_INT_LINE_EN_0);
1515                 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1516                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1517                 if (single_msix)
1518                         val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
1519         } else if (msi) {
1520                 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1521                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1522                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1523                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1524         } else {
1525                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1526                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1527                         HC_CONFIG_0_REG_INT_LINE_EN_0 |
1528                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1529
1530                 if (!CHIP_IS_E1(bp)) {
1531                         DP(NETIF_MSG_IFUP,
1532                            "write %x to HC %d (addr 0x%x)\n", val, port, addr);
1533
1534                         REG_WR(bp, addr, val);
1535
1536                         val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1537                 }
1538         }
1539
1540         if (CHIP_IS_E1(bp))
1541                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1542
1543         DP(NETIF_MSG_IFUP,
1544            "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1545            (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1546
1547         REG_WR(bp, addr, val);
1548         /*
1549          * Ensure that HC_CONFIG is written before leading/trailing edge config
1550          */
1551         mmiowb();
1552         barrier();
1553
1554         if (!CHIP_IS_E1(bp)) {
1555                 /* init leading/trailing edge */
1556                 if (IS_MF(bp)) {
1557                         val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1558                         if (bp->port.pmf)
1559                                 /* enable nig and gpio3 attention */
1560                                 val |= 0x1100;
1561                 } else
1562                         val = 0xffff;
1563
1564                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1565                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1566         }
1567
1568         /* Make sure that interrupts are indeed enabled from here on */
1569         mmiowb();
1570 }
1571
1572 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1573 {
1574         u32 val;
1575         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1576         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1577         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1578
1579         val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1580
1581         if (msix) {
1582                 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1583                          IGU_PF_CONF_SINGLE_ISR_EN);
1584                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1585                         IGU_PF_CONF_ATTN_BIT_EN);
1586
1587                 if (single_msix)
1588                         val |= IGU_PF_CONF_SINGLE_ISR_EN;
1589         } else if (msi) {
1590                 val &= ~IGU_PF_CONF_INT_LINE_EN;
1591                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1592                         IGU_PF_CONF_ATTN_BIT_EN |
1593                         IGU_PF_CONF_SINGLE_ISR_EN);
1594         } else {
1595                 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1596                 val |= (IGU_PF_CONF_INT_LINE_EN |
1597                         IGU_PF_CONF_ATTN_BIT_EN |
1598                         IGU_PF_CONF_SINGLE_ISR_EN);
1599         }
1600
1601         /* Clean previous status - need to configure igu prior to ack*/
1602         if ((!msix) || single_msix) {
1603                 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1604                 bnx2x_ack_int(bp);
1605         }
1606
1607         val |= IGU_PF_CONF_FUNC_EN;
1608
1609         DP(NETIF_MSG_IFUP, "write 0x%x to IGU  mode %s\n",
1610            val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1611
1612         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1613
1614         if (val & IGU_PF_CONF_INT_LINE_EN)
1615                 pci_intx(bp->pdev, true);
1616
1617         barrier();
1618
1619         /* init leading/trailing edge */
1620         if (IS_MF(bp)) {
1621                 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1622                 if (bp->port.pmf)
1623                         /* enable nig and gpio3 attention */
1624                         val |= 0x1100;
1625         } else
1626                 val = 0xffff;
1627
1628         REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1629         REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1630
1631         /* Make sure that interrupts are indeed enabled from here on */
1632         mmiowb();
1633 }
1634
1635 void bnx2x_int_enable(struct bnx2x *bp)
1636 {
1637         if (bp->common.int_block == INT_BLOCK_HC)
1638                 bnx2x_hc_int_enable(bp);
1639         else
1640                 bnx2x_igu_int_enable(bp);
1641 }
1642
1643 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1644 {
1645         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1646         int i, offset;
1647
1648         if (disable_hw)
1649                 /* prevent the HW from sending interrupts */
1650                 bnx2x_int_disable(bp);
1651
1652         /* make sure all ISRs are done */
1653         if (msix) {
1654                 synchronize_irq(bp->msix_table[0].vector);
1655                 offset = 1;
1656                 if (CNIC_SUPPORT(bp))
1657                         offset++;
1658                 for_each_eth_queue(bp, i)
1659                         synchronize_irq(bp->msix_table[offset++].vector);
1660         } else
1661                 synchronize_irq(bp->pdev->irq);
1662
1663         /* make sure sp_task is not running */
1664         cancel_delayed_work(&bp->sp_task);
1665         cancel_delayed_work(&bp->period_task);
1666         flush_workqueue(bnx2x_wq);
1667 }
1668
1669 /* fast path */
1670
1671 /*
1672  * General service functions
1673  */
1674
1675 /* Return true if succeeded to acquire the lock */
1676 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1677 {
1678         u32 lock_status;
1679         u32 resource_bit = (1 << resource);
1680         int func = BP_FUNC(bp);
1681         u32 hw_lock_control_reg;
1682
1683         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1684            "Trying to take a lock on resource %d\n", resource);
1685
1686         /* Validating that the resource is within range */
1687         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1688                 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1689                    "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1690                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1691                 return false;
1692         }
1693
1694         if (func <= 5)
1695                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1696         else
1697                 hw_lock_control_reg =
1698                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1699
1700         /* Try to acquire the lock */
1701         REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1702         lock_status = REG_RD(bp, hw_lock_control_reg);
1703         if (lock_status & resource_bit)
1704                 return true;
1705
1706         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1707            "Failed to get a lock on resource %d\n", resource);
1708         return false;
1709 }
1710
1711 /**
1712  * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1713  *
1714  * @bp: driver handle
1715  *
1716  * Returns the recovery leader resource id according to the engine this function
1717  * belongs to. Currently only only 2 engines is supported.
1718  */
1719 static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1720 {
1721         if (BP_PATH(bp))
1722                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1723         else
1724                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1725 }
1726
1727 /**
1728  * bnx2x_trylock_leader_lock- try to acquire a leader lock.
1729  *
1730  * @bp: driver handle
1731  *
1732  * Tries to acquire a leader lock for current engine.
1733  */
1734 static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1735 {
1736         return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1737 }
1738
1739 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1740
1741 /* schedule the sp task and mark that interrupt occurred (runs from ISR) */
1742 static int bnx2x_schedule_sp_task(struct bnx2x *bp)
1743 {
1744         /* Set the interrupt occurred bit for the sp-task to recognize it
1745          * must ack the interrupt and transition according to the IGU
1746          * state machine.
1747          */
1748         atomic_set(&bp->interrupt_occurred, 1);
1749
1750         /* The sp_task must execute only after this bit
1751          * is set, otherwise we will get out of sync and miss all
1752          * further interrupts. Hence, the barrier.
1753          */
1754         smp_wmb();
1755
1756         /* schedule sp_task to workqueue */
1757         return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1758 }
1759
1760 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1761 {
1762         struct bnx2x *bp = fp->bp;
1763         int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1764         int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1765         enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1766         struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
1767
1768         DP(BNX2X_MSG_SP,
1769            "fp %d  cid %d  got ramrod #%d  state is %x  type is %d\n",
1770            fp->index, cid, command, bp->state,
1771            rr_cqe->ramrod_cqe.ramrod_type);
1772
1773         /* If cid is within VF range, replace the slowpath object with the
1774          * one corresponding to this VF
1775          */
1776         if (cid >= BNX2X_FIRST_VF_CID  &&
1777             cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)
1778                 bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj);
1779
1780         switch (command) {
1781         case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1782                 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
1783                 drv_cmd = BNX2X_Q_CMD_UPDATE;
1784                 break;
1785
1786         case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1787                 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
1788                 drv_cmd = BNX2X_Q_CMD_SETUP;
1789                 break;
1790
1791         case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1792                 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1793                 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1794                 break;
1795
1796         case (RAMROD_CMD_ID_ETH_HALT):
1797                 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
1798                 drv_cmd = BNX2X_Q_CMD_HALT;
1799                 break;
1800
1801         case (RAMROD_CMD_ID_ETH_TERMINATE):
1802                 DP(BNX2X_MSG_SP, "got MULTI[%d] terminate ramrod\n", cid);
1803                 drv_cmd = BNX2X_Q_CMD_TERMINATE;
1804                 break;
1805
1806         case (RAMROD_CMD_ID_ETH_EMPTY):
1807                 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
1808                 drv_cmd = BNX2X_Q_CMD_EMPTY;
1809                 break;
1810
1811         default:
1812                 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1813                           command, fp->index);
1814                 return;
1815         }
1816
1817         if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1818             q_obj->complete_cmd(bp, q_obj, drv_cmd))
1819                 /* q_obj->complete_cmd() failure means that this was
1820                  * an unexpected completion.
1821                  *
1822                  * In this case we don't want to increase the bp->spq_left
1823                  * because apparently we haven't sent this command the first
1824                  * place.
1825                  */
1826 #ifdef BNX2X_STOP_ON_ERROR
1827                 bnx2x_panic();
1828 #else
1829                 return;
1830 #endif
1831         /* SRIOV: reschedule any 'in_progress' operations */
1832         bnx2x_iov_sp_event(bp, cid, true);
1833
1834         smp_mb__before_atomic_inc();
1835         atomic_inc(&bp->cq_spq_left);
1836         /* push the change in bp->spq_left and towards the memory */
1837         smp_mb__after_atomic_inc();
1838
1839         DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1840
1841         if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1842             (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
1843                 /* if Q update ramrod is completed for last Q in AFEX vif set
1844                  * flow, then ACK MCP at the end
1845                  *
1846                  * mark pending ACK to MCP bit.
1847                  * prevent case that both bits are cleared.
1848                  * At the end of load/unload driver checks that
1849                  * sp_state is cleared, and this order prevents
1850                  * races
1851                  */
1852                 smp_mb__before_clear_bit();
1853                 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
1854                 wmb();
1855                 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
1856                 smp_mb__after_clear_bit();
1857
1858                 /* schedule the sp task as mcp ack is required */
1859                 bnx2x_schedule_sp_task(bp);
1860         }
1861
1862         return;
1863 }
1864
1865 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1866 {
1867         struct bnx2x *bp = netdev_priv(dev_instance);
1868         u16 status = bnx2x_ack_int(bp);
1869         u16 mask;
1870         int i;
1871         u8 cos;
1872
1873         /* Return here if interrupt is shared and it's not for us */
1874         if (unlikely(status == 0)) {
1875                 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1876                 return IRQ_NONE;
1877         }
1878         DP(NETIF_MSG_INTR, "got an interrupt  status 0x%x\n", status);
1879
1880 #ifdef BNX2X_STOP_ON_ERROR
1881         if (unlikely(bp->panic))
1882                 return IRQ_HANDLED;
1883 #endif
1884
1885         for_each_eth_queue(bp, i) {
1886                 struct bnx2x_fastpath *fp = &bp->fp[i];
1887
1888                 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp));
1889                 if (status & mask) {
1890                         /* Handle Rx or Tx according to SB id */
1891                         for_each_cos_in_tx_queue(fp, cos)
1892                                 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
1893                         prefetch(&fp->sb_running_index[SM_RX_ID]);
1894                         napi_schedule(&bnx2x_fp(bp, fp->index, napi));
1895                         status &= ~mask;
1896                 }
1897         }
1898
1899         if (CNIC_SUPPORT(bp)) {
1900                 mask = 0x2;
1901                 if (status & (mask | 0x1)) {
1902                         struct cnic_ops *c_ops = NULL;
1903
1904                         rcu_read_lock();
1905                         c_ops = rcu_dereference(bp->cnic_ops);
1906                         if (c_ops && (bp->cnic_eth_dev.drv_state &
1907                                       CNIC_DRV_STATE_HANDLES_IRQ))
1908                                 c_ops->cnic_handler(bp->cnic_data, NULL);
1909                         rcu_read_unlock();
1910
1911                         status &= ~mask;
1912                 }
1913         }
1914
1915         if (unlikely(status & 0x1)) {
1916
1917                 /* schedule sp task to perform default status block work, ack
1918                  * attentions and enable interrupts.
1919                  */
1920                 bnx2x_schedule_sp_task(bp);
1921
1922                 status &= ~0x1;
1923                 if (!status)
1924                         return IRQ_HANDLED;
1925         }
1926
1927         if (unlikely(status))
1928                 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1929                    status);
1930
1931         return IRQ_HANDLED;
1932 }
1933
1934 /* Link */
1935
1936 /*
1937  * General service functions
1938  */
1939
1940 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1941 {
1942         u32 lock_status;
1943         u32 resource_bit = (1 << resource);
1944         int func = BP_FUNC(bp);
1945         u32 hw_lock_control_reg;
1946         int cnt;
1947
1948         /* Validating that the resource is within range */
1949         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1950                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1951                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1952                 return -EINVAL;
1953         }
1954
1955         if (func <= 5) {
1956                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1957         } else {
1958                 hw_lock_control_reg =
1959                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1960         }
1961
1962         /* Validating that the resource is not already taken */
1963         lock_status = REG_RD(bp, hw_lock_control_reg);
1964         if (lock_status & resource_bit) {
1965                 BNX2X_ERR("lock_status 0x%x  resource_bit 0x%x\n",
1966                    lock_status, resource_bit);
1967                 return -EEXIST;
1968         }
1969
1970         /* Try for 5 second every 5ms */
1971         for (cnt = 0; cnt < 1000; cnt++) {
1972                 /* Try to acquire the lock */
1973                 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1974                 lock_status = REG_RD(bp, hw_lock_control_reg);
1975                 if (lock_status & resource_bit)
1976                         return 0;
1977
1978                 usleep_range(5000, 10000);
1979         }
1980         BNX2X_ERR("Timeout\n");
1981         return -EAGAIN;
1982 }
1983
1984 int bnx2x_release_leader_lock(struct bnx2x *bp)
1985 {
1986         return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1987 }
1988
1989 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
1990 {
1991         u32 lock_status;
1992         u32 resource_bit = (1 << resource);
1993         int func = BP_FUNC(bp);
1994         u32 hw_lock_control_reg;
1995
1996         /* Validating that the resource is within range */
1997         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1998                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1999                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
2000                 return -EINVAL;
2001         }
2002
2003         if (func <= 5) {
2004                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
2005         } else {
2006                 hw_lock_control_reg =
2007                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2008         }
2009
2010         /* Validating that the resource is currently taken */
2011         lock_status = REG_RD(bp, hw_lock_control_reg);
2012         if (!(lock_status & resource_bit)) {
2013                 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. Unlock was called but lock wasn't taken!\n",
2014                           lock_status, resource_bit);
2015                 return -EFAULT;
2016         }
2017
2018         REG_WR(bp, hw_lock_control_reg, resource_bit);
2019         return 0;
2020 }
2021
2022 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
2023 {
2024         /* The GPIO should be swapped if swap register is set and active */
2025         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2026                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2027         int gpio_shift = gpio_num +
2028                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2029         u32 gpio_mask = (1 << gpio_shift);
2030         u32 gpio_reg;
2031         int value;
2032
2033         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2034                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2035                 return -EINVAL;
2036         }
2037
2038         /* read GPIO value */
2039         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2040
2041         /* get the requested pin value */
2042         if ((gpio_reg & gpio_mask) == gpio_mask)
2043                 value = 1;
2044         else
2045                 value = 0;
2046
2047         DP(NETIF_MSG_LINK, "pin %d  value 0x%x\n", gpio_num, value);
2048
2049         return value;
2050 }
2051
2052 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2053 {
2054         /* The GPIO should be swapped if swap register is set and active */
2055         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2056                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2057         int gpio_shift = gpio_num +
2058                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2059         u32 gpio_mask = (1 << gpio_shift);
2060         u32 gpio_reg;
2061
2062         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2063                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2064                 return -EINVAL;
2065         }
2066
2067         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2068         /* read GPIO and mask except the float bits */
2069         gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
2070
2071         switch (mode) {
2072         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2073                 DP(NETIF_MSG_LINK,
2074                    "Set GPIO %d (shift %d) -> output low\n",
2075                    gpio_num, gpio_shift);
2076                 /* clear FLOAT and set CLR */
2077                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2078                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
2079                 break;
2080
2081         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2082                 DP(NETIF_MSG_LINK,
2083                    "Set GPIO %d (shift %d) -> output high\n",
2084                    gpio_num, gpio_shift);
2085                 /* clear FLOAT and set SET */
2086                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2087                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
2088                 break;
2089
2090         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2091                 DP(NETIF_MSG_LINK,
2092                    "Set GPIO %d (shift %d) -> input\n",
2093                    gpio_num, gpio_shift);
2094                 /* set FLOAT */
2095                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2096                 break;
2097
2098         default:
2099                 break;
2100         }
2101
2102         REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2103         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2104
2105         return 0;
2106 }
2107
2108 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
2109 {
2110         u32 gpio_reg = 0;
2111         int rc = 0;
2112
2113         /* Any port swapping should be handled by caller. */
2114
2115         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2116         /* read GPIO and mask except the float bits */
2117         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2118         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2119         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
2120         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
2121
2122         switch (mode) {
2123         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2124                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2125                 /* set CLR */
2126                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2127                 break;
2128
2129         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2130                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2131                 /* set SET */
2132                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2133                 break;
2134
2135         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2136                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2137                 /* set FLOAT */
2138                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2139                 break;
2140
2141         default:
2142                 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2143                 rc = -EINVAL;
2144                 break;
2145         }
2146
2147         if (rc == 0)
2148                 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2149
2150         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2151
2152         return rc;
2153 }
2154
2155 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2156 {
2157         /* The GPIO should be swapped if swap register is set and active */
2158         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2159                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2160         int gpio_shift = gpio_num +
2161                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2162         u32 gpio_mask = (1 << gpio_shift);
2163         u32 gpio_reg;
2164
2165         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2166                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2167                 return -EINVAL;
2168         }
2169
2170         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2171         /* read GPIO int */
2172         gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2173
2174         switch (mode) {
2175         case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2176                 DP(NETIF_MSG_LINK,
2177                    "Clear GPIO INT %d (shift %d) -> output low\n",
2178                    gpio_num, gpio_shift);
2179                 /* clear SET and set CLR */
2180                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2181                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2182                 break;
2183
2184         case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2185                 DP(NETIF_MSG_LINK,
2186                    "Set GPIO INT %d (shift %d) -> output high\n",
2187                    gpio_num, gpio_shift);
2188                 /* clear CLR and set SET */
2189                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2190                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2191                 break;
2192
2193         default:
2194                 break;
2195         }
2196
2197         REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2198         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2199
2200         return 0;
2201 }
2202
2203 static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode)
2204 {
2205         u32 spio_reg;
2206
2207         /* Only 2 SPIOs are configurable */
2208         if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
2209                 BNX2X_ERR("Invalid SPIO 0x%x\n", spio);
2210                 return -EINVAL;
2211         }
2212
2213         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2214         /* read SPIO and mask except the float bits */
2215         spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
2216
2217         switch (mode) {
2218         case MISC_SPIO_OUTPUT_LOW:
2219                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio);
2220                 /* clear FLOAT and set CLR */
2221                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2222                 spio_reg |=  (spio << MISC_SPIO_CLR_POS);
2223                 break;
2224
2225         case MISC_SPIO_OUTPUT_HIGH:
2226                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio);
2227                 /* clear FLOAT and set SET */
2228                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2229                 spio_reg |=  (spio << MISC_SPIO_SET_POS);
2230                 break;
2231
2232         case MISC_SPIO_INPUT_HI_Z:
2233                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio);
2234                 /* set FLOAT */
2235                 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
2236                 break;
2237
2238         default:
2239                 break;
2240         }
2241
2242         REG_WR(bp, MISC_REG_SPIO, spio_reg);
2243         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2244
2245         return 0;
2246 }
2247
2248 void bnx2x_calc_fc_adv(struct bnx2x *bp)
2249 {
2250         u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2251         switch (bp->link_vars.ieee_fc &
2252                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2253         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
2254                 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2255                                                    ADVERTISED_Pause);
2256                 break;
2257
2258         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2259                 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2260                                                   ADVERTISED_Pause);
2261                 break;
2262
2263         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2264                 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2265                 break;
2266
2267         default:
2268                 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2269                                                    ADVERTISED_Pause);
2270                 break;
2271         }
2272 }
2273
2274 static void bnx2x_set_requested_fc(struct bnx2x *bp)
2275 {
2276         /* Initialize link parameters structure variables
2277          * It is recommended to turn off RX FC for jumbo frames
2278          *  for better performance
2279          */
2280         if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2281                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2282         else
2283                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2284 }
2285
2286 static void bnx2x_init_dropless_fc(struct bnx2x *bp)
2287 {
2288         u32 pause_enabled = 0;
2289
2290         if (!CHIP_IS_E1(bp) && bp->dropless_fc && bp->link_vars.link_up) {
2291                 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2292                         pause_enabled = 1;
2293
2294                 REG_WR(bp, BAR_USTRORM_INTMEM +
2295                            USTORM_ETH_PAUSE_ENABLED_OFFSET(BP_PORT(bp)),
2296                        pause_enabled);
2297         }
2298
2299         DP(NETIF_MSG_IFUP | NETIF_MSG_LINK, "dropless_fc is %s\n",
2300            pause_enabled ? "enabled" : "disabled");
2301 }
2302
2303 int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2304 {
2305         int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp);
2306         u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2307
2308         if (!BP_NOMCP(bp)) {
2309                 bnx2x_set_requested_fc(bp);
2310                 bnx2x_acquire_phy_lock(bp);
2311
2312                 if (load_mode == LOAD_DIAG) {
2313                         struct link_params *lp = &bp->link_params;
2314                         lp->loopback_mode = LOOPBACK_XGXS;
2315                         /* do PHY loopback at 10G speed, if possible */
2316                         if (lp->req_line_speed[cfx_idx] < SPEED_10000) {
2317                                 if (lp->speed_cap_mask[cfx_idx] &
2318                                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2319                                         lp->req_line_speed[cfx_idx] =
2320                                         SPEED_10000;
2321                                 else
2322                                         lp->req_line_speed[cfx_idx] =
2323                                         SPEED_1000;
2324                         }
2325                 }
2326
2327                 if (load_mode == LOAD_LOOPBACK_EXT) {
2328                         struct link_params *lp = &bp->link_params;
2329                         lp->loopback_mode = LOOPBACK_EXT;
2330                 }
2331
2332                 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2333
2334                 bnx2x_release_phy_lock(bp);
2335
2336                 bnx2x_init_dropless_fc(bp);
2337
2338                 bnx2x_calc_fc_adv(bp);
2339
2340                 if (bp->link_vars.link_up) {
2341                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2342                         bnx2x_link_report(bp);
2343                 }
2344                 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2345                 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2346                 return rc;
2347         }
2348         BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2349         return -EINVAL;
2350 }
2351
2352 void bnx2x_link_set(struct bnx2x *bp)
2353 {
2354         if (!BP_NOMCP(bp)) {
2355                 bnx2x_acquire_phy_lock(bp);
2356                 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2357                 bnx2x_release_phy_lock(bp);
2358
2359                 bnx2x_init_dropless_fc(bp);
2360
2361                 bnx2x_calc_fc_adv(bp);
2362         } else
2363                 BNX2X_ERR("Bootcode is missing - can not set link\n");
2364 }
2365
2366 static void bnx2x__link_reset(struct bnx2x *bp)
2367 {
2368         if (!BP_NOMCP(bp)) {
2369                 bnx2x_acquire_phy_lock(bp);
2370                 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars);
2371                 bnx2x_release_phy_lock(bp);
2372         } else
2373                 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2374 }
2375
2376 void bnx2x_force_link_reset(struct bnx2x *bp)
2377 {
2378         bnx2x_acquire_phy_lock(bp);
2379         bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2380         bnx2x_release_phy_lock(bp);
2381 }
2382
2383 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2384 {
2385         u8 rc = 0;
2386
2387         if (!BP_NOMCP(bp)) {
2388                 bnx2x_acquire_phy_lock(bp);
2389                 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2390                                      is_serdes);
2391                 bnx2x_release_phy_lock(bp);
2392         } else
2393                 BNX2X_ERR("Bootcode is missing - can not test link\n");
2394
2395         return rc;
2396 }
2397
2398 /* Calculates the sum of vn_min_rates.
2399    It's needed for further normalizing of the min_rates.
2400    Returns:
2401      sum of vn_min_rates.
2402        or
2403      0 - if all the min_rates are 0.
2404      In the later case fairness algorithm should be deactivated.
2405      If not all min_rates are zero then those that are zeroes will be set to 1.
2406  */
2407 static void bnx2x_calc_vn_min(struct bnx2x *bp,
2408                                       struct cmng_init_input *input)
2409 {
2410         int all_zero = 1;
2411         int vn;
2412
2413         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2414                 u32 vn_cfg = bp->mf_config[vn];
2415                 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2416                                    FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2417
2418                 /* Skip hidden vns */
2419                 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2420                         vn_min_rate = 0;
2421                 /* If min rate is zero - set it to 1 */
2422                 else if (!vn_min_rate)
2423                         vn_min_rate = DEF_MIN_RATE;
2424                 else
2425                         all_zero = 0;
2426
2427                 input->vnic_min_rate[vn] = vn_min_rate;
2428         }
2429
2430         /* if ETS or all min rates are zeros - disable fairness */
2431         if (BNX2X_IS_ETS_ENABLED(bp)) {
2432                 input->flags.cmng_enables &=
2433                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2434                 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2435         } else if (all_zero) {
2436                 input->flags.cmng_enables &=
2437                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2438                 DP(NETIF_MSG_IFUP,
2439                    "All MIN values are zeroes fairness will be disabled\n");
2440         } else
2441                 input->flags.cmng_enables |=
2442                                         CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2443 }
2444
2445 static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2446                                     struct cmng_init_input *input)
2447 {
2448         u16 vn_max_rate;
2449         u32 vn_cfg = bp->mf_config[vn];
2450
2451         if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2452                 vn_max_rate = 0;
2453         else {
2454                 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2455
2456                 if (IS_MF_SI(bp)) {
2457                         /* maxCfg in percents of linkspeed */
2458                         vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2459                 } else /* SD modes */
2460                         /* maxCfg is absolute in 100Mb units */
2461                         vn_max_rate = maxCfg * 100;
2462         }
2463
2464         DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
2465
2466         input->vnic_max_rate[vn] = vn_max_rate;
2467 }
2468
2469 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2470 {
2471         if (CHIP_REV_IS_SLOW(bp))
2472                 return CMNG_FNS_NONE;
2473         if (IS_MF(bp))
2474                 return CMNG_FNS_MINMAX;
2475
2476         return CMNG_FNS_NONE;
2477 }
2478
2479 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2480 {
2481         int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2482
2483         if (BP_NOMCP(bp))
2484                 return; /* what should be the default value in this case */
2485
2486         /* For 2 port configuration the absolute function number formula
2487          * is:
2488          *      abs_func = 2 * vn + BP_PORT + BP_PATH
2489          *
2490          *      and there are 4 functions per port
2491          *
2492          * For 4 port configuration it is
2493          *      abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2494          *
2495          *      and there are 2 functions per port
2496          */
2497         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2498                 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2499
2500                 if (func >= E1H_FUNC_MAX)
2501                         break;
2502
2503                 bp->mf_config[vn] =
2504                         MF_CFG_RD(bp, func_mf_config[func].config);
2505         }
2506         if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2507                 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2508                 bp->flags |= MF_FUNC_DIS;
2509         } else {
2510                 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2511                 bp->flags &= ~MF_FUNC_DIS;
2512         }
2513 }
2514
2515 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2516 {
2517         struct cmng_init_input input;
2518         memset(&input, 0, sizeof(struct cmng_init_input));
2519
2520         input.port_rate = bp->link_vars.line_speed;
2521
2522         if (cmng_type == CMNG_FNS_MINMAX && input.port_rate) {
2523                 int vn;
2524
2525                 /* read mf conf from shmem */
2526                 if (read_cfg)
2527                         bnx2x_read_mf_cfg(bp);
2528
2529                 /* vn_weight_sum and enable fairness if not 0 */
2530                 bnx2x_calc_vn_min(bp, &input);
2531
2532                 /* calculate and set min-max rate for each vn */
2533                 if (bp->port.pmf)
2534                         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
2535                                 bnx2x_calc_vn_max(bp, vn, &input);
2536
2537                 /* always enable rate shaping and fairness */
2538                 input.flags.cmng_enables |=
2539                                         CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2540
2541                 bnx2x_init_cmng(&input, &bp->cmng);
2542                 return;
2543         }
2544
2545         /* rate shaping and fairness are disabled */
2546         DP(NETIF_MSG_IFUP,
2547            "rate shaping and fairness are disabled\n");
2548 }
2549
2550 static void storm_memset_cmng(struct bnx2x *bp,
2551                               struct cmng_init *cmng,
2552                               u8 port)
2553 {
2554         int vn;
2555         size_t size = sizeof(struct cmng_struct_per_port);
2556
2557         u32 addr = BAR_XSTRORM_INTMEM +
2558                         XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
2559
2560         __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2561
2562         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2563                 int func = func_by_vn(bp, vn);
2564
2565                 addr = BAR_XSTRORM_INTMEM +
2566                        XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
2567                 size = sizeof(struct rate_shaping_vars_per_vn);
2568                 __storm_memset_struct(bp, addr, size,
2569                                       (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2570
2571                 addr = BAR_XSTRORM_INTMEM +
2572                        XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
2573                 size = sizeof(struct fairness_vars_per_vn);
2574                 __storm_memset_struct(bp, addr, size,
2575                                       (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2576         }
2577 }
2578
2579 /* init cmng mode in HW according to local configuration */
2580 void bnx2x_set_local_cmng(struct bnx2x *bp)
2581 {
2582         int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2583
2584         if (cmng_fns != CMNG_FNS_NONE) {
2585                 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2586                 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2587         } else {
2588                 /* rate shaping and fairness are disabled */
2589                 DP(NETIF_MSG_IFUP,
2590                    "single function mode without fairness\n");
2591         }
2592 }
2593
2594 /* This function is called upon link interrupt */
2595 static void bnx2x_link_attn(struct bnx2x *bp)
2596 {
2597         /* Make sure that we are synced with the current statistics */
2598         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2599
2600         bnx2x_link_update(&bp->link_params, &bp->link_vars);
2601
2602         bnx2x_init_dropless_fc(bp);
2603
2604         if (bp->link_vars.link_up) {
2605
2606                 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2607                         struct host_port_stats *pstats;
2608
2609                         pstats = bnx2x_sp(bp, port_stats);
2610                         /* reset old mac stats */
2611                         memset(&(pstats->mac_stx[0]), 0,
2612                                sizeof(struct mac_stx));
2613                 }
2614                 if (bp->state == BNX2X_STATE_OPEN)
2615                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2616         }
2617
2618         if (bp->link_vars.link_up && bp->link_vars.line_speed)
2619                 bnx2x_set_local_cmng(bp);
2620
2621         __bnx2x_link_report(bp);
2622
2623         if (IS_MF(bp))
2624                 bnx2x_link_sync_notify(bp);
2625 }
2626
2627 void bnx2x__link_status_update(struct bnx2x *bp)
2628 {
2629         if (bp->state != BNX2X_STATE_OPEN)
2630                 return;
2631
2632         /* read updated dcb configuration */
2633         if (IS_PF(bp)) {
2634                 bnx2x_dcbx_pmf_update(bp);
2635                 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2636                 if (bp->link_vars.link_up)
2637                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2638                 else
2639                         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2640                         /* indicate link status */
2641                 bnx2x_link_report(bp);
2642
2643         } else { /* VF */
2644                 bp->port.supported[0] |= (SUPPORTED_10baseT_Half |
2645                                           SUPPORTED_10baseT_Full |
2646                                           SUPPORTED_100baseT_Half |
2647                                           SUPPORTED_100baseT_Full |
2648                                           SUPPORTED_1000baseT_Full |
2649                                           SUPPORTED_2500baseX_Full |
2650                                           SUPPORTED_10000baseT_Full |
2651                                           SUPPORTED_TP |
2652                                           SUPPORTED_FIBRE |
2653                                           SUPPORTED_Autoneg |
2654                                           SUPPORTED_Pause |
2655                                           SUPPORTED_Asym_Pause);
2656                 bp->port.advertising[0] = bp->port.supported[0];
2657
2658                 bp->link_params.bp = bp;
2659                 bp->link_params.port = BP_PORT(bp);
2660                 bp->link_params.req_duplex[0] = DUPLEX_FULL;
2661                 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE;
2662                 bp->link_params.req_line_speed[0] = SPEED_10000;
2663                 bp->link_params.speed_cap_mask[0] = 0x7f0000;
2664                 bp->link_params.switch_cfg = SWITCH_CFG_10G;
2665                 bp->link_vars.mac_type = MAC_TYPE_BMAC;
2666                 bp->link_vars.line_speed = SPEED_10000;
2667                 bp->link_vars.link_status =
2668                         (LINK_STATUS_LINK_UP |
2669                          LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
2670                 bp->link_vars.link_up = 1;
2671                 bp->link_vars.duplex = DUPLEX_FULL;
2672                 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2673                 __bnx2x_link_report(bp);
2674                 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2675         }
2676 }
2677
2678 static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2679                                   u16 vlan_val, u8 allowed_prio)
2680 {
2681         struct bnx2x_func_state_params func_params = {NULL};
2682         struct bnx2x_func_afex_update_params *f_update_params =
2683                 &func_params.params.afex_update;
2684
2685         func_params.f_obj = &bp->func_obj;
2686         func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2687
2688         /* no need to wait for RAMROD completion, so don't
2689          * set RAMROD_COMP_WAIT flag
2690          */
2691
2692         f_update_params->vif_id = vifid;
2693         f_update_params->afex_default_vlan = vlan_val;
2694         f_update_params->allowed_priorities = allowed_prio;
2695
2696         /* if ramrod can not be sent, response to MCP immediately */
2697         if (bnx2x_func_state_change(bp, &func_params) < 0)
2698                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
2699
2700         return 0;
2701 }
2702
2703 static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2704                                           u16 vif_index, u8 func_bit_map)
2705 {
2706         struct bnx2x_func_state_params func_params = {NULL};
2707         struct bnx2x_func_afex_viflists_params *update_params =
2708                 &func_params.params.afex_viflists;
2709         int rc;
2710         u32 drv_msg_code;
2711
2712         /* validate only LIST_SET and LIST_GET are received from switch */
2713         if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2714                 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2715                           cmd_type);
2716
2717         func_params.f_obj = &bp->func_obj;
2718         func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2719
2720         /* set parameters according to cmd_type */
2721         update_params->afex_vif_list_command = cmd_type;
2722         update_params->vif_list_index = vif_index;
2723         update_params->func_bit_map =
2724                 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2725         update_params->func_to_clear = 0;
2726         drv_msg_code =
2727                 (cmd_type == VIF_LIST_RULE_GET) ?
2728                 DRV_MSG_CODE_AFEX_LISTGET_ACK :
2729                 DRV_MSG_CODE_AFEX_LISTSET_ACK;
2730
2731         /* if ramrod can not be sent, respond to MCP immediately for
2732          * SET and GET requests (other are not triggered from MCP)
2733          */
2734         rc = bnx2x_func_state_change(bp, &func_params);
2735         if (rc < 0)
2736                 bnx2x_fw_command(bp, drv_msg_code, 0);
2737
2738         return 0;
2739 }
2740
2741 static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2742 {
2743         struct afex_stats afex_stats;
2744         u32 func = BP_ABS_FUNC(bp);
2745         u32 mf_config;
2746         u16 vlan_val;
2747         u32 vlan_prio;
2748         u16 vif_id;
2749         u8 allowed_prio;
2750         u8 vlan_mode;
2751         u32 addr_to_write, vifid, addrs, stats_type, i;
2752
2753         if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2754                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2755                 DP(BNX2X_MSG_MCP,
2756                    "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2757                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2758         }
2759
2760         if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2761                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2762                 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2763                 DP(BNX2X_MSG_MCP,
2764                    "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2765                    vifid, addrs);
2766                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2767                                                addrs);
2768         }
2769
2770         if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2771                 addr_to_write = SHMEM2_RD(bp,
2772                         afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2773                 stats_type = SHMEM2_RD(bp,
2774                         afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2775
2776                 DP(BNX2X_MSG_MCP,
2777                    "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2778                    addr_to_write);
2779
2780                 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2781
2782                 /* write response to scratchpad, for MCP */
2783                 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2784                         REG_WR(bp, addr_to_write + i*sizeof(u32),
2785                                *(((u32 *)(&afex_stats))+i));
2786
2787                 /* send ack message to MCP */
2788                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
2789         }
2790
2791         if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2792                 mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2793                 bp->mf_config[BP_VN(bp)] = mf_config;
2794                 DP(BNX2X_MSG_MCP,
2795                    "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2796                    mf_config);
2797
2798                 /* if VIF_SET is "enabled" */
2799                 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2800                         /* set rate limit directly to internal RAM */
2801                         struct cmng_init_input cmng_input;
2802                         struct rate_shaping_vars_per_vn m_rs_vn;
2803                         size_t size = sizeof(struct rate_shaping_vars_per_vn);
2804                         u32 addr = BAR_XSTRORM_INTMEM +
2805                             XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
2806
2807                         bp->mf_config[BP_VN(bp)] = mf_config;
2808
2809                         bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2810                         m_rs_vn.vn_counter.rate =
2811                                 cmng_input.vnic_max_rate[BP_VN(bp)];
2812                         m_rs_vn.vn_counter.quota =
2813                                 (m_rs_vn.vn_counter.rate *
2814                                  RS_PERIODIC_TIMEOUT_USEC) / 8;
2815
2816                         __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2817
2818                         /* read relevant values from mf_cfg struct in shmem */
2819                         vif_id =
2820                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2821                                  FUNC_MF_CFG_E1HOV_TAG_MASK) >>
2822                                 FUNC_MF_CFG_E1HOV_TAG_SHIFT;
2823                         vlan_val =
2824                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2825                                  FUNC_MF_CFG_AFEX_VLAN_MASK) >>
2826                                 FUNC_MF_CFG_AFEX_VLAN_SHIFT;
2827                         vlan_prio = (mf_config &
2828                                      FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
2829                                     FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
2830                         vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2831                         vlan_mode =
2832                                 (MF_CFG_RD(bp,
2833                                            func_mf_config[func].afex_config) &
2834                                  FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
2835                                 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
2836                         allowed_prio =
2837                                 (MF_CFG_RD(bp,
2838                                            func_mf_config[func].afex_config) &
2839                                  FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
2840                                 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
2841
2842                         /* send ramrod to FW, return in case of failure */
2843                         if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2844                                                    allowed_prio))
2845                                 return;
2846
2847                         bp->afex_def_vlan_tag = vlan_val;
2848                         bp->afex_vlan_mode = vlan_mode;
2849                 } else {
2850                         /* notify link down because BP->flags is disabled */
2851                         bnx2x_link_report(bp);
2852
2853                         /* send INVALID VIF ramrod to FW */
2854                         bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2855
2856                         /* Reset the default afex VLAN */
2857                         bp->afex_def_vlan_tag = -1;
2858                 }
2859         }
2860 }
2861
2862 static void bnx2x_pmf_update(struct bnx2x *bp)
2863 {
2864         int port = BP_PORT(bp);
2865         u32 val;
2866
2867         bp->port.pmf = 1;
2868         DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
2869
2870         /*
2871          * We need the mb() to ensure the ordering between the writing to
2872          * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2873          */
2874         smp_mb();
2875
2876         /* queue a periodic task */
2877         queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2878
2879         bnx2x_dcbx_pmf_update(bp);
2880
2881         /* enable nig attention */
2882         val = (0xff0f | (1 << (BP_VN(bp) + 4)));
2883         if (bp->common.int_block == INT_BLOCK_HC) {
2884                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2885                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2886         } else if (!CHIP_IS_E1x(bp)) {
2887                 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2888                 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2889         }
2890
2891         bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2892 }
2893
2894 /* end of Link */
2895
2896 /* slow path */
2897
2898 /*
2899  * General service functions
2900  */
2901
2902 /* send the MCP a request, block until there is a reply */
2903 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2904 {
2905         int mb_idx = BP_FW_MB_IDX(bp);
2906         u32 seq;
2907         u32 rc = 0;
2908         u32 cnt = 1;
2909         u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2910
2911         mutex_lock(&bp->fw_mb_mutex);
2912         seq = ++bp->fw_seq;
2913         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2914         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2915
2916         DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
2917                         (command | seq), param);
2918
2919         do {
2920                 /* let the FW do it's magic ... */
2921                 msleep(delay);
2922
2923                 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2924
2925                 /* Give the FW up to 5 second (500*10ms) */
2926         } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2927
2928         DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2929            cnt*delay, rc, seq);
2930
2931         /* is this a reply to our command? */
2932         if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2933                 rc &= FW_MSG_CODE_MASK;
2934         else {
2935                 /* FW BUG! */
2936                 BNX2X_ERR("FW failed to respond!\n");
2937                 bnx2x_fw_dump(bp);
2938                 rc = 0;
2939         }
2940         mutex_unlock(&bp->fw_mb_mutex);
2941
2942         return rc;
2943 }
2944
2945 static void storm_memset_func_cfg(struct bnx2x *bp,
2946                                  struct tstorm_eth_function_common_config *tcfg,
2947                                  u16 abs_fid)
2948 {
2949         size_t size = sizeof(struct tstorm_eth_function_common_config);
2950
2951         u32 addr = BAR_TSTRORM_INTMEM +
2952                         TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
2953
2954         __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
2955 }
2956
2957 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2958 {
2959         if (CHIP_IS_E1x(bp)) {
2960                 struct tstorm_eth_function_common_config tcfg = {0};
2961
2962                 storm_memset_func_cfg(bp, &tcfg, p->func_id);
2963         }
2964
2965         /* Enable the function in the FW */
2966         storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2967         storm_memset_func_en(bp, p->func_id, 1);
2968
2969         /* spq */
2970         if (p->func_flgs & FUNC_FLG_SPQ) {
2971                 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
2972                 REG_WR(bp, XSEM_REG_FAST_MEMORY +
2973                        XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
2974         }
2975 }
2976
2977 /**
2978  * bnx2x_get_common_flags - Return common flags
2979  *
2980  * @bp          device handle
2981  * @fp          queue handle
2982  * @zero_stats  TRUE if statistics zeroing is needed
2983  *
2984  * Return the flags that are common for the Tx-only and not normal connections.
2985  */
2986 static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
2987                                             struct bnx2x_fastpath *fp,
2988                                             bool zero_stats)
2989 {
2990         unsigned long flags = 0;
2991
2992         /* PF driver will always initialize the Queue to an ACTIVE state */
2993         __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
2994
2995         /* tx only connections collect statistics (on the same index as the
2996          * parent connection). The statistics are zeroed when the parent
2997          * connection is initialized.
2998          */
2999
3000         __set_bit(BNX2X_Q_FLG_STATS, &flags);
3001         if (zero_stats)
3002                 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
3003
3004         __set_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, &flags);
3005         __set_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, &flags);
3006
3007 #ifdef BNX2X_STOP_ON_ERROR
3008         __set_bit(BNX2X_Q_FLG_TX_SEC, &flags);
3009 #endif
3010
3011         return flags;
3012 }
3013
3014 static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
3015                                        struct bnx2x_fastpath *fp,
3016                                        bool leading)
3017 {
3018         unsigned long flags = 0;
3019
3020         /* calculate other queue flags */
3021         if (IS_MF_SD(bp))
3022                 __set_bit(BNX2X_Q_FLG_OV, &flags);
3023
3024         if (IS_FCOE_FP(fp)) {
3025                 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
3026                 /* For FCoE - force usage of default priority (for afex) */
3027                 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
3028         }
3029
3030         if (!fp->disable_tpa) {
3031                 __set_bit(BNX2X_Q_FLG_TPA, &flags);
3032                 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
3033                 if (fp->mode == TPA_MODE_GRO)
3034                         __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
3035         }
3036
3037         if (leading) {
3038                 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
3039                 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
3040         }
3041
3042         /* Always set HW VLAN stripping */
3043         __set_bit(BNX2X_Q_FLG_VLAN, &flags);
3044
3045         /* configure silent vlan removal */
3046         if (IS_MF_AFEX(bp))
3047                 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
3048
3049         return flags | bnx2x_get_common_flags(bp, fp, true);
3050 }
3051
3052 static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
3053         struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
3054         u8 cos)
3055 {
3056         gen_init->stat_id = bnx2x_stats_id(fp);
3057         gen_init->spcl_id = fp->cl_id;
3058
3059         /* Always use mini-jumbo MTU for FCoE L2 ring */
3060         if (IS_FCOE_FP(fp))
3061                 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
3062         else
3063                 gen_init->mtu = bp->dev->mtu;
3064
3065         gen_init->cos = cos;
3066 }
3067
3068 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
3069         struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
3070         struct bnx2x_rxq_setup_params *rxq_init)
3071 {
3072         u8 max_sge = 0;
3073         u16 sge_sz = 0;
3074         u16 tpa_agg_size = 0;
3075
3076         if (!fp->disable_tpa) {
3077                 pause->sge_th_lo = SGE_TH_LO(bp);
3078                 pause->sge_th_hi = SGE_TH_HI(bp);
3079
3080                 /* validate SGE ring has enough to cross high threshold */
3081                 WARN_ON(bp->dropless_fc &&
3082                                 pause->sge_th_hi + FW_PREFETCH_CNT >
3083                                 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
3084
3085                 tpa_agg_size = TPA_AGG_SIZE;
3086                 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
3087                         SGE_PAGE_SHIFT;
3088                 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
3089                           (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
3090                 sge_sz = (u16)min_t(u32, SGE_PAGES, 0xffff);
3091         }
3092
3093         /* pause - not for e1 */
3094         if (!CHIP_IS_E1(bp)) {
3095                 pause->bd_th_lo = BD_TH_LO(bp);
3096                 pause->bd_th_hi = BD_TH_HI(bp);
3097
3098                 pause->rcq_th_lo = RCQ_TH_LO(bp);
3099                 pause->rcq_th_hi = RCQ_TH_HI(bp);
3100                 /*
3101                  * validate that rings have enough entries to cross
3102                  * high thresholds
3103                  */
3104                 WARN_ON(bp->dropless_fc &&
3105                                 pause->bd_th_hi + FW_PREFETCH_CNT >
3106                                 bp->rx_ring_size);
3107                 WARN_ON(bp->dropless_fc &&
3108                                 pause->rcq_th_hi + FW_PREFETCH_CNT >
3109                                 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
3110
3111                 pause->pri_map = 1;
3112         }
3113
3114         /* rxq setup */
3115         rxq_init->dscr_map = fp->rx_desc_mapping;
3116         rxq_init->sge_map = fp->rx_sge_mapping;
3117         rxq_init->rcq_map = fp->rx_comp_mapping;
3118         rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
3119
3120         /* This should be a maximum number of data bytes that may be
3121          * placed on the BD (not including paddings).
3122          */
3123         rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
3124                            BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
3125
3126         rxq_init->cl_qzone_id = fp->cl_qzone_id;
3127         rxq_init->tpa_agg_sz = tpa_agg_size;
3128         rxq_init->sge_buf_sz = sge_sz;
3129         rxq_init->max_sges_pkt = max_sge;
3130         rxq_init->rss_engine_id = BP_FUNC(bp);
3131         rxq_init->mcast_engine_id = BP_FUNC(bp);
3132
3133         /* Maximum number or simultaneous TPA aggregation for this Queue.
3134          *
3135          * For PF Clients it should be the maximum available number.
3136          * VF driver(s) may want to define it to a smaller value.
3137          */
3138         rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
3139
3140         rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
3141         rxq_init->fw_sb_id = fp->fw_sb_id;
3142
3143         if (IS_FCOE_FP(fp))
3144                 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
3145         else
3146                 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
3147         /* configure silent vlan removal
3148          * if multi function mode is afex, then mask default vlan
3149          */
3150         if (IS_MF_AFEX(bp)) {
3151                 rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
3152                 rxq_init->silent_removal_mask = VLAN_VID_MASK;
3153         }
3154 }
3155
3156 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
3157         struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
3158         u8 cos)
3159 {
3160         txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
3161         txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
3162         txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
3163         txq_init->fw_sb_id = fp->fw_sb_id;
3164
3165         /*
3166          * set the tss leading client id for TX classification ==
3167          * leading RSS client id
3168          */
3169         txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
3170
3171         if (IS_FCOE_FP(fp)) {
3172                 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
3173                 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
3174         }
3175 }
3176
3177 static void bnx2x_pf_init(struct bnx2x *bp)
3178 {
3179         struct bnx2x_func_init_params func_init = {0};
3180         struct event_ring_data eq_data = { {0} };
3181         u16 flags;
3182
3183         if (!CHIP_IS_E1x(bp)) {
3184                 /* reset IGU PF statistics: MSIX + ATTN */
3185                 /* PF */
3186                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3187                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3188                            (CHIP_MODE_IS_4_PORT(bp) ?
3189                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3190                 /* ATTN */
3191                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3192                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3193                            BNX2X_IGU_STAS_MSG_PF_CNT*4 +
3194                            (CHIP_MODE_IS_4_PORT(bp) ?
3195                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3196         }
3197
3198         /* function setup flags */
3199         flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
3200
3201         /* This flag is relevant for E1x only.
3202          * E2 doesn't have a TPA configuration in a function level.
3203          */
3204         flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
3205
3206         func_init.func_flgs = flags;
3207         func_init.pf_id = BP_FUNC(bp);
3208         func_init.func_id = BP_FUNC(bp);
3209         func_init.spq_map = bp->spq_mapping;
3210         func_init.spq_prod = bp->spq_prod_idx;
3211
3212         bnx2x_func_init(bp, &func_init);
3213
3214         memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
3215
3216         /*
3217          * Congestion management values depend on the link rate
3218          * There is no active link so initial link rate is set to 10 Gbps.
3219          * When the link comes up The congestion management values are
3220          * re-calculated according to the actual link rate.
3221          */
3222         bp->link_vars.line_speed = SPEED_10000;
3223         bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
3224
3225         /* Only the PMF sets the HW */
3226         if (bp->port.pmf)
3227                 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3228
3229         /* init Event Queue - PCI bus guarantees correct endianity*/
3230         eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
3231         eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
3232         eq_data.producer = bp->eq_prod;
3233         eq_data.index_id = HC_SP_INDEX_EQ_CONS;
3234         eq_data.sb_id = DEF_SB_ID;
3235         storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3236 }
3237
3238 static void bnx2x_e1h_disable(struct bnx2x *bp)
3239 {
3240         int port = BP_PORT(bp);
3241
3242         bnx2x_tx_disable(bp);
3243
3244         REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
3245 }
3246
3247 static void bnx2x_e1h_enable(struct bnx2x *bp)
3248 {
3249         int port = BP_PORT(bp);
3250
3251         REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
3252
3253         /* Tx queue should be only re-enabled */
3254         netif_tx_wake_all_queues(bp->dev);
3255
3256         /*
3257          * Should not call netif_carrier_on since it will be called if the link
3258          * is up when checking for link state
3259          */
3260 }
3261
3262 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3263
3264 static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3265 {
3266         struct eth_stats_info *ether_stat =
3267                 &bp->slowpath->drv_info_to_mcp.ether_stat;
3268         struct bnx2x_vlan_mac_obj *mac_obj =
3269                 &bp->sp_objs->mac_obj;
3270         int i;
3271
3272         strlcpy(ether_stat->version, DRV_MODULE_VERSION,
3273                 ETH_STAT_INFO_VERSION_LEN);
3274
3275         /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the
3276          * mac_local field in ether_stat struct. The base address is offset by 2
3277          * bytes to account for the field being 8 bytes but a mac address is
3278          * only 6 bytes. Likewise, the stride for the get_n_elements function is
3279          * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes
3280          * allocated by the ether_stat struct, so the macs will land in their
3281          * proper positions.
3282          */
3283         for (i = 0; i < DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED; i++)
3284                 memset(ether_stat->mac_local + i, 0,
3285                        sizeof(ether_stat->mac_local[0]));
3286         mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3287                                 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3288                                 ether_stat->mac_local + MAC_PAD, MAC_PAD,
3289                                 ETH_ALEN);
3290         ether_stat->mtu_size = bp->dev->mtu;
3291         if (bp->dev->features & NETIF_F_RXCSUM)
3292                 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3293         if (bp->dev->features & NETIF_F_TSO)
3294                 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3295         ether_stat->feature_flags |= bp->common.boot_mode;
3296
3297         ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3298
3299         ether_stat->txq_size = bp->tx_ring_size;
3300         ether_stat->rxq_size = bp->rx_ring_size;
3301 }
3302
3303 static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3304 {
3305         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3306         struct fcoe_stats_info *fcoe_stat =
3307                 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3308
3309         if (!CNIC_LOADED(bp))
3310                 return;
3311
3312         memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN);
3313
3314         fcoe_stat->qos_priority =
3315                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
3316
3317         /* insert FCoE stats from ramrod response */
3318         if (!NO_FCOE(bp)) {
3319                 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
3320                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3321                         tstorm_queue_statistics;
3322
3323                 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
3324                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3325                         xstorm_queue_statistics;
3326
3327                 struct fcoe_statistics_params *fw_fcoe_stat =
3328                         &bp->fw_stats_data->fcoe;
3329
3330                 ADD_64_LE(fcoe_stat->rx_bytes_hi, LE32_0,
3331                           fcoe_stat->rx_bytes_lo,
3332                           fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
3333
3334                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3335                           fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3336                           fcoe_stat->rx_bytes_lo,
3337                           fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
3338
3339                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3340                           fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3341                           fcoe_stat->rx_bytes_lo,
3342                           fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
3343
3344                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3345                           fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3346                           fcoe_stat->rx_bytes_lo,
3347                           fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
3348
3349                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3350                           fcoe_stat->rx_frames_lo,
3351                           fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
3352
3353                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3354                           fcoe_stat->rx_frames_lo,
3355                           fcoe_q_tstorm_stats->rcv_ucast_pkts);
3356
3357                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3358                           fcoe_stat->rx_frames_lo,
3359                           fcoe_q_tstorm_stats->rcv_bcast_pkts);
3360
3361                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3362                           fcoe_stat->rx_frames_lo,
3363                           fcoe_q_tstorm_stats->rcv_mcast_pkts);
3364
3365                 ADD_64_LE(fcoe_stat->tx_bytes_hi, LE32_0,
3366                           fcoe_stat->tx_bytes_lo,
3367                           fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
3368
3369                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3370                           fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3371                           fcoe_stat->tx_bytes_lo,
3372                           fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
3373
3374                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3375                           fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3376                           fcoe_stat->tx_bytes_lo,
3377                           fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
3378
3379                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3380                           fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3381                           fcoe_stat->tx_bytes_lo,
3382                           fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
3383
3384                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3385                           fcoe_stat->tx_frames_lo,
3386                           fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
3387
3388                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3389                           fcoe_stat->tx_frames_lo,
3390                           fcoe_q_xstorm_stats->ucast_pkts_sent);
3391
3392                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3393                           fcoe_stat->tx_frames_lo,
3394                           fcoe_q_xstorm_stats->bcast_pkts_sent);
3395
3396                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3397                           fcoe_stat->tx_frames_lo,
3398                           fcoe_q_xstorm_stats->mcast_pkts_sent);
3399         }
3400
3401         /* ask L5 driver to add data to the struct */
3402         bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
3403 }
3404
3405 static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3406 {
3407         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3408         struct iscsi_stats_info *iscsi_stat =
3409                 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3410
3411         if (!CNIC_LOADED(bp))
3412                 return;
3413
3414         memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac,
3415                ETH_ALEN);
3416
3417         iscsi_stat->qos_priority =
3418                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3419
3420         /* ask L5 driver to add data to the struct */
3421         bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
3422 }
3423
3424 /* called due to MCP event (on pmf):
3425  *      reread new bandwidth configuration
3426  *      configure FW
3427  *      notify others function about the change
3428  */
3429 static void bnx2x_config_mf_bw(struct bnx2x *bp)
3430 {
3431         if (bp->link_vars.link_up) {
3432                 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3433                 bnx2x_link_sync_notify(bp);
3434         }
3435         storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3436 }
3437
3438 static void bnx2x_set_mf_bw(struct bnx2x *bp)
3439 {
3440         bnx2x_config_mf_bw(bp);
3441         bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3442 }
3443
3444 static void bnx2x_handle_eee_event(struct bnx2x *bp)
3445 {
3446         DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3447         bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3448 }
3449
3450 static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3451 {
3452         enum drv_info_opcode op_code;
3453         u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
3454
3455         /* if drv_info version supported by MFW doesn't match - send NACK */
3456         if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3457                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3458                 return;
3459         }
3460
3461         op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3462                   DRV_INFO_CONTROL_OP_CODE_SHIFT;
3463
3464         memset(&bp->slowpath->drv_info_to_mcp, 0,
3465                sizeof(union drv_info_to_mcp));
3466
3467         switch (op_code) {
3468         case ETH_STATS_OPCODE:
3469                 bnx2x_drv_info_ether_stat(bp);
3470                 break;
3471         case FCOE_STATS_OPCODE:
3472                 bnx2x_drv_info_fcoe_stat(bp);
3473                 break;
3474         case ISCSI_STATS_OPCODE:
3475                 bnx2x_drv_info_iscsi_stat(bp);
3476                 break;
3477         default:
3478                 /* if op code isn't supported - send NACK */
3479                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3480                 return;
3481         }
3482
3483         /* if we got drv_info attn from MFW then these fields are defined in
3484          * shmem2 for sure
3485          */
3486         SHMEM2_WR(bp, drv_info_host_addr_lo,
3487                 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3488         SHMEM2_WR(bp, drv_info_host_addr_hi,
3489                 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3490
3491         bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3492 }
3493
3494 static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
3495 {
3496         DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
3497
3498         if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3499
3500                 /*
3501                  * This is the only place besides the function initialization
3502                  * where the bp->flags can change so it is done without any
3503                  * locks
3504                  */
3505                 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
3506                         DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
3507                         bp->flags |= MF_FUNC_DIS;
3508
3509                         bnx2x_e1h_disable(bp);
3510                 } else {
3511                         DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
3512                         bp->flags &= ~MF_FUNC_DIS;
3513
3514                         bnx2x_e1h_enable(bp);
3515                 }
3516                 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3517         }
3518         if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
3519                 bnx2x_config_mf_bw(bp);
3520                 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3521         }
3522
3523         /* Report results to MCP */
3524         if (dcc_event)
3525                 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
3526         else
3527                 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
3528 }
3529
3530 /* must be called under the spq lock */
3531 static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
3532 {
3533         struct eth_spe *next_spe = bp->spq_prod_bd;
3534
3535         if (bp->spq_prod_bd == bp->spq_last_bd) {
3536                 bp->spq_prod_bd = bp->spq;
3537                 bp->spq_prod_idx = 0;
3538                 DP(BNX2X_MSG_SP, "end of spq\n");
3539         } else {
3540                 bp->spq_prod_bd++;
3541                 bp->spq_prod_idx++;
3542         }
3543         return next_spe;
3544 }
3545
3546 /* must be called under the spq lock */
3547 static void bnx2x_sp_prod_update(struct bnx2x *bp)
3548 {
3549         int func = BP_FUNC(bp);
3550
3551         /*
3552          * Make sure that BD data is updated before writing the producer:
3553          * BD data is written to the memory, the producer is read from the
3554          * memory, thus we need a full memory barrier to ensure the ordering.
3555          */
3556         mb();
3557
3558         REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
3559                  bp->spq_prod_idx);
3560         mmiowb();
3561 }
3562
3563 /**
3564  * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3565  *
3566  * @cmd:        command to check
3567  * @cmd_type:   command type
3568  */
3569 static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3570 {
3571         if ((cmd_type == NONE_CONNECTION_TYPE) ||
3572             (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
3573             (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3574             (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3575             (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3576             (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3577             (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3578                 return true;
3579         else
3580                 return false;
3581 }
3582
3583 /**
3584  * bnx2x_sp_post - place a single command on an SP ring
3585  *
3586  * @bp:         driver handle
3587  * @command:    command to place (e.g. SETUP, FILTER_RULES, etc.)
3588  * @cid:        SW CID the command is related to
3589  * @data_hi:    command private data address (high 32 bits)
3590  * @data_lo:    command private data address (low 32 bits)
3591  * @cmd_type:   command type (e.g. NONE, ETH)
3592  *
3593  * SP data is handled as if it's always an address pair, thus data fields are
3594  * not swapped to little endian in upper functions. Instead this function swaps
3595  * data as if it's two u32 fields.
3596  */
3597 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3598                   u32 data_hi, u32 data_lo, int cmd_type)
3599 {
3600         struct eth_spe *spe;
3601         u16 type;
3602         bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3603
3604 #ifdef BNX2X_STOP_ON_ERROR
3605         if (unlikely(bp->panic)) {
3606                 BNX2X_ERR("Can't post SP when there is panic\n");
3607                 return -EIO;
3608         }
3609 #endif
3610
3611         spin_lock_bh(&bp->spq_lock);
3612
3613         if (common) {
3614                 if (!atomic_read(&bp->eq_spq_left)) {
3615                         BNX2X_ERR("BUG! EQ ring full!\n");
3616                         spin_unlock_bh(&bp->spq_lock);
3617                         bnx2x_panic();
3618                         return -EBUSY;
3619                 }
3620         } else if (!atomic_read(&bp->cq_spq_left)) {
3621                         BNX2X_ERR("BUG! SPQ ring full!\n");
3622                         spin_unlock_bh(&bp->spq_lock);
3623                         bnx2x_panic();
3624                         return -EBUSY;
3625         }
3626
3627         spe = bnx2x_sp_get_next(bp);
3628
3629         /* CID needs port number to be encoded int it */
3630         spe->hdr.conn_and_cmd_data =
3631                         cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3632                                     HW_CID(bp, cid));
3633
3634         type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
3635
3636         type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3637                  SPE_HDR_FUNCTION_ID);
3638
3639         spe->hdr.type = cpu_to_le16(type);
3640
3641         spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3642         spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3643
3644         /*
3645          * It's ok if the actual decrement is issued towards the memory
3646          * somewhere between the spin_lock and spin_unlock. Thus no
3647          * more explicit memory barrier is needed.
3648          */
3649         if (common)
3650                 atomic_dec(&bp->eq_spq_left);
3651         else
3652                 atomic_dec(&bp->cq_spq_left);
3653
3654         DP(BNX2X_MSG_SP,
3655            "SPQE[%x] (%x:%x)  (cmd, common?) (%d,%d)  hw_cid %x  data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
3656            bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3657            (u32)(U64_LO(bp->spq_mapping) +
3658            (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
3659            HW_CID(bp, cid), data_hi, data_lo, type,
3660            atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
3661
3662         bnx2x_sp_prod_update(bp);
3663         spin_unlock_bh(&bp->spq_lock);
3664         return 0;
3665 }
3666
3667 /* acquire split MCP access lock register */
3668 static int bnx2x_acquire_alr(struct bnx2x *bp)
3669 {
3670         u32 j, val;
3671         int rc = 0;
3672
3673         might_sleep();
3674         for (j = 0; j < 1000; j++) {
3675                 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, MCPR_ACCESS_LOCK_LOCK);
3676                 val = REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK);
3677                 if (val & MCPR_ACCESS_LOCK_LOCK)
3678                         break;
3679
3680                 usleep_range(5000, 10000);
3681         }
3682         if (!(val & MCPR_ACCESS_LOCK_LOCK)) {
3683                 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3684                 rc = -EBUSY;
3685         }
3686
3687         return rc;
3688 }
3689
3690 /* release split MCP access lock register */
3691 static void bnx2x_release_alr(struct bnx2x *bp)
3692 {
3693         REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
3694 }
3695
3696 #define BNX2X_DEF_SB_ATT_IDX    0x0001
3697 #define BNX2X_DEF_SB_IDX        0x0002
3698
3699 static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3700 {
3701         struct host_sp_status_block *def_sb = bp->def_status_blk;
3702         u16 rc = 0;
3703
3704         barrier(); /* status block is written to by the chip */
3705         if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3706                 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3707                 rc |= BNX2X_DEF_SB_ATT_IDX;
3708         }
3709
3710         if (bp->def_idx != def_sb->sp_sb.running_index) {
3711                 bp->def_idx = def_sb->sp_sb.running_index;
3712                 rc |= BNX2X_DEF_SB_IDX;
3713         }
3714
3715         /* Do not reorder: indices reading should complete before handling */
3716         barrier();
3717         return rc;
3718 }
3719
3720 /*
3721  * slow path service functions
3722  */
3723
3724 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3725 {
3726         int port = BP_PORT(bp);
3727         u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3728                               MISC_REG_AEU_MASK_ATTN_FUNC_0;
3729         u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3730                                        NIG_REG_MASK_INTERRUPT_PORT0;
3731         u32 aeu_mask;
3732         u32 nig_mask = 0;
3733         u32 reg_addr;
3734
3735         if (bp->attn_state & asserted)
3736                 BNX2X_ERR("IGU ERROR\n");
3737
3738         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3739         aeu_mask = REG_RD(bp, aeu_addr);
3740
3741         DP(NETIF_MSG_HW, "aeu_mask %x  newly asserted %x\n",
3742            aeu_mask, asserted);
3743         aeu_mask &= ~(asserted & 0x3ff);
3744         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
3745
3746         REG_WR(bp, aeu_addr, aeu_mask);
3747         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3748
3749         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3750         bp->attn_state |= asserted;
3751         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3752
3753         if (asserted & ATTN_HARD_WIRED_MASK) {
3754                 if (asserted & ATTN_NIG_FOR_FUNC) {
3755
3756                         bnx2x_acquire_phy_lock(bp);
3757
3758                         /* save nig interrupt mask */
3759                         nig_mask = REG_RD(bp, nig_int_mask_addr);
3760
3761                         /* If nig_mask is not set, no need to call the update
3762                          * function.
3763                          */
3764                         if (nig_mask) {
3765                                 REG_WR(bp, nig_int_mask_addr, 0);
3766
3767                                 bnx2x_link_attn(bp);
3768                         }
3769
3770                         /* handle unicore attn? */
3771                 }
3772                 if (asserted & ATTN_SW_TIMER_4_FUNC)
3773                         DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
3774
3775                 if (asserted & GPIO_2_FUNC)
3776                         DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
3777
3778                 if (asserted & GPIO_3_FUNC)
3779                         DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
3780
3781                 if (asserted & GPIO_4_FUNC)
3782                         DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
3783
3784                 if (port == 0) {
3785                         if (asserted & ATTN_GENERAL_ATTN_1) {
3786                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
3787                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3788                         }
3789                         if (asserted & ATTN_GENERAL_ATTN_2) {
3790                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
3791                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3792                         }
3793                         if (asserted & ATTN_GENERAL_ATTN_3) {
3794                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
3795                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3796                         }
3797                 } else {
3798                         if (asserted & ATTN_GENERAL_ATTN_4) {
3799                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
3800                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3801                         }
3802                         if (asserted & ATTN_GENERAL_ATTN_5) {
3803                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
3804                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3805                         }
3806                         if (asserted & ATTN_GENERAL_ATTN_6) {
3807                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
3808                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3809                         }
3810                 }
3811
3812         } /* if hardwired */
3813
3814         if (bp->common.int_block == INT_BLOCK_HC)
3815                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3816                             COMMAND_REG_ATTN_BITS_SET);
3817         else
3818                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
3819
3820         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
3821            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3822         REG_WR(bp, reg_addr, asserted);
3823
3824         /* now set back the mask */
3825         if (asserted & ATTN_NIG_FOR_FUNC) {
3826                 /* Verify that IGU ack through BAR was written before restoring
3827                  * NIG mask. This loop should exit after 2-3 iterations max.
3828                  */
3829                 if (bp->common.int_block != INT_BLOCK_HC) {
3830                         u32 cnt = 0, igu_acked;
3831                         do {
3832                                 igu_acked = REG_RD(bp,
3833                                                    IGU_REG_ATTENTION_ACK_BITS);
3834                         } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
3835                                  (++cnt < MAX_IGU_ATTN_ACK_TO));
3836                         if (!igu_acked)
3837                                 DP(NETIF_MSG_HW,
3838                                    "Failed to verify IGU ack on time\n");
3839                         barrier();
3840                 }
3841                 REG_WR(bp, nig_int_mask_addr, nig_mask);
3842                 bnx2x_release_phy_lock(bp);
3843         }
3844 }
3845
3846 static void bnx2x_fan_failure(struct bnx2x *bp)
3847 {
3848         int port = BP_PORT(bp);
3849         u32 ext_phy_config;
3850         /* mark the failure */
3851         ext_phy_config =
3852                 SHMEM_RD(bp,
3853                          dev_info.port_hw_config[port].external_phy_config);
3854
3855         ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
3856         ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
3857         SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
3858                  ext_phy_config);
3859
3860         /* log the failure */
3861         netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
3862                             "Please contact OEM Support for assistance\n");
3863
3864         /* Schedule device reset (unload)
3865          * This is due to some boards consuming sufficient power when driver is
3866          * up to overheat if fan fails.
3867          */
3868         smp_mb__before_clear_bit();
3869         set_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state);
3870         smp_mb__after_clear_bit();
3871         schedule_delayed_work(&bp->sp_rtnl_task, 0);
3872 }
3873
3874 static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
3875 {
3876         int port = BP_PORT(bp);
3877         int reg_offset;
3878         u32 val;
3879
3880         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
3881                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
3882
3883         if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
3884
3885                 val = REG_RD(bp, reg_offset);
3886                 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
3887                 REG_WR(bp, reg_offset, val);
3888
3889                 BNX2X_ERR("SPIO5 hw attention\n");
3890
3891                 /* Fan failure attention */
3892                 bnx2x_hw_reset_phy(&bp->link_params);
3893                 bnx2x_fan_failure(bp);
3894         }
3895
3896         if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
3897                 bnx2x_acquire_phy_lock(bp);
3898                 bnx2x_handle_module_detect_int(&bp->link_params);
3899                 bnx2x_release_phy_lock(bp);
3900         }
3901
3902         if (attn & HW_INTERRUT_ASSERT_SET_0) {
3903
3904                 val = REG_RD(bp, reg_offset);
3905                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
3906                 REG_WR(bp, reg_offset, val);
3907
3908                 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
3909                           (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
3910                 bnx2x_panic();
3911         }
3912 }
3913
3914 static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
3915 {
3916         u32 val;
3917
3918         if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
3919
3920                 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
3921                 BNX2X_ERR("DB hw attention 0x%x\n", val);
3922                 /* DORQ discard attention */
3923                 if (val & 0x2)
3924                         BNX2X_ERR("FATAL error from DORQ\n");
3925         }
3926
3927         if (attn & HW_INTERRUT_ASSERT_SET_1) {
3928
3929                 int port = BP_PORT(bp);
3930                 int reg_offset;
3931
3932                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3933                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3934
3935                 val = REG_RD(bp, reg_offset);
3936                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3937                 REG_WR(bp, reg_offset, val);
3938
3939                 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
3940                           (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
3941                 bnx2x_panic();
3942         }
3943 }
3944
3945 static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
3946 {
3947         u32 val;
3948
3949         if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3950
3951                 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
3952                 BNX2X_ERR("CFC hw attention 0x%x\n", val);
3953                 /* CFC error attention */
3954                 if (val & 0x2)
3955                         BNX2X_ERR("FATAL error from CFC\n");
3956         }
3957
3958         if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3959                 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
3960                 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
3961                 /* RQ_USDMDP_FIFO_OVERFLOW */
3962                 if (val & 0x18000)
3963                         BNX2X_ERR("FATAL error from PXP\n");
3964
3965                 if (!CHIP_IS_E1x(bp)) {
3966                         val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
3967                         BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
3968                 }
3969         }
3970
3971         if (attn & HW_INTERRUT_ASSERT_SET_2) {
3972
3973                 int port = BP_PORT(bp);
3974                 int reg_offset;
3975
3976                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3977                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3978
3979                 val = REG_RD(bp, reg_offset);
3980                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3981                 REG_WR(bp, reg_offset, val);
3982
3983                 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
3984                           (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
3985                 bnx2x_panic();
3986         }
3987 }
3988
3989 static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
3990 {
3991         u32 val;
3992
3993         if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3994
3995                 if (attn & BNX2X_PMF_LINK_ASSERT) {
3996                         int func = BP_FUNC(bp);
3997
3998                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
3999                         bnx2x_read_mf_cfg(bp);
4000                         bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
4001                                         func_mf_config[BP_ABS_FUNC(bp)].config);
4002                         val = SHMEM_RD(bp,
4003                                        func_mb[BP_FW_MB_IDX(bp)].drv_status);
4004                         if (val & DRV_STATUS_DCC_EVENT_MASK)
4005                                 bnx2x_dcc_event(bp,
4006                                             (val & DRV_STATUS_DCC_EVENT_MASK));
4007
4008                         if (val & DRV_STATUS_SET_MF_BW)
4009                                 bnx2x_set_mf_bw(bp);
4010
4011                         if (val & DRV_STATUS_DRV_INFO_REQ)
4012                                 bnx2x_handle_drv_info_req(bp);
4013
4014                         if (val & DRV_STATUS_VF_DISABLED)
4015                                 bnx2x_vf_handle_flr_event(bp);
4016
4017                         if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
4018                                 bnx2x_pmf_update(bp);
4019
4020                         if (bp->port.pmf &&
4021                             (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
4022                                 bp->dcbx_enabled > 0)
4023                                 /* start dcbx state machine */
4024                                 bnx2x_dcbx_set_params(bp,
4025                                         BNX2X_DCBX_STATE_NEG_RECEIVED);
4026                         if (val & DRV_STATUS_AFEX_EVENT_MASK)
4027                                 bnx2x_handle_afex_cmd(bp,
4028                                         val & DRV_STATUS_AFEX_EVENT_MASK);
4029                         if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
4030                                 bnx2x_handle_eee_event(bp);
4031                         if (bp->link_vars.periodic_flags &
4032                             PERIODIC_FLAGS_LINK_EVENT) {
4033                                 /*  sync with link */
4034                                 bnx2x_acquire_phy_lock(bp);
4035                                 bp->link_vars.periodic_flags &=
4036                                         ~PERIODIC_FLAGS_LINK_EVENT;
4037                                 bnx2x_release_phy_lock(bp);
4038                                 if (IS_MF(bp))
4039                                         bnx2x_link_sync_notify(bp);
4040                                 bnx2x_link_report(bp);
4041                         }
4042                         /* Always call it here: bnx2x_link_report() will
4043                          * prevent the link indication duplication.
4044                          */
4045                         bnx2x__link_status_update(bp);
4046                 } else if (attn & BNX2X_MC_ASSERT_BITS) {
4047
4048                         BNX2X_ERR("MC assert!\n");
4049                         bnx2x_mc_assert(bp);
4050                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
4051                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
4052                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
4053                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
4054                         bnx2x_panic();
4055
4056                 } else if (attn & BNX2X_MCP_ASSERT) {
4057
4058                         BNX2X_ERR("MCP assert!\n");
4059                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
4060                         bnx2x_fw_dump(bp);
4061
4062                 } else
4063                         BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
4064         }
4065
4066         if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
4067                 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
4068                 if (attn & BNX2X_GRC_TIMEOUT) {
4069                         val = CHIP_IS_E1(bp) ? 0 :
4070                                         REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
4071                         BNX2X_ERR("GRC time-out 0x%08x\n", val);
4072                 }
4073                 if (attn & BNX2X_GRC_RSV) {
4074                         val = CHIP_IS_E1(bp) ? 0 :
4075                                         REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
4076                         BNX2X_ERR("GRC reserved 0x%08x\n", val);
4077                 }
4078                 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
4079         }
4080 }
4081
4082 /*
4083  * Bits map:
4084  * 0-7   - Engine0 load counter.
4085  * 8-15  - Engine1 load counter.
4086  * 16    - Engine0 RESET_IN_PROGRESS bit.
4087  * 17    - Engine1 RESET_IN_PROGRESS bit.
4088  * 18    - Engine0 ONE_IS_LOADED. Set when there is at least one active function
4089  *         on the engine
4090  * 19    - Engine1 ONE_IS_LOADED.
4091  * 20    - Chip reset flow bit. When set none-leader must wait for both engines
4092  *         leader to complete (check for both RESET_IN_PROGRESS bits and not for
4093  *         just the one belonging to its engine).
4094  *
4095  */
4096 #define BNX2X_RECOVERY_GLOB_REG         MISC_REG_GENERIC_POR_1
4097
4098 #define BNX2X_PATH0_LOAD_CNT_MASK       0x000000ff
4099 #define BNX2X_PATH0_LOAD_CNT_SHIFT      0
4100 #define BNX2X_PATH1_LOAD_CNT_MASK       0x0000ff00
4101 #define BNX2X_PATH1_LOAD_CNT_SHIFT      8
4102 #define BNX2X_PATH0_RST_IN_PROG_BIT     0x00010000
4103 #define BNX2X_PATH1_RST_IN_PROG_BIT     0x00020000
4104 #define BNX2X_GLOBAL_RESET_BIT          0x00040000
4105
4106 /*
4107  * Set the GLOBAL_RESET bit.
4108  *
4109  * Should be run under rtnl lock
4110  */
4111 void bnx2x_set_reset_global(struct bnx2x *bp)
4112 {
4113         u32 val;
4114         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4115         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4116         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
4117         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4118 }
4119
4120 /*
4121  * Clear the GLOBAL_RESET bit.
4122  *
4123  * Should be run under rtnl lock
4124  */
4125 static void bnx2x_clear_reset_global(struct bnx2x *bp)
4126 {
4127         u32 val;
4128         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4129         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4130         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
4131         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4132 }
4133
4134 /*
4135  * Checks the GLOBAL_RESET bit.
4136  *
4137  * should be run under rtnl lock
4138  */
4139 static bool bnx2x_reset_is_global(struct bnx2x *bp)
4140 {
4141         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4142
4143         DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
4144         return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
4145 }
4146
4147 /*
4148  * Clear RESET_IN_PROGRESS bit for the current engine.
4149  *
4150  * Should be run under rtnl lock
4151  */
4152 static void bnx2x_set_reset_done(struct bnx2x *bp)
4153 {
4154         u32 val;
4155         u32 bit = BP_PATH(bp) ?
4156                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4157         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4158         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4159
4160         /* Clear the bit */
4161         val &= ~bit;
4162         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4163
4164         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4165 }
4166
4167 /*
4168  * Set RESET_IN_PROGRESS for the current engine.
4169  *
4170  * should be run under rtnl lock
4171  */
4172 void bnx2x_set_reset_in_progress(struct bnx2x *bp)
4173 {
4174         u32 val;
4175         u32 bit = BP_PATH(bp) ?
4176                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4177         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4178         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4179
4180         /* Set the bit */
4181         val |= bit;
4182         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4183         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4184 }
4185
4186 /*
4187  * Checks the RESET_IN_PROGRESS bit for the given engine.
4188  * should be run under rtnl lock
4189  */
4190 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
4191 {
4192         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4193         u32 bit = engine ?
4194                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4195
4196         /* return false if bit is set */
4197         return (val & bit) ? false : true;
4198 }
4199
4200 /*
4201  * set pf load for the current pf.
4202  *
4203  * should be run under rtnl lock
4204  */
4205 void bnx2x_set_pf_load(struct bnx2x *bp)
4206 {
4207         u32 val1, val;
4208         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4209                              BNX2X_PATH0_LOAD_CNT_MASK;
4210         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4211                              BNX2X_PATH0_LOAD_CNT_SHIFT;
4212
4213         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4214         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4215
4216         DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
4217
4218         /* get the current counter value */
4219         val1 = (val & mask) >> shift;
4220
4221         /* set bit of that PF */
4222         val1 |= (1 << bp->pf_num);
4223
4224         /* clear the old value */
4225         val &= ~mask;
4226
4227         /* set the new one */
4228         val |= ((val1 << shift) & mask);
4229
4230         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4231         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4232 }
4233
4234 /**
4235  * bnx2x_clear_pf_load - clear pf load mark
4236  *
4237  * @bp:         driver handle
4238  *
4239  * Should be run under rtnl lock.
4240  * Decrements the load counter for the current engine. Returns
4241  * whether other functions are still loaded
4242  */
4243 bool bnx2x_clear_pf_load(struct bnx2x *bp)
4244 {
4245         u32 val1, val;
4246         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4247                              BNX2X_PATH0_LOAD_CNT_MASK;
4248         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4249                              BNX2X_PATH0_LOAD_CNT_SHIFT;
4250
4251         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4252         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4253         DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
4254
4255         /* get the current counter value */
4256         val1 = (val & mask) >> shift;
4257
4258         /* clear bit of that PF */
4259         val1 &= ~(1 << bp->pf_num);
4260
4261         /* clear the old value */
4262         val &= ~mask;
4263
4264         /* set the new one */
4265         val |= ((val1 << shift) & mask);
4266
4267         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4268         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4269         return val1 != 0;
4270 }
4271
4272 /*
4273  * Read the load status for the current engine.
4274  *
4275  * should be run under rtnl lock
4276  */
4277 static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
4278 {
4279         u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4280                              BNX2X_PATH0_LOAD_CNT_MASK);
4281         u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4282                              BNX2X_PATH0_LOAD_CNT_SHIFT);
4283         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4284
4285         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
4286
4287         val = (val & mask) >> shift;
4288
4289         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4290            engine, val);
4291
4292         return val != 0;
4293 }
4294
4295 static void _print_parity(struct bnx2x *bp, u32 reg)
4296 {
4297         pr_cont(" [0x%08x] ", REG_RD(bp, reg));
4298 }
4299
4300 static void _print_next_block(int idx, const char *blk)
4301 {
4302         pr_cont("%s%s", idx ? ", " : "", blk);
4303 }
4304
4305 static bool bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig,
4306                                             int *par_num, bool print)
4307 {
4308         u32 cur_bit;
4309         bool res;
4310         int i;
4311
4312         res = false;
4313
4314         for (i = 0; sig; i++) {
4315                 cur_bit = (0x1UL << i);
4316                 if (sig & cur_bit) {
4317                         res |= true; /* Each bit is real error! */
4318
4319                         if (print) {
4320                                 switch (cur_bit) {
4321                                 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
4322                                         _print_next_block((*par_num)++, "BRB");
4323                                         _print_parity(bp,
4324                                                       BRB1_REG_BRB1_PRTY_STS);
4325                                         break;
4326                                 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
4327                                         _print_next_block((*par_num)++,
4328                                                           "PARSER");
4329                                         _print_parity(bp, PRS_REG_PRS_PRTY_STS);
4330                                         break;
4331                                 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
4332                                         _print_next_block((*par_num)++, "TSDM");
4333                                         _print_parity(bp,
4334                                                       TSDM_REG_TSDM_PRTY_STS);
4335                                         break;
4336                                 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
4337                                         _print_next_block((*par_num)++,
4338                                                           "SEARCHER");
4339                                         _print_parity(bp, SRC_REG_SRC_PRTY_STS);
4340                                         break;
4341                                 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4342                                         _print_next_block((*par_num)++, "TCM");
4343                                         _print_parity(bp, TCM_REG_TCM_PRTY_STS);
4344                                         break;
4345                                 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4346                                         _print_next_block((*par_num)++,
4347                                                           "TSEMI");
4348                                         _print_parity(bp,
4349                                                       TSEM_REG_TSEM_PRTY_STS_0);
4350                                         _print_parity(bp,
4351                                                       TSEM_REG_TSEM_PRTY_STS_1);
4352                                         break;
4353                                 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4354                                         _print_next_block((*par_num)++, "XPB");
4355                                         _print_parity(bp, GRCBASE_XPB +
4356                                                           PB_REG_PB_PRTY_STS);
4357                                         break;
4358                                 }
4359                         }
4360
4361                         /* Clear the bit */
4362                         sig &= ~cur_bit;
4363                 }
4364         }
4365
4366         return res;
4367 }
4368
4369 static bool bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
4370                                             int *par_num, bool *global,
4371                                             bool print)
4372 {
4373         u32 cur_bit;
4374         bool res;
4375         int i;
4376
4377         res = false;
4378
4379         for (i = 0; sig; i++) {
4380                 cur_bit = (0x1UL << i);
4381                 if (sig & cur_bit) {
4382                         res |= true; /* Each bit is real error! */
4383                         switch (cur_bit) {
4384                         case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
4385                                 if (print) {
4386                                         _print_next_block((*par_num)++, "PBF");
4387                                         _print_parity(bp, PBF_REG_PBF_PRTY_STS);
4388                                 }
4389                                 break;
4390                         case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
4391                                 if (print) {
4392                                         _print_next_block((*par_num)++, "QM");
4393                                         _print_parity(bp, QM_REG_QM_PRTY_STS);
4394                                 }
4395                                 break;
4396                         case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
4397                                 if (print) {
4398                                         _print_next_block((*par_num)++, "TM");
4399                                         _print_parity(bp, TM_REG_TM_PRTY_STS);
4400                                 }
4401                                 break;
4402                         case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
4403                                 if (print) {
4404                                         _print_next_block((*par_num)++, "XSDM");
4405                                         _print_parity(bp,
4406                                                       XSDM_REG_XSDM_PRTY_STS);
4407                                 }
4408                                 break;
4409                         case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
4410                                 if (print) {
4411                                         _print_next_block((*par_num)++, "XCM");
4412                                         _print_parity(bp, XCM_REG_XCM_PRTY_STS);
4413                                 }
4414                                 break;
4415                         case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
4416                                 if (print) {
4417                                         _print_next_block((*par_num)++,
4418                                                           "XSEMI");
4419                                         _print_parity(bp,
4420                                                       XSEM_REG_XSEM_PRTY_STS_0);
4421                                         _print_parity(bp,
4422                                                       XSEM_REG_XSEM_PRTY_STS_1);
4423                                 }
4424                                 break;
4425                         case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
4426                                 if (print) {
4427                                         _print_next_block((*par_num)++,
4428                                                           "DOORBELLQ");
4429                                         _print_parity(bp,
4430                                                       DORQ_REG_DORQ_PRTY_STS);
4431                                 }
4432                                 break;
4433                         case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
4434                                 if (print) {
4435                                         _print_next_block((*par_num)++, "NIG");
4436                                         if (CHIP_IS_E1x(bp)) {
4437                                                 _print_parity(bp,
4438                                                         NIG_REG_NIG_PRTY_STS);
4439                                         } else {
4440                                                 _print_parity(bp,
4441                                                         NIG_REG_NIG_PRTY_STS_0);
4442                                                 _print_parity(bp,
4443                                                         NIG_REG_NIG_PRTY_STS_1);
4444                                         }
4445                                 }
4446                                 break;
4447                         case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
4448                                 if (print)
4449                                         _print_next_block((*par_num)++,
4450                                                           "VAUX PCI CORE");
4451                                 *global = true;
4452                                 break;
4453                         case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
4454                                 if (print) {
4455                                         _print_next_block((*par_num)++,
4456                                                           "DEBUG");
4457                                         _print_parity(bp, DBG_REG_DBG_PRTY_STS);
4458                                 }
4459                                 break;
4460                         case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
4461                                 if (print) {
4462                                         _print_next_block((*par_num)++, "USDM");
4463                                         _print_parity(bp,
4464                                                       USDM_REG_USDM_PRTY_STS);
4465                                 }
4466                                 break;
4467                         case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
4468                                 if (print) {
4469                                         _print_next_block((*par_num)++, "UCM");
4470                                         _print_parity(bp, UCM_REG_UCM_PRTY_STS);
4471                                 }
4472                                 break;
4473                         case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
4474                                 if (print) {
4475                                         _print_next_block((*par_num)++,
4476                                                           "USEMI");
4477                                         _print_parity(bp,
4478                                                       USEM_REG_USEM_PRTY_STS_0);
4479                                         _print_parity(bp,
4480                                                       USEM_REG_USEM_PRTY_STS_1);
4481                                 }
4482                                 break;
4483                         case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
4484                                 if (print) {
4485                                         _print_next_block((*par_num)++, "UPB");
4486                                         _print_parity(bp, GRCBASE_UPB +
4487                                                           PB_REG_PB_PRTY_STS);
4488                                 }
4489                                 break;
4490                         case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
4491                                 if (print) {
4492                                         _print_next_block((*par_num)++, "CSDM");
4493                                         _print_parity(bp,
4494                                                       CSDM_REG_CSDM_PRTY_STS);
4495                                 }
4496                                 break;
4497                         case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
4498                                 if (print) {
4499                                         _print_next_block((*par_num)++, "CCM");
4500                                         _print_parity(bp, CCM_REG_CCM_PRTY_STS);
4501                                 }
4502                                 break;
4503                         }
4504
4505                         /* Clear the bit */
4506                         sig &= ~cur_bit;
4507                 }
4508         }
4509
4510         return res;
4511 }
4512
4513 static bool bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig,
4514                                             int *par_num, bool print)
4515 {
4516         u32 cur_bit;
4517         bool res;
4518         int i;
4519
4520         res = false;
4521
4522         for (i = 0; sig; i++) {
4523                 cur_bit = (0x1UL << i);
4524                 if (sig & cur_bit) {
4525                         res |= true; /* Each bit is real error! */
4526                         if (print) {
4527                                 switch (cur_bit) {
4528                                 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4529                                         _print_next_block((*par_num)++,
4530                                                           "CSEMI");
4531                                         _print_parity(bp,
4532                                                       CSEM_REG_CSEM_PRTY_STS_0);
4533                                         _print_parity(bp,
4534                                                       CSEM_REG_CSEM_PRTY_STS_1);
4535                                         break;
4536                                 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4537                                         _print_next_block((*par_num)++, "PXP");
4538                                         _print_parity(bp, PXP_REG_PXP_PRTY_STS);
4539                                         _print_parity(bp,
4540                                                       PXP2_REG_PXP2_PRTY_STS_0);
4541                                         _print_parity(bp,
4542                                                       PXP2_REG_PXP2_PRTY_STS_1);
4543                                         break;
4544                                 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4545                                         _print_next_block((*par_num)++,
4546                                                           "PXPPCICLOCKCLIENT");
4547                                         break;
4548                                 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4549                                         _print_next_block((*par_num)++, "CFC");
4550                                         _print_parity(bp,
4551                                                       CFC_REG_CFC_PRTY_STS);
4552                                         break;
4553                                 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4554                                         _print_next_block((*par_num)++, "CDU");
4555                                         _print_parity(bp, CDU_REG_CDU_PRTY_STS);
4556                                         break;
4557                                 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4558                                         _print_next_block((*par_num)++, "DMAE");
4559                                         _print_parity(bp,
4560                                                       DMAE_REG_DMAE_PRTY_STS);
4561                                         break;
4562                                 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4563                                         _print_next_block((*par_num)++, "IGU");
4564                                         if (CHIP_IS_E1x(bp))
4565                                                 _print_parity(bp,
4566                                                         HC_REG_HC_PRTY_STS);
4567                                         else
4568                                                 _print_parity(bp,
4569                                                         IGU_REG_IGU_PRTY_STS);
4570                                         break;
4571                                 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4572                                         _print_next_block((*par_num)++, "MISC");
4573                                         _print_parity(bp,
4574                                                       MISC_REG_MISC_PRTY_STS);
4575                                         break;
4576                                 }
4577                         }
4578
4579                         /* Clear the bit */
4580                         sig &= ~cur_bit;
4581                 }
4582         }
4583
4584         return res;
4585 }
4586
4587 static bool bnx2x_check_blocks_with_parity3(struct bnx2x *bp, u32 sig,
4588                                             int *par_num, bool *global,
4589                                             bool print)
4590 {
4591         bool res = false;
4592         u32 cur_bit;
4593         int i;
4594
4595         for (i = 0; sig; i++) {
4596                 cur_bit = (0x1UL << i);
4597                 if (sig & cur_bit) {
4598                         switch (cur_bit) {
4599                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
4600                                 if (print)
4601                                         _print_next_block((*par_num)++,
4602                                                           "MCP ROM");
4603                                 *global = true;
4604                                 res |= true;
4605                                 break;
4606                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
4607                                 if (print)
4608                                         _print_next_block((*par_num)++,
4609                                                           "MCP UMP RX");
4610                                 *global = true;
4611                                 res |= true;
4612                                 break;
4613                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
4614                                 if (print)
4615                                         _print_next_block((*par_num)++,
4616                                                           "MCP UMP TX");
4617                                 *global = true;
4618                                 res |= true;
4619                                 break;
4620                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
4621                                 if (print)
4622                                         _print_next_block((*par_num)++,
4623                                                           "MCP SCPAD");
4624                                 /* clear latched SCPAD PATIRY from MCP */
4625                                 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL,
4626                                        1UL << 10);
4627                                 break;
4628                         }
4629
4630                         /* Clear the bit */
4631                         sig &= ~cur_bit;
4632                 }
4633         }
4634
4635         return res;
4636 }
4637
4638 static bool bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig,
4639                                             int *par_num, bool print)
4640 {
4641         u32 cur_bit;
4642         bool res;
4643         int i;
4644
4645         res = false;
4646
4647         for (i = 0; sig; i++) {
4648                 cur_bit = (0x1UL << i);
4649                 if (sig & cur_bit) {
4650                         res |= true; /* Each bit is real error! */
4651                         if (print) {
4652                                 switch (cur_bit) {
4653                                 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4654                                         _print_next_block((*par_num)++,
4655                                                           "PGLUE_B");
4656                                         _print_parity(bp,
4657                                                       PGLUE_B_REG_PGLUE_B_PRTY_STS);
4658                                         break;
4659                                 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4660                                         _print_next_block((*par_num)++, "ATC");
4661                                         _print_parity(bp,
4662                                                       ATC_REG_ATC_PRTY_STS);
4663                                         break;
4664                                 }
4665                         }
4666                         /* Clear the bit */
4667                         sig &= ~cur_bit;
4668                 }
4669         }
4670
4671         return res;
4672 }
4673
4674 static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4675                               u32 *sig)
4676 {
4677         bool res = false;
4678
4679         if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4680             (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4681             (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4682             (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4683             (sig[4] & HW_PRTY_ASSERT_SET_4)) {
4684                 int par_num = 0;
4685                 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4686                                  "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
4687                           sig[0] & HW_PRTY_ASSERT_SET_0,
4688                           sig[1] & HW_PRTY_ASSERT_SET_1,
4689                           sig[2] & HW_PRTY_ASSERT_SET_2,
4690                           sig[3] & HW_PRTY_ASSERT_SET_3,
4691                           sig[4] & HW_PRTY_ASSERT_SET_4);
4692                 if (print)
4693                         netdev_err(bp->dev,
4694                                    "Parity errors detected in blocks: ");
4695                 res |= bnx2x_check_blocks_with_parity0(bp,
4696                         sig[0] & HW_PRTY_ASSERT_SET_0, &par_num, print);
4697                 res |= bnx2x_check_blocks_with_parity1(bp,
4698                         sig[1] & HW_PRTY_ASSERT_SET_1, &par_num, global, print);
4699                 res |= bnx2x_check_blocks_with_parity2(bp,
4700                         sig[2] & HW_PRTY_ASSERT_SET_2, &par_num, print);
4701                 res |= bnx2x_check_blocks_with_parity3(bp,
4702                         sig[3] & HW_PRTY_ASSERT_SET_3, &par_num, global, print);
4703                 res |= bnx2x_check_blocks_with_parity4(bp,
4704                         sig[4] & HW_PRTY_ASSERT_SET_4, &par_num, print);
4705
4706                 if (print)
4707                         pr_cont("\n");
4708         }
4709
4710         return res;
4711 }
4712
4713 /**
4714  * bnx2x_chk_parity_attn - checks for parity attentions.
4715  *
4716  * @bp:         driver handle
4717  * @global:     true if there was a global attention
4718  * @print:      show parity attention in syslog
4719  */
4720 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
4721 {
4722         struct attn_route attn = { {0} };
4723         int port = BP_PORT(bp);
4724
4725         attn.sig[0] = REG_RD(bp,
4726                 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
4727                              port*4);
4728         attn.sig[1] = REG_RD(bp,
4729                 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
4730                              port*4);
4731         attn.sig[2] = REG_RD(bp,
4732                 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
4733                              port*4);
4734         attn.sig[3] = REG_RD(bp,
4735                 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
4736                              port*4);
4737         /* Since MCP attentions can't be disabled inside the block, we need to
4738          * read AEU registers to see whether they're currently disabled
4739          */
4740         attn.sig[3] &= ((REG_RD(bp,
4741                                 !port ? MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0
4742                                       : MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0) &
4743                          MISC_AEU_ENABLE_MCP_PRTY_BITS) |
4744                         ~MISC_AEU_ENABLE_MCP_PRTY_BITS);
4745
4746         if (!CHIP_IS_E1x(bp))
4747                 attn.sig[4] = REG_RD(bp,
4748                         MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
4749                                      port*4);
4750
4751         return bnx2x_parity_attn(bp, global, print, attn.sig);
4752 }
4753
4754 static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
4755 {
4756         u32 val;
4757         if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
4758
4759                 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
4760                 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
4761                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
4762                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
4763                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
4764                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
4765                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
4766                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
4767                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
4768                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
4769                 if (val &
4770                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
4771                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
4772                 if (val &
4773                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
4774                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
4775                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
4776                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
4777                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
4778                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
4779                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
4780                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
4781         }
4782         if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
4783                 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
4784                 BNX2X_ERR("ATC hw attention 0x%x\n", val);
4785                 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
4786                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
4787                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
4788                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
4789                 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
4790                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
4791                 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
4792                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
4793                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
4794                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
4795                 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
4796                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
4797         }
4798
4799         if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4800                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
4801                 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
4802                 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4803                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
4804         }
4805 }
4806
4807 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
4808 {
4809         struct attn_route attn, *group_mask;
4810         int port = BP_PORT(bp);
4811         int index;
4812         u32 reg_addr;
4813         u32 val;
4814         u32 aeu_mask;
4815         bool global = false;
4816
4817         /* need to take HW lock because MCP or other port might also
4818            try to handle this event */
4819         bnx2x_acquire_alr(bp);
4820
4821         if (bnx2x_chk_parity_attn(bp, &global, true)) {
4822 #ifndef BNX2X_STOP_ON_ERROR
4823                 bp->recovery_state = BNX2X_RECOVERY_INIT;
4824                 schedule_delayed_work(&bp->sp_rtnl_task, 0);
4825                 /* Disable HW interrupts */
4826                 bnx2x_int_disable(bp);
4827                 /* In case of parity errors don't handle attentions so that
4828                  * other function would "see" parity errors.
4829                  */
4830 #else
4831                 bnx2x_panic();
4832 #endif
4833                 bnx2x_release_alr(bp);
4834                 return;
4835         }
4836
4837         attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
4838         attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
4839         attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
4840         attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
4841         if (!CHIP_IS_E1x(bp))
4842                 attn.sig[4] =
4843                       REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
4844         else
4845                 attn.sig[4] = 0;
4846
4847         DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
4848            attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
4849
4850         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4851                 if (deasserted & (1 << index)) {
4852                         group_mask = &bp->attn_group[index];
4853
4854                         DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
4855                            index,
4856                            group_mask->sig[0], group_mask->sig[1],
4857                            group_mask->sig[2], group_mask->sig[3],
4858                            group_mask->sig[4]);
4859
4860                         bnx2x_attn_int_deasserted4(bp,
4861                                         attn.sig[4] & group_mask->sig[4]);
4862                         bnx2x_attn_int_deasserted3(bp,
4863                                         attn.sig[3] & group_mask->sig[3]);
4864                         bnx2x_attn_int_deasserted1(bp,
4865                                         attn.sig[1] & group_mask->sig[1]);
4866                         bnx2x_attn_int_deasserted2(bp,
4867                                         attn.sig[2] & group_mask->sig[2]);
4868                         bnx2x_attn_int_deasserted0(bp,
4869                                         attn.sig[0] & group_mask->sig[0]);
4870                 }
4871         }
4872
4873         bnx2x_release_alr(bp);
4874
4875         if (bp->common.int_block == INT_BLOCK_HC)
4876                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4877                             COMMAND_REG_ATTN_BITS_CLR);
4878         else
4879                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
4880
4881         val = ~deasserted;
4882         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
4883            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4884         REG_WR(bp, reg_addr, val);
4885
4886         if (~bp->attn_state & deasserted)
4887                 BNX2X_ERR("IGU ERROR\n");
4888
4889         reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4890                           MISC_REG_AEU_MASK_ATTN_FUNC_0;
4891
4892         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4893         aeu_mask = REG_RD(bp, reg_addr);
4894
4895         DP(NETIF_MSG_HW, "aeu_mask %x  newly deasserted %x\n",
4896            aeu_mask, deasserted);
4897         aeu_mask |= (deasserted & 0x3ff);
4898         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
4899
4900         REG_WR(bp, reg_addr, aeu_mask);
4901         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4902
4903         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
4904         bp->attn_state &= ~deasserted;
4905         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
4906 }
4907
4908 static void bnx2x_attn_int(struct bnx2x *bp)
4909 {
4910         /* read local copy of bits */
4911         u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
4912                                                                 attn_bits);
4913         u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
4914                                                                 attn_bits_ack);
4915         u32 attn_state = bp->attn_state;
4916
4917         /* look for changed bits */
4918         u32 asserted   =  attn_bits & ~attn_ack & ~attn_state;
4919         u32 deasserted = ~attn_bits &  attn_ack &  attn_state;
4920
4921         DP(NETIF_MSG_HW,
4922            "attn_bits %x  attn_ack %x  asserted %x  deasserted %x\n",
4923            attn_bits, attn_ack, asserted, deasserted);
4924
4925         if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
4926                 BNX2X_ERR("BAD attention state\n");
4927
4928         /* handle bits that were raised */
4929         if (asserted)
4930                 bnx2x_attn_int_asserted(bp, asserted);
4931
4932         if (deasserted)
4933                 bnx2x_attn_int_deasserted(bp, deasserted);
4934 }
4935
4936 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
4937                       u16 index, u8 op, u8 update)
4938 {
4939         u32 igu_addr = bp->igu_base_addr;
4940         igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
4941         bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
4942                              igu_addr);
4943 }
4944
4945 static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
4946 {
4947         /* No memory barriers */
4948         storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
4949         mmiowb(); /* keep prod updates ordered */
4950 }
4951
4952 static int  bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
4953                                       union event_ring_elem *elem)
4954 {
4955         u8 err = elem->message.error;
4956
4957         if (!bp->cnic_eth_dev.starting_cid  ||
4958             (cid < bp->cnic_eth_dev.starting_cid &&
4959             cid != bp->cnic_eth_dev.iscsi_l2_cid))
4960                 return 1;
4961
4962         DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
4963
4964         if (unlikely(err)) {
4965
4966                 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
4967                           cid);
4968                 bnx2x_panic_dump(bp, false);
4969         }
4970         bnx2x_cnic_cfc_comp(bp, cid, err);
4971         return 0;
4972 }
4973
4974 static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
4975 {
4976         struct bnx2x_mcast_ramrod_params rparam;
4977         int rc;
4978
4979         memset(&rparam, 0, sizeof(rparam));
4980
4981         rparam.mcast_obj = &bp->mcast_obj;
4982
4983         netif_addr_lock_bh(bp->dev);
4984
4985         /* Clear pending state for the last command */
4986         bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
4987
4988         /* If there are pending mcast commands - send them */
4989         if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
4990                 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
4991                 if (rc < 0)
4992                         BNX2X_ERR("Failed to send pending mcast commands: %d\n",
4993                                   rc);
4994         }
4995
4996         netif_addr_unlock_bh(bp->dev);
4997 }
4998
4999 static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
5000                                             union event_ring_elem *elem)
5001 {
5002         unsigned long ramrod_flags = 0;
5003         int rc = 0;
5004         u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
5005         struct bnx2x_vlan_mac_obj *vlan_mac_obj;
5006
5007         /* Always push next commands out, don't wait here */
5008         __set_bit(RAMROD_CONT, &ramrod_flags);
5009
5010         switch (le32_to_cpu((__force __le32)elem->message.data.eth_event.echo)
5011                             >> BNX2X_SWCID_SHIFT) {
5012         case BNX2X_FILTER_MAC_PENDING:
5013                 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
5014                 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp)))
5015                         vlan_mac_obj = &bp->iscsi_l2_mac_obj;
5016                 else
5017                         vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
5018
5019                 break;
5020         case BNX2X_FILTER_MCAST_PENDING:
5021                 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
5022                 /* This is only relevant for 57710 where multicast MACs are
5023                  * configured as unicast MACs using the same ramrod.
5024                  */
5025                 bnx2x_handle_mcast_eqe(bp);
5026                 return;
5027         default:
5028                 BNX2X_ERR("Unsupported classification command: %d\n",
5029                           elem->message.data.eth_event.echo);
5030                 return;
5031         }
5032
5033         rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
5034
5035         if (rc < 0)
5036                 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
5037         else if (rc > 0)
5038                 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
5039 }
5040
5041 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
5042
5043 static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
5044 {
5045         netif_addr_lock_bh(bp->dev);
5046
5047         clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5048
5049         /* Send rx_mode command again if was requested */
5050         if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
5051                 bnx2x_set_storm_rx_mode(bp);
5052         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
5053                                     &bp->sp_state))
5054                 bnx2x_set_iscsi_eth_rx_mode(bp, true);
5055         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
5056                                     &bp->sp_state))
5057                 bnx2x_set_iscsi_eth_rx_mode(bp, false);
5058
5059         netif_addr_unlock_bh(bp->dev);
5060 }
5061
5062 static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
5063                                               union event_ring_elem *elem)
5064 {
5065         if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
5066                 DP(BNX2X_MSG_SP,
5067                    "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
5068                    elem->message.data.vif_list_event.func_bit_map);
5069                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
5070                         elem->message.data.vif_list_event.func_bit_map);
5071         } else if (elem->message.data.vif_list_event.echo ==
5072                    VIF_LIST_RULE_SET) {
5073                 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
5074                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
5075         }
5076 }
5077
5078 /* called with rtnl_lock */
5079 static void bnx2x_after_function_update(struct bnx2x *bp)
5080 {
5081         int q, rc;
5082         struct bnx2x_fastpath *fp;
5083         struct bnx2x_queue_state_params queue_params = {NULL};
5084         struct bnx2x_queue_update_params *q_update_params =
5085                 &queue_params.params.update;
5086
5087         /* Send Q update command with afex vlan removal values for all Qs */
5088         queue_params.cmd = BNX2X_Q_CMD_UPDATE;
5089
5090         /* set silent vlan removal values according to vlan mode */
5091         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
5092                   &q_update_params->update_flags);
5093         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
5094                   &q_update_params->update_flags);
5095         __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5096
5097         /* in access mode mark mask and value are 0 to strip all vlans */
5098         if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
5099                 q_update_params->silent_removal_value = 0;
5100                 q_update_params->silent_removal_mask = 0;
5101         } else {
5102                 q_update_params->silent_removal_value =
5103                         (bp->afex_def_vlan_tag & VLAN_VID_MASK);
5104                 q_update_params->silent_removal_mask = VLAN_VID_MASK;
5105         }
5106
5107         for_each_eth_queue(bp, q) {
5108                 /* Set the appropriate Queue object */
5109                 fp = &bp->fp[q];
5110                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5111
5112                 /* send the ramrod */
5113                 rc = bnx2x_queue_state_change(bp, &queue_params);
5114                 if (rc < 0)
5115                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5116                                   q);
5117         }
5118
5119         if (!NO_FCOE(bp) && CNIC_ENABLED(bp)) {
5120                 fp = &bp->fp[FCOE_IDX(bp)];
5121                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5122
5123                 /* clear pending completion bit */
5124                 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5125
5126                 /* mark latest Q bit */
5127                 smp_mb__before_clear_bit();
5128                 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
5129                 smp_mb__after_clear_bit();
5130
5131                 /* send Q update ramrod for FCoE Q */
5132                 rc = bnx2x_queue_state_change(bp, &queue_params);
5133                 if (rc < 0)
5134                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5135                                   q);
5136         } else {
5137                 /* If no FCoE ring - ACK MCP now */
5138                 bnx2x_link_report(bp);
5139                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5140         }
5141 }
5142
5143 static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
5144         struct bnx2x *bp, u32 cid)
5145 {
5146         DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
5147
5148         if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp)))
5149                 return &bnx2x_fcoe_sp_obj(bp, q_obj);
5150         else
5151                 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
5152 }
5153
5154 static void bnx2x_eq_int(struct bnx2x *bp)
5155 {
5156         u16 hw_cons, sw_cons, sw_prod;
5157         union event_ring_elem *elem;
5158         u8 echo;
5159         u32 cid;
5160         u8 opcode;
5161         int rc, spqe_cnt = 0;
5162         struct bnx2x_queue_sp_obj *q_obj;
5163         struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
5164         struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
5165
5166         hw_cons = le16_to_cpu(*bp->eq_cons_sb);
5167
5168         /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
5169          * when we get the next-page we need to adjust so the loop
5170          * condition below will be met. The next element is the size of a
5171          * regular element and hence incrementing by 1
5172          */
5173         if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
5174                 hw_cons++;
5175
5176         /* This function may never run in parallel with itself for a
5177          * specific bp, thus there is no need in "paired" read memory
5178          * barrier here.
5179          */
5180         sw_cons = bp->eq_cons;
5181         sw_prod = bp->eq_prod;
5182
5183         DP(BNX2X_MSG_SP, "EQ:  hw_cons %u  sw_cons %u bp->eq_spq_left %x\n",
5184                         hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
5185
5186         for (; sw_cons != hw_cons;
5187               sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
5188
5189                 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
5190
5191                 rc = bnx2x_iov_eq_sp_event(bp, elem);
5192                 if (!rc) {
5193                         DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n",
5194                            rc);
5195                         goto next_spqe;
5196                 }
5197
5198                 /* elem CID originates from FW; actually LE */
5199                 cid = SW_CID((__force __le32)
5200                              elem->message.data.cfc_del_event.cid);
5201                 opcode = elem->message.opcode;
5202
5203                 /* handle eq element */
5204                 switch (opcode) {
5205                 case EVENT_RING_OPCODE_VF_PF_CHANNEL:
5206                         DP(BNX2X_MSG_IOV, "vf pf channel element on eq\n");
5207                         bnx2x_vf_mbx(bp, &elem->message.data.vf_pf_event);
5208                         continue;
5209
5210                 case EVENT_RING_OPCODE_STAT_QUERY:
5211                         DP(BNX2X_MSG_SP | BNX2X_MSG_STATS,
5212                            "got statistics comp event %d\n",
5213                            bp->stats_comp++);
5214                         /* nothing to do with stats comp */
5215                         goto next_spqe;
5216
5217                 case EVENT_RING_OPCODE_CFC_DEL:
5218                         /* handle according to cid range */
5219                         /*
5220                          * we may want to verify here that the bp state is
5221                          * HALTING
5222                          */
5223                         DP(BNX2X_MSG_SP,
5224                            "got delete ramrod for MULTI[%d]\n", cid);
5225
5226                         if (CNIC_LOADED(bp) &&
5227                             !bnx2x_cnic_handle_cfc_del(bp, cid, elem))
5228                                 goto next_spqe;
5229
5230                         q_obj = bnx2x_cid_to_q_obj(bp, cid);
5231
5232                         if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
5233                                 break;
5234
5235                         goto next_spqe;
5236
5237                 case EVENT_RING_OPCODE_STOP_TRAFFIC:
5238                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
5239                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
5240                         if (f_obj->complete_cmd(bp, f_obj,
5241                                                 BNX2X_F_CMD_TX_STOP))
5242                                 break;
5243                         goto next_spqe;
5244
5245                 case EVENT_RING_OPCODE_START_TRAFFIC:
5246                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
5247                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
5248                         if (f_obj->complete_cmd(bp, f_obj,
5249                                                 BNX2X_F_CMD_TX_START))
5250                                 break;
5251                         goto next_spqe;
5252
5253                 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
5254                         echo = elem->message.data.function_update_event.echo;
5255                         if (echo == SWITCH_UPDATE) {
5256                                 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5257                                    "got FUNC_SWITCH_UPDATE ramrod\n");
5258                                 if (f_obj->complete_cmd(
5259                                         bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE))
5260                                         break;
5261
5262                         } else {
5263                                 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
5264                                    "AFEX: ramrod completed FUNCTION_UPDATE\n");
5265                                 f_obj->complete_cmd(bp, f_obj,
5266                                                     BNX2X_F_CMD_AFEX_UPDATE);
5267
5268                                 /* We will perform the Queues update from
5269                                  * sp_rtnl task as all Queue SP operations
5270                                  * should run under rtnl_lock.
5271                                  */
5272                                 smp_mb__before_clear_bit();
5273                                 set_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE,
5274                                         &bp->sp_rtnl_state);
5275                                 smp_mb__after_clear_bit();
5276
5277                                 schedule_delayed_work(&bp->sp_rtnl_task, 0);
5278                         }
5279
5280                         goto next_spqe;
5281
5282                 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
5283                         f_obj->complete_cmd(bp, f_obj,
5284                                             BNX2X_F_CMD_AFEX_VIFLISTS);
5285                         bnx2x_after_afex_vif_lists(bp, elem);
5286                         goto next_spqe;
5287                 case EVENT_RING_OPCODE_FUNCTION_START:
5288                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5289                            "got FUNC_START ramrod\n");
5290                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
5291                                 break;
5292
5293                         goto next_spqe;
5294
5295                 case EVENT_RING_OPCODE_FUNCTION_STOP:
5296                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5297                            "got FUNC_STOP ramrod\n");
5298                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
5299                                 break;
5300
5301                         goto next_spqe;
5302                 }
5303
5304                 switch (opcode | bp->state) {
5305                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5306                       BNX2X_STATE_OPEN):
5307                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5308                       BNX2X_STATE_OPENING_WAIT4_PORT):
5309                         cid = elem->message.data.eth_event.echo &
5310                                 BNX2X_SWCID_MASK;
5311                         DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
5312                            cid);
5313                         rss_raw->clear_pending(rss_raw);
5314                         break;
5315
5316                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
5317                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
5318                 case (EVENT_RING_OPCODE_SET_MAC |
5319                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5320                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5321                       BNX2X_STATE_OPEN):
5322                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5323                       BNX2X_STATE_DIAG):
5324                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5325                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5326                         DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n");
5327                         bnx2x_handle_classification_eqe(bp, elem);
5328                         break;
5329
5330                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5331                       BNX2X_STATE_OPEN):
5332                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5333                       BNX2X_STATE_DIAG):
5334                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5335                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5336                         DP(BNX2X_MSG_SP, "got mcast ramrod\n");
5337                         bnx2x_handle_mcast_eqe(bp);
5338                         break;
5339
5340                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5341                       BNX2X_STATE_OPEN):
5342                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5343                       BNX2X_STATE_DIAG):
5344                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5345                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5346                         DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
5347                         bnx2x_handle_rx_mode_eqe(bp);
5348                         break;
5349                 default:
5350                         /* unknown event log error and continue */
5351                         BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
5352                                   elem->message.opcode, bp->state);
5353                 }
5354 next_spqe:
5355                 spqe_cnt++;
5356         } /* for */
5357
5358         smp_mb__before_atomic_inc();
5359         atomic_add(spqe_cnt, &bp->eq_spq_left);
5360
5361         bp->eq_cons = sw_cons;
5362         bp->eq_prod = sw_prod;
5363         /* Make sure that above mem writes were issued towards the memory */
5364         smp_wmb();
5365
5366         /* update producer */
5367         bnx2x_update_eq_prod(bp, bp->eq_prod);
5368 }
5369
5370 static void bnx2x_sp_task(struct work_struct *work)
5371 {
5372         struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
5373
5374         DP(BNX2X_MSG_SP, "sp task invoked\n");
5375
5376         /* make sure the atomic interrupt_occurred has been written */
5377         smp_rmb();
5378         if (atomic_read(&bp->interrupt_occurred)) {
5379
5380                 /* what work needs to be performed? */
5381                 u16 status = bnx2x_update_dsb_idx(bp);
5382
5383                 DP(BNX2X_MSG_SP, "status %x\n", status);
5384                 DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n");
5385                 atomic_set(&bp->interrupt_occurred, 0);
5386
5387                 /* HW attentions */
5388                 if (status & BNX2X_DEF_SB_ATT_IDX) {
5389                         bnx2x_attn_int(bp);
5390                         status &= ~BNX2X_DEF_SB_ATT_IDX;
5391                 }
5392
5393                 /* SP events: STAT_QUERY and others */
5394                 if (status & BNX2X_DEF_SB_IDX) {
5395                         struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
5396
5397                 if (FCOE_INIT(bp) &&
5398                             (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5399                                 /* Prevent local bottom-halves from running as
5400                                  * we are going to change the local NAPI list.
5401                                  */
5402                                 local_bh_disable();
5403                                 napi_schedule(&bnx2x_fcoe(bp, napi));
5404                                 local_bh_enable();
5405                         }
5406
5407                         /* Handle EQ completions */
5408                         bnx2x_eq_int(bp);
5409                         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5410                                      le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5411
5412                         status &= ~BNX2X_DEF_SB_IDX;
5413                 }
5414
5415                 /* if status is non zero then perhaps something went wrong */
5416                 if (unlikely(status))
5417                         DP(BNX2X_MSG_SP,
5418                            "got an unknown interrupt! (status 0x%x)\n", status);
5419
5420                 /* ack status block only if something was actually handled */
5421                 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5422                              le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
5423         }
5424
5425         /* must be called after the EQ processing (since eq leads to sriov
5426          * ramrod completion flows).
5427          * This flow may have been scheduled by the arrival of a ramrod
5428          * completion, or by the sriov code rescheduling itself.
5429          */
5430         bnx2x_iov_sp_task(bp);
5431
5432         /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5433         if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
5434                                &bp->sp_state)) {
5435                 bnx2x_link_report(bp);
5436                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5437         }
5438 }
5439
5440 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
5441 {
5442         struct net_device *dev = dev_instance;
5443         struct bnx2x *bp = netdev_priv(dev);
5444
5445         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5446                      IGU_INT_DISABLE, 0);
5447
5448 #ifdef BNX2X_STOP_ON_ERROR
5449         if (unlikely(bp->panic))
5450                 return IRQ_HANDLED;
5451 #endif
5452
5453         if (CNIC_LOADED(bp)) {
5454                 struct cnic_ops *c_ops;
5455
5456                 rcu_read_lock();
5457                 c_ops = rcu_dereference(bp->cnic_ops);
5458                 if (c_ops)
5459                         c_ops->cnic_handler(bp->cnic_data, NULL);
5460                 rcu_read_unlock();
5461         }
5462
5463         /* schedule sp task to perform default status block work, ack
5464          * attentions and enable interrupts.
5465          */
5466         bnx2x_schedule_sp_task(bp);
5467
5468         return IRQ_HANDLED;
5469 }
5470
5471 /* end of slow path */
5472
5473 void bnx2x_drv_pulse(struct bnx2x *bp)
5474 {
5475         SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5476                  bp->fw_drv_pulse_wr_seq);
5477 }
5478
5479 static void bnx2x_timer(unsigned long data)
5480 {
5481         struct bnx2x *bp = (struct bnx2x *) data;
5482
5483         if (!netif_running(bp->dev))
5484                 return;
5485
5486         if (IS_PF(bp) &&
5487             !BP_NOMCP(bp)) {
5488                 int mb_idx = BP_FW_MB_IDX(bp);
5489                 u16 drv_pulse;
5490                 u16 mcp_pulse;
5491
5492                 ++bp->fw_drv_pulse_wr_seq;
5493                 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
5494                 drv_pulse = bp->fw_drv_pulse_wr_seq;
5495                 bnx2x_drv_pulse(bp);
5496
5497                 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
5498                              MCP_PULSE_SEQ_MASK);
5499                 /* The delta between driver pulse and mcp response
5500                  * should not get too big. If the MFW is more than 5 pulses
5501                  * behind, we should worry about it enough to generate an error
5502                  * log.
5503                  */
5504                 if (((drv_pulse - mcp_pulse) & MCP_PULSE_SEQ_MASK) > 5)
5505                         BNX2X_ERR("MFW seems hanged: drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
5506                                   drv_pulse, mcp_pulse);
5507         }
5508
5509         if (bp->state == BNX2X_STATE_OPEN)
5510                 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
5511
5512         /* sample pf vf bulletin board for new posts from pf */
5513         if (IS_VF(bp))
5514                 bnx2x_timer_sriov(bp);
5515
5516         mod_timer(&bp->timer, jiffies + bp->current_interval);
5517 }
5518
5519 /* end of Statistics */
5520
5521 /* nic init */
5522
5523 /*
5524  * nic init service functions
5525  */
5526
5527 static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
5528 {
5529         u32 i;
5530         if (!(len%4) && !(addr%4))
5531                 for (i = 0; i < len; i += 4)
5532                         REG_WR(bp, addr + i, fill);
5533         else
5534                 for (i = 0; i < len; i++)
5535                         REG_WR8(bp, addr + i, fill);
5536 }
5537
5538 /* helper: writes FP SP data to FW - data_size in dwords */
5539 static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5540                                 int fw_sb_id,
5541                                 u32 *sb_data_p,
5542                                 u32 data_size)
5543 {
5544         int index;
5545         for (index = 0; index < data_size; index++)
5546                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5547                         CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
5548                         sizeof(u32)*index,
5549                         *(sb_data_p + index));
5550 }
5551
5552 static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
5553 {
5554         u32 *sb_data_p;
5555         u32 data_size = 0;
5556         struct hc_status_block_data_e2 sb_data_e2;
5557         struct hc_status_block_data_e1x sb_data_e1x;
5558
5559         /* disable the function first */
5560         if (!CHIP_IS_E1x(bp)) {
5561                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5562                 sb_data_e2.common.state = SB_DISABLED;
5563                 sb_data_e2.common.p_func.vf_valid = false;
5564                 sb_data_p = (u32 *)&sb_data_e2;
5565                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5566         } else {
5567                 memset(&sb_data_e1x, 0,
5568                        sizeof(struct hc_status_block_data_e1x));
5569                 sb_data_e1x.common.state = SB_DISABLED;
5570                 sb_data_e1x.common.p_func.vf_valid = false;
5571                 sb_data_p = (u32 *)&sb_data_e1x;
5572                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5573         }
5574         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5575
5576         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5577                         CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5578                         CSTORM_STATUS_BLOCK_SIZE);
5579         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5580                         CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5581                         CSTORM_SYNC_BLOCK_SIZE);
5582 }
5583
5584 /* helper:  writes SP SB data to FW */
5585 static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
5586                 struct hc_sp_status_block_data *sp_sb_data)
5587 {
5588         int func = BP_FUNC(bp);
5589         int i;
5590         for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5591                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5592                         CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
5593                         i*sizeof(u32),
5594                         *((u32 *)sp_sb_data + i));
5595 }
5596
5597 static void bnx2x_zero_sp_sb(struct bnx2x *bp)
5598 {
5599         int func = BP_FUNC(bp);
5600         struct hc_sp_status_block_data sp_sb_data;
5601         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5602
5603         sp_sb_data.state = SB_DISABLED;
5604         sp_sb_data.p_func.vf_valid = false;
5605
5606         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5607
5608         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5609                         CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
5610                         CSTORM_SP_STATUS_BLOCK_SIZE);
5611         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5612                         CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5613                         CSTORM_SP_SYNC_BLOCK_SIZE);
5614 }
5615
5616 static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
5617                                            int igu_sb_id, int igu_seg_id)
5618 {
5619         hc_sm->igu_sb_id = igu_sb_id;
5620         hc_sm->igu_seg_id = igu_seg_id;
5621         hc_sm->timer_value = 0xFF;
5622         hc_sm->time_to_expire = 0xFFFFFFFF;
5623 }
5624
5625 /* allocates state machine ids. */
5626 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
5627 {
5628         /* zero out state machine indices */
5629         /* rx indices */
5630         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5631
5632         /* tx indices */
5633         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5634         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5635         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5636         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5637
5638         /* map indices */
5639         /* rx indices */
5640         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5641                 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5642
5643         /* tx indices */
5644         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5645                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5646         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5647                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5648         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5649                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5650         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5651                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5652 }
5653
5654 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
5655                           u8 vf_valid, int fw_sb_id, int igu_sb_id)
5656 {
5657         int igu_seg_id;
5658
5659         struct hc_status_block_data_e2 sb_data_e2;
5660         struct hc_status_block_data_e1x sb_data_e1x;
5661         struct hc_status_block_sm  *hc_sm_p;
5662         int data_size;
5663         u32 *sb_data_p;
5664
5665         if (CHIP_INT_MODE_IS_BC(bp))
5666                 igu_seg_id = HC_SEG_ACCESS_NORM;
5667         else
5668                 igu_seg_id = IGU_SEG_ACCESS_NORM;
5669
5670         bnx2x_zero_fp_sb(bp, fw_sb_id);
5671
5672         if (!CHIP_IS_E1x(bp)) {
5673                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5674                 sb_data_e2.common.state = SB_ENABLED;
5675                 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5676                 sb_data_e2.common.p_func.vf_id = vfid;
5677                 sb_data_e2.common.p_func.vf_valid = vf_valid;
5678                 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5679                 sb_data_e2.common.same_igu_sb_1b = true;
5680                 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5681                 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5682                 hc_sm_p = sb_data_e2.common.state_machine;
5683                 sb_data_p = (u32 *)&sb_data_e2;
5684                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5685                 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
5686         } else {
5687                 memset(&sb_data_e1x, 0,
5688                        sizeof(struct hc_status_block_data_e1x));
5689                 sb_data_e1x.common.state = SB_ENABLED;
5690                 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5691                 sb_data_e1x.common.p_func.vf_id = 0xff;
5692                 sb_data_e1x.common.p_func.vf_valid = false;
5693                 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5694                 sb_data_e1x.common.same_igu_sb_1b = true;
5695                 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5696                 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5697                 hc_sm_p = sb_data_e1x.common.state_machine;
5698                 sb_data_p = (u32 *)&sb_data_e1x;
5699                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5700                 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
5701         }
5702
5703         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5704                                        igu_sb_id, igu_seg_id);
5705         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5706                                        igu_sb_id, igu_seg_id);
5707
5708         DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
5709
5710         /* write indices to HW - PCI guarantees endianity of regpairs */
5711         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5712 }
5713
5714 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
5715                                      u16 tx_usec, u16 rx_usec)
5716 {
5717         bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
5718                                     false, rx_usec);
5719         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5720                                        HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
5721                                        tx_usec);
5722         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5723                                        HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
5724                                        tx_usec);
5725         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5726                                        HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
5727                                        tx_usec);
5728 }
5729
5730 static void bnx2x_init_def_sb(struct bnx2x *bp)
5731 {
5732         struct host_sp_status_block *def_sb = bp->def_status_blk;
5733         dma_addr_t mapping = bp->def_status_blk_mapping;
5734         int igu_sp_sb_index;
5735         int igu_seg_id;
5736         int port = BP_PORT(bp);
5737         int func = BP_FUNC(bp);
5738         int reg_offset, reg_offset_en5;
5739         u64 section;
5740         int index;
5741         struct hc_sp_status_block_data sp_sb_data;
5742         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5743
5744         if (CHIP_INT_MODE_IS_BC(bp)) {
5745                 igu_sp_sb_index = DEF_SB_IGU_ID;
5746                 igu_seg_id = HC_SEG_ACCESS_DEF;
5747         } else {
5748                 igu_sp_sb_index = bp->igu_dsb_id;
5749                 igu_seg_id = IGU_SEG_ACCESS_DEF;
5750         }
5751
5752         /* ATTN */
5753         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5754                                             atten_status_block);
5755         def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
5756
5757         bp->attn_state = 0;
5758
5759         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5760                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
5761         reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5762                                  MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
5763         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5764                 int sindex;
5765                 /* take care of sig[0]..sig[4] */
5766                 for (sindex = 0; sindex < 4; sindex++)
5767                         bp->attn_group[index].sig[sindex] =
5768                            REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
5769
5770                 if (!CHIP_IS_E1x(bp))
5771                         /*
5772                          * enable5 is separate from the rest of the registers,
5773                          * and therefore the address skip is 4
5774                          * and not 16 between the different groups
5775                          */
5776                         bp->attn_group[index].sig[4] = REG_RD(bp,
5777                                         reg_offset_en5 + 0x4*index);
5778                 else
5779                         bp->attn_group[index].sig[4] = 0;
5780         }
5781
5782         if (bp->common.int_block == INT_BLOCK_HC) {
5783                 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
5784                                      HC_REG_ATTN_MSG0_ADDR_L);
5785
5786                 REG_WR(bp, reg_offset, U64_LO(section));
5787                 REG_WR(bp, reg_offset + 4, U64_HI(section));
5788         } else if (!CHIP_IS_E1x(bp)) {
5789                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5790                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5791         }
5792
5793         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5794                                             sp_sb);
5795
5796         bnx2x_zero_sp_sb(bp);
5797
5798         /* PCI guarantees endianity of regpairs */
5799         sp_sb_data.state                = SB_ENABLED;
5800         sp_sb_data.host_sb_addr.lo      = U64_LO(section);
5801         sp_sb_data.host_sb_addr.hi      = U64_HI(section);
5802         sp_sb_data.igu_sb_id            = igu_sp_sb_index;
5803         sp_sb_data.igu_seg_id           = igu_seg_id;
5804         sp_sb_data.p_func.pf_id         = func;
5805         sp_sb_data.p_func.vnic_id       = BP_VN(bp);
5806         sp_sb_data.p_func.vf_id         = 0xff;
5807
5808         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5809
5810         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5811 }
5812
5813 void bnx2x_update_coalesce(struct bnx2x *bp)
5814 {
5815         int i;
5816
5817         for_each_eth_queue(bp, i)
5818                 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
5819                                          bp->tx_ticks, bp->rx_ticks);
5820 }
5821
5822 static void bnx2x_init_sp_ring(struct bnx2x *bp)
5823 {
5824         spin_lock_init(&bp->spq_lock);
5825         atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
5826
5827         bp->spq_prod_idx = 0;
5828         bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
5829         bp->spq_prod_bd = bp->spq;
5830         bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
5831 }
5832
5833 static void bnx2x_init_eq_ring(struct bnx2x *bp)
5834 {
5835         int i;
5836         for (i = 1; i <= NUM_EQ_PAGES; i++) {
5837                 union event_ring_elem *elem =
5838                         &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
5839
5840                 elem->next_page.addr.hi =
5841                         cpu_to_le32(U64_HI(bp->eq_mapping +
5842                                    BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
5843                 elem->next_page.addr.lo =
5844                         cpu_to_le32(U64_LO(bp->eq_mapping +
5845                                    BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
5846         }
5847         bp->eq_cons = 0;
5848         bp->eq_prod = NUM_EQ_DESC;
5849         bp->eq_cons_sb = BNX2X_EQ_INDEX;
5850         /* we want a warning message before it gets wrought... */
5851         atomic_set(&bp->eq_spq_left,
5852                 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
5853 }
5854
5855 /* called with netif_addr_lock_bh() */
5856 int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
5857                         unsigned long rx_mode_flags,
5858                         unsigned long rx_accept_flags,
5859                         unsigned long tx_accept_flags,
5860                         unsigned long ramrod_flags)
5861 {
5862         struct bnx2x_rx_mode_ramrod_params ramrod_param;
5863         int rc;
5864
5865         memset(&ramrod_param, 0, sizeof(ramrod_param));
5866
5867         /* Prepare ramrod parameters */
5868         ramrod_param.cid = 0;
5869         ramrod_param.cl_id = cl_id;
5870         ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
5871         ramrod_param.func_id = BP_FUNC(bp);
5872
5873         ramrod_param.pstate = &bp->sp_state;
5874         ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
5875
5876         ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
5877         ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
5878
5879         set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5880
5881         ramrod_param.ramrod_flags = ramrod_flags;
5882         ramrod_param.rx_mode_flags = rx_mode_flags;
5883
5884         ramrod_param.rx_accept_flags = rx_accept_flags;
5885         ramrod_param.tx_accept_flags = tx_accept_flags;
5886
5887         rc = bnx2x_config_rx_mode(bp, &ramrod_param);
5888         if (rc < 0) {
5889                 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
5890                 return rc;
5891         }
5892
5893         return 0;
5894 }
5895
5896 static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode,
5897                                    unsigned long *rx_accept_flags,
5898                                    unsigned long *tx_accept_flags)
5899 {
5900         /* Clear the flags first */
5901         *rx_accept_flags = 0;
5902         *tx_accept_flags = 0;
5903
5904         switch (rx_mode) {
5905         case BNX2X_RX_MODE_NONE:
5906                 /*
5907                  * 'drop all' supersedes any accept flags that may have been
5908                  * passed to the function.
5909                  */
5910                 break;
5911         case BNX2X_RX_MODE_NORMAL:
5912                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
5913                 __set_bit(BNX2X_ACCEPT_MULTICAST, rx_accept_flags);
5914                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
5915
5916                 /* internal switching mode */
5917                 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
5918                 __set_bit(BNX2X_ACCEPT_MULTICAST, tx_accept_flags);
5919                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
5920
5921                 break;
5922         case BNX2X_RX_MODE_ALLMULTI:
5923                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
5924                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
5925                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
5926
5927                 /* internal switching mode */
5928                 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
5929                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
5930                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
5931
5932                 break;
5933         case BNX2X_RX_MODE_PROMISC:
5934                 /* According to definition of SI mode, iface in promisc mode
5935                  * should receive matched and unmatched (in resolution of port)
5936                  * unicast packets.
5937                  */
5938                 __set_bit(BNX2X_ACCEPT_UNMATCHED, rx_accept_flags);
5939                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
5940                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
5941                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
5942
5943                 /* internal switching mode */
5944                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
5945                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
5946
5947                 if (IS_MF_SI(bp))
5948                         __set_bit(BNX2X_ACCEPT_ALL_UNICAST, tx_accept_flags);
5949                 else
5950                         __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
5951
5952                 break;
5953         default:
5954                 BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode);
5955                 return -EINVAL;
5956         }
5957
5958         /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
5959         if (bp->rx_mode != BNX2X_RX_MODE_NONE) {
5960                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
5961                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
5962         }
5963
5964         return 0;
5965 }
5966
5967 /* called with netif_addr_lock_bh() */
5968 int bnx2x_set_storm_rx_mode(struct bnx2x *bp)
5969 {
5970         unsigned long rx_mode_flags = 0, ramrod_flags = 0;
5971         unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
5972         int rc;
5973
5974         if (!NO_FCOE(bp))
5975                 /* Configure rx_mode of FCoE Queue */
5976                 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
5977
5978         rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags,
5979                                      &tx_accept_flags);
5980         if (rc)
5981                 return rc;
5982
5983         __set_bit(RAMROD_RX, &ramrod_flags);
5984         __set_bit(RAMROD_TX, &ramrod_flags);
5985
5986         return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags,
5987                                    rx_accept_flags, tx_accept_flags,
5988                                    ramrod_flags);
5989 }
5990
5991 static void bnx2x_init_internal_common(struct bnx2x *bp)
5992 {
5993         int i;
5994
5995         if (IS_MF_SI(bp))
5996                 /*
5997                  * In switch independent mode, the TSTORM needs to accept
5998                  * packets that failed classification, since approximate match
5999                  * mac addresses aren't written to NIG LLH
6000                  */
6001                 REG_WR8(bp, BAR_TSTRORM_INTMEM +
6002                             TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2);
6003         else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */
6004                 REG_WR8(bp, BAR_TSTRORM_INTMEM +
6005                             TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0);
6006
6007         /* Zero this manually as its initialization is
6008            currently missing in the initTool */
6009         for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
6010                 REG_WR(bp, BAR_USTRORM_INTMEM +
6011                        USTORM_AGG_DATA_OFFSET + i * 4, 0);
6012         if (!CHIP_IS_E1x(bp)) {
6013                 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
6014                         CHIP_INT_MODE_IS_BC(bp) ?
6015                         HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
6016         }
6017 }
6018
6019 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
6020 {
6021         switch (load_code) {
6022         case FW_MSG_CODE_DRV_LOAD_COMMON:
6023         case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
6024                 bnx2x_init_internal_common(bp);
6025                 /* no break */
6026
6027         case FW_MSG_CODE_DRV_LOAD_PORT:
6028                 /* nothing to do */
6029                 /* no break */
6030
6031         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
6032                 /* internal memory per function is
6033                    initialized inside bnx2x_pf_init */
6034                 break;
6035
6036         default:
6037                 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
6038                 break;
6039         }
6040 }
6041
6042 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
6043 {
6044         return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp);
6045 }
6046
6047 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
6048 {
6049         return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp);
6050 }
6051
6052 static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
6053 {
6054         if (CHIP_IS_E1x(fp->bp))
6055                 return BP_L_ID(fp->bp) + fp->index;
6056         else    /* We want Client ID to be the same as IGU SB ID for 57712 */
6057                 return bnx2x_fp_igu_sb_id(fp);
6058 }
6059
6060 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
6061 {
6062         struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
6063         u8 cos;
6064         unsigned long q_type = 0;
6065         u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
6066         fp->rx_queue = fp_idx;
6067         fp->cid = fp_idx;
6068         fp->cl_id = bnx2x_fp_cl_id(fp);
6069         fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
6070         fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
6071         /* qZone id equals to FW (per path) client id */
6072         fp->cl_qzone_id  = bnx2x_fp_qzone_id(fp);
6073
6074         /* init shortcut */
6075         fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
6076
6077         /* Setup SB indices */
6078         fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
6079
6080         /* Configure Queue State object */
6081         __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6082         __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6083
6084         BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
6085
6086         /* init tx data */
6087         for_each_cos_in_tx_queue(fp, cos) {
6088                 bnx2x_init_txdata(bp, fp->txdata_ptr[cos],
6089                                   CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp),
6090                                   FP_COS_TO_TXQ(fp, cos, bp),
6091                                   BNX2X_TX_SB_INDEX_BASE + cos, fp);
6092                 cids[cos] = fp->txdata_ptr[cos]->cid;
6093         }
6094
6095         /* nothing more for vf to do here */
6096         if (IS_VF(bp))
6097                 return;
6098
6099         bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
6100                       fp->fw_sb_id, fp->igu_sb_id);
6101         bnx2x_update_fpsb_idx(fp);
6102         bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids,
6103                              fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6104                              bnx2x_sp_mapping(bp, q_rdata), q_type);
6105
6106         /**
6107          * Configure classification DBs: Always enable Tx switching
6108          */
6109         bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
6110
6111         DP(NETIF_MSG_IFUP,
6112            "queue[%d]:  bnx2x_init_sb(%p,%p)  cl_id %d  fw_sb %d  igu_sb %d\n",
6113            fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6114            fp->igu_sb_id);
6115 }
6116
6117 static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
6118 {
6119         int i;
6120
6121         for (i = 1; i <= NUM_TX_RINGS; i++) {
6122                 struct eth_tx_next_bd *tx_next_bd =
6123                         &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
6124
6125                 tx_next_bd->addr_hi =
6126                         cpu_to_le32(U64_HI(txdata->tx_desc_mapping +
6127                                     BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6128                 tx_next_bd->addr_lo =
6129                         cpu_to_le32(U64_LO(txdata->tx_desc_mapping +
6130                                     BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6131         }
6132
6133         *txdata->tx_cons_sb = cpu_to_le16(0);
6134
6135         SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
6136         txdata->tx_db.data.zero_fill1 = 0;
6137         txdata->tx_db.data.prod = 0;
6138
6139         txdata->tx_pkt_prod = 0;
6140         txdata->tx_pkt_cons = 0;
6141         txdata->tx_bd_prod = 0;
6142         txdata->tx_bd_cons = 0;
6143         txdata->tx_pkt = 0;
6144 }
6145
6146 static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp)
6147 {
6148         int i;
6149
6150         for_each_tx_queue_cnic(bp, i)
6151                 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]);
6152 }
6153
6154 static void bnx2x_init_tx_rings(struct bnx2x *bp)
6155 {
6156         int i;
6157         u8 cos;
6158
6159         for_each_eth_queue(bp, i)
6160                 for_each_cos_in_tx_queue(&bp->fp[i], cos)
6161                         bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]);
6162 }
6163
6164 void bnx2x_nic_init_cnic(struct bnx2x *bp)
6165 {
6166         if (!NO_FCOE(bp))
6167                 bnx2x_init_fcoe_fp(bp);
6168
6169         bnx2x_init_sb(bp, bp->cnic_sb_mapping,
6170                       BNX2X_VF_ID_INVALID, false,
6171                       bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
6172
6173         /* ensure status block indices were read */
6174         rmb();
6175         bnx2x_init_rx_rings_cnic(bp);
6176         bnx2x_init_tx_rings_cnic(bp);
6177
6178         /* flush all */
6179         mb();
6180         mmiowb();
6181 }
6182
6183 void bnx2x_pre_irq_nic_init(struct bnx2x *bp)
6184 {
6185         int i;
6186
6187         /* Setup NIC internals and enable interrupts */
6188         for_each_eth_queue(bp, i)
6189                 bnx2x_init_eth_fp(bp, i);
6190
6191         /* ensure status block indices were read */
6192         rmb();
6193         bnx2x_init_rx_rings(bp);
6194         bnx2x_init_tx_rings(bp);
6195
6196         if (IS_PF(bp)) {
6197                 /* Initialize MOD_ABS interrupts */
6198                 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
6199                                        bp->common.shmem_base,
6200                                        bp->common.shmem2_base, BP_PORT(bp));
6201
6202                 /* initialize the default status block and sp ring */
6203                 bnx2x_init_def_sb(bp);
6204                 bnx2x_update_dsb_idx(bp);
6205                 bnx2x_init_sp_ring(bp);
6206         } else {
6207                 bnx2x_memset_stats(bp);
6208         }
6209 }
6210
6211 void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code)
6212 {
6213         bnx2x_init_eq_ring(bp);
6214         bnx2x_init_internal(bp, load_code);
6215         bnx2x_pf_init(bp);
6216         bnx2x_stats_init(bp);
6217
6218         /* flush all before enabling interrupts */
6219         mb();
6220         mmiowb();
6221
6222         bnx2x_int_enable(bp);
6223
6224         /* Check for SPIO5 */
6225         bnx2x_attn_int_deasserted0(bp,
6226                 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
6227                                    AEU_INPUTS_ATTN_BITS_SPIO5);
6228 }
6229
6230 /* gzip service functions */
6231 static int bnx2x_gunzip_init(struct bnx2x *bp)
6232 {
6233         bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
6234                                             &bp->gunzip_mapping, GFP_KERNEL);
6235         if (bp->gunzip_buf  == NULL)
6236                 goto gunzip_nomem1;
6237
6238         bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
6239         if (bp->strm  == NULL)
6240                 goto gunzip_nomem2;
6241
6242         bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
6243         if (bp->strm->workspace == NULL)
6244                 goto gunzip_nomem3;
6245
6246         return 0;
6247
6248 gunzip_nomem3:
6249         kfree(bp->strm);
6250         bp->strm = NULL;
6251
6252 gunzip_nomem2:
6253         dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6254                           bp->gunzip_mapping);
6255         bp->gunzip_buf = NULL;
6256
6257 gunzip_nomem1:
6258         BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
6259         return -ENOMEM;
6260 }
6261
6262 static void bnx2x_gunzip_end(struct bnx2x *bp)
6263 {
6264         if (bp->strm) {
6265                 vfree(bp->strm->workspace);
6266                 kfree(bp->strm);
6267                 bp->strm = NULL;
6268         }
6269
6270         if (bp->gunzip_buf) {
6271                 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6272                                   bp->gunzip_mapping);
6273                 bp->gunzip_buf = NULL;
6274         }
6275 }
6276
6277 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
6278 {
6279         int n, rc;
6280
6281         /* check gzip header */
6282         if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
6283                 BNX2X_ERR("Bad gzip header\n");
6284                 return -EINVAL;
6285         }
6286
6287         n = 10;
6288
6289 #define FNAME                           0x8
6290
6291         if (zbuf[3] & FNAME)
6292                 while ((zbuf[n++] != 0) && (n < len));
6293
6294         bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
6295         bp->strm->avail_in = len - n;
6296         bp->strm->next_out = bp->gunzip_buf;
6297         bp->strm->avail_out = FW_BUF_SIZE;
6298
6299         rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
6300         if (rc != Z_OK)
6301                 return rc;
6302
6303         rc = zlib_inflate(bp->strm, Z_FINISH);
6304         if ((rc != Z_OK) && (rc != Z_STREAM_END))
6305                 netdev_err(bp->dev, "Firmware decompression error: %s\n",
6306                            bp->strm->msg);
6307
6308         bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
6309         if (bp->gunzip_outlen & 0x3)
6310                 netdev_err(bp->dev,
6311                            "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
6312                                 bp->gunzip_outlen);
6313         bp->gunzip_outlen >>= 2;
6314
6315         zlib_inflateEnd(bp->strm);
6316
6317         if (rc == Z_STREAM_END)
6318                 return 0;
6319
6320         return rc;
6321 }
6322
6323 /* nic load/unload */
6324
6325 /*
6326  * General service functions
6327  */
6328
6329 /* send a NIG loopback debug packet */
6330 static void bnx2x_lb_pckt(struct bnx2x *bp)
6331 {
6332         u32 wb_write[3];
6333
6334         /* Ethernet source and destination addresses */
6335         wb_write[0] = 0x55555555;
6336         wb_write[1] = 0x55555555;
6337         wb_write[2] = 0x20;             /* SOP */
6338         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6339
6340         /* NON-IP protocol */
6341         wb_write[0] = 0x09000000;
6342         wb_write[1] = 0x55555555;
6343         wb_write[2] = 0x10;             /* EOP, eop_bvalid = 0 */
6344         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6345 }
6346
6347 /* some of the internal memories
6348  * are not directly readable from the driver
6349  * to test them we send debug packets
6350  */
6351 static int bnx2x_int_mem_test(struct bnx2x *bp)
6352 {
6353         int factor;
6354         int count, i;
6355         u32 val = 0;
6356
6357         if (CHIP_REV_IS_FPGA(bp))
6358                 factor = 120;
6359         else if (CHIP_REV_IS_EMUL(bp))
6360                 factor = 200;
6361         else
6362                 factor = 1;
6363
6364         /* Disable inputs of parser neighbor blocks */
6365         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6366         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6367         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6368         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6369
6370         /*  Write 0 to parser credits for CFC search request */
6371         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6372
6373         /* send Ethernet packet */
6374         bnx2x_lb_pckt(bp);
6375
6376         /* TODO do i reset NIG statistic? */
6377         /* Wait until NIG register shows 1 packet of size 0x10 */
6378         count = 1000 * factor;
6379         while (count) {
6380
6381                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6382                 val = *bnx2x_sp(bp, wb_data[0]);
6383                 if (val == 0x10)
6384                         break;
6385
6386                 usleep_range(10000, 20000);
6387                 count--;
6388         }
6389         if (val != 0x10) {
6390                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
6391                 return -1;
6392         }
6393
6394         /* Wait until PRS register shows 1 packet */
6395         count = 1000 * factor;
6396         while (count) {
6397                 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6398                 if (val == 1)
6399                         break;
6400
6401                 usleep_range(10000, 20000);
6402                 count--;
6403         }
6404         if (val != 0x1) {
6405                 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6406                 return -2;
6407         }
6408
6409         /* Reset and init BRB, PRS */
6410         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6411         msleep(50);
6412         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6413         msleep(50);
6414         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6415         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6416
6417         DP(NETIF_MSG_HW, "part2\n");
6418
6419         /* Disable inputs of parser neighbor blocks */
6420         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6421         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6422         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6423         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6424
6425         /* Write 0 to parser credits for CFC search request */
6426         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6427
6428         /* send 10 Ethernet packets */
6429         for (i = 0; i < 10; i++)
6430                 bnx2x_lb_pckt(bp);
6431
6432         /* Wait until NIG register shows 10 + 1
6433            packets of size 11*0x10 = 0xb0 */
6434         count = 1000 * factor;
6435         while (count) {
6436
6437                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6438                 val = *bnx2x_sp(bp, wb_data[0]);
6439                 if (val == 0xb0)
6440                         break;
6441
6442                 usleep_range(10000, 20000);
6443                 count--;
6444         }
6445         if (val != 0xb0) {
6446                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
6447                 return -3;
6448         }
6449
6450         /* Wait until PRS register shows 2 packets */
6451         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6452         if (val != 2)
6453                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
6454
6455         /* Write 1 to parser credits for CFC search request */
6456         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
6457
6458         /* Wait until PRS register shows 3 packets */
6459         msleep(10 * factor);
6460         /* Wait until NIG register shows 1 packet of size 0x10 */
6461         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6462         if (val != 3)
6463                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
6464
6465         /* clear NIG EOP FIFO */
6466         for (i = 0; i < 11; i++)
6467                 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
6468         val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
6469         if (val != 1) {
6470                 BNX2X_ERR("clear of NIG failed\n");
6471                 return -4;
6472         }
6473
6474         /* Reset and init BRB, PRS, NIG */
6475         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6476         msleep(50);
6477         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6478         msleep(50);
6479         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6480         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6481         if (!CNIC_SUPPORT(bp))
6482                 /* set NIC mode */
6483                 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6484
6485         /* Enable inputs of parser neighbor blocks */
6486         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
6487         REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
6488         REG_WR(bp, CFC_REG_DEBUG0, 0x0);
6489         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
6490
6491         DP(NETIF_MSG_HW, "done\n");
6492
6493         return 0; /* OK */
6494 }
6495
6496 static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
6497 {
6498         u32 val;
6499
6500         REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6501         if (!CHIP_IS_E1x(bp))
6502                 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
6503         else
6504                 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
6505         REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6506         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6507         /*
6508          * mask read length error interrupts in brb for parser
6509          * (parsing unit and 'checksum and crc' unit)
6510          * these errors are legal (PU reads fixed length and CAC can cause
6511          * read length error on truncated packets)
6512          */
6513         REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
6514         REG_WR(bp, QM_REG_QM_INT_MASK, 0);
6515         REG_WR(bp, TM_REG_TM_INT_MASK, 0);
6516         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
6517         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
6518         REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
6519 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6520 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
6521         REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
6522         REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
6523         REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
6524 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6525 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
6526         REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
6527         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
6528         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
6529         REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
6530 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6531 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
6532
6533         val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT  |
6534                 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
6535                 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN;
6536         if (!CHIP_IS_E1x(bp))
6537                 val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
6538                         PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED;
6539         REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val);
6540
6541         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
6542         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
6543         REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
6544 /*      REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
6545
6546         if (!CHIP_IS_E1x(bp))
6547                 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
6548                 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
6549
6550         REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
6551         REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
6552 /*      REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
6553         REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18);         /* bit 3,4 masked */
6554 }
6555
6556 static void bnx2x_reset_common(struct bnx2x *bp)
6557 {
6558         u32 val = 0x1400;
6559
6560         /* reset_common */
6561         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6562                0xd3ffff7f);
6563
6564         if (CHIP_IS_E3(bp)) {
6565                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6566                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6567         }
6568
6569         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
6570 }
6571
6572 static void bnx2x_setup_dmae(struct bnx2x *bp)
6573 {
6574         bp->dmae_ready = 0;
6575         spin_lock_init(&bp->dmae_lock);
6576 }
6577
6578 static void bnx2x_init_pxp(struct bnx2x *bp)
6579 {
6580         u16 devctl;
6581         int r_order, w_order;
6582
6583         pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl);
6584         DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
6585         w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6586         if (bp->mrrs == -1)
6587                 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
6588         else {
6589                 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
6590                 r_order = bp->mrrs;
6591         }
6592
6593         bnx2x_init_pxp_arb(bp, r_order, w_order);
6594 }
6595
6596 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
6597 {
6598         int is_required;
6599         u32 val;
6600         int port;
6601
6602         if (BP_NOMCP(bp))
6603                 return;
6604
6605         is_required = 0;
6606         val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
6607               SHARED_HW_CFG_FAN_FAILURE_MASK;
6608
6609         if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
6610                 is_required = 1;
6611
6612         /*
6613          * The fan failure mechanism is usually related to the PHY type since
6614          * the power consumption of the board is affected by the PHY. Currently,
6615          * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6616          */
6617         else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
6618                 for (port = PORT_0; port < PORT_MAX; port++) {
6619                         is_required |=
6620                                 bnx2x_fan_failure_det_req(
6621                                         bp,
6622                                         bp->common.shmem_base,
6623                                         bp->common.shmem2_base,
6624                                         port);
6625                 }
6626
6627         DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
6628
6629         if (is_required == 0)
6630                 return;
6631
6632         /* Fan failure is indicated by SPIO 5 */
6633         bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
6634
6635         /* set to active low mode */
6636         val = REG_RD(bp, MISC_REG_SPIO_INT);
6637         val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
6638         REG_WR(bp, MISC_REG_SPIO_INT, val);
6639
6640         /* enable interrupt to signal the IGU */
6641         val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6642         val |= MISC_SPIO_SPIO5;
6643         REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
6644 }
6645
6646 void bnx2x_pf_disable(struct bnx2x *bp)
6647 {
6648         u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
6649         val &= ~IGU_PF_CONF_FUNC_EN;
6650
6651         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
6652         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6653         REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
6654 }
6655
6656 static void bnx2x__common_init_phy(struct bnx2x *bp)
6657 {
6658         u32 shmem_base[2], shmem2_base[2];
6659         /* Avoid common init in case MFW supports LFA */
6660         if (SHMEM2_RD(bp, size) >
6661             (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
6662                 return;
6663         shmem_base[0] =  bp->common.shmem_base;
6664         shmem2_base[0] = bp->common.shmem2_base;
6665         if (!CHIP_IS_E1x(bp)) {
6666                 shmem_base[1] =
6667                         SHMEM2_RD(bp, other_shmem_base_addr);
6668                 shmem2_base[1] =
6669                         SHMEM2_RD(bp, other_shmem2_base_addr);
6670         }
6671         bnx2x_acquire_phy_lock(bp);
6672         bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
6673                               bp->common.chip_id);
6674         bnx2x_release_phy_lock(bp);
6675 }
6676
6677 /**
6678  * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
6679  *
6680  * @bp:         driver handle
6681  */
6682 static int bnx2x_init_hw_common(struct bnx2x *bp)
6683 {
6684         u32 val;
6685
6686         DP(NETIF_MSG_HW, "starting common init  func %d\n", BP_ABS_FUNC(bp));
6687
6688         /*
6689          * take the RESET lock to protect undi_unload flow from accessing
6690          * registers while we're resetting the chip
6691          */
6692         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
6693
6694         bnx2x_reset_common(bp);
6695         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
6696
6697         val = 0xfffc;
6698         if (CHIP_IS_E3(bp)) {
6699                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6700                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6701         }
6702         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
6703
6704         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
6705
6706         bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
6707
6708         if (!CHIP_IS_E1x(bp)) {
6709                 u8 abs_func_id;
6710
6711                 /**
6712                  * 4-port mode or 2-port mode we need to turn of master-enable
6713                  * for everyone, after that, turn it back on for self.
6714                  * so, we disregard multi-function or not, and always disable
6715                  * for all functions on the given path, this means 0,2,4,6 for
6716                  * path 0 and 1,3,5,7 for path 1
6717                  */
6718                 for (abs_func_id = BP_PATH(bp);
6719                      abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
6720                         if (abs_func_id == BP_ABS_FUNC(bp)) {
6721                                 REG_WR(bp,
6722                                     PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
6723                                     1);
6724                                 continue;
6725                         }
6726
6727                         bnx2x_pretend_func(bp, abs_func_id);
6728                         /* clear pf enable */
6729                         bnx2x_pf_disable(bp);
6730                         bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6731                 }
6732         }
6733
6734         bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
6735         if (CHIP_IS_E1(bp)) {
6736                 /* enable HW interrupt from PXP on USDM overflow
6737                    bit 16 on INT_MASK_0 */
6738                 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6739         }
6740
6741         bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
6742         bnx2x_init_pxp(bp);
6743
6744 #ifdef __BIG_ENDIAN
6745         REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
6746         REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
6747         REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
6748         REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
6749         REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
6750         /* make sure this value is 0 */
6751         REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
6752
6753 /*      REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
6754         REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
6755         REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
6756         REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
6757         REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
6758 #endif
6759
6760         bnx2x_ilt_init_page_size(bp, INITOP_SET);
6761
6762         if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
6763                 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
6764
6765         /* let the HW do it's magic ... */
6766         msleep(100);
6767         /* finish PXP init */
6768         val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
6769         if (val != 1) {
6770                 BNX2X_ERR("PXP2 CFG failed\n");
6771                 return -EBUSY;
6772         }
6773         val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
6774         if (val != 1) {
6775                 BNX2X_ERR("PXP2 RD_INIT failed\n");
6776                 return -EBUSY;
6777         }
6778
6779         /* Timers bug workaround E2 only. We need to set the entire ILT to
6780          * have entries with value "0" and valid bit on.
6781          * This needs to be done by the first PF that is loaded in a path
6782          * (i.e. common phase)
6783          */
6784         if (!CHIP_IS_E1x(bp)) {
6785 /* In E2 there is a bug in the timers block that can cause function 6 / 7
6786  * (i.e. vnic3) to start even if it is marked as "scan-off".
6787  * This occurs when a different function (func2,3) is being marked
6788  * as "scan-off". Real-life scenario for example: if a driver is being
6789  * load-unloaded while func6,7 are down. This will cause the timer to access
6790  * the ilt, translate to a logical address and send a request to read/write.
6791  * Since the ilt for the function that is down is not valid, this will cause
6792  * a translation error which is unrecoverable.
6793  * The Workaround is intended to make sure that when this happens nothing fatal
6794  * will occur. The workaround:
6795  *      1.  First PF driver which loads on a path will:
6796  *              a.  After taking the chip out of reset, by using pretend,
6797  *                  it will write "0" to the following registers of
6798  *                  the other vnics.
6799  *                  REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6800  *                  REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
6801  *                  REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
6802  *                  And for itself it will write '1' to
6803  *                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
6804  *                  dmae-operations (writing to pram for example.)
6805  *                  note: can be done for only function 6,7 but cleaner this
6806  *                        way.
6807  *              b.  Write zero+valid to the entire ILT.
6808  *              c.  Init the first_timers_ilt_entry, last_timers_ilt_entry of
6809  *                  VNIC3 (of that port). The range allocated will be the
6810  *                  entire ILT. This is needed to prevent  ILT range error.
6811  *      2.  Any PF driver load flow:
6812  *              a.  ILT update with the physical addresses of the allocated
6813  *                  logical pages.
6814  *              b.  Wait 20msec. - note that this timeout is needed to make
6815  *                  sure there are no requests in one of the PXP internal
6816  *                  queues with "old" ILT addresses.
6817  *              c.  PF enable in the PGLC.
6818  *              d.  Clear the was_error of the PF in the PGLC. (could have
6819  *                  occurred while driver was down)
6820  *              e.  PF enable in the CFC (WEAK + STRONG)
6821  *              f.  Timers scan enable
6822  *      3.  PF driver unload flow:
6823  *              a.  Clear the Timers scan_en.
6824  *              b.  Polling for scan_on=0 for that PF.
6825  *              c.  Clear the PF enable bit in the PXP.
6826  *              d.  Clear the PF enable in the CFC (WEAK + STRONG)
6827  *              e.  Write zero+valid to all ILT entries (The valid bit must
6828  *                  stay set)
6829  *              f.  If this is VNIC 3 of a port then also init
6830  *                  first_timers_ilt_entry to zero and last_timers_ilt_entry
6831  *                  to the last entry in the ILT.
6832  *
6833  *      Notes:
6834  *      Currently the PF error in the PGLC is non recoverable.
6835  *      In the future the there will be a recovery routine for this error.
6836  *      Currently attention is masked.
6837  *      Having an MCP lock on the load/unload process does not guarantee that
6838  *      there is no Timer disable during Func6/7 enable. This is because the
6839  *      Timers scan is currently being cleared by the MCP on FLR.
6840  *      Step 2.d can be done only for PF6/7 and the driver can also check if
6841  *      there is error before clearing it. But the flow above is simpler and
6842  *      more general.
6843  *      All ILT entries are written by zero+valid and not just PF6/7
6844  *      ILT entries since in the future the ILT entries allocation for
6845  *      PF-s might be dynamic.
6846  */
6847                 struct ilt_client_info ilt_cli;
6848                 struct bnx2x_ilt ilt;
6849                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
6850                 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
6851
6852                 /* initialize dummy TM client */
6853                 ilt_cli.start = 0;
6854                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
6855                 ilt_cli.client_num = ILT_CLIENT_TM;
6856
6857                 /* Step 1: set zeroes to all ilt page entries with valid bit on
6858                  * Step 2: set the timers first/last ilt entry to point
6859                  * to the entire range to prevent ILT range error for 3rd/4th
6860                  * vnic (this code assumes existence of the vnic)
6861                  *
6862                  * both steps performed by call to bnx2x_ilt_client_init_op()
6863                  * with dummy TM client
6864                  *
6865                  * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
6866                  * and his brother are split registers
6867                  */
6868                 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
6869                 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
6870                 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6871
6872                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
6873                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
6874                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
6875         }
6876
6877         REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
6878         REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
6879
6880         if (!CHIP_IS_E1x(bp)) {
6881                 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
6882                                 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
6883                 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
6884
6885                 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
6886
6887                 /* let the HW do it's magic ... */
6888                 do {
6889                         msleep(200);
6890                         val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
6891                 } while (factor-- && (val != 1));
6892
6893                 if (val != 1) {
6894                         BNX2X_ERR("ATC_INIT failed\n");
6895                         return -EBUSY;
6896                 }
6897         }
6898
6899         bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
6900
6901         bnx2x_iov_init_dmae(bp);
6902
6903         /* clean the DMAE memory */
6904         bp->dmae_ready = 1;
6905         bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
6906
6907         bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
6908
6909         bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
6910
6911         bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
6912
6913         bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
6914
6915         bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
6916         bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
6917         bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
6918         bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
6919
6920         bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
6921
6922         /* QM queues pointers table */
6923         bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
6924
6925         /* soft reset pulse */
6926         REG_WR(bp, QM_REG_SOFT_RESET, 1);
6927         REG_WR(bp, QM_REG_SOFT_RESET, 0);
6928
6929         if (CNIC_SUPPORT(bp))
6930                 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
6931
6932         bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
6933
6934         if (!CHIP_REV_IS_SLOW(bp))
6935                 /* enable hw interrupt from doorbell Q */
6936                 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6937
6938         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6939
6940         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6941         REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
6942
6943         if (!CHIP_IS_E1(bp))
6944                 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
6945
6946         if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) {
6947                 if (IS_MF_AFEX(bp)) {
6948                         /* configure that VNTag and VLAN headers must be
6949                          * received in afex mode
6950                          */
6951                         REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE);
6952                         REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA);
6953                         REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
6954                         REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
6955                         REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4);
6956                 } else {
6957                         /* Bit-map indicating which L2 hdrs may appear
6958                          * after the basic Ethernet header
6959                          */
6960                         REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
6961                                bp->path_has_ovlan ? 7 : 6);
6962                 }
6963         }
6964
6965         bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
6966         bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
6967         bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
6968         bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
6969
6970         if (!CHIP_IS_E1x(bp)) {
6971                 /* reset VFC memories */
6972                 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6973                            VFC_MEMORIES_RST_REG_CAM_RST |
6974                            VFC_MEMORIES_RST_REG_RAM_RST);
6975                 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6976                            VFC_MEMORIES_RST_REG_CAM_RST |
6977                            VFC_MEMORIES_RST_REG_RAM_RST);
6978
6979                 msleep(20);
6980         }
6981
6982         bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
6983         bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
6984         bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
6985         bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
6986
6987         /* sync semi rtc */
6988         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6989                0x80000000);
6990         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
6991                0x80000000);
6992
6993         bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
6994         bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
6995         bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
6996
6997         if (!CHIP_IS_E1x(bp)) {
6998                 if (IS_MF_AFEX(bp)) {
6999                         /* configure that VNTag and VLAN headers must be
7000                          * sent in afex mode
7001                          */
7002                         REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE);
7003                         REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA);
7004                         REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
7005                         REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
7006                         REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4);
7007                 } else {
7008                         REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
7009                                bp->path_has_ovlan ? 7 : 6);
7010                 }
7011         }
7012
7013         REG_WR(bp, SRC_REG_SOFT_RST, 1);
7014
7015         bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
7016
7017         if (CNIC_SUPPORT(bp)) {
7018                 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
7019                 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
7020                 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
7021                 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
7022                 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
7023                 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
7024                 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
7025                 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
7026                 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
7027                 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
7028         }
7029         REG_WR(bp, SRC_REG_SOFT_RST, 0);
7030
7031         if (sizeof(union cdu_context) != 1024)
7032                 /* we currently assume that a context is 1024 bytes */
7033                 dev_alert(&bp->pdev->dev,
7034                           "please adjust the size of cdu_context(%ld)\n",
7035                           (long)sizeof(union cdu_context));
7036
7037         bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
7038         val = (4 << 24) + (0 << 12) + 1024;
7039         REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
7040
7041         bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
7042         REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
7043         /* enable context validation interrupt from CFC */
7044         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
7045
7046         /* set the thresholds to prevent CFC/CDU race */
7047         REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
7048
7049         bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
7050
7051         if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
7052                 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
7053
7054         bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
7055         bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
7056
7057         /* Reset PCIE errors for debug */
7058         REG_WR(bp, 0x2814, 0xffffffff);
7059         REG_WR(bp, 0x3820, 0xffffffff);
7060
7061         if (!CHIP_IS_E1x(bp)) {
7062                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
7063                            (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
7064                                 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
7065                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
7066                            (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
7067                                 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
7068                                 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
7069                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
7070                            (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
7071                                 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
7072                                 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
7073         }
7074
7075         bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
7076         if (!CHIP_IS_E1(bp)) {
7077                 /* in E3 this done in per-port section */
7078                 if (!CHIP_IS_E3(bp))
7079                         REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
7080         }
7081         if (CHIP_IS_E1H(bp))
7082                 /* not applicable for E2 (and above ...) */
7083                 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
7084
7085         if (CHIP_REV_IS_SLOW(bp))
7086                 msleep(200);
7087
7088         /* finish CFC init */
7089         val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
7090         if (val != 1) {
7091                 BNX2X_ERR("CFC LL_INIT failed\n");
7092                 return -EBUSY;
7093         }
7094         val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
7095         if (val != 1) {
7096                 BNX2X_ERR("CFC AC_INIT failed\n");
7097                 return -EBUSY;
7098         }
7099         val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
7100         if (val != 1) {
7101                 BNX2X_ERR("CFC CAM_INIT failed\n");
7102                 return -EBUSY;
7103         }
7104         REG_WR(bp, CFC_REG_DEBUG0, 0);
7105
7106         if (CHIP_IS_E1(bp)) {
7107                 /* read NIG statistic
7108                    to see if this is our first up since powerup */
7109                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
7110                 val = *bnx2x_sp(bp, wb_data[0]);
7111
7112                 /* do internal memory self test */
7113                 if ((val == 0) && bnx2x_int_mem_test(bp)) {
7114                         BNX2X_ERR("internal mem self test failed\n");
7115                         return -EBUSY;
7116                 }
7117         }
7118
7119         bnx2x_setup_fan_failure_detection(bp);
7120
7121         /* clear PXP2 attentions */
7122         REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
7123
7124         bnx2x_enable_blocks_attention(bp);
7125         bnx2x_enable_blocks_parity(bp);
7126
7127         if (!BP_NOMCP(bp)) {
7128                 if (CHIP_IS_E1x(bp))
7129                         bnx2x__common_init_phy(bp);
7130         } else
7131                 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
7132
7133         return 0;
7134 }
7135
7136 /**
7137  * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
7138  *
7139  * @bp:         driver handle
7140  */
7141 static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
7142 {
7143         int rc = bnx2x_init_hw_common(bp);
7144
7145         if (rc)
7146                 return rc;
7147
7148         /* In E2 2-PORT mode, same ext phy is used for the two paths */
7149         if (!BP_NOMCP(bp))
7150                 bnx2x__common_init_phy(bp);
7151
7152         return 0;
7153 }
7154
7155 static int bnx2x_init_hw_port(struct bnx2x *bp)
7156 {
7157         int port = BP_PORT(bp);
7158         int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
7159         u32 low, high;
7160         u32 val, reg;
7161
7162         DP(NETIF_MSG_HW, "starting port init  port %d\n", port);
7163
7164         REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
7165
7166         bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7167         bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7168         bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7169
7170         /* Timers bug workaround: disables the pf_master bit in pglue at
7171          * common phase, we need to enable it here before any dmae access are
7172          * attempted. Therefore we manually added the enable-master to the
7173          * port phase (it also happens in the function phase)
7174          */
7175         if (!CHIP_IS_E1x(bp))
7176                 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7177
7178         bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7179         bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7180         bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7181         bnx2x_init_block(bp, BLOCK_QM, init_phase);
7182
7183         bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7184         bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7185         bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7186         bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7187
7188         /* QM cid (connection) count */
7189         bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
7190
7191         if (CNIC_SUPPORT(bp)) {
7192                 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7193                 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
7194                 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
7195         }
7196
7197         bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7198
7199         bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7200
7201         if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
7202
7203                 if (IS_MF(bp))
7204                         low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
7205                 else if (bp->dev->mtu > 4096) {
7206                         if (bp->flags & ONE_PORT_FLAG)
7207                                 low = 160;
7208                         else {
7209                                 val = bp->dev->mtu;
7210                                 /* (24*1024 + val*4)/256 */
7211                                 low = 96 + (val/64) +
7212                                                 ((val % 64) ? 1 : 0);
7213                         }
7214                 } else
7215                         low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
7216                 high = low + 56;        /* 14*1024/256 */
7217                 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
7218                 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
7219         }
7220
7221         if (CHIP_MODE_IS_4_PORT(bp))
7222                 REG_WR(bp, (BP_PORT(bp) ?
7223                             BRB1_REG_MAC_GUARANTIED_1 :
7224                             BRB1_REG_MAC_GUARANTIED_0), 40);
7225
7226         bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7227         if (CHIP_IS_E3B0(bp)) {
7228                 if (IS_MF_AFEX(bp)) {
7229                         /* configure headers for AFEX mode */
7230                         REG_WR(bp, BP_PORT(bp) ?
7231                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7232                                PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
7233                         REG_WR(bp, BP_PORT(bp) ?
7234                                PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
7235                                PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
7236                         REG_WR(bp, BP_PORT(bp) ?
7237                                PRS_REG_MUST_HAVE_HDRS_PORT_1 :
7238                                PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
7239                 } else {
7240                         /* Ovlan exists only if we are in multi-function +
7241                          * switch-dependent mode, in switch-independent there
7242                          * is no ovlan headers
7243                          */
7244                         REG_WR(bp, BP_PORT(bp) ?
7245                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7246                                PRS_REG_HDRS_AFTER_BASIC_PORT_0,
7247                                (bp->path_has_ovlan ? 7 : 6));
7248                 }
7249         }
7250
7251         bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7252         bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7253         bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7254         bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7255
7256         bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7257         bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7258         bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7259         bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7260
7261         bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7262         bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7263
7264         bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7265
7266         if (CHIP_IS_E1x(bp)) {
7267                 /* configure PBF to work without PAUSE mtu 9000 */
7268                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
7269
7270                 /* update threshold */
7271                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
7272                 /* update init credit */
7273                 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
7274
7275                 /* probe changes */
7276                 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
7277                 udelay(50);
7278                 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
7279         }
7280
7281         if (CNIC_SUPPORT(bp))
7282                 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7283
7284         bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7285         bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7286
7287         if (CHIP_IS_E1(bp)) {
7288                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7289                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7290         }
7291         bnx2x_init_block(bp, BLOCK_HC, init_phase);
7292
7293         bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7294
7295         bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7296         /* init aeu_mask_attn_func_0/1:
7297          *  - SF mode: bits 3-7 are masked. Only bits 0-2 are in use
7298          *  - MF mode: bit 3 is masked. Bits 0-2 are in use as in SF
7299          *             bits 4-7 are used for "per vn group attention" */
7300         val = IS_MF(bp) ? 0xF7 : 0x7;
7301         /* Enable DCBX attention for all but E1 */
7302         val |= CHIP_IS_E1(bp) ? 0 : 0x10;
7303         REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
7304
7305         /* SCPAD_PARITY should NOT trigger close the gates */
7306         reg = port ? MISC_REG_AEU_ENABLE4_NIG_1 : MISC_REG_AEU_ENABLE4_NIG_0;
7307         REG_WR(bp, reg,
7308                REG_RD(bp, reg) &
7309                ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7310
7311         reg = port ? MISC_REG_AEU_ENABLE4_PXP_1 : MISC_REG_AEU_ENABLE4_PXP_0;
7312         REG_WR(bp, reg,
7313                REG_RD(bp, reg) &
7314                ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7315
7316         bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7317
7318         if (!CHIP_IS_E1x(bp)) {
7319                 /* Bit-map indicating which L2 hdrs may appear after the
7320                  * basic Ethernet header
7321                  */
7322                 if (IS_MF_AFEX(bp))
7323                         REG_WR(bp, BP_PORT(bp) ?
7324                                NIG_REG_P1_HDRS_AFTER_BASIC :
7325                                NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
7326                 else
7327                         REG_WR(bp, BP_PORT(bp) ?
7328                                NIG_REG_P1_HDRS_AFTER_BASIC :
7329                                NIG_REG_P0_HDRS_AFTER_BASIC,
7330                                IS_MF_SD(bp) ? 7 : 6);
7331
7332                 if (CHIP_IS_E3(bp))
7333                         REG_WR(bp, BP_PORT(bp) ?
7334                                    NIG_REG_LLH1_MF_MODE :
7335                                    NIG_REG_LLH_MF_MODE, IS_MF(bp));
7336         }
7337         if (!CHIP_IS_E3(bp))
7338                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
7339
7340         if (!CHIP_IS_E1(bp)) {
7341                 /* 0x2 disable mf_ov, 0x1 enable */
7342                 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
7343                        (IS_MF_SD(bp) ? 0x1 : 0x2));
7344
7345                 if (!CHIP_IS_E1x(bp)) {
7346                         val = 0;
7347                         switch (bp->mf_mode) {
7348                         case MULTI_FUNCTION_SD:
7349                                 val = 1;
7350                                 break;
7351                         case MULTI_FUNCTION_SI:
7352                         case MULTI_FUNCTION_AFEX:
7353                                 val = 2;
7354                                 break;
7355                         }
7356
7357                         REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
7358                                                   NIG_REG_LLH0_CLS_TYPE), val);
7359                 }
7360                 {
7361                         REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
7362                         REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
7363                         REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
7364                 }
7365         }
7366
7367         /* If SPIO5 is set to generate interrupts, enable it for this port */
7368         val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
7369         if (val & MISC_SPIO_SPIO5) {
7370                 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
7371                                        MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
7372                 val = REG_RD(bp, reg_addr);
7373                 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
7374                 REG_WR(bp, reg_addr, val);
7375         }
7376
7377         return 0;
7378 }
7379
7380 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
7381 {
7382         int reg;
7383         u32 wb_write[2];
7384
7385         if (CHIP_IS_E1(bp))
7386                 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
7387         else
7388                 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
7389
7390         wb_write[0] = ONCHIP_ADDR1(addr);
7391         wb_write[1] = ONCHIP_ADDR2(addr);
7392         REG_WR_DMAE(bp, reg, wb_write, 2);
7393 }
7394
7395 void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf)
7396 {
7397         u32 data, ctl, cnt = 100;
7398         u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
7399         u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
7400         u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
7401         u32 sb_bit =  1 << (idu_sb_id%32);
7402         u32 func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
7403         u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
7404
7405         /* Not supported in BC mode */
7406         if (CHIP_INT_MODE_IS_BC(bp))
7407                 return;
7408
7409         data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
7410                         << IGU_REGULAR_CLEANUP_TYPE_SHIFT)      |
7411                 IGU_REGULAR_CLEANUP_SET                         |
7412                 IGU_REGULAR_BCLEANUP;
7413
7414         ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT         |
7415               func_encode << IGU_CTRL_REG_FID_SHIFT             |
7416               IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
7417
7418         DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7419                          data, igu_addr_data);
7420         REG_WR(bp, igu_addr_data, data);
7421         mmiowb();
7422         barrier();
7423         DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7424                           ctl, igu_addr_ctl);
7425         REG_WR(bp, igu_addr_ctl, ctl);
7426         mmiowb();
7427         barrier();
7428
7429         /* wait for clean up to finish */
7430         while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
7431                 msleep(20);
7432
7433         if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
7434                 DP(NETIF_MSG_HW,
7435                    "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
7436                           idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
7437         }
7438 }
7439
7440 static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
7441 {
7442         bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
7443 }
7444
7445 static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
7446 {
7447         u32 i, base = FUNC_ILT_BASE(func);
7448         for (i = base; i < base + ILT_PER_FUNC; i++)
7449                 bnx2x_ilt_wr(bp, i, 0);
7450 }
7451
7452 static void bnx2x_init_searcher(struct bnx2x *bp)
7453 {
7454         int port = BP_PORT(bp);
7455         bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
7456         /* T1 hash bits value determines the T1 number of entries */
7457         REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
7458 }
7459
7460 static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend)
7461 {
7462         int rc;
7463         struct bnx2x_func_state_params func_params = {NULL};
7464         struct bnx2x_func_switch_update_params *switch_update_params =
7465                 &func_params.params.switch_update;
7466
7467         /* Prepare parameters for function state transitions */
7468         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7469         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
7470
7471         func_params.f_obj = &bp->func_obj;
7472         func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
7473
7474         /* Function parameters */
7475         switch_update_params->suspend = suspend;
7476
7477         rc = bnx2x_func_state_change(bp, &func_params);
7478
7479         return rc;
7480 }
7481
7482 static int bnx2x_reset_nic_mode(struct bnx2x *bp)
7483 {
7484         int rc, i, port = BP_PORT(bp);
7485         int vlan_en = 0, mac_en[NUM_MACS];
7486
7487         /* Close input from network */
7488         if (bp->mf_mode == SINGLE_FUNCTION) {
7489                 bnx2x_set_rx_filter(&bp->link_params, 0);
7490         } else {
7491                 vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN :
7492                                    NIG_REG_LLH0_FUNC_EN);
7493                 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7494                           NIG_REG_LLH0_FUNC_EN, 0);
7495                 for (i = 0; i < NUM_MACS; i++) {
7496                         mac_en[i] = REG_RD(bp, port ?
7497                                              (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7498                                               4 * i) :
7499                                              (NIG_REG_LLH0_FUNC_MEM_ENABLE +
7500                                               4 * i));
7501                         REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7502                                               4 * i) :
7503                                   (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0);
7504                 }
7505         }
7506
7507         /* Close BMC to host */
7508         REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7509                NIG_REG_P1_TX_MNG_HOST_ENABLE, 0);
7510
7511         /* Suspend Tx switching to the PF. Completion of this ramrod
7512          * further guarantees that all the packets of that PF / child
7513          * VFs in BRB were processed by the Parser, so it is safe to
7514          * change the NIC_MODE register.
7515          */
7516         rc = bnx2x_func_switch_update(bp, 1);
7517         if (rc) {
7518                 BNX2X_ERR("Can't suspend tx-switching!\n");
7519                 return rc;
7520         }
7521
7522         /* Change NIC_MODE register */
7523         REG_WR(bp, PRS_REG_NIC_MODE, 0);
7524
7525         /* Open input from network */
7526         if (bp->mf_mode == SINGLE_FUNCTION) {
7527                 bnx2x_set_rx_filter(&bp->link_params, 1);
7528         } else {
7529                 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7530                           NIG_REG_LLH0_FUNC_EN, vlan_en);
7531                 for (i = 0; i < NUM_MACS; i++) {
7532                         REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7533                                               4 * i) :
7534                                   (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i),
7535                                   mac_en[i]);
7536                 }
7537         }
7538
7539         /* Enable BMC to host */
7540         REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7541                NIG_REG_P1_TX_MNG_HOST_ENABLE, 1);
7542
7543         /* Resume Tx switching to the PF */
7544         rc = bnx2x_func_switch_update(bp, 0);
7545         if (rc) {
7546                 BNX2X_ERR("Can't resume tx-switching!\n");
7547                 return rc;
7548         }
7549
7550         DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7551         return 0;
7552 }
7553
7554 int bnx2x_init_hw_func_cnic(struct bnx2x *bp)
7555 {
7556         int rc;
7557
7558         bnx2x_ilt_init_op_cnic(bp, INITOP_SET);
7559
7560         if (CONFIGURE_NIC_MODE(bp)) {
7561                 /* Configure searcher as part of function hw init */
7562                 bnx2x_init_searcher(bp);
7563
7564                 /* Reset NIC mode */
7565                 rc = bnx2x_reset_nic_mode(bp);
7566                 if (rc)
7567                         BNX2X_ERR("Can't change NIC mode!\n");
7568                 return rc;
7569         }
7570
7571         return 0;
7572 }
7573
7574 static int bnx2x_init_hw_func(struct bnx2x *bp)
7575 {
7576         int port = BP_PORT(bp);
7577         int func = BP_FUNC(bp);
7578         int init_phase = PHASE_PF0 + func;
7579         struct bnx2x_ilt *ilt = BP_ILT(bp);
7580         u16 cdu_ilt_start;
7581         u32 addr, val;
7582         u32 main_mem_base, main_mem_size, main_mem_prty_clr;
7583         int i, main_mem_width, rc;
7584
7585         DP(NETIF_MSG_HW, "starting func init  func %d\n", func);
7586
7587         /* FLR cleanup - hmmm */
7588         if (!CHIP_IS_E1x(bp)) {
7589                 rc = bnx2x_pf_flr_clnup(bp);
7590                 if (rc) {
7591                         bnx2x_fw_dump(bp);
7592                         return rc;
7593                 }
7594         }
7595
7596         /* set MSI reconfigure capability */
7597         if (bp->common.int_block == INT_BLOCK_HC) {
7598                 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
7599                 val = REG_RD(bp, addr);
7600                 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
7601                 REG_WR(bp, addr, val);
7602         }
7603
7604         bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7605         bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7606
7607         ilt = BP_ILT(bp);
7608         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7609
7610         if (IS_SRIOV(bp))
7611                 cdu_ilt_start += BNX2X_FIRST_VF_CID/ILT_PAGE_CIDS;
7612         cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start);
7613
7614         /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes
7615          * those of the VFs, so start line should be reset
7616          */
7617         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7618         for (i = 0; i < L2_ILT_LINES(bp); i++) {
7619                 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt;
7620                 ilt->lines[cdu_ilt_start + i].page_mapping =
7621                         bp->context[i].cxt_mapping;
7622                 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size;
7623         }
7624
7625         bnx2x_ilt_init_op(bp, INITOP_SET);
7626
7627         if (!CONFIGURE_NIC_MODE(bp)) {
7628                 bnx2x_init_searcher(bp);
7629                 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7630                 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7631         } else {
7632                 /* Set NIC mode */
7633                 REG_WR(bp, PRS_REG_NIC_MODE, 1);
7634                 DP(NETIF_MSG_IFUP, "NIC MODE configured\n");
7635         }
7636
7637         if (!CHIP_IS_E1x(bp)) {
7638                 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
7639
7640                 /* Turn on a single ISR mode in IGU if driver is going to use
7641                  * INT#x or MSI
7642                  */
7643                 if (!(bp->flags & USING_MSIX_FLAG))
7644                         pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
7645                 /*
7646                  * Timers workaround bug: function init part.
7647                  * Need to wait 20msec after initializing ILT,
7648                  * needed to make sure there are no requests in
7649                  * one of the PXP internal queues with "old" ILT addresses
7650                  */
7651                 msleep(20);
7652                 /*
7653                  * Master enable - Due to WB DMAE writes performed before this
7654                  * register is re-initialized as part of the regular function
7655                  * init
7656                  */
7657                 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7658                 /* Enable the function in IGU */
7659                 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
7660         }
7661
7662         bp->dmae_ready = 1;
7663
7664         bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7665
7666         if (!CHIP_IS_E1x(bp))
7667                 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
7668
7669         bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7670         bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7671         bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7672         bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7673         bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7674         bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7675         bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7676         bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7677         bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7678         bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7679         bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7680         bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7681         bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7682
7683         if (!CHIP_IS_E1x(bp))
7684                 REG_WR(bp, QM_REG_PF_EN, 1);
7685
7686         if (!CHIP_IS_E1x(bp)) {
7687                 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7688                 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7689                 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7690                 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7691         }
7692         bnx2x_init_block(bp, BLOCK_QM, init_phase);
7693
7694         bnx2x_init_block(bp, BLOCK_TM, init_phase);
7695         bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7696         REG_WR(bp, DORQ_REG_MODE_ACT, 1); /* no dpm */
7697
7698         bnx2x_iov_init_dq(bp);
7699
7700         bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7701         bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7702         bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7703         bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7704         bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7705         bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7706         bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7707         bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7708         bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7709         if (!CHIP_IS_E1x(bp))
7710                 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
7711
7712         bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7713
7714         bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7715
7716         if (!CHIP_IS_E1x(bp))
7717                 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
7718
7719         if (IS_MF(bp)) {
7720                 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
7721                 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
7722         }
7723
7724         bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7725
7726         /* HC init per function */
7727         if (bp->common.int_block == INT_BLOCK_HC) {
7728                 if (CHIP_IS_E1H(bp)) {
7729                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7730
7731                         REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7732                         REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7733                 }
7734                 bnx2x_init_block(bp, BLOCK_HC, init_phase);
7735
7736         } else {
7737                 int num_segs, sb_idx, prod_offset;
7738
7739                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7740
7741                 if (!CHIP_IS_E1x(bp)) {
7742                         REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
7743                         REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
7744                 }
7745
7746                 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7747
7748                 if (!CHIP_IS_E1x(bp)) {
7749                         int dsb_idx = 0;
7750                         /**
7751                          * Producer memory:
7752                          * E2 mode: address 0-135 match to the mapping memory;
7753                          * 136 - PF0 default prod; 137 - PF1 default prod;
7754                          * 138 - PF2 default prod; 139 - PF3 default prod;
7755                          * 140 - PF0 attn prod;    141 - PF1 attn prod;
7756                          * 142 - PF2 attn prod;    143 - PF3 attn prod;
7757                          * 144-147 reserved.
7758                          *
7759                          * E1.5 mode - In backward compatible mode;
7760                          * for non default SB; each even line in the memory
7761                          * holds the U producer and each odd line hold
7762                          * the C producer. The first 128 producers are for
7763                          * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
7764                          * producers are for the DSB for each PF.
7765                          * Each PF has five segments: (the order inside each
7766                          * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
7767                          * 132-135 C prods; 136-139 X prods; 140-143 T prods;
7768                          * 144-147 attn prods;
7769                          */
7770                         /* non-default-status-blocks */
7771                         num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7772                                 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
7773                         for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
7774                                 prod_offset = (bp->igu_base_sb + sb_idx) *
7775                                         num_segs;
7776
7777                                 for (i = 0; i < num_segs; i++) {
7778                                         addr = IGU_REG_PROD_CONS_MEMORY +
7779                                                         (prod_offset + i) * 4;
7780                                         REG_WR(bp, addr, 0);
7781                                 }
7782                                 /* send consumer update with value 0 */
7783                                 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
7784                                              USTORM_ID, 0, IGU_INT_NOP, 1);
7785                                 bnx2x_igu_clear_sb(bp,
7786                                                    bp->igu_base_sb + sb_idx);
7787                         }
7788
7789                         /* default-status-blocks */
7790                         num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7791                                 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
7792
7793                         if (CHIP_MODE_IS_4_PORT(bp))
7794                                 dsb_idx = BP_FUNC(bp);
7795                         else
7796                                 dsb_idx = BP_VN(bp);
7797
7798                         prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
7799                                        IGU_BC_BASE_DSB_PROD + dsb_idx :
7800                                        IGU_NORM_BASE_DSB_PROD + dsb_idx);
7801
7802                         /*
7803                          * igu prods come in chunks of E1HVN_MAX (4) -
7804                          * does not matters what is the current chip mode
7805                          */
7806                         for (i = 0; i < (num_segs * E1HVN_MAX);
7807                              i += E1HVN_MAX) {
7808                                 addr = IGU_REG_PROD_CONS_MEMORY +
7809                                                         (prod_offset + i)*4;
7810                                 REG_WR(bp, addr, 0);
7811                         }
7812                         /* send consumer update with 0 */
7813                         if (CHIP_INT_MODE_IS_BC(bp)) {
7814                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7815                                              USTORM_ID, 0, IGU_INT_NOP, 1);
7816                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7817                                              CSTORM_ID, 0, IGU_INT_NOP, 1);
7818                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7819                                              XSTORM_ID, 0, IGU_INT_NOP, 1);
7820                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7821                                              TSTORM_ID, 0, IGU_INT_NOP, 1);
7822                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7823                                              ATTENTION_ID, 0, IGU_INT_NOP, 1);
7824                         } else {
7825                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7826                                              USTORM_ID, 0, IGU_INT_NOP, 1);
7827                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7828                                              ATTENTION_ID, 0, IGU_INT_NOP, 1);
7829                         }
7830                         bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
7831
7832                         /* !!! These should become driver const once
7833                            rf-tool supports split-68 const */
7834                         REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
7835                         REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
7836                         REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
7837                         REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
7838                         REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
7839                         REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
7840                 }
7841         }
7842
7843         /* Reset PCIE errors for debug */
7844         REG_WR(bp, 0x2114, 0xffffffff);
7845         REG_WR(bp, 0x2120, 0xffffffff);
7846
7847         if (CHIP_IS_E1x(bp)) {
7848                 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
7849                 main_mem_base = HC_REG_MAIN_MEMORY +
7850                                 BP_PORT(bp) * (main_mem_size * 4);
7851                 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
7852                 main_mem_width = 8;
7853
7854                 val = REG_RD(bp, main_mem_prty_clr);
7855                 if (val)
7856                         DP(NETIF_MSG_HW,
7857                            "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
7858                            val);
7859
7860                 /* Clear "false" parity errors in MSI-X table */
7861                 for (i = main_mem_base;
7862                      i < main_mem_base + main_mem_size * 4;
7863                      i += main_mem_width) {
7864                         bnx2x_read_dmae(bp, i, main_mem_width / 4);
7865                         bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
7866                                          i, main_mem_width / 4);
7867                 }
7868                 /* Clear HC parity attention */
7869                 REG_RD(bp, main_mem_prty_clr);
7870         }
7871
7872 #ifdef BNX2X_STOP_ON_ERROR
7873         /* Enable STORMs SP logging */
7874         REG_WR8(bp, BAR_USTRORM_INTMEM +
7875                USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7876         REG_WR8(bp, BAR_TSTRORM_INTMEM +
7877                TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7878         REG_WR8(bp, BAR_CSTRORM_INTMEM +
7879                CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7880         REG_WR8(bp, BAR_XSTRORM_INTMEM +
7881                XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7882 #endif
7883
7884         bnx2x_phy_probe(&bp->link_params);
7885
7886         return 0;
7887 }
7888
7889 void bnx2x_free_mem_cnic(struct bnx2x *bp)
7890 {
7891         bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE);
7892
7893         if (!CHIP_IS_E1x(bp))
7894                 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
7895                                sizeof(struct host_hc_status_block_e2));
7896         else
7897                 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
7898                                sizeof(struct host_hc_status_block_e1x));
7899
7900         BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
7901 }
7902
7903 void bnx2x_free_mem(struct bnx2x *bp)
7904 {
7905         int i;
7906
7907         BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
7908                        bp->fw_stats_data_sz + bp->fw_stats_req_sz);
7909
7910         if (IS_VF(bp))
7911                 return;
7912
7913         BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
7914                        sizeof(struct host_sp_status_block));
7915
7916         BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
7917                        sizeof(struct bnx2x_slowpath));
7918
7919         for (i = 0; i < L2_ILT_LINES(bp); i++)
7920                 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping,
7921                                bp->context[i].size);
7922         bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
7923
7924         BNX2X_FREE(bp->ilt->lines);
7925
7926         BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
7927
7928         BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
7929                        BCM_PAGE_SIZE * NUM_EQ_PAGES);
7930
7931         BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
7932
7933         bnx2x_iov_free_mem(bp);
7934 }
7935
7936 int bnx2x_alloc_mem_cnic(struct bnx2x *bp)
7937 {
7938         if (!CHIP_IS_E1x(bp))
7939                 /* size = the status block + ramrod buffers */
7940                 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping,
7941                                 sizeof(struct host_hc_status_block_e2));
7942         else
7943                 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb,
7944                                 &bp->cnic_sb_mapping,
7945                                 sizeof(struct
7946                                        host_hc_status_block_e1x));
7947
7948         if (CONFIGURE_NIC_MODE(bp) && !bp->t2)
7949                 /* allocate searcher T2 table, as it wasn't allocated before */
7950                 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
7951
7952         /* write address to which L5 should insert its values */
7953         bp->cnic_eth_dev.addr_drv_info_to_mcp =
7954                 &bp->slowpath->drv_info_to_mcp;
7955
7956         if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC))
7957                 goto alloc_mem_err;
7958
7959         return 0;
7960
7961 alloc_mem_err:
7962         bnx2x_free_mem_cnic(bp);
7963         BNX2X_ERR("Can't allocate memory\n");
7964         return -ENOMEM;
7965 }
7966
7967 int bnx2x_alloc_mem(struct bnx2x *bp)
7968 {
7969         int i, allocated, context_size;
7970
7971         if (!CONFIGURE_NIC_MODE(bp) && !bp->t2)
7972                 /* allocate searcher T2 table */
7973                 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
7974
7975         BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
7976                         sizeof(struct host_sp_status_block));
7977
7978         BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
7979                         sizeof(struct bnx2x_slowpath));
7980
7981         /* Allocate memory for CDU context:
7982          * This memory is allocated separately and not in the generic ILT
7983          * functions because CDU differs in few aspects:
7984          * 1. There are multiple entities allocating memory for context -
7985          * 'regular' driver, CNIC and SRIOV driver. Each separately controls
7986          * its own ILT lines.
7987          * 2. Since CDU page-size is not a single 4KB page (which is the case
7988          * for the other ILT clients), to be efficient we want to support
7989          * allocation of sub-page-size in the last entry.
7990          * 3. Context pointers are used by the driver to pass to FW / update
7991          * the context (for the other ILT clients the pointers are used just to
7992          * free the memory during unload).
7993          */
7994         context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
7995
7996         for (i = 0, allocated = 0; allocated < context_size; i++) {
7997                 bp->context[i].size = min(CDU_ILT_PAGE_SZ,
7998                                           (context_size - allocated));
7999                 BNX2X_PCI_ALLOC(bp->context[i].vcxt,
8000                                 &bp->context[i].cxt_mapping,
8001                                 bp->context[i].size);
8002                 allocated += bp->context[i].size;
8003         }
8004         BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES);
8005
8006         if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
8007                 goto alloc_mem_err;
8008
8009         if (bnx2x_iov_alloc_mem(bp))
8010                 goto alloc_mem_err;
8011
8012         /* Slow path ring */
8013         BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
8014
8015         /* EQ */
8016         BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping,
8017                         BCM_PAGE_SIZE * NUM_EQ_PAGES);
8018
8019         return 0;
8020
8021 alloc_mem_err:
8022         bnx2x_free_mem(bp);
8023         BNX2X_ERR("Can't allocate memory\n");
8024         return -ENOMEM;
8025 }
8026
8027 /*
8028  * Init service functions
8029  */
8030
8031 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
8032                       struct bnx2x_vlan_mac_obj *obj, bool set,
8033                       int mac_type, unsigned long *ramrod_flags)
8034 {
8035         int rc;
8036         struct bnx2x_vlan_mac_ramrod_params ramrod_param;
8037
8038         memset(&ramrod_param, 0, sizeof(ramrod_param));
8039
8040         /* Fill general parameters */
8041         ramrod_param.vlan_mac_obj = obj;
8042         ramrod_param.ramrod_flags = *ramrod_flags;
8043
8044         /* Fill a user request section if needed */
8045         if (!test_bit(RAMROD_CONT, ramrod_flags)) {
8046                 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
8047
8048                 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
8049
8050                 /* Set the command: ADD or DEL */
8051                 if (set)
8052                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
8053                 else
8054                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
8055         }
8056
8057         rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
8058
8059         if (rc == -EEXIST) {
8060                 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
8061                 /* do not treat adding same MAC as error */
8062                 rc = 0;
8063         } else if (rc < 0)
8064                 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
8065
8066         return rc;
8067 }
8068
8069 int bnx2x_del_all_macs(struct bnx2x *bp,
8070                        struct bnx2x_vlan_mac_obj *mac_obj,
8071                        int mac_type, bool wait_for_comp)
8072 {
8073         int rc;
8074         unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
8075
8076         /* Wait for completion of requested */
8077         if (wait_for_comp)
8078                 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8079
8080         /* Set the mac type of addresses we want to clear */
8081         __set_bit(mac_type, &vlan_mac_flags);
8082
8083         rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
8084         if (rc < 0)
8085                 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
8086
8087         return rc;
8088 }
8089
8090 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
8091 {
8092         if (is_zero_ether_addr(bp->dev->dev_addr) &&
8093             (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp))) {
8094                 DP(NETIF_MSG_IFUP | NETIF_MSG_IFDOWN,
8095                    "Ignoring Zero MAC for STORAGE SD mode\n");
8096                 return 0;
8097         }
8098
8099         if (IS_PF(bp)) {
8100                 unsigned long ramrod_flags = 0;
8101
8102                 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
8103                 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8104                 return bnx2x_set_mac_one(bp, bp->dev->dev_addr,
8105                                          &bp->sp_objs->mac_obj, set,
8106                                          BNX2X_ETH_MAC, &ramrod_flags);
8107         } else { /* vf */
8108                 return bnx2x_vfpf_config_mac(bp, bp->dev->dev_addr,
8109                                              bp->fp->index, true);
8110         }
8111 }
8112
8113 int bnx2x_setup_leading(struct bnx2x *bp)
8114 {
8115         if (IS_PF(bp))
8116                 return bnx2x_setup_queue(bp, &bp->fp[0], true);
8117         else /* VF */
8118                 return bnx2x_vfpf_setup_q(bp, &bp->fp[0], true);
8119 }
8120
8121 /**
8122  * bnx2x_set_int_mode - configure interrupt mode
8123  *
8124  * @bp:         driver handle
8125  *
8126  * In case of MSI-X it will also try to enable MSI-X.
8127  */
8128 int bnx2x_set_int_mode(struct bnx2x *bp)
8129 {
8130         int rc = 0;
8131
8132         if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX) {
8133                 BNX2X_ERR("VF not loaded since interrupt mode not msix\n");
8134                 return -EINVAL;
8135         }
8136
8137         switch (int_mode) {
8138         case BNX2X_INT_MODE_MSIX:
8139                 /* attempt to enable msix */
8140                 rc = bnx2x_enable_msix(bp);
8141
8142                 /* msix attained */
8143                 if (!rc)
8144                         return 0;
8145
8146                 /* vfs use only msix */
8147                 if (rc && IS_VF(bp))
8148                         return rc;
8149
8150                 /* failed to enable multiple MSI-X */
8151                 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
8152                                bp->num_queues,
8153                                1 + bp->num_cnic_queues);
8154
8155                 /* falling through... */
8156         case BNX2X_INT_MODE_MSI:
8157                 bnx2x_enable_msi(bp);
8158
8159                 /* falling through... */
8160         case BNX2X_INT_MODE_INTX:
8161                 bp->num_ethernet_queues = 1;
8162                 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
8163                 BNX2X_DEV_INFO("set number of queues to 1\n");
8164                 break;
8165         default:
8166                 BNX2X_DEV_INFO("unknown value in int_mode module parameter\n");
8167                 return -EINVAL;
8168         }
8169         return 0;
8170 }
8171
8172 /* must be called prior to any HW initializations */
8173 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
8174 {
8175         if (IS_SRIOV(bp))
8176                 return (BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)/ILT_PAGE_CIDS;
8177         return L2_ILT_LINES(bp);
8178 }
8179
8180 void bnx2x_ilt_set_info(struct bnx2x *bp)
8181 {
8182         struct ilt_client_info *ilt_client;
8183         struct bnx2x_ilt *ilt = BP_ILT(bp);
8184         u16 line = 0;
8185
8186         ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
8187         DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
8188
8189         /* CDU */
8190         ilt_client = &ilt->clients[ILT_CLIENT_CDU];
8191         ilt_client->client_num = ILT_CLIENT_CDU;
8192         ilt_client->page_size = CDU_ILT_PAGE_SZ;
8193         ilt_client->flags = ILT_CLIENT_SKIP_MEM;
8194         ilt_client->start = line;
8195         line += bnx2x_cid_ilt_lines(bp);
8196
8197         if (CNIC_SUPPORT(bp))
8198                 line += CNIC_ILT_LINES;
8199         ilt_client->end = line - 1;
8200
8201         DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8202            ilt_client->start,
8203            ilt_client->end,
8204            ilt_client->page_size,
8205            ilt_client->flags,
8206            ilog2(ilt_client->page_size >> 12));
8207
8208         /* QM */
8209         if (QM_INIT(bp->qm_cid_count)) {
8210                 ilt_client = &ilt->clients[ILT_CLIENT_QM];
8211                 ilt_client->client_num = ILT_CLIENT_QM;
8212                 ilt_client->page_size = QM_ILT_PAGE_SZ;
8213                 ilt_client->flags = 0;
8214                 ilt_client->start = line;
8215
8216                 /* 4 bytes for each cid */
8217                 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
8218                                                          QM_ILT_PAGE_SZ);
8219
8220                 ilt_client->end = line - 1;
8221
8222                 DP(NETIF_MSG_IFUP,
8223                    "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8224                    ilt_client->start,
8225                    ilt_client->end,
8226                    ilt_client->page_size,
8227                    ilt_client->flags,
8228                    ilog2(ilt_client->page_size >> 12));
8229         }
8230
8231         if (CNIC_SUPPORT(bp)) {
8232                 /* SRC */
8233                 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
8234                 ilt_client->client_num = ILT_CLIENT_SRC;
8235                 ilt_client->page_size = SRC_ILT_PAGE_SZ;
8236                 ilt_client->flags = 0;
8237                 ilt_client->start = line;
8238                 line += SRC_ILT_LINES;
8239                 ilt_client->end = line - 1;
8240
8241                 DP(NETIF_MSG_IFUP,
8242                    "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8243                    ilt_client->start,
8244                    ilt_client->end,
8245                    ilt_client->page_size,
8246                    ilt_client->flags,
8247                    ilog2(ilt_client->page_size >> 12));
8248
8249                 /* TM */
8250                 ilt_client = &ilt->clients[ILT_CLIENT_TM];
8251                 ilt_client->client_num = ILT_CLIENT_TM;
8252                 ilt_client->page_size = TM_ILT_PAGE_SZ;
8253                 ilt_client->flags = 0;
8254                 ilt_client->start = line;
8255                 line += TM_ILT_LINES;
8256                 ilt_client->end = line - 1;
8257
8258                 DP(NETIF_MSG_IFUP,
8259                    "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8260                    ilt_client->start,
8261                    ilt_client->end,
8262                    ilt_client->page_size,
8263                    ilt_client->flags,
8264                    ilog2(ilt_client->page_size >> 12));
8265         }
8266
8267         BUG_ON(line > ILT_MAX_LINES);
8268 }
8269
8270 /**
8271  * bnx2x_pf_q_prep_init - prepare INIT transition parameters
8272  *
8273  * @bp:                 driver handle
8274  * @fp:                 pointer to fastpath
8275  * @init_params:        pointer to parameters structure
8276  *
8277  * parameters configured:
8278  *      - HC configuration
8279  *      - Queue's CDU context
8280  */
8281 static void bnx2x_pf_q_prep_init(struct bnx2x *bp,
8282         struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
8283 {
8284         u8 cos;
8285         int cxt_index, cxt_offset;
8286
8287         /* FCoE Queue uses Default SB, thus has no HC capabilities */
8288         if (!IS_FCOE_FP(fp)) {
8289                 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
8290                 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
8291
8292                 /* If HC is supported, enable host coalescing in the transition
8293                  * to INIT state.
8294                  */
8295                 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
8296                 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
8297
8298                 /* HC rate */
8299                 init_params->rx.hc_rate = bp->rx_ticks ?
8300                         (1000000 / bp->rx_ticks) : 0;
8301                 init_params->tx.hc_rate = bp->tx_ticks ?
8302                         (1000000 / bp->tx_ticks) : 0;
8303
8304                 /* FW SB ID */
8305                 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
8306                         fp->fw_sb_id;
8307
8308                 /*
8309                  * CQ index among the SB indices: FCoE clients uses the default
8310                  * SB, therefore it's different.
8311                  */
8312                 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
8313                 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
8314         }
8315
8316         /* set maximum number of COSs supported by this queue */
8317         init_params->max_cos = fp->max_cos;
8318
8319         DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n",
8320             fp->index, init_params->max_cos);
8321
8322         /* set the context pointers queue object */
8323         for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
8324                 cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS;
8325                 cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index *
8326                                 ILT_PAGE_CIDS);
8327                 init_params->cxts[cos] =
8328                         &bp->context[cxt_index].vcxt[cxt_offset].eth;
8329         }
8330 }
8331
8332 static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8333                         struct bnx2x_queue_state_params *q_params,
8334                         struct bnx2x_queue_setup_tx_only_params *tx_only_params,
8335                         int tx_index, bool leading)
8336 {
8337         memset(tx_only_params, 0, sizeof(*tx_only_params));
8338
8339         /* Set the command */
8340         q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
8341
8342         /* Set tx-only QUEUE flags: don't zero statistics */
8343         tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
8344
8345         /* choose the index of the cid to send the slow path on */
8346         tx_only_params->cid_index = tx_index;
8347
8348         /* Set general TX_ONLY_SETUP parameters */
8349         bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
8350
8351         /* Set Tx TX_ONLY_SETUP parameters */
8352         bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
8353
8354         DP(NETIF_MSG_IFUP,
8355            "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
8356            tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
8357            q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
8358            tx_only_params->gen_params.spcl_id, tx_only_params->flags);
8359
8360         /* send the ramrod */
8361         return bnx2x_queue_state_change(bp, q_params);
8362 }
8363
8364 /**
8365  * bnx2x_setup_queue - setup queue
8366  *
8367  * @bp:         driver handle
8368  * @fp:         pointer to fastpath
8369  * @leading:    is leading
8370  *
8371  * This function performs 2 steps in a Queue state machine
8372  *      actually: 1) RESET->INIT 2) INIT->SETUP
8373  */
8374
8375 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8376                        bool leading)
8377 {
8378         struct bnx2x_queue_state_params q_params = {NULL};
8379         struct bnx2x_queue_setup_params *setup_params =
8380                                                 &q_params.params.setup;
8381         struct bnx2x_queue_setup_tx_only_params *tx_only_params =
8382                                                 &q_params.params.tx_only;
8383         int rc;
8384         u8 tx_index;
8385
8386         DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index);
8387
8388         /* reset IGU state skip FCoE L2 queue */
8389         if (!IS_FCOE_FP(fp))
8390                 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
8391                              IGU_INT_ENABLE, 0);
8392
8393         q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8394         /* We want to wait for completion in this context */
8395         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8396
8397         /* Prepare the INIT parameters */
8398         bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
8399
8400         /* Set the command */
8401         q_params.cmd = BNX2X_Q_CMD_INIT;
8402
8403         /* Change the state to INIT */
8404         rc = bnx2x_queue_state_change(bp, &q_params);
8405         if (rc) {
8406                 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
8407                 return rc;
8408         }
8409
8410         DP(NETIF_MSG_IFUP, "init complete\n");
8411
8412         /* Now move the Queue to the SETUP state... */
8413         memset(setup_params, 0, sizeof(*setup_params));
8414
8415         /* Set QUEUE flags */
8416         setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
8417
8418         /* Set general SETUP parameters */
8419         bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
8420                                 FIRST_TX_COS_INDEX);
8421
8422         bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
8423                             &setup_params->rxq_params);
8424
8425         bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
8426                            FIRST_TX_COS_INDEX);
8427
8428         /* Set the command */
8429         q_params.cmd = BNX2X_Q_CMD_SETUP;
8430
8431         if (IS_FCOE_FP(fp))
8432                 bp->fcoe_init = true;
8433
8434         /* Change the state to SETUP */
8435         rc = bnx2x_queue_state_change(bp, &q_params);
8436         if (rc) {
8437                 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
8438                 return rc;
8439         }
8440
8441         /* loop through the relevant tx-only indices */
8442         for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8443               tx_index < fp->max_cos;
8444               tx_index++) {
8445
8446                 /* prepare and send tx-only ramrod*/
8447                 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
8448                                           tx_only_params, tx_index, leading);
8449                 if (rc) {
8450                         BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
8451                                   fp->index, tx_index);
8452                         return rc;
8453                 }
8454         }
8455
8456         return rc;
8457 }
8458
8459 static int bnx2x_stop_queue(struct bnx2x *bp, int index)
8460 {
8461         struct bnx2x_fastpath *fp = &bp->fp[index];
8462         struct bnx2x_fp_txdata *txdata;
8463         struct bnx2x_queue_state_params q_params = {NULL};
8464         int rc, tx_index;
8465
8466         DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid);
8467
8468         q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8469         /* We want to wait for completion in this context */
8470         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8471
8472         /* close tx-only connections */
8473         for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8474              tx_index < fp->max_cos;
8475              tx_index++){
8476
8477                 /* ascertain this is a normal queue*/
8478                 txdata = fp->txdata_ptr[tx_index];
8479
8480                 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n",
8481                                                         txdata->txq_index);
8482
8483                 /* send halt terminate on tx-only connection */
8484                 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8485                 memset(&q_params.params.terminate, 0,
8486                        sizeof(q_params.params.terminate));
8487                 q_params.params.terminate.cid_index = tx_index;
8488
8489                 rc = bnx2x_queue_state_change(bp, &q_params);
8490                 if (rc)
8491                         return rc;
8492
8493                 /* send halt terminate on tx-only connection */
8494                 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8495                 memset(&q_params.params.cfc_del, 0,
8496                        sizeof(q_params.params.cfc_del));
8497                 q_params.params.cfc_del.cid_index = tx_index;
8498                 rc = bnx2x_queue_state_change(bp, &q_params);
8499                 if (rc)
8500                         return rc;
8501         }
8502         /* Stop the primary connection: */
8503         /* ...halt the connection */
8504         q_params.cmd = BNX2X_Q_CMD_HALT;
8505         rc = bnx2x_queue_state_change(bp, &q_params);
8506         if (rc)
8507                 return rc;
8508
8509         /* ...terminate the connection */
8510         q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8511         memset(&q_params.params.terminate, 0,
8512                sizeof(q_params.params.terminate));
8513         q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
8514         rc = bnx2x_queue_state_change(bp, &q_params);
8515         if (rc)
8516                 return rc;
8517         /* ...delete cfc entry */
8518         q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8519         memset(&q_params.params.cfc_del, 0,
8520                sizeof(q_params.params.cfc_del));
8521         q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
8522         return bnx2x_queue_state_change(bp, &q_params);
8523 }
8524
8525 static void bnx2x_reset_func(struct bnx2x *bp)
8526 {
8527         int port = BP_PORT(bp);
8528         int func = BP_FUNC(bp);
8529         int i;
8530
8531         /* Disable the function in the FW */
8532         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
8533         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
8534         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
8535         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
8536
8537         /* FP SBs */
8538         for_each_eth_queue(bp, i) {
8539                 struct bnx2x_fastpath *fp = &bp->fp[i];
8540                 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8541                            CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
8542                            SB_DISABLED);
8543         }
8544
8545         if (CNIC_LOADED(bp))
8546                 /* CNIC SB */
8547                 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8548                         CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET
8549                         (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED);
8550
8551         /* SP SB */
8552         REG_WR8(bp, BAR_CSTRORM_INTMEM +
8553                 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
8554                 SB_DISABLED);
8555
8556         for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
8557                 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
8558                        0);
8559
8560         /* Configure IGU */
8561         if (bp->common.int_block == INT_BLOCK_HC) {
8562                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8563                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8564         } else {
8565                 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8566                 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8567         }
8568
8569         if (CNIC_LOADED(bp)) {
8570                 /* Disable Timer scan */
8571                 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
8572                 /*
8573                  * Wait for at least 10ms and up to 2 second for the timers
8574                  * scan to complete
8575                  */
8576                 for (i = 0; i < 200; i++) {
8577                         usleep_range(10000, 20000);
8578                         if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
8579                                 break;
8580                 }
8581         }
8582         /* Clear ILT */
8583         bnx2x_clear_func_ilt(bp, func);
8584
8585         /* Timers workaround bug for E2: if this is vnic-3,
8586          * we need to set the entire ilt range for this timers.
8587          */
8588         if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
8589                 struct ilt_client_info ilt_cli;
8590                 /* use dummy TM client */
8591                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
8592                 ilt_cli.start = 0;
8593                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
8594                 ilt_cli.client_num = ILT_CLIENT_TM;
8595
8596                 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
8597         }
8598
8599         /* this assumes that reset_port() called before reset_func()*/
8600         if (!CHIP_IS_E1x(bp))
8601                 bnx2x_pf_disable(bp);
8602
8603         bp->dmae_ready = 0;
8604 }
8605
8606 static void bnx2x_reset_port(struct bnx2x *bp)
8607 {
8608         int port = BP_PORT(bp);
8609         u32 val;
8610
8611         /* Reset physical Link */
8612         bnx2x__link_reset(bp);
8613
8614         REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
8615
8616         /* Do not rcv packets to BRB */
8617         REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
8618         /* Do not direct rcv packets that are not for MCP to the BRB */
8619         REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8620                            NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
8621
8622         /* Configure AEU */
8623         REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
8624
8625         msleep(100);
8626         /* Check for BRB port occupancy */
8627         val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
8628         if (val)
8629                 DP(NETIF_MSG_IFDOWN,
8630                    "BRB1 is not empty  %d blocks are occupied\n", val);
8631
8632         /* TODO: Close Doorbell port? */
8633 }
8634
8635 static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
8636 {
8637         struct bnx2x_func_state_params func_params = {NULL};
8638
8639         /* Prepare parameters for function state transitions */
8640         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8641
8642         func_params.f_obj = &bp->func_obj;
8643         func_params.cmd = BNX2X_F_CMD_HW_RESET;
8644
8645         func_params.params.hw_init.load_phase = load_code;
8646
8647         return bnx2x_func_state_change(bp, &func_params);
8648 }
8649
8650 static int bnx2x_func_stop(struct bnx2x *bp)
8651 {
8652         struct bnx2x_func_state_params func_params = {NULL};
8653         int rc;
8654
8655         /* Prepare parameters for function state transitions */
8656         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8657         func_params.f_obj = &bp->func_obj;
8658         func_params.cmd = BNX2X_F_CMD_STOP;
8659
8660         /*
8661          * Try to stop the function the 'good way'. If fails (in case
8662          * of a parity error during bnx2x_chip_cleanup()) and we are
8663          * not in a debug mode, perform a state transaction in order to
8664          * enable further HW_RESET transaction.
8665          */
8666         rc = bnx2x_func_state_change(bp, &func_params);
8667         if (rc) {
8668 #ifdef BNX2X_STOP_ON_ERROR
8669                 return rc;
8670 #else
8671                 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
8672                 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
8673                 return bnx2x_func_state_change(bp, &func_params);
8674 #endif
8675         }
8676
8677         return 0;
8678 }
8679
8680 /**
8681  * bnx2x_send_unload_req - request unload mode from the MCP.
8682  *
8683  * @bp:                 driver handle
8684  * @unload_mode:        requested function's unload mode
8685  *
8686  * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
8687  */
8688 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
8689 {
8690         u32 reset_code = 0;
8691         int port = BP_PORT(bp);
8692
8693         /* Select the UNLOAD request mode */
8694         if (unload_mode == UNLOAD_NORMAL)
8695                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8696
8697         else if (bp->flags & NO_WOL_FLAG)
8698                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
8699
8700         else if (bp->wol) {
8701                 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
8702                 u8 *mac_addr = bp->dev->dev_addr;
8703                 struct pci_dev *pdev = bp->pdev;
8704                 u32 val;
8705                 u16 pmc;
8706
8707                 /* The mac address is written to entries 1-4 to
8708                  * preserve entry 0 which is used by the PMF
8709                  */
8710                 u8 entry = (BP_VN(bp) + 1)*8;
8711
8712                 val = (mac_addr[0] << 8) | mac_addr[1];
8713                 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
8714
8715                 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
8716                       (mac_addr[4] << 8) | mac_addr[5];
8717                 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
8718
8719                 /* Enable the PME and clear the status */
8720                 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &pmc);
8721                 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
8722                 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, pmc);
8723
8724                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
8725
8726         } else
8727                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8728
8729         /* Send the request to the MCP */
8730         if (!BP_NOMCP(bp))
8731                 reset_code = bnx2x_fw_command(bp, reset_code, 0);
8732         else {
8733                 int path = BP_PATH(bp);
8734
8735                 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d]      %d, %d, %d\n",
8736                    path, load_count[path][0], load_count[path][1],
8737                    load_count[path][2]);
8738                 load_count[path][0]--;
8739                 load_count[path][1 + port]--;
8740                 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d]  %d, %d, %d\n",
8741                    path, load_count[path][0], load_count[path][1],
8742                    load_count[path][2]);
8743                 if (load_count[path][0] == 0)
8744                         reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
8745                 else if (load_count[path][1 + port] == 0)
8746                         reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
8747                 else
8748                         reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
8749         }
8750
8751         return reset_code;
8752 }
8753
8754 /**
8755  * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
8756  *
8757  * @bp:         driver handle
8758  * @keep_link:          true iff link should be kept up
8759  */
8760 void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link)
8761 {
8762         u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
8763
8764         /* Report UNLOAD_DONE to MCP */
8765         if (!BP_NOMCP(bp))
8766                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
8767 }
8768
8769 static int bnx2x_func_wait_started(struct bnx2x *bp)
8770 {
8771         int tout = 50;
8772         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8773
8774         if (!bp->port.pmf)
8775                 return 0;
8776
8777         /*
8778          * (assumption: No Attention from MCP at this stage)
8779          * PMF probably in the middle of TX disable/enable transaction
8780          * 1. Sync IRS for default SB
8781          * 2. Sync SP queue - this guarantees us that attention handling started
8782          * 3. Wait, that TX disable/enable transaction completes
8783          *
8784          * 1+2 guarantee that if DCBx attention was scheduled it already changed
8785          * pending bit of transaction from STARTED-->TX_STOPPED, if we already
8786          * received completion for the transaction the state is TX_STOPPED.
8787          * State will return to STARTED after completion of TX_STOPPED-->STARTED
8788          * transaction.
8789          */
8790
8791         /* make sure default SB ISR is done */
8792         if (msix)
8793                 synchronize_irq(bp->msix_table[0].vector);
8794         else
8795                 synchronize_irq(bp->pdev->irq);
8796
8797         flush_workqueue(bnx2x_wq);
8798
8799         while (bnx2x_func_get_state(bp, &bp->func_obj) !=
8800                                 BNX2X_F_STATE_STARTED && tout--)
8801                 msleep(20);
8802
8803         if (bnx2x_func_get_state(bp, &bp->func_obj) !=
8804                                                 BNX2X_F_STATE_STARTED) {
8805 #ifdef BNX2X_STOP_ON_ERROR
8806                 BNX2X_ERR("Wrong function state\n");
8807                 return -EBUSY;
8808 #else
8809                 /*
8810                  * Failed to complete the transaction in a "good way"
8811                  * Force both transactions with CLR bit
8812                  */
8813                 struct bnx2x_func_state_params func_params = {NULL};
8814
8815                 DP(NETIF_MSG_IFDOWN,
8816                    "Hmmm... Unexpected function state! Forcing STARTED-->TX_ST0PPED-->STARTED\n");
8817
8818                 func_params.f_obj = &bp->func_obj;
8819                 __set_bit(RAMROD_DRV_CLR_ONLY,
8820                                         &func_params.ramrod_flags);
8821
8822                 /* STARTED-->TX_ST0PPED */
8823                 func_params.cmd = BNX2X_F_CMD_TX_STOP;
8824                 bnx2x_func_state_change(bp, &func_params);
8825
8826                 /* TX_ST0PPED-->STARTED */
8827                 func_params.cmd = BNX2X_F_CMD_TX_START;
8828                 return bnx2x_func_state_change(bp, &func_params);
8829 #endif
8830         }
8831
8832         return 0;
8833 }
8834
8835 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link)
8836 {
8837         int port = BP_PORT(bp);
8838         int i, rc = 0;
8839         u8 cos;
8840         struct bnx2x_mcast_ramrod_params rparam = {NULL};
8841         u32 reset_code;
8842
8843         /* Wait until tx fastpath tasks complete */
8844         for_each_tx_queue(bp, i) {
8845                 struct bnx2x_fastpath *fp = &bp->fp[i];
8846
8847                 for_each_cos_in_tx_queue(fp, cos)
8848                         rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
8849 #ifdef BNX2X_STOP_ON_ERROR
8850                 if (rc)
8851                         return;
8852 #endif
8853         }
8854
8855         /* Give HW time to discard old tx messages */
8856         usleep_range(1000, 2000);
8857
8858         /* Clean all ETH MACs */
8859         rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC,
8860                                 false);
8861         if (rc < 0)
8862                 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
8863
8864         /* Clean up UC list  */
8865         rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC,
8866                                 true);
8867         if (rc < 0)
8868                 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
8869                           rc);
8870
8871         /* Disable LLH */
8872         if (!CHIP_IS_E1(bp))
8873                 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
8874
8875         /* Set "drop all" (stop Rx).
8876          * We need to take a netif_addr_lock() here in order to prevent
8877          * a race between the completion code and this code.
8878          */
8879         netif_addr_lock_bh(bp->dev);
8880         /* Schedule the rx_mode command */
8881         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
8882                 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
8883         else
8884                 bnx2x_set_storm_rx_mode(bp);
8885
8886         /* Cleanup multicast configuration */
8887         rparam.mcast_obj = &bp->mcast_obj;
8888         rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
8889         if (rc < 0)
8890                 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
8891
8892         netif_addr_unlock_bh(bp->dev);
8893
8894         bnx2x_iov_chip_cleanup(bp);
8895
8896         /*
8897          * Send the UNLOAD_REQUEST to the MCP. This will return if
8898          * this function should perform FUNC, PORT or COMMON HW
8899          * reset.
8900          */
8901         reset_code = bnx2x_send_unload_req(bp, unload_mode);
8902
8903         /*
8904          * (assumption: No Attention from MCP at this stage)
8905          * PMF probably in the middle of TX disable/enable transaction
8906          */
8907         rc = bnx2x_func_wait_started(bp);
8908         if (rc) {
8909                 BNX2X_ERR("bnx2x_func_wait_started failed\n");
8910 #ifdef BNX2X_STOP_ON_ERROR
8911                 return;
8912 #endif
8913         }
8914
8915         /* Close multi and leading connections
8916          * Completions for ramrods are collected in a synchronous way
8917          */
8918         for_each_eth_queue(bp, i)
8919                 if (bnx2x_stop_queue(bp, i))
8920 #ifdef BNX2X_STOP_ON_ERROR
8921                         return;
8922 #else
8923                         goto unload_error;
8924 #endif
8925
8926         if (CNIC_LOADED(bp)) {
8927                 for_each_cnic_queue(bp, i)
8928                         if (bnx2x_stop_queue(bp, i))
8929 #ifdef BNX2X_STOP_ON_ERROR
8930                                 return;
8931 #else
8932                                 goto unload_error;
8933 #endif
8934         }
8935
8936         /* If SP settings didn't get completed so far - something
8937          * very wrong has happen.
8938          */
8939         if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
8940                 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
8941
8942 #ifndef BNX2X_STOP_ON_ERROR
8943 unload_error:
8944 #endif
8945         rc = bnx2x_func_stop(bp);
8946         if (rc) {
8947                 BNX2X_ERR("Function stop failed!\n");
8948 #ifdef BNX2X_STOP_ON_ERROR
8949                 return;
8950 #endif
8951         }
8952
8953         /* Disable HW interrupts, NAPI */
8954         bnx2x_netif_stop(bp, 1);
8955         /* Delete all NAPI objects */
8956         bnx2x_del_all_napi(bp);
8957         if (CNIC_LOADED(bp))
8958                 bnx2x_del_all_napi_cnic(bp);
8959
8960         /* Release IRQs */
8961         bnx2x_free_irq(bp);
8962
8963         /* Reset the chip */
8964         rc = bnx2x_reset_hw(bp, reset_code);
8965         if (rc)
8966                 BNX2X_ERR("HW_RESET failed\n");
8967
8968         /* Report UNLOAD_DONE to MCP */
8969         bnx2x_send_unload_done(bp, keep_link);
8970 }
8971
8972 void bnx2x_disable_close_the_gate(struct bnx2x *bp)
8973 {
8974         u32 val;
8975
8976         DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n");
8977
8978         if (CHIP_IS_E1(bp)) {
8979                 int port = BP_PORT(bp);
8980                 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
8981                         MISC_REG_AEU_MASK_ATTN_FUNC_0;
8982
8983                 val = REG_RD(bp, addr);
8984                 val &= ~(0x300);
8985                 REG_WR(bp, addr, val);
8986         } else {
8987                 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
8988                 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
8989                          MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
8990                 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
8991         }
8992 }
8993
8994 /* Close gates #2, #3 and #4: */
8995 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
8996 {
8997         u32 val;
8998
8999         /* Gates #2 and #4a are closed/opened for "not E1" only */
9000         if (!CHIP_IS_E1(bp)) {
9001                 /* #4 */
9002                 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
9003                 /* #2 */
9004                 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
9005         }
9006
9007         /* #3 */
9008         if (CHIP_IS_E1x(bp)) {
9009                 /* Prevent interrupts from HC on both ports */
9010                 val = REG_RD(bp, HC_REG_CONFIG_1);
9011                 REG_WR(bp, HC_REG_CONFIG_1,
9012                        (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
9013                        (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
9014
9015                 val = REG_RD(bp, HC_REG_CONFIG_0);
9016                 REG_WR(bp, HC_REG_CONFIG_0,
9017                        (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
9018                        (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
9019         } else {
9020                 /* Prevent incoming interrupts in IGU */
9021                 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
9022
9023                 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
9024                        (!close) ?
9025                        (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
9026                        (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
9027         }
9028
9029         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
9030                 close ? "closing" : "opening");
9031         mmiowb();
9032 }
9033
9034 #define SHARED_MF_CLP_MAGIC  0x80000000 /* `magic' bit */
9035
9036 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
9037 {
9038         /* Do some magic... */
9039         u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9040         *magic_val = val & SHARED_MF_CLP_MAGIC;
9041         MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
9042 }
9043
9044 /**
9045  * bnx2x_clp_reset_done - restore the value of the `magic' bit.
9046  *
9047  * @bp:         driver handle
9048  * @magic_val:  old value of the `magic' bit.
9049  */
9050 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
9051 {
9052         /* Restore the `magic' bit value... */
9053         u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9054         MF_CFG_WR(bp, shared_mf_config.clp_mb,
9055                 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
9056 }
9057
9058 /**
9059  * bnx2x_reset_mcp_prep - prepare for MCP reset.
9060  *
9061  * @bp:         driver handle
9062  * @magic_val:  old value of 'magic' bit.
9063  *
9064  * Takes care of CLP configurations.
9065  */
9066 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
9067 {
9068         u32 shmem;
9069         u32 validity_offset;
9070
9071         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n");
9072
9073         /* Set `magic' bit in order to save MF config */
9074         if (!CHIP_IS_E1(bp))
9075                 bnx2x_clp_reset_prep(bp, magic_val);
9076
9077         /* Get shmem offset */
9078         shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9079         validity_offset =
9080                 offsetof(struct shmem_region, validity_map[BP_PORT(bp)]);
9081
9082         /* Clear validity map flags */
9083         if (shmem > 0)
9084                 REG_WR(bp, shmem + validity_offset, 0);
9085 }
9086
9087 #define MCP_TIMEOUT      5000   /* 5 seconds (in ms) */
9088 #define MCP_ONE_TIMEOUT  100    /* 100 ms */
9089
9090 /**
9091  * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
9092  *
9093  * @bp: driver handle
9094  */
9095 static void bnx2x_mcp_wait_one(struct bnx2x *bp)
9096 {
9097         /* special handling for emulation and FPGA,
9098            wait 10 times longer */
9099         if (CHIP_REV_IS_SLOW(bp))
9100                 msleep(MCP_ONE_TIMEOUT*10);
9101         else
9102                 msleep(MCP_ONE_TIMEOUT);
9103 }
9104
9105 /*
9106  * initializes bp->common.shmem_base and waits for validity signature to appear
9107  */
9108 static int bnx2x_init_shmem(struct bnx2x *bp)
9109 {
9110         int cnt = 0;
9111         u32 val = 0;
9112
9113         do {
9114                 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9115                 if (bp->common.shmem_base) {
9116                         val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
9117                         if (val & SHR_MEM_VALIDITY_MB)
9118                                 return 0;
9119                 }
9120
9121                 bnx2x_mcp_wait_one(bp);
9122
9123         } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
9124
9125         BNX2X_ERR("BAD MCP validity signature\n");
9126
9127         return -ENODEV;
9128 }
9129
9130 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
9131 {
9132         int rc = bnx2x_init_shmem(bp);
9133
9134         /* Restore the `magic' bit value */
9135         if (!CHIP_IS_E1(bp))
9136                 bnx2x_clp_reset_done(bp, magic_val);
9137
9138         return rc;
9139 }
9140
9141 static void bnx2x_pxp_prep(struct bnx2x *bp)
9142 {
9143         if (!CHIP_IS_E1(bp)) {
9144                 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
9145                 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
9146                 mmiowb();
9147         }
9148 }
9149
9150 /*
9151  * Reset the whole chip except for:
9152  *      - PCIE core
9153  *      - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
9154  *              one reset bit)
9155  *      - IGU
9156  *      - MISC (including AEU)
9157  *      - GRC
9158  *      - RBCN, RBCP
9159  */
9160 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
9161 {
9162         u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
9163         u32 global_bits2, stay_reset2;
9164
9165         /*
9166          * Bits that have to be set in reset_mask2 if we want to reset 'global'
9167          * (per chip) blocks.
9168          */
9169         global_bits2 =
9170                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
9171                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
9172
9173         /* Don't reset the following blocks.
9174          * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
9175          *            reset, as in 4 port device they might still be owned
9176          *            by the MCP (there is only one leader per path).
9177          */
9178         not_reset_mask1 =
9179                 MISC_REGISTERS_RESET_REG_1_RST_HC |
9180                 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
9181                 MISC_REGISTERS_RESET_REG_1_RST_PXP;
9182
9183         not_reset_mask2 =
9184                 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
9185                 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
9186                 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
9187                 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
9188                 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
9189                 MISC_REGISTERS_RESET_REG_2_RST_GRC  |
9190                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
9191                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
9192                 MISC_REGISTERS_RESET_REG_2_RST_ATC |
9193                 MISC_REGISTERS_RESET_REG_2_PGLC |
9194                 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
9195                 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
9196                 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
9197                 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
9198                 MISC_REGISTERS_RESET_REG_2_UMAC0 |
9199                 MISC_REGISTERS_RESET_REG_2_UMAC1;
9200
9201         /*
9202          * Keep the following blocks in reset:
9203          *  - all xxMACs are handled by the bnx2x_link code.
9204          */
9205         stay_reset2 =
9206                 MISC_REGISTERS_RESET_REG_2_XMAC |
9207                 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
9208
9209         /* Full reset masks according to the chip */
9210         reset_mask1 = 0xffffffff;
9211
9212         if (CHIP_IS_E1(bp))
9213                 reset_mask2 = 0xffff;
9214         else if (CHIP_IS_E1H(bp))
9215                 reset_mask2 = 0x1ffff;
9216         else if (CHIP_IS_E2(bp))
9217                 reset_mask2 = 0xfffff;
9218         else /* CHIP_IS_E3 */
9219                 reset_mask2 = 0x3ffffff;
9220
9221         /* Don't reset global blocks unless we need to */
9222         if (!global)
9223                 reset_mask2 &= ~global_bits2;
9224
9225         /*
9226          * In case of attention in the QM, we need to reset PXP
9227          * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
9228          * because otherwise QM reset would release 'close the gates' shortly
9229          * before resetting the PXP, then the PSWRQ would send a write
9230          * request to PGLUE. Then when PXP is reset, PGLUE would try to
9231          * read the payload data from PSWWR, but PSWWR would not
9232          * respond. The write queue in PGLUE would stuck, dmae commands
9233          * would not return. Therefore it's important to reset the second
9234          * reset register (containing the
9235          * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
9236          * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
9237          * bit).
9238          */
9239         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
9240                reset_mask2 & (~not_reset_mask2));
9241
9242         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
9243                reset_mask1 & (~not_reset_mask1));
9244
9245         barrier();
9246         mmiowb();
9247
9248         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
9249                reset_mask2 & (~stay_reset2));
9250
9251         barrier();
9252         mmiowb();
9253
9254         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
9255         mmiowb();
9256 }
9257
9258 /**
9259  * bnx2x_er_poll_igu_vq - poll for pending writes bit.
9260  * It should get cleared in no more than 1s.
9261  *
9262  * @bp: driver handle
9263  *
9264  * It should get cleared in no more than 1s. Returns 0 if
9265  * pending writes bit gets cleared.
9266  */
9267 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
9268 {
9269         u32 cnt = 1000;
9270         u32 pend_bits = 0;
9271
9272         do {
9273                 pend_bits  = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
9274
9275                 if (pend_bits == 0)
9276                         break;
9277
9278                 usleep_range(1000, 2000);
9279         } while (cnt-- > 0);
9280
9281         if (cnt <= 0) {
9282                 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
9283                           pend_bits);
9284                 return -EBUSY;
9285         }
9286
9287         return 0;
9288 }
9289
9290 static int bnx2x_process_kill(struct bnx2x *bp, bool global)
9291 {
9292         int cnt = 1000;
9293         u32 val = 0;
9294         u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
9295         u32 tags_63_32 = 0;
9296
9297         /* Empty the Tetris buffer, wait for 1s */
9298         do {
9299                 sr_cnt  = REG_RD(bp, PXP2_REG_RD_SR_CNT);
9300                 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
9301                 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
9302                 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
9303                 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
9304                 if (CHIP_IS_E3(bp))
9305                         tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32);
9306
9307                 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
9308                     ((port_is_idle_0 & 0x1) == 0x1) &&
9309                     ((port_is_idle_1 & 0x1) == 0x1) &&
9310                     (pgl_exp_rom2 == 0xffffffff) &&
9311                     (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff)))
9312                         break;
9313                 usleep_range(1000, 2000);
9314         } while (cnt-- > 0);
9315
9316         if (cnt <= 0) {
9317                 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
9318                 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
9319                           sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
9320                           pgl_exp_rom2);
9321                 return -EAGAIN;
9322         }
9323
9324         barrier();
9325
9326         /* Close gates #2, #3 and #4 */
9327         bnx2x_set_234_gates(bp, true);
9328
9329         /* Poll for IGU VQs for 57712 and newer chips */
9330         if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
9331                 return -EAGAIN;
9332
9333         /* TBD: Indicate that "process kill" is in progress to MCP */
9334
9335         /* Clear "unprepared" bit */
9336         REG_WR(bp, MISC_REG_UNPREPARED, 0);
9337         barrier();
9338
9339         /* Make sure all is written to the chip before the reset */
9340         mmiowb();
9341
9342         /* Wait for 1ms to empty GLUE and PCI-E core queues,
9343          * PSWHST, GRC and PSWRD Tetris buffer.
9344          */
9345         usleep_range(1000, 2000);
9346
9347         /* Prepare to chip reset: */
9348         /* MCP */
9349         if (global)
9350                 bnx2x_reset_mcp_prep(bp, &val);
9351
9352         /* PXP */
9353         bnx2x_pxp_prep(bp);
9354         barrier();
9355
9356         /* reset the chip */
9357         bnx2x_process_kill_chip_reset(bp, global);
9358         barrier();
9359
9360         /* clear errors in PGB */
9361         if (!CHIP_IS_E1x(bp))
9362                 REG_WR(bp, PGLUE_B_REG_LATCHED_ERRORS_CLR, 0x7f);
9363
9364         /* Recover after reset: */
9365         /* MCP */
9366         if (global && bnx2x_reset_mcp_comp(bp, val))
9367                 return -EAGAIN;
9368
9369         /* TBD: Add resetting the NO_MCP mode DB here */
9370
9371         /* Open the gates #2, #3 and #4 */
9372         bnx2x_set_234_gates(bp, false);
9373
9374         /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
9375          * reset state, re-enable attentions. */
9376
9377         return 0;
9378 }
9379
9380 static int bnx2x_leader_reset(struct bnx2x *bp)
9381 {
9382         int rc = 0;
9383         bool global = bnx2x_reset_is_global(bp);
9384         u32 load_code;
9385
9386         /* if not going to reset MCP - load "fake" driver to reset HW while
9387          * driver is owner of the HW
9388          */
9389         if (!global && !BP_NOMCP(bp)) {
9390                 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ,
9391                                              DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
9392                 if (!load_code) {
9393                         BNX2X_ERR("MCP response failure, aborting\n");
9394                         rc = -EAGAIN;
9395                         goto exit_leader_reset;
9396                 }
9397                 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
9398                     (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
9399                         BNX2X_ERR("MCP unexpected resp, aborting\n");
9400                         rc = -EAGAIN;
9401                         goto exit_leader_reset2;
9402                 }
9403                 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
9404                 if (!load_code) {
9405                         BNX2X_ERR("MCP response failure, aborting\n");
9406                         rc = -EAGAIN;
9407                         goto exit_leader_reset2;
9408                 }
9409         }
9410
9411         /* Try to recover after the failure */
9412         if (bnx2x_process_kill(bp, global)) {
9413                 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
9414                           BP_PATH(bp));
9415                 rc = -EAGAIN;
9416                 goto exit_leader_reset2;
9417         }
9418
9419         /*
9420          * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
9421          * state.
9422          */
9423         bnx2x_set_reset_done(bp);
9424         if (global)
9425                 bnx2x_clear_reset_global(bp);
9426
9427 exit_leader_reset2:
9428         /* unload "fake driver" if it was loaded */
9429         if (!global && !BP_NOMCP(bp)) {
9430                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
9431                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
9432         }
9433 exit_leader_reset:
9434         bp->is_leader = 0;
9435         bnx2x_release_leader_lock(bp);
9436         smp_mb();
9437         return rc;
9438 }
9439
9440 static void bnx2x_recovery_failed(struct bnx2x *bp)
9441 {
9442         netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
9443
9444         /* Disconnect this device */
9445         netif_device_detach(bp->dev);
9446
9447         /*
9448          * Block ifup for all function on this engine until "process kill"
9449          * or power cycle.
9450          */
9451         bnx2x_set_reset_in_progress(bp);
9452
9453         /* Shut down the power */
9454         bnx2x_set_power_state(bp, PCI_D3hot);
9455
9456         bp->recovery_state = BNX2X_RECOVERY_FAILED;
9457
9458         smp_mb();
9459 }
9460
9461 /*
9462  * Assumption: runs under rtnl lock. This together with the fact
9463  * that it's called only from bnx2x_sp_rtnl() ensure that it
9464  * will never be called when netif_running(bp->dev) is false.
9465  */
9466 static void bnx2x_parity_recover(struct bnx2x *bp)
9467 {
9468         bool global = false;
9469         u32 error_recovered, error_unrecovered;
9470         bool is_parity;
9471
9472         DP(NETIF_MSG_HW, "Handling parity\n");
9473         while (1) {
9474                 switch (bp->recovery_state) {
9475                 case BNX2X_RECOVERY_INIT:
9476                         DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
9477                         is_parity = bnx2x_chk_parity_attn(bp, &global, false);
9478                         WARN_ON(!is_parity);
9479
9480                         /* Try to get a LEADER_LOCK HW lock */
9481                         if (bnx2x_trylock_leader_lock(bp)) {
9482                                 bnx2x_set_reset_in_progress(bp);
9483                                 /*
9484                                  * Check if there is a global attention and if
9485                                  * there was a global attention, set the global
9486                                  * reset bit.
9487                                  */
9488
9489                                 if (global)
9490                                         bnx2x_set_reset_global(bp);
9491
9492                                 bp->is_leader = 1;
9493                         }
9494
9495                         /* Stop the driver */
9496                         /* If interface has been removed - break */
9497                         if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false))
9498                                 return;
9499
9500                         bp->recovery_state = BNX2X_RECOVERY_WAIT;
9501
9502                         /* Ensure "is_leader", MCP command sequence and
9503                          * "recovery_state" update values are seen on other
9504                          * CPUs.
9505                          */
9506                         smp_mb();
9507                         break;
9508
9509                 case BNX2X_RECOVERY_WAIT:
9510                         DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
9511                         if (bp->is_leader) {
9512                                 int other_engine = BP_PATH(bp) ? 0 : 1;
9513                                 bool other_load_status =
9514                                         bnx2x_get_load_status(bp, other_engine);
9515                                 bool load_status =
9516                                         bnx2x_get_load_status(bp, BP_PATH(bp));
9517                                 global = bnx2x_reset_is_global(bp);
9518
9519                                 /*
9520                                  * In case of a parity in a global block, let
9521                                  * the first leader that performs a
9522                                  * leader_reset() reset the global blocks in
9523                                  * order to clear global attentions. Otherwise
9524                                  * the gates will remain closed for that
9525                                  * engine.
9526                                  */
9527                                 if (load_status ||
9528                                     (global && other_load_status)) {
9529                                         /* Wait until all other functions get
9530                                          * down.
9531                                          */
9532                                         schedule_delayed_work(&bp->sp_rtnl_task,
9533                                                                 HZ/10);
9534                                         return;
9535                                 } else {
9536                                         /* If all other functions got down -
9537                                          * try to bring the chip back to
9538                                          * normal. In any case it's an exit
9539                                          * point for a leader.
9540                                          */
9541                                         if (bnx2x_leader_reset(bp)) {
9542                                                 bnx2x_recovery_failed(bp);
9543                                                 return;
9544                                         }
9545
9546                                         /* If we are here, means that the
9547                                          * leader has succeeded and doesn't
9548                                          * want to be a leader any more. Try
9549                                          * to continue as a none-leader.
9550                                          */
9551                                         break;
9552                                 }
9553                         } else { /* non-leader */
9554                                 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
9555                                         /* Try to get a LEADER_LOCK HW lock as
9556                                          * long as a former leader may have
9557                                          * been unloaded by the user or
9558                                          * released a leadership by another
9559                                          * reason.
9560                                          */
9561                                         if (bnx2x_trylock_leader_lock(bp)) {
9562                                                 /* I'm a leader now! Restart a
9563                                                  * switch case.
9564                                                  */
9565                                                 bp->is_leader = 1;
9566                                                 break;
9567                                         }
9568
9569                                         schedule_delayed_work(&bp->sp_rtnl_task,
9570                                                                 HZ/10);
9571                                         return;
9572
9573                                 } else {
9574                                         /*
9575                                          * If there was a global attention, wait
9576                                          * for it to be cleared.
9577                                          */
9578                                         if (bnx2x_reset_is_global(bp)) {
9579                                                 schedule_delayed_work(
9580                                                         &bp->sp_rtnl_task,
9581                                                         HZ/10);
9582                                                 return;
9583                                         }
9584
9585                                         error_recovered =
9586                                           bp->eth_stats.recoverable_error;
9587                                         error_unrecovered =
9588                                           bp->eth_stats.unrecoverable_error;
9589                                         bp->recovery_state =
9590                                                 BNX2X_RECOVERY_NIC_LOADING;
9591                                         if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
9592                                                 error_unrecovered++;
9593                                                 netdev_err(bp->dev,
9594                                                            "Recovery failed. Power cycle needed\n");
9595                                                 /* Disconnect this device */
9596                                                 netif_device_detach(bp->dev);
9597                                                 /* Shut down the power */
9598                                                 bnx2x_set_power_state(
9599                                                         bp, PCI_D3hot);
9600                                                 smp_mb();
9601                                         } else {
9602                                                 bp->recovery_state =
9603                                                         BNX2X_RECOVERY_DONE;
9604                                                 error_recovered++;
9605                                                 smp_mb();
9606                                         }
9607                                         bp->eth_stats.recoverable_error =
9608                                                 error_recovered;
9609                                         bp->eth_stats.unrecoverable_error =
9610                                                 error_unrecovered;
9611
9612                                         return;
9613                                 }
9614                         }
9615                 default:
9616                         return;
9617                 }
9618         }
9619 }
9620
9621 static int bnx2x_close(struct net_device *dev);
9622
9623 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
9624  * scheduled on a general queue in order to prevent a dead lock.
9625  */
9626 static void bnx2x_sp_rtnl_task(struct work_struct *work)
9627 {
9628         struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
9629
9630         rtnl_lock();
9631
9632         if (!netif_running(bp->dev)) {
9633                 rtnl_unlock();
9634                 return;
9635         }
9636
9637         if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
9638 #ifdef BNX2X_STOP_ON_ERROR
9639                 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
9640                           "you will need to reboot when done\n");
9641                 goto sp_rtnl_not_reset;
9642 #endif
9643                 /*
9644                  * Clear all pending SP commands as we are going to reset the
9645                  * function anyway.
9646                  */
9647                 bp->sp_rtnl_state = 0;
9648                 smp_mb();
9649
9650                 bnx2x_parity_recover(bp);
9651
9652                 rtnl_unlock();
9653                 return;
9654         }
9655
9656         if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
9657 #ifdef BNX2X_STOP_ON_ERROR
9658                 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
9659                           "you will need to reboot when done\n");
9660                 goto sp_rtnl_not_reset;
9661 #endif
9662
9663                 /*
9664                  * Clear all pending SP commands as we are going to reset the
9665                  * function anyway.
9666                  */
9667                 bp->sp_rtnl_state = 0;
9668                 smp_mb();
9669
9670                 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
9671                 bnx2x_nic_load(bp, LOAD_NORMAL);
9672
9673                 rtnl_unlock();
9674                 return;
9675         }
9676 #ifdef BNX2X_STOP_ON_ERROR
9677 sp_rtnl_not_reset:
9678 #endif
9679         if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
9680                 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
9681         if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state))
9682                 bnx2x_after_function_update(bp);
9683         /*
9684          * in case of fan failure we need to reset id if the "stop on error"
9685          * debug flag is set, since we trying to prevent permanent overheating
9686          * damage
9687          */
9688         if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
9689                 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n");
9690                 netif_device_detach(bp->dev);
9691                 bnx2x_close(bp->dev);
9692                 rtnl_unlock();
9693                 return;
9694         }
9695
9696         if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) {
9697                 DP(BNX2X_MSG_SP,
9698                    "sending set mcast vf pf channel message from rtnl sp-task\n");
9699                 bnx2x_vfpf_set_mcast(bp->dev);
9700         }
9701         if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN,
9702                                &bp->sp_rtnl_state)){
9703                 if (!test_bit(__LINK_STATE_NOCARRIER, &bp->dev->state)) {
9704                         bnx2x_tx_disable(bp);
9705                         BNX2X_ERR("PF indicated channel is not servicable anymore. This means this VF device is no longer operational\n");
9706                 }
9707         }
9708
9709         if (test_and_clear_bit(BNX2X_SP_RTNL_RX_MODE, &bp->sp_rtnl_state)) {
9710                 DP(BNX2X_MSG_SP, "Handling Rx Mode setting\n");
9711                 bnx2x_set_rx_mode_inner(bp);
9712         }
9713
9714         if (test_and_clear_bit(BNX2X_SP_RTNL_HYPERVISOR_VLAN,
9715                                &bp->sp_rtnl_state))
9716                 bnx2x_pf_set_vfs_vlan(bp);
9717
9718         if (test_and_clear_bit(BNX2X_SP_RTNL_TX_STOP, &bp->sp_rtnl_state)) {
9719                 bnx2x_dcbx_stop_hw_tx(bp);
9720                 bnx2x_dcbx_resume_hw_tx(bp);
9721         }
9722
9723         /* work which needs rtnl lock not-taken (as it takes the lock itself and
9724          * can be called from other contexts as well)
9725          */
9726         rtnl_unlock();
9727
9728         /* enable SR-IOV if applicable */
9729         if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV,
9730                                                &bp->sp_rtnl_state)) {
9731                 bnx2x_disable_sriov(bp);
9732                 bnx2x_enable_sriov(bp);
9733         }
9734 }
9735
9736 static void bnx2x_period_task(struct work_struct *work)
9737 {
9738         struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
9739
9740         if (!netif_running(bp->dev))
9741                 goto period_task_exit;
9742
9743         if (CHIP_REV_IS_SLOW(bp)) {
9744                 BNX2X_ERR("period task called on emulation, ignoring\n");
9745                 goto period_task_exit;
9746         }
9747
9748         bnx2x_acquire_phy_lock(bp);
9749         /*
9750          * The barrier is needed to ensure the ordering between the writing to
9751          * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
9752          * the reading here.
9753          */
9754         smp_mb();
9755         if (bp->port.pmf) {
9756                 bnx2x_period_func(&bp->link_params, &bp->link_vars);
9757
9758                 /* Re-queue task in 1 sec */
9759                 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
9760         }
9761
9762         bnx2x_release_phy_lock(bp);
9763 period_task_exit:
9764         return;
9765 }
9766
9767 /*
9768  * Init service functions
9769  */
9770
9771 u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
9772 {
9773         u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
9774         u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
9775         return base + (BP_ABS_FUNC(bp)) * stride;
9776 }
9777
9778 static void bnx2x_prev_unload_close_mac(struct bnx2x *bp,
9779                                         struct bnx2x_mac_vals *vals)
9780 {
9781         u32 val, base_addr, offset, mask, reset_reg;
9782         bool mac_stopped = false;
9783         u8 port = BP_PORT(bp);
9784
9785         /* reset addresses as they also mark which values were changed */
9786         vals->bmac_addr = 0;
9787         vals->umac_addr = 0;
9788         vals->xmac_addr = 0;
9789         vals->emac_addr = 0;
9790
9791         reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);
9792
9793         if (!CHIP_IS_E3(bp)) {
9794                 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
9795                 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
9796                 if ((mask & reset_reg) && val) {
9797                         u32 wb_data[2];
9798                         BNX2X_DEV_INFO("Disable bmac Rx\n");
9799                         base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM
9800                                                 : NIG_REG_INGRESS_BMAC0_MEM;
9801                         offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL
9802                                                 : BIGMAC_REGISTER_BMAC_CONTROL;
9803
9804                         /*
9805                          * use rd/wr since we cannot use dmae. This is safe
9806                          * since MCP won't access the bus due to the request
9807                          * to unload, and no function on the path can be
9808                          * loaded at this time.
9809                          */
9810                         wb_data[0] = REG_RD(bp, base_addr + offset);
9811                         wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);
9812                         vals->bmac_addr = base_addr + offset;
9813                         vals->bmac_val[0] = wb_data[0];
9814                         vals->bmac_val[1] = wb_data[1];
9815                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
9816                         REG_WR(bp, vals->bmac_addr, wb_data[0]);
9817                         REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]);
9818                 }
9819                 BNX2X_DEV_INFO("Disable emac Rx\n");
9820                 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4;
9821                 vals->emac_val = REG_RD(bp, vals->emac_addr);
9822                 REG_WR(bp, vals->emac_addr, 0);
9823                 mac_stopped = true;
9824         } else {
9825                 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
9826                         BNX2X_DEV_INFO("Disable xmac Rx\n");
9827                         base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
9828                         val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);
9829                         REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
9830                                val & ~(1 << 1));
9831                         REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
9832                                val | (1 << 1));
9833                         vals->xmac_addr = base_addr + XMAC_REG_CTRL;
9834                         vals->xmac_val = REG_RD(bp, vals->xmac_addr);
9835                         REG_WR(bp, vals->xmac_addr, 0);
9836                         mac_stopped = true;
9837                 }
9838                 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
9839                 if (mask & reset_reg) {
9840                         BNX2X_DEV_INFO("Disable umac Rx\n");
9841                         base_addr = BP_PORT(bp) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
9842                         vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;
9843                         vals->umac_val = REG_RD(bp, vals->umac_addr);
9844                         REG_WR(bp, vals->umac_addr, 0);
9845                         mac_stopped = true;
9846                 }
9847         }
9848
9849         if (mac_stopped)
9850                 msleep(20);
9851 }
9852
9853 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
9854 #define BNX2X_PREV_UNDI_RCQ(val)        ((val) & 0xffff)
9855 #define BNX2X_PREV_UNDI_BD(val)         ((val) >> 16 & 0xffff)
9856 #define BNX2X_PREV_UNDI_PROD(rcq, bd)   ((bd) << 16 | (rcq))
9857
9858 #define BCM_5710_UNDI_FW_MF_MAJOR       (0x07)
9859 #define BCM_5710_UNDI_FW_MF_MINOR       (0x08)
9860 #define BCM_5710_UNDI_FW_MF_VERS        (0x05)
9861 #define BNX2X_PREV_UNDI_MF_PORT(p)      (0x1a150c + ((p) << 4))
9862 #define BNX2X_PREV_UNDI_MF_FUNC(f)      (0x1a184c + ((f) << 4))
9863 static bool bnx2x_prev_unload_undi_fw_supports_mf(struct bnx2x *bp)
9864 {
9865         u8 major, minor, version;
9866         u32 fw;
9867
9868         /* Must check that FW is loaded */
9869         if (!(REG_RD(bp, MISC_REG_RESET_REG_1) &
9870              MISC_REGISTERS_RESET_REG_1_RST_XSEM)) {
9871                 BNX2X_DEV_INFO("XSEM is reset - UNDI MF FW is not loaded\n");
9872                 return false;
9873         }
9874
9875         /* Read Currently loaded FW version */
9876         fw = REG_RD(bp, XSEM_REG_PRAM);
9877         major = fw & 0xff;
9878         minor = (fw >> 0x8) & 0xff;
9879         version = (fw >> 0x10) & 0xff;
9880         BNX2X_DEV_INFO("Loaded FW: 0x%08x: Major 0x%02x Minor 0x%02x Version 0x%02x\n",
9881                        fw, major, minor, version);
9882
9883         if (major > BCM_5710_UNDI_FW_MF_MAJOR)
9884                 return true;
9885
9886         if ((major == BCM_5710_UNDI_FW_MF_MAJOR) &&
9887             (minor > BCM_5710_UNDI_FW_MF_MINOR))
9888                 return true;
9889
9890         if ((major == BCM_5710_UNDI_FW_MF_MAJOR) &&
9891             (minor == BCM_5710_UNDI_FW_MF_MINOR) &&
9892             (version >= BCM_5710_UNDI_FW_MF_VERS))
9893                 return true;
9894
9895         return false;
9896 }
9897
9898 static void bnx2x_prev_unload_undi_mf(struct bnx2x *bp)
9899 {
9900         int i;
9901
9902         /* Due to legacy (FW) code, the first function on each engine has a
9903          * different offset macro from the rest of the functions.
9904          * Setting this for all 8 functions is harmless regardless of whether
9905          * this is actually a multi-function device.
9906          */
9907         for (i = 0; i < 2; i++)
9908                 REG_WR(bp, BNX2X_PREV_UNDI_MF_PORT(i), 1);
9909
9910         for (i = 2; i < 8; i++)
9911                 REG_WR(bp, BNX2X_PREV_UNDI_MF_FUNC(i - 2), 1);
9912
9913         BNX2X_DEV_INFO("UNDI FW (MF) set to discard\n");
9914 }
9915
9916 static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 port, u8 inc)
9917 {
9918         u16 rcq, bd;
9919         u32 tmp_reg = REG_RD(bp, BNX2X_PREV_UNDI_PROD_ADDR(port));
9920
9921         rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
9922         bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
9923
9924         tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
9925         REG_WR(bp, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
9926
9927         BNX2X_DEV_INFO("UNDI producer [%d] rings bd -> 0x%04x, rcq -> 0x%04x\n",
9928                        port, bd, rcq);
9929 }
9930
9931 static int bnx2x_prev_mcp_done(struct bnx2x *bp)
9932 {
9933         u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE,
9934                                   DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
9935         if (!rc) {
9936                 BNX2X_ERR("MCP response failure, aborting\n");
9937                 return -EBUSY;
9938         }
9939
9940         return 0;
9941 }
9942
9943 static struct bnx2x_prev_path_list *
9944                 bnx2x_prev_path_get_entry(struct bnx2x *bp)
9945 {
9946         struct bnx2x_prev_path_list *tmp_list;
9947
9948         list_for_each_entry(tmp_list, &bnx2x_prev_list, list)
9949                 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
9950                     bp->pdev->bus->number == tmp_list->bus &&
9951                     BP_PATH(bp) == tmp_list->path)
9952                         return tmp_list;
9953
9954         return NULL;
9955 }
9956
9957 static int bnx2x_prev_path_mark_eeh(struct bnx2x *bp)
9958 {
9959         struct bnx2x_prev_path_list *tmp_list;
9960         int rc;
9961
9962         rc = down_interruptible(&bnx2x_prev_sem);
9963         if (rc) {
9964                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
9965                 return rc;
9966         }
9967
9968         tmp_list = bnx2x_prev_path_get_entry(bp);
9969         if (tmp_list) {
9970                 tmp_list->aer = 1;
9971                 rc = 0;
9972         } else {
9973                 BNX2X_ERR("path %d: Entry does not exist for eeh; Flow occurs before initial insmod is over ?\n",
9974                           BP_PATH(bp));
9975         }
9976
9977         up(&bnx2x_prev_sem);
9978
9979         return rc;
9980 }
9981
9982 static bool bnx2x_prev_is_path_marked(struct bnx2x *bp)
9983 {
9984         struct bnx2x_prev_path_list *tmp_list;
9985         bool rc = false;
9986
9987         if (down_trylock(&bnx2x_prev_sem))
9988                 return false;
9989
9990         tmp_list = bnx2x_prev_path_get_entry(bp);
9991         if (tmp_list) {
9992                 if (tmp_list->aer) {
9993                         DP(NETIF_MSG_HW, "Path %d was marked by AER\n",
9994                            BP_PATH(bp));
9995                 } else {
9996                         rc = true;
9997                         BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
9998                                        BP_PATH(bp));
9999                 }
10000         }
10001
10002         up(&bnx2x_prev_sem);
10003
10004         return rc;
10005 }
10006
10007 bool bnx2x_port_after_undi(struct bnx2x *bp)
10008 {
10009         struct bnx2x_prev_path_list *entry;
10010         bool val;
10011
10012         down(&bnx2x_prev_sem);
10013
10014         entry = bnx2x_prev_path_get_entry(bp);
10015         val = !!(entry && (entry->undi & (1 << BP_PORT(bp))));
10016
10017         up(&bnx2x_prev_sem);
10018
10019         return val;
10020 }
10021
10022 static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi)
10023 {
10024         struct bnx2x_prev_path_list *tmp_list;
10025         int rc;
10026
10027         rc = down_interruptible(&bnx2x_prev_sem);
10028         if (rc) {
10029                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10030                 return rc;
10031         }
10032
10033         /* Check whether the entry for this path already exists */
10034         tmp_list = bnx2x_prev_path_get_entry(bp);
10035         if (tmp_list) {
10036                 if (!tmp_list->aer) {
10037                         BNX2X_ERR("Re-Marking the path.\n");
10038                 } else {
10039                         DP(NETIF_MSG_HW, "Removing AER indication from path %d\n",
10040                            BP_PATH(bp));
10041                         tmp_list->aer = 0;
10042                 }
10043                 up(&bnx2x_prev_sem);
10044                 return 0;
10045         }
10046         up(&bnx2x_prev_sem);
10047
10048         /* Create an entry for this path and add it */
10049         tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL);
10050         if (!tmp_list) {
10051                 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
10052                 return -ENOMEM;
10053         }
10054
10055         tmp_list->bus = bp->pdev->bus->number;
10056         tmp_list->slot = PCI_SLOT(bp->pdev->devfn);
10057         tmp_list->path = BP_PATH(bp);
10058         tmp_list->aer = 0;
10059         tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0;
10060
10061         rc = down_interruptible(&bnx2x_prev_sem);
10062         if (rc) {
10063                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10064                 kfree(tmp_list);
10065         } else {
10066                 DP(NETIF_MSG_HW, "Marked path [%d] - finished previous unload\n",
10067                    BP_PATH(bp));
10068                 list_add(&tmp_list->list, &bnx2x_prev_list);
10069                 up(&bnx2x_prev_sem);
10070         }
10071
10072         return rc;
10073 }
10074
10075 static int bnx2x_do_flr(struct bnx2x *bp)
10076 {
10077         struct pci_dev *dev = bp->pdev;
10078
10079         if (CHIP_IS_E1x(bp)) {
10080                 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n");
10081                 return -EINVAL;
10082         }
10083
10084         /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
10085         if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
10086                 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
10087                           bp->common.bc_ver);
10088                 return -EINVAL;
10089         }
10090
10091         if (!pci_wait_for_pending_transaction(dev))
10092                 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
10093
10094         BNX2X_DEV_INFO("Initiating FLR\n");
10095         bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0);
10096
10097         return 0;
10098 }
10099
10100 static int bnx2x_prev_unload_uncommon(struct bnx2x *bp)
10101 {
10102         int rc;
10103
10104         BNX2X_DEV_INFO("Uncommon unload Flow\n");
10105
10106         /* Test if previous unload process was already finished for this path */
10107         if (bnx2x_prev_is_path_marked(bp))
10108                 return bnx2x_prev_mcp_done(bp);
10109
10110         BNX2X_DEV_INFO("Path is unmarked\n");
10111
10112         /* If function has FLR capabilities, and existing FW version matches
10113          * the one required, then FLR will be sufficient to clean any residue
10114          * left by previous driver
10115          */
10116         rc = bnx2x_compare_fw_ver(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION, false);
10117
10118         if (!rc) {
10119                 /* fw version is good */
10120                 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
10121                 rc = bnx2x_do_flr(bp);
10122         }
10123
10124         if (!rc) {
10125                 /* FLR was performed */
10126                 BNX2X_DEV_INFO("FLR successful\n");
10127                 return 0;
10128         }
10129
10130         BNX2X_DEV_INFO("Could not FLR\n");
10131
10132         /* Close the MCP request, return failure*/
10133         rc = bnx2x_prev_mcp_done(bp);
10134         if (!rc)
10135                 rc = BNX2X_PREV_WAIT_NEEDED;
10136
10137         return rc;
10138 }
10139
10140 static int bnx2x_prev_unload_common(struct bnx2x *bp)
10141 {
10142         u32 reset_reg, tmp_reg = 0, rc;
10143         bool prev_undi = false;
10144         struct bnx2x_mac_vals mac_vals;
10145
10146         /* It is possible a previous function received 'common' answer,
10147          * but hasn't loaded yet, therefore creating a scenario of
10148          * multiple functions receiving 'common' on the same path.
10149          */
10150         BNX2X_DEV_INFO("Common unload Flow\n");
10151
10152         memset(&mac_vals, 0, sizeof(mac_vals));
10153
10154         if (bnx2x_prev_is_path_marked(bp))
10155                 return bnx2x_prev_mcp_done(bp);
10156
10157         reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
10158
10159         /* Reset should be performed after BRB is emptied */
10160         if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
10161                 u32 timer_count = 1000;
10162
10163                 /* Close the MAC Rx to prevent BRB from filling up */
10164                 bnx2x_prev_unload_close_mac(bp, &mac_vals);
10165
10166                 /* close LLH filters towards the BRB */
10167                 bnx2x_set_rx_filter(&bp->link_params, 0);
10168
10169                 /* Check if the UNDI driver was previously loaded
10170                  * UNDI driver initializes CID offset for normal bell to 0x7
10171                  */
10172                 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
10173                         tmp_reg = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
10174                         if (tmp_reg == 0x7) {
10175                                 BNX2X_DEV_INFO("UNDI previously loaded\n");
10176                                 prev_undi = true;
10177                                 /* clear the UNDI indication */
10178                                 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
10179                                 /* clear possible idle check errors */
10180                                 REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0);
10181                         }
10182                 }
10183                 if (!CHIP_IS_E1x(bp))
10184                         /* block FW from writing to host */
10185                         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10186
10187                 /* wait until BRB is empty */
10188                 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10189                 while (timer_count) {
10190                         u32 prev_brb = tmp_reg;
10191
10192                         tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10193                         if (!tmp_reg)
10194                                 break;
10195
10196                         BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg);
10197
10198                         /* reset timer as long as BRB actually gets emptied */
10199                         if (prev_brb > tmp_reg)
10200                                 timer_count = 1000;
10201                         else
10202                                 timer_count--;
10203
10204                         /* New UNDI FW supports MF and contains better
10205                          * cleaning methods - might be redundant but harmless.
10206                          */
10207                         if (bnx2x_prev_unload_undi_fw_supports_mf(bp)) {
10208                                 bnx2x_prev_unload_undi_mf(bp);
10209                         } else if (prev_undi) {
10210                                 /* If UNDI resides in memory,
10211                                  * manually increment it
10212                                  */
10213                                 bnx2x_prev_unload_undi_inc(bp, BP_PORT(bp), 1);
10214                         }
10215                         udelay(10);
10216                 }
10217
10218                 if (!timer_count)
10219                         BNX2X_ERR("Failed to empty BRB, hope for the best\n");
10220         }
10221
10222         /* No packets are in the pipeline, path is ready for reset */
10223         bnx2x_reset_common(bp);
10224
10225         if (mac_vals.xmac_addr)
10226                 REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val);
10227         if (mac_vals.umac_addr)
10228                 REG_WR(bp, mac_vals.umac_addr, mac_vals.umac_val);
10229         if (mac_vals.emac_addr)
10230                 REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val);
10231         if (mac_vals.bmac_addr) {
10232                 REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
10233                 REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
10234         }
10235
10236         rc = bnx2x_prev_mark_path(bp, prev_undi);
10237         if (rc) {
10238                 bnx2x_prev_mcp_done(bp);
10239                 return rc;
10240         }
10241
10242         return bnx2x_prev_mcp_done(bp);
10243 }
10244
10245 /* previous driver DMAE transaction may have occurred when pre-boot stage ended
10246  * and boot began, or when kdump kernel was loaded. Either case would invalidate
10247  * the addresses of the transaction, resulting in was-error bit set in the pci
10248  * causing all hw-to-host pcie transactions to timeout. If this happened we want
10249  * to clear the interrupt which detected this from the pglueb and the was done
10250  * bit
10251  */
10252 static void bnx2x_prev_interrupted_dmae(struct bnx2x *bp)
10253 {
10254         if (!CHIP_IS_E1x(bp)) {
10255                 u32 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS);
10256                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
10257                         DP(BNX2X_MSG_SP,
10258                            "'was error' bit was found to be set in pglueb upon startup. Clearing\n");
10259                         REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
10260                                1 << BP_FUNC(bp));
10261                 }
10262         }
10263 }
10264
10265 static int bnx2x_prev_unload(struct bnx2x *bp)
10266 {
10267         int time_counter = 10;
10268         u32 rc, fw, hw_lock_reg, hw_lock_val;
10269         BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
10270
10271         /* clear hw from errors which may have resulted from an interrupted
10272          * dmae transaction.
10273          */
10274         bnx2x_prev_interrupted_dmae(bp);
10275
10276         /* Release previously held locks */
10277         hw_lock_reg = (BP_FUNC(bp) <= 5) ?
10278                       (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) :
10279                       (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8);
10280
10281         hw_lock_val = REG_RD(bp, hw_lock_reg);
10282         if (hw_lock_val) {
10283                 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
10284                         BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
10285                         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
10286                                (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp)));
10287                 }
10288
10289                 BNX2X_DEV_INFO("Release Previously held hw lock\n");
10290                 REG_WR(bp, hw_lock_reg, 0xffffffff);
10291         } else
10292                 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
10293
10294         if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {
10295                 BNX2X_DEV_INFO("Release previously held alr\n");
10296                 bnx2x_release_alr(bp);
10297         }
10298
10299         do {
10300                 int aer = 0;
10301                 /* Lock MCP using an unload request */
10302                 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
10303                 if (!fw) {
10304                         BNX2X_ERR("MCP response failure, aborting\n");
10305                         rc = -EBUSY;
10306                         break;
10307                 }
10308
10309                 rc = down_interruptible(&bnx2x_prev_sem);
10310                 if (rc) {
10311                         BNX2X_ERR("Cannot check for AER; Received %d when tried to take lock\n",
10312                                   rc);
10313                 } else {
10314                         /* If Path is marked by EEH, ignore unload status */
10315                         aer = !!(bnx2x_prev_path_get_entry(bp) &&
10316                                  bnx2x_prev_path_get_entry(bp)->aer);
10317                         up(&bnx2x_prev_sem);
10318                 }
10319
10320                 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON || aer) {
10321                         rc = bnx2x_prev_unload_common(bp);
10322                         break;
10323                 }
10324
10325                 /* non-common reply from MCP might require looping */
10326                 rc = bnx2x_prev_unload_uncommon(bp);
10327                 if (rc != BNX2X_PREV_WAIT_NEEDED)
10328                         break;
10329
10330                 msleep(20);
10331         } while (--time_counter);
10332
10333         if (!time_counter || rc) {
10334                 BNX2X_DEV_INFO("Unloading previous driver did not occur, Possibly due to MF UNDI\n");
10335                 rc = -EPROBE_DEFER;
10336         }
10337
10338         /* Mark function if its port was used to boot from SAN */
10339         if (bnx2x_port_after_undi(bp))
10340                 bp->link_params.feature_config_flags |=
10341                         FEATURE_CONFIG_BOOT_FROM_SAN;
10342
10343         BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc);
10344
10345         return rc;
10346 }
10347
10348 static void bnx2x_get_common_hwinfo(struct bnx2x *bp)
10349 {
10350         u32 val, val2, val3, val4, id, boot_mode;
10351         u16 pmc;
10352
10353         /* Get the chip revision id and number. */
10354         /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
10355         val = REG_RD(bp, MISC_REG_CHIP_NUM);
10356         id = ((val & 0xffff) << 16);
10357         val = REG_RD(bp, MISC_REG_CHIP_REV);
10358         id |= ((val & 0xf) << 12);
10359
10360         /* Metal is read from PCI regs, but we can't access >=0x400 from
10361          * the configuration space (so we need to reg_rd)
10362          */
10363         val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3);
10364         id |= (((val >> 24) & 0xf) << 4);
10365         val = REG_RD(bp, MISC_REG_BOND_ID);
10366         id |= (val & 0xf);
10367         bp->common.chip_id = id;
10368
10369         /* force 57811 according to MISC register */
10370         if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
10371                 if (CHIP_IS_57810(bp))
10372                         bp->common.chip_id = (CHIP_NUM_57811 << 16) |
10373                                 (bp->common.chip_id & 0x0000FFFF);
10374                 else if (CHIP_IS_57810_MF(bp))
10375                         bp->common.chip_id = (CHIP_NUM_57811_MF << 16) |
10376                                 (bp->common.chip_id & 0x0000FFFF);
10377                 bp->common.chip_id |= 0x1;
10378         }
10379
10380         /* Set doorbell size */
10381         bp->db_size = (1 << BNX2X_DB_SHIFT);
10382
10383         if (!CHIP_IS_E1x(bp)) {
10384                 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
10385                 if ((val & 1) == 0)
10386                         val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
10387                 else
10388                         val = (val >> 1) & 1;
10389                 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
10390                                                        "2_PORT_MODE");
10391                 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
10392                                                  CHIP_2_PORT_MODE;
10393
10394                 if (CHIP_MODE_IS_4_PORT(bp))
10395                         bp->pfid = (bp->pf_num >> 1);   /* 0..3 */
10396                 else
10397                         bp->pfid = (bp->pf_num & 0x6);  /* 0, 2, 4, 6 */
10398         } else {
10399                 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
10400                 bp->pfid = bp->pf_num;                  /* 0..7 */
10401         }
10402
10403         BNX2X_DEV_INFO("pf_id: %x", bp->pfid);
10404
10405         bp->link_params.chip_id = bp->common.chip_id;
10406         BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
10407
10408         val = (REG_RD(bp, 0x2874) & 0x55);
10409         if ((bp->common.chip_id & 0x1) ||
10410             (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
10411                 bp->flags |= ONE_PORT_FLAG;
10412                 BNX2X_DEV_INFO("single port device\n");
10413         }
10414
10415         val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
10416         bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
10417                                  (val & MCPR_NVM_CFG4_FLASH_SIZE));
10418         BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
10419                        bp->common.flash_size, bp->common.flash_size);
10420
10421         bnx2x_init_shmem(bp);
10422
10423         bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
10424                                         MISC_REG_GENERIC_CR_1 :
10425                                         MISC_REG_GENERIC_CR_0));
10426
10427         bp->link_params.shmem_base = bp->common.shmem_base;
10428         bp->link_params.shmem2_base = bp->common.shmem2_base;
10429         if (SHMEM2_RD(bp, size) >
10430             (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
10431                 bp->link_params.lfa_base =
10432                 REG_RD(bp, bp->common.shmem2_base +
10433                        (u32)offsetof(struct shmem2_region,
10434                                      lfa_host_addr[BP_PORT(bp)]));
10435         else
10436                 bp->link_params.lfa_base = 0;
10437         BNX2X_DEV_INFO("shmem offset 0x%x  shmem2 offset 0x%x\n",
10438                        bp->common.shmem_base, bp->common.shmem2_base);
10439
10440         if (!bp->common.shmem_base) {
10441                 BNX2X_DEV_INFO("MCP not active\n");
10442                 bp->flags |= NO_MCP_FLAG;
10443                 return;
10444         }
10445
10446         bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
10447         BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
10448
10449         bp->link_params.hw_led_mode = ((bp->common.hw_config &
10450                                         SHARED_HW_CFG_LED_MODE_MASK) >>
10451                                        SHARED_HW_CFG_LED_MODE_SHIFT);
10452
10453         bp->link_params.feature_config_flags = 0;
10454         val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
10455         if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
10456                 bp->link_params.feature_config_flags |=
10457                                 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10458         else
10459                 bp->link_params.feature_config_flags &=
10460                                 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10461
10462         val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
10463         bp->common.bc_ver = val;
10464         BNX2X_DEV_INFO("bc_ver %X\n", val);
10465         if (val < BNX2X_BC_VER) {
10466                 /* for now only warn
10467                  * later we might need to enforce this */
10468                 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
10469                           BNX2X_BC_VER, val);
10470         }
10471         bp->link_params.feature_config_flags |=
10472                                 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
10473                                 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
10474
10475         bp->link_params.feature_config_flags |=
10476                 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
10477                 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
10478         bp->link_params.feature_config_flags |=
10479                 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
10480                 FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
10481         bp->link_params.feature_config_flags |=
10482                 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
10483                 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
10484
10485         bp->link_params.feature_config_flags |=
10486                 (val >= REQ_BC_VER_4_MT_SUPPORTED) ?
10487                 FEATURE_CONFIG_MT_SUPPORT : 0;
10488
10489         bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
10490                         BC_SUPPORTS_PFC_STATS : 0;
10491
10492         bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ?
10493                         BC_SUPPORTS_FCOE_FEATURES : 0;
10494
10495         bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ?
10496                         BC_SUPPORTS_DCBX_MSG_NON_PMF : 0;
10497
10498         bp->flags |= (val >= REQ_BC_VER_4_RMMOD_CMD) ?
10499                         BC_SUPPORTS_RMMOD_CMD : 0;
10500
10501         boot_mode = SHMEM_RD(bp,
10502                         dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
10503                         PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK;
10504         switch (boot_mode) {
10505         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE:
10506                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
10507                 break;
10508         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB:
10509                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
10510                 break;
10511         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT:
10512                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
10513                 break;
10514         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE:
10515                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
10516                 break;
10517         }
10518
10519         pci_read_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_PMC, &pmc);
10520         bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
10521
10522         BNX2X_DEV_INFO("%sWoL capable\n",
10523                        (bp->flags & NO_WOL_FLAG) ? "not " : "");
10524
10525         val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
10526         val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
10527         val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
10528         val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
10529
10530         dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
10531                  val, val2, val3, val4);
10532 }
10533
10534 #define IGU_FID(val)    GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
10535 #define IGU_VEC(val)    GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
10536
10537 static int bnx2x_get_igu_cam_info(struct bnx2x *bp)
10538 {
10539         int pfid = BP_FUNC(bp);
10540         int igu_sb_id;
10541         u32 val;
10542         u8 fid, igu_sb_cnt = 0;
10543
10544         bp->igu_base_sb = 0xff;
10545         if (CHIP_INT_MODE_IS_BC(bp)) {
10546                 int vn = BP_VN(bp);
10547                 igu_sb_cnt = bp->igu_sb_cnt;
10548                 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
10549                         FP_SB_MAX_E1x;
10550
10551                 bp->igu_dsb_id =  E1HVN_MAX * FP_SB_MAX_E1x +
10552                         (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
10553
10554                 return 0;
10555         }
10556
10557         /* IGU in normal mode - read CAM */
10558         for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
10559              igu_sb_id++) {
10560                 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
10561                 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
10562                         continue;
10563                 fid = IGU_FID(val);
10564                 if ((fid & IGU_FID_ENCODE_IS_PF)) {
10565                         if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
10566                                 continue;
10567                         if (IGU_VEC(val) == 0)
10568                                 /* default status block */
10569                                 bp->igu_dsb_id = igu_sb_id;
10570                         else {
10571                                 if (bp->igu_base_sb == 0xff)
10572                                         bp->igu_base_sb = igu_sb_id;
10573                                 igu_sb_cnt++;
10574                         }
10575                 }
10576         }
10577
10578 #ifdef CONFIG_PCI_MSI
10579         /* Due to new PF resource allocation by MFW T7.4 and above, it's
10580          * optional that number of CAM entries will not be equal to the value
10581          * advertised in PCI.
10582          * Driver should use the minimal value of both as the actual status
10583          * block count
10584          */
10585         bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt);
10586 #endif
10587
10588         if (igu_sb_cnt == 0) {
10589                 BNX2X_ERR("CAM configuration error\n");
10590                 return -EINVAL;
10591         }
10592
10593         return 0;
10594 }
10595
10596 static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
10597 {
10598         int cfg_size = 0, idx, port = BP_PORT(bp);
10599
10600         /* Aggregation of supported attributes of all external phys */
10601         bp->port.supported[0] = 0;
10602         bp->port.supported[1] = 0;
10603         switch (bp->link_params.num_phys) {
10604         case 1:
10605                 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
10606                 cfg_size = 1;
10607                 break;
10608         case 2:
10609                 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
10610                 cfg_size = 1;
10611                 break;
10612         case 3:
10613                 if (bp->link_params.multi_phy_config &
10614                     PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
10615                         bp->port.supported[1] =
10616                                 bp->link_params.phy[EXT_PHY1].supported;
10617                         bp->port.supported[0] =
10618                                 bp->link_params.phy[EXT_PHY2].supported;
10619                 } else {
10620                         bp->port.supported[0] =
10621                                 bp->link_params.phy[EXT_PHY1].supported;
10622                         bp->port.supported[1] =
10623                                 bp->link_params.phy[EXT_PHY2].supported;
10624                 }
10625                 cfg_size = 2;
10626                 break;
10627         }
10628
10629         if (!(bp->port.supported[0] || bp->port.supported[1])) {
10630                 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
10631                            SHMEM_RD(bp,
10632                            dev_info.port_hw_config[port].external_phy_config),
10633                            SHMEM_RD(bp,
10634                            dev_info.port_hw_config[port].external_phy_config2));
10635                         return;
10636         }
10637
10638         if (CHIP_IS_E3(bp))
10639                 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
10640         else {
10641                 switch (switch_cfg) {
10642                 case SWITCH_CFG_1G:
10643                         bp->port.phy_addr = REG_RD(
10644                                 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
10645                         break;
10646                 case SWITCH_CFG_10G:
10647                         bp->port.phy_addr = REG_RD(
10648                                 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
10649                         break;
10650                 default:
10651                         BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
10652                                   bp->port.link_config[0]);
10653                         return;
10654                 }
10655         }
10656         BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
10657         /* mask what we support according to speed_cap_mask per configuration */
10658         for (idx = 0; idx < cfg_size; idx++) {
10659                 if (!(bp->link_params.speed_cap_mask[idx] &
10660                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
10661                         bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
10662
10663                 if (!(bp->link_params.speed_cap_mask[idx] &
10664                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
10665                         bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
10666
10667                 if (!(bp->link_params.speed_cap_mask[idx] &
10668                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
10669                         bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
10670
10671                 if (!(bp->link_params.speed_cap_mask[idx] &
10672                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
10673                         bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
10674
10675                 if (!(bp->link_params.speed_cap_mask[idx] &
10676                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
10677                         bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
10678                                                      SUPPORTED_1000baseT_Full);
10679
10680                 if (!(bp->link_params.speed_cap_mask[idx] &
10681                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
10682                         bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
10683
10684                 if (!(bp->link_params.speed_cap_mask[idx] &
10685                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
10686                         bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
10687
10688                 if (!(bp->link_params.speed_cap_mask[idx] &
10689                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))
10690                         bp->port.supported[idx] &= ~SUPPORTED_20000baseKR2_Full;
10691         }
10692
10693         BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
10694                        bp->port.supported[1]);
10695 }
10696
10697 static void bnx2x_link_settings_requested(struct bnx2x *bp)
10698 {
10699         u32 link_config, idx, cfg_size = 0;
10700         bp->port.advertising[0] = 0;
10701         bp->port.advertising[1] = 0;
10702         switch (bp->link_params.num_phys) {
10703         case 1:
10704         case 2:
10705                 cfg_size = 1;
10706                 break;
10707         case 3:
10708                 cfg_size = 2;
10709                 break;
10710         }
10711         for (idx = 0; idx < cfg_size; idx++) {
10712                 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
10713                 link_config = bp->port.link_config[idx];
10714                 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
10715                 case PORT_FEATURE_LINK_SPEED_AUTO:
10716                         if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
10717                                 bp->link_params.req_line_speed[idx] =
10718                                         SPEED_AUTO_NEG;
10719                                 bp->port.advertising[idx] |=
10720                                         bp->port.supported[idx];
10721                                 if (bp->link_params.phy[EXT_PHY1].type ==
10722                                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
10723                                         bp->port.advertising[idx] |=
10724                                         (SUPPORTED_100baseT_Half |
10725                                          SUPPORTED_100baseT_Full);
10726                         } else {
10727                                 /* force 10G, no AN */
10728                                 bp->link_params.req_line_speed[idx] =
10729                                         SPEED_10000;
10730                                 bp->port.advertising[idx] |=
10731                                         (ADVERTISED_10000baseT_Full |
10732                                          ADVERTISED_FIBRE);
10733                                 continue;
10734                         }
10735                         break;
10736
10737                 case PORT_FEATURE_LINK_SPEED_10M_FULL:
10738                         if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
10739                                 bp->link_params.req_line_speed[idx] =
10740                                         SPEED_10;
10741                                 bp->port.advertising[idx] |=
10742                                         (ADVERTISED_10baseT_Full |
10743                                          ADVERTISED_TP);
10744                         } else {
10745                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10746                                             link_config,
10747                                     bp->link_params.speed_cap_mask[idx]);
10748                                 return;
10749                         }
10750                         break;
10751
10752                 case PORT_FEATURE_LINK_SPEED_10M_HALF:
10753                         if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
10754                                 bp->link_params.req_line_speed[idx] =
10755                                         SPEED_10;
10756                                 bp->link_params.req_duplex[idx] =
10757                                         DUPLEX_HALF;
10758                                 bp->port.advertising[idx] |=
10759                                         (ADVERTISED_10baseT_Half |
10760                                          ADVERTISED_TP);
10761                         } else {
10762                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10763                                             link_config,
10764                                           bp->link_params.speed_cap_mask[idx]);
10765                                 return;
10766                         }
10767                         break;
10768
10769                 case PORT_FEATURE_LINK_SPEED_100M_FULL:
10770                         if (bp->port.supported[idx] &
10771                             SUPPORTED_100baseT_Full) {
10772                                 bp->link_params.req_line_speed[idx] =
10773                                         SPEED_100;
10774                                 bp->port.advertising[idx] |=
10775                                         (ADVERTISED_100baseT_Full |
10776                                          ADVERTISED_TP);
10777                         } else {
10778                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10779                                             link_config,
10780                                           bp->link_params.speed_cap_mask[idx]);
10781                                 return;
10782                         }
10783                         break;
10784
10785                 case PORT_FEATURE_LINK_SPEED_100M_HALF:
10786                         if (bp->port.supported[idx] &
10787                             SUPPORTED_100baseT_Half) {
10788                                 bp->link_params.req_line_speed[idx] =
10789                                                                 SPEED_100;
10790                                 bp->link_params.req_duplex[idx] =
10791                                                                 DUPLEX_HALF;
10792                                 bp->port.advertising[idx] |=
10793                                         (ADVERTISED_100baseT_Half |
10794                                          ADVERTISED_TP);
10795                         } else {
10796                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10797                                     link_config,
10798                                     bp->link_params.speed_cap_mask[idx]);
10799                                 return;
10800                         }
10801                         break;
10802
10803                 case PORT_FEATURE_LINK_SPEED_1G:
10804                         if (bp->port.supported[idx] &
10805                             SUPPORTED_1000baseT_Full) {
10806                                 bp->link_params.req_line_speed[idx] =
10807                                         SPEED_1000;
10808                                 bp->port.advertising[idx] |=
10809                                         (ADVERTISED_1000baseT_Full |
10810                                          ADVERTISED_TP);
10811                         } else {
10812                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10813                                     link_config,
10814                                     bp->link_params.speed_cap_mask[idx]);
10815                                 return;
10816                         }
10817                         break;
10818
10819                 case PORT_FEATURE_LINK_SPEED_2_5G:
10820                         if (bp->port.supported[idx] &
10821                             SUPPORTED_2500baseX_Full) {
10822                                 bp->link_params.req_line_speed[idx] =
10823                                         SPEED_2500;
10824                                 bp->port.advertising[idx] |=
10825                                         (ADVERTISED_2500baseX_Full |
10826                                                 ADVERTISED_TP);
10827                         } else {
10828                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10829                                     link_config,
10830                                     bp->link_params.speed_cap_mask[idx]);
10831                                 return;
10832                         }
10833                         break;
10834
10835                 case PORT_FEATURE_LINK_SPEED_10G_CX4:
10836                         if (bp->port.supported[idx] &
10837                             SUPPORTED_10000baseT_Full) {
10838                                 bp->link_params.req_line_speed[idx] =
10839                                         SPEED_10000;
10840                                 bp->port.advertising[idx] |=
10841                                         (ADVERTISED_10000baseT_Full |
10842                                                 ADVERTISED_FIBRE);
10843                         } else {
10844                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
10845                                     link_config,
10846                                     bp->link_params.speed_cap_mask[idx]);
10847                                 return;
10848                         }
10849                         break;
10850                 case PORT_FEATURE_LINK_SPEED_20G:
10851                         bp->link_params.req_line_speed[idx] = SPEED_20000;
10852
10853                         break;
10854                 default:
10855                         BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
10856                                   link_config);
10857                                 bp->link_params.req_line_speed[idx] =
10858                                                         SPEED_AUTO_NEG;
10859                                 bp->port.advertising[idx] =
10860                                                 bp->port.supported[idx];
10861                         break;
10862                 }
10863
10864                 bp->link_params.req_flow_ctrl[idx] = (link_config &
10865                                          PORT_FEATURE_FLOW_CONTROL_MASK);
10866                 if (bp->link_params.req_flow_ctrl[idx] ==
10867                     BNX2X_FLOW_CTRL_AUTO) {
10868                         if (!(bp->port.supported[idx] & SUPPORTED_Autoneg))
10869                                 bp->link_params.req_flow_ctrl[idx] =
10870                                                         BNX2X_FLOW_CTRL_NONE;
10871                         else
10872                                 bnx2x_set_requested_fc(bp);
10873                 }
10874
10875                 BNX2X_DEV_INFO("req_line_speed %d  req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
10876                                bp->link_params.req_line_speed[idx],
10877                                bp->link_params.req_duplex[idx],
10878                                bp->link_params.req_flow_ctrl[idx],
10879                                bp->port.advertising[idx]);
10880         }
10881 }
10882
10883 static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
10884 {
10885         __be16 mac_hi_be = cpu_to_be16(mac_hi);
10886         __be32 mac_lo_be = cpu_to_be32(mac_lo);
10887         memcpy(mac_buf, &mac_hi_be, sizeof(mac_hi_be));
10888         memcpy(mac_buf + sizeof(mac_hi_be), &mac_lo_be, sizeof(mac_lo_be));
10889 }
10890
10891 static void bnx2x_get_port_hwinfo(struct bnx2x *bp)
10892 {
10893         int port = BP_PORT(bp);
10894         u32 config;
10895         u32 ext_phy_type, ext_phy_config, eee_mode;
10896
10897         bp->link_params.bp = bp;
10898         bp->link_params.port = port;
10899
10900         bp->link_params.lane_config =
10901                 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
10902
10903         bp->link_params.speed_cap_mask[0] =
10904                 SHMEM_RD(bp,
10905                          dev_info.port_hw_config[port].speed_capability_mask) &
10906                 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
10907         bp->link_params.speed_cap_mask[1] =
10908                 SHMEM_RD(bp,
10909                          dev_info.port_hw_config[port].speed_capability_mask2) &
10910                 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
10911         bp->port.link_config[0] =
10912                 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
10913
10914         bp->port.link_config[1] =
10915                 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
10916
10917         bp->link_params.multi_phy_config =
10918                 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
10919         /* If the device is capable of WoL, set the default state according
10920          * to the HW
10921          */
10922         config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
10923         bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
10924                    (config & PORT_FEATURE_WOL_ENABLED));
10925
10926         if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
10927             PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE && !IS_MF(bp))
10928                 bp->flags |= NO_ISCSI_FLAG;
10929         if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
10930             PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI && !(IS_MF(bp)))
10931                 bp->flags |= NO_FCOE_FLAG;
10932
10933         BNX2X_DEV_INFO("lane_config 0x%08x  speed_cap_mask0 0x%08x  link_config0 0x%08x\n",
10934                        bp->link_params.lane_config,
10935                        bp->link_params.speed_cap_mask[0],
10936                        bp->port.link_config[0]);
10937
10938         bp->link_params.switch_cfg = (bp->port.link_config[0] &
10939                                       PORT_FEATURE_CONNECTED_SWITCH_MASK);
10940         bnx2x_phy_probe(&bp->link_params);
10941         bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
10942
10943         bnx2x_link_settings_requested(bp);
10944
10945         /*
10946          * If connected directly, work with the internal PHY, otherwise, work
10947          * with the external PHY
10948          */
10949         ext_phy_config =
10950                 SHMEM_RD(bp,
10951                          dev_info.port_hw_config[port].external_phy_config);
10952         ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
10953         if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
10954                 bp->mdio.prtad = bp->port.phy_addr;
10955
10956         else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
10957                  (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
10958                 bp->mdio.prtad =
10959                         XGXS_EXT_PHY_ADDR(ext_phy_config);
10960
10961         /* Configure link feature according to nvram value */
10962         eee_mode = (((SHMEM_RD(bp, dev_info.
10963                       port_feature_config[port].eee_power_mode)) &
10964                      PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
10965                     PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
10966         if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
10967                 bp->link_params.eee_mode = EEE_MODE_ADV_LPI |
10968                                            EEE_MODE_ENABLE_LPI |
10969                                            EEE_MODE_OUTPUT_TIME;
10970         } else {
10971                 bp->link_params.eee_mode = 0;
10972         }
10973 }
10974
10975 void bnx2x_get_iscsi_info(struct bnx2x *bp)
10976 {
10977         u32 no_flags = NO_ISCSI_FLAG;
10978         int port = BP_PORT(bp);
10979         u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
10980                                 drv_lic_key[port].max_iscsi_conn);
10981
10982         if (!CNIC_SUPPORT(bp)) {
10983                 bp->flags |= no_flags;
10984                 return;
10985         }
10986
10987         /* Get the number of maximum allowed iSCSI connections */
10988         bp->cnic_eth_dev.max_iscsi_conn =
10989                 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
10990                 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
10991
10992         BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
10993                        bp->cnic_eth_dev.max_iscsi_conn);
10994
10995         /*
10996          * If maximum allowed number of connections is zero -
10997          * disable the feature.
10998          */
10999         if (!bp->cnic_eth_dev.max_iscsi_conn)
11000                 bp->flags |= no_flags;
11001 }
11002
11003 static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func)
11004 {
11005         /* Port info */
11006         bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11007                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper);
11008         bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11009                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower);
11010
11011         /* Node info */
11012         bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11013                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper);
11014         bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11015                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower);
11016 }
11017
11018 static int bnx2x_shared_fcoe_funcs(struct bnx2x *bp)
11019 {
11020         u8 count = 0;
11021
11022         if (IS_MF(bp)) {
11023                 u8 fid;
11024
11025                 /* iterate over absolute function ids for this path: */
11026                 for (fid = BP_PATH(bp); fid < E2_FUNC_MAX * 2; fid += 2) {
11027                         if (IS_MF_SD(bp)) {
11028                                 u32 cfg = MF_CFG_RD(bp,
11029                                                     func_mf_config[fid].config);
11030
11031                                 if (!(cfg & FUNC_MF_CFG_FUNC_HIDE) &&
11032                                     ((cfg & FUNC_MF_CFG_PROTOCOL_MASK) ==
11033                                             FUNC_MF_CFG_PROTOCOL_FCOE))
11034                                         count++;
11035                         } else {
11036                                 u32 cfg = MF_CFG_RD(bp,
11037                                                     func_ext_config[fid].
11038                                                                       func_cfg);
11039
11040                                 if ((cfg & MACP_FUNC_CFG_FLAGS_ENABLED) &&
11041                                     (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD))
11042                                         count++;
11043                         }
11044                 }
11045         } else { /* SF */
11046                 int port, port_cnt = CHIP_MODE_IS_4_PORT(bp) ? 2 : 1;
11047
11048                 for (port = 0; port < port_cnt; port++) {
11049                         u32 lic = SHMEM_RD(bp,
11050                                            drv_lic_key[port].max_fcoe_conn) ^
11051                                   FW_ENCODE_32BIT_PATTERN;
11052                         if (lic)
11053                                 count++;
11054                 }
11055         }
11056
11057         return count;
11058 }
11059
11060 static void bnx2x_get_fcoe_info(struct bnx2x *bp)
11061 {
11062         int port = BP_PORT(bp);
11063         int func = BP_ABS_FUNC(bp);
11064         u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
11065                                 drv_lic_key[port].max_fcoe_conn);
11066         u8 num_fcoe_func = bnx2x_shared_fcoe_funcs(bp);
11067
11068         if (!CNIC_SUPPORT(bp)) {
11069                 bp->flags |= NO_FCOE_FLAG;
11070                 return;
11071         }
11072
11073         /* Get the number of maximum allowed FCoE connections */
11074         bp->cnic_eth_dev.max_fcoe_conn =
11075                 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
11076                 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
11077
11078         /* Calculate the number of maximum allowed FCoE tasks */
11079         bp->cnic_eth_dev.max_fcoe_exchanges = MAX_NUM_FCOE_TASKS_PER_ENGINE;
11080
11081         /* check if FCoE resources must be shared between different functions */
11082         if (num_fcoe_func)
11083                 bp->cnic_eth_dev.max_fcoe_exchanges /= num_fcoe_func;
11084
11085         /* Read the WWN: */
11086         if (!IS_MF(bp)) {
11087                 /* Port info */
11088                 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11089                         SHMEM_RD(bp,
11090                                  dev_info.port_hw_config[port].
11091                                  fcoe_wwn_port_name_upper);
11092                 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11093                         SHMEM_RD(bp,
11094                                  dev_info.port_hw_config[port].
11095                                  fcoe_wwn_port_name_lower);
11096
11097                 /* Node info */
11098                 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11099                         SHMEM_RD(bp,
11100                                  dev_info.port_hw_config[port].
11101                                  fcoe_wwn_node_name_upper);
11102                 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11103                         SHMEM_RD(bp,
11104                                  dev_info.port_hw_config[port].
11105                                  fcoe_wwn_node_name_lower);
11106         } else if (!IS_MF_SD(bp)) {
11107                 /*
11108                  * Read the WWN info only if the FCoE feature is enabled for
11109                  * this function.
11110                  */
11111                 if (BNX2X_MF_EXT_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp))
11112                         bnx2x_get_ext_wwn_info(bp, func);
11113
11114         } else if (IS_MF_FCOE_SD(bp) && !CHIP_IS_E1x(bp)) {
11115                 bnx2x_get_ext_wwn_info(bp, func);
11116         }
11117
11118         BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
11119
11120         /*
11121          * If maximum allowed number of connections is zero -
11122          * disable the feature.
11123          */
11124         if (!bp->cnic_eth_dev.max_fcoe_conn)
11125                 bp->flags |= NO_FCOE_FLAG;
11126 }
11127
11128 static void bnx2x_get_cnic_info(struct bnx2x *bp)
11129 {
11130         /*
11131          * iSCSI may be dynamically disabled but reading
11132          * info here we will decrease memory usage by driver
11133          * if the feature is disabled for good
11134          */
11135         bnx2x_get_iscsi_info(bp);
11136         bnx2x_get_fcoe_info(bp);
11137 }
11138
11139 static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp)
11140 {
11141         u32 val, val2;
11142         int func = BP_ABS_FUNC(bp);
11143         int port = BP_PORT(bp);
11144         u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
11145         u8 *fip_mac = bp->fip_mac;
11146
11147         if (IS_MF(bp)) {
11148                 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
11149                  * FCoE MAC then the appropriate feature should be disabled.
11150                  * In non SD mode features configuration comes from struct
11151                  * func_ext_config.
11152                  */
11153                 if (!IS_MF_SD(bp) && !CHIP_IS_E1x(bp)) {
11154                         u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
11155                         if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
11156                                 val2 = MF_CFG_RD(bp, func_ext_config[func].
11157                                                  iscsi_mac_addr_upper);
11158                                 val = MF_CFG_RD(bp, func_ext_config[func].
11159                                                 iscsi_mac_addr_lower);
11160                                 bnx2x_set_mac_buf(iscsi_mac, val, val2);
11161                                 BNX2X_DEV_INFO
11162                                         ("Read iSCSI MAC: %pM\n", iscsi_mac);
11163                         } else {
11164                                 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
11165                         }
11166
11167                         if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
11168                                 val2 = MF_CFG_RD(bp, func_ext_config[func].
11169                                                  fcoe_mac_addr_upper);
11170                                 val = MF_CFG_RD(bp, func_ext_config[func].
11171                                                 fcoe_mac_addr_lower);
11172                                 bnx2x_set_mac_buf(fip_mac, val, val2);
11173                                 BNX2X_DEV_INFO
11174                                         ("Read FCoE L2 MAC: %pM\n", fip_mac);
11175                         } else {
11176                                 bp->flags |= NO_FCOE_FLAG;
11177                         }
11178
11179                         bp->mf_ext_config = cfg;
11180
11181                 } else { /* SD MODE */
11182                         if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) {
11183                                 /* use primary mac as iscsi mac */
11184                                 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN);
11185
11186                                 BNX2X_DEV_INFO("SD ISCSI MODE\n");
11187                                 BNX2X_DEV_INFO
11188                                         ("Read iSCSI MAC: %pM\n", iscsi_mac);
11189                         } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) {
11190                                 /* use primary mac as fip mac */
11191                                 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
11192                                 BNX2X_DEV_INFO("SD FCoE MODE\n");
11193                                 BNX2X_DEV_INFO
11194                                         ("Read FIP MAC: %pM\n", fip_mac);
11195                         }
11196                 }
11197
11198                 /* If this is a storage-only interface, use SAN mac as
11199                  * primary MAC. Notice that for SD this is already the case,
11200                  * as the SAN mac was copied from the primary MAC.
11201                  */
11202                 if (IS_MF_FCOE_AFEX(bp))
11203                         memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN);
11204         } else {
11205                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
11206                                 iscsi_mac_upper);
11207                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
11208                                iscsi_mac_lower);
11209                 bnx2x_set_mac_buf(iscsi_mac, val, val2);
11210
11211                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
11212                                 fcoe_fip_mac_upper);
11213                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
11214                                fcoe_fip_mac_lower);
11215                 bnx2x_set_mac_buf(fip_mac, val, val2);
11216         }
11217
11218         /* Disable iSCSI OOO if MAC configuration is invalid. */
11219         if (!is_valid_ether_addr(iscsi_mac)) {
11220                 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
11221                 memset(iscsi_mac, 0, ETH_ALEN);
11222         }
11223
11224         /* Disable FCoE if MAC configuration is invalid. */
11225         if (!is_valid_ether_addr(fip_mac)) {
11226                 bp->flags |= NO_FCOE_FLAG;
11227                 memset(bp->fip_mac, 0, ETH_ALEN);
11228         }
11229 }
11230
11231 static void bnx2x_get_mac_hwinfo(struct bnx2x *bp)
11232 {
11233         u32 val, val2;
11234         int func = BP_ABS_FUNC(bp);
11235         int port = BP_PORT(bp);
11236
11237         /* Zero primary MAC configuration */
11238         memset(bp->dev->dev_addr, 0, ETH_ALEN);
11239
11240         if (BP_NOMCP(bp)) {
11241                 BNX2X_ERROR("warning: random MAC workaround active\n");
11242                 eth_hw_addr_random(bp->dev);
11243         } else if (IS_MF(bp)) {
11244                 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
11245                 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
11246                 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
11247                     (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
11248                         bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11249
11250                 if (CNIC_SUPPORT(bp))
11251                         bnx2x_get_cnic_mac_hwinfo(bp);
11252         } else {
11253                 /* in SF read MACs from port configuration */
11254                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11255                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11256                 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11257
11258                 if (CNIC_SUPPORT(bp))
11259                         bnx2x_get_cnic_mac_hwinfo(bp);
11260         }
11261
11262         if (!BP_NOMCP(bp)) {
11263                 /* Read physical port identifier from shmem */
11264                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11265                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11266                 bnx2x_set_mac_buf(bp->phys_port_id, val, val2);
11267                 bp->flags |= HAS_PHYS_PORT_ID;
11268         }
11269
11270         memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
11271
11272         if (!bnx2x_is_valid_ether_addr(bp, bp->dev->dev_addr))
11273                 dev_err(&bp->pdev->dev,
11274                         "bad Ethernet MAC address configuration: %pM\n"
11275                         "change it manually before bringing up the appropriate network interface\n",
11276                         bp->dev->dev_addr);
11277 }
11278
11279 static bool bnx2x_get_dropless_info(struct bnx2x *bp)
11280 {
11281         int tmp;
11282         u32 cfg;
11283
11284         if (IS_VF(bp))
11285                 return 0;
11286
11287         if (IS_MF(bp) && !CHIP_IS_E1x(bp)) {
11288                 /* Take function: tmp = func */
11289                 tmp = BP_ABS_FUNC(bp);
11290                 cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg);
11291                 cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING);
11292         } else {
11293                 /* Take port: tmp = port */
11294                 tmp = BP_PORT(bp);
11295                 cfg = SHMEM_RD(bp,
11296                                dev_info.port_hw_config[tmp].generic_features);
11297                 cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED);
11298         }
11299         return cfg;
11300 }
11301
11302 static int bnx2x_get_hwinfo(struct bnx2x *bp)
11303 {
11304         int /*abs*/func = BP_ABS_FUNC(bp);
11305         int vn;
11306         u32 val = 0;
11307         int rc = 0;
11308
11309         bnx2x_get_common_hwinfo(bp);
11310
11311         /*
11312          * initialize IGU parameters
11313          */
11314         if (CHIP_IS_E1x(bp)) {
11315                 bp->common.int_block = INT_BLOCK_HC;
11316
11317                 bp->igu_dsb_id = DEF_SB_IGU_ID;
11318                 bp->igu_base_sb = 0;
11319         } else {
11320                 bp->common.int_block = INT_BLOCK_IGU;
11321
11322                 /* do not allow device reset during IGU info processing */
11323                 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11324
11325                 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
11326
11327                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11328                         int tout = 5000;
11329
11330                         BNX2X_DEV_INFO("FORCING Normal Mode\n");
11331
11332                         val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
11333                         REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
11334                         REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
11335
11336                         while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11337                                 tout--;
11338                                 usleep_range(1000, 2000);
11339                         }
11340
11341                         if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11342                                 dev_err(&bp->pdev->dev,
11343                                         "FORCING Normal Mode failed!!!\n");
11344                                 bnx2x_release_hw_lock(bp,
11345                                                       HW_LOCK_RESOURCE_RESET);
11346                                 return -EPERM;
11347                         }
11348                 }
11349
11350                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11351                         BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
11352                         bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
11353                 } else
11354                         BNX2X_DEV_INFO("IGU Normal Mode\n");
11355
11356                 rc = bnx2x_get_igu_cam_info(bp);
11357                 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11358                 if (rc)
11359                         return rc;
11360         }
11361
11362         /*
11363          * set base FW non-default (fast path) status block id, this value is
11364          * used to initialize the fw_sb_id saved on the fp/queue structure to
11365          * determine the id used by the FW.
11366          */
11367         if (CHIP_IS_E1x(bp))
11368                 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
11369         else /*
11370               * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
11371               * the same queue are indicated on the same IGU SB). So we prefer
11372               * FW and IGU SBs to be the same value.
11373               */
11374                 bp->base_fw_ndsb = bp->igu_base_sb;
11375
11376         BNX2X_DEV_INFO("igu_dsb_id %d  igu_base_sb %d  igu_sb_cnt %d\n"
11377                        "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
11378                        bp->igu_sb_cnt, bp->base_fw_ndsb);
11379
11380         /*
11381          * Initialize MF configuration
11382          */
11383
11384         bp->mf_ov = 0;
11385         bp->mf_mode = 0;
11386         vn = BP_VN(bp);
11387
11388         if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
11389                 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
11390                                bp->common.shmem2_base, SHMEM2_RD(bp, size),
11391                               (u32)offsetof(struct shmem2_region, mf_cfg_addr));
11392
11393                 if (SHMEM2_HAS(bp, mf_cfg_addr))
11394                         bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
11395                 else
11396                         bp->common.mf_cfg_base = bp->common.shmem_base +
11397                                 offsetof(struct shmem_region, func_mb) +
11398                                 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
11399                 /*
11400                  * get mf configuration:
11401                  * 1. Existence of MF configuration
11402                  * 2. MAC address must be legal (check only upper bytes)
11403                  *    for  Switch-Independent mode;
11404                  *    OVLAN must be legal for Switch-Dependent mode
11405                  * 3. SF_MODE configures specific MF mode
11406                  */
11407                 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11408                         /* get mf configuration */
11409                         val = SHMEM_RD(bp,
11410                                        dev_info.shared_feature_config.config);
11411                         val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
11412
11413                         switch (val) {
11414                         case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
11415                                 val = MF_CFG_RD(bp, func_mf_config[func].
11416                                                 mac_upper);
11417                                 /* check for legal mac (upper bytes)*/
11418                                 if (val != 0xffff) {
11419                                         bp->mf_mode = MULTI_FUNCTION_SI;
11420                                         bp->mf_config[vn] = MF_CFG_RD(bp,
11421                                                    func_mf_config[func].config);
11422                                 } else
11423                                         BNX2X_DEV_INFO("illegal MAC address for SI\n");
11424                                 break;
11425                         case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
11426                                 if ((!CHIP_IS_E1x(bp)) &&
11427                                     (MF_CFG_RD(bp, func_mf_config[func].
11428                                                mac_upper) != 0xffff) &&
11429                                     (SHMEM2_HAS(bp,
11430                                                 afex_driver_support))) {
11431                                         bp->mf_mode = MULTI_FUNCTION_AFEX;
11432                                         bp->mf_config[vn] = MF_CFG_RD(bp,
11433                                                 func_mf_config[func].config);
11434                                 } else {
11435                                         BNX2X_DEV_INFO("can not configure afex mode\n");
11436                                 }
11437                                 break;
11438                         case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
11439                                 /* get OV configuration */
11440                                 val = MF_CFG_RD(bp,
11441                                         func_mf_config[FUNC_0].e1hov_tag);
11442                                 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
11443
11444                                 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11445                                         bp->mf_mode = MULTI_FUNCTION_SD;
11446                                         bp->mf_config[vn] = MF_CFG_RD(bp,
11447                                                 func_mf_config[func].config);
11448                                 } else
11449                                         BNX2X_DEV_INFO("illegal OV for SD\n");
11450                                 break;
11451                         case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
11452                                 bp->mf_config[vn] = 0;
11453                                 break;
11454                         default:
11455                                 /* Unknown configuration: reset mf_config */
11456                                 bp->mf_config[vn] = 0;
11457                                 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val);
11458                         }
11459                 }
11460
11461                 BNX2X_DEV_INFO("%s function mode\n",
11462                                IS_MF(bp) ? "multi" : "single");
11463
11464                 switch (bp->mf_mode) {
11465                 case MULTI_FUNCTION_SD:
11466                         val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
11467                               FUNC_MF_CFG_E1HOV_TAG_MASK;
11468                         if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11469                                 bp->mf_ov = val;
11470                                 bp->path_has_ovlan = true;
11471
11472                                 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
11473                                                func, bp->mf_ov, bp->mf_ov);
11474                         } else {
11475                                 dev_err(&bp->pdev->dev,
11476                                         "No valid MF OV for func %d, aborting\n",
11477                                         func);
11478                                 return -EPERM;
11479                         }
11480                         break;
11481                 case MULTI_FUNCTION_AFEX:
11482                         BNX2X_DEV_INFO("func %d is in MF afex mode\n", func);
11483                         break;
11484                 case MULTI_FUNCTION_SI:
11485                         BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
11486                                        func);
11487                         break;
11488                 default:
11489                         if (vn) {
11490                                 dev_err(&bp->pdev->dev,
11491                                         "VN %d is in a single function mode, aborting\n",
11492                                         vn);
11493                                 return -EPERM;
11494                         }
11495                         break;
11496                 }
11497
11498                 /* check if other port on the path needs ovlan:
11499                  * Since MF configuration is shared between ports
11500                  * Possible mixed modes are only
11501                  * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
11502                  */
11503                 if (CHIP_MODE_IS_4_PORT(bp) &&
11504                     !bp->path_has_ovlan &&
11505                     !IS_MF(bp) &&
11506                     bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11507                         u8 other_port = !BP_PORT(bp);
11508                         u8 other_func = BP_PATH(bp) + 2*other_port;
11509                         val = MF_CFG_RD(bp,
11510                                         func_mf_config[other_func].e1hov_tag);
11511                         if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
11512                                 bp->path_has_ovlan = true;
11513                 }
11514         }
11515
11516         /* adjust igu_sb_cnt to MF for E1x */
11517         if (CHIP_IS_E1x(bp) && IS_MF(bp))
11518                 bp->igu_sb_cnt /= E1HVN_MAX;
11519
11520         /* port info */
11521         bnx2x_get_port_hwinfo(bp);
11522
11523         /* Get MAC addresses */
11524         bnx2x_get_mac_hwinfo(bp);
11525
11526         bnx2x_get_cnic_info(bp);
11527
11528         return rc;
11529 }
11530
11531 static void bnx2x_read_fwinfo(struct bnx2x *bp)
11532 {
11533         int cnt, i, block_end, rodi;
11534         char vpd_start[BNX2X_VPD_LEN+1];
11535         char str_id_reg[VENDOR_ID_LEN+1];
11536         char str_id_cap[VENDOR_ID_LEN+1];
11537         char *vpd_data;
11538         char *vpd_extended_data = NULL;
11539         u8 len;
11540
11541         cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start);
11542         memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
11543
11544         if (cnt < BNX2X_VPD_LEN)
11545                 goto out_not_found;
11546
11547         /* VPD RO tag should be first tag after identifier string, hence
11548          * we should be able to find it in first BNX2X_VPD_LEN chars
11549          */
11550         i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN,
11551                              PCI_VPD_LRDT_RO_DATA);
11552         if (i < 0)
11553                 goto out_not_found;
11554
11555         block_end = i + PCI_VPD_LRDT_TAG_SIZE +
11556                     pci_vpd_lrdt_size(&vpd_start[i]);
11557
11558         i += PCI_VPD_LRDT_TAG_SIZE;
11559
11560         if (block_end > BNX2X_VPD_LEN) {
11561                 vpd_extended_data = kmalloc(block_end, GFP_KERNEL);
11562                 if (vpd_extended_data  == NULL)
11563                         goto out_not_found;
11564
11565                 /* read rest of vpd image into vpd_extended_data */
11566                 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN);
11567                 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN,
11568                                    block_end - BNX2X_VPD_LEN,
11569                                    vpd_extended_data + BNX2X_VPD_LEN);
11570                 if (cnt < (block_end - BNX2X_VPD_LEN))
11571                         goto out_not_found;
11572                 vpd_data = vpd_extended_data;
11573         } else
11574                 vpd_data = vpd_start;
11575
11576         /* now vpd_data holds full vpd content in both cases */
11577
11578         rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11579                                    PCI_VPD_RO_KEYWORD_MFR_ID);
11580         if (rodi < 0)
11581                 goto out_not_found;
11582
11583         len = pci_vpd_info_field_size(&vpd_data[rodi]);
11584
11585         if (len != VENDOR_ID_LEN)
11586                 goto out_not_found;
11587
11588         rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11589
11590         /* vendor specific info */
11591         snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
11592         snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
11593         if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
11594             !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
11595
11596                 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11597                                                 PCI_VPD_RO_KEYWORD_VENDOR0);
11598                 if (rodi >= 0) {
11599                         len = pci_vpd_info_field_size(&vpd_data[rodi]);
11600
11601                         rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11602
11603                         if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
11604                                 memcpy(bp->fw_ver, &vpd_data[rodi], len);
11605                                 bp->fw_ver[len] = ' ';
11606                         }
11607                 }
11608                 kfree(vpd_extended_data);
11609                 return;
11610         }
11611 out_not_found:
11612         kfree(vpd_extended_data);
11613         return;
11614 }
11615
11616 static void bnx2x_set_modes_bitmap(struct bnx2x *bp)
11617 {
11618         u32 flags = 0;
11619
11620         if (CHIP_REV_IS_FPGA(bp))
11621                 SET_FLAGS(flags, MODE_FPGA);
11622         else if (CHIP_REV_IS_EMUL(bp))
11623                 SET_FLAGS(flags, MODE_EMUL);
11624         else
11625                 SET_FLAGS(flags, MODE_ASIC);
11626
11627         if (CHIP_MODE_IS_4_PORT(bp))
11628                 SET_FLAGS(flags, MODE_PORT4);
11629         else
11630                 SET_FLAGS(flags, MODE_PORT2);
11631
11632         if (CHIP_IS_E2(bp))
11633                 SET_FLAGS(flags, MODE_E2);
11634         else if (CHIP_IS_E3(bp)) {
11635                 SET_FLAGS(flags, MODE_E3);
11636                 if (CHIP_REV(bp) == CHIP_REV_Ax)
11637                         SET_FLAGS(flags, MODE_E3_A0);
11638                 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
11639                         SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
11640         }
11641
11642         if (IS_MF(bp)) {
11643                 SET_FLAGS(flags, MODE_MF);
11644                 switch (bp->mf_mode) {
11645                 case MULTI_FUNCTION_SD:
11646                         SET_FLAGS(flags, MODE_MF_SD);
11647                         break;
11648                 case MULTI_FUNCTION_SI:
11649                         SET_FLAGS(flags, MODE_MF_SI);
11650                         break;
11651                 case MULTI_FUNCTION_AFEX:
11652                         SET_FLAGS(flags, MODE_MF_AFEX);
11653                         break;
11654                 }
11655         } else
11656                 SET_FLAGS(flags, MODE_SF);
11657
11658 #if defined(__LITTLE_ENDIAN)
11659         SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
11660 #else /*(__BIG_ENDIAN)*/
11661         SET_FLAGS(flags, MODE_BIG_ENDIAN);
11662 #endif
11663         INIT_MODE_FLAGS(bp) = flags;
11664 }
11665
11666 static int bnx2x_init_bp(struct bnx2x *bp)
11667 {
11668         int func;
11669         int rc;
11670
11671         mutex_init(&bp->port.phy_mutex);
11672         mutex_init(&bp->fw_mb_mutex);
11673         spin_lock_init(&bp->stats_lock);
11674         sema_init(&bp->stats_sema, 1);
11675
11676         INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
11677         INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
11678         INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
11679         if (IS_PF(bp)) {
11680                 rc = bnx2x_get_hwinfo(bp);
11681                 if (rc)
11682                         return rc;
11683         } else {
11684                 eth_zero_addr(bp->dev->dev_addr);
11685         }
11686
11687         bnx2x_set_modes_bitmap(bp);
11688
11689         rc = bnx2x_alloc_mem_bp(bp);
11690         if (rc)
11691                 return rc;
11692
11693         bnx2x_read_fwinfo(bp);
11694
11695         func = BP_FUNC(bp);
11696
11697         /* need to reset chip if undi was active */
11698         if (IS_PF(bp) && !BP_NOMCP(bp)) {
11699                 /* init fw_seq */
11700                 bp->fw_seq =
11701                         SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
11702                                                         DRV_MSG_SEQ_NUMBER_MASK;
11703                 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
11704
11705                 rc = bnx2x_prev_unload(bp);
11706                 if (rc) {
11707                         bnx2x_free_mem_bp(bp);
11708                         return rc;
11709                 }
11710         }
11711
11712         if (CHIP_REV_IS_FPGA(bp))
11713                 dev_err(&bp->pdev->dev, "FPGA detected\n");
11714
11715         if (BP_NOMCP(bp) && (func == 0))
11716                 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
11717
11718         bp->disable_tpa = disable_tpa;
11719         bp->disable_tpa |= IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp);
11720
11721         /* Set TPA flags */
11722         if (bp->disable_tpa) {
11723                 bp->flags &= ~(TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
11724                 bp->dev->features &= ~NETIF_F_LRO;
11725         } else {
11726                 bp->flags |= (TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
11727                 bp->dev->features |= NETIF_F_LRO;
11728         }
11729
11730         if (CHIP_IS_E1(bp))
11731                 bp->dropless_fc = 0;
11732         else
11733                 bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp);
11734
11735         bp->mrrs = mrrs;
11736
11737         bp->tx_ring_size = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
11738         if (IS_VF(bp))
11739                 bp->rx_ring_size = MAX_RX_AVAIL;
11740
11741         /* make sure that the numbers are in the right granularity */
11742         bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
11743         bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
11744
11745         bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ;
11746
11747         init_timer(&bp->timer);
11748         bp->timer.expires = jiffies + bp->current_interval;
11749         bp->timer.data = (unsigned long) bp;
11750         bp->timer.function = bnx2x_timer;
11751
11752         if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) &&
11753             SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) &&
11754             SHMEM2_RD(bp, dcbx_lldp_params_offset) &&
11755             SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset)) {
11756                 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
11757                 bnx2x_dcbx_init_params(bp);
11758         } else {
11759                 bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF);
11760         }
11761
11762         if (CHIP_IS_E1x(bp))
11763                 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
11764         else
11765                 bp->cnic_base_cl_id = FP_SB_MAX_E2;
11766
11767         /* multiple tx priority */
11768         if (IS_VF(bp))
11769                 bp->max_cos = 1;
11770         else if (CHIP_IS_E1x(bp))
11771                 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
11772         else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
11773                 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
11774         else if (CHIP_IS_E3B0(bp))
11775                 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
11776         else
11777                 BNX2X_ERR("unknown chip %x revision %x\n",
11778                           CHIP_NUM(bp), CHIP_REV(bp));
11779         BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos);
11780
11781         /* We need at least one default status block for slow-path events,
11782          * second status block for the L2 queue, and a third status block for
11783          * CNIC if supported.
11784          */
11785         if (IS_VF(bp))
11786                 bp->min_msix_vec_cnt = 1;
11787         else if (CNIC_SUPPORT(bp))
11788                 bp->min_msix_vec_cnt = 3;
11789         else /* PF w/o cnic */
11790                 bp->min_msix_vec_cnt = 2;
11791         BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt);
11792
11793         bp->dump_preset_idx = 1;
11794
11795         return rc;
11796 }
11797
11798 /****************************************************************************
11799 * General service functions
11800 ****************************************************************************/
11801
11802 /*
11803  * net_device service functions
11804  */
11805
11806 /* called with rtnl_lock */
11807 static int bnx2x_open(struct net_device *dev)
11808 {
11809         struct bnx2x *bp = netdev_priv(dev);
11810         int rc;
11811
11812         bp->stats_init = true;
11813
11814         netif_carrier_off(dev);
11815
11816         bnx2x_set_power_state(bp, PCI_D0);
11817
11818         /* If parity had happen during the unload, then attentions
11819          * and/or RECOVERY_IN_PROGRES may still be set. In this case we
11820          * want the first function loaded on the current engine to
11821          * complete the recovery.
11822          * Parity recovery is only relevant for PF driver.
11823          */
11824         if (IS_PF(bp)) {
11825                 int other_engine = BP_PATH(bp) ? 0 : 1;
11826                 bool other_load_status, load_status;
11827                 bool global = false;
11828
11829                 other_load_status = bnx2x_get_load_status(bp, other_engine);
11830                 load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
11831                 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
11832                     bnx2x_chk_parity_attn(bp, &global, true)) {
11833                         do {
11834                                 /* If there are attentions and they are in a
11835                                  * global blocks, set the GLOBAL_RESET bit
11836                                  * regardless whether it will be this function
11837                                  * that will complete the recovery or not.
11838                                  */
11839                                 if (global)
11840                                         bnx2x_set_reset_global(bp);
11841
11842                                 /* Only the first function on the current
11843                                  * engine should try to recover in open. In case
11844                                  * of attentions in global blocks only the first
11845                                  * in the chip should try to recover.
11846                                  */
11847                                 if ((!load_status &&
11848                                      (!global || !other_load_status)) &&
11849                                       bnx2x_trylock_leader_lock(bp) &&
11850                                       !bnx2x_leader_reset(bp)) {
11851                                         netdev_info(bp->dev,
11852                                                     "Recovered in open\n");
11853                                         break;
11854                                 }
11855
11856                                 /* recovery has failed... */
11857                                 bnx2x_set_power_state(bp, PCI_D3hot);
11858                                 bp->recovery_state = BNX2X_RECOVERY_FAILED;
11859
11860                                 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
11861                                           "If you still see this message after a few retries then power cycle is required.\n");
11862
11863                                 return -EAGAIN;
11864                         } while (0);
11865                 }
11866         }
11867
11868         bp->recovery_state = BNX2X_RECOVERY_DONE;
11869         rc = bnx2x_nic_load(bp, LOAD_OPEN);
11870         if (rc)
11871                 return rc;
11872         return 0;
11873 }
11874
11875 /* called with rtnl_lock */
11876 static int bnx2x_close(struct net_device *dev)
11877 {
11878         struct bnx2x *bp = netdev_priv(dev);
11879
11880         /* Unload the driver, release IRQs */
11881         bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
11882
11883         return 0;
11884 }
11885
11886 static int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
11887                                       struct bnx2x_mcast_ramrod_params *p)
11888 {
11889         int mc_count = netdev_mc_count(bp->dev);
11890         struct bnx2x_mcast_list_elem *mc_mac =
11891                 kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC);
11892         struct netdev_hw_addr *ha;
11893
11894         if (!mc_mac)
11895                 return -ENOMEM;
11896
11897         INIT_LIST_HEAD(&p->mcast_list);
11898
11899         netdev_for_each_mc_addr(ha, bp->dev) {
11900                 mc_mac->mac = bnx2x_mc_addr(ha);
11901                 list_add_tail(&mc_mac->link, &p->mcast_list);
11902                 mc_mac++;
11903         }
11904
11905         p->mcast_list_len = mc_count;
11906
11907         return 0;
11908 }
11909
11910 static void bnx2x_free_mcast_macs_list(
11911         struct bnx2x_mcast_ramrod_params *p)
11912 {
11913         struct bnx2x_mcast_list_elem *mc_mac =
11914                 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
11915                                  link);
11916
11917         WARN_ON(!mc_mac);
11918         kfree(mc_mac);
11919 }
11920
11921 /**
11922  * bnx2x_set_uc_list - configure a new unicast MACs list.
11923  *
11924  * @bp: driver handle
11925  *
11926  * We will use zero (0) as a MAC type for these MACs.
11927  */
11928 static int bnx2x_set_uc_list(struct bnx2x *bp)
11929 {
11930         int rc;
11931         struct net_device *dev = bp->dev;
11932         struct netdev_hw_addr *ha;
11933         struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
11934         unsigned long ramrod_flags = 0;
11935
11936         /* First schedule a cleanup up of old configuration */
11937         rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
11938         if (rc < 0) {
11939                 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
11940                 return rc;
11941         }
11942
11943         netdev_for_each_uc_addr(ha, dev) {
11944                 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
11945                                        BNX2X_UC_LIST_MAC, &ramrod_flags);
11946                 if (rc == -EEXIST) {
11947                         DP(BNX2X_MSG_SP,
11948                            "Failed to schedule ADD operations: %d\n", rc);
11949                         /* do not treat adding same MAC as error */
11950                         rc = 0;
11951
11952                 } else if (rc < 0) {
11953
11954                         BNX2X_ERR("Failed to schedule ADD operations: %d\n",
11955                                   rc);
11956                         return rc;
11957                 }
11958         }
11959
11960         /* Execute the pending commands */
11961         __set_bit(RAMROD_CONT, &ramrod_flags);
11962         return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
11963                                  BNX2X_UC_LIST_MAC, &ramrod_flags);
11964 }
11965
11966 static int bnx2x_set_mc_list(struct bnx2x *bp)
11967 {
11968         struct net_device *dev = bp->dev;
11969         struct bnx2x_mcast_ramrod_params rparam = {NULL};
11970         int rc = 0;
11971
11972         rparam.mcast_obj = &bp->mcast_obj;
11973
11974         /* first, clear all configured multicast MACs */
11975         rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
11976         if (rc < 0) {
11977                 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc);
11978                 return rc;
11979         }
11980
11981         /* then, configure a new MACs list */
11982         if (netdev_mc_count(dev)) {
11983                 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
11984                 if (rc) {
11985                         BNX2X_ERR("Failed to create multicast MACs list: %d\n",
11986                                   rc);
11987                         return rc;
11988                 }
11989
11990                 /* Now add the new MACs */
11991                 rc = bnx2x_config_mcast(bp, &rparam,
11992                                         BNX2X_MCAST_CMD_ADD);
11993                 if (rc < 0)
11994                         BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
11995                                   rc);
11996
11997                 bnx2x_free_mcast_macs_list(&rparam);
11998         }
11999
12000         return rc;
12001 }
12002
12003 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
12004 void bnx2x_set_rx_mode(struct net_device *dev)
12005 {
12006         struct bnx2x *bp = netdev_priv(dev);
12007
12008         if (bp->state != BNX2X_STATE_OPEN) {
12009                 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
12010                 return;
12011         } else {
12012                 /* Schedule an SP task to handle rest of change */
12013                 DP(NETIF_MSG_IFUP, "Scheduling an Rx mode change\n");
12014                 smp_mb__before_clear_bit();
12015                 set_bit(BNX2X_SP_RTNL_RX_MODE, &bp->sp_rtnl_state);
12016                 smp_mb__after_clear_bit();
12017                 schedule_delayed_work(&bp->sp_rtnl_task, 0);
12018         }
12019 }
12020
12021 void bnx2x_set_rx_mode_inner(struct bnx2x *bp)
12022 {
12023         u32 rx_mode = BNX2X_RX_MODE_NORMAL;
12024
12025         DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
12026
12027         netif_addr_lock_bh(bp->dev);
12028
12029         if (bp->dev->flags & IFF_PROMISC) {
12030                 rx_mode = BNX2X_RX_MODE_PROMISC;
12031         } else if ((bp->dev->flags & IFF_ALLMULTI) ||
12032                    ((netdev_mc_count(bp->dev) > BNX2X_MAX_MULTICAST) &&
12033                     CHIP_IS_E1(bp))) {
12034                 rx_mode = BNX2X_RX_MODE_ALLMULTI;
12035         } else {
12036                 if (IS_PF(bp)) {
12037                         /* some multicasts */
12038                         if (bnx2x_set_mc_list(bp) < 0)
12039                                 rx_mode = BNX2X_RX_MODE_ALLMULTI;
12040
12041                         /* release bh lock, as bnx2x_set_uc_list might sleep */
12042                         netif_addr_unlock_bh(bp->dev);
12043                         if (bnx2x_set_uc_list(bp) < 0)
12044                                 rx_mode = BNX2X_RX_MODE_PROMISC;
12045                         netif_addr_lock_bh(bp->dev);
12046                 } else {
12047                         /* configuring mcast to a vf involves sleeping (when we
12048                          * wait for the pf's response).
12049                          */
12050                         smp_mb__before_clear_bit();
12051                         set_bit(BNX2X_SP_RTNL_VFPF_MCAST,
12052                                 &bp->sp_rtnl_state);
12053                         smp_mb__after_clear_bit();
12054                         schedule_delayed_work(&bp->sp_rtnl_task, 0);
12055                 }
12056         }
12057
12058         bp->rx_mode = rx_mode;
12059         /* handle ISCSI SD mode */
12060         if (IS_MF_ISCSI_SD(bp))
12061                 bp->rx_mode = BNX2X_RX_MODE_NONE;
12062
12063         /* Schedule the rx_mode command */
12064         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
12065                 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
12066                 netif_addr_unlock_bh(bp->dev);
12067                 return;
12068         }
12069
12070         if (IS_PF(bp)) {
12071                 bnx2x_set_storm_rx_mode(bp);
12072                 netif_addr_unlock_bh(bp->dev);
12073         } else {
12074                 /* VF will need to request the PF to make this change, and so
12075                  * the VF needs to release the bottom-half lock prior to the
12076                  * request (as it will likely require sleep on the VF side)
12077                  */
12078                 netif_addr_unlock_bh(bp->dev);
12079                 bnx2x_vfpf_storm_rx_mode(bp);
12080         }
12081 }
12082
12083 /* called with rtnl_lock */
12084 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
12085                            int devad, u16 addr)
12086 {
12087         struct bnx2x *bp = netdev_priv(netdev);
12088         u16 value;
12089         int rc;
12090
12091         DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
12092            prtad, devad, addr);
12093
12094         /* The HW expects different devad if CL22 is used */
12095         devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
12096
12097         bnx2x_acquire_phy_lock(bp);
12098         rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
12099         bnx2x_release_phy_lock(bp);
12100         DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
12101
12102         if (!rc)
12103                 rc = value;
12104         return rc;
12105 }
12106
12107 /* called with rtnl_lock */
12108 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
12109                             u16 addr, u16 value)
12110 {
12111         struct bnx2x *bp = netdev_priv(netdev);
12112         int rc;
12113
12114         DP(NETIF_MSG_LINK,
12115            "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
12116            prtad, devad, addr, value);
12117
12118         /* The HW expects different devad if CL22 is used */
12119         devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
12120
12121         bnx2x_acquire_phy_lock(bp);
12122         rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
12123         bnx2x_release_phy_lock(bp);
12124         return rc;
12125 }
12126
12127 /* called with rtnl_lock */
12128 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
12129 {
12130         struct bnx2x *bp = netdev_priv(dev);
12131         struct mii_ioctl_data *mdio = if_mii(ifr);
12132
12133         DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
12134            mdio->phy_id, mdio->reg_num, mdio->val_in);
12135
12136         if (!netif_running(dev))
12137                 return -EAGAIN;
12138
12139         return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
12140 }
12141
12142 #ifdef CONFIG_NET_POLL_CONTROLLER
12143 static void poll_bnx2x(struct net_device *dev)
12144 {
12145         struct bnx2x *bp = netdev_priv(dev);
12146         int i;
12147
12148         for_each_eth_queue(bp, i) {
12149                 struct bnx2x_fastpath *fp = &bp->fp[i];
12150                 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
12151         }
12152 }
12153 #endif
12154
12155 static int bnx2x_validate_addr(struct net_device *dev)
12156 {
12157         struct bnx2x *bp = netdev_priv(dev);
12158
12159         /* query the bulletin board for mac address configured by the PF */
12160         if (IS_VF(bp))
12161                 bnx2x_sample_bulletin(bp);
12162
12163         if (!bnx2x_is_valid_ether_addr(bp, dev->dev_addr)) {
12164                 BNX2X_ERR("Non-valid Ethernet address\n");
12165                 return -EADDRNOTAVAIL;
12166         }
12167         return 0;
12168 }
12169
12170 static int bnx2x_get_phys_port_id(struct net_device *netdev,
12171                                   struct netdev_phys_port_id *ppid)
12172 {
12173         struct bnx2x *bp = netdev_priv(netdev);
12174
12175         if (!(bp->flags & HAS_PHYS_PORT_ID))
12176                 return -EOPNOTSUPP;
12177
12178         ppid->id_len = sizeof(bp->phys_port_id);
12179         memcpy(ppid->id, bp->phys_port_id, ppid->id_len);
12180
12181         return 0;
12182 }
12183
12184 static const struct net_device_ops bnx2x_netdev_ops = {
12185         .ndo_open               = bnx2x_open,
12186         .ndo_stop               = bnx2x_close,
12187         .ndo_start_xmit         = bnx2x_start_xmit,
12188         .ndo_select_queue       = bnx2x_select_queue,
12189         .ndo_set_rx_mode        = bnx2x_set_rx_mode,
12190         .ndo_set_mac_address    = bnx2x_change_mac_addr,
12191         .ndo_validate_addr      = bnx2x_validate_addr,
12192         .ndo_do_ioctl           = bnx2x_ioctl,
12193         .ndo_change_mtu         = bnx2x_change_mtu,
12194         .ndo_fix_features       = bnx2x_fix_features,
12195         .ndo_set_features       = bnx2x_set_features,
12196         .ndo_tx_timeout         = bnx2x_tx_timeout,
12197 #ifdef CONFIG_NET_POLL_CONTROLLER
12198         .ndo_poll_controller    = poll_bnx2x,
12199 #endif
12200         .ndo_setup_tc           = bnx2x_setup_tc,
12201 #ifdef CONFIG_BNX2X_SRIOV
12202         .ndo_set_vf_mac         = bnx2x_set_vf_mac,
12203         .ndo_set_vf_vlan        = bnx2x_set_vf_vlan,
12204         .ndo_get_vf_config      = bnx2x_get_vf_config,
12205 #endif
12206 #ifdef NETDEV_FCOE_WWNN
12207         .ndo_fcoe_get_wwn       = bnx2x_fcoe_get_wwn,
12208 #endif
12209
12210 #ifdef CONFIG_NET_RX_BUSY_POLL
12211         .ndo_busy_poll          = bnx2x_low_latency_recv,
12212 #endif
12213         .ndo_get_phys_port_id   = bnx2x_get_phys_port_id,
12214 };
12215
12216 static int bnx2x_set_coherency_mask(struct bnx2x *bp)
12217 {
12218         struct device *dev = &bp->pdev->dev;
12219
12220         if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)) != 0 &&
12221             dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)) != 0) {
12222                 dev_err(dev, "System does not support DMA, aborting\n");
12223                 return -EIO;
12224         }
12225
12226         return 0;
12227 }
12228
12229 static void bnx2x_disable_pcie_error_reporting(struct bnx2x *bp)
12230 {
12231         if (bp->flags & AER_ENABLED) {
12232                 pci_disable_pcie_error_reporting(bp->pdev);
12233                 bp->flags &= ~AER_ENABLED;
12234         }
12235 }
12236
12237 static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev,
12238                           struct net_device *dev, unsigned long board_type)
12239 {
12240         int rc;
12241         u32 pci_cfg_dword;
12242         bool chip_is_e1x = (board_type == BCM57710 ||
12243                             board_type == BCM57711 ||
12244                             board_type == BCM57711E);
12245
12246         SET_NETDEV_DEV(dev, &pdev->dev);
12247
12248         bp->dev = dev;
12249         bp->pdev = pdev;
12250
12251         rc = pci_enable_device(pdev);
12252         if (rc) {
12253                 dev_err(&bp->pdev->dev,
12254                         "Cannot enable PCI device, aborting\n");
12255                 goto err_out;
12256         }
12257
12258         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
12259                 dev_err(&bp->pdev->dev,
12260                         "Cannot find PCI device base address, aborting\n");
12261                 rc = -ENODEV;
12262                 goto err_out_disable;
12263         }
12264
12265         if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
12266                 dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n");
12267                 rc = -ENODEV;
12268                 goto err_out_disable;
12269         }
12270
12271         pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword);
12272         if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) ==
12273             PCICFG_REVESION_ID_ERROR_VAL) {
12274                 pr_err("PCI device error, probably due to fan failure, aborting\n");
12275                 rc = -ENODEV;
12276                 goto err_out_disable;
12277         }
12278
12279         if (atomic_read(&pdev->enable_cnt) == 1) {
12280                 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
12281                 if (rc) {
12282                         dev_err(&bp->pdev->dev,
12283                                 "Cannot obtain PCI resources, aborting\n");
12284                         goto err_out_disable;
12285                 }
12286
12287                 pci_set_master(pdev);
12288                 pci_save_state(pdev);
12289         }
12290
12291         if (IS_PF(bp)) {
12292                 if (!pdev->pm_cap) {
12293                         dev_err(&bp->pdev->dev,
12294                                 "Cannot find power management capability, aborting\n");
12295                         rc = -EIO;
12296                         goto err_out_release;
12297                 }
12298         }
12299
12300         if (!pci_is_pcie(pdev)) {
12301                 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
12302                 rc = -EIO;
12303                 goto err_out_release;
12304         }
12305
12306         rc = bnx2x_set_coherency_mask(bp);
12307         if (rc)
12308                 goto err_out_release;
12309
12310         dev->mem_start = pci_resource_start(pdev, 0);
12311         dev->base_addr = dev->mem_start;
12312         dev->mem_end = pci_resource_end(pdev, 0);
12313
12314         dev->irq = pdev->irq;
12315
12316         bp->regview = pci_ioremap_bar(pdev, 0);
12317         if (!bp->regview) {
12318                 dev_err(&bp->pdev->dev,
12319                         "Cannot map register space, aborting\n");
12320                 rc = -ENOMEM;
12321                 goto err_out_release;
12322         }
12323
12324         /* In E1/E1H use pci device function given by kernel.
12325          * In E2/E3 read physical function from ME register since these chips
12326          * support Physical Device Assignment where kernel BDF maybe arbitrary
12327          * (depending on hypervisor).
12328          */
12329         if (chip_is_e1x) {
12330                 bp->pf_num = PCI_FUNC(pdev->devfn);
12331         } else {
12332                 /* chip is E2/3*/
12333                 pci_read_config_dword(bp->pdev,
12334                                       PCICFG_ME_REGISTER, &pci_cfg_dword);
12335                 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
12336                                   ME_REG_ABS_PF_NUM_SHIFT);
12337         }
12338         BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
12339
12340         /* clean indirect addresses */
12341         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
12342                                PCICFG_VENDOR_ID_OFFSET);
12343
12344         /* AER (Advanced Error reporting) configuration */
12345         rc = pci_enable_pcie_error_reporting(pdev);
12346         if (!rc)
12347                 bp->flags |= AER_ENABLED;
12348         else
12349                 BNX2X_DEV_INFO("Failed To configure PCIe AER [%d]\n", rc);
12350
12351         /*
12352          * Clean the following indirect addresses for all functions since it
12353          * is not used by the driver.
12354          */
12355         if (IS_PF(bp)) {
12356                 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
12357                 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
12358                 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
12359                 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
12360
12361                 if (chip_is_e1x) {
12362                         REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
12363                         REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
12364                         REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
12365                         REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
12366                 }
12367
12368                 /* Enable internal target-read (in case we are probed after PF
12369                  * FLR). Must be done prior to any BAR read access. Only for
12370                  * 57712 and up
12371                  */
12372                 if (!chip_is_e1x)
12373                         REG_WR(bp,
12374                                PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
12375         }
12376
12377         dev->watchdog_timeo = TX_TIMEOUT;
12378
12379         dev->netdev_ops = &bnx2x_netdev_ops;
12380         bnx2x_set_ethtool_ops(bp, dev);
12381
12382         dev->priv_flags |= IFF_UNICAST_FLT;
12383
12384         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
12385                 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
12386                 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO |
12387                 NETIF_F_RXHASH | NETIF_F_HW_VLAN_CTAG_TX;
12388         if (!CHIP_IS_E1x(bp)) {
12389                 dev->hw_features |= NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL |
12390                                     NETIF_F_GSO_IPIP | NETIF_F_GSO_SIT;
12391                 dev->hw_enc_features =
12392                         NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
12393                         NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
12394                         NETIF_F_GSO_IPIP |
12395                         NETIF_F_GSO_SIT |
12396                         NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL;
12397         }
12398
12399         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
12400                 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
12401
12402         dev->features |= dev->hw_features | NETIF_F_HW_VLAN_CTAG_RX;
12403         dev->features |= NETIF_F_HIGHDMA;
12404
12405         /* Add Loopback capability to the device */
12406         dev->hw_features |= NETIF_F_LOOPBACK;
12407
12408 #ifdef BCM_DCBNL
12409         dev->dcbnl_ops = &bnx2x_dcbnl_ops;
12410 #endif
12411
12412         /* get_port_hwinfo() will set prtad and mmds properly */
12413         bp->mdio.prtad = MDIO_PRTAD_NONE;
12414         bp->mdio.mmds = 0;
12415         bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
12416         bp->mdio.dev = dev;
12417         bp->mdio.mdio_read = bnx2x_mdio_read;
12418         bp->mdio.mdio_write = bnx2x_mdio_write;
12419
12420         return 0;
12421
12422 err_out_release:
12423         if (atomic_read(&pdev->enable_cnt) == 1)
12424                 pci_release_regions(pdev);
12425
12426 err_out_disable:
12427         pci_disable_device(pdev);
12428
12429 err_out:
12430         return rc;
12431 }
12432
12433 static int bnx2x_check_firmware(struct bnx2x *bp)
12434 {
12435         const struct firmware *firmware = bp->firmware;
12436         struct bnx2x_fw_file_hdr *fw_hdr;
12437         struct bnx2x_fw_file_section *sections;
12438         u32 offset, len, num_ops;
12439         __be16 *ops_offsets;
12440         int i;
12441         const u8 *fw_ver;
12442
12443         if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) {
12444                 BNX2X_ERR("Wrong FW size\n");
12445                 return -EINVAL;
12446         }
12447
12448         fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
12449         sections = (struct bnx2x_fw_file_section *)fw_hdr;
12450
12451         /* Make sure none of the offsets and sizes make us read beyond
12452          * the end of the firmware data */
12453         for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
12454                 offset = be32_to_cpu(sections[i].offset);
12455                 len = be32_to_cpu(sections[i].len);
12456                 if (offset + len > firmware->size) {
12457                         BNX2X_ERR("Section %d length is out of bounds\n", i);
12458                         return -EINVAL;
12459                 }
12460         }
12461
12462         /* Likewise for the init_ops offsets */
12463         offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
12464         ops_offsets = (__force __be16 *)(firmware->data + offset);
12465         num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
12466
12467         for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
12468                 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
12469                         BNX2X_ERR("Section offset %d is out of bounds\n", i);
12470                         return -EINVAL;
12471                 }
12472         }
12473
12474         /* Check FW version */
12475         offset = be32_to_cpu(fw_hdr->fw_version.offset);
12476         fw_ver = firmware->data + offset;
12477         if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
12478             (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
12479             (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
12480             (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
12481                 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
12482                        fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3],
12483                        BCM_5710_FW_MAJOR_VERSION,
12484                        BCM_5710_FW_MINOR_VERSION,
12485                        BCM_5710_FW_REVISION_VERSION,
12486                        BCM_5710_FW_ENGINEERING_VERSION);
12487                 return -EINVAL;
12488         }
12489
12490         return 0;
12491 }
12492
12493 static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
12494 {
12495         const __be32 *source = (const __be32 *)_source;
12496         u32 *target = (u32 *)_target;
12497         u32 i;
12498
12499         for (i = 0; i < n/4; i++)
12500                 target[i] = be32_to_cpu(source[i]);
12501 }
12502
12503 /*
12504    Ops array is stored in the following format:
12505    {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
12506  */
12507 static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
12508 {
12509         const __be32 *source = (const __be32 *)_source;
12510         struct raw_op *target = (struct raw_op *)_target;
12511         u32 i, j, tmp;
12512
12513         for (i = 0, j = 0; i < n/8; i++, j += 2) {
12514                 tmp = be32_to_cpu(source[j]);
12515                 target[i].op = (tmp >> 24) & 0xff;
12516                 target[i].offset = tmp & 0xffffff;
12517                 target[i].raw_data = be32_to_cpu(source[j + 1]);
12518         }
12519 }
12520
12521 /* IRO array is stored in the following format:
12522  * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
12523  */
12524 static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
12525 {
12526         const __be32 *source = (const __be32 *)_source;
12527         struct iro *target = (struct iro *)_target;
12528         u32 i, j, tmp;
12529
12530         for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
12531                 target[i].base = be32_to_cpu(source[j]);
12532                 j++;
12533                 tmp = be32_to_cpu(source[j]);
12534                 target[i].m1 = (tmp >> 16) & 0xffff;
12535                 target[i].m2 = tmp & 0xffff;
12536                 j++;
12537                 tmp = be32_to_cpu(source[j]);
12538                 target[i].m3 = (tmp >> 16) & 0xffff;
12539                 target[i].size = tmp & 0xffff;
12540                 j++;
12541         }
12542 }
12543
12544 static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
12545 {
12546         const __be16 *source = (const __be16 *)_source;
12547         u16 *target = (u16 *)_target;
12548         u32 i;
12549
12550         for (i = 0; i < n/2; i++)
12551                 target[i] = be16_to_cpu(source[i]);
12552 }
12553
12554 #define BNX2X_ALLOC_AND_SET(arr, lbl, func)                             \
12555 do {                                                                    \
12556         u32 len = be32_to_cpu(fw_hdr->arr.len);                         \
12557         bp->arr = kmalloc(len, GFP_KERNEL);                             \
12558         if (!bp->arr)                                                   \
12559                 goto lbl;                                               \
12560         func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset),      \
12561              (u8 *)bp->arr, len);                                       \
12562 } while (0)
12563
12564 static int bnx2x_init_firmware(struct bnx2x *bp)
12565 {
12566         const char *fw_file_name;
12567         struct bnx2x_fw_file_hdr *fw_hdr;
12568         int rc;
12569
12570         if (bp->firmware)
12571                 return 0;
12572
12573         if (CHIP_IS_E1(bp))
12574                 fw_file_name = FW_FILE_NAME_E1;
12575         else if (CHIP_IS_E1H(bp))
12576                 fw_file_name = FW_FILE_NAME_E1H;
12577         else if (!CHIP_IS_E1x(bp))
12578                 fw_file_name = FW_FILE_NAME_E2;
12579         else {
12580                 BNX2X_ERR("Unsupported chip revision\n");
12581                 return -EINVAL;
12582         }
12583         BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
12584
12585         rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
12586         if (rc) {
12587                 BNX2X_ERR("Can't load firmware file %s\n",
12588                           fw_file_name);
12589                 goto request_firmware_exit;
12590         }
12591
12592         rc = bnx2x_check_firmware(bp);
12593         if (rc) {
12594                 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
12595                 goto request_firmware_exit;
12596         }
12597
12598         fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
12599
12600         /* Initialize the pointers to the init arrays */
12601         /* Blob */
12602         BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
12603
12604         /* Opcodes */
12605         BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
12606
12607         /* Offsets */
12608         BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
12609                             be16_to_cpu_n);
12610
12611         /* STORMs firmware */
12612         INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12613                         be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
12614         INIT_TSEM_PRAM_DATA(bp)      = bp->firmware->data +
12615                         be32_to_cpu(fw_hdr->tsem_pram_data.offset);
12616         INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12617                         be32_to_cpu(fw_hdr->usem_int_table_data.offset);
12618         INIT_USEM_PRAM_DATA(bp)      = bp->firmware->data +
12619                         be32_to_cpu(fw_hdr->usem_pram_data.offset);
12620         INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12621                         be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
12622         INIT_XSEM_PRAM_DATA(bp)      = bp->firmware->data +
12623                         be32_to_cpu(fw_hdr->xsem_pram_data.offset);
12624         INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12625                         be32_to_cpu(fw_hdr->csem_int_table_data.offset);
12626         INIT_CSEM_PRAM_DATA(bp)      = bp->firmware->data +
12627                         be32_to_cpu(fw_hdr->csem_pram_data.offset);
12628         /* IRO */
12629         BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
12630
12631         return 0;
12632
12633 iro_alloc_err:
12634         kfree(bp->init_ops_offsets);
12635 init_offsets_alloc_err:
12636         kfree(bp->init_ops);
12637 init_ops_alloc_err:
12638         kfree(bp->init_data);
12639 request_firmware_exit:
12640         release_firmware(bp->firmware);
12641         bp->firmware = NULL;
12642
12643         return rc;
12644 }
12645
12646 static void bnx2x_release_firmware(struct bnx2x *bp)
12647 {
12648         kfree(bp->init_ops_offsets);
12649         kfree(bp->init_ops);
12650         kfree(bp->init_data);
12651         release_firmware(bp->firmware);
12652         bp->firmware = NULL;
12653 }
12654
12655 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
12656         .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
12657         .init_hw_cmn      = bnx2x_init_hw_common,
12658         .init_hw_port     = bnx2x_init_hw_port,
12659         .init_hw_func     = bnx2x_init_hw_func,
12660
12661         .reset_hw_cmn     = bnx2x_reset_common,
12662         .reset_hw_port    = bnx2x_reset_port,
12663         .reset_hw_func    = bnx2x_reset_func,
12664
12665         .gunzip_init      = bnx2x_gunzip_init,
12666         .gunzip_end       = bnx2x_gunzip_end,
12667
12668         .init_fw          = bnx2x_init_firmware,
12669         .release_fw       = bnx2x_release_firmware,
12670 };
12671
12672 void bnx2x__init_func_obj(struct bnx2x *bp)
12673 {
12674         /* Prepare DMAE related driver resources */
12675         bnx2x_setup_dmae(bp);
12676
12677         bnx2x_init_func_obj(bp, &bp->func_obj,
12678                             bnx2x_sp(bp, func_rdata),
12679                             bnx2x_sp_mapping(bp, func_rdata),
12680                             bnx2x_sp(bp, func_afex_rdata),
12681                             bnx2x_sp_mapping(bp, func_afex_rdata),
12682                             &bnx2x_func_sp_drv);
12683 }
12684
12685 /* must be called after sriov-enable */
12686 static int bnx2x_set_qm_cid_count(struct bnx2x *bp)
12687 {
12688         int cid_count = BNX2X_L2_MAX_CID(bp);
12689
12690         if (IS_SRIOV(bp))
12691                 cid_count += BNX2X_VF_CIDS;
12692
12693         if (CNIC_SUPPORT(bp))
12694                 cid_count += CNIC_CID_MAX;
12695
12696         return roundup(cid_count, QM_CID_ROUND);
12697 }
12698
12699 /**
12700  * bnx2x_get_num_none_def_sbs - return the number of none default SBs
12701  *
12702  * @dev:        pci device
12703  *
12704  */
12705 static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev, int cnic_cnt)
12706 {
12707         int index;
12708         u16 control = 0;
12709
12710         /*
12711          * If MSI-X is not supported - return number of SBs needed to support
12712          * one fast path queue: one FP queue + SB for CNIC
12713          */
12714         if (!pdev->msix_cap) {
12715                 dev_info(&pdev->dev, "no msix capability found\n");
12716                 return 1 + cnic_cnt;
12717         }
12718         dev_info(&pdev->dev, "msix capability found\n");
12719
12720         /*
12721          * The value in the PCI configuration space is the index of the last
12722          * entry, namely one less than the actual size of the table, which is
12723          * exactly what we want to return from this function: number of all SBs
12724          * without the default SB.
12725          * For VFs there is no default SB, then we return (index+1).
12726          */
12727         pci_read_config_word(pdev, pdev->msix_cap + PCI_MSI_FLAGS, &control);
12728
12729         index = control & PCI_MSIX_FLAGS_QSIZE;
12730
12731         return index;
12732 }
12733
12734 static int set_max_cos_est(int chip_id)
12735 {
12736         switch (chip_id) {
12737         case BCM57710:
12738         case BCM57711:
12739         case BCM57711E:
12740                 return BNX2X_MULTI_TX_COS_E1X;
12741         case BCM57712:
12742         case BCM57712_MF:
12743                 return BNX2X_MULTI_TX_COS_E2_E3A0;
12744         case BCM57800:
12745         case BCM57800_MF:
12746         case BCM57810:
12747         case BCM57810_MF:
12748         case BCM57840_4_10:
12749         case BCM57840_2_20:
12750         case BCM57840_O:
12751         case BCM57840_MFO:
12752         case BCM57840_MF:
12753         case BCM57811:
12754         case BCM57811_MF:
12755                 return BNX2X_MULTI_TX_COS_E3B0;
12756         case BCM57712_VF:
12757         case BCM57800_VF:
12758         case BCM57810_VF:
12759         case BCM57840_VF:
12760         case BCM57811_VF:
12761                 return 1;
12762         default:
12763                 pr_err("Unknown board_type (%d), aborting\n", chip_id);
12764                 return -ENODEV;
12765         }
12766 }
12767
12768 static int set_is_vf(int chip_id)
12769 {
12770         switch (chip_id) {
12771         case BCM57712_VF:
12772         case BCM57800_VF:
12773         case BCM57810_VF:
12774         case BCM57840_VF:
12775         case BCM57811_VF:
12776                 return true;
12777         default:
12778                 return false;
12779         }
12780 }
12781
12782 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev);
12783
12784 static int bnx2x_init_one(struct pci_dev *pdev,
12785                                     const struct pci_device_id *ent)
12786 {
12787         struct net_device *dev = NULL;
12788         struct bnx2x *bp;
12789         enum pcie_link_width pcie_width;
12790         enum pci_bus_speed pcie_speed;
12791         int rc, max_non_def_sbs;
12792         int rx_count, tx_count, rss_count, doorbell_size;
12793         int max_cos_est;
12794         bool is_vf;
12795         int cnic_cnt;
12796
12797         /* An estimated maximum supported CoS number according to the chip
12798          * version.
12799          * We will try to roughly estimate the maximum number of CoSes this chip
12800          * may support in order to minimize the memory allocated for Tx
12801          * netdev_queue's. This number will be accurately calculated during the
12802          * initialization of bp->max_cos based on the chip versions AND chip
12803          * revision in the bnx2x_init_bp().
12804          */
12805         max_cos_est = set_max_cos_est(ent->driver_data);
12806         if (max_cos_est < 0)
12807                 return max_cos_est;
12808         is_vf = set_is_vf(ent->driver_data);
12809         cnic_cnt = is_vf ? 0 : 1;
12810
12811         max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt);
12812
12813         /* add another SB for VF as it has no default SB */
12814         max_non_def_sbs += is_vf ? 1 : 0;
12815
12816         /* Maximum number of RSS queues: one IGU SB goes to CNIC */
12817         rss_count = max_non_def_sbs - cnic_cnt;
12818
12819         if (rss_count < 1)
12820                 return -EINVAL;
12821
12822         /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
12823         rx_count = rss_count + cnic_cnt;
12824
12825         /* Maximum number of netdev Tx queues:
12826          * Maximum TSS queues * Maximum supported number of CoS  + FCoE L2
12827          */
12828         tx_count = rss_count * max_cos_est + cnic_cnt;
12829
12830         /* dev zeroed in init_etherdev */
12831         dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
12832         if (!dev)
12833                 return -ENOMEM;
12834
12835         bp = netdev_priv(dev);
12836
12837         bp->flags = 0;
12838         if (is_vf)
12839                 bp->flags |= IS_VF_FLAG;
12840
12841         bp->igu_sb_cnt = max_non_def_sbs;
12842         bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
12843         bp->msg_enable = debug;
12844         bp->cnic_support = cnic_cnt;
12845         bp->cnic_probe = bnx2x_cnic_probe;
12846
12847         pci_set_drvdata(pdev, dev);
12848
12849         rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data);
12850         if (rc < 0) {
12851                 free_netdev(dev);
12852                 return rc;
12853         }
12854
12855         BNX2X_DEV_INFO("This is a %s function\n",
12856                        IS_PF(bp) ? "physical" : "virtual");
12857         BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off");
12858         BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs);
12859         BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
12860                        tx_count, rx_count);
12861
12862         rc = bnx2x_init_bp(bp);
12863         if (rc)
12864                 goto init_one_exit;
12865
12866         /* Map doorbells here as we need the real value of bp->max_cos which
12867          * is initialized in bnx2x_init_bp() to determine the number of
12868          * l2 connections.
12869          */
12870         if (IS_VF(bp)) {
12871                 bp->doorbells = bnx2x_vf_doorbells(bp);
12872                 rc = bnx2x_vf_pci_alloc(bp);
12873                 if (rc)
12874                         goto init_one_exit;
12875         } else {
12876                 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT);
12877                 if (doorbell_size > pci_resource_len(pdev, 2)) {
12878                         dev_err(&bp->pdev->dev,
12879                                 "Cannot map doorbells, bar size too small, aborting\n");
12880                         rc = -ENOMEM;
12881                         goto init_one_exit;
12882                 }
12883                 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
12884                                                 doorbell_size);
12885         }
12886         if (!bp->doorbells) {
12887                 dev_err(&bp->pdev->dev,
12888                         "Cannot map doorbell space, aborting\n");
12889                 rc = -ENOMEM;
12890                 goto init_one_exit;
12891         }
12892
12893         if (IS_VF(bp)) {
12894                 rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count);
12895                 if (rc)
12896                         goto init_one_exit;
12897         }
12898
12899         /* Enable SRIOV if capability found in configuration space */
12900         rc = bnx2x_iov_init_one(bp, int_mode, BNX2X_MAX_NUM_OF_VFS);
12901         if (rc)
12902                 goto init_one_exit;
12903
12904         /* calc qm_cid_count */
12905         bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
12906         BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count);
12907
12908         /* disable FCOE L2 queue for E1x*/
12909         if (CHIP_IS_E1x(bp))
12910                 bp->flags |= NO_FCOE_FLAG;
12911
12912         /* Set bp->num_queues for MSI-X mode*/
12913         bnx2x_set_num_queues(bp);
12914
12915         /* Configure interrupt mode: try to enable MSI-X/MSI if
12916          * needed.
12917          */
12918         rc = bnx2x_set_int_mode(bp);
12919         if (rc) {
12920                 dev_err(&pdev->dev, "Cannot set interrupts\n");
12921                 goto init_one_exit;
12922         }
12923         BNX2X_DEV_INFO("set interrupts successfully\n");
12924
12925         /* register the net device */
12926         rc = register_netdev(dev);
12927         if (rc) {
12928                 dev_err(&pdev->dev, "Cannot register net device\n");
12929                 goto init_one_exit;
12930         }
12931         BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name);
12932
12933         if (!NO_FCOE(bp)) {
12934                 /* Add storage MAC address */
12935                 rtnl_lock();
12936                 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
12937                 rtnl_unlock();
12938         }
12939         if (pcie_get_minimum_link(bp->pdev, &pcie_speed, &pcie_width) ||
12940             pcie_speed == PCI_SPEED_UNKNOWN ||
12941             pcie_width == PCIE_LNK_WIDTH_UNKNOWN)
12942                 BNX2X_DEV_INFO("Failed to determine PCI Express Bandwidth\n");
12943         else
12944                 BNX2X_DEV_INFO(
12945                        "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
12946                        board_info[ent->driver_data].name,
12947                        (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
12948                        pcie_width,
12949                        pcie_speed == PCIE_SPEED_2_5GT ? "2.5GHz" :
12950                        pcie_speed == PCIE_SPEED_5_0GT ? "5.0GHz" :
12951                        pcie_speed == PCIE_SPEED_8_0GT ? "8.0GHz" :
12952                        "Unknown",
12953                        dev->base_addr, bp->pdev->irq, dev->dev_addr);
12954
12955         return 0;
12956
12957 init_one_exit:
12958         bnx2x_disable_pcie_error_reporting(bp);
12959
12960         if (bp->regview)
12961                 iounmap(bp->regview);
12962
12963         if (IS_PF(bp) && bp->doorbells)
12964                 iounmap(bp->doorbells);
12965
12966         free_netdev(dev);
12967
12968         if (atomic_read(&pdev->enable_cnt) == 1)
12969                 pci_release_regions(pdev);
12970
12971         pci_disable_device(pdev);
12972
12973         return rc;
12974 }
12975
12976 static void __bnx2x_remove(struct pci_dev *pdev,
12977                            struct net_device *dev,
12978                            struct bnx2x *bp,
12979                            bool remove_netdev)
12980 {
12981         /* Delete storage MAC address */
12982         if (!NO_FCOE(bp)) {
12983                 rtnl_lock();
12984                 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
12985                 rtnl_unlock();
12986         }
12987
12988 #ifdef BCM_DCBNL
12989         /* Delete app tlvs from dcbnl */
12990         bnx2x_dcbnl_update_applist(bp, true);
12991 #endif
12992
12993         if (IS_PF(bp) &&
12994             !BP_NOMCP(bp) &&
12995             (bp->flags & BC_SUPPORTS_RMMOD_CMD))
12996                 bnx2x_fw_command(bp, DRV_MSG_CODE_RMMOD, 0);
12997
12998         /* Close the interface - either directly or implicitly */
12999         if (remove_netdev) {
13000                 unregister_netdev(dev);
13001         } else {
13002                 rtnl_lock();
13003                 dev_close(dev);
13004                 rtnl_unlock();
13005         }
13006
13007         bnx2x_iov_remove_one(bp);
13008
13009         /* Power on: we can't let PCI layer write to us while we are in D3 */
13010         if (IS_PF(bp))
13011                 bnx2x_set_power_state(bp, PCI_D0);
13012
13013         /* Disable MSI/MSI-X */
13014         bnx2x_disable_msi(bp);
13015
13016         /* Power off */
13017         if (IS_PF(bp))
13018                 bnx2x_set_power_state(bp, PCI_D3hot);
13019
13020         /* Make sure RESET task is not scheduled before continuing */
13021         cancel_delayed_work_sync(&bp->sp_rtnl_task);
13022
13023         /* send message via vfpf channel to release the resources of this vf */
13024         if (IS_VF(bp))
13025                 bnx2x_vfpf_release(bp);
13026
13027         /* Assumes no further PCIe PM changes will occur */
13028         if (system_state == SYSTEM_POWER_OFF) {
13029                 pci_wake_from_d3(pdev, bp->wol);
13030                 pci_set_power_state(pdev, PCI_D3hot);
13031         }
13032
13033         bnx2x_disable_pcie_error_reporting(bp);
13034
13035         if (bp->regview)
13036                 iounmap(bp->regview);
13037
13038         /* for vf doorbells are part of the regview and were unmapped along with
13039          * it. FW is only loaded by PF.
13040          */
13041         if (IS_PF(bp)) {
13042                 if (bp->doorbells)
13043                         iounmap(bp->doorbells);
13044
13045                 bnx2x_release_firmware(bp);
13046         }
13047         bnx2x_free_mem_bp(bp);
13048
13049         if (remove_netdev)
13050                 free_netdev(dev);
13051
13052         if (atomic_read(&pdev->enable_cnt) == 1)
13053                 pci_release_regions(pdev);
13054
13055         pci_disable_device(pdev);
13056 }
13057
13058 static void bnx2x_remove_one(struct pci_dev *pdev)
13059 {
13060         struct net_device *dev = pci_get_drvdata(pdev);
13061         struct bnx2x *bp;
13062
13063         if (!dev) {
13064                 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
13065                 return;
13066         }
13067         bp = netdev_priv(dev);
13068
13069         __bnx2x_remove(pdev, dev, bp, true);
13070 }
13071
13072 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
13073 {
13074         bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;
13075
13076         bp->rx_mode = BNX2X_RX_MODE_NONE;
13077
13078         if (CNIC_LOADED(bp))
13079                 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
13080
13081         /* Stop Tx */
13082         bnx2x_tx_disable(bp);
13083         /* Delete all NAPI objects */
13084         bnx2x_del_all_napi(bp);
13085         if (CNIC_LOADED(bp))
13086                 bnx2x_del_all_napi_cnic(bp);
13087         netdev_reset_tc(bp->dev);
13088
13089         del_timer_sync(&bp->timer);
13090         cancel_delayed_work(&bp->sp_task);
13091         cancel_delayed_work(&bp->period_task);
13092
13093         spin_lock_bh(&bp->stats_lock);
13094         bp->stats_state = STATS_STATE_DISABLED;
13095         spin_unlock_bh(&bp->stats_lock);
13096
13097         bnx2x_save_statistics(bp);
13098
13099         netif_carrier_off(bp->dev);
13100
13101         return 0;
13102 }
13103
13104 /**
13105  * bnx2x_io_error_detected - called when PCI error is detected
13106  * @pdev: Pointer to PCI device
13107  * @state: The current pci connection state
13108  *
13109  * This function is called after a PCI bus error affecting
13110  * this device has been detected.
13111  */
13112 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
13113                                                 pci_channel_state_t state)
13114 {
13115         struct net_device *dev = pci_get_drvdata(pdev);
13116         struct bnx2x *bp = netdev_priv(dev);
13117
13118         rtnl_lock();
13119
13120         BNX2X_ERR("IO error detected\n");
13121
13122         netif_device_detach(dev);
13123
13124         if (state == pci_channel_io_perm_failure) {
13125                 rtnl_unlock();
13126                 return PCI_ERS_RESULT_DISCONNECT;
13127         }
13128
13129         if (netif_running(dev))
13130                 bnx2x_eeh_nic_unload(bp);
13131
13132         bnx2x_prev_path_mark_eeh(bp);
13133
13134         pci_disable_device(pdev);
13135
13136         rtnl_unlock();
13137
13138         /* Request a slot reset */
13139         return PCI_ERS_RESULT_NEED_RESET;
13140 }
13141
13142 /**
13143  * bnx2x_io_slot_reset - called after the PCI bus has been reset
13144  * @pdev: Pointer to PCI device
13145  *
13146  * Restart the card from scratch, as if from a cold-boot.
13147  */
13148 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
13149 {
13150         struct net_device *dev = pci_get_drvdata(pdev);
13151         struct bnx2x *bp = netdev_priv(dev);
13152         int i;
13153
13154         rtnl_lock();
13155         BNX2X_ERR("IO slot reset initializing...\n");
13156         if (pci_enable_device(pdev)) {
13157                 dev_err(&pdev->dev,
13158                         "Cannot re-enable PCI device after reset\n");
13159                 rtnl_unlock();
13160                 return PCI_ERS_RESULT_DISCONNECT;
13161         }
13162
13163         pci_set_master(pdev);
13164         pci_restore_state(pdev);
13165         pci_save_state(pdev);
13166
13167         if (netif_running(dev))
13168                 bnx2x_set_power_state(bp, PCI_D0);
13169
13170         if (netif_running(dev)) {
13171                 BNX2X_ERR("IO slot reset --> driver unload\n");
13172
13173                 /* MCP should have been reset; Need to wait for validity */
13174                 bnx2x_init_shmem(bp);
13175
13176                 if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
13177                         u32 v;
13178
13179                         v = SHMEM2_RD(bp,
13180                                       drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
13181                         SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
13182                                   v & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
13183                 }
13184                 bnx2x_drain_tx_queues(bp);
13185                 bnx2x_send_unload_req(bp, UNLOAD_RECOVERY);
13186                 bnx2x_netif_stop(bp, 1);
13187                 bnx2x_free_irq(bp);
13188
13189                 /* Report UNLOAD_DONE to MCP */
13190                 bnx2x_send_unload_done(bp, true);
13191
13192                 bp->sp_state = 0;
13193                 bp->port.pmf = 0;
13194
13195                 bnx2x_prev_unload(bp);
13196
13197                 /* We should have reseted the engine, so It's fair to
13198                  * assume the FW will no longer write to the bnx2x driver.
13199                  */
13200                 bnx2x_squeeze_objects(bp);
13201                 bnx2x_free_skbs(bp);
13202                 for_each_rx_queue(bp, i)
13203                         bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
13204                 bnx2x_free_fp_mem(bp);
13205                 bnx2x_free_mem(bp);
13206
13207                 bp->state = BNX2X_STATE_CLOSED;
13208         }
13209
13210         rtnl_unlock();
13211
13212         /* If AER, perform cleanup of the PCIe registers */
13213         if (bp->flags & AER_ENABLED) {
13214                 if (pci_cleanup_aer_uncorrect_error_status(pdev))
13215                         BNX2X_ERR("pci_cleanup_aer_uncorrect_error_status failed\n");
13216                 else
13217                         DP(NETIF_MSG_HW, "pci_cleanup_aer_uncorrect_error_status succeeded\n");
13218         }
13219
13220         return PCI_ERS_RESULT_RECOVERED;
13221 }
13222
13223 /**
13224  * bnx2x_io_resume - called when traffic can start flowing again
13225  * @pdev: Pointer to PCI device
13226  *
13227  * This callback is called when the error recovery driver tells us that
13228  * its OK to resume normal operation.
13229  */
13230 static void bnx2x_io_resume(struct pci_dev *pdev)
13231 {
13232         struct net_device *dev = pci_get_drvdata(pdev);
13233         struct bnx2x *bp = netdev_priv(dev);
13234
13235         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
13236                 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n");
13237                 return;
13238         }
13239
13240         rtnl_lock();
13241
13242         bp->fw_seq = SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
13243                                                         DRV_MSG_SEQ_NUMBER_MASK;
13244
13245         if (netif_running(dev))
13246                 bnx2x_nic_load(bp, LOAD_NORMAL);
13247
13248         netif_device_attach(dev);
13249
13250         rtnl_unlock();
13251 }
13252
13253 static const struct pci_error_handlers bnx2x_err_handler = {
13254         .error_detected = bnx2x_io_error_detected,
13255         .slot_reset     = bnx2x_io_slot_reset,
13256         .resume         = bnx2x_io_resume,
13257 };
13258
13259 static void bnx2x_shutdown(struct pci_dev *pdev)
13260 {
13261         struct net_device *dev = pci_get_drvdata(pdev);
13262         struct bnx2x *bp;
13263
13264         if (!dev)
13265                 return;
13266
13267         bp = netdev_priv(dev);
13268         if (!bp)
13269                 return;
13270
13271         rtnl_lock();
13272         netif_device_detach(dev);
13273         rtnl_unlock();
13274
13275         /* Don't remove the netdevice, as there are scenarios which will cause
13276          * the kernel to hang, e.g., when trying to remove bnx2i while the
13277          * rootfs is mounted from SAN.
13278          */
13279         __bnx2x_remove(pdev, dev, bp, false);
13280 }
13281
13282 static struct pci_driver bnx2x_pci_driver = {
13283         .name        = DRV_MODULE_NAME,
13284         .id_table    = bnx2x_pci_tbl,
13285         .probe       = bnx2x_init_one,
13286         .remove      = bnx2x_remove_one,
13287         .suspend     = bnx2x_suspend,
13288         .resume      = bnx2x_resume,
13289         .err_handler = &bnx2x_err_handler,
13290 #ifdef CONFIG_BNX2X_SRIOV
13291         .sriov_configure = bnx2x_sriov_configure,
13292 #endif
13293         .shutdown    = bnx2x_shutdown,
13294 };
13295
13296 static int __init bnx2x_init(void)
13297 {
13298         int ret;
13299
13300         pr_info("%s", version);
13301
13302         bnx2x_wq = create_singlethread_workqueue("bnx2x");
13303         if (bnx2x_wq == NULL) {
13304                 pr_err("Cannot create workqueue\n");
13305                 return -ENOMEM;
13306         }
13307
13308         ret = pci_register_driver(&bnx2x_pci_driver);
13309         if (ret) {
13310                 pr_err("Cannot register driver\n");
13311                 destroy_workqueue(bnx2x_wq);
13312         }
13313         return ret;
13314 }
13315
13316 static void __exit bnx2x_cleanup(void)
13317 {
13318         struct list_head *pos, *q;
13319
13320         pci_unregister_driver(&bnx2x_pci_driver);
13321
13322         destroy_workqueue(bnx2x_wq);
13323
13324         /* Free globally allocated resources */
13325         list_for_each_safe(pos, q, &bnx2x_prev_list) {
13326                 struct bnx2x_prev_path_list *tmp =
13327                         list_entry(pos, struct bnx2x_prev_path_list, list);
13328                 list_del(pos);
13329                 kfree(tmp);
13330         }
13331 }
13332
13333 void bnx2x_notify_link_changed(struct bnx2x *bp)
13334 {
13335         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
13336 }
13337
13338 module_init(bnx2x_init);
13339 module_exit(bnx2x_cleanup);
13340
13341 /**
13342  * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
13343  *
13344  * @bp:         driver handle
13345  * @set:        set or clear the CAM entry
13346  *
13347  * This function will wait until the ramrod completion returns.
13348  * Return 0 if success, -ENODEV if ramrod doesn't return.
13349  */
13350 static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
13351 {
13352         unsigned long ramrod_flags = 0;
13353
13354         __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
13355         return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
13356                                  &bp->iscsi_l2_mac_obj, true,
13357                                  BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
13358 }
13359
13360 /* count denotes the number of new completions we have seen */
13361 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
13362 {
13363         struct eth_spe *spe;
13364         int cxt_index, cxt_offset;
13365
13366 #ifdef BNX2X_STOP_ON_ERROR
13367         if (unlikely(bp->panic))
13368                 return;
13369 #endif
13370
13371         spin_lock_bh(&bp->spq_lock);
13372         BUG_ON(bp->cnic_spq_pending < count);
13373         bp->cnic_spq_pending -= count;
13374
13375         for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
13376                 u16 type =  (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
13377                                 & SPE_HDR_CONN_TYPE) >>
13378                                 SPE_HDR_CONN_TYPE_SHIFT;
13379                 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
13380                                 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
13381
13382                 /* Set validation for iSCSI L2 client before sending SETUP
13383                  *  ramrod
13384                  */
13385                 if (type == ETH_CONNECTION_TYPE) {
13386                         if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) {
13387                                 cxt_index = BNX2X_ISCSI_ETH_CID(bp) /
13388                                         ILT_PAGE_CIDS;
13389                                 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) -
13390                                         (cxt_index * ILT_PAGE_CIDS);
13391                                 bnx2x_set_ctx_validation(bp,
13392                                         &bp->context[cxt_index].
13393                                                          vcxt[cxt_offset].eth,
13394                                         BNX2X_ISCSI_ETH_CID(bp));
13395                         }
13396                 }
13397
13398                 /*
13399                  * There may be not more than 8 L2, not more than 8 L5 SPEs
13400                  * and in the air. We also check that number of outstanding
13401                  * COMMON ramrods is not more than the EQ and SPQ can
13402                  * accommodate.
13403                  */
13404                 if (type == ETH_CONNECTION_TYPE) {
13405                         if (!atomic_read(&bp->cq_spq_left))
13406                                 break;
13407                         else
13408                                 atomic_dec(&bp->cq_spq_left);
13409                 } else if (type == NONE_CONNECTION_TYPE) {
13410                         if (!atomic_read(&bp->eq_spq_left))
13411                                 break;
13412                         else
13413                                 atomic_dec(&bp->eq_spq_left);
13414                 } else if ((type == ISCSI_CONNECTION_TYPE) ||
13415                            (type == FCOE_CONNECTION_TYPE)) {
13416                         if (bp->cnic_spq_pending >=
13417                             bp->cnic_eth_dev.max_kwqe_pending)
13418                                 break;
13419                         else
13420                                 bp->cnic_spq_pending++;
13421                 } else {
13422                         BNX2X_ERR("Unknown SPE type: %d\n", type);
13423                         bnx2x_panic();
13424                         break;
13425                 }
13426
13427                 spe = bnx2x_sp_get_next(bp);
13428                 *spe = *bp->cnic_kwq_cons;
13429
13430                 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n",
13431                    bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
13432
13433                 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
13434                         bp->cnic_kwq_cons = bp->cnic_kwq;
13435                 else
13436                         bp->cnic_kwq_cons++;
13437         }
13438         bnx2x_sp_prod_update(bp);
13439         spin_unlock_bh(&bp->spq_lock);
13440 }
13441
13442 static int bnx2x_cnic_sp_queue(struct net_device *dev,
13443                                struct kwqe_16 *kwqes[], u32 count)
13444 {
13445         struct bnx2x *bp = netdev_priv(dev);
13446         int i;
13447
13448 #ifdef BNX2X_STOP_ON_ERROR
13449         if (unlikely(bp->panic)) {
13450                 BNX2X_ERR("Can't post to SP queue while panic\n");
13451                 return -EIO;
13452         }
13453 #endif
13454
13455         if ((bp->recovery_state != BNX2X_RECOVERY_DONE) &&
13456             (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
13457                 BNX2X_ERR("Handling parity error recovery. Try again later\n");
13458                 return -EAGAIN;
13459         }
13460
13461         spin_lock_bh(&bp->spq_lock);
13462
13463         for (i = 0; i < count; i++) {
13464                 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
13465
13466                 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
13467                         break;
13468
13469                 *bp->cnic_kwq_prod = *spe;
13470
13471                 bp->cnic_kwq_pending++;
13472
13473                 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n",
13474                    spe->hdr.conn_and_cmd_data, spe->hdr.type,
13475                    spe->data.update_data_addr.hi,
13476                    spe->data.update_data_addr.lo,
13477                    bp->cnic_kwq_pending);
13478
13479                 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
13480                         bp->cnic_kwq_prod = bp->cnic_kwq;
13481                 else
13482                         bp->cnic_kwq_prod++;
13483         }
13484
13485         spin_unlock_bh(&bp->spq_lock);
13486
13487         if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
13488                 bnx2x_cnic_sp_post(bp, 0);
13489
13490         return i;
13491 }
13492
13493 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
13494 {
13495         struct cnic_ops *c_ops;
13496         int rc = 0;
13497
13498         mutex_lock(&bp->cnic_mutex);
13499         c_ops = rcu_dereference_protected(bp->cnic_ops,
13500                                           lockdep_is_held(&bp->cnic_mutex));
13501         if (c_ops)
13502                 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
13503         mutex_unlock(&bp->cnic_mutex);
13504
13505         return rc;
13506 }
13507
13508 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
13509 {
13510         struct cnic_ops *c_ops;
13511         int rc = 0;
13512
13513         rcu_read_lock();
13514         c_ops = rcu_dereference(bp->cnic_ops);
13515         if (c_ops)
13516                 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
13517         rcu_read_unlock();
13518
13519         return rc;
13520 }
13521
13522 /*
13523  * for commands that have no data
13524  */
13525 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
13526 {
13527         struct cnic_ctl_info ctl = {0};
13528
13529         ctl.cmd = cmd;
13530
13531         return bnx2x_cnic_ctl_send(bp, &ctl);
13532 }
13533
13534 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
13535 {
13536         struct cnic_ctl_info ctl = {0};
13537
13538         /* first we tell CNIC and only then we count this as a completion */
13539         ctl.cmd = CNIC_CTL_COMPLETION_CMD;
13540         ctl.data.comp.cid = cid;
13541         ctl.data.comp.error = err;
13542
13543         bnx2x_cnic_ctl_send_bh(bp, &ctl);
13544         bnx2x_cnic_sp_post(bp, 0);
13545 }
13546
13547 /* Called with netif_addr_lock_bh() taken.
13548  * Sets an rx_mode config for an iSCSI ETH client.
13549  * Doesn't block.
13550  * Completion should be checked outside.
13551  */
13552 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
13553 {
13554         unsigned long accept_flags = 0, ramrod_flags = 0;
13555         u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
13556         int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
13557
13558         if (start) {
13559                 /* Start accepting on iSCSI L2 ring. Accept all multicasts
13560                  * because it's the only way for UIO Queue to accept
13561                  * multicasts (in non-promiscuous mode only one Queue per
13562                  * function will receive multicast packets (leading in our
13563                  * case).
13564                  */
13565                 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
13566                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
13567                 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
13568                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
13569
13570                 /* Clear STOP_PENDING bit if START is requested */
13571                 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
13572
13573                 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
13574         } else
13575                 /* Clear START_PENDING bit if STOP is requested */
13576                 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
13577
13578         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
13579                 set_bit(sched_state, &bp->sp_state);
13580         else {
13581                 __set_bit(RAMROD_RX, &ramrod_flags);
13582                 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
13583                                     ramrod_flags);
13584         }
13585 }
13586
13587 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
13588 {
13589         struct bnx2x *bp = netdev_priv(dev);
13590         int rc = 0;
13591
13592         switch (ctl->cmd) {
13593         case DRV_CTL_CTXTBL_WR_CMD: {
13594                 u32 index = ctl->data.io.offset;
13595                 dma_addr_t addr = ctl->data.io.dma_addr;
13596
13597                 bnx2x_ilt_wr(bp, index, addr);
13598                 break;
13599         }
13600
13601         case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
13602                 int count = ctl->data.credit.credit_count;
13603
13604                 bnx2x_cnic_sp_post(bp, count);
13605                 break;
13606         }
13607
13608         /* rtnl_lock is held.  */
13609         case DRV_CTL_START_L2_CMD: {
13610                 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13611                 unsigned long sp_bits = 0;
13612
13613                 /* Configure the iSCSI classification object */
13614                 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
13615                                    cp->iscsi_l2_client_id,
13616                                    cp->iscsi_l2_cid, BP_FUNC(bp),
13617                                    bnx2x_sp(bp, mac_rdata),
13618                                    bnx2x_sp_mapping(bp, mac_rdata),
13619                                    BNX2X_FILTER_MAC_PENDING,
13620                                    &bp->sp_state, BNX2X_OBJ_TYPE_RX,
13621                                    &bp->macs_pool);
13622
13623                 /* Set iSCSI MAC address */
13624                 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
13625                 if (rc)
13626                         break;
13627
13628                 mmiowb();
13629                 barrier();
13630
13631                 /* Start accepting on iSCSI L2 ring */
13632
13633                 netif_addr_lock_bh(dev);
13634                 bnx2x_set_iscsi_eth_rx_mode(bp, true);
13635                 netif_addr_unlock_bh(dev);
13636
13637                 /* bits to wait on */
13638                 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
13639                 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
13640
13641                 if (!bnx2x_wait_sp_comp(bp, sp_bits))
13642                         BNX2X_ERR("rx_mode completion timed out!\n");
13643
13644                 break;
13645         }
13646
13647         /* rtnl_lock is held.  */
13648         case DRV_CTL_STOP_L2_CMD: {
13649                 unsigned long sp_bits = 0;
13650
13651                 /* Stop accepting on iSCSI L2 ring */
13652                 netif_addr_lock_bh(dev);
13653                 bnx2x_set_iscsi_eth_rx_mode(bp, false);
13654                 netif_addr_unlock_bh(dev);
13655
13656                 /* bits to wait on */
13657                 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
13658                 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
13659
13660                 if (!bnx2x_wait_sp_comp(bp, sp_bits))
13661                         BNX2X_ERR("rx_mode completion timed out!\n");
13662
13663                 mmiowb();
13664                 barrier();
13665
13666                 /* Unset iSCSI L2 MAC */
13667                 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
13668                                         BNX2X_ISCSI_ETH_MAC, true);
13669                 break;
13670         }
13671         case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
13672                 int count = ctl->data.credit.credit_count;
13673
13674                 smp_mb__before_atomic_inc();
13675                 atomic_add(count, &bp->cq_spq_left);
13676                 smp_mb__after_atomic_inc();
13677                 break;
13678         }
13679         case DRV_CTL_ULP_REGISTER_CMD: {
13680                 int ulp_type = ctl->data.register_data.ulp_type;
13681
13682                 if (CHIP_IS_E3(bp)) {
13683                         int idx = BP_FW_MB_IDX(bp);
13684                         u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
13685                         int path = BP_PATH(bp);
13686                         int port = BP_PORT(bp);
13687                         int i;
13688                         u32 scratch_offset;
13689                         u32 *host_addr;
13690
13691                         /* first write capability to shmem2 */
13692                         if (ulp_type == CNIC_ULP_ISCSI)
13693                                 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
13694                         else if (ulp_type == CNIC_ULP_FCOE)
13695                                 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
13696                         SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
13697
13698                         if ((ulp_type != CNIC_ULP_FCOE) ||
13699                             (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) ||
13700                             (!(bp->flags &  BC_SUPPORTS_FCOE_FEATURES)))
13701                                 break;
13702
13703                         /* if reached here - should write fcoe capabilities */
13704                         scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr);
13705                         if (!scratch_offset)
13706                                 break;
13707                         scratch_offset += offsetof(struct glob_ncsi_oem_data,
13708                                                    fcoe_features[path][port]);
13709                         host_addr = (u32 *) &(ctl->data.register_data.
13710                                               fcoe_features);
13711                         for (i = 0; i < sizeof(struct fcoe_capabilities);
13712                              i += 4)
13713                                 REG_WR(bp, scratch_offset + i,
13714                                        *(host_addr + i/4));
13715                 }
13716                 break;
13717         }
13718
13719         case DRV_CTL_ULP_UNREGISTER_CMD: {
13720                 int ulp_type = ctl->data.ulp_type;
13721
13722                 if (CHIP_IS_E3(bp)) {
13723                         int idx = BP_FW_MB_IDX(bp);
13724                         u32 cap;
13725
13726                         cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
13727                         if (ulp_type == CNIC_ULP_ISCSI)
13728                                 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
13729                         else if (ulp_type == CNIC_ULP_FCOE)
13730                                 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
13731                         SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
13732                 }
13733                 break;
13734         }
13735
13736         default:
13737                 BNX2X_ERR("unknown command %x\n", ctl->cmd);
13738                 rc = -EINVAL;
13739         }
13740
13741         return rc;
13742 }
13743
13744 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
13745 {
13746         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13747
13748         if (bp->flags & USING_MSIX_FLAG) {
13749                 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
13750                 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
13751                 cp->irq_arr[0].vector = bp->msix_table[1].vector;
13752         } else {
13753                 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
13754                 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
13755         }
13756         if (!CHIP_IS_E1x(bp))
13757                 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
13758         else
13759                 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
13760
13761         cp->irq_arr[0].status_blk_num =  bnx2x_cnic_fw_sb_id(bp);
13762         cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
13763         cp->irq_arr[1].status_blk = bp->def_status_blk;
13764         cp->irq_arr[1].status_blk_num = DEF_SB_ID;
13765         cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
13766
13767         cp->num_irq = 2;
13768 }
13769
13770 void bnx2x_setup_cnic_info(struct bnx2x *bp)
13771 {
13772         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13773
13774         cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
13775                              bnx2x_cid_ilt_lines(bp);
13776         cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
13777         cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
13778         cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
13779
13780         DP(NETIF_MSG_IFUP, "BNX2X_1st_NON_L2_ETH_CID(bp) %x, cp->starting_cid %x, cp->fcoe_init_cid %x, cp->iscsi_l2_cid %x\n",
13781            BNX2X_1st_NON_L2_ETH_CID(bp), cp->starting_cid, cp->fcoe_init_cid,
13782            cp->iscsi_l2_cid);
13783
13784         if (NO_ISCSI_OOO(bp))
13785                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
13786 }
13787
13788 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
13789                                void *data)
13790 {
13791         struct bnx2x *bp = netdev_priv(dev);
13792         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13793         int rc;
13794
13795         DP(NETIF_MSG_IFUP, "Register_cnic called\n");
13796
13797         if (ops == NULL) {
13798                 BNX2X_ERR("NULL ops received\n");
13799                 return -EINVAL;
13800         }
13801
13802         if (!CNIC_SUPPORT(bp)) {
13803                 BNX2X_ERR("Can't register CNIC when not supported\n");
13804                 return -EOPNOTSUPP;
13805         }
13806
13807         if (!CNIC_LOADED(bp)) {
13808                 rc = bnx2x_load_cnic(bp);
13809                 if (rc) {
13810                         BNX2X_ERR("CNIC-related load failed\n");
13811                         return rc;
13812                 }
13813         }
13814
13815         bp->cnic_enabled = true;
13816
13817         bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
13818         if (!bp->cnic_kwq)
13819                 return -ENOMEM;
13820
13821         bp->cnic_kwq_cons = bp->cnic_kwq;
13822         bp->cnic_kwq_prod = bp->cnic_kwq;
13823         bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
13824
13825         bp->cnic_spq_pending = 0;
13826         bp->cnic_kwq_pending = 0;
13827
13828         bp->cnic_data = data;
13829
13830         cp->num_irq = 0;
13831         cp->drv_state |= CNIC_DRV_STATE_REGD;
13832         cp->iro_arr = bp->iro_arr;
13833
13834         bnx2x_setup_cnic_irq_info(bp);
13835
13836         rcu_assign_pointer(bp->cnic_ops, ops);
13837
13838         return 0;
13839 }
13840
13841 static int bnx2x_unregister_cnic(struct net_device *dev)
13842 {
13843         struct bnx2x *bp = netdev_priv(dev);
13844         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13845
13846         mutex_lock(&bp->cnic_mutex);
13847         cp->drv_state = 0;
13848         RCU_INIT_POINTER(bp->cnic_ops, NULL);
13849         mutex_unlock(&bp->cnic_mutex);
13850         synchronize_rcu();
13851         bp->cnic_enabled = false;
13852         kfree(bp->cnic_kwq);
13853         bp->cnic_kwq = NULL;
13854
13855         return 0;
13856 }
13857
13858 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
13859 {
13860         struct bnx2x *bp = netdev_priv(dev);
13861         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13862
13863         /* If both iSCSI and FCoE are disabled - return NULL in
13864          * order to indicate CNIC that it should not try to work
13865          * with this device.
13866          */
13867         if (NO_ISCSI(bp) && NO_FCOE(bp))
13868                 return NULL;
13869
13870         cp->drv_owner = THIS_MODULE;
13871         cp->chip_id = CHIP_ID(bp);
13872         cp->pdev = bp->pdev;
13873         cp->io_base = bp->regview;
13874         cp->io_base2 = bp->doorbells;
13875         cp->max_kwqe_pending = 8;
13876         cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
13877         cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
13878                              bnx2x_cid_ilt_lines(bp);
13879         cp->ctx_tbl_len = CNIC_ILT_LINES;
13880         cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
13881         cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
13882         cp->drv_ctl = bnx2x_drv_ctl;
13883         cp->drv_register_cnic = bnx2x_register_cnic;
13884         cp->drv_unregister_cnic = bnx2x_unregister_cnic;
13885         cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
13886         cp->iscsi_l2_client_id =
13887                 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
13888         cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
13889
13890         if (NO_ISCSI_OOO(bp))
13891                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
13892
13893         if (NO_ISCSI(bp))
13894                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
13895
13896         if (NO_FCOE(bp))
13897                 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
13898
13899         BNX2X_DEV_INFO(
13900                 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
13901            cp->ctx_blk_size,
13902            cp->ctx_tbl_offset,
13903            cp->ctx_tbl_len,
13904            cp->starting_cid);
13905         return cp;
13906 }
13907
13908 u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp)
13909 {
13910         struct bnx2x *bp = fp->bp;
13911         u32 offset = BAR_USTRORM_INTMEM;
13912
13913         if (IS_VF(bp))
13914                 return bnx2x_vf_ustorm_prods_offset(bp, fp);
13915         else if (!CHIP_IS_E1x(bp))
13916                 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
13917         else
13918                 offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id);
13919
13920         return offset;
13921 }
13922
13923 /* called only on E1H or E2.
13924  * When pretending to be PF, the pretend value is the function number 0...7
13925  * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
13926  * combination
13927  */
13928 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val)
13929 {
13930         u32 pretend_reg;
13931
13932         if (CHIP_IS_E1H(bp) && pretend_func_val >= E1H_FUNC_MAX)
13933                 return -1;
13934
13935         /* get my own pretend register */
13936         pretend_reg = bnx2x_get_pretend_reg(bp);
13937         REG_WR(bp, pretend_reg, pretend_func_val);
13938         REG_RD(bp, pretend_reg);
13939         return 0;
13940 }