drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c

   1 /* bnx2x_main.c: Broadcom Everest network driver.
   2  *
   3  * Copyright (c) 2007-2013 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  *
   9  * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
  10  * Written by: Eliezer Tamir
  11  * Based on code from Michael Chan's bnx2 driver
  12  * UDP CSUM errata workaround by Arik Gendelman
  13  * Slowpath and fastpath rework by Vladislav Zolotarov
  14  * Statistics and Link management by Yitchak Gertner
  15  *
  16  */
  17
  18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  19
  20 #include <linux/module.h>
  21 #include <linux/moduleparam.h>
  22 #include <linux/kernel.h>
  23 #include <linux/device.h>  /* for dev_info() */
  24 #include <linux/timer.h>
  25 #include <linux/errno.h>
  26 #include <linux/ioport.h>
  27 #include <linux/slab.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/pci.h>
  30 #include <linux/aer.h>
  31 #include <linux/init.h>
  32 #include <linux/netdevice.h>
  33 #include <linux/etherdevice.h>
  34 #include <linux/skbuff.h>
  35 #include <linux/dma-mapping.h>
  36 #include <linux/bitops.h>
  37 #include <linux/irq.h>
  38 #include <linux/delay.h>
  39 #include <asm/byteorder.h>
  40 #include <linux/time.h>
  41 #include <linux/ethtool.h>
  42 #include <linux/mii.h>
  43 #include <linux/if_vlan.h>
  44 #include <linux/crash_dump.h>
  45 #include <net/ip.h>
  46 #include <net/ipv6.h>
  47 #include <net/tcp.h>
  48 #include <net/vxlan.h>
  49 #include <net/checksum.h>
  50 #include <net/ip6_checksum.h>
  51 #include <linux/workqueue.h>
  52 #include <linux/crc32.h>
  53 #include <linux/crc32c.h>
  54 #include <linux/prefetch.h>
  55 #include <linux/zlib.h>
  56 #include <linux/io.h>
  57 #include <linux/semaphore.h>
  58 #include <linux/stringify.h>
  59 #include <linux/vmalloc.h>
  60
  61 #include "bnx2x.h"
  62 #include "bnx2x_init.h"
  63 #include "bnx2x_init_ops.h"
  64 #include "bnx2x_cmn.h"
  65 #include "bnx2x_vfpf.h"
  66 #include "bnx2x_dcb.h"
  67 #include "bnx2x_sp.h"
  68 #include <linux/firmware.h>
  69 #include "bnx2x_fw_file_hdr.h"
  70 /* FW files */
  71 #define FW_FILE_VERSION                                 \
  72         __stringify(BCM_5710_FW_MAJOR_VERSION) "."      \
  73         __stringify(BCM_5710_FW_MINOR_VERSION) "."      \
  74         __stringify(BCM_5710_FW_REVISION_VERSION) "."   \
  75         __stringify(BCM_5710_FW_ENGINEERING_VERSION)
  76 #define FW_FILE_NAME_E1         "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
  77 #define FW_FILE_NAME_E1H        "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
  78 #define FW_FILE_NAME_E2         "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
  79
  80 /* Time in jiffies before concluding the transmitter is hung */
  81 #define TX_TIMEOUT              (5*HZ)
  82
  83 static char version[] =
  84         "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
  85         DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  86
  87 MODULE_AUTHOR("Eliezer Tamir");
  88 MODULE_DESCRIPTION("Broadcom NetXtreme II "
  89                    "BCM57710/57711/57711E/"
  90                    "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
  91                    "57840/57840_MF Driver");
  92 MODULE_LICENSE("GPL");
  93 MODULE_VERSION(DRV_MODULE_VERSION);
  94 MODULE_FIRMWARE(FW_FILE_NAME_E1);
  95 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
  96 MODULE_FIRMWARE(FW_FILE_NAME_E2);
  97
  98 int bnx2x_num_queues;
  99 module_param_named(num_queues, bnx2x_num_queues, int, S_IRUGO);
 100 MODULE_PARM_DESC(num_queues,
 101                  " Set number of queues (default is as a number of CPUs)");
 102
 103 static int disable_tpa;
 104 module_param(disable_tpa, int, S_IRUGO);
 105 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
 106
 107 static int int_mode;
 108 module_param(int_mode, int, S_IRUGO);
 109 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
 110                                 "(1 INT#x; 2 MSI)");
 111
 112 static int dropless_fc;
 113 module_param(dropless_fc, int, S_IRUGO);
 114 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
 115
 116 static int mrrs = -1;
 117 module_param(mrrs, int, S_IRUGO);
 118 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
 119
 120 static int debug;
 121 module_param(debug, int, S_IRUGO);
 122 MODULE_PARM_DESC(debug, " Default debug msglevel");
 123
 124 static struct workqueue_struct *bnx2x_wq;
 125 struct workqueue_struct *bnx2x_iov_wq;
 126
 127 struct bnx2x_mac_vals {
 128         u32 xmac_addr;
 129         u32 xmac_val;
 130         u32 emac_addr;
 131         u32 emac_val;
 132         u32 umac_addr;
 133         u32 umac_val;
 134         u32 bmac_addr;
 135         u32 bmac_val[2];
 136 };
 137
 138 enum bnx2x_board_type {
 139         BCM57710 = 0,
 140         BCM57711,
 141         BCM57711E,
 142         BCM57712,
 143         BCM57712_MF,
 144         BCM57712_VF,
 145         BCM57800,
 146         BCM57800_MF,
 147         BCM57800_VF,
 148         BCM57810,
 149         BCM57810_MF,
 150         BCM57810_VF,
 151         BCM57840_4_10,
 152         BCM57840_2_20,
 153         BCM57840_MF,
 154         BCM57840_VF,
 155         BCM57811,
 156         BCM57811_MF,
 157         BCM57840_O,
 158         BCM57840_MFO,
 159         BCM57811_VF
 160 };
 161
 162 /* indexed by board_type, above */
 163 static struct {
 164         char *name;
 165 } board_info[] = {
 166         [BCM57710]      = { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
 167         [BCM57711]      = { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
 168         [BCM57711E]     = { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
 169         [BCM57712]      = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
 170         [BCM57712_MF]   = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
 171         [BCM57712_VF]   = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Virtual Function" },
 172         [BCM57800]      = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
 173         [BCM57800_MF]   = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
 174         [BCM57800_VF]   = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Virtual Function" },
 175         [BCM57810]      = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
 176         [BCM57810_MF]   = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
 177         [BCM57810_VF]   = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Virtual Function" },
 178         [BCM57840_4_10] = { "Broadcom NetXtreme II BCM57840 10 Gigabit Ethernet" },
 179         [BCM57840_2_20] = { "Broadcom NetXtreme II BCM57840 20 Gigabit Ethernet" },
 180         [BCM57840_MF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
 181         [BCM57840_VF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" },
 182         [BCM57811]      = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet" },
 183         [BCM57811_MF]   = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet Multi Function" },
 184         [BCM57840_O]    = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
 185         [BCM57840_MFO]  = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
 186         [BCM57811_VF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" }
 187 };
 188
 189 #ifndef PCI_DEVICE_ID_NX2_57710
 190 #define PCI_DEVICE_ID_NX2_57710         CHIP_NUM_57710
 191 #endif
 192 #ifndef PCI_DEVICE_ID_NX2_57711
 193 #define PCI_DEVICE_ID_NX2_57711         CHIP_NUM_57711
 194 #endif
 195 #ifndef PCI_DEVICE_ID_NX2_57711E
 196 #define PCI_DEVICE_ID_NX2_57711E        CHIP_NUM_57711E
 197 #endif
 198 #ifndef PCI_DEVICE_ID_NX2_57712
 199 #define PCI_DEVICE_ID_NX2_57712         CHIP_NUM_57712
 200 #endif
 201 #ifndef PCI_DEVICE_ID_NX2_57712_MF
 202 #define PCI_DEVICE_ID_NX2_57712_MF      CHIP_NUM_57712_MF
 203 #endif
 204 #ifndef PCI_DEVICE_ID_NX2_57712_VF
 205 #define PCI_DEVICE_ID_NX2_57712_VF      CHIP_NUM_57712_VF
 206 #endif
 207 #ifndef PCI_DEVICE_ID_NX2_57800
 208 #define PCI_DEVICE_ID_NX2_57800         CHIP_NUM_57800
 209 #endif
 210 #ifndef PCI_DEVICE_ID_NX2_57800_MF
 211 #define PCI_DEVICE_ID_NX2_57800_MF      CHIP_NUM_57800_MF
 212 #endif
 213 #ifndef PCI_DEVICE_ID_NX2_57800_VF
 214 #define PCI_DEVICE_ID_NX2_57800_VF      CHIP_NUM_57800_VF
 215 #endif
 216 #ifndef PCI_DEVICE_ID_NX2_57810
 217 #define PCI_DEVICE_ID_NX2_57810         CHIP_NUM_57810
 218 #endif
 219 #ifndef PCI_DEVICE_ID_NX2_57810_MF
 220 #define PCI_DEVICE_ID_NX2_57810_MF      CHIP_NUM_57810_MF
 221 #endif
 222 #ifndef PCI_DEVICE_ID_NX2_57840_O
 223 #define PCI_DEVICE_ID_NX2_57840_O       CHIP_NUM_57840_OBSOLETE
 224 #endif
 225 #ifndef PCI_DEVICE_ID_NX2_57810_VF
 226 #define PCI_DEVICE_ID_NX2_57810_VF      CHIP_NUM_57810_VF
 227 #endif
 228 #ifndef PCI_DEVICE_ID_NX2_57840_4_10
 229 #define PCI_DEVICE_ID_NX2_57840_4_10    CHIP_NUM_57840_4_10
 230 #endif
 231 #ifndef PCI_DEVICE_ID_NX2_57840_2_20
 232 #define PCI_DEVICE_ID_NX2_57840_2_20    CHIP_NUM_57840_2_20
 233 #endif
 234 #ifndef PCI_DEVICE_ID_NX2_57840_MFO
 235 #define PCI_DEVICE_ID_NX2_57840_MFO     CHIP_NUM_57840_MF_OBSOLETE
 236 #endif
 237 #ifndef PCI_DEVICE_ID_NX2_57840_MF
 238 #define PCI_DEVICE_ID_NX2_57840_MF      CHIP_NUM_57840_MF
 239 #endif
 240 #ifndef PCI_DEVICE_ID_NX2_57840_VF
 241 #define PCI_DEVICE_ID_NX2_57840_VF      CHIP_NUM_57840_VF
 242 #endif
 243 #ifndef PCI_DEVICE_ID_NX2_57811
 244 #define PCI_DEVICE_ID_NX2_57811         CHIP_NUM_57811
 245 #endif
 246 #ifndef PCI_DEVICE_ID_NX2_57811_MF
 247 #define PCI_DEVICE_ID_NX2_57811_MF      CHIP_NUM_57811_MF
 248 #endif
 249 #ifndef PCI_DEVICE_ID_NX2_57811_VF
 250 #define PCI_DEVICE_ID_NX2_57811_VF      CHIP_NUM_57811_VF
 251 #endif
 252
 253 static const struct pci_device_id bnx2x_pci_tbl[] = {
 254         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
 255         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
 256         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
 257         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
 258         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
 259         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF },
 260         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
 261         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
 262         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF },
 263         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
 264         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
 265         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O },
 266         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
 267         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 },
 268         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF },
 269         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO },
 270         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
 271         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
 272         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
 273         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
 274         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF },
 275         { 0 }
 276 };
 277
 278 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
 279
 280 /* Global resources for unloading a previously loaded device */
 281 #define BNX2X_PREV_WAIT_NEEDED 1
 282 static DEFINE_SEMAPHORE(bnx2x_prev_sem);
 283 static LIST_HEAD(bnx2x_prev_list);
 284
 285 /* Forward declaration */
 286 static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev);
 287 static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp);
 288 static int bnx2x_set_storm_rx_mode(struct bnx2x *bp);
 289
 290 /****************************************************************************
 291 * General service functions
 292 ****************************************************************************/
 293
 294 static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr);
 295
 296 static void __storm_memset_dma_mapping(struct bnx2x *bp,
 297                                        u32 addr, dma_addr_t mapping)
 298 {
 299         REG_WR(bp,  addr, U64_LO(mapping));
 300         REG_WR(bp,  addr + 4, U64_HI(mapping));
 301 }
 302
 303 static void storm_memset_spq_addr(struct bnx2x *bp,
 304                                   dma_addr_t mapping, u16 abs_fid)
 305 {
 306         u32 addr = XSEM_REG_FAST_MEMORY +
 307                         XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
 308
 309         __storm_memset_dma_mapping(bp, addr, mapping);
 310 }
 311
 312 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
 313                                   u16 pf_id)
 314 {
 315         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
 316                 pf_id);
 317         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
 318                 pf_id);
 319         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
 320                 pf_id);
 321         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
 322                 pf_id);
 323 }
 324
 325 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
 326                                  u8 enable)
 327 {
 328         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
 329                 enable);
 330         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
 331                 enable);
 332         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
 333                 enable);
 334         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
 335                 enable);
 336 }
 337
 338 static void storm_memset_eq_data(struct bnx2x *bp,
 339                                  struct event_ring_data *eq_data,
 340                                 u16 pfid)
 341 {
 342         size_t size = sizeof(struct event_ring_data);
 343
 344         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
 345
 346         __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
 347 }
 348
 349 static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
 350                                  u16 pfid)
 351 {
 352         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
 353         REG_WR16(bp, addr, eq_prod);
 354 }
 355
 356 /* used only at init
 357  * locking is done by mcp
 358  */
 359 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
 360 {
 361         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
 362         pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
 363         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
 364                                PCICFG_VENDOR_ID_OFFSET);
 365 }
 366
 367 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
 368 {
 369         u32 val;
 370
 371         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
 372         pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
 373         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
 374                                PCICFG_VENDOR_ID_OFFSET);
 375
 376         return val;
 377 }
 378
 379 #define DMAE_DP_SRC_GRC         "grc src_addr [%08x]"
 380 #define DMAE_DP_SRC_PCI         "pci src_addr [%x:%08x]"
 381 #define DMAE_DP_DST_GRC         "grc dst_addr [%08x]"
 382 #define DMAE_DP_DST_PCI         "pci dst_addr [%x:%08x]"
 383 #define DMAE_DP_DST_NONE        "dst_addr [none]"
 384
 385 static void bnx2x_dp_dmae(struct bnx2x *bp,
 386                           struct dmae_command *dmae, int msglvl)
 387 {
 388         u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
 389         int i;
 390
 391         switch (dmae->opcode & DMAE_COMMAND_DST) {
 392         case DMAE_CMD_DST_PCI:
 393                 if (src_type == DMAE_CMD_SRC_PCI)
 394                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 395                            "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
 396                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 397                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 398                            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
 399                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 400                            dmae->comp_val);
 401                 else
 402                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 403                            "src [%08x], len [%d*4], dst [%x:%08x]\n"
 404                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 405                            dmae->opcode, dmae->src_addr_lo >> 2,
 406                            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
 407                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 408                            dmae->comp_val);
 409                 break;
 410         case DMAE_CMD_DST_GRC:
 411                 if (src_type == DMAE_CMD_SRC_PCI)
 412                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 413                            "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
 414                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 415                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 416                            dmae->len, dmae->dst_addr_lo >> 2,
 417                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 418                            dmae->comp_val);
 419                 else
 420                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 421                            "src [%08x], len [%d*4], dst [%08x]\n"
 422                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 423                            dmae->opcode, dmae->src_addr_lo >> 2,
 424                            dmae->len, dmae->dst_addr_lo >> 2,
 425                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 426                            dmae->comp_val);
 427                 break;
 428         default:
 429                 if (src_type == DMAE_CMD_SRC_PCI)
 430                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 431                            "src_addr [%x:%08x]  len [%d * 4]  dst_addr [none]\n"
 432                            "comp_addr [%x:%08x]  comp_val 0x%08x\n",
 433                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 434                            dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
 435                            dmae->comp_val);
 436                 else
 437                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 438                            "src_addr [%08x]  len [%d * 4]  dst_addr [none]\n"
 439                            "comp_addr [%x:%08x]  comp_val 0x%08x\n",
 440                            dmae->opcode, dmae->src_addr_lo >> 2,
 441                            dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
 442                            dmae->comp_val);
 443                 break;
 444         }
 445
 446         for (i = 0; i < (sizeof(struct dmae_command)/4); i++)
 447                 DP(msglvl, "DMAE RAW [%02d]: 0x%08x\n",
 448                    i, *(((u32 *)dmae) + i));
 449 }
 450
 451 /* copy command into DMAE command memory and set DMAE command go */
 452 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
 453 {
 454         u32 cmd_offset;
 455         int i;
 456
 457         cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
 458         for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
 459                 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
 460         }
 461         REG_WR(bp, dmae_reg_go_c[idx], 1);
 462 }
 463
 464 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
 465 {
 466         return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
 467                            DMAE_CMD_C_ENABLE);
 468 }
 469
 470 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
 471 {
 472         return opcode & ~DMAE_CMD_SRC_RESET;
 473 }
 474
 475 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
 476                              bool with_comp, u8 comp_type)
 477 {
 478         u32 opcode = 0;
 479
 480         opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
 481                    (dst_type << DMAE_COMMAND_DST_SHIFT));
 482
 483         opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
 484
 485         opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
 486         opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
 487                    (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
 488         opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
 489
 490 #ifdef __BIG_ENDIAN
 491         opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
 492 #else
 493         opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
 494 #endif
 495         if (with_comp)
 496                 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
 497         return opcode;
 498 }
 499
 500 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
 501                                       struct dmae_command *dmae,
 502                                       u8 src_type, u8 dst_type)
 503 {
 504         memset(dmae, 0, sizeof(struct dmae_command));
 505
 506         /* set the opcode */
 507         dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
 508                                          true, DMAE_COMP_PCI);
 509
 510         /* fill in the completion parameters */
 511         dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
 512         dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
 513         dmae->comp_val = DMAE_COMP_VAL;
 514 }
 515
 516 /* issue a dmae command over the init-channel and wait for completion */
 517 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
 518                                u32 *comp)
 519 {
 520         int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
 521         int rc = 0;
 522
 523         bnx2x_dp_dmae(bp, dmae, BNX2X_MSG_DMAE);
 524
 525         /* Lock the dmae channel. Disable BHs to prevent a dead-lock
 526          * as long as this code is called both from syscall context and
 527          * from ndo_set_rx_mode() flow that may be called from BH.
 528          */
 529
 530         spin_lock_bh(&bp->dmae_lock);
 531
 532         /* reset completion */
 533         *comp = 0;
 534
 535         /* post the command on the channel used for initializations */
 536         bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
 537
 538         /* wait for completion */
 539         udelay(5);
 540         while ((*comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
 541
 542                 if (!cnt ||
 543                     (bp->recovery_state != BNX2X_RECOVERY_DONE &&
 544                      bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
 545                         BNX2X_ERR("DMAE timeout!\n");
 546                         rc = DMAE_TIMEOUT;
 547                         goto unlock;
 548                 }
 549                 cnt--;
 550                 udelay(50);
 551         }
 552         if (*comp & DMAE_PCI_ERR_FLAG) {
 553                 BNX2X_ERR("DMAE PCI error!\n");
 554                 rc = DMAE_PCI_ERROR;
 555         }
 556
 557 unlock:
 558
 559         spin_unlock_bh(&bp->dmae_lock);
 560
 561         return rc;
 562 }
 563
 564 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
 565                       u32 len32)
 566 {
 567         int rc;
 568         struct dmae_command dmae;
 569
 570         if (!bp->dmae_ready) {
 571                 u32 *data = bnx2x_sp(bp, wb_data[0]);
 572
 573                 if (CHIP_IS_E1(bp))
 574                         bnx2x_init_ind_wr(bp, dst_addr, data, len32);
 575                 else
 576                         bnx2x_init_str_wr(bp, dst_addr, data, len32);
 577                 return;
 578         }
 579
 580         /* set opcode and fixed command fields */
 581         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
 582
 583         /* fill in addresses and len */
 584         dmae.src_addr_lo = U64_LO(dma_addr);
 585         dmae.src_addr_hi = U64_HI(dma_addr);
 586         dmae.dst_addr_lo = dst_addr >> 2;
 587         dmae.dst_addr_hi = 0;
 588         dmae.len = len32;
 589
 590         /* issue the command and wait for completion */
 591         rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
 592         if (rc) {
 593                 BNX2X_ERR("DMAE returned failure %d\n", rc);
 594 #ifdef BNX2X_STOP_ON_ERROR
 595                 bnx2x_panic();
 596 #endif
 597         }
 598 }
 599
 600 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
 601 {
 602         int rc;
 603         struct dmae_command dmae;
 604
 605         if (!bp->dmae_ready) {
 606                 u32 *data = bnx2x_sp(bp, wb_data[0]);
 607                 int i;
 608
 609                 if (CHIP_IS_E1(bp))
 610                         for (i = 0; i < len32; i++)
 611                                 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
 612                 else
 613                         for (i = 0; i < len32; i++)
 614                                 data[i] = REG_RD(bp, src_addr + i*4);
 615
 616                 return;
 617         }
 618
 619         /* set opcode and fixed command fields */
 620         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
 621
 622         /* fill in addresses and len */
 623         dmae.src_addr_lo = src_addr >> 2;
 624         dmae.src_addr_hi = 0;
 625         dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
 626         dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
 627         dmae.len = len32;
 628
 629         /* issue the command and wait for completion */
 630         rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
 631         if (rc) {
 632                 BNX2X_ERR("DMAE returned failure %d\n", rc);
 633 #ifdef BNX2X_STOP_ON_ERROR
 634                 bnx2x_panic();
 635 #endif
 636         }
 637 }
 638
 639 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
 640                                       u32 addr, u32 len)
 641 {
 642         int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
 643         int offset = 0;
 644
 645         while (len > dmae_wr_max) {
 646                 bnx2x_write_dmae(bp, phys_addr + offset,
 647                                  addr + offset, dmae_wr_max);
 648                 offset += dmae_wr_max * 4;
 649                 len -= dmae_wr_max;
 650         }
 651
 652         bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
 653 }
 654
 655 enum storms {
 656            XSTORM,
 657            TSTORM,
 658            CSTORM,
 659            USTORM,
 660            MAX_STORMS
 661 };
 662
 663 #define STORMS_NUM 4
 664 #define REGS_IN_ENTRY 4
 665
 666 static inline int bnx2x_get_assert_list_entry(struct bnx2x *bp,
 667                                               enum storms storm,
 668                                               int entry)
 669 {
 670         switch (storm) {
 671         case XSTORM:
 672                 return XSTORM_ASSERT_LIST_OFFSET(entry);
 673         case TSTORM:
 674                 return TSTORM_ASSERT_LIST_OFFSET(entry);
 675         case CSTORM:
 676                 return CSTORM_ASSERT_LIST_OFFSET(entry);
 677         case USTORM:
 678                 return USTORM_ASSERT_LIST_OFFSET(entry);
 679         case MAX_STORMS:
 680         default:
 681                 BNX2X_ERR("unknown storm\n");
 682         }
 683         return -EINVAL;
 684 }
 685
 686 static int bnx2x_mc_assert(struct bnx2x *bp)
 687 {
 688         char last_idx;
 689         int i, j, rc = 0;
 690         enum storms storm;
 691         u32 regs[REGS_IN_ENTRY];
 692         u32 bar_storm_intmem[STORMS_NUM] = {
 693                 BAR_XSTRORM_INTMEM,
 694                 BAR_TSTRORM_INTMEM,
 695                 BAR_CSTRORM_INTMEM,
 696                 BAR_USTRORM_INTMEM
 697         };
 698         u32 storm_assert_list_index[STORMS_NUM] = {
 699                 XSTORM_ASSERT_LIST_INDEX_OFFSET,
 700                 TSTORM_ASSERT_LIST_INDEX_OFFSET,
 701                 CSTORM_ASSERT_LIST_INDEX_OFFSET,
 702                 USTORM_ASSERT_LIST_INDEX_OFFSET
 703         };
 704         char *storms_string[STORMS_NUM] = {
 705                 "XSTORM",
 706                 "TSTORM",
 707                 "CSTORM",
 708                 "USTORM"
 709         };
 710
 711         for (storm = XSTORM; storm < MAX_STORMS; storm++) {
 712                 last_idx = REG_RD8(bp, bar_storm_intmem[storm] +
 713                                    storm_assert_list_index[storm]);
 714                 if (last_idx)
 715                         BNX2X_ERR("%s_ASSERT_LIST_INDEX 0x%x\n",
 716                                   storms_string[storm], last_idx);
 717
 718                 /* print the asserts */
 719                 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 720                         /* read a single assert entry */
 721                         for (j = 0; j < REGS_IN_ENTRY; j++)
 722                                 regs[j] = REG_RD(bp, bar_storm_intmem[storm] +
 723                                           bnx2x_get_assert_list_entry(bp,
 724                                                                       storm,
 725                                                                       i) +
 726                                           sizeof(u32) * j);
 727
 728                         /* log entry if it contains a valid assert */
 729                         if (regs[0] != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 730                                 BNX2X_ERR("%s_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
 731                                           storms_string[storm], i, regs[3],
 732                                           regs[2], regs[1], regs[0]);
 733                                 rc++;
 734                         } else {
 735                                 break;
 736                         }
 737                 }
 738         }
 739
 740         BNX2X_ERR("Chip Revision: %s, FW Version: %d_%d_%d\n",
 741                   CHIP_IS_E1(bp) ? "everest1" :
 742                   CHIP_IS_E1H(bp) ? "everest1h" :
 743                   CHIP_IS_E2(bp) ? "everest2" : "everest3",
 744                   BCM_5710_FW_MAJOR_VERSION,
 745                   BCM_5710_FW_MINOR_VERSION,
 746                   BCM_5710_FW_REVISION_VERSION);
 747
 748         return rc;
 749 }
 750
 751 #define MCPR_TRACE_BUFFER_SIZE  (0x800)
 752 #define SCRATCH_BUFFER_SIZE(bp) \
 753         (CHIP_IS_E1(bp) ? 0x10000 : (CHIP_IS_E1H(bp) ? 0x20000 : 0x28000))
 754
 755 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
 756 {
 757         u32 addr, val;
 758         u32 mark, offset;
 759         __be32 data[9];
 760         int word;
 761         u32 trace_shmem_base;
 762         if (BP_NOMCP(bp)) {
 763                 BNX2X_ERR("NO MCP - can not dump\n");
 764                 return;
 765         }
 766         netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
 767                 (bp->common.bc_ver & 0xff0000) >> 16,
 768                 (bp->common.bc_ver & 0xff00) >> 8,
 769                 (bp->common.bc_ver & 0xff));
 770
 771         val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
 772         if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
 773                 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
 774
 775         if (BP_PATH(bp) == 0)
 776                 trace_shmem_base = bp->common.shmem_base;
 777         else
 778                 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
 779
 780         /* sanity */
 781         if (trace_shmem_base < MCPR_SCRATCH_BASE(bp) + MCPR_TRACE_BUFFER_SIZE ||
 782             trace_shmem_base >= MCPR_SCRATCH_BASE(bp) +
 783                                 SCRATCH_BUFFER_SIZE(bp)) {
 784                 BNX2X_ERR("Unable to dump trace buffer (mark %x)\n",
 785                           trace_shmem_base);
 786                 return;
 787         }
 788
 789         addr = trace_shmem_base - MCPR_TRACE_BUFFER_SIZE;
 790
 791         /* validate TRCB signature */
 792         mark = REG_RD(bp, addr);
 793         if (mark != MFW_TRACE_SIGNATURE) {
 794                 BNX2X_ERR("Trace buffer signature is missing.");
 795                 return ;
 796         }
 797
 798         /* read cyclic buffer pointer */
 799         addr += 4;
 800         mark = REG_RD(bp, addr);
 801         mark = MCPR_SCRATCH_BASE(bp) + ((mark + 0x3) & ~0x3) - 0x08000000;
 802         if (mark >= trace_shmem_base || mark < addr + 4) {
 803                 BNX2X_ERR("Mark doesn't fall inside Trace Buffer\n");
 804                 return;
 805         }
 806         printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
 807
 808         printk("%s", lvl);
 809
 810         /* dump buffer after the mark */
 811         for (offset = mark; offset < trace_shmem_base; offset += 0x8*4) {
 812                 for (word = 0; word < 8; word++)
 813                         data[word] = htonl(REG_RD(bp, offset + 4*word));
 814                 data[8] = 0x0;
 815                 pr_cont("%s", (char *)data);
 816         }
 817
 818         /* dump buffer before the mark */
 819         for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
 820                 for (word = 0; word < 8; word++)
 821                         data[word] = htonl(REG_RD(bp, offset + 4*word));
 822                 data[8] = 0x0;
 823                 pr_cont("%s", (char *)data);
 824         }
 825         printk("%s" "end of fw dump\n", lvl);
 826 }
 827
 828 static void bnx2x_fw_dump(struct bnx2x *bp)
 829 {
 830         bnx2x_fw_dump_lvl(bp, KERN_ERR);
 831 }
 832
 833 static void bnx2x_hc_int_disable(struct bnx2x *bp)
 834 {
 835         int port = BP_PORT(bp);
 836         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
 837         u32 val = REG_RD(bp, addr);
 838
 839         /* in E1 we must use only PCI configuration space to disable
 840          * MSI/MSIX capability
 841          * It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
 842          */
 843         if (CHIP_IS_E1(bp)) {
 844                 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
 845                  * Use mask register to prevent from HC sending interrupts
 846                  * after we exit the function
 847                  */
 848                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
 849
 850                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
 851                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
 852                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
 853         } else
 854                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
 855                          HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
 856                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
 857                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
 858
 859         DP(NETIF_MSG_IFDOWN,
 860            "write %x to HC %d (addr 0x%x)\n",
 861            val, port, addr);
 862
 863         /* flush all outstanding writes */
 864         mmiowb();
 865
 866         REG_WR(bp, addr, val);
 867         if (REG_RD(bp, addr) != val)
 868                 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
 869 }
 870
 871 static void bnx2x_igu_int_disable(struct bnx2x *bp)
 872 {
 873         u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
 874
 875         val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
 876                  IGU_PF_CONF_INT_LINE_EN |
 877                  IGU_PF_CONF_ATTN_BIT_EN);
 878
 879         DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
 880
 881         /* flush all outstanding writes */
 882         mmiowb();
 883
 884         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
 885         if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
 886                 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
 887 }
 888
 889 static void bnx2x_int_disable(struct bnx2x *bp)
 890 {
 891         if (bp->common.int_block == INT_BLOCK_HC)
 892                 bnx2x_hc_int_disable(bp);
 893         else
 894                 bnx2x_igu_int_disable(bp);
 895 }
 896
 897 void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int)
 898 {
 899         int i;
 900         u16 j;
 901         struct hc_sp_status_block_data sp_sb_data;
 902         int func = BP_FUNC(bp);
 903 #ifdef BNX2X_STOP_ON_ERROR
 904         u16 start = 0, end = 0;
 905         u8 cos;
 906 #endif
 907         if (IS_PF(bp) && disable_int)
 908                 bnx2x_int_disable(bp);
 909
 910         bp->stats_state = STATS_STATE_DISABLED;
 911         bp->eth_stats.unrecoverable_error++;
 912         DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
 913
 914         BNX2X_ERR("begin crash dump -----------------\n");
 915
 916         /* Indices */
 917         /* Common */
 918         if (IS_PF(bp)) {
 919                 struct host_sp_status_block *def_sb = bp->def_status_blk;
 920                 int data_size, cstorm_offset;
 921
 922                 BNX2X_ERR("def_idx(0x%x)  def_att_idx(0x%x)  attn_state(0x%x)  spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
 923                           bp->def_idx, bp->def_att_idx, bp->attn_state,
 924                           bp->spq_prod_idx, bp->stats_counter);
 925                 BNX2X_ERR("DSB: attn bits(0x%x)  ack(0x%x)  id(0x%x)  idx(0x%x)\n",
 926                           def_sb->atten_status_block.attn_bits,
 927                           def_sb->atten_status_block.attn_bits_ack,
 928                           def_sb->atten_status_block.status_block_id,
 929                           def_sb->atten_status_block.attn_bits_index);
 930                 BNX2X_ERR("     def (");
 931                 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
 932                         pr_cont("0x%x%s",
 933                                 def_sb->sp_sb.index_values[i],
 934                                 (i == HC_SP_SB_MAX_INDICES - 1) ? ")  " : " ");
 935
 936                 data_size = sizeof(struct hc_sp_status_block_data) /
 937                             sizeof(u32);
 938                 cstorm_offset = CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func);
 939                 for (i = 0; i < data_size; i++)
 940                         *((u32 *)&sp_sb_data + i) =
 941                                 REG_RD(bp, BAR_CSTRORM_INTMEM + cstorm_offset +
 942                                            i * sizeof(u32));
 943
 944                 pr_cont("igu_sb_id(0x%x)  igu_seg_id(0x%x) pf_id(0x%x)  vnic_id(0x%x)  vf_id(0x%x)  vf_valid (0x%x) state(0x%x)\n",
 945                         sp_sb_data.igu_sb_id,
 946                         sp_sb_data.igu_seg_id,
 947                         sp_sb_data.p_func.pf_id,
 948                         sp_sb_data.p_func.vnic_id,
 949                         sp_sb_data.p_func.vf_id,
 950                         sp_sb_data.p_func.vf_valid,
 951                         sp_sb_data.state);
 952         }
 953
 954         for_each_eth_queue(bp, i) {
 955                 struct bnx2x_fastpath *fp = &bp->fp[i];
 956                 int loop;
 957                 struct hc_status_block_data_e2 sb_data_e2;
 958                 struct hc_status_block_data_e1x sb_data_e1x;
 959                 struct hc_status_block_sm  *hc_sm_p =
 960                         CHIP_IS_E1x(bp) ?
 961                         sb_data_e1x.common.state_machine :
 962                         sb_data_e2.common.state_machine;
 963                 struct hc_index_data *hc_index_p =
 964                         CHIP_IS_E1x(bp) ?
 965                         sb_data_e1x.index_data :
 966                         sb_data_e2.index_data;
 967                 u8 data_size, cos;
 968                 u32 *sb_data_p;
 969                 struct bnx2x_fp_txdata txdata;
 970
 971                 if (!bp->fp)
 972                         break;
 973
 974                 if (!fp->rx_cons_sb)
 975                         continue;
 976
 977                 /* Rx */
 978                 BNX2X_ERR("fp%d: rx_bd_prod(0x%x)  rx_bd_cons(0x%x)  rx_comp_prod(0x%x)  rx_comp_cons(0x%x)  *rx_cons_sb(0x%x)\n",
 979                           i, fp->rx_bd_prod, fp->rx_bd_cons,
 980                           fp->rx_comp_prod,
 981                           fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
 982                 BNX2X_ERR("     rx_sge_prod(0x%x)  last_max_sge(0x%x)  fp_hc_idx(0x%x)\n",
 983                           fp->rx_sge_prod, fp->last_max_sge,
 984                           le16_to_cpu(fp->fp_hc_idx));
 985
 986                 /* Tx */
 987                 for_each_cos_in_tx_queue(fp, cos)
 988                 {
 989                         if (!fp->txdata_ptr[cos])
 990                                 break;
 991
 992                         txdata = *fp->txdata_ptr[cos];
 993
 994                         if (!txdata.tx_cons_sb)
 995                                 continue;
 996
 997                         BNX2X_ERR("fp%d: tx_pkt_prod(0x%x)  tx_pkt_cons(0x%x)  tx_bd_prod(0x%x)  tx_bd_cons(0x%x)  *tx_cons_sb(0x%x)\n",
 998                                   i, txdata.tx_pkt_prod,
 999                                   txdata.tx_pkt_cons, txdata.tx_bd_prod,
1000                                   txdata.tx_bd_cons,
1001                                   le16_to_cpu(*txdata.tx_cons_sb));
1002                 }
1003
1004                 loop = CHIP_IS_E1x(bp) ?
1005                         HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
1006
1007                 /* host sb data */
1008
1009                 if (IS_FCOE_FP(fp))
1010                         continue;
1011
1012                 BNX2X_ERR("     run indexes (");
1013                 for (j = 0; j < HC_SB_MAX_SM; j++)
1014                         pr_cont("0x%x%s",
1015                                fp->sb_running_index[j],
1016                                (j == HC_SB_MAX_SM - 1) ? ")" : " ");
1017
1018                 BNX2X_ERR("     indexes (");
1019                 for (j = 0; j < loop; j++)
1020                         pr_cont("0x%x%s",
1021                                fp->sb_index_values[j],
1022                                (j == loop - 1) ? ")" : " ");
1023
1024                 /* VF cannot access FW refelection for status block */
1025                 if (IS_VF(bp))
1026                         continue;
1027
1028                 /* fw sb data */
1029                 data_size = CHIP_IS_E1x(bp) ?
1030                         sizeof(struct hc_status_block_data_e1x) :
1031                         sizeof(struct hc_status_block_data_e2);
1032                 data_size /= sizeof(u32);
1033                 sb_data_p = CHIP_IS_E1x(bp) ?
1034                         (u32 *)&sb_data_e1x :
1035                         (u32 *)&sb_data_e2;
1036                 /* copy sb data in here */
1037                 for (j = 0; j < data_size; j++)
1038                         *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
1039                                 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
1040                                 j * sizeof(u32));
1041
1042                 if (!CHIP_IS_E1x(bp)) {
1043                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
1044                                 sb_data_e2.common.p_func.pf_id,
1045                                 sb_data_e2.common.p_func.vf_id,
1046                                 sb_data_e2.common.p_func.vf_valid,
1047                                 sb_data_e2.common.p_func.vnic_id,
1048                                 sb_data_e2.common.same_igu_sb_1b,
1049                                 sb_data_e2.common.state);
1050                 } else {
1051                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
1052                                 sb_data_e1x.common.p_func.pf_id,
1053                                 sb_data_e1x.common.p_func.vf_id,
1054                                 sb_data_e1x.common.p_func.vf_valid,
1055                                 sb_data_e1x.common.p_func.vnic_id,
1056                                 sb_data_e1x.common.same_igu_sb_1b,
1057                                 sb_data_e1x.common.state);
1058                 }
1059
1060                 /* SB_SMs data */
1061                 for (j = 0; j < HC_SB_MAX_SM; j++) {
1062                         pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x)  igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
1063                                 j, hc_sm_p[j].__flags,
1064                                 hc_sm_p[j].igu_sb_id,
1065                                 hc_sm_p[j].igu_seg_id,
1066                                 hc_sm_p[j].time_to_expire,
1067                                 hc_sm_p[j].timer_value);
1068                 }
1069
1070                 /* Indices data */
1071                 for (j = 0; j < loop; j++) {
1072                         pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
1073                                hc_index_p[j].flags,
1074                                hc_index_p[j].timeout);
1075                 }
1076         }
1077
1078 #ifdef BNX2X_STOP_ON_ERROR
1079         if (IS_PF(bp)) {
1080                 /* event queue */
1081                 BNX2X_ERR("eq cons %x prod %x\n", bp->eq_cons, bp->eq_prod);
1082                 for (i = 0; i < NUM_EQ_DESC; i++) {
1083                         u32 *data = (u32 *)&bp->eq_ring[i].message.data;
1084
1085                         BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n",
1086                                   i, bp->eq_ring[i].message.opcode,
1087                                   bp->eq_ring[i].message.error);
1088                         BNX2X_ERR("data: %x %x %x\n",
1089                                   data[0], data[1], data[2]);
1090                 }
1091         }
1092
1093         /* Rings */
1094         /* Rx */
1095         for_each_valid_rx_queue(bp, i) {
1096                 struct bnx2x_fastpath *fp = &bp->fp[i];
1097
1098                 if (!bp->fp)
1099                         break;
1100
1101                 if (!fp->rx_cons_sb)
1102                         continue;
1103
1104                 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
1105                 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
1106                 for (j = start; j != end; j = RX_BD(j + 1)) {
1107                         u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
1108                         struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
1109
1110                         BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x]  sw_bd=[%p]\n",
1111                                   i, j, rx_bd[1], rx_bd[0], sw_bd->data);
1112                 }
1113
1114                 start = RX_SGE(fp->rx_sge_prod);
1115                 end = RX_SGE(fp->last_max_sge);
1116                 for (j = start; j != end; j = RX_SGE(j + 1)) {
1117                         u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
1118                         struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
1119
1120                         BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x]  sw_page=[%p]\n",
1121                                   i, j, rx_sge[1], rx_sge[0], sw_page->page);
1122                 }
1123
1124                 start = RCQ_BD(fp->rx_comp_cons - 10);
1125                 end = RCQ_BD(fp->rx_comp_cons + 503);
1126                 for (j = start; j != end; j = RCQ_BD(j + 1)) {
1127                         u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
1128
1129                         BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1130                                   i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
1131                 }
1132         }
1133
1134         /* Tx */
1135         for_each_valid_tx_queue(bp, i) {
1136                 struct bnx2x_fastpath *fp = &bp->fp[i];
1137
1138                 if (!bp->fp)
1139                         break;
1140
1141                 for_each_cos_in_tx_queue(fp, cos) {
1142                         struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
1143
1144                         if (!fp->txdata_ptr[cos])
1145                                 break;
1146
1147                         if (!txdata->tx_cons_sb)
1148                                 continue;
1149
1150                         start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
1151                         end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
1152                         for (j = start; j != end; j = TX_BD(j + 1)) {
1153                                 struct sw_tx_bd *sw_bd =
1154                                         &txdata->tx_buf_ring[j];
1155
1156                                 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
1157                                           i, cos, j, sw_bd->skb,
1158                                           sw_bd->first_bd);
1159                         }
1160
1161                         start = TX_BD(txdata->tx_bd_cons - 10);
1162                         end = TX_BD(txdata->tx_bd_cons + 254);
1163                         for (j = start; j != end; j = TX_BD(j + 1)) {
1164                                 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
1165
1166                                 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
1167                                           i, cos, j, tx_bd[0], tx_bd[1],
1168                                           tx_bd[2], tx_bd[3]);
1169                         }
1170                 }
1171         }
1172 #endif
1173         if (IS_PF(bp)) {
1174                 bnx2x_fw_dump(bp);
1175                 bnx2x_mc_assert(bp);
1176         }
1177         BNX2X_ERR("end crash dump -----------------\n");
1178 }
1179
1180 /*
1181  * FLR Support for E2
1182  *
1183  * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1184  * initialization.
1185  */
1186 #define FLR_WAIT_USEC           10000   /* 10 milliseconds */
1187 #define FLR_WAIT_INTERVAL       50      /* usec */
1188 #define FLR_POLL_CNT            (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
1189
1190 struct pbf_pN_buf_regs {
1191         int pN;
1192         u32 init_crd;
1193         u32 crd;
1194         u32 crd_freed;
1195 };
1196
1197 struct pbf_pN_cmd_regs {
1198         int pN;
1199         u32 lines_occup;
1200         u32 lines_freed;
1201 };
1202
1203 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1204                                      struct pbf_pN_buf_regs *regs,
1205                                      u32 poll_count)
1206 {
1207         u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1208         u32 cur_cnt = poll_count;
1209
1210         crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1211         crd = crd_start = REG_RD(bp, regs->crd);
1212         init_crd = REG_RD(bp, regs->init_crd);
1213
1214         DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1215         DP(BNX2X_MSG_SP, "CREDIT[%d]      : s:%x\n", regs->pN, crd);
1216         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1217
1218         while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1219                (init_crd - crd_start))) {
1220                 if (cur_cnt--) {
1221                         udelay(FLR_WAIT_INTERVAL);
1222                         crd = REG_RD(bp, regs->crd);
1223                         crd_freed = REG_RD(bp, regs->crd_freed);
1224                 } else {
1225                         DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1226                            regs->pN);
1227                         DP(BNX2X_MSG_SP, "CREDIT[%d]      : c:%x\n",
1228                            regs->pN, crd);
1229                         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1230                            regs->pN, crd_freed);
1231                         break;
1232                 }
1233         }
1234         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1235            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1236 }
1237
1238 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1239                                      struct pbf_pN_cmd_regs *regs,
1240                                      u32 poll_count)
1241 {
1242         u32 occup, to_free, freed, freed_start;
1243         u32 cur_cnt = poll_count;
1244
1245         occup = to_free = REG_RD(bp, regs->lines_occup);
1246         freed = freed_start = REG_RD(bp, regs->lines_freed);
1247
1248         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n", regs->pN, occup);
1249         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1250
1251         while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1252                 if (cur_cnt--) {
1253                         udelay(FLR_WAIT_INTERVAL);
1254                         occup = REG_RD(bp, regs->lines_occup);
1255                         freed = REG_RD(bp, regs->lines_freed);
1256                 } else {
1257                         DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1258                            regs->pN);
1259                         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n",
1260                            regs->pN, occup);
1261                         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1262                            regs->pN, freed);
1263                         break;
1264                 }
1265         }
1266         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1267            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1268 }
1269
1270 static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1271                                     u32 expected, u32 poll_count)
1272 {
1273         u32 cur_cnt = poll_count;
1274         u32 val;
1275
1276         while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1277                 udelay(FLR_WAIT_INTERVAL);
1278
1279         return val;
1280 }
1281
1282 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1283                                     char *msg, u32 poll_cnt)
1284 {
1285         u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1286         if (val != 0) {
1287                 BNX2X_ERR("%s usage count=%d\n", msg, val);
1288                 return 1;
1289         }
1290         return 0;
1291 }
1292
1293 /* Common routines with VF FLR cleanup */
1294 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1295 {
1296         /* adjust polling timeout */
1297         if (CHIP_REV_IS_EMUL(bp))
1298                 return FLR_POLL_CNT * 2000;
1299
1300         if (CHIP_REV_IS_FPGA(bp))
1301                 return FLR_POLL_CNT * 120;
1302
1303         return FLR_POLL_CNT;
1304 }
1305
1306 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1307 {
1308         struct pbf_pN_cmd_regs cmd_regs[] = {
1309                 {0, (CHIP_IS_E3B0(bp)) ?
1310                         PBF_REG_TQ_OCCUPANCY_Q0 :
1311                         PBF_REG_P0_TQ_OCCUPANCY,
1312                     (CHIP_IS_E3B0(bp)) ?
1313                         PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1314                         PBF_REG_P0_TQ_LINES_FREED_CNT},
1315                 {1, (CHIP_IS_E3B0(bp)) ?
1316                         PBF_REG_TQ_OCCUPANCY_Q1 :
1317                         PBF_REG_P1_TQ_OCCUPANCY,
1318                     (CHIP_IS_E3B0(bp)) ?
1319                         PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1320                         PBF_REG_P1_TQ_LINES_FREED_CNT},
1321                 {4, (CHIP_IS_E3B0(bp)) ?
1322                         PBF_REG_TQ_OCCUPANCY_LB_Q :
1323                         PBF_REG_P4_TQ_OCCUPANCY,
1324                     (CHIP_IS_E3B0(bp)) ?
1325                         PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1326                         PBF_REG_P4_TQ_LINES_FREED_CNT}
1327         };
1328
1329         struct pbf_pN_buf_regs buf_regs[] = {
1330                 {0, (CHIP_IS_E3B0(bp)) ?
1331                         PBF_REG_INIT_CRD_Q0 :
1332                         PBF_REG_P0_INIT_CRD ,
1333                     (CHIP_IS_E3B0(bp)) ?
1334                         PBF_REG_CREDIT_Q0 :
1335                         PBF_REG_P0_CREDIT,
1336                     (CHIP_IS_E3B0(bp)) ?
1337                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1338                         PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1339                 {1, (CHIP_IS_E3B0(bp)) ?
1340                         PBF_REG_INIT_CRD_Q1 :
1341                         PBF_REG_P1_INIT_CRD,
1342                     (CHIP_IS_E3B0(bp)) ?
1343                         PBF_REG_CREDIT_Q1 :
1344                         PBF_REG_P1_CREDIT,
1345                     (CHIP_IS_E3B0(bp)) ?
1346                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1347                         PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1348                 {4, (CHIP_IS_E3B0(bp)) ?
1349                         PBF_REG_INIT_CRD_LB_Q :
1350                         PBF_REG_P4_INIT_CRD,
1351                     (CHIP_IS_E3B0(bp)) ?
1352                         PBF_REG_CREDIT_LB_Q :
1353                         PBF_REG_P4_CREDIT,
1354                     (CHIP_IS_E3B0(bp)) ?
1355                         PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1356                         PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1357         };
1358
1359         int i;
1360
1361         /* Verify the command queues are flushed P0, P1, P4 */
1362         for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1363                 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1364
1365         /* Verify the transmission buffers are flushed P0, P1, P4 */
1366         for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1367                 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1368 }
1369
1370 #define OP_GEN_PARAM(param) \
1371         (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1372
1373 #define OP_GEN_TYPE(type) \
1374         (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1375
1376 #define OP_GEN_AGG_VECT(index) \
1377         (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1378
1379 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt)
1380 {
1381         u32 op_gen_command = 0;
1382         u32 comp_addr = BAR_CSTRORM_INTMEM +
1383                         CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1384         int ret = 0;
1385
1386         if (REG_RD(bp, comp_addr)) {
1387                 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
1388                 return 1;
1389         }
1390
1391         op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1392         op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1393         op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
1394         op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1395
1396         DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
1397         REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command);
1398
1399         if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1400                 BNX2X_ERR("FW final cleanup did not succeed\n");
1401                 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1402                    (REG_RD(bp, comp_addr)));
1403                 bnx2x_panic();
1404                 return 1;
1405         }
1406         /* Zero completion for next FLR */
1407         REG_WR(bp, comp_addr, 0);
1408
1409         return ret;
1410 }
1411
1412 u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1413 {
1414         u16 status;
1415
1416         pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
1417         return status & PCI_EXP_DEVSTA_TRPND;
1418 }
1419
1420 /* PF FLR specific routines
1421 */
1422 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1423 {
1424         /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1425         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1426                         CFC_REG_NUM_LCIDS_INSIDE_PF,
1427                         "CFC PF usage counter timed out",
1428                         poll_cnt))
1429                 return 1;
1430
1431         /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1432         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1433                         DORQ_REG_PF_USAGE_CNT,
1434                         "DQ PF usage counter timed out",
1435                         poll_cnt))
1436                 return 1;
1437
1438         /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1439         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1440                         QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1441                         "QM PF usage counter timed out",
1442                         poll_cnt))
1443                 return 1;
1444
1445         /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1446         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1447                         TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1448                         "Timers VNIC usage counter timed out",
1449                         poll_cnt))
1450                 return 1;
1451         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1452                         TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1453                         "Timers NUM_SCANS usage counter timed out",
1454                         poll_cnt))
1455                 return 1;
1456
1457         /* Wait DMAE PF usage counter to zero */
1458         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1459                         dmae_reg_go_c[INIT_DMAE_C(bp)],
1460                         "DMAE command register timed out",
1461                         poll_cnt))
1462                 return 1;
1463
1464         return 0;
1465 }
1466
1467 static void bnx2x_hw_enable_status(struct bnx2x *bp)
1468 {
1469         u32 val;
1470
1471         val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1472         DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1473
1474         val = REG_RD(bp, PBF_REG_DISABLE_PF);
1475         DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1476
1477         val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1478         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1479
1480         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1481         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1482
1483         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1484         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1485
1486         val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1487         DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1488
1489         val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1490         DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1491
1492         val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1493         DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1494            val);
1495 }
1496
1497 static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1498 {
1499         u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1500
1501         DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1502
1503         /* Re-enable PF target read access */
1504         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1505
1506         /* Poll HW usage counters */
1507         DP(BNX2X_MSG_SP, "Polling usage counters\n");
1508         if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1509                 return -EBUSY;
1510
1511         /* Zero the igu 'trailing edge' and 'leading edge' */
1512
1513         /* Send the FW cleanup command */
1514         if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1515                 return -EBUSY;
1516
1517         /* ATC cleanup */
1518
1519         /* Verify TX hw is flushed */
1520         bnx2x_tx_hw_flushed(bp, poll_cnt);
1521
1522         /* Wait 100ms (not adjusted according to platform) */
1523         msleep(100);
1524
1525         /* Verify no pending pci transactions */
1526         if (bnx2x_is_pcie_pending(bp->pdev))
1527                 BNX2X_ERR("PCIE Transactions still pending\n");
1528
1529         /* Debug */
1530         bnx2x_hw_enable_status(bp);
1531
1532         /*
1533          * Master enable - Due to WB DMAE writes performed before this
1534          * register is re-initialized as part of the regular function init
1535          */
1536         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1537
1538         return 0;
1539 }
1540
1541 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1542 {
1543         int port = BP_PORT(bp);
1544         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1545         u32 val = REG_RD(bp, addr);
1546         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1547         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1548         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1549
1550         if (msix) {
1551                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1552                          HC_CONFIG_0_REG_INT_LINE_EN_0);
1553                 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1554                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1555                 if (single_msix)
1556                         val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
1557         } else if (msi) {
1558                 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1559                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1560                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1561                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1562         } else {
1563                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1564                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1565                         HC_CONFIG_0_REG_INT_LINE_EN_0 |
1566                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1567
1568                 if (!CHIP_IS_E1(bp)) {
1569                         DP(NETIF_MSG_IFUP,
1570                            "write %x to HC %d (addr 0x%x)\n", val, port, addr);
1571
1572                         REG_WR(bp, addr, val);
1573
1574                         val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1575                 }
1576         }
1577
1578         if (CHIP_IS_E1(bp))
1579                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1580
1581         DP(NETIF_MSG_IFUP,
1582            "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1583            (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1584
1585         REG_WR(bp, addr, val);
1586         /*
1587          * Ensure that HC_CONFIG is written before leading/trailing edge config
1588          */
1589         mmiowb();
1590         barrier();
1591
1592         if (!CHIP_IS_E1(bp)) {
1593                 /* init leading/trailing edge */
1594                 if (IS_MF(bp)) {
1595                         val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1596                         if (bp->port.pmf)
1597                                 /* enable nig and gpio3 attention */
1598                                 val |= 0x1100;
1599                 } else
1600                         val = 0xffff;
1601
1602                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1603                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1604         }
1605
1606         /* Make sure that interrupts are indeed enabled from here on */
1607         mmiowb();
1608 }
1609
1610 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1611 {
1612         u32 val;
1613         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1614         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1615         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1616
1617         val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1618
1619         if (msix) {
1620                 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1621                          IGU_PF_CONF_SINGLE_ISR_EN);
1622                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1623                         IGU_PF_CONF_ATTN_BIT_EN);
1624
1625                 if (single_msix)
1626                         val |= IGU_PF_CONF_SINGLE_ISR_EN;
1627         } else if (msi) {
1628                 val &= ~IGU_PF_CONF_INT_LINE_EN;
1629                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1630                         IGU_PF_CONF_ATTN_BIT_EN |
1631                         IGU_PF_CONF_SINGLE_ISR_EN);
1632         } else {
1633                 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1634                 val |= (IGU_PF_CONF_INT_LINE_EN |
1635                         IGU_PF_CONF_ATTN_BIT_EN |
1636                         IGU_PF_CONF_SINGLE_ISR_EN);
1637         }
1638
1639         /* Clean previous status - need to configure igu prior to ack*/
1640         if ((!msix) || single_msix) {
1641                 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1642                 bnx2x_ack_int(bp);
1643         }
1644
1645         val |= IGU_PF_CONF_FUNC_EN;
1646
1647         DP(NETIF_MSG_IFUP, "write 0x%x to IGU  mode %s\n",
1648            val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1649
1650         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1651
1652         if (val & IGU_PF_CONF_INT_LINE_EN)
1653                 pci_intx(bp->pdev, true);
1654
1655         barrier();
1656
1657         /* init leading/trailing edge */
1658         if (IS_MF(bp)) {
1659                 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1660                 if (bp->port.pmf)
1661                         /* enable nig and gpio3 attention */
1662                         val |= 0x1100;
1663         } else
1664                 val = 0xffff;
1665
1666         REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1667         REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1668
1669         /* Make sure that interrupts are indeed enabled from here on */
1670         mmiowb();
1671 }
1672
1673 void bnx2x_int_enable(struct bnx2x *bp)
1674 {
1675         if (bp->common.int_block == INT_BLOCK_HC)
1676                 bnx2x_hc_int_enable(bp);
1677         else
1678                 bnx2x_igu_int_enable(bp);
1679 }
1680
1681 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1682 {
1683         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1684         int i, offset;
1685
1686         if (disable_hw)
1687                 /* prevent the HW from sending interrupts */
1688                 bnx2x_int_disable(bp);
1689
1690         /* make sure all ISRs are done */
1691         if (msix) {
1692                 synchronize_irq(bp->msix_table[0].vector);
1693                 offset = 1;
1694                 if (CNIC_SUPPORT(bp))
1695                         offset++;
1696                 for_each_eth_queue(bp, i)
1697                         synchronize_irq(bp->msix_table[offset++].vector);
1698         } else
1699                 synchronize_irq(bp->pdev->irq);
1700
1701         /* make sure sp_task is not running */
1702         cancel_delayed_work(&bp->sp_task);
1703         cancel_delayed_work(&bp->period_task);
1704         flush_workqueue(bnx2x_wq);
1705 }
1706
1707 /* fast path */
1708
1709 /*
1710  * General service functions
1711  */
1712
1713 /* Return true if succeeded to acquire the lock */
1714 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1715 {
1716         u32 lock_status;
1717         u32 resource_bit = (1 << resource);
1718         int func = BP_FUNC(bp);
1719         u32 hw_lock_control_reg;
1720
1721         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1722            "Trying to take a lock on resource %d\n", resource);
1723
1724         /* Validating that the resource is within range */
1725         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1726                 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1727                    "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1728                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1729                 return false;
1730         }
1731
1732         if (func <= 5)
1733                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1734         else
1735                 hw_lock_control_reg =
1736                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1737
1738         /* Try to acquire the lock */
1739         REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1740         lock_status = REG_RD(bp, hw_lock_control_reg);
1741         if (lock_status & resource_bit)
1742                 return true;
1743
1744         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1745            "Failed to get a lock on resource %d\n", resource);
1746         return false;
1747 }
1748
1749 /**
1750  * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1751  *
1752  * @bp: driver handle
1753  *
1754  * Returns the recovery leader resource id according to the engine this function
1755  * belongs to. Currently only only 2 engines is supported.
1756  */
1757 static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1758 {
1759         if (BP_PATH(bp))
1760                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1761         else
1762                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1763 }
1764
1765 /**
1766  * bnx2x_trylock_leader_lock- try to acquire a leader lock.
1767  *
1768  * @bp: driver handle
1769  *
1770  * Tries to acquire a leader lock for current engine.
1771  */
1772 static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1773 {
1774         return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1775 }
1776
1777 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1778
1779 /* schedule the sp task and mark that interrupt occurred (runs from ISR) */
1780 static int bnx2x_schedule_sp_task(struct bnx2x *bp)
1781 {
1782         /* Set the interrupt occurred bit for the sp-task to recognize it
1783          * must ack the interrupt and transition according to the IGU
1784          * state machine.
1785          */
1786         atomic_set(&bp->interrupt_occurred, 1);
1787
1788         /* The sp_task must execute only after this bit
1789          * is set, otherwise we will get out of sync and miss all
1790          * further interrupts. Hence, the barrier.
1791          */
1792         smp_wmb();
1793
1794         /* schedule sp_task to workqueue */
1795         return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1796 }
1797
1798 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1799 {
1800         struct bnx2x *bp = fp->bp;
1801         int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1802         int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1803         enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1804         struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
1805
1806         DP(BNX2X_MSG_SP,
1807            "fp %d  cid %d  got ramrod #%d  state is %x  type is %d\n",
1808            fp->index, cid, command, bp->state,
1809            rr_cqe->ramrod_cqe.ramrod_type);
1810
1811         /* If cid is within VF range, replace the slowpath object with the
1812          * one corresponding to this VF
1813          */
1814         if (cid >= BNX2X_FIRST_VF_CID  &&
1815             cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)
1816                 bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj);
1817
1818         switch (command) {
1819         case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1820                 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
1821                 drv_cmd = BNX2X_Q_CMD_UPDATE;
1822                 break;
1823
1824         case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1825                 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
1826                 drv_cmd = BNX2X_Q_CMD_SETUP;
1827                 break;
1828
1829         case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1830                 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1831                 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1832                 break;
1833
1834         case (RAMROD_CMD_ID_ETH_HALT):
1835                 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
1836                 drv_cmd = BNX2X_Q_CMD_HALT;
1837                 break;
1838
1839         case (RAMROD_CMD_ID_ETH_TERMINATE):
1840                 DP(BNX2X_MSG_SP, "got MULTI[%d] terminate ramrod\n", cid);
1841                 drv_cmd = BNX2X_Q_CMD_TERMINATE;
1842                 break;
1843
1844         case (RAMROD_CMD_ID_ETH_EMPTY):
1845                 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
1846                 drv_cmd = BNX2X_Q_CMD_EMPTY;
1847                 break;
1848
1849         case (RAMROD_CMD_ID_ETH_TPA_UPDATE):
1850                 DP(BNX2X_MSG_SP, "got tpa update ramrod CID=%d\n", cid);
1851                 drv_cmd = BNX2X_Q_CMD_UPDATE_TPA;
1852                 break;
1853
1854         default:
1855                 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1856                           command, fp->index);
1857                 return;
1858         }
1859
1860         if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1861             q_obj->complete_cmd(bp, q_obj, drv_cmd))
1862                 /* q_obj->complete_cmd() failure means that this was
1863                  * an unexpected completion.
1864                  *
1865                  * In this case we don't want to increase the bp->spq_left
1866                  * because apparently we haven't sent this command the first
1867                  * place.
1868                  */
1869 #ifdef BNX2X_STOP_ON_ERROR
1870                 bnx2x_panic();
1871 #else
1872                 return;
1873 #endif
1874
1875         smp_mb__before_atomic();
1876         atomic_inc(&bp->cq_spq_left);
1877         /* push the change in bp->spq_left and towards the memory */
1878         smp_mb__after_atomic();
1879
1880         DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1881
1882         if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1883             (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
1884                 /* if Q update ramrod is completed for last Q in AFEX vif set
1885                  * flow, then ACK MCP at the end
1886                  *
1887                  * mark pending ACK to MCP bit.
1888                  * prevent case that both bits are cleared.
1889                  * At the end of load/unload driver checks that
1890                  * sp_state is cleared, and this order prevents
1891                  * races
1892                  */
1893                 smp_mb__before_atomic();
1894                 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
1895                 wmb();
1896                 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
1897                 smp_mb__after_atomic();
1898
1899                 /* schedule the sp task as mcp ack is required */
1900                 bnx2x_schedule_sp_task(bp);
1901         }
1902
1903         return;
1904 }
1905
1906 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1907 {
1908         struct bnx2x *bp = netdev_priv(dev_instance);
1909         u16 status = bnx2x_ack_int(bp);
1910         u16 mask;
1911         int i;
1912         u8 cos;
1913
1914         /* Return here if interrupt is shared and it's not for us */
1915         if (unlikely(status == 0)) {
1916                 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1917                 return IRQ_NONE;
1918         }
1919         DP(NETIF_MSG_INTR, "got an interrupt  status 0x%x\n", status);
1920
1921 #ifdef BNX2X_STOP_ON_ERROR
1922         if (unlikely(bp->panic))
1923                 return IRQ_HANDLED;
1924 #endif
1925
1926         for_each_eth_queue(bp, i) {
1927                 struct bnx2x_fastpath *fp = &bp->fp[i];
1928
1929                 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp));
1930                 if (status & mask) {
1931                         /* Handle Rx or Tx according to SB id */
1932                         for_each_cos_in_tx_queue(fp, cos)
1933                                 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
1934                         prefetch(&fp->sb_running_index[SM_RX_ID]);
1935                         napi_schedule(&bnx2x_fp(bp, fp->index, napi));
1936                         status &= ~mask;
1937                 }
1938         }
1939
1940         if (CNIC_SUPPORT(bp)) {
1941                 mask = 0x2;
1942                 if (status & (mask | 0x1)) {
1943                         struct cnic_ops *c_ops = NULL;
1944
1945                         rcu_read_lock();
1946                         c_ops = rcu_dereference(bp->cnic_ops);
1947                         if (c_ops && (bp->cnic_eth_dev.drv_state &
1948                                       CNIC_DRV_STATE_HANDLES_IRQ))
1949                                 c_ops->cnic_handler(bp->cnic_data, NULL);
1950                         rcu_read_unlock();
1951
1952                         status &= ~mask;
1953                 }
1954         }
1955
1956         if (unlikely(status & 0x1)) {
1957
1958                 /* schedule sp task to perform default status block work, ack
1959                  * attentions and enable interrupts.
1960                  */
1961                 bnx2x_schedule_sp_task(bp);
1962
1963                 status &= ~0x1;
1964                 if (!status)
1965                         return IRQ_HANDLED;
1966         }
1967
1968         if (unlikely(status))
1969                 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1970                    status);
1971
1972         return IRQ_HANDLED;
1973 }
1974
1975 /* Link */
1976
1977 /*
1978  * General service functions
1979  */
1980
1981 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1982 {
1983         u32 lock_status;
1984         u32 resource_bit = (1 << resource);
1985         int func = BP_FUNC(bp);
1986         u32 hw_lock_control_reg;
1987         int cnt;
1988
1989         /* Validating that the resource is within range */
1990         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1991                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1992                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1993                 return -EINVAL;
1994         }
1995
1996         if (func <= 5) {
1997                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1998         } else {
1999                 hw_lock_control_reg =
2000                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2001         }
2002
2003         /* Validating that the resource is not already taken */
2004         lock_status = REG_RD(bp, hw_lock_control_reg);
2005         if (lock_status & resource_bit) {
2006                 BNX2X_ERR("lock_status 0x%x  resource_bit 0x%x\n",
2007                    lock_status, resource_bit);
2008                 return -EEXIST;
2009         }
2010
2011         /* Try for 5 second every 5ms */
2012         for (cnt = 0; cnt < 1000; cnt++) {
2013                 /* Try to acquire the lock */
2014                 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
2015                 lock_status = REG_RD(bp, hw_lock_control_reg);
2016                 if (lock_status & resource_bit)
2017                         return 0;
2018
2019                 usleep_range(5000, 10000);
2020         }
2021         BNX2X_ERR("Timeout\n");
2022         return -EAGAIN;
2023 }
2024
2025 int bnx2x_release_leader_lock(struct bnx2x *bp)
2026 {
2027         return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
2028 }
2029
2030 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
2031 {
2032         u32 lock_status;
2033         u32 resource_bit = (1 << resource);
2034         int func = BP_FUNC(bp);
2035         u32 hw_lock_control_reg;
2036
2037         /* Validating that the resource is within range */
2038         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
2039                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
2040                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
2041                 return -EINVAL;
2042         }
2043
2044         if (func <= 5) {
2045                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
2046         } else {
2047                 hw_lock_control_reg =
2048                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2049         }
2050
2051         /* Validating that the resource is currently taken */
2052         lock_status = REG_RD(bp, hw_lock_control_reg);
2053         if (!(lock_status & resource_bit)) {
2054                 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. Unlock was called but lock wasn't taken!\n",
2055                           lock_status, resource_bit);
2056                 return -EFAULT;
2057         }
2058
2059         REG_WR(bp, hw_lock_control_reg, resource_bit);
2060         return 0;
2061 }
2062
2063 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
2064 {
2065         /* The GPIO should be swapped if swap register is set and active */
2066         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2067                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2068         int gpio_shift = gpio_num +
2069                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2070         u32 gpio_mask = (1 << gpio_shift);
2071         u32 gpio_reg;
2072         int value;
2073
2074         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2075                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2076                 return -EINVAL;
2077         }
2078
2079         /* read GPIO value */
2080         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2081
2082         /* get the requested pin value */
2083         if ((gpio_reg & gpio_mask) == gpio_mask)
2084                 value = 1;
2085         else
2086                 value = 0;
2087
2088         return value;
2089 }
2090
2091 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2092 {
2093         /* The GPIO should be swapped if swap register is set and active */
2094         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2095                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2096         int gpio_shift = gpio_num +
2097                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2098         u32 gpio_mask = (1 << gpio_shift);
2099         u32 gpio_reg;
2100
2101         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2102                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2103                 return -EINVAL;
2104         }
2105
2106         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2107         /* read GPIO and mask except the float bits */
2108         gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
2109
2110         switch (mode) {
2111         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2112                 DP(NETIF_MSG_LINK,
2113                    "Set GPIO %d (shift %d) -> output low\n",
2114                    gpio_num, gpio_shift);
2115                 /* clear FLOAT and set CLR */
2116                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2117                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
2118                 break;
2119
2120         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2121                 DP(NETIF_MSG_LINK,
2122                    "Set GPIO %d (shift %d) -> output high\n",
2123                    gpio_num, gpio_shift);
2124                 /* clear FLOAT and set SET */
2125                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2126                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
2127                 break;
2128
2129         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2130                 DP(NETIF_MSG_LINK,
2131                    "Set GPIO %d (shift %d) -> input\n",
2132                    gpio_num, gpio_shift);
2133                 /* set FLOAT */
2134                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2135                 break;
2136
2137         default:
2138                 break;
2139         }
2140
2141         REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2142         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2143
2144         return 0;
2145 }
2146
2147 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
2148 {
2149         u32 gpio_reg = 0;
2150         int rc = 0;
2151
2152         /* Any port swapping should be handled by caller. */
2153
2154         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2155         /* read GPIO and mask except the float bits */
2156         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2157         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2158         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
2159         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
2160
2161         switch (mode) {
2162         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2163                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2164                 /* set CLR */
2165                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2166                 break;
2167
2168         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2169                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2170                 /* set SET */
2171                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2172                 break;
2173
2174         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2175                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2176                 /* set FLOAT */
2177                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2178                 break;
2179
2180         default:
2181                 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2182                 rc = -EINVAL;
2183                 break;
2184         }
2185
2186         if (rc == 0)
2187                 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2188
2189         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2190
2191         return rc;
2192 }
2193
2194 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2195 {
2196         /* The GPIO should be swapped if swap register is set and active */
2197         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2198                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2199         int gpio_shift = gpio_num +
2200                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2201         u32 gpio_mask = (1 << gpio_shift);
2202         u32 gpio_reg;
2203
2204         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2205                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2206                 return -EINVAL;
2207         }
2208
2209         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2210         /* read GPIO int */
2211         gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2212
2213         switch (mode) {
2214         case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2215                 DP(NETIF_MSG_LINK,
2216                    "Clear GPIO INT %d (shift %d) -> output low\n",
2217                    gpio_num, gpio_shift);
2218                 /* clear SET and set CLR */
2219                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2220                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2221                 break;
2222
2223         case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2224                 DP(NETIF_MSG_LINK,
2225                    "Set GPIO INT %d (shift %d) -> output high\n",
2226                    gpio_num, gpio_shift);
2227                 /* clear CLR and set SET */
2228                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2229                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2230                 break;
2231
2232         default:
2233                 break;
2234         }
2235
2236         REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2237         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2238
2239         return 0;
2240 }
2241
2242 static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode)
2243 {
2244         u32 spio_reg;
2245
2246         /* Only 2 SPIOs are configurable */
2247         if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
2248                 BNX2X_ERR("Invalid SPIO 0x%x\n", spio);
2249                 return -EINVAL;
2250         }
2251
2252         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2253         /* read SPIO and mask except the float bits */
2254         spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
2255
2256         switch (mode) {
2257         case MISC_SPIO_OUTPUT_LOW:
2258                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio);
2259                 /* clear FLOAT and set CLR */
2260                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2261                 spio_reg |=  (spio << MISC_SPIO_CLR_POS);
2262                 break;
2263
2264         case MISC_SPIO_OUTPUT_HIGH:
2265                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio);
2266                 /* clear FLOAT and set SET */
2267                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2268                 spio_reg |=  (spio << MISC_SPIO_SET_POS);
2269                 break;
2270
2271         case MISC_SPIO_INPUT_HI_Z:
2272                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio);
2273                 /* set FLOAT */
2274                 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
2275                 break;
2276
2277         default:
2278                 break;
2279         }
2280
2281         REG_WR(bp, MISC_REG_SPIO, spio_reg);
2282         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2283
2284         return 0;
2285 }
2286
2287 void bnx2x_calc_fc_adv(struct bnx2x *bp)
2288 {
2289         u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2290         switch (bp->link_vars.ieee_fc &
2291                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2292         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
2293                 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2294                                                    ADVERTISED_Pause);
2295                 break;
2296
2297         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2298                 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2299                                                   ADVERTISED_Pause);
2300                 break;
2301
2302         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2303                 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2304                 break;
2305
2306         default:
2307                 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2308                                                    ADVERTISED_Pause);
2309                 break;
2310         }
2311 }
2312
2313 static void bnx2x_set_requested_fc(struct bnx2x *bp)
2314 {
2315         /* Initialize link parameters structure variables
2316          * It is recommended to turn off RX FC for jumbo frames
2317          *  for better performance
2318          */
2319         if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2320                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2321         else
2322                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2323 }
2324
2325 static void bnx2x_init_dropless_fc(struct bnx2x *bp)
2326 {
2327         u32 pause_enabled = 0;
2328
2329         if (!CHIP_IS_E1(bp) && bp->dropless_fc && bp->link_vars.link_up) {
2330                 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2331                         pause_enabled = 1;
2332
2333                 REG_WR(bp, BAR_USTRORM_INTMEM +
2334                            USTORM_ETH_PAUSE_ENABLED_OFFSET(BP_PORT(bp)),
2335                        pause_enabled);
2336         }
2337
2338         DP(NETIF_MSG_IFUP | NETIF_MSG_LINK, "dropless_fc is %s\n",
2339            pause_enabled ? "enabled" : "disabled");
2340 }
2341
2342 int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2343 {
2344         int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp);
2345         u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2346
2347         if (!BP_NOMCP(bp)) {
2348                 bnx2x_set_requested_fc(bp);
2349                 bnx2x_acquire_phy_lock(bp);
2350
2351                 if (load_mode == LOAD_DIAG) {
2352                         struct link_params *lp = &bp->link_params;
2353                         lp->loopback_mode = LOOPBACK_XGXS;
2354                         /* do PHY loopback at 10G speed, if possible */
2355                         if (lp->req_line_speed[cfx_idx] < SPEED_10000) {
2356                                 if (lp->speed_cap_mask[cfx_idx] &
2357                                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2358                                         lp->req_line_speed[cfx_idx] =
2359                                         SPEED_10000;
2360                                 else
2361                                         lp->req_line_speed[cfx_idx] =
2362                                         SPEED_1000;
2363                         }
2364                 }
2365
2366                 if (load_mode == LOAD_LOOPBACK_EXT) {
2367                         struct link_params *lp = &bp->link_params;
2368                         lp->loopback_mode = LOOPBACK_EXT;
2369                 }
2370
2371                 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2372
2373                 bnx2x_release_phy_lock(bp);
2374
2375                 bnx2x_init_dropless_fc(bp);
2376
2377                 bnx2x_calc_fc_adv(bp);
2378
2379                 if (bp->link_vars.link_up) {
2380                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2381                         bnx2x_link_report(bp);
2382                 }
2383                 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2384                 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2385                 return rc;
2386         }
2387         BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2388         return -EINVAL;
2389 }
2390
2391 void bnx2x_link_set(struct bnx2x *bp)
2392 {
2393         if (!BP_NOMCP(bp)) {
2394                 bnx2x_acquire_phy_lock(bp);
2395                 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2396                 bnx2x_release_phy_lock(bp);
2397
2398                 bnx2x_init_dropless_fc(bp);
2399
2400                 bnx2x_calc_fc_adv(bp);
2401         } else
2402                 BNX2X_ERR("Bootcode is missing - can not set link\n");
2403 }
2404
2405 static void bnx2x__link_reset(struct bnx2x *bp)
2406 {
2407         if (!BP_NOMCP(bp)) {
2408                 bnx2x_acquire_phy_lock(bp);
2409                 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars);
2410                 bnx2x_release_phy_lock(bp);
2411         } else
2412                 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2413 }
2414
2415 void bnx2x_force_link_reset(struct bnx2x *bp)
2416 {
2417         bnx2x_acquire_phy_lock(bp);
2418         bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2419         bnx2x_release_phy_lock(bp);
2420 }
2421
2422 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2423 {
2424         u8 rc = 0;
2425
2426         if (!BP_NOMCP(bp)) {
2427                 bnx2x_acquire_phy_lock(bp);
2428                 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2429                                      is_serdes);
2430                 bnx2x_release_phy_lock(bp);
2431         } else
2432                 BNX2X_ERR("Bootcode is missing - can not test link\n");
2433
2434         return rc;
2435 }
2436
2437 /* Calculates the sum of vn_min_rates.
2438    It's needed for further normalizing of the min_rates.
2439    Returns:
2440      sum of vn_min_rates.
2441        or
2442      0 - if all the min_rates are 0.
2443      In the later case fairness algorithm should be deactivated.
2444      If not all min_rates are zero then those that are zeroes will be set to 1.
2445  */
2446 static void bnx2x_calc_vn_min(struct bnx2x *bp,
2447                                       struct cmng_init_input *input)
2448 {
2449         int all_zero = 1;
2450         int vn;
2451
2452         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2453                 u32 vn_cfg = bp->mf_config[vn];
2454                 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2455                                    FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2456
2457                 /* Skip hidden vns */
2458                 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2459                         vn_min_rate = 0;
2460                 /* If min rate is zero - set it to 1 */
2461                 else if (!vn_min_rate)
2462                         vn_min_rate = DEF_MIN_RATE;
2463                 else
2464                         all_zero = 0;
2465
2466                 input->vnic_min_rate[vn] = vn_min_rate;
2467         }
2468
2469         /* if ETS or all min rates are zeros - disable fairness */
2470         if (BNX2X_IS_ETS_ENABLED(bp)) {
2471                 input->flags.cmng_enables &=
2472                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2473                 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2474         } else if (all_zero) {
2475                 input->flags.cmng_enables &=
2476                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2477                 DP(NETIF_MSG_IFUP,
2478                    "All MIN values are zeroes fairness will be disabled\n");
2479         } else
2480                 input->flags.cmng_enables |=
2481                                         CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2482 }
2483
2484 static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2485                                     struct cmng_init_input *input)
2486 {
2487         u16 vn_max_rate;
2488         u32 vn_cfg = bp->mf_config[vn];
2489
2490         if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2491                 vn_max_rate = 0;
2492         else {
2493                 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2494
2495                 if (IS_MF_SI(bp)) {
2496                         /* maxCfg in percents of linkspeed */
2497                         vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2498                 } else /* SD modes */
2499                         /* maxCfg is absolute in 100Mb units */
2500                         vn_max_rate = maxCfg * 100;
2501         }
2502
2503         DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
2504
2505         input->vnic_max_rate[vn] = vn_max_rate;
2506 }
2507
2508 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2509 {
2510         if (CHIP_REV_IS_SLOW(bp))
2511                 return CMNG_FNS_NONE;
2512         if (IS_MF(bp))
2513                 return CMNG_FNS_MINMAX;
2514
2515         return CMNG_FNS_NONE;
2516 }
2517
2518 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2519 {
2520         int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2521
2522         if (BP_NOMCP(bp))
2523                 return; /* what should be the default value in this case */
2524
2525         /* For 2 port configuration the absolute function number formula
2526          * is:
2527          *      abs_func = 2 * vn + BP_PORT + BP_PATH
2528          *
2529          *      and there are 4 functions per port
2530          *
2531          * For 4 port configuration it is
2532          *      abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2533          *
2534          *      and there are 2 functions per port
2535          */
2536         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2537                 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2538
2539                 if (func >= E1H_FUNC_MAX)
2540                         break;
2541
2542                 bp->mf_config[vn] =
2543                         MF_CFG_RD(bp, func_mf_config[func].config);
2544         }
2545         if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2546                 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2547                 bp->flags |= MF_FUNC_DIS;
2548         } else {
2549                 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2550                 bp->flags &= ~MF_FUNC_DIS;
2551         }
2552 }
2553
2554 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2555 {
2556         struct cmng_init_input input;
2557         memset(&input, 0, sizeof(struct cmng_init_input));
2558
2559         input.port_rate = bp->link_vars.line_speed;
2560
2561         if (cmng_type == CMNG_FNS_MINMAX && input.port_rate) {
2562                 int vn;
2563
2564                 /* read mf conf from shmem */
2565                 if (read_cfg)
2566                         bnx2x_read_mf_cfg(bp);
2567
2568                 /* vn_weight_sum and enable fairness if not 0 */
2569                 bnx2x_calc_vn_min(bp, &input);
2570
2571                 /* calculate and set min-max rate for each vn */
2572                 if (bp->port.pmf)
2573                         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
2574                                 bnx2x_calc_vn_max(bp, vn, &input);
2575
2576                 /* always enable rate shaping and fairness */
2577                 input.flags.cmng_enables |=
2578                                         CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2579
2580                 bnx2x_init_cmng(&input, &bp->cmng);
2581                 return;
2582         }
2583
2584         /* rate shaping and fairness are disabled */
2585         DP(NETIF_MSG_IFUP,
2586            "rate shaping and fairness are disabled\n");
2587 }
2588
2589 static void storm_memset_cmng(struct bnx2x *bp,
2590                               struct cmng_init *cmng,
2591                               u8 port)
2592 {
2593         int vn;
2594         size_t size = sizeof(struct cmng_struct_per_port);
2595
2596         u32 addr = BAR_XSTRORM_INTMEM +
2597                         XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
2598
2599         __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2600
2601         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2602                 int func = func_by_vn(bp, vn);
2603
2604                 addr = BAR_XSTRORM_INTMEM +
2605                        XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
2606                 size = sizeof(struct rate_shaping_vars_per_vn);
2607                 __storm_memset_struct(bp, addr, size,
2608                                       (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2609
2610                 addr = BAR_XSTRORM_INTMEM +
2611                        XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
2612                 size = sizeof(struct fairness_vars_per_vn);
2613                 __storm_memset_struct(bp, addr, size,
2614                                       (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2615         }
2616 }
2617
2618 /* init cmng mode in HW according to local configuration */
2619 void bnx2x_set_local_cmng(struct bnx2x *bp)
2620 {
2621         int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2622
2623         if (cmng_fns != CMNG_FNS_NONE) {
2624                 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2625                 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2626         } else {
2627                 /* rate shaping and fairness are disabled */
2628                 DP(NETIF_MSG_IFUP,
2629                    "single function mode without fairness\n");
2630         }
2631 }
2632
2633 /* This function is called upon link interrupt */
2634 static void bnx2x_link_attn(struct bnx2x *bp)
2635 {
2636         /* Make sure that we are synced with the current statistics */
2637         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2638
2639         bnx2x_link_update(&bp->link_params, &bp->link_vars);
2640
2641         bnx2x_init_dropless_fc(bp);
2642
2643         if (bp->link_vars.link_up) {
2644
2645                 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2646                         struct host_port_stats *pstats;
2647
2648                         pstats = bnx2x_sp(bp, port_stats);
2649                         /* reset old mac stats */
2650                         memset(&(pstats->mac_stx[0]), 0,
2651                                sizeof(struct mac_stx));
2652                 }
2653                 if (bp->state == BNX2X_STATE_OPEN)
2654                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2655         }
2656
2657         if (bp->link_vars.link_up && bp->link_vars.line_speed)
2658                 bnx2x_set_local_cmng(bp);
2659
2660         __bnx2x_link_report(bp);
2661
2662         if (IS_MF(bp))
2663                 bnx2x_link_sync_notify(bp);
2664 }
2665
2666 void bnx2x__link_status_update(struct bnx2x *bp)
2667 {
2668         if (bp->state != BNX2X_STATE_OPEN)
2669                 return;
2670
2671         /* read updated dcb configuration */
2672         if (IS_PF(bp)) {
2673                 bnx2x_dcbx_pmf_update(bp);
2674                 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2675                 if (bp->link_vars.link_up)
2676                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2677                 else
2678                         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2679                         /* indicate link status */
2680                 bnx2x_link_report(bp);
2681
2682         } else { /* VF */
2683                 bp->port.supported[0] |= (SUPPORTED_10baseT_Half |
2684                                           SUPPORTED_10baseT_Full |
2685                                           SUPPORTED_100baseT_Half |
2686                                           SUPPORTED_100baseT_Full |
2687                                           SUPPORTED_1000baseT_Full |
2688                                           SUPPORTED_2500baseX_Full |
2689                                           SUPPORTED_10000baseT_Full |
2690                                           SUPPORTED_TP |
2691                                           SUPPORTED_FIBRE |
2692                                           SUPPORTED_Autoneg |
2693                                           SUPPORTED_Pause |
2694                                           SUPPORTED_Asym_Pause);
2695                 bp->port.advertising[0] = bp->port.supported[0];
2696
2697                 bp->link_params.bp = bp;
2698                 bp->link_params.port = BP_PORT(bp);
2699                 bp->link_params.req_duplex[0] = DUPLEX_FULL;
2700                 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE;
2701                 bp->link_params.req_line_speed[0] = SPEED_10000;
2702                 bp->link_params.speed_cap_mask[0] = 0x7f0000;
2703                 bp->link_params.switch_cfg = SWITCH_CFG_10G;
2704                 bp->link_vars.mac_type = MAC_TYPE_BMAC;
2705                 bp->link_vars.line_speed = SPEED_10000;
2706                 bp->link_vars.link_status =
2707                         (LINK_STATUS_LINK_UP |
2708                          LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
2709                 bp->link_vars.link_up = 1;
2710                 bp->link_vars.duplex = DUPLEX_FULL;
2711                 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2712                 __bnx2x_link_report(bp);
2713
2714                 bnx2x_sample_bulletin(bp);
2715
2716                 /* if bulletin board did not have an update for link status
2717                  * __bnx2x_link_report will report current status
2718                  * but it will NOT duplicate report in case of already reported
2719                  * during sampling bulletin board.
2720                  */
2721                 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2722         }
2723 }
2724
2725 static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2726                                   u16 vlan_val, u8 allowed_prio)
2727 {
2728         struct bnx2x_func_state_params func_params = {NULL};
2729         struct bnx2x_func_afex_update_params *f_update_params =
2730                 &func_params.params.afex_update;
2731
2732         func_params.f_obj = &bp->func_obj;
2733         func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2734
2735         /* no need to wait for RAMROD completion, so don't
2736          * set RAMROD_COMP_WAIT flag
2737          */
2738
2739         f_update_params->vif_id = vifid;
2740         f_update_params->afex_default_vlan = vlan_val;
2741         f_update_params->allowed_priorities = allowed_prio;
2742
2743         /* if ramrod can not be sent, response to MCP immediately */
2744         if (bnx2x_func_state_change(bp, &func_params) < 0)
2745                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
2746
2747         return 0;
2748 }
2749
2750 static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2751                                           u16 vif_index, u8 func_bit_map)
2752 {
2753         struct bnx2x_func_state_params func_params = {NULL};
2754         struct bnx2x_func_afex_viflists_params *update_params =
2755                 &func_params.params.afex_viflists;
2756         int rc;
2757         u32 drv_msg_code;
2758
2759         /* validate only LIST_SET and LIST_GET are received from switch */
2760         if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2761                 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2762                           cmd_type);
2763
2764         func_params.f_obj = &bp->func_obj;
2765         func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2766
2767         /* set parameters according to cmd_type */
2768         update_params->afex_vif_list_command = cmd_type;
2769         update_params->vif_list_index = vif_index;
2770         update_params->func_bit_map =
2771                 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2772         update_params->func_to_clear = 0;
2773         drv_msg_code =
2774                 (cmd_type == VIF_LIST_RULE_GET) ?
2775                 DRV_MSG_CODE_AFEX_LISTGET_ACK :
2776                 DRV_MSG_CODE_AFEX_LISTSET_ACK;
2777
2778         /* if ramrod can not be sent, respond to MCP immediately for
2779          * SET and GET requests (other are not triggered from MCP)
2780          */
2781         rc = bnx2x_func_state_change(bp, &func_params);
2782         if (rc < 0)
2783                 bnx2x_fw_command(bp, drv_msg_code, 0);
2784
2785         return 0;
2786 }
2787
2788 static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2789 {
2790         struct afex_stats afex_stats;
2791         u32 func = BP_ABS_FUNC(bp);
2792         u32 mf_config;
2793         u16 vlan_val;
2794         u32 vlan_prio;
2795         u16 vif_id;
2796         u8 allowed_prio;
2797         u8 vlan_mode;
2798         u32 addr_to_write, vifid, addrs, stats_type, i;
2799
2800         if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2801                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2802                 DP(BNX2X_MSG_MCP,
2803                    "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2804                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2805         }
2806
2807         if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2808                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2809                 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2810                 DP(BNX2X_MSG_MCP,
2811                    "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2812                    vifid, addrs);
2813                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2814                                                addrs);
2815         }
2816
2817         if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2818                 addr_to_write = SHMEM2_RD(bp,
2819                         afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2820                 stats_type = SHMEM2_RD(bp,
2821                         afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2822
2823                 DP(BNX2X_MSG_MCP,
2824                    "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2825                    addr_to_write);
2826
2827                 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2828
2829                 /* write response to scratchpad, for MCP */
2830                 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2831                         REG_WR(bp, addr_to_write + i*sizeof(u32),
2832                                *(((u32 *)(&afex_stats))+i));
2833
2834                 /* send ack message to MCP */
2835                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
2836         }
2837
2838         if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2839                 mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2840                 bp->mf_config[BP_VN(bp)] = mf_config;
2841                 DP(BNX2X_MSG_MCP,
2842                    "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2843                    mf_config);
2844
2845                 /* if VIF_SET is "enabled" */
2846                 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2847                         /* set rate limit directly to internal RAM */
2848                         struct cmng_init_input cmng_input;
2849                         struct rate_shaping_vars_per_vn m_rs_vn;
2850                         size_t size = sizeof(struct rate_shaping_vars_per_vn);
2851                         u32 addr = BAR_XSTRORM_INTMEM +
2852                             XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
2853
2854                         bp->mf_config[BP_VN(bp)] = mf_config;
2855
2856                         bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2857                         m_rs_vn.vn_counter.rate =
2858                                 cmng_input.vnic_max_rate[BP_VN(bp)];
2859                         m_rs_vn.vn_counter.quota =
2860                                 (m_rs_vn.vn_counter.rate *
2861                                  RS_PERIODIC_TIMEOUT_USEC) / 8;
2862
2863                         __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2864
2865                         /* read relevant values from mf_cfg struct in shmem */
2866                         vif_id =
2867                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2868                                  FUNC_MF_CFG_E1HOV_TAG_MASK) >>
2869                                 FUNC_MF_CFG_E1HOV_TAG_SHIFT;
2870                         vlan_val =
2871                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2872                                  FUNC_MF_CFG_AFEX_VLAN_MASK) >>
2873                                 FUNC_MF_CFG_AFEX_VLAN_SHIFT;
2874                         vlan_prio = (mf_config &
2875                                      FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
2876                                     FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
2877                         vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2878                         vlan_mode =
2879                                 (MF_CFG_RD(bp,
2880                                            func_mf_config[func].afex_config) &
2881                                  FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
2882                                 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
2883                         allowed_prio =
2884                                 (MF_CFG_RD(bp,
2885                                            func_mf_config[func].afex_config) &
2886                                  FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
2887                                 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
2888
2889                         /* send ramrod to FW, return in case of failure */
2890                         if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2891                                                    allowed_prio))
2892                                 return;
2893
2894                         bp->afex_def_vlan_tag = vlan_val;
2895                         bp->afex_vlan_mode = vlan_mode;
2896                 } else {
2897                         /* notify link down because BP->flags is disabled */
2898                         bnx2x_link_report(bp);
2899
2900                         /* send INVALID VIF ramrod to FW */
2901                         bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2902
2903                         /* Reset the default afex VLAN */
2904                         bp->afex_def_vlan_tag = -1;
2905                 }
2906         }
2907 }
2908
2909 static void bnx2x_handle_update_svid_cmd(struct bnx2x *bp)
2910 {
2911         struct bnx2x_func_switch_update_params *switch_update_params;
2912         struct bnx2x_func_state_params func_params;
2913
2914         memset(&func_params, 0, sizeof(struct bnx2x_func_state_params));
2915         switch_update_params = &func_params.params.switch_update;
2916         func_params.f_obj = &bp->func_obj;
2917         func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
2918
2919         if (IS_MF_UFP(bp)) {
2920                 int func = BP_ABS_FUNC(bp);
2921                 u32 val;
2922
2923                 /* Re-learn the S-tag from shmem */
2924                 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2925                                 FUNC_MF_CFG_E1HOV_TAG_MASK;
2926                 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
2927                         bp->mf_ov = val;
2928                 } else {
2929                         BNX2X_ERR("Got an SVID event, but no tag is configured in shmem\n");
2930                         goto fail;
2931                 }
2932
2933                 /* Configure new S-tag in LLH */
2934                 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + BP_PORT(bp) * 8,
2935                        bp->mf_ov);
2936
2937                 /* Send Ramrod to update FW of change */
2938                 __set_bit(BNX2X_F_UPDATE_SD_VLAN_TAG_CHNG,
2939                           &switch_update_params->changes);
2940                 switch_update_params->vlan = bp->mf_ov;
2941
2942                 if (bnx2x_func_state_change(bp, &func_params) < 0) {
2943                         BNX2X_ERR("Failed to configure FW of S-tag Change to %02x\n",
2944                                   bp->mf_ov);
2945                         goto fail;
2946                 }
2947
2948                 DP(BNX2X_MSG_MCP, "Configured S-tag %02x\n", bp->mf_ov);
2949
2950                 bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_OK, 0);
2951
2952                 return;
2953         }
2954
2955         /* not supported by SW yet */
2956 fail:
2957         bnx2x_fw_command(bp, DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE, 0);
2958 }
2959
2960 static void bnx2x_pmf_update(struct bnx2x *bp)
2961 {
2962         int port = BP_PORT(bp);
2963         u32 val;
2964
2965         bp->port.pmf = 1;
2966         DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
2967
2968         /*
2969          * We need the mb() to ensure the ordering between the writing to
2970          * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2971          */
2972         smp_mb();
2973
2974         /* queue a periodic task */
2975         queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2976
2977         bnx2x_dcbx_pmf_update(bp);
2978
2979         /* enable nig attention */
2980         val = (0xff0f | (1 << (BP_VN(bp) + 4)));
2981         if (bp->common.int_block == INT_BLOCK_HC) {
2982                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2983                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2984         } else if (!CHIP_IS_E1x(bp)) {
2985                 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2986                 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2987         }
2988
2989         bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2990 }
2991
2992 /* end of Link */
2993
2994 /* slow path */
2995
2996 /*
2997  * General service functions
2998  */
2999
3000 /* send the MCP a request, block until there is a reply */
3001 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
3002 {
3003         int mb_idx = BP_FW_MB_IDX(bp);
3004         u32 seq;
3005         u32 rc = 0;
3006         u32 cnt = 1;
3007         u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
3008
3009         mutex_lock(&bp->fw_mb_mutex);
3010         seq = ++bp->fw_seq;
3011         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
3012         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
3013
3014         DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
3015                         (command | seq), param);
3016
3017         do {
3018                 /* let the FW do it's magic ... */
3019                 msleep(delay);
3020
3021                 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
3022
3023                 /* Give the FW up to 5 second (500*10ms) */
3024         } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
3025
3026         DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
3027            cnt*delay, rc, seq);
3028
3029         /* is this a reply to our command? */
3030         if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
3031                 rc &= FW_MSG_CODE_MASK;
3032         else {
3033                 /* FW BUG! */
3034                 BNX2X_ERR("FW failed to respond!\n");
3035                 bnx2x_fw_dump(bp);
3036                 rc = 0;
3037         }
3038         mutex_unlock(&bp->fw_mb_mutex);
3039
3040         return rc;
3041 }
3042
3043 static void storm_memset_func_cfg(struct bnx2x *bp,
3044                                  struct tstorm_eth_function_common_config *tcfg,
3045                                  u16 abs_fid)
3046 {
3047         size_t size = sizeof(struct tstorm_eth_function_common_config);
3048
3049         u32 addr = BAR_TSTRORM_INTMEM +
3050                         TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
3051
3052         __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
3053 }
3054
3055 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
3056 {
3057         if (CHIP_IS_E1x(bp)) {
3058                 struct tstorm_eth_function_common_config tcfg = {0};
3059
3060                 storm_memset_func_cfg(bp, &tcfg, p->func_id);
3061         }
3062
3063         /* Enable the function in the FW */
3064         storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
3065         storm_memset_func_en(bp, p->func_id, 1);
3066
3067         /* spq */
3068         if (p->func_flgs & FUNC_FLG_SPQ) {
3069                 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
3070                 REG_WR(bp, XSEM_REG_FAST_MEMORY +
3071                        XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
3072         }
3073 }
3074
3075 /**
3076  * bnx2x_get_common_flags - Return common flags
3077  *
3078  * @bp          device handle
3079  * @fp          queue handle
3080  * @zero_stats  TRUE if statistics zeroing is needed
3081  *
3082  * Return the flags that are common for the Tx-only and not normal connections.
3083  */
3084 static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
3085                                             struct bnx2x_fastpath *fp,
3086                                             bool zero_stats)
3087 {
3088         unsigned long flags = 0;
3089
3090         /* PF driver will always initialize the Queue to an ACTIVE state */
3091         __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
3092
3093         /* tx only connections collect statistics (on the same index as the
3094          * parent connection). The statistics are zeroed when the parent
3095          * connection is initialized.
3096          */
3097
3098         __set_bit(BNX2X_Q_FLG_STATS, &flags);
3099         if (zero_stats)
3100                 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
3101
3102         if (bp->flags & TX_SWITCHING)
3103                 __set_bit(BNX2X_Q_FLG_TX_SWITCH, &flags);
3104
3105         __set_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, &flags);
3106         __set_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, &flags);
3107
3108 #ifdef BNX2X_STOP_ON_ERROR
3109         __set_bit(BNX2X_Q_FLG_TX_SEC, &flags);
3110 #endif
3111
3112         return flags;
3113 }
3114
3115 static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
3116                                        struct bnx2x_fastpath *fp,
3117                                        bool leading)
3118 {
3119         unsigned long flags = 0;
3120
3121         /* calculate other queue flags */
3122         if (IS_MF_SD(bp))
3123                 __set_bit(BNX2X_Q_FLG_OV, &flags);
3124
3125         if (IS_FCOE_FP(fp)) {
3126                 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
3127                 /* For FCoE - force usage of default priority (for afex) */
3128                 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
3129         }
3130
3131         if (!fp->disable_tpa) {
3132                 __set_bit(BNX2X_Q_FLG_TPA, &flags);
3133                 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
3134                 if (fp->mode == TPA_MODE_GRO)
3135                         __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
3136         }
3137
3138         if (leading) {
3139                 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
3140                 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
3141         }
3142
3143         /* Always set HW VLAN stripping */
3144         __set_bit(BNX2X_Q_FLG_VLAN, &flags);
3145
3146         /* configure silent vlan removal */
3147         if (IS_MF_AFEX(bp))
3148                 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
3149
3150         return flags | bnx2x_get_common_flags(bp, fp, true);
3151 }
3152
3153 static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
3154         struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
3155         u8 cos)
3156 {
3157         gen_init->stat_id = bnx2x_stats_id(fp);
3158         gen_init->spcl_id = fp->cl_id;
3159
3160         /* Always use mini-jumbo MTU for FCoE L2 ring */
3161         if (IS_FCOE_FP(fp))
3162                 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
3163         else
3164                 gen_init->mtu = bp->dev->mtu;
3165
3166         gen_init->cos = cos;
3167 }
3168
3169 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
3170         struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
3171         struct bnx2x_rxq_setup_params *rxq_init)
3172 {
3173         u8 max_sge = 0;
3174         u16 sge_sz = 0;
3175         u16 tpa_agg_size = 0;
3176
3177         if (!fp->disable_tpa) {
3178                 pause->sge_th_lo = SGE_TH_LO(bp);
3179                 pause->sge_th_hi = SGE_TH_HI(bp);
3180
3181                 /* validate SGE ring has enough to cross high threshold */
3182                 WARN_ON(bp->dropless_fc &&
3183                                 pause->sge_th_hi + FW_PREFETCH_CNT >
3184                                 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
3185
3186                 tpa_agg_size = TPA_AGG_SIZE;
3187                 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
3188                         SGE_PAGE_SHIFT;
3189                 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
3190                           (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
3191                 sge_sz = (u16)min_t(u32, SGE_PAGES, 0xffff);
3192         }
3193
3194         /* pause - not for e1 */
3195         if (!CHIP_IS_E1(bp)) {
3196                 pause->bd_th_lo = BD_TH_LO(bp);
3197                 pause->bd_th_hi = BD_TH_HI(bp);
3198
3199                 pause->rcq_th_lo = RCQ_TH_LO(bp);
3200                 pause->rcq_th_hi = RCQ_TH_HI(bp);
3201                 /*
3202                  * validate that rings have enough entries to cross
3203                  * high thresholds
3204                  */
3205                 WARN_ON(bp->dropless_fc &&
3206                                 pause->bd_th_hi + FW_PREFETCH_CNT >
3207                                 bp->rx_ring_size);
3208                 WARN_ON(bp->dropless_fc &&
3209                                 pause->rcq_th_hi + FW_PREFETCH_CNT >
3210                                 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
3211
3212                 pause->pri_map = 1;
3213         }
3214
3215         /* rxq setup */
3216         rxq_init->dscr_map = fp->rx_desc_mapping;
3217         rxq_init->sge_map = fp->rx_sge_mapping;
3218         rxq_init->rcq_map = fp->rx_comp_mapping;
3219         rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
3220
3221         /* This should be a maximum number of data bytes that may be
3222          * placed on the BD (not including paddings).
3223          */
3224         rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
3225                            BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
3226
3227         rxq_init->cl_qzone_id = fp->cl_qzone_id;
3228         rxq_init->tpa_agg_sz = tpa_agg_size;
3229         rxq_init->sge_buf_sz = sge_sz;
3230         rxq_init->max_sges_pkt = max_sge;
3231         rxq_init->rss_engine_id = BP_FUNC(bp);
3232         rxq_init->mcast_engine_id = BP_FUNC(bp);
3233
3234         /* Maximum number or simultaneous TPA aggregation for this Queue.
3235          *
3236          * For PF Clients it should be the maximum available number.
3237          * VF driver(s) may want to define it to a smaller value.
3238          */
3239         rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
3240
3241         rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
3242         rxq_init->fw_sb_id = fp->fw_sb_id;
3243
3244         if (IS_FCOE_FP(fp))
3245                 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
3246         else
3247                 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
3248         /* configure silent vlan removal
3249          * if multi function mode is afex, then mask default vlan
3250          */
3251         if (IS_MF_AFEX(bp)) {
3252                 rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
3253                 rxq_init->silent_removal_mask = VLAN_VID_MASK;
3254         }
3255 }
3256
3257 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
3258         struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
3259         u8 cos)
3260 {
3261         txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
3262         txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
3263         txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
3264         txq_init->fw_sb_id = fp->fw_sb_id;
3265
3266         /*
3267          * set the tss leading client id for TX classification ==
3268          * leading RSS client id
3269          */
3270         txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
3271
3272         if (IS_FCOE_FP(fp)) {
3273                 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
3274                 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
3275         }
3276 }
3277
3278 static void bnx2x_pf_init(struct bnx2x *bp)
3279 {
3280         struct bnx2x_func_init_params func_init = {0};
3281         struct event_ring_data eq_data = { {0} };
3282         u16 flags;
3283
3284         if (!CHIP_IS_E1x(bp)) {
3285                 /* reset IGU PF statistics: MSIX + ATTN */
3286                 /* PF */
3287                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3288                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3289                            (CHIP_MODE_IS_4_PORT(bp) ?
3290                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3291                 /* ATTN */
3292                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3293                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3294                            BNX2X_IGU_STAS_MSG_PF_CNT*4 +
3295                            (CHIP_MODE_IS_4_PORT(bp) ?
3296                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3297         }
3298
3299         /* function setup flags */
3300         flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
3301
3302         /* This flag is relevant for E1x only.
3303          * E2 doesn't have a TPA configuration in a function level.
3304          */
3305         flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
3306
3307         func_init.func_flgs = flags;
3308         func_init.pf_id = BP_FUNC(bp);
3309         func_init.func_id = BP_FUNC(bp);
3310         func_init.spq_map = bp->spq_mapping;
3311         func_init.spq_prod = bp->spq_prod_idx;
3312
3313         bnx2x_func_init(bp, &func_init);
3314
3315         memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
3316
3317         /*
3318          * Congestion management values depend on the link rate
3319          * There is no active link so initial link rate is set to 10 Gbps.
3320          * When the link comes up The congestion management values are
3321          * re-calculated according to the actual link rate.
3322          */
3323         bp->link_vars.line_speed = SPEED_10000;
3324         bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
3325
3326         /* Only the PMF sets the HW */
3327         if (bp->port.pmf)
3328                 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3329
3330         /* init Event Queue - PCI bus guarantees correct endianity*/
3331         eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
3332         eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
3333         eq_data.producer = bp->eq_prod;
3334         eq_data.index_id = HC_SP_INDEX_EQ_CONS;
3335         eq_data.sb_id = DEF_SB_ID;
3336         storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3337 }
3338
3339 static void bnx2x_e1h_disable(struct bnx2x *bp)
3340 {
3341         int port = BP_PORT(bp);
3342
3343         bnx2x_tx_disable(bp);
3344
3345         REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
3346 }
3347
3348 static void bnx2x_e1h_enable(struct bnx2x *bp)
3349 {
3350         int port = BP_PORT(bp);
3351
3352         if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)))
3353                 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
3354
3355         /* Tx queue should be only re-enabled */
3356         netif_tx_wake_all_queues(bp->dev);
3357
3358         /*
3359          * Should not call netif_carrier_on since it will be called if the link
3360          * is up when checking for link state
3361          */
3362 }
3363
3364 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3365
3366 static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3367 {
3368         struct eth_stats_info *ether_stat =
3369                 &bp->slowpath->drv_info_to_mcp.ether_stat;
3370         struct bnx2x_vlan_mac_obj *mac_obj =
3371                 &bp->sp_objs->mac_obj;
3372         int i;
3373
3374         strlcpy(ether_stat->version, DRV_MODULE_VERSION,
3375                 ETH_STAT_INFO_VERSION_LEN);
3376
3377         /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the
3378          * mac_local field in ether_stat struct. The base address is offset by 2
3379          * bytes to account for the field being 8 bytes but a mac address is
3380          * only 6 bytes. Likewise, the stride for the get_n_elements function is
3381          * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes
3382          * allocated by the ether_stat struct, so the macs will land in their
3383          * proper positions.
3384          */
3385         for (i = 0; i < DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED; i++)
3386                 memset(ether_stat->mac_local + i, 0,
3387                        sizeof(ether_stat->mac_local[0]));
3388         mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3389                                 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3390                                 ether_stat->mac_local + MAC_PAD, MAC_PAD,
3391                                 ETH_ALEN);
3392         ether_stat->mtu_size = bp->dev->mtu;
3393         if (bp->dev->features & NETIF_F_RXCSUM)
3394                 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3395         if (bp->dev->features & NETIF_F_TSO)
3396                 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3397         ether_stat->feature_flags |= bp->common.boot_mode;
3398
3399         ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3400
3401         ether_stat->txq_size = bp->tx_ring_size;
3402         ether_stat->rxq_size = bp->rx_ring_size;
3403
3404 #ifdef CONFIG_BNX2X_SRIOV
3405         ether_stat->vf_cnt = IS_SRIOV(bp) ? bp->vfdb->sriov.nr_virtfn : 0;
3406 #endif
3407 }
3408
3409 static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3410 {
3411         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3412         struct fcoe_stats_info *fcoe_stat =
3413                 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3414
3415         if (!CNIC_LOADED(bp))
3416                 return;
3417
3418         memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN);
3419
3420         fcoe_stat->qos_priority =
3421                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
3422
3423         /* insert FCoE stats from ramrod response */
3424         if (!NO_FCOE(bp)) {
3425                 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
3426                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3427                         tstorm_queue_statistics;
3428
3429                 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
3430                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3431                         xstorm_queue_statistics;
3432
3433                 struct fcoe_statistics_params *fw_fcoe_stat =
3434                         &bp->fw_stats_data->fcoe;
3435
3436                 ADD_64_LE(fcoe_stat->rx_bytes_hi, LE32_0,
3437                           fcoe_stat->rx_bytes_lo,
3438                           fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
3439
3440                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3441                           fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3442                           fcoe_stat->rx_bytes_lo,
3443                           fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
3444
3445                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3446                           fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3447                           fcoe_stat->rx_bytes_lo,
3448                           fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
3449
3450                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3451                           fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3452                           fcoe_stat->rx_bytes_lo,
3453                           fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
3454
3455                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3456                           fcoe_stat->rx_frames_lo,
3457                           fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
3458
3459                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3460                           fcoe_stat->rx_frames_lo,
3461                           fcoe_q_tstorm_stats->rcv_ucast_pkts);
3462
3463                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3464                           fcoe_stat->rx_frames_lo,
3465                           fcoe_q_tstorm_stats->rcv_bcast_pkts);
3466
3467                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3468                           fcoe_stat->rx_frames_lo,
3469                           fcoe_q_tstorm_stats->rcv_mcast_pkts);
3470
3471                 ADD_64_LE(fcoe_stat->tx_bytes_hi, LE32_0,
3472                           fcoe_stat->tx_bytes_lo,
3473                           fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
3474
3475                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3476                           fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3477                           fcoe_stat->tx_bytes_lo,
3478                           fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
3479
3480                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3481                           fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3482                           fcoe_stat->tx_bytes_lo,
3483                           fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
3484
3485                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3486                           fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3487                           fcoe_stat->tx_bytes_lo,
3488                           fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
3489
3490                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3491                           fcoe_stat->tx_frames_lo,
3492                           fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
3493
3494                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3495                           fcoe_stat->tx_frames_lo,
3496                           fcoe_q_xstorm_stats->ucast_pkts_sent);
3497
3498                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3499                           fcoe_stat->tx_frames_lo,
3500                           fcoe_q_xstorm_stats->bcast_pkts_sent);
3501
3502                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3503                           fcoe_stat->tx_frames_lo,
3504                           fcoe_q_xstorm_stats->mcast_pkts_sent);
3505         }
3506
3507         /* ask L5 driver to add data to the struct */
3508         bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
3509 }
3510
3511 static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3512 {
3513         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3514         struct iscsi_stats_info *iscsi_stat =
3515                 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3516
3517         if (!CNIC_LOADED(bp))
3518                 return;
3519
3520         memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac,
3521                ETH_ALEN);
3522
3523         iscsi_stat->qos_priority =
3524                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3525
3526         /* ask L5 driver to add data to the struct */
3527         bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
3528 }
3529
3530 /* called due to MCP event (on pmf):
3531  *      reread new bandwidth configuration
3532  *      configure FW
3533  *      notify others function about the change
3534  */
3535 static void bnx2x_config_mf_bw(struct bnx2x *bp)
3536 {
3537         if (bp->link_vars.link_up) {
3538                 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3539                 bnx2x_link_sync_notify(bp);
3540         }
3541         storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3542 }
3543
3544 static void bnx2x_set_mf_bw(struct bnx2x *bp)
3545 {
3546         bnx2x_config_mf_bw(bp);
3547         bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3548 }
3549
3550 static void bnx2x_handle_eee_event(struct bnx2x *bp)
3551 {
3552         DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3553         bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3554 }
3555
3556 #define BNX2X_UPDATE_DRV_INFO_IND_LENGTH        (20)
3557 #define BNX2X_UPDATE_DRV_INFO_IND_COUNT         (25)
3558
3559 static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3560 {
3561         enum drv_info_opcode op_code;
3562         u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
3563         bool release = false;
3564         int wait;
3565
3566         /* if drv_info version supported by MFW doesn't match - send NACK */
3567         if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3568                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3569                 return;
3570         }
3571
3572         op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3573                   DRV_INFO_CONTROL_OP_CODE_SHIFT;
3574
3575         /* Must prevent other flows from accessing drv_info_to_mcp */
3576         mutex_lock(&bp->drv_info_mutex);
3577
3578         memset(&bp->slowpath->drv_info_to_mcp, 0,
3579                sizeof(union drv_info_to_mcp));
3580
3581         switch (op_code) {
3582         case ETH_STATS_OPCODE:
3583                 bnx2x_drv_info_ether_stat(bp);
3584                 break;
3585         case FCOE_STATS_OPCODE:
3586                 bnx2x_drv_info_fcoe_stat(bp);
3587                 break;
3588         case ISCSI_STATS_OPCODE:
3589                 bnx2x_drv_info_iscsi_stat(bp);
3590                 break;
3591         default:
3592                 /* if op code isn't supported - send NACK */
3593                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3594                 goto out;
3595         }
3596
3597         /* if we got drv_info attn from MFW then these fields are defined in
3598          * shmem2 for sure
3599          */
3600         SHMEM2_WR(bp, drv_info_host_addr_lo,
3601                 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3602         SHMEM2_WR(bp, drv_info_host_addr_hi,
3603                 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3604
3605         bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3606
3607         /* Since possible management wants both this and get_driver_version
3608          * need to wait until management notifies us it finished utilizing
3609          * the buffer.
3610          */
3611         if (!SHMEM2_HAS(bp, mfw_drv_indication)) {
3612                 DP(BNX2X_MSG_MCP, "Management does not support indication\n");
3613         } else if (!bp->drv_info_mng_owner) {
3614                 u32 bit = MFW_DRV_IND_READ_DONE_OFFSET((BP_ABS_FUNC(bp) >> 1));
3615
3616                 for (wait = 0; wait < BNX2X_UPDATE_DRV_INFO_IND_COUNT; wait++) {
3617                         u32 indication = SHMEM2_RD(bp, mfw_drv_indication);
3618
3619                         /* Management is done; need to clear indication */
3620                         if (indication & bit) {
3621                                 SHMEM2_WR(bp, mfw_drv_indication,
3622                                           indication & ~bit);
3623                                 release = true;
3624                                 break;
3625                         }
3626
3627                         msleep(BNX2X_UPDATE_DRV_INFO_IND_LENGTH);
3628                 }
3629         }
3630         if (!release) {
3631                 DP(BNX2X_MSG_MCP, "Management did not release indication\n");
3632                 bp->drv_info_mng_owner = true;
3633         }
3634
3635 out:
3636         mutex_unlock(&bp->drv_info_mutex);
3637 }
3638
3639 static u32 bnx2x_update_mng_version_utility(u8 *version, bool bnx2x_format)
3640 {
3641         u8 vals[4];
3642         int i = 0;
3643
3644         if (bnx2x_format) {
3645                 i = sscanf(version, "1.%c%hhd.%hhd.%hhd",
3646                            &vals[0], &vals[1], &vals[2], &vals[3]);
3647                 if (i > 0)
3648                         vals[0] -= '0';
3649         } else {
3650                 i = sscanf(version, "%hhd.%hhd.%hhd.%hhd",
3651                            &vals[0], &vals[1], &vals[2], &vals[3]);
3652         }
3653
3654         while (i < 4)
3655                 vals[i++] = 0;
3656
3657         return (vals[0] << 24) | (vals[1] << 16) | (vals[2] << 8) | vals[3];
3658 }
3659
3660 void bnx2x_update_mng_version(struct bnx2x *bp)
3661 {
3662         u32 iscsiver = DRV_VER_NOT_LOADED;
3663         u32 fcoever = DRV_VER_NOT_LOADED;
3664         u32 ethver = DRV_VER_NOT_LOADED;
3665         int idx = BP_FW_MB_IDX(bp);
3666         u8 *version;
3667
3668         if (!SHMEM2_HAS(bp, func_os_drv_ver))
3669                 return;
3670
3671         mutex_lock(&bp->drv_info_mutex);
3672         /* Must not proceed when `bnx2x_handle_drv_info_req' is feasible */
3673         if (bp->drv_info_mng_owner)
3674                 goto out;
3675
3676         if (bp->state != BNX2X_STATE_OPEN)
3677                 goto out;
3678
3679         /* Parse ethernet driver version */
3680         ethver = bnx2x_update_mng_version_utility(DRV_MODULE_VERSION, true);
3681         if (!CNIC_LOADED(bp))
3682                 goto out;
3683
3684         /* Try getting storage driver version via cnic */
3685         memset(&bp->slowpath->drv_info_to_mcp, 0,
3686                sizeof(union drv_info_to_mcp));
3687         bnx2x_drv_info_iscsi_stat(bp);
3688         version = bp->slowpath->drv_info_to_mcp.iscsi_stat.version;
3689         iscsiver = bnx2x_update_mng_version_utility(version, false);
3690
3691         memset(&bp->slowpath->drv_info_to_mcp, 0,
3692                sizeof(union drv_info_to_mcp));
3693         bnx2x_drv_info_fcoe_stat(bp);
3694         version = bp->slowpath->drv_info_to_mcp.fcoe_stat.version;
3695         fcoever = bnx2x_update_mng_version_utility(version, false);
3696
3697 out:
3698         SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ETHERNET], ethver);
3699         SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ISCSI], iscsiver);
3700         SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_FCOE], fcoever);
3701
3702         mutex_unlock(&bp->drv_info_mutex);
3703
3704         DP(BNX2X_MSG_MCP, "Setting driver version: ETH [%08x] iSCSI [%08x] FCoE [%08x]\n",
3705            ethver, iscsiver, fcoever);
3706 }
3707
3708 static void bnx2x_oem_event(struct bnx2x *bp, u32 event)
3709 {
3710         u32 cmd_ok, cmd_fail;
3711
3712         /* sanity */
3713         if (event & DRV_STATUS_DCC_EVENT_MASK &&
3714             event & DRV_STATUS_OEM_EVENT_MASK) {
3715                 BNX2X_ERR("Received simultaneous events %08x\n", event);
3716                 return;
3717         }
3718
3719         if (event & DRV_STATUS_DCC_EVENT_MASK) {
3720                 cmd_fail = DRV_MSG_CODE_DCC_FAILURE;
3721                 cmd_ok = DRV_MSG_CODE_DCC_OK;
3722         } else /* if (event & DRV_STATUS_OEM_EVENT_MASK) */ {
3723                 cmd_fail = DRV_MSG_CODE_OEM_FAILURE;
3724                 cmd_ok = DRV_MSG_CODE_OEM_OK;
3725         }
3726
3727         DP(BNX2X_MSG_MCP, "oem_event 0x%x\n", event);
3728
3729         if (event & (DRV_STATUS_DCC_DISABLE_ENABLE_PF |
3730                      DRV_STATUS_OEM_DISABLE_ENABLE_PF)) {
3731                 /* This is the only place besides the function initialization
3732                  * where the bp->flags can change so it is done without any
3733                  * locks
3734                  */
3735                 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
3736                         DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
3737                         bp->flags |= MF_FUNC_DIS;
3738
3739                         bnx2x_e1h_disable(bp);
3740                 } else {
3741                         DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
3742                         bp->flags &= ~MF_FUNC_DIS;
3743
3744                         bnx2x_e1h_enable(bp);
3745                 }
3746                 event &= ~(DRV_STATUS_DCC_DISABLE_ENABLE_PF |
3747                            DRV_STATUS_OEM_DISABLE_ENABLE_PF);
3748         }
3749
3750         if (event & (DRV_STATUS_DCC_BANDWIDTH_ALLOCATION |
3751                      DRV_STATUS_OEM_BANDWIDTH_ALLOCATION)) {
3752                 bnx2x_config_mf_bw(bp);
3753                 event &= ~(DRV_STATUS_DCC_BANDWIDTH_ALLOCATION |
3754                            DRV_STATUS_OEM_BANDWIDTH_ALLOCATION);
3755         }
3756
3757         /* Report results to MCP */
3758         if (event)
3759                 bnx2x_fw_command(bp, cmd_fail, 0);
3760         else
3761                 bnx2x_fw_command(bp, cmd_ok, 0);
3762 }
3763
3764 /* must be called under the spq lock */
3765 static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
3766 {
3767         struct eth_spe *next_spe = bp->spq_prod_bd;
3768
3769         if (bp->spq_prod_bd == bp->spq_last_bd) {
3770                 bp->spq_prod_bd = bp->spq;
3771                 bp->spq_prod_idx = 0;
3772                 DP(BNX2X_MSG_SP, "end of spq\n");
3773         } else {
3774                 bp->spq_prod_bd++;
3775                 bp->spq_prod_idx++;
3776         }
3777         return next_spe;
3778 }
3779
3780 /* must be called under the spq lock */
3781 static void bnx2x_sp_prod_update(struct bnx2x *bp)
3782 {
3783         int func = BP_FUNC(bp);
3784
3785         /*
3786          * Make sure that BD data is updated before writing the producer:
3787          * BD data is written to the memory, the producer is read from the
3788          * memory, thus we need a full memory barrier to ensure the ordering.
3789          */
3790         mb();
3791
3792         REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
3793                  bp->spq_prod_idx);
3794         mmiowb();
3795 }
3796
3797 /**
3798  * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3799  *
3800  * @cmd:        command to check
3801  * @cmd_type:   command type
3802  */
3803 static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3804 {
3805         if ((cmd_type == NONE_CONNECTION_TYPE) ||
3806             (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
3807             (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3808             (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3809             (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3810             (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3811             (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3812                 return true;
3813         else
3814                 return false;
3815 }
3816
3817 /**
3818  * bnx2x_sp_post - place a single command on an SP ring
3819  *
3820  * @bp:         driver handle
3821  * @command:    command to place (e.g. SETUP, FILTER_RULES, etc.)
3822  * @cid:        SW CID the command is related to
3823  * @data_hi:    command private data address (high 32 bits)
3824  * @data_lo:    command private data address (low 32 bits)
3825  * @cmd_type:   command type (e.g. NONE, ETH)
3826  *
3827  * SP data is handled as if it's always an address pair, thus data fields are
3828  * not swapped to little endian in upper functions. Instead this function swaps
3829  * data as if it's two u32 fields.
3830  */
3831 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3832                   u32 data_hi, u32 data_lo, int cmd_type)
3833 {
3834         struct eth_spe *spe;
3835         u16 type;
3836         bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3837
3838 #ifdef BNX2X_STOP_ON_ERROR
3839         if (unlikely(bp->panic)) {
3840                 BNX2X_ERR("Can't post SP when there is panic\n");
3841                 return -EIO;
3842         }
3843 #endif
3844
3845         spin_lock_bh(&bp->spq_lock);
3846
3847         if (common) {
3848                 if (!atomic_read(&bp->eq_spq_left)) {
3849                         BNX2X_ERR("BUG! EQ ring full!\n");
3850                         spin_unlock_bh(&bp->spq_lock);
3851                         bnx2x_panic();
3852                         return -EBUSY;
3853                 }
3854         } else if (!atomic_read(&bp->cq_spq_left)) {
3855                         BNX2X_ERR("BUG! SPQ ring full!\n");
3856                         spin_unlock_bh(&bp->spq_lock);
3857                         bnx2x_panic();
3858                         return -EBUSY;
3859         }
3860
3861         spe = bnx2x_sp_get_next(bp);
3862
3863         /* CID needs port number to be encoded int it */
3864         spe->hdr.conn_and_cmd_data =
3865                         cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3866                                     HW_CID(bp, cid));
3867
3868         /* In some cases, type may already contain the func-id
3869          * mainly in SRIOV related use cases, so we add it here only
3870          * if it's not already set.
3871          */
3872         if (!(cmd_type & SPE_HDR_FUNCTION_ID)) {
3873                 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) &
3874                         SPE_HDR_CONN_TYPE;
3875                 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3876                          SPE_HDR_FUNCTION_ID);
3877         } else {
3878                 type = cmd_type;
3879         }
3880
3881         spe->hdr.type = cpu_to_le16(type);
3882
3883         spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3884         spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3885
3886         /*
3887          * It's ok if the actual decrement is issued towards the memory
3888          * somewhere between the spin_lock and spin_unlock. Thus no
3889          * more explicit memory barrier is needed.
3890          */
3891         if (common)
3892                 atomic_dec(&bp->eq_spq_left);
3893         else
3894                 atomic_dec(&bp->cq_spq_left);
3895
3896         DP(BNX2X_MSG_SP,
3897            "SPQE[%x] (%x:%x)  (cmd, common?) (%d,%d)  hw_cid %x  data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
3898            bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3899            (u32)(U64_LO(bp->spq_mapping) +
3900            (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
3901            HW_CID(bp, cid), data_hi, data_lo, type,
3902            atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
3903
3904         bnx2x_sp_prod_update(bp);
3905         spin_unlock_bh(&bp->spq_lock);
3906         return 0;
3907 }
3908
3909 /* acquire split MCP access lock register */
3910 static int bnx2x_acquire_alr(struct bnx2x *bp)
3911 {
3912         u32 j, val;
3913         int rc = 0;
3914
3915         might_sleep();
3916         for (j = 0; j < 1000; j++) {
3917                 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, MCPR_ACCESS_LOCK_LOCK);
3918                 val = REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK);
3919                 if (val & MCPR_ACCESS_LOCK_LOCK)
3920                         break;
3921
3922                 usleep_range(5000, 10000);
3923         }
3924         if (!(val & MCPR_ACCESS_LOCK_LOCK)) {
3925                 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3926                 rc = -EBUSY;
3927         }
3928
3929         return rc;
3930 }
3931
3932 /* release split MCP access lock register */
3933 static void bnx2x_release_alr(struct bnx2x *bp)
3934 {
3935         REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
3936 }
3937
3938 #define BNX2X_DEF_SB_ATT_IDX    0x0001
3939 #define BNX2X_DEF_SB_IDX        0x0002
3940
3941 static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3942 {
3943         struct host_sp_status_block *def_sb = bp->def_status_blk;
3944         u16 rc = 0;
3945
3946         barrier(); /* status block is written to by the chip */
3947         if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3948                 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3949                 rc |= BNX2X_DEF_SB_ATT_IDX;
3950         }
3951
3952         if (bp->def_idx != def_sb->sp_sb.running_index) {
3953                 bp->def_idx = def_sb->sp_sb.running_index;
3954                 rc |= BNX2X_DEF_SB_IDX;
3955         }
3956
3957         /* Do not reorder: indices reading should complete before handling */
3958         barrier();
3959         return rc;
3960 }
3961
3962 /*
3963  * slow path service functions
3964  */
3965
3966 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3967 {
3968         int port = BP_PORT(bp);
3969         u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3970                               MISC_REG_AEU_MASK_ATTN_FUNC_0;
3971         u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3972                                        NIG_REG_MASK_INTERRUPT_PORT0;
3973         u32 aeu_mask;
3974         u32 nig_mask = 0;
3975         u32 reg_addr;
3976
3977         if (bp->attn_state & asserted)
3978                 BNX2X_ERR("IGU ERROR\n");
3979
3980         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3981         aeu_mask = REG_RD(bp, aeu_addr);
3982
3983         DP(NETIF_MSG_HW, "aeu_mask %x  newly asserted %x\n",
3984            aeu_mask, asserted);
3985         aeu_mask &= ~(asserted & 0x3ff);
3986         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
3987
3988         REG_WR(bp, aeu_addr, aeu_mask);
3989         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3990
3991         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3992         bp->attn_state |= asserted;
3993         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3994
3995         if (asserted & ATTN_HARD_WIRED_MASK) {
3996                 if (asserted & ATTN_NIG_FOR_FUNC) {
3997
3998                         bnx2x_acquire_phy_lock(bp);
3999
4000                         /* save nig interrupt mask */
4001                         nig_mask = REG_RD(bp, nig_int_mask_addr);
4002
4003                         /* If nig_mask is not set, no need to call the update
4004                          * function.
4005                          */
4006                         if (nig_mask) {
4007                                 REG_WR(bp, nig_int_mask_addr, 0);
4008
4009                                 bnx2x_link_attn(bp);
4010                         }
4011
4012                         /* handle unicore attn? */
4013                 }
4014                 if (asserted & ATTN_SW_TIMER_4_FUNC)
4015                         DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
4016
4017                 if (asserted & GPIO_2_FUNC)
4018                         DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
4019
4020                 if (asserted & GPIO_3_FUNC)
4021                         DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
4022
4023                 if (asserted & GPIO_4_FUNC)
4024                         DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
4025
4026                 if (port == 0) {
4027                         if (asserted & ATTN_GENERAL_ATTN_1) {
4028                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
4029                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
4030                         }
4031                         if (asserted & ATTN_GENERAL_ATTN_2) {
4032                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
4033                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
4034                         }
4035                         if (asserted & ATTN_GENERAL_ATTN_3) {
4036                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
4037                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
4038                         }
4039                 } else {
4040                         if (asserted & ATTN_GENERAL_ATTN_4) {
4041                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
4042                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
4043                         }
4044                         if (asserted & ATTN_GENERAL_ATTN_5) {
4045                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
4046                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
4047                         }
4048                         if (asserted & ATTN_GENERAL_ATTN_6) {
4049                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
4050                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
4051                         }
4052                 }
4053
4054         } /* if hardwired */
4055
4056         if (bp->common.int_block == INT_BLOCK_HC)
4057                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4058                             COMMAND_REG_ATTN_BITS_SET);
4059         else
4060                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
4061
4062         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
4063            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4064         REG_WR(bp, reg_addr, asserted);
4065
4066         /* now set back the mask */
4067         if (asserted & ATTN_NIG_FOR_FUNC) {
4068                 /* Verify that IGU ack through BAR was written before restoring
4069                  * NIG mask. This loop should exit after 2-3 iterations max.
4070                  */
4071                 if (bp->common.int_block != INT_BLOCK_HC) {
4072                         u32 cnt = 0, igu_acked;
4073                         do {
4074                                 igu_acked = REG_RD(bp,
4075                                                    IGU_REG_ATTENTION_ACK_BITS);
4076                         } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
4077                                  (++cnt < MAX_IGU_ATTN_ACK_TO));
4078                         if (!igu_acked)
4079                                 DP(NETIF_MSG_HW,
4080                                    "Failed to verify IGU ack on time\n");
4081                         barrier();
4082                 }
4083                 REG_WR(bp, nig_int_mask_addr, nig_mask);
4084                 bnx2x_release_phy_lock(bp);
4085         }
4086 }
4087
4088 static void bnx2x_fan_failure(struct bnx2x *bp)
4089 {
4090         int port = BP_PORT(bp);
4091         u32 ext_phy_config;
4092         /* mark the failure */
4093         ext_phy_config =
4094                 SHMEM_RD(bp,
4095                          dev_info.port_hw_config[port].external_phy_config);
4096
4097         ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
4098         ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
4099         SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
4100                  ext_phy_config);
4101
4102         /* log the failure */
4103         netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
4104                             "Please contact OEM Support for assistance\n");
4105
4106         /* Schedule device reset (unload)
4107          * This is due to some boards consuming sufficient power when driver is
4108          * up to overheat if fan fails.
4109          */
4110         bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_FAN_FAILURE, 0);
4111 }
4112
4113 static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
4114 {
4115         int port = BP_PORT(bp);
4116         int reg_offset;
4117         u32 val;
4118
4119         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4120                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
4121
4122         if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
4123
4124                 val = REG_RD(bp, reg_offset);
4125                 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4126                 REG_WR(bp, reg_offset, val);
4127
4128                 BNX2X_ERR("SPIO5 hw attention\n");
4129
4130                 /* Fan failure attention */
4131                 bnx2x_hw_reset_phy(&bp->link_params);
4132                 bnx2x_fan_failure(bp);
4133         }
4134
4135         if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
4136                 bnx2x_acquire_phy_lock(bp);
4137                 bnx2x_handle_module_detect_int(&bp->link_params);
4138                 bnx2x_release_phy_lock(bp);
4139         }
4140
4141         if (attn & HW_INTERRUT_ASSERT_SET_0) {
4142
4143                 val = REG_RD(bp, reg_offset);
4144                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
4145                 REG_WR(bp, reg_offset, val);
4146
4147                 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
4148                           (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
4149                 bnx2x_panic();
4150         }
4151 }
4152
4153 static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
4154 {
4155         u32 val;
4156
4157         if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
4158
4159                 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
4160                 BNX2X_ERR("DB hw attention 0x%x\n", val);
4161                 /* DORQ discard attention */
4162                 if (val & 0x2)
4163                         BNX2X_ERR("FATAL error from DORQ\n");
4164         }
4165
4166         if (attn & HW_INTERRUT_ASSERT_SET_1) {
4167
4168                 int port = BP_PORT(bp);
4169                 int reg_offset;
4170
4171                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
4172                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
4173
4174                 val = REG_RD(bp, reg_offset);
4175                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
4176                 REG_WR(bp, reg_offset, val);
4177
4178                 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
4179                           (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
4180                 bnx2x_panic();
4181         }
4182 }
4183
4184 static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
4185 {
4186         u32 val;
4187
4188         if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
4189
4190                 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
4191                 BNX2X_ERR("CFC hw attention 0x%x\n", val);
4192                 /* CFC error attention */
4193                 if (val & 0x2)
4194                         BNX2X_ERR("FATAL error from CFC\n");
4195         }
4196
4197         if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
4198                 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
4199                 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
4200                 /* RQ_USDMDP_FIFO_OVERFLOW */
4201                 if (val & 0x18000)
4202                         BNX2X_ERR("FATAL error from PXP\n");
4203
4204                 if (!CHIP_IS_E1x(bp)) {
4205                         val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
4206                         BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
4207                 }
4208         }
4209
4210         if (attn & HW_INTERRUT_ASSERT_SET_2) {
4211
4212                 int port = BP_PORT(bp);
4213                 int reg_offset;
4214
4215                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
4216                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
4217
4218                 val = REG_RD(bp, reg_offset);
4219                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
4220                 REG_WR(bp, reg_offset, val);
4221
4222                 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
4223                           (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
4224                 bnx2x_panic();
4225         }
4226 }
4227
4228 static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
4229 {
4230         u32 val;
4231
4232         if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
4233
4234                 if (attn & BNX2X_PMF_LINK_ASSERT) {
4235                         int func = BP_FUNC(bp);
4236
4237                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
4238                         bnx2x_read_mf_cfg(bp);
4239                         bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
4240                                         func_mf_config[BP_ABS_FUNC(bp)].config);
4241                         val = SHMEM_RD(bp,
4242                                        func_mb[BP_FW_MB_IDX(bp)].drv_status);
4243
4244                         if (val & (DRV_STATUS_DCC_EVENT_MASK |
4245                                    DRV_STATUS_OEM_EVENT_MASK))
4246                                 bnx2x_oem_event(bp,
4247                                         (val & (DRV_STATUS_DCC_EVENT_MASK |
4248                                                 DRV_STATUS_OEM_EVENT_MASK)));
4249
4250                         if (val & DRV_STATUS_SET_MF_BW)
4251                                 bnx2x_set_mf_bw(bp);
4252
4253                         if (val & DRV_STATUS_DRV_INFO_REQ)
4254                                 bnx2x_handle_drv_info_req(bp);
4255
4256                         if (val & DRV_STATUS_VF_DISABLED)
4257                                 bnx2x_schedule_iov_task(bp,
4258                                                         BNX2X_IOV_HANDLE_FLR);
4259
4260                         if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
4261                                 bnx2x_pmf_update(bp);
4262
4263                         if (bp->port.pmf &&
4264                             (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
4265                                 bp->dcbx_enabled > 0)
4266                                 /* start dcbx state machine */
4267                                 bnx2x_dcbx_set_params(bp,
4268                                         BNX2X_DCBX_STATE_NEG_RECEIVED);
4269                         if (val & DRV_STATUS_AFEX_EVENT_MASK)
4270                                 bnx2x_handle_afex_cmd(bp,
4271                                         val & DRV_STATUS_AFEX_EVENT_MASK);
4272                         if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
4273                                 bnx2x_handle_eee_event(bp);
4274
4275                         if (val & DRV_STATUS_OEM_UPDATE_SVID)
4276                                 bnx2x_handle_update_svid_cmd(bp);
4277
4278                         if (bp->link_vars.periodic_flags &
4279                             PERIODIC_FLAGS_LINK_EVENT) {
4280                                 /*  sync with link */
4281                                 bnx2x_acquire_phy_lock(bp);
4282                                 bp->link_vars.periodic_flags &=
4283                                         ~PERIODIC_FLAGS_LINK_EVENT;
4284                                 bnx2x_release_phy_lock(bp);
4285                                 if (IS_MF(bp))
4286                                         bnx2x_link_sync_notify(bp);
4287                                 bnx2x_link_report(bp);
4288                         }
4289                         /* Always call it here: bnx2x_link_report() will
4290                          * prevent the link indication duplication.
4291                          */
4292                         bnx2x__link_status_update(bp);
4293                 } else if (attn & BNX2X_MC_ASSERT_BITS) {
4294
4295                         BNX2X_ERR("MC assert!\n");
4296                         bnx2x_mc_assert(bp);
4297                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
4298                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
4299                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
4300                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
4301                         bnx2x_panic();
4302
4303                 } else if (attn & BNX2X_MCP_ASSERT) {
4304
4305                         BNX2X_ERR("MCP assert!\n");
4306                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
4307                         bnx2x_fw_dump(bp);
4308
4309                 } else
4310                         BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
4311         }
4312
4313         if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
4314                 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
4315                 if (attn & BNX2X_GRC_TIMEOUT) {
4316                         val = CHIP_IS_E1(bp) ? 0 :
4317                                         REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
4318                         BNX2X_ERR("GRC time-out 0x%08x\n", val);
4319                 }
4320                 if (attn & BNX2X_GRC_RSV) {
4321                         val = CHIP_IS_E1(bp) ? 0 :
4322                                         REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
4323                         BNX2X_ERR("GRC reserved 0x%08x\n", val);
4324                 }
4325                 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
4326         }
4327 }
4328
4329 /*
4330  * Bits map:
4331  * 0-7   - Engine0 load counter.
4332  * 8-15  - Engine1 load counter.
4333  * 16    - Engine0 RESET_IN_PROGRESS bit.
4334  * 17    - Engine1 RESET_IN_PROGRESS bit.
4335  * 18    - Engine0 ONE_IS_LOADED. Set when there is at least one active function
4336  *         on the engine
4337  * 19    - Engine1 ONE_IS_LOADED.
4338  * 20    - Chip reset flow bit. When set none-leader must wait for both engines
4339  *         leader to complete (check for both RESET_IN_PROGRESS bits and not for
4340  *         just the one belonging to its engine).
4341  *
4342  */
4343 #define BNX2X_RECOVERY_GLOB_REG         MISC_REG_GENERIC_POR_1
4344
4345 #define BNX2X_PATH0_LOAD_CNT_MASK       0x000000ff
4346 #define BNX2X_PATH0_LOAD_CNT_SHIFT      0
4347 #define BNX2X_PATH1_LOAD_CNT_MASK       0x0000ff00
4348 #define BNX2X_PATH1_LOAD_CNT_SHIFT      8
4349 #define BNX2X_PATH0_RST_IN_PROG_BIT     0x00010000
4350 #define BNX2X_PATH1_RST_IN_PROG_BIT     0x00020000
4351 #define BNX2X_GLOBAL_RESET_BIT          0x00040000
4352
4353 /*
4354  * Set the GLOBAL_RESET bit.
4355  *
4356  * Should be run under rtnl lock
4357  */
4358 void bnx2x_set_reset_global(struct bnx2x *bp)
4359 {
4360         u32 val;
4361         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4362         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4363         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
4364         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4365 }
4366
4367 /*
4368  * Clear the GLOBAL_RESET bit.
4369  *
4370  * Should be run under rtnl lock
4371  */
4372 static void bnx2x_clear_reset_global(struct bnx2x *bp)
4373 {
4374         u32 val;
4375         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4376         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4377         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
4378         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4379 }
4380
4381 /*
4382  * Checks the GLOBAL_RESET bit.
4383  *
4384  * should be run under rtnl lock
4385  */
4386 static bool bnx2x_reset_is_global(struct bnx2x *bp)
4387 {
4388         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4389
4390         DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
4391         return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
4392 }
4393
4394 /*
4395  * Clear RESET_IN_PROGRESS bit for the current engine.
4396  *
4397  * Should be run under rtnl lock
4398  */
4399 static void bnx2x_set_reset_done(struct bnx2x *bp)
4400 {
4401         u32 val;
4402         u32 bit = BP_PATH(bp) ?
4403                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4404         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4405         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4406
4407         /* Clear the bit */
4408         val &= ~bit;
4409         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4410
4411         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4412 }
4413
4414 /*
4415  * Set RESET_IN_PROGRESS for the current engine.
4416  *
4417  * should be run under rtnl lock
4418  */
4419 void bnx2x_set_reset_in_progress(struct bnx2x *bp)
4420 {
4421         u32 val;
4422         u32 bit = BP_PATH(bp) ?
4423                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4424         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4425         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4426
4427         /* Set the bit */
4428         val |= bit;
4429         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4430         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4431 }
4432
4433 /*
4434  * Checks the RESET_IN_PROGRESS bit for the given engine.
4435  * should be run under rtnl lock
4436  */
4437 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
4438 {
4439         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4440         u32 bit = engine ?
4441                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4442
4443         /* return false if bit is set */
4444         return (val & bit) ? false : true;
4445 }
4446
4447 /*
4448  * set pf load for the current pf.
4449  *
4450  * should be run under rtnl lock
4451  */
4452 void bnx2x_set_pf_load(struct bnx2x *bp)
4453 {
4454         u32 val1, val;
4455         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4456                              BNX2X_PATH0_LOAD_CNT_MASK;
4457         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4458                              BNX2X_PATH0_LOAD_CNT_SHIFT;
4459
4460         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4461         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4462
4463         DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
4464
4465         /* get the current counter value */
4466         val1 = (val & mask) >> shift;
4467
4468         /* set bit of that PF */
4469         val1 |= (1 << bp->pf_num);
4470
4471         /* clear the old value */
4472         val &= ~mask;
4473
4474         /* set the new one */
4475         val |= ((val1 << shift) & mask);
4476
4477         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4478         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4479 }
4480
4481 /**
4482  * bnx2x_clear_pf_load - clear pf load mark
4483  *
4484  * @bp:         driver handle
4485  *
4486  * Should be run under rtnl lock.
4487  * Decrements the load counter for the current engine. Returns
4488  * whether other functions are still loaded
4489  */
4490 bool bnx2x_clear_pf_load(struct bnx2x *bp)
4491 {
4492         u32 val1, val;
4493         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4494                              BNX2X_PATH0_LOAD_CNT_MASK;
4495         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4496                              BNX2X_PATH0_LOAD_CNT_SHIFT;
4497
4498         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4499         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4500         DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
4501
4502         /* get the current counter value */
4503         val1 = (val & mask) >> shift;
4504
4505         /* clear bit of that PF */
4506         val1 &= ~(1 << bp->pf_num);
4507
4508         /* clear the old value */
4509         val &= ~mask;
4510
4511         /* set the new one */
4512         val |= ((val1 << shift) & mask);
4513
4514         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4515         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4516         return val1 != 0;
4517 }
4518
4519 /*
4520  * Read the load status for the current engine.
4521  *
4522  * should be run under rtnl lock
4523  */
4524 static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
4525 {
4526         u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4527                              BNX2X_PATH0_LOAD_CNT_MASK);
4528         u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4529                              BNX2X_PATH0_LOAD_CNT_SHIFT);
4530         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4531
4532         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
4533
4534         val = (val & mask) >> shift;
4535
4536         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4537            engine, val);
4538
4539         return val != 0;
4540 }
4541
4542 static void _print_parity(struct bnx2x *bp, u32 reg)
4543 {
4544         pr_cont(" [0x%08x] ", REG_RD(bp, reg));
4545 }
4546
4547 static void _print_next_block(int idx, const char *blk)
4548 {
4549         pr_cont("%s%s", idx ? ", " : "", blk);
4550 }
4551
4552 static bool bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig,
4553                                             int *par_num, bool print)
4554 {
4555         u32 cur_bit;
4556         bool res;
4557         int i;
4558
4559         res = false;
4560
4561         for (i = 0; sig; i++) {
4562                 cur_bit = (0x1UL << i);
4563                 if (sig & cur_bit) {
4564                         res |= true; /* Each bit is real error! */
4565
4566                         if (print) {
4567                                 switch (cur_bit) {
4568                                 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
4569                                         _print_next_block((*par_num)++, "BRB");
4570                                         _print_parity(bp,
4571                                                       BRB1_REG_BRB1_PRTY_STS);
4572                                         break;
4573                                 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
4574                                         _print_next_block((*par_num)++,
4575                                                           "PARSER");
4576                                         _print_parity(bp, PRS_REG_PRS_PRTY_STS);
4577                                         break;
4578                                 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
4579                                         _print_next_block((*par_num)++, "TSDM");
4580                                         _print_parity(bp,
4581                                                       TSDM_REG_TSDM_PRTY_STS);
4582                                         break;
4583                                 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
4584                                         _print_next_block((*par_num)++,
4585                                                           "SEARCHER");
4586                                         _print_parity(bp, SRC_REG_SRC_PRTY_STS);
4587                                         break;
4588                                 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4589                                         _print_next_block((*par_num)++, "TCM");
4590                                         _print_parity(bp, TCM_REG_TCM_PRTY_STS);
4591                                         break;
4592                                 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4593                                         _print_next_block((*par_num)++,
4594                                                           "TSEMI");
4595                                         _print_parity(bp,
4596                                                       TSEM_REG_TSEM_PRTY_STS_0);
4597                                         _print_parity(bp,
4598                                                       TSEM_REG_TSEM_PRTY_STS_1);
4599                                         break;
4600                                 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4601                                         _print_next_block((*par_num)++, "XPB");
4602                                         _print_parity(bp, GRCBASE_XPB +
4603                                                           PB_REG_PB_PRTY_STS);
4604                                         break;
4605                                 }
4606                         }
4607
4608                         /* Clear the bit */
4609                         sig &= ~cur_bit;
4610                 }
4611         }
4612
4613         return res;
4614 }
4615
4616 static bool bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
4617                                             int *par_num, bool *global,
4618                                             bool print)
4619 {
4620         u32 cur_bit;
4621         bool res;
4622         int i;
4623
4624         res = false;
4625
4626         for (i = 0; sig; i++) {
4627                 cur_bit = (0x1UL << i);
4628                 if (sig & cur_bit) {
4629                         res |= true; /* Each bit is real error! */
4630                         switch (cur_bit) {
4631                         case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
4632                                 if (print) {
4633                                         _print_next_block((*par_num)++, "PBF");
4634                                         _print_parity(bp, PBF_REG_PBF_PRTY_STS);
4635                                 }
4636                                 break;
4637                         case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
4638                                 if (print) {
4639                                         _print_next_block((*par_num)++, "QM");
4640                                         _print_parity(bp, QM_REG_QM_PRTY_STS);
4641                                 }
4642                                 break;
4643                         case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
4644                                 if (print) {
4645                                         _print_next_block((*par_num)++, "TM");
4646                                         _print_parity(bp, TM_REG_TM_PRTY_STS);
4647                                 }
4648                                 break;
4649                         case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
4650                                 if (print) {
4651                                         _print_next_block((*par_num)++, "XSDM");
4652                                         _print_parity(bp,
4653                                                       XSDM_REG_XSDM_PRTY_STS);
4654                                 }
4655                                 break;
4656                         case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
4657                                 if (print) {
4658                                         _print_next_block((*par_num)++, "XCM");
4659                                         _print_parity(bp, XCM_REG_XCM_PRTY_STS);
4660                                 }
4661                                 break;
4662                         case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
4663                                 if (print) {
4664                                         _print_next_block((*par_num)++,
4665                                                           "XSEMI");
4666                                         _print_parity(bp,
4667                                                       XSEM_REG_XSEM_PRTY_STS_0);
4668                                         _print_parity(bp,
4669                                                       XSEM_REG_XSEM_PRTY_STS_1);
4670                                 }
4671                                 break;
4672                         case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
4673                                 if (print) {
4674                                         _print_next_block((*par_num)++,
4675                                                           "DOORBELLQ");
4676                                         _print_parity(bp,
4677                                                       DORQ_REG_DORQ_PRTY_STS);
4678                                 }
4679                                 break;
4680                         case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
4681                                 if (print) {
4682                                         _print_next_block((*par_num)++, "NIG");
4683                                         if (CHIP_IS_E1x(bp)) {
4684                                                 _print_parity(bp,
4685                                                         NIG_REG_NIG_PRTY_STS);
4686                                         } else {
4687                                                 _print_parity(bp,
4688                                                         NIG_REG_NIG_PRTY_STS_0);
4689                                                 _print_parity(bp,
4690                                                         NIG_REG_NIG_PRTY_STS_1);
4691                                         }
4692                                 }
4693                                 break;
4694                         case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
4695                                 if (print)
4696                                         _print_next_block((*par_num)++,
4697                                                           "VAUX PCI CORE");
4698                                 *global = true;
4699                                 break;
4700                         case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
4701                                 if (print) {
4702                                         _print_next_block((*par_num)++,
4703                                                           "DEBUG");
4704                                         _print_parity(bp, DBG_REG_DBG_PRTY_STS);
4705                                 }
4706                                 break;
4707                         case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
4708                                 if (print) {
4709                                         _print_next_block((*par_num)++, "USDM");
4710                                         _print_parity(bp,
4711                                                       USDM_REG_USDM_PRTY_STS);
4712                                 }
4713                                 break;
4714                         case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
4715                                 if (print) {
4716                                         _print_next_block((*par_num)++, "UCM");
4717                                         _print_parity(bp, UCM_REG_UCM_PRTY_STS);
4718                                 }
4719                                 break;
4720                         case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
4721                                 if (print) {
4722                                         _print_next_block((*par_num)++,
4723                                                           "USEMI");
4724                                         _print_parity(bp,
4725                                                       USEM_REG_USEM_PRTY_STS_0);
4726                                         _print_parity(bp,
4727                                                       USEM_REG_USEM_PRTY_STS_1);
4728                                 }
4729                                 break;
4730                         case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
4731                                 if (print) {
4732                                         _print_next_block((*par_num)++, "UPB");
4733                                         _print_parity(bp, GRCBASE_UPB +
4734                                                           PB_REG_PB_PRTY_STS);
4735                                 }
4736                                 break;
4737                         case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
4738                                 if (print) {
4739                                         _print_next_block((*par_num)++, "CSDM");
4740                                         _print_parity(bp,
4741                                                       CSDM_REG_CSDM_PRTY_STS);
4742                                 }
4743                                 break;
4744                         case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
4745                                 if (print) {
4746                                         _print_next_block((*par_num)++, "CCM");
4747                                         _print_parity(bp, CCM_REG_CCM_PRTY_STS);
4748                                 }
4749                                 break;
4750                         }
4751
4752                         /* Clear the bit */
4753                         sig &= ~cur_bit;
4754                 }
4755         }
4756
4757         return res;
4758 }
4759
4760 static bool bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig,
4761                                             int *par_num, bool print)
4762 {
4763         u32 cur_bit;
4764         bool res;
4765         int i;
4766
4767         res = false;
4768
4769         for (i = 0; sig; i++) {
4770                 cur_bit = (0x1UL << i);
4771                 if (sig & cur_bit) {
4772                         res = true; /* Each bit is real error! */
4773                         if (print) {
4774                                 switch (cur_bit) {
4775                                 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4776                                         _print_next_block((*par_num)++,
4777                                                           "CSEMI");
4778                                         _print_parity(bp,
4779                                                       CSEM_REG_CSEM_PRTY_STS_0);
4780                                         _print_parity(bp,
4781                                                       CSEM_REG_CSEM_PRTY_STS_1);
4782                                         break;
4783                                 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4784                                         _print_next_block((*par_num)++, "PXP");
4785                                         _print_parity(bp, PXP_REG_PXP_PRTY_STS);
4786                                         _print_parity(bp,
4787                                                       PXP2_REG_PXP2_PRTY_STS_0);
4788                                         _print_parity(bp,
4789                                                       PXP2_REG_PXP2_PRTY_STS_1);
4790                                         break;
4791                                 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4792                                         _print_next_block((*par_num)++,
4793                                                           "PXPPCICLOCKCLIENT");
4794                                         break;
4795                                 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4796                                         _print_next_block((*par_num)++, "CFC");
4797                                         _print_parity(bp,
4798                                                       CFC_REG_CFC_PRTY_STS);
4799                                         break;
4800                                 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4801                                         _print_next_block((*par_num)++, "CDU");
4802                                         _print_parity(bp, CDU_REG_CDU_PRTY_STS);
4803                                         break;
4804                                 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4805                                         _print_next_block((*par_num)++, "DMAE");
4806                                         _print_parity(bp,
4807                                                       DMAE_REG_DMAE_PRTY_STS);
4808                                         break;
4809                                 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4810                                         _print_next_block((*par_num)++, "IGU");
4811                                         if (CHIP_IS_E1x(bp))
4812                                                 _print_parity(bp,
4813                                                         HC_REG_HC_PRTY_STS);
4814                                         else
4815                                                 _print_parity(bp,
4816                                                         IGU_REG_IGU_PRTY_STS);
4817                                         break;
4818                                 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4819                                         _print_next_block((*par_num)++, "MISC");
4820                                         _print_parity(bp,
4821                                                       MISC_REG_MISC_PRTY_STS);
4822                                         break;
4823                                 }
4824                         }
4825
4826                         /* Clear the bit */
4827                         sig &= ~cur_bit;
4828                 }
4829         }
4830
4831         return res;
4832 }
4833
4834 static bool bnx2x_check_blocks_with_parity3(struct bnx2x *bp, u32 sig,
4835                                             int *par_num, bool *global,
4836                                             bool print)
4837 {
4838         bool res = false;
4839         u32 cur_bit;
4840         int i;
4841
4842         for (i = 0; sig; i++) {
4843                 cur_bit = (0x1UL << i);
4844                 if (sig & cur_bit) {
4845                         switch (cur_bit) {
4846                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
4847                                 if (print)
4848                                         _print_next_block((*par_num)++,
4849                                                           "MCP ROM");
4850                                 *global = true;
4851                                 res = true;
4852                                 break;
4853                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
4854                                 if (print)
4855                                         _print_next_block((*par_num)++,
4856                                                           "MCP UMP RX");
4857                                 *global = true;
4858                                 res = true;
4859                                 break;
4860                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
4861                                 if (print)
4862                                         _print_next_block((*par_num)++,
4863                                                           "MCP UMP TX");
4864                                 *global = true;
4865                                 res = true;
4866                                 break;
4867                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
4868                                 if (print)
4869                                         _print_next_block((*par_num)++,
4870                                                           "MCP SCPAD");
4871                                 /* clear latched SCPAD PATIRY from MCP */
4872                                 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL,
4873                                        1UL << 10);
4874                                 break;
4875                         }
4876
4877                         /* Clear the bit */
4878                         sig &= ~cur_bit;
4879                 }
4880         }
4881
4882         return res;
4883 }
4884
4885 static bool bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig,
4886                                             int *par_num, bool print)
4887 {
4888         u32 cur_bit;
4889         bool res;
4890         int i;
4891
4892         res = false;
4893
4894         for (i = 0; sig; i++) {
4895                 cur_bit = (0x1UL << i);
4896                 if (sig & cur_bit) {
4897                         res = true; /* Each bit is real error! */
4898                         if (print) {
4899                                 switch (cur_bit) {
4900                                 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4901                                         _print_next_block((*par_num)++,
4902                                                           "PGLUE_B");
4903                                         _print_parity(bp,
4904                                                       PGLUE_B_REG_PGLUE_B_PRTY_STS);
4905                                         break;
4906                                 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4907                                         _print_next_block((*par_num)++, "ATC");
4908                                         _print_parity(bp,
4909                                                       ATC_REG_ATC_PRTY_STS);
4910                                         break;
4911                                 }
4912                         }
4913                         /* Clear the bit */
4914                         sig &= ~cur_bit;
4915                 }
4916         }
4917
4918         return res;
4919 }
4920
4921 static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4922                               u32 *sig)
4923 {
4924         bool res = false;
4925
4926         if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4927             (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4928             (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4929             (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4930             (sig[4] & HW_PRTY_ASSERT_SET_4)) {
4931                 int par_num = 0;
4932                 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4933                                  "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
4934                           sig[0] & HW_PRTY_ASSERT_SET_0,
4935                           sig[1] & HW_PRTY_ASSERT_SET_1,
4936                           sig[2] & HW_PRTY_ASSERT_SET_2,
4937                           sig[3] & HW_PRTY_ASSERT_SET_3,
4938                           sig[4] & HW_PRTY_ASSERT_SET_4);
4939                 if (print)
4940                         netdev_err(bp->dev,
4941                                    "Parity errors detected in blocks: ");
4942                 res |= bnx2x_check_blocks_with_parity0(bp,
4943                         sig[0] & HW_PRTY_ASSERT_SET_0, &par_num, print);
4944                 res |= bnx2x_check_blocks_with_parity1(bp,
4945                         sig[1] & HW_PRTY_ASSERT_SET_1, &par_num, global, print);
4946                 res |= bnx2x_check_blocks_with_parity2(bp,
4947                         sig[2] & HW_PRTY_ASSERT_SET_2, &par_num, print);
4948                 res |= bnx2x_check_blocks_with_parity3(bp,
4949                         sig[3] & HW_PRTY_ASSERT_SET_3, &par_num, global, print);
4950                 res |= bnx2x_check_blocks_with_parity4(bp,
4951                         sig[4] & HW_PRTY_ASSERT_SET_4, &par_num, print);
4952
4953                 if (print)
4954                         pr_cont("\n");
4955         }
4956
4957         return res;
4958 }
4959
4960 /**
4961  * bnx2x_chk_parity_attn - checks for parity attentions.
4962  *
4963  * @bp:         driver handle
4964  * @global:     true if there was a global attention
4965  * @print:      show parity attention in syslog
4966  */
4967 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
4968 {
4969         struct attn_route attn = { {0} };
4970         int port = BP_PORT(bp);
4971
4972         attn.sig[0] = REG_RD(bp,
4973                 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
4974                              port*4);
4975         attn.sig[1] = REG_RD(bp,
4976                 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
4977                              port*4);
4978         attn.sig[2] = REG_RD(bp,
4979                 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
4980                              port*4);
4981         attn.sig[3] = REG_RD(bp,
4982                 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
4983                              port*4);
4984         /* Since MCP attentions can't be disabled inside the block, we need to
4985          * read AEU registers to see whether they're currently disabled
4986          */
4987         attn.sig[3] &= ((REG_RD(bp,
4988                                 !port ? MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0
4989                                       : MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0) &
4990                          MISC_AEU_ENABLE_MCP_PRTY_BITS) |
4991                         ~MISC_AEU_ENABLE_MCP_PRTY_BITS);
4992
4993         if (!CHIP_IS_E1x(bp))
4994                 attn.sig[4] = REG_RD(bp,
4995                         MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
4996                                      port*4);
4997
4998         return bnx2x_parity_attn(bp, global, print, attn.sig);
4999 }
5000
5001 static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
5002 {
5003         u32 val;
5004         if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
5005
5006                 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
5007                 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
5008                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
5009                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
5010                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
5011                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
5012                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
5013                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
5014                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
5015                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
5016                 if (val &
5017                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
5018                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
5019                 if (val &
5020                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
5021                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
5022                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
5023                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
5024                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
5025                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
5026                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
5027                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
5028         }
5029         if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
5030                 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
5031                 BNX2X_ERR("ATC hw attention 0x%x\n", val);
5032                 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
5033                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
5034                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
5035                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
5036                 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
5037                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
5038                 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
5039                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
5040                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
5041                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
5042                 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
5043                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
5044         }
5045
5046         if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
5047                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
5048                 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
5049                 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
5050                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
5051         }
5052 }
5053
5054 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
5055 {
5056         struct attn_route attn, *group_mask;
5057         int port = BP_PORT(bp);
5058         int index;
5059         u32 reg_addr;
5060         u32 val;
5061         u32 aeu_mask;
5062         bool global = false;
5063
5064         /* need to take HW lock because MCP or other port might also
5065            try to handle this event */
5066         bnx2x_acquire_alr(bp);
5067
5068         if (bnx2x_chk_parity_attn(bp, &global, true)) {
5069 #ifndef BNX2X_STOP_ON_ERROR
5070                 bp->recovery_state = BNX2X_RECOVERY_INIT;
5071                 schedule_delayed_work(&bp->sp_rtnl_task, 0);
5072                 /* Disable HW interrupts */
5073                 bnx2x_int_disable(bp);
5074                 /* In case of parity errors don't handle attentions so that
5075                  * other function would "see" parity errors.
5076                  */
5077 #else
5078                 bnx2x_panic();
5079 #endif
5080                 bnx2x_release_alr(bp);
5081                 return;
5082         }
5083
5084         attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
5085         attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
5086         attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
5087         attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
5088         if (!CHIP_IS_E1x(bp))
5089                 attn.sig[4] =
5090                       REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
5091         else
5092                 attn.sig[4] = 0;
5093
5094         DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
5095            attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
5096
5097         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5098                 if (deasserted & (1 << index)) {
5099                         group_mask = &bp->attn_group[index];
5100
5101                         DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
5102                            index,
5103                            group_mask->sig[0], group_mask->sig[1],
5104                            group_mask->sig[2], group_mask->sig[3],
5105                            group_mask->sig[4]);
5106
5107                         bnx2x_attn_int_deasserted4(bp,
5108                                         attn.sig[4] & group_mask->sig[4]);
5109                         bnx2x_attn_int_deasserted3(bp,
5110                                         attn.sig[3] & group_mask->sig[3]);
5111                         bnx2x_attn_int_deasserted1(bp,
5112                                         attn.sig[1] & group_mask->sig[1]);
5113                         bnx2x_attn_int_deasserted2(bp,
5114                                         attn.sig[2] & group_mask->sig[2]);
5115                         bnx2x_attn_int_deasserted0(bp,
5116                                         attn.sig[0] & group_mask->sig[0]);
5117                 }
5118         }
5119
5120         bnx2x_release_alr(bp);
5121
5122         if (bp->common.int_block == INT_BLOCK_HC)
5123                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
5124                             COMMAND_REG_ATTN_BITS_CLR);
5125         else
5126                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
5127
5128         val = ~deasserted;
5129         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
5130            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
5131         REG_WR(bp, reg_addr, val);
5132
5133         if (~bp->attn_state & deasserted)
5134                 BNX2X_ERR("IGU ERROR\n");
5135
5136         reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
5137                           MISC_REG_AEU_MASK_ATTN_FUNC_0;
5138
5139         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
5140         aeu_mask = REG_RD(bp, reg_addr);
5141
5142         DP(NETIF_MSG_HW, "aeu_mask %x  newly deasserted %x\n",
5143            aeu_mask, deasserted);
5144         aeu_mask |= (deasserted & 0x3ff);
5145         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
5146
5147         REG_WR(bp, reg_addr, aeu_mask);
5148         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
5149
5150         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
5151         bp->attn_state &= ~deasserted;
5152         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
5153 }
5154
5155 static void bnx2x_attn_int(struct bnx2x *bp)
5156 {
5157         /* read local copy of bits */
5158         u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
5159                                                                 attn_bits);
5160         u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
5161                                                                 attn_bits_ack);
5162         u32 attn_state = bp->attn_state;
5163
5164         /* look for changed bits */
5165         u32 asserted   =  attn_bits & ~attn_ack & ~attn_state;
5166         u32 deasserted = ~attn_bits &  attn_ack &  attn_state;
5167
5168         DP(NETIF_MSG_HW,
5169            "attn_bits %x  attn_ack %x  asserted %x  deasserted %x\n",
5170            attn_bits, attn_ack, asserted, deasserted);
5171
5172         if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
5173                 BNX2X_ERR("BAD attention state\n");
5174
5175         /* handle bits that were raised */
5176         if (asserted)
5177                 bnx2x_attn_int_asserted(bp, asserted);
5178
5179         if (deasserted)
5180                 bnx2x_attn_int_deasserted(bp, deasserted);
5181 }
5182
5183 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
5184                       u16 index, u8 op, u8 update)
5185 {
5186         u32 igu_addr = bp->igu_base_addr;
5187         igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
5188         bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
5189                              igu_addr);
5190 }
5191
5192 static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
5193 {
5194         /* No memory barriers */
5195         storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
5196         mmiowb(); /* keep prod updates ordered */
5197 }
5198
5199 static int  bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
5200                                       union event_ring_elem *elem)
5201 {
5202         u8 err = elem->message.error;
5203
5204         if (!bp->cnic_eth_dev.starting_cid  ||
5205             (cid < bp->cnic_eth_dev.starting_cid &&
5206             cid != bp->cnic_eth_dev.iscsi_l2_cid))
5207                 return 1;
5208
5209         DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
5210
5211         if (unlikely(err)) {
5212
5213                 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
5214                           cid);
5215                 bnx2x_panic_dump(bp, false);
5216         }
5217         bnx2x_cnic_cfc_comp(bp, cid, err);
5218         return 0;
5219 }
5220
5221 static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
5222 {
5223         struct bnx2x_mcast_ramrod_params rparam;
5224         int rc;
5225
5226         memset(&rparam, 0, sizeof(rparam));
5227
5228         rparam.mcast_obj = &bp->mcast_obj;
5229
5230         netif_addr_lock_bh(bp->dev);
5231
5232         /* Clear pending state for the last command */
5233         bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
5234
5235         /* If there are pending mcast commands - send them */
5236         if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
5237                 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
5238                 if (rc < 0)
5239                         BNX2X_ERR("Failed to send pending mcast commands: %d\n",
5240                                   rc);
5241         }
5242
5243         netif_addr_unlock_bh(bp->dev);
5244 }
5245
5246 static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
5247                                             union event_ring_elem *elem)
5248 {
5249         unsigned long ramrod_flags = 0;
5250         int rc = 0;
5251         u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
5252         struct bnx2x_vlan_mac_obj *vlan_mac_obj;
5253
5254         /* Always push next commands out, don't wait here */
5255         __set_bit(RAMROD_CONT, &ramrod_flags);
5256
5257         switch (le32_to_cpu((__force __le32)elem->message.data.eth_event.echo)
5258                             >> BNX2X_SWCID_SHIFT) {
5259         case BNX2X_FILTER_MAC_PENDING:
5260                 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
5261                 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp)))
5262                         vlan_mac_obj = &bp->iscsi_l2_mac_obj;
5263                 else
5264                         vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
5265
5266                 break;
5267         case BNX2X_FILTER_MCAST_PENDING:
5268                 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
5269                 /* This is only relevant for 57710 where multicast MACs are
5270                  * configured as unicast MACs using the same ramrod.
5271                  */
5272                 bnx2x_handle_mcast_eqe(bp);
5273                 return;
5274         default:
5275                 BNX2X_ERR("Unsupported classification command: %d\n",
5276                           elem->message.data.eth_event.echo);
5277                 return;
5278         }
5279
5280         rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
5281
5282         if (rc < 0)
5283                 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
5284         else if (rc > 0)
5285                 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
5286 }
5287
5288 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
5289
5290 static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
5291 {
5292         netif_addr_lock_bh(bp->dev);
5293
5294         clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5295
5296         /* Send rx_mode command again if was requested */
5297         if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
5298                 bnx2x_set_storm_rx_mode(bp);
5299         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
5300                                     &bp->sp_state))
5301                 bnx2x_set_iscsi_eth_rx_mode(bp, true);
5302         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
5303                                     &bp->sp_state))
5304                 bnx2x_set_iscsi_eth_rx_mode(bp, false);
5305
5306         netif_addr_unlock_bh(bp->dev);
5307 }
5308
5309 static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
5310                                               union event_ring_elem *elem)
5311 {
5312         if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
5313                 DP(BNX2X_MSG_SP,
5314                    "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
5315                    elem->message.data.vif_list_event.func_bit_map);
5316                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
5317                         elem->message.data.vif_list_event.func_bit_map);
5318         } else if (elem->message.data.vif_list_event.echo ==
5319                    VIF_LIST_RULE_SET) {
5320                 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
5321                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
5322         }
5323 }
5324
5325 /* called with rtnl_lock */
5326 static void bnx2x_after_function_update(struct bnx2x *bp)
5327 {
5328         int q, rc;
5329         struct bnx2x_fastpath *fp;
5330         struct bnx2x_queue_state_params queue_params = {NULL};
5331         struct bnx2x_queue_update_params *q_update_params =
5332                 &queue_params.params.update;
5333
5334         /* Send Q update command with afex vlan removal values for all Qs */
5335         queue_params.cmd = BNX2X_Q_CMD_UPDATE;
5336
5337         /* set silent vlan removal values according to vlan mode */
5338         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
5339                   &q_update_params->update_flags);
5340         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
5341                   &q_update_params->update_flags);
5342         __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5343
5344         /* in access mode mark mask and value are 0 to strip all vlans */
5345         if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
5346                 q_update_params->silent_removal_value = 0;
5347                 q_update_params->silent_removal_mask = 0;
5348         } else {
5349                 q_update_params->silent_removal_value =
5350                         (bp->afex_def_vlan_tag & VLAN_VID_MASK);
5351                 q_update_params->silent_removal_mask = VLAN_VID_MASK;
5352         }
5353
5354         for_each_eth_queue(bp, q) {
5355                 /* Set the appropriate Queue object */
5356                 fp = &bp->fp[q];
5357                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5358
5359                 /* send the ramrod */
5360                 rc = bnx2x_queue_state_change(bp, &queue_params);
5361                 if (rc < 0)
5362                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5363                                   q);
5364         }
5365
5366         if (!NO_FCOE(bp) && CNIC_ENABLED(bp)) {
5367                 fp = &bp->fp[FCOE_IDX(bp)];
5368                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5369
5370                 /* clear pending completion bit */
5371                 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5372
5373                 /* mark latest Q bit */
5374                 smp_mb__before_atomic();
5375                 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
5376                 smp_mb__after_atomic();
5377
5378                 /* send Q update ramrod for FCoE Q */
5379                 rc = bnx2x_queue_state_change(bp, &queue_params);
5380                 if (rc < 0)
5381                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5382                                   q);
5383         } else {
5384                 /* If no FCoE ring - ACK MCP now */
5385                 bnx2x_link_report(bp);
5386                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5387         }
5388 }
5389
5390 static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
5391         struct bnx2x *bp, u32 cid)
5392 {
5393         DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
5394
5395         if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp)))
5396                 return &bnx2x_fcoe_sp_obj(bp, q_obj);
5397         else
5398                 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
5399 }
5400
5401 static void bnx2x_eq_int(struct bnx2x *bp)
5402 {
5403         u16 hw_cons, sw_cons, sw_prod;
5404         union event_ring_elem *elem;
5405         u8 echo;
5406         u32 cid;
5407         u8 opcode;
5408         int rc, spqe_cnt = 0;
5409         struct bnx2x_queue_sp_obj *q_obj;
5410         struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
5411         struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
5412
5413         hw_cons = le16_to_cpu(*bp->eq_cons_sb);
5414
5415         /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
5416          * when we get the next-page we need to adjust so the loop
5417          * condition below will be met. The next element is the size of a
5418          * regular element and hence incrementing by 1
5419          */
5420         if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
5421                 hw_cons++;
5422
5423         /* This function may never run in parallel with itself for a
5424          * specific bp, thus there is no need in "paired" read memory
5425          * barrier here.
5426          */
5427         sw_cons = bp->eq_cons;
5428         sw_prod = bp->eq_prod;
5429
5430         DP(BNX2X_MSG_SP, "EQ:  hw_cons %u  sw_cons %u bp->eq_spq_left %x\n",
5431                         hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
5432
5433         for (; sw_cons != hw_cons;
5434               sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
5435
5436                 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
5437
5438                 rc = bnx2x_iov_eq_sp_event(bp, elem);
5439                 if (!rc) {
5440                         DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n",
5441                            rc);
5442                         goto next_spqe;
5443                 }
5444
5445                 /* elem CID originates from FW; actually LE */
5446                 cid = SW_CID((__force __le32)
5447                              elem->message.data.cfc_del_event.cid);
5448                 opcode = elem->message.opcode;
5449
5450                 /* handle eq element */
5451                 switch (opcode) {
5452                 case EVENT_RING_OPCODE_VF_PF_CHANNEL:
5453                         bnx2x_vf_mbx_schedule(bp,
5454                                               &elem->message.data.vf_pf_event);
5455                         continue;
5456
5457                 case EVENT_RING_OPCODE_STAT_QUERY:
5458                         DP_AND((BNX2X_MSG_SP | BNX2X_MSG_STATS),
5459                                "got statistics comp event %d\n",
5460                                bp->stats_comp++);
5461                         /* nothing to do with stats comp */
5462                         goto next_spqe;
5463
5464                 case EVENT_RING_OPCODE_CFC_DEL:
5465                         /* handle according to cid range */
5466                         /*
5467                          * we may want to verify here that the bp state is
5468                          * HALTING
5469                          */
5470                         DP(BNX2X_MSG_SP,
5471                            "got delete ramrod for MULTI[%d]\n", cid);
5472
5473                         if (CNIC_LOADED(bp) &&
5474                             !bnx2x_cnic_handle_cfc_del(bp, cid, elem))
5475                                 goto next_spqe;
5476
5477                         q_obj = bnx2x_cid_to_q_obj(bp, cid);
5478
5479                         if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
5480                                 break;
5481
5482                         goto next_spqe;
5483
5484                 case EVENT_RING_OPCODE_STOP_TRAFFIC:
5485                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
5486                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
5487                         if (f_obj->complete_cmd(bp, f_obj,
5488                                                 BNX2X_F_CMD_TX_STOP))
5489                                 break;
5490                         goto next_spqe;
5491
5492                 case EVENT_RING_OPCODE_START_TRAFFIC:
5493                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
5494                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
5495                         if (f_obj->complete_cmd(bp, f_obj,
5496                                                 BNX2X_F_CMD_TX_START))
5497                                 break;
5498                         goto next_spqe;
5499
5500                 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
5501                         echo = elem->message.data.function_update_event.echo;
5502                         if (echo == SWITCH_UPDATE) {
5503                                 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5504                                    "got FUNC_SWITCH_UPDATE ramrod\n");
5505                                 if (f_obj->complete_cmd(
5506                                         bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE))
5507                                         break;
5508
5509                         } else {
5510                                 int cmd = BNX2X_SP_RTNL_AFEX_F_UPDATE;
5511
5512                                 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
5513                                    "AFEX: ramrod completed FUNCTION_UPDATE\n");
5514                                 f_obj->complete_cmd(bp, f_obj,
5515                                                     BNX2X_F_CMD_AFEX_UPDATE);
5516
5517                                 /* We will perform the Queues update from
5518                                  * sp_rtnl task as all Queue SP operations
5519                                  * should run under rtnl_lock.
5520                                  */
5521                                 bnx2x_schedule_sp_rtnl(bp, cmd, 0);
5522                         }
5523
5524                         goto next_spqe;
5525
5526                 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
5527                         f_obj->complete_cmd(bp, f_obj,
5528                                             BNX2X_F_CMD_AFEX_VIFLISTS);
5529                         bnx2x_after_afex_vif_lists(bp, elem);
5530                         goto next_spqe;
5531                 case EVENT_RING_OPCODE_FUNCTION_START:
5532                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5533                            "got FUNC_START ramrod\n");
5534                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
5535                                 break;
5536
5537                         goto next_spqe;
5538
5539                 case EVENT_RING_OPCODE_FUNCTION_STOP:
5540                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5541                            "got FUNC_STOP ramrod\n");
5542                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
5543                                 break;
5544
5545                         goto next_spqe;
5546
5547                 case EVENT_RING_OPCODE_SET_TIMESYNC:
5548                         DP(BNX2X_MSG_SP | BNX2X_MSG_PTP,
5549                            "got set_timesync ramrod completion\n");
5550                         if (f_obj->complete_cmd(bp, f_obj,
5551                                                 BNX2X_F_CMD_SET_TIMESYNC))
5552                                 break;
5553                         goto next_spqe;
5554                 }
5555
5556                 switch (opcode | bp->state) {
5557                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5558                       BNX2X_STATE_OPEN):
5559                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5560                       BNX2X_STATE_OPENING_WAIT4_PORT):
5561                         cid = elem->message.data.eth_event.echo &
5562                                 BNX2X_SWCID_MASK;
5563                         DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
5564                            cid);
5565                         rss_raw->clear_pending(rss_raw);
5566                         break;
5567
5568                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
5569                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
5570                 case (EVENT_RING_OPCODE_SET_MAC |
5571                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5572                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5573                       BNX2X_STATE_OPEN):
5574                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5575                       BNX2X_STATE_DIAG):
5576                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5577                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5578                         DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n");
5579                         bnx2x_handle_classification_eqe(bp, elem);
5580                         break;
5581
5582                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5583                       BNX2X_STATE_OPEN):
5584                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5585                       BNX2X_STATE_DIAG):
5586                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5587                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5588                         DP(BNX2X_MSG_SP, "got mcast ramrod\n");
5589                         bnx2x_handle_mcast_eqe(bp);
5590                         break;
5591
5592                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5593                       BNX2X_STATE_OPEN):
5594                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5595                       BNX2X_STATE_DIAG):
5596                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5597                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5598                         DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
5599                         bnx2x_handle_rx_mode_eqe(bp);
5600                         break;
5601                 default:
5602                         /* unknown event log error and continue */
5603                         BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
5604                                   elem->message.opcode, bp->state);
5605                 }
5606 next_spqe:
5607                 spqe_cnt++;
5608         } /* for */
5609
5610         smp_mb__before_atomic();
5611         atomic_add(spqe_cnt, &bp->eq_spq_left);
5612
5613         bp->eq_cons = sw_cons;
5614         bp->eq_prod = sw_prod;
5615         /* Make sure that above mem writes were issued towards the memory */
5616         smp_wmb();
5617
5618         /* update producer */
5619         bnx2x_update_eq_prod(bp, bp->eq_prod);
5620 }
5621
5622 static void bnx2x_sp_task(struct work_struct *work)
5623 {
5624         struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
5625
5626         DP(BNX2X_MSG_SP, "sp task invoked\n");
5627
5628         /* make sure the atomic interrupt_occurred has been written */
5629         smp_rmb();
5630         if (atomic_read(&bp->interrupt_occurred)) {
5631
5632                 /* what work needs to be performed? */
5633                 u16 status = bnx2x_update_dsb_idx(bp);
5634
5635                 DP(BNX2X_MSG_SP, "status %x\n", status);
5636                 DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n");
5637                 atomic_set(&bp->interrupt_occurred, 0);
5638
5639                 /* HW attentions */
5640                 if (status & BNX2X_DEF_SB_ATT_IDX) {
5641                         bnx2x_attn_int(bp);
5642                         status &= ~BNX2X_DEF_SB_ATT_IDX;
5643                 }
5644
5645                 /* SP events: STAT_QUERY and others */
5646                 if (status & BNX2X_DEF_SB_IDX) {
5647                         struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
5648
5649                 if (FCOE_INIT(bp) &&
5650                             (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5651                                 /* Prevent local bottom-halves from running as
5652                                  * we are going to change the local NAPI list.
5653                                  */
5654                                 local_bh_disable();
5655                                 napi_schedule(&bnx2x_fcoe(bp, napi));
5656                                 local_bh_enable();
5657                         }
5658
5659                         /* Handle EQ completions */
5660                         bnx2x_eq_int(bp);
5661                         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5662                                      le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5663
5664                         status &= ~BNX2X_DEF_SB_IDX;
5665                 }
5666
5667                 /* if status is non zero then perhaps something went wrong */
5668                 if (unlikely(status))
5669                         DP(BNX2X_MSG_SP,
5670                            "got an unknown interrupt! (status 0x%x)\n", status);
5671
5672                 /* ack status block only if something was actually handled */
5673                 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5674                              le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
5675         }
5676
5677         /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5678         if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
5679                                &bp->sp_state)) {
5680                 bnx2x_link_report(bp);
5681                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5682         }
5683 }
5684
5685 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
5686 {
5687         struct net_device *dev = dev_instance;
5688         struct bnx2x *bp = netdev_priv(dev);
5689
5690         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5691                      IGU_INT_DISABLE, 0);
5692
5693 #ifdef BNX2X_STOP_ON_ERROR
5694         if (unlikely(bp->panic))
5695                 return IRQ_HANDLED;
5696 #endif
5697
5698         if (CNIC_LOADED(bp)) {
5699                 struct cnic_ops *c_ops;
5700
5701                 rcu_read_lock();
5702                 c_ops = rcu_dereference(bp->cnic_ops);
5703                 if (c_ops)
5704                         c_ops->cnic_handler(bp->cnic_data, NULL);
5705                 rcu_read_unlock();
5706         }
5707
5708         /* schedule sp task to perform default status block work, ack
5709          * attentions and enable interrupts.
5710          */
5711         bnx2x_schedule_sp_task(bp);
5712
5713         return IRQ_HANDLED;
5714 }
5715
5716 /* end of slow path */
5717
5718 void bnx2x_drv_pulse(struct bnx2x *bp)
5719 {
5720         SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5721                  bp->fw_drv_pulse_wr_seq);
5722 }
5723
5724 static void bnx2x_timer(unsigned long data)
5725 {
5726         struct bnx2x *bp = (struct bnx2x *) data;
5727
5728         if (!netif_running(bp->dev))
5729                 return;
5730
5731         if (IS_PF(bp) &&
5732             !BP_NOMCP(bp)) {
5733                 int mb_idx = BP_FW_MB_IDX(bp);
5734                 u16 drv_pulse;
5735                 u16 mcp_pulse;
5736
5737                 ++bp->fw_drv_pulse_wr_seq;
5738                 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
5739                 drv_pulse = bp->fw_drv_pulse_wr_seq;
5740                 bnx2x_drv_pulse(bp);
5741
5742                 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
5743                              MCP_PULSE_SEQ_MASK);
5744                 /* The delta between driver pulse and mcp response
5745                  * should not get too big. If the MFW is more than 5 pulses
5746                  * behind, we should worry about it enough to generate an error
5747                  * log.
5748                  */
5749                 if (((drv_pulse - mcp_pulse) & MCP_PULSE_SEQ_MASK) > 5)
5750                         BNX2X_ERR("MFW seems hanged: drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
5751                                   drv_pulse, mcp_pulse);
5752         }
5753
5754         if (bp->state == BNX2X_STATE_OPEN)
5755                 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
5756
5757         /* sample pf vf bulletin board for new posts from pf */
5758         if (IS_VF(bp))
5759                 bnx2x_timer_sriov(bp);
5760
5761         mod_timer(&bp->timer, jiffies + bp->current_interval);
5762 }
5763
5764 /* end of Statistics */
5765
5766 /* nic init */
5767
5768 /*
5769  * nic init service functions
5770  */
5771
5772 static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
5773 {
5774         u32 i;
5775         if (!(len%4) && !(addr%4))
5776                 for (i = 0; i < len; i += 4)
5777                         REG_WR(bp, addr + i, fill);
5778         else
5779                 for (i = 0; i < len; i++)
5780                         REG_WR8(bp, addr + i, fill);
5781 }
5782
5783 /* helper: writes FP SP data to FW - data_size in dwords */
5784 static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5785                                 int fw_sb_id,
5786                                 u32 *sb_data_p,
5787                                 u32 data_size)
5788 {
5789         int index;
5790         for (index = 0; index < data_size; index++)
5791                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5792                         CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
5793                         sizeof(u32)*index,
5794                         *(sb_data_p + index));
5795 }
5796
5797 static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
5798 {
5799         u32 *sb_data_p;
5800         u32 data_size = 0;
5801         struct hc_status_block_data_e2 sb_data_e2;
5802         struct hc_status_block_data_e1x sb_data_e1x;
5803
5804         /* disable the function first */
5805         if (!CHIP_IS_E1x(bp)) {
5806                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5807                 sb_data_e2.common.state = SB_DISABLED;
5808                 sb_data_e2.common.p_func.vf_valid = false;
5809                 sb_data_p = (u32 *)&sb_data_e2;
5810                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5811         } else {
5812                 memset(&sb_data_e1x, 0,
5813                        sizeof(struct hc_status_block_data_e1x));
5814                 sb_data_e1x.common.state = SB_DISABLED;
5815                 sb_data_e1x.common.p_func.vf_valid = false;
5816                 sb_data_p = (u32 *)&sb_data_e1x;
5817                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5818         }
5819         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5820
5821         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5822                         CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5823                         CSTORM_STATUS_BLOCK_SIZE);
5824         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5825                         CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5826                         CSTORM_SYNC_BLOCK_SIZE);
5827 }
5828
5829 /* helper:  writes SP SB data to FW */
5830 static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
5831                 struct hc_sp_status_block_data *sp_sb_data)
5832 {
5833         int func = BP_FUNC(bp);
5834         int i;
5835         for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5836                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5837                         CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
5838                         i*sizeof(u32),
5839                         *((u32 *)sp_sb_data + i));
5840 }
5841
5842 static void bnx2x_zero_sp_sb(struct bnx2x *bp)
5843 {
5844         int func = BP_FUNC(bp);
5845         struct hc_sp_status_block_data sp_sb_data;
5846         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5847
5848         sp_sb_data.state = SB_DISABLED;
5849         sp_sb_data.p_func.vf_valid = false;
5850
5851         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5852
5853         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5854                         CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
5855                         CSTORM_SP_STATUS_BLOCK_SIZE);
5856         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5857                         CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5858                         CSTORM_SP_SYNC_BLOCK_SIZE);
5859 }
5860
5861 static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
5862                                            int igu_sb_id, int igu_seg_id)
5863 {
5864         hc_sm->igu_sb_id = igu_sb_id;
5865         hc_sm->igu_seg_id = igu_seg_id;
5866         hc_sm->timer_value = 0xFF;
5867         hc_sm->time_to_expire = 0xFFFFFFFF;
5868 }
5869
5870 /* allocates state machine ids. */
5871 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
5872 {
5873         /* zero out state machine indices */
5874         /* rx indices */
5875         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5876
5877         /* tx indices */
5878         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5879         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5880         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5881         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5882
5883         /* map indices */
5884         /* rx indices */
5885         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5886                 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5887
5888         /* tx indices */
5889         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5890                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5891         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5892                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5893         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5894                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5895         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5896                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5897 }
5898
5899 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
5900                           u8 vf_valid, int fw_sb_id, int igu_sb_id)
5901 {
5902         int igu_seg_id;
5903
5904         struct hc_status_block_data_e2 sb_data_e2;
5905         struct hc_status_block_data_e1x sb_data_e1x;
5906         struct hc_status_block_sm  *hc_sm_p;
5907         int data_size;
5908         u32 *sb_data_p;
5909
5910         if (CHIP_INT_MODE_IS_BC(bp))
5911                 igu_seg_id = HC_SEG_ACCESS_NORM;
5912         else
5913                 igu_seg_id = IGU_SEG_ACCESS_NORM;
5914
5915         bnx2x_zero_fp_sb(bp, fw_sb_id);
5916
5917         if (!CHIP_IS_E1x(bp)) {
5918                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5919                 sb_data_e2.common.state = SB_ENABLED;
5920                 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5921                 sb_data_e2.common.p_func.vf_id = vfid;
5922                 sb_data_e2.common.p_func.vf_valid = vf_valid;
5923                 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5924                 sb_data_e2.common.same_igu_sb_1b = true;
5925                 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5926                 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5927                 hc_sm_p = sb_data_e2.common.state_machine;
5928                 sb_data_p = (u32 *)&sb_data_e2;
5929                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5930                 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
5931         } else {
5932                 memset(&sb_data_e1x, 0,
5933                        sizeof(struct hc_status_block_data_e1x));
5934                 sb_data_e1x.common.state = SB_ENABLED;
5935                 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5936                 sb_data_e1x.common.p_func.vf_id = 0xff;
5937                 sb_data_e1x.common.p_func.vf_valid = false;
5938                 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5939                 sb_data_e1x.common.same_igu_sb_1b = true;
5940                 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5941                 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5942                 hc_sm_p = sb_data_e1x.common.state_machine;
5943                 sb_data_p = (u32 *)&sb_data_e1x;
5944                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5945                 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
5946         }
5947
5948         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5949                                        igu_sb_id, igu_seg_id);
5950         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5951                                        igu_sb_id, igu_seg_id);
5952
5953         DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
5954
5955         /* write indices to HW - PCI guarantees endianity of regpairs */
5956         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5957 }
5958
5959 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
5960                                      u16 tx_usec, u16 rx_usec)
5961 {
5962         bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
5963                                     false, rx_usec);
5964         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5965                                        HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
5966                                        tx_usec);
5967         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5968                                        HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
5969                                        tx_usec);
5970         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5971                                        HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
5972                                        tx_usec);
5973 }
5974
5975 static void bnx2x_init_def_sb(struct bnx2x *bp)
5976 {
5977         struct host_sp_status_block *def_sb = bp->def_status_blk;
5978         dma_addr_t mapping = bp->def_status_blk_mapping;
5979         int igu_sp_sb_index;
5980         int igu_seg_id;
5981         int port = BP_PORT(bp);
5982         int func = BP_FUNC(bp);
5983         int reg_offset, reg_offset_en5;
5984         u64 section;
5985         int index;
5986         struct hc_sp_status_block_data sp_sb_data;
5987         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5988
5989         if (CHIP_INT_MODE_IS_BC(bp)) {
5990                 igu_sp_sb_index = DEF_SB_IGU_ID;
5991                 igu_seg_id = HC_SEG_ACCESS_DEF;
5992         } else {
5993                 igu_sp_sb_index = bp->igu_dsb_id;
5994                 igu_seg_id = IGU_SEG_ACCESS_DEF;
5995         }
5996
5997         /* ATTN */
5998         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5999                                             atten_status_block);
6000         def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
6001
6002         bp->attn_state = 0;
6003
6004         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
6005                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
6006         reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
6007                                  MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
6008         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
6009                 int sindex;
6010                 /* take care of sig[0]..sig[4] */
6011                 for (sindex = 0; sindex < 4; sindex++)
6012                         bp->attn_group[index].sig[sindex] =
6013                            REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
6014
6015                 if (!CHIP_IS_E1x(bp))
6016                         /*
6017                          * enable5 is separate from the rest of the registers,
6018                          * and therefore the address skip is 4
6019                          * and not 16 between the different groups
6020                          */
6021                         bp->attn_group[index].sig[4] = REG_RD(bp,
6022                                         reg_offset_en5 + 0x4*index);
6023                 else
6024                         bp->attn_group[index].sig[4] = 0;
6025         }
6026
6027         if (bp->common.int_block == INT_BLOCK_HC) {
6028                 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
6029                                      HC_REG_ATTN_MSG0_ADDR_L);
6030
6031                 REG_WR(bp, reg_offset, U64_LO(section));
6032                 REG_WR(bp, reg_offset + 4, U64_HI(section));
6033         } else if (!CHIP_IS_E1x(bp)) {
6034                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
6035                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
6036         }
6037
6038         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
6039                                             sp_sb);
6040
6041         bnx2x_zero_sp_sb(bp);
6042
6043         /* PCI guarantees endianity of regpairs */
6044         sp_sb_data.state                = SB_ENABLED;
6045         sp_sb_data.host_sb_addr.lo      = U64_LO(section);
6046         sp_sb_data.host_sb_addr.hi      = U64_HI(section);
6047         sp_sb_data.igu_sb_id            = igu_sp_sb_index;
6048         sp_sb_data.igu_seg_id           = igu_seg_id;
6049         sp_sb_data.p_func.pf_id         = func;
6050         sp_sb_data.p_func.vnic_id       = BP_VN(bp);
6051         sp_sb_data.p_func.vf_id         = 0xff;
6052
6053         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
6054
6055         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
6056 }
6057
6058 void bnx2x_update_coalesce(struct bnx2x *bp)
6059 {
6060         int i;
6061
6062         for_each_eth_queue(bp, i)
6063                 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
6064                                          bp->tx_ticks, bp->rx_ticks);
6065 }
6066
6067 static void bnx2x_init_sp_ring(struct bnx2x *bp)
6068 {
6069         spin_lock_init(&bp->spq_lock);
6070         atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
6071
6072         bp->spq_prod_idx = 0;
6073         bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
6074         bp->spq_prod_bd = bp->spq;
6075         bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
6076 }
6077
6078 static void bnx2x_init_eq_ring(struct bnx2x *bp)
6079 {
6080         int i;
6081         for (i = 1; i <= NUM_EQ_PAGES; i++) {
6082                 union event_ring_elem *elem =
6083                         &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
6084
6085                 elem->next_page.addr.hi =
6086                         cpu_to_le32(U64_HI(bp->eq_mapping +
6087                                    BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
6088                 elem->next_page.addr.lo =
6089                         cpu_to_le32(U64_LO(bp->eq_mapping +
6090                                    BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
6091         }
6092         bp->eq_cons = 0;
6093         bp->eq_prod = NUM_EQ_DESC;
6094         bp->eq_cons_sb = BNX2X_EQ_INDEX;
6095         /* we want a warning message before it gets wrought... */
6096         atomic_set(&bp->eq_spq_left,
6097                 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
6098 }
6099
6100 /* called with netif_addr_lock_bh() */
6101 static int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
6102                                unsigned long rx_mode_flags,
6103                                unsigned long rx_accept_flags,
6104                                unsigned long tx_accept_flags,
6105                                unsigned long ramrod_flags)
6106 {
6107         struct bnx2x_rx_mode_ramrod_params ramrod_param;
6108         int rc;
6109
6110         memset(&ramrod_param, 0, sizeof(ramrod_param));
6111
6112         /* Prepare ramrod parameters */
6113         ramrod_param.cid = 0;
6114         ramrod_param.cl_id = cl_id;
6115         ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
6116         ramrod_param.func_id = BP_FUNC(bp);
6117
6118         ramrod_param.pstate = &bp->sp_state;
6119         ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
6120
6121         ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
6122         ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
6123
6124         set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
6125
6126         ramrod_param.ramrod_flags = ramrod_flags;
6127         ramrod_param.rx_mode_flags = rx_mode_flags;
6128
6129         ramrod_param.rx_accept_flags = rx_accept_flags;
6130         ramrod_param.tx_accept_flags = tx_accept_flags;
6131
6132         rc = bnx2x_config_rx_mode(bp, &ramrod_param);
6133         if (rc < 0) {
6134                 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
6135                 return rc;
6136         }
6137
6138         return 0;
6139 }
6140
6141 static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode,
6142                                    unsigned long *rx_accept_flags,
6143                                    unsigned long *tx_accept_flags)
6144 {
6145         /* Clear the flags first */
6146         *rx_accept_flags = 0;
6147         *tx_accept_flags = 0;
6148
6149         switch (rx_mode) {
6150         case BNX2X_RX_MODE_NONE:
6151                 /*
6152                  * 'drop all' supersedes any accept flags that may have been
6153                  * passed to the function.
6154                  */
6155                 break;
6156         case BNX2X_RX_MODE_NORMAL:
6157                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6158                 __set_bit(BNX2X_ACCEPT_MULTICAST, rx_accept_flags);
6159                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6160
6161                 /* internal switching mode */
6162                 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6163                 __set_bit(BNX2X_ACCEPT_MULTICAST, tx_accept_flags);
6164                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6165
6166                 break;
6167         case BNX2X_RX_MODE_ALLMULTI:
6168                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6169                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6170                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6171
6172                 /* internal switching mode */
6173                 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6174                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6175                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6176
6177                 break;
6178         case BNX2X_RX_MODE_PROMISC:
6179                 /* According to definition of SI mode, iface in promisc mode
6180                  * should receive matched and unmatched (in resolution of port)
6181                  * unicast packets.
6182                  */
6183                 __set_bit(BNX2X_ACCEPT_UNMATCHED, rx_accept_flags);
6184                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6185                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6186                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6187
6188                 /* internal switching mode */
6189                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6190                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6191
6192                 if (IS_MF_SI(bp))
6193                         __set_bit(BNX2X_ACCEPT_ALL_UNICAST, tx_accept_flags);
6194                 else
6195                         __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6196
6197                 break;
6198         default:
6199                 BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode);
6200                 return -EINVAL;
6201         }
6202
6203         /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
6204         if (rx_mode != BNX2X_RX_MODE_NONE) {
6205                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6206                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
6207         }
6208
6209         return 0;
6210 }
6211
6212 /* called with netif_addr_lock_bh() */
6213 static int bnx2x_set_storm_rx_mode(struct bnx2x *bp)
6214 {
6215         unsigned long rx_mode_flags = 0, ramrod_flags = 0;
6216         unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
6217         int rc;
6218
6219         if (!NO_FCOE(bp))
6220                 /* Configure rx_mode of FCoE Queue */
6221                 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
6222
6223         rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags,
6224                                      &tx_accept_flags);
6225         if (rc)
6226                 return rc;
6227
6228         __set_bit(RAMROD_RX, &ramrod_flags);
6229         __set_bit(RAMROD_TX, &ramrod_flags);
6230
6231         return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags,
6232                                    rx_accept_flags, tx_accept_flags,
6233                                    ramrod_flags);
6234 }
6235
6236 static void bnx2x_init_internal_common(struct bnx2x *bp)
6237 {
6238         int i;
6239
6240         /* Zero this manually as its initialization is
6241            currently missing in the initTool */
6242         for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
6243                 REG_WR(bp, BAR_USTRORM_INTMEM +
6244                        USTORM_AGG_DATA_OFFSET + i * 4, 0);
6245         if (!CHIP_IS_E1x(bp)) {
6246                 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
6247                         CHIP_INT_MODE_IS_BC(bp) ?
6248                         HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
6249         }
6250 }
6251
6252 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
6253 {
6254         switch (load_code) {
6255         case FW_MSG_CODE_DRV_LOAD_COMMON:
6256         case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
6257                 bnx2x_init_internal_common(bp);
6258                 /* no break */
6259
6260         case FW_MSG_CODE_DRV_LOAD_PORT:
6261                 /* nothing to do */
6262                 /* no break */
6263
6264         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
6265                 /* internal memory per function is
6266                    initialized inside bnx2x_pf_init */
6267                 break;
6268
6269         default:
6270                 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
6271                 break;
6272         }
6273 }
6274
6275 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
6276 {
6277         return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp);
6278 }
6279
6280 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
6281 {
6282         return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp);
6283 }
6284
6285 static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
6286 {
6287         if (CHIP_IS_E1x(fp->bp))
6288                 return BP_L_ID(fp->bp) + fp->index;
6289         else    /* We want Client ID to be the same as IGU SB ID for 57712 */
6290                 return bnx2x_fp_igu_sb_id(fp);
6291 }
6292
6293 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
6294 {
6295         struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
6296         u8 cos;
6297         unsigned long q_type = 0;
6298         u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
6299         fp->rx_queue = fp_idx;
6300         fp->cid = fp_idx;
6301         fp->cl_id = bnx2x_fp_cl_id(fp);
6302         fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
6303         fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
6304         /* qZone id equals to FW (per path) client id */
6305         fp->cl_qzone_id  = bnx2x_fp_qzone_id(fp);
6306
6307         /* init shortcut */
6308         fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
6309
6310         /* Setup SB indices */
6311         fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
6312
6313         /* Configure Queue State object */
6314         __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6315         __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6316
6317         BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
6318
6319         /* init tx data */
6320         for_each_cos_in_tx_queue(fp, cos) {
6321                 bnx2x_init_txdata(bp, fp->txdata_ptr[cos],
6322                                   CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp),
6323                                   FP_COS_TO_TXQ(fp, cos, bp),
6324                                   BNX2X_TX_SB_INDEX_BASE + cos, fp);
6325                 cids[cos] = fp->txdata_ptr[cos]->cid;
6326         }
6327
6328         /* nothing more for vf to do here */
6329         if (IS_VF(bp))
6330                 return;
6331
6332         bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
6333                       fp->fw_sb_id, fp->igu_sb_id);
6334         bnx2x_update_fpsb_idx(fp);
6335         bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids,
6336                              fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6337                              bnx2x_sp_mapping(bp, q_rdata), q_type);
6338
6339         /**
6340          * Configure classification DBs: Always enable Tx switching
6341          */
6342         bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
6343
6344         DP(NETIF_MSG_IFUP,
6345            "queue[%d]:  bnx2x_init_sb(%p,%p)  cl_id %d  fw_sb %d  igu_sb %d\n",
6346            fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6347            fp->igu_sb_id);
6348 }
6349
6350 static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
6351 {
6352         int i;
6353
6354         for (i = 1; i <= NUM_TX_RINGS; i++) {
6355                 struct eth_tx_next_bd *tx_next_bd =
6356                         &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
6357
6358                 tx_next_bd->addr_hi =
6359                         cpu_to_le32(U64_HI(txdata->tx_desc_mapping +
6360                                     BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6361                 tx_next_bd->addr_lo =
6362                         cpu_to_le32(U64_LO(txdata->tx_desc_mapping +
6363                                     BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6364         }
6365
6366         *txdata->tx_cons_sb = cpu_to_le16(0);
6367
6368         SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
6369         txdata->tx_db.data.zero_fill1 = 0;
6370         txdata->tx_db.data.prod = 0;
6371
6372         txdata->tx_pkt_prod = 0;
6373         txdata->tx_pkt_cons = 0;
6374         txdata->tx_bd_prod = 0;
6375         txdata->tx_bd_cons = 0;
6376         txdata->tx_pkt = 0;
6377 }
6378
6379 static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp)
6380 {
6381         int i;
6382
6383         for_each_tx_queue_cnic(bp, i)
6384                 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]);
6385 }
6386
6387 static void bnx2x_init_tx_rings(struct bnx2x *bp)
6388 {
6389         int i;
6390         u8 cos;
6391
6392         for_each_eth_queue(bp, i)
6393                 for_each_cos_in_tx_queue(&bp->fp[i], cos)
6394                         bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]);
6395 }
6396
6397 static void bnx2x_init_fcoe_fp(struct bnx2x *bp)
6398 {
6399         struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
6400         unsigned long q_type = 0;
6401
6402         bnx2x_fcoe(bp, rx_queue) = BNX2X_NUM_ETH_QUEUES(bp);
6403         bnx2x_fcoe(bp, cl_id) = bnx2x_cnic_eth_cl_id(bp,
6404                                                      BNX2X_FCOE_ETH_CL_ID_IDX);
6405         bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID(bp);
6406         bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID;
6407         bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id;
6408         bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX;
6409         bnx2x_init_txdata(bp, bnx2x_fcoe(bp, txdata_ptr[0]),
6410                           fp->cid, FCOE_TXQ_IDX(bp), BNX2X_FCOE_L2_TX_INDEX,
6411                           fp);
6412
6413         DP(NETIF_MSG_IFUP, "created fcoe tx data (fp index %d)\n", fp->index);
6414
6415         /* qZone id equals to FW (per path) client id */
6416         bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fp_qzone_id(fp);
6417         /* init shortcut */
6418         bnx2x_fcoe(bp, ustorm_rx_prods_offset) =
6419                 bnx2x_rx_ustorm_prods_offset(fp);
6420
6421         /* Configure Queue State object */
6422         __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6423         __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6424
6425         /* No multi-CoS for FCoE L2 client */
6426         BUG_ON(fp->max_cos != 1);
6427
6428         bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id,
6429                              &fp->cid, 1, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6430                              bnx2x_sp_mapping(bp, q_rdata), q_type);
6431
6432         DP(NETIF_MSG_IFUP,
6433            "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
6434            fp->index, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6435            fp->igu_sb_id);
6436 }
6437
6438 void bnx2x_nic_init_cnic(struct bnx2x *bp)
6439 {
6440         if (!NO_FCOE(bp))
6441                 bnx2x_init_fcoe_fp(bp);
6442
6443         bnx2x_init_sb(bp, bp->cnic_sb_mapping,
6444                       BNX2X_VF_ID_INVALID, false,
6445                       bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
6446
6447         /* ensure status block indices were read */
6448         rmb();
6449         bnx2x_init_rx_rings_cnic(bp);
6450         bnx2x_init_tx_rings_cnic(bp);
6451
6452         /* flush all */
6453         mb();
6454         mmiowb();
6455 }
6456
6457 void bnx2x_pre_irq_nic_init(struct bnx2x *bp)
6458 {
6459         int i;
6460
6461         /* Setup NIC internals and enable interrupts */
6462         for_each_eth_queue(bp, i)
6463                 bnx2x_init_eth_fp(bp, i);
6464
6465         /* ensure status block indices were read */
6466         rmb();
6467         bnx2x_init_rx_rings(bp);
6468         bnx2x_init_tx_rings(bp);
6469
6470         if (IS_PF(bp)) {
6471                 /* Initialize MOD_ABS interrupts */
6472                 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
6473                                        bp->common.shmem_base,
6474                                        bp->common.shmem2_base, BP_PORT(bp));
6475
6476                 /* initialize the default status block and sp ring */
6477                 bnx2x_init_def_sb(bp);
6478                 bnx2x_update_dsb_idx(bp);
6479                 bnx2x_init_sp_ring(bp);
6480         } else {
6481                 bnx2x_memset_stats(bp);
6482         }
6483 }
6484
6485 void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code)
6486 {
6487         bnx2x_init_eq_ring(bp);
6488         bnx2x_init_internal(bp, load_code);
6489         bnx2x_pf_init(bp);
6490         bnx2x_stats_init(bp);
6491
6492         /* flush all before enabling interrupts */
6493         mb();
6494         mmiowb();
6495
6496         bnx2x_int_enable(bp);
6497
6498         /* Check for SPIO5 */
6499         bnx2x_attn_int_deasserted0(bp,
6500                 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
6501                                    AEU_INPUTS_ATTN_BITS_SPIO5);
6502 }
6503
6504 /* gzip service functions */
6505 static int bnx2x_gunzip_init(struct bnx2x *bp)
6506 {
6507         bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
6508                                             &bp->gunzip_mapping, GFP_KERNEL);
6509         if (bp->gunzip_buf  == NULL)
6510                 goto gunzip_nomem1;
6511
6512         bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
6513         if (bp->strm  == NULL)
6514                 goto gunzip_nomem2;
6515
6516         bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
6517         if (bp->strm->workspace == NULL)
6518                 goto gunzip_nomem3;
6519
6520         return 0;
6521
6522 gunzip_nomem3:
6523         kfree(bp->strm);
6524         bp->strm = NULL;
6525
6526 gunzip_nomem2:
6527         dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6528                           bp->gunzip_mapping);
6529         bp->gunzip_buf = NULL;
6530
6531 gunzip_nomem1:
6532         BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
6533         return -ENOMEM;
6534 }
6535
6536 static void bnx2x_gunzip_end(struct bnx2x *bp)
6537 {
6538         if (bp->strm) {
6539                 vfree(bp->strm->workspace);
6540                 kfree(bp->strm);
6541                 bp->strm = NULL;
6542         }
6543
6544         if (bp->gunzip_buf) {
6545                 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6546                                   bp->gunzip_mapping);
6547                 bp->gunzip_buf = NULL;
6548         }
6549 }
6550
6551 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
6552 {
6553         int n, rc;
6554
6555         /* check gzip header */
6556         if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
6557                 BNX2X_ERR("Bad gzip header\n");
6558                 return -EINVAL;
6559         }
6560
6561         n = 10;
6562
6563 #define FNAME                           0x8
6564
6565         if (zbuf[3] & FNAME)
6566                 while ((zbuf[n++] != 0) && (n < len));
6567
6568         bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
6569         bp->strm->avail_in = len - n;
6570         bp->strm->next_out = bp->gunzip_buf;
6571         bp->strm->avail_out = FW_BUF_SIZE;
6572
6573         rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
6574         if (rc != Z_OK)
6575                 return rc;
6576
6577         rc = zlib_inflate(bp->strm, Z_FINISH);
6578         if ((rc != Z_OK) && (rc != Z_STREAM_END))
6579                 netdev_err(bp->dev, "Firmware decompression error: %s\n",
6580                            bp->strm->msg);
6581
6582         bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
6583         if (bp->gunzip_outlen & 0x3)
6584                 netdev_err(bp->dev,
6585                            "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
6586                                 bp->gunzip_outlen);
6587         bp->gunzip_outlen >>= 2;
6588
6589         zlib_inflateEnd(bp->strm);
6590
6591         if (rc == Z_STREAM_END)
6592                 return 0;
6593
6594         return rc;
6595 }
6596
6597 /* nic load/unload */
6598
6599 /*
6600  * General service functions
6601  */
6602
6603 /* send a NIG loopback debug packet */
6604 static void bnx2x_lb_pckt(struct bnx2x *bp)
6605 {
6606         u32 wb_write[3];
6607
6608         /* Ethernet source and destination addresses */
6609         wb_write[0] = 0x55555555;
6610         wb_write[1] = 0x55555555;
6611         wb_write[2] = 0x20;             /* SOP */
6612         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6613
6614         /* NON-IP protocol */
6615         wb_write[0] = 0x09000000;
6616         wb_write[1] = 0x55555555;
6617         wb_write[2] = 0x10;             /* EOP, eop_bvalid = 0 */
6618         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6619 }
6620
6621 /* some of the internal memories
6622  * are not directly readable from the driver
6623  * to test them we send debug packets
6624  */
6625 static int bnx2x_int_mem_test(struct bnx2x *bp)
6626 {
6627         int factor;
6628         int count, i;
6629         u32 val = 0;
6630
6631         if (CHIP_REV_IS_FPGA(bp))
6632                 factor = 120;
6633         else if (CHIP_REV_IS_EMUL(bp))
6634                 factor = 200;
6635         else
6636                 factor = 1;
6637
6638         /* Disable inputs of parser neighbor blocks */
6639         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6640         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6641         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6642         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6643
6644         /*  Write 0 to parser credits for CFC search request */
6645         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6646
6647         /* send Ethernet packet */
6648         bnx2x_lb_pckt(bp);
6649
6650         /* TODO do i reset NIG statistic? */
6651         /* Wait until NIG register shows 1 packet of size 0x10 */
6652         count = 1000 * factor;
6653         while (count) {
6654
6655                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6656                 val = *bnx2x_sp(bp, wb_data[0]);
6657                 if (val == 0x10)
6658                         break;
6659
6660                 usleep_range(10000, 20000);
6661                 count--;
6662         }
6663         if (val != 0x10) {
6664                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
6665                 return -1;
6666         }
6667
6668         /* Wait until PRS register shows 1 packet */
6669         count = 1000 * factor;
6670         while (count) {
6671                 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6672                 if (val == 1)
6673                         break;
6674
6675                 usleep_range(10000, 20000);
6676                 count--;
6677         }
6678         if (val != 0x1) {
6679                 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6680                 return -2;
6681         }
6682
6683         /* Reset and init BRB, PRS */
6684         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6685         msleep(50);
6686         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6687         msleep(50);
6688         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6689         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6690
6691         DP(NETIF_MSG_HW, "part2\n");
6692
6693         /* Disable inputs of parser neighbor blocks */
6694         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6695         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6696         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6697         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6698
6699         /* Write 0 to parser credits for CFC search request */
6700         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6701
6702         /* send 10 Ethernet packets */
6703         for (i = 0; i < 10; i++)
6704                 bnx2x_lb_pckt(bp);
6705
6706         /* Wait until NIG register shows 10 + 1
6707            packets of size 11*0x10 = 0xb0 */
6708         count = 1000 * factor;
6709         while (count) {
6710
6711                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6712                 val = *bnx2x_sp(bp, wb_data[0]);
6713                 if (val == 0xb0)
6714                         break;
6715
6716                 usleep_range(10000, 20000);
6717                 count--;
6718         }
6719         if (val != 0xb0) {
6720                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
6721                 return -3;
6722         }
6723
6724         /* Wait until PRS register shows 2 packets */
6725         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6726         if (val != 2)
6727                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
6728
6729         /* Write 1 to parser credits for CFC search request */
6730         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
6731
6732         /* Wait until PRS register shows 3 packets */
6733         msleep(10 * factor);
6734         /* Wait until NIG register shows 1 packet of size 0x10 */
6735         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6736         if (val != 3)
6737                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
6738
6739         /* clear NIG EOP FIFO */
6740         for (i = 0; i < 11; i++)
6741                 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
6742         val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
6743         if (val != 1) {
6744                 BNX2X_ERR("clear of NIG failed\n");
6745                 return -4;
6746         }
6747
6748         /* Reset and init BRB, PRS, NIG */
6749         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6750         msleep(50);
6751         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6752         msleep(50);
6753         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6754         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6755         if (!CNIC_SUPPORT(bp))
6756                 /* set NIC mode */
6757                 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6758
6759         /* Enable inputs of parser neighbor blocks */
6760         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
6761         REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
6762         REG_WR(bp, CFC_REG_DEBUG0, 0x0);
6763         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
6764
6765         DP(NETIF_MSG_HW, "done\n");
6766
6767         return 0; /* OK */
6768 }
6769
6770 static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
6771 {
6772         u32 val;
6773
6774         REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6775         if (!CHIP_IS_E1x(bp))
6776                 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
6777         else
6778                 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
6779         REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6780         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6781         /*
6782          * mask read length error interrupts in brb for parser
6783          * (parsing unit and 'checksum and crc' unit)
6784          * these errors are legal (PU reads fixed length and CAC can cause
6785          * read length error on truncated packets)
6786          */
6787         REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
6788         REG_WR(bp, QM_REG_QM_INT_MASK, 0);
6789         REG_WR(bp, TM_REG_TM_INT_MASK, 0);
6790         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
6791         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
6792         REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
6793 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6794 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
6795         REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
6796         REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
6797         REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
6798 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6799 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
6800         REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
6801         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
6802         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
6803         REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
6804 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6805 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
6806
6807         val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT  |
6808                 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
6809                 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN;
6810         if (!CHIP_IS_E1x(bp))
6811                 val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
6812                         PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED;
6813         REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val);
6814
6815         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
6816         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
6817         REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
6818 /*      REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
6819
6820         if (!CHIP_IS_E1x(bp))
6821                 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
6822                 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
6823
6824         REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
6825         REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
6826 /*      REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
6827         REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18);         /* bit 3,4 masked */
6828 }
6829
6830 static void bnx2x_reset_common(struct bnx2x *bp)
6831 {
6832         u32 val = 0x1400;
6833
6834         /* reset_common */
6835         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6836                0xd3ffff7f);
6837
6838         if (CHIP_IS_E3(bp)) {
6839                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6840                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6841         }
6842
6843         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
6844 }
6845
6846 static void bnx2x_setup_dmae(struct bnx2x *bp)
6847 {
6848         bp->dmae_ready = 0;
6849         spin_lock_init(&bp->dmae_lock);
6850 }
6851
6852 static void bnx2x_init_pxp(struct bnx2x *bp)
6853 {
6854         u16 devctl;
6855         int r_order, w_order;
6856
6857         pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl);
6858         DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
6859         w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6860         if (bp->mrrs == -1)
6861                 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
6862         else {
6863                 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
6864                 r_order = bp->mrrs;
6865         }
6866
6867         bnx2x_init_pxp_arb(bp, r_order, w_order);
6868 }
6869
6870 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
6871 {
6872         int is_required;
6873         u32 val;
6874         int port;
6875
6876         if (BP_NOMCP(bp))
6877                 return;
6878
6879         is_required = 0;
6880         val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
6881               SHARED_HW_CFG_FAN_FAILURE_MASK;
6882
6883         if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
6884                 is_required = 1;
6885
6886         /*
6887          * The fan failure mechanism is usually related to the PHY type since
6888          * the power consumption of the board is affected by the PHY. Currently,
6889          * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6890          */
6891         else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
6892                 for (port = PORT_0; port < PORT_MAX; port++) {
6893                         is_required |=
6894                                 bnx2x_fan_failure_det_req(
6895                                         bp,
6896                                         bp->common.shmem_base,
6897                                         bp->common.shmem2_base,
6898                                         port);
6899                 }
6900
6901         DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
6902
6903         if (is_required == 0)
6904                 return;
6905
6906         /* Fan failure is indicated by SPIO 5 */
6907         bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
6908
6909         /* set to active low mode */
6910         val = REG_RD(bp, MISC_REG_SPIO_INT);
6911         val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
6912         REG_WR(bp, MISC_REG_SPIO_INT, val);
6913
6914         /* enable interrupt to signal the IGU */
6915         val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6916         val |= MISC_SPIO_SPIO5;
6917         REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
6918 }
6919
6920 void bnx2x_pf_disable(struct bnx2x *bp)
6921 {
6922         u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
6923         val &= ~IGU_PF_CONF_FUNC_EN;
6924
6925         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
6926         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6927         REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
6928 }
6929
6930 static void bnx2x__common_init_phy(struct bnx2x *bp)
6931 {
6932         u32 shmem_base[2], shmem2_base[2];
6933         /* Avoid common init in case MFW supports LFA */
6934         if (SHMEM2_RD(bp, size) >
6935             (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
6936                 return;
6937         shmem_base[0] =  bp->common.shmem_base;
6938         shmem2_base[0] = bp->common.shmem2_base;
6939         if (!CHIP_IS_E1x(bp)) {
6940                 shmem_base[1] =
6941                         SHMEM2_RD(bp, other_shmem_base_addr);
6942                 shmem2_base[1] =
6943                         SHMEM2_RD(bp, other_shmem2_base_addr);
6944         }
6945         bnx2x_acquire_phy_lock(bp);
6946         bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
6947                               bp->common.chip_id);
6948         bnx2x_release_phy_lock(bp);
6949 }
6950
6951 static void bnx2x_config_endianity(struct bnx2x *bp, u32 val)
6952 {
6953         REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, val);
6954         REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, val);
6955         REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, val);
6956         REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, val);
6957         REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, val);
6958
6959         /* make sure this value is 0 */
6960         REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
6961
6962         REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, val);
6963         REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, val);
6964         REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, val);
6965         REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, val);
6966 }
6967
6968 static void bnx2x_set_endianity(struct bnx2x *bp)
6969 {
6970 #ifdef __BIG_ENDIAN
6971         bnx2x_config_endianity(bp, 1);
6972 #else
6973         bnx2x_config_endianity(bp, 0);
6974 #endif
6975 }
6976
6977 static void bnx2x_reset_endianity(struct bnx2x *bp)
6978 {
6979         bnx2x_config_endianity(bp, 0);
6980 }
6981
6982 /**
6983  * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
6984  *
6985  * @bp:         driver handle
6986  */
6987 static int bnx2x_init_hw_common(struct bnx2x *bp)
6988 {
6989         u32 val;
6990
6991         DP(NETIF_MSG_HW, "starting common init  func %d\n", BP_ABS_FUNC(bp));
6992
6993         /*
6994          * take the RESET lock to protect undi_unload flow from accessing
6995          * registers while we're resetting the chip
6996          */
6997         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
6998
6999         bnx2x_reset_common(bp);
7000         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
7001
7002         val = 0xfffc;
7003         if (CHIP_IS_E3(bp)) {
7004                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
7005                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
7006         }
7007         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
7008
7009         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
7010
7011         bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
7012
7013         if (!CHIP_IS_E1x(bp)) {
7014                 u8 abs_func_id;
7015
7016                 /**
7017                  * 4-port mode or 2-port mode we need to turn of master-enable
7018                  * for everyone, after that, turn it back on for self.
7019                  * so, we disregard multi-function or not, and always disable
7020                  * for all functions on the given path, this means 0,2,4,6 for
7021                  * path 0 and 1,3,5,7 for path 1
7022                  */
7023                 for (abs_func_id = BP_PATH(bp);
7024                      abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
7025                         if (abs_func_id == BP_ABS_FUNC(bp)) {
7026                                 REG_WR(bp,
7027                                     PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
7028                                     1);
7029                                 continue;
7030                         }
7031
7032                         bnx2x_pretend_func(bp, abs_func_id);
7033                         /* clear pf enable */
7034                         bnx2x_pf_disable(bp);
7035                         bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
7036                 }
7037         }
7038
7039         bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
7040         if (CHIP_IS_E1(bp)) {
7041                 /* enable HW interrupt from PXP on USDM overflow
7042                    bit 16 on INT_MASK_0 */
7043                 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
7044         }
7045
7046         bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
7047         bnx2x_init_pxp(bp);
7048         bnx2x_set_endianity(bp);
7049         bnx2x_ilt_init_page_size(bp, INITOP_SET);
7050
7051         if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
7052                 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
7053
7054         /* let the HW do it's magic ... */
7055         msleep(100);
7056         /* finish PXP init */
7057         val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
7058         if (val != 1) {
7059                 BNX2X_ERR("PXP2 CFG failed\n");
7060                 return -EBUSY;
7061         }
7062         val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
7063         if (val != 1) {
7064                 BNX2X_ERR("PXP2 RD_INIT failed\n");
7065                 return -EBUSY;
7066         }
7067
7068         /* Timers bug workaround E2 only. We need to set the entire ILT to
7069          * have entries with value "0" and valid bit on.
7070          * This needs to be done by the first PF that is loaded in a path
7071          * (i.e. common phase)
7072          */
7073         if (!CHIP_IS_E1x(bp)) {
7074 /* In E2 there is a bug in the timers block that can cause function 6 / 7
7075  * (i.e. vnic3) to start even if it is marked as "scan-off".
7076  * This occurs when a different function (func2,3) is being marked
7077  * as "scan-off". Real-life scenario for example: if a driver is being
7078  * load-unloaded while func6,7 are down. This will cause the timer to access
7079  * the ilt, translate to a logical address and send a request to read/write.
7080  * Since the ilt for the function that is down is not valid, this will cause
7081  * a translation error which is unrecoverable.
7082  * The Workaround is intended to make sure that when this happens nothing fatal
7083  * will occur. The workaround:
7084  *      1.  First PF driver which loads on a path will:
7085  *              a.  After taking the chip out of reset, by using pretend,
7086  *                  it will write "0" to the following registers of
7087  *                  the other vnics.
7088  *                  REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
7089  *                  REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
7090  *                  REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
7091  *                  And for itself it will write '1' to
7092  *                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
7093  *                  dmae-operations (writing to pram for example.)
7094  *                  note: can be done for only function 6,7 but cleaner this
7095  *                        way.
7096  *              b.  Write zero+valid to the entire ILT.
7097  *              c.  Init the first_timers_ilt_entry, last_timers_ilt_entry of
7098  *                  VNIC3 (of that port). The range allocated will be the
7099  *                  entire ILT. This is needed to prevent  ILT range error.
7100  *      2.  Any PF driver load flow:
7101  *              a.  ILT update with the physical addresses of the allocated
7102  *                  logical pages.
7103  *              b.  Wait 20msec. - note that this timeout is needed to make
7104  *                  sure there are no requests in one of the PXP internal
7105  *                  queues with "old" ILT addresses.
7106  *              c.  PF enable in the PGLC.
7107  *              d.  Clear the was_error of the PF in the PGLC. (could have
7108  *                  occurred while driver was down)
7109  *              e.  PF enable in the CFC (WEAK + STRONG)
7110  *              f.  Timers scan enable
7111  *      3.  PF driver unload flow:
7112  *              a.  Clear the Timers scan_en.
7113  *              b.  Polling for scan_on=0 for that PF.
7114  *              c.  Clear the PF enable bit in the PXP.
7115  *              d.  Clear the PF enable in the CFC (WEAK + STRONG)
7116  *              e.  Write zero+valid to all ILT entries (The valid bit must
7117  *                  stay set)
7118  *              f.  If this is VNIC 3 of a port then also init
7119  *                  first_timers_ilt_entry to zero and last_timers_ilt_entry
7120  *                  to the last entry in the ILT.
7121  *
7122  *      Notes:
7123  *      Currently the PF error in the PGLC is non recoverable.
7124  *      In the future the there will be a recovery routine for this error.
7125  *      Currently attention is masked.
7126  *      Having an MCP lock on the load/unload process does not guarantee that
7127  *      there is no Timer disable during Func6/7 enable. This is because the
7128  *      Timers scan is currently being cleared by the MCP on FLR.
7129  *      Step 2.d can be done only for PF6/7 and the driver can also check if
7130  *      there is error before clearing it. But the flow above is simpler and
7131  *      more general.
7132  *      All ILT entries are written by zero+valid and not just PF6/7
7133  *      ILT entries since in the future the ILT entries allocation for
7134  *      PF-s might be dynamic.
7135  */
7136                 struct ilt_client_info ilt_cli;
7137                 struct bnx2x_ilt ilt;
7138                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
7139                 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
7140
7141                 /* initialize dummy TM client */
7142                 ilt_cli.start = 0;
7143                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
7144                 ilt_cli.client_num = ILT_CLIENT_TM;
7145
7146                 /* Step 1: set zeroes to all ilt page entries with valid bit on
7147                  * Step 2: set the timers first/last ilt entry to point
7148                  * to the entire range to prevent ILT range error for 3rd/4th
7149                  * vnic (this code assumes existence of the vnic)
7150                  *
7151                  * both steps performed by call to bnx2x_ilt_client_init_op()
7152                  * with dummy TM client
7153                  *
7154                  * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
7155                  * and his brother are split registers
7156                  */
7157                 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
7158                 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
7159                 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
7160
7161                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
7162                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
7163                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
7164         }
7165
7166         REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
7167         REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
7168
7169         if (!CHIP_IS_E1x(bp)) {
7170                 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
7171                                 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
7172                 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
7173
7174                 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
7175
7176                 /* let the HW do it's magic ... */
7177                 do {
7178                         msleep(200);
7179                         val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
7180                 } while (factor-- && (val != 1));
7181
7182                 if (val != 1) {
7183                         BNX2X_ERR("ATC_INIT failed\n");
7184                         return -EBUSY;
7185                 }
7186         }
7187
7188         bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
7189
7190         bnx2x_iov_init_dmae(bp);
7191
7192         /* clean the DMAE memory */
7193         bp->dmae_ready = 1;
7194         bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
7195
7196         bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
7197
7198         bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
7199
7200         bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
7201
7202         bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
7203
7204         bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
7205         bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
7206         bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
7207         bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
7208
7209         bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
7210
7211         /* QM queues pointers table */
7212         bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
7213
7214         /* soft reset pulse */
7215         REG_WR(bp, QM_REG_SOFT_RESET, 1);
7216         REG_WR(bp, QM_REG_SOFT_RESET, 0);
7217
7218         if (CNIC_SUPPORT(bp))
7219                 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
7220
7221         bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
7222
7223         if (!CHIP_REV_IS_SLOW(bp))
7224                 /* enable hw interrupt from doorbell Q */
7225                 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
7226
7227         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
7228
7229         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
7230         REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
7231
7232         if (!CHIP_IS_E1(bp))
7233                 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
7234
7235         if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) {
7236                 if (IS_MF_AFEX(bp)) {
7237                         /* configure that VNTag and VLAN headers must be
7238                          * received in afex mode
7239                          */
7240                         REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE);
7241                         REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA);
7242                         REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
7243                         REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
7244                         REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4);
7245                 } else {
7246                         /* Bit-map indicating which L2 hdrs may appear
7247                          * after the basic Ethernet header
7248                          */
7249                         REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
7250                                bp->path_has_ovlan ? 7 : 6);
7251                 }
7252         }
7253
7254         bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
7255         bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
7256         bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
7257         bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
7258
7259         if (!CHIP_IS_E1x(bp)) {
7260                 /* reset VFC memories */
7261                 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
7262                            VFC_MEMORIES_RST_REG_CAM_RST |
7263                            VFC_MEMORIES_RST_REG_RAM_RST);
7264                 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
7265                            VFC_MEMORIES_RST_REG_CAM_RST |
7266                            VFC_MEMORIES_RST_REG_RAM_RST);
7267
7268                 msleep(20);
7269         }
7270
7271         bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
7272         bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
7273         bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
7274         bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
7275
7276         /* sync semi rtc */
7277         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
7278                0x80000000);
7279         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
7280                0x80000000);
7281
7282         bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
7283         bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
7284         bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
7285
7286         if (!CHIP_IS_E1x(bp)) {
7287                 if (IS_MF_AFEX(bp)) {
7288                         /* configure that VNTag and VLAN headers must be
7289                          * sent in afex mode
7290                          */
7291                         REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE);
7292                         REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA);
7293                         REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
7294                         REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
7295                         REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4);
7296                 } else {
7297                         REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
7298                                bp->path_has_ovlan ? 7 : 6);
7299                 }
7300         }
7301
7302         REG_WR(bp, SRC_REG_SOFT_RST, 1);
7303
7304         bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
7305
7306         if (CNIC_SUPPORT(bp)) {
7307                 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
7308                 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
7309                 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
7310                 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
7311                 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
7312                 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
7313                 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
7314                 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
7315                 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
7316                 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
7317         }
7318         REG_WR(bp, SRC_REG_SOFT_RST, 0);
7319
7320         if (sizeof(union cdu_context) != 1024)
7321                 /* we currently assume that a context is 1024 bytes */
7322                 dev_alert(&bp->pdev->dev,
7323                           "please adjust the size of cdu_context(%ld)\n",
7324                           (long)sizeof(union cdu_context));
7325
7326         bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
7327         val = (4 << 24) + (0 << 12) + 1024;
7328         REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
7329
7330         bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
7331         REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
7332         /* enable context validation interrupt from CFC */
7333         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
7334
7335         /* set the thresholds to prevent CFC/CDU race */
7336         REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
7337
7338         bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
7339
7340         if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
7341                 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
7342
7343         bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
7344         bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
7345
7346         /* Reset PCIE errors for debug */
7347         REG_WR(bp, 0x2814, 0xffffffff);
7348         REG_WR(bp, 0x3820, 0xffffffff);
7349
7350         if (!CHIP_IS_E1x(bp)) {
7351                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
7352                            (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
7353                                 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
7354                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
7355                            (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
7356                                 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
7357                                 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
7358                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
7359                            (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
7360                                 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
7361                                 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
7362         }
7363
7364         bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
7365         if (!CHIP_IS_E1(bp)) {
7366                 /* in E3 this done in per-port section */
7367                 if (!CHIP_IS_E3(bp))
7368                         REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
7369         }
7370         if (CHIP_IS_E1H(bp))
7371                 /* not applicable for E2 (and above ...) */
7372                 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
7373
7374         if (CHIP_REV_IS_SLOW(bp))
7375                 msleep(200);
7376
7377         /* finish CFC init */
7378         val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
7379         if (val != 1) {
7380                 BNX2X_ERR("CFC LL_INIT failed\n");
7381                 return -EBUSY;
7382         }
7383         val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
7384         if (val != 1) {
7385                 BNX2X_ERR("CFC AC_INIT failed\n");
7386                 return -EBUSY;
7387         }
7388         val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
7389         if (val != 1) {
7390                 BNX2X_ERR("CFC CAM_INIT failed\n");
7391                 return -EBUSY;
7392         }
7393         REG_WR(bp, CFC_REG_DEBUG0, 0);
7394
7395         if (CHIP_IS_E1(bp)) {
7396                 /* read NIG statistic
7397                    to see if this is our first up since powerup */
7398                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
7399                 val = *bnx2x_sp(bp, wb_data[0]);
7400
7401                 /* do internal memory self test */
7402                 if ((val == 0) && bnx2x_int_mem_test(bp)) {
7403                         BNX2X_ERR("internal mem self test failed\n");
7404                         return -EBUSY;
7405                 }
7406         }
7407
7408         bnx2x_setup_fan_failure_detection(bp);
7409
7410         /* clear PXP2 attentions */
7411         REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
7412
7413         bnx2x_enable_blocks_attention(bp);
7414         bnx2x_enable_blocks_parity(bp);
7415
7416         if (!BP_NOMCP(bp)) {
7417                 if (CHIP_IS_E1x(bp))
7418                         bnx2x__common_init_phy(bp);
7419         } else
7420                 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
7421
7422         return 0;
7423 }
7424
7425 /**
7426  * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
7427  *
7428  * @bp:         driver handle
7429  */
7430 static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
7431 {
7432         int rc = bnx2x_init_hw_common(bp);
7433
7434         if (rc)
7435                 return rc;
7436
7437         /* In E2 2-PORT mode, same ext phy is used for the two paths */
7438         if (!BP_NOMCP(bp))
7439                 bnx2x__common_init_phy(bp);
7440
7441         return 0;
7442 }
7443
7444 static int bnx2x_init_hw_port(struct bnx2x *bp)
7445 {
7446         int port = BP_PORT(bp);
7447         int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
7448         u32 low, high;
7449         u32 val, reg;
7450
7451         DP(NETIF_MSG_HW, "starting port init  port %d\n", port);
7452
7453         REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
7454
7455         bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7456         bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7457         bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7458
7459         /* Timers bug workaround: disables the pf_master bit in pglue at
7460          * common phase, we need to enable it here before any dmae access are
7461          * attempted. Therefore we manually added the enable-master to the
7462          * port phase (it also happens in the function phase)
7463          */
7464         if (!CHIP_IS_E1x(bp))
7465                 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7466
7467         bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7468         bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7469         bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7470         bnx2x_init_block(bp, BLOCK_QM, init_phase);
7471
7472         bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7473         bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7474         bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7475         bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7476
7477         /* QM cid (connection) count */
7478         bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
7479
7480         if (CNIC_SUPPORT(bp)) {
7481                 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7482                 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
7483                 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
7484         }
7485
7486         bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7487
7488         bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7489
7490         if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
7491
7492                 if (IS_MF(bp))
7493                         low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
7494                 else if (bp->dev->mtu > 4096) {
7495                         if (bp->flags & ONE_PORT_FLAG)
7496                                 low = 160;
7497                         else {
7498                                 val = bp->dev->mtu;
7499                                 /* (24*1024 + val*4)/256 */
7500                                 low = 96 + (val/64) +
7501                                                 ((val % 64) ? 1 : 0);
7502                         }
7503                 } else
7504                         low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
7505                 high = low + 56;        /* 14*1024/256 */
7506                 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
7507                 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
7508         }
7509
7510         if (CHIP_MODE_IS_4_PORT(bp))
7511                 REG_WR(bp, (BP_PORT(bp) ?
7512                             BRB1_REG_MAC_GUARANTIED_1 :
7513                             BRB1_REG_MAC_GUARANTIED_0), 40);
7514
7515         bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7516         if (CHIP_IS_E3B0(bp)) {
7517                 if (IS_MF_AFEX(bp)) {
7518                         /* configure headers for AFEX mode */
7519                         REG_WR(bp, BP_PORT(bp) ?
7520                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7521                                PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
7522                         REG_WR(bp, BP_PORT(bp) ?
7523                                PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
7524                                PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
7525                         REG_WR(bp, BP_PORT(bp) ?
7526                                PRS_REG_MUST_HAVE_HDRS_PORT_1 :
7527                                PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
7528                 } else {
7529                         /* Ovlan exists only if we are in multi-function +
7530                          * switch-dependent mode, in switch-independent there
7531                          * is no ovlan headers
7532                          */
7533                         REG_WR(bp, BP_PORT(bp) ?
7534                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7535                                PRS_REG_HDRS_AFTER_BASIC_PORT_0,
7536                                (bp->path_has_ovlan ? 7 : 6));
7537                 }
7538         }
7539
7540         bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7541         bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7542         bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7543         bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7544
7545         bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7546         bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7547         bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7548         bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7549
7550         bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7551         bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7552
7553         bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7554
7555         if (CHIP_IS_E1x(bp)) {
7556                 /* configure PBF to work without PAUSE mtu 9000 */
7557                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
7558
7559                 /* update threshold */
7560                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
7561                 /* update init credit */
7562                 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
7563
7564                 /* probe changes */
7565                 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
7566                 udelay(50);
7567                 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
7568         }
7569
7570         if (CNIC_SUPPORT(bp))
7571                 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7572
7573         bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7574         bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7575
7576         if (CHIP_IS_E1(bp)) {
7577                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7578                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7579         }
7580         bnx2x_init_block(bp, BLOCK_HC, init_phase);
7581
7582         bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7583
7584         bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7585         /* init aeu_mask_attn_func_0/1:
7586          *  - SF mode: bits 3-7 are masked. Only bits 0-2 are in use
7587          *  - MF mode: bit 3 is masked. Bits 0-2 are in use as in SF
7588          *             bits 4-7 are used for "per vn group attention" */
7589         val = IS_MF(bp) ? 0xF7 : 0x7;
7590         /* Enable DCBX attention for all but E1 */
7591         val |= CHIP_IS_E1(bp) ? 0 : 0x10;
7592         REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
7593
7594         /* SCPAD_PARITY should NOT trigger close the gates */
7595         reg = port ? MISC_REG_AEU_ENABLE4_NIG_1 : MISC_REG_AEU_ENABLE4_NIG_0;
7596         REG_WR(bp, reg,
7597                REG_RD(bp, reg) &
7598                ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7599
7600         reg = port ? MISC_REG_AEU_ENABLE4_PXP_1 : MISC_REG_AEU_ENABLE4_PXP_0;
7601         REG_WR(bp, reg,
7602                REG_RD(bp, reg) &
7603                ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7604
7605         bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7606
7607         if (!CHIP_IS_E1x(bp)) {
7608                 /* Bit-map indicating which L2 hdrs may appear after the
7609                  * basic Ethernet header
7610                  */
7611                 if (IS_MF_AFEX(bp))
7612                         REG_WR(bp, BP_PORT(bp) ?
7613                                NIG_REG_P1_HDRS_AFTER_BASIC :
7614                                NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
7615                 else
7616                         REG_WR(bp, BP_PORT(bp) ?
7617                                NIG_REG_P1_HDRS_AFTER_BASIC :
7618                                NIG_REG_P0_HDRS_AFTER_BASIC,
7619                                IS_MF_SD(bp) ? 7 : 6);
7620
7621                 if (CHIP_IS_E3(bp))
7622                         REG_WR(bp, BP_PORT(bp) ?
7623                                    NIG_REG_LLH1_MF_MODE :
7624                                    NIG_REG_LLH_MF_MODE, IS_MF(bp));
7625         }
7626         if (!CHIP_IS_E3(bp))
7627                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
7628
7629         if (!CHIP_IS_E1(bp)) {
7630                 /* 0x2 disable mf_ov, 0x1 enable */
7631                 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
7632                        (IS_MF_SD(bp) ? 0x1 : 0x2));
7633
7634                 if (!CHIP_IS_E1x(bp)) {
7635                         val = 0;
7636                         switch (bp->mf_mode) {
7637                         case MULTI_FUNCTION_SD:
7638                                 val = 1;
7639                                 break;
7640                         case MULTI_FUNCTION_SI:
7641                         case MULTI_FUNCTION_AFEX:
7642                                 val = 2;
7643                                 break;
7644                         }
7645
7646                         REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
7647                                                   NIG_REG_LLH0_CLS_TYPE), val);
7648                 }
7649                 {
7650                         REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
7651                         REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
7652                         REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
7653                 }
7654         }
7655
7656         /* If SPIO5 is set to generate interrupts, enable it for this port */
7657         val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
7658         if (val & MISC_SPIO_SPIO5) {
7659                 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
7660                                        MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
7661                 val = REG_RD(bp, reg_addr);
7662                 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
7663                 REG_WR(bp, reg_addr, val);
7664         }
7665
7666         return 0;
7667 }
7668
7669 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
7670 {
7671         int reg;
7672         u32 wb_write[2];
7673
7674         if (CHIP_IS_E1(bp))
7675                 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
7676         else
7677                 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
7678
7679         wb_write[0] = ONCHIP_ADDR1(addr);
7680         wb_write[1] = ONCHIP_ADDR2(addr);
7681         REG_WR_DMAE(bp, reg, wb_write, 2);
7682 }
7683
7684 void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf)
7685 {
7686         u32 data, ctl, cnt = 100;
7687         u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
7688         u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
7689         u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
7690         u32 sb_bit =  1 << (idu_sb_id%32);
7691         u32 func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
7692         u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
7693
7694         /* Not supported in BC mode */
7695         if (CHIP_INT_MODE_IS_BC(bp))
7696                 return;
7697
7698         data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
7699                         << IGU_REGULAR_CLEANUP_TYPE_SHIFT)      |
7700                 IGU_REGULAR_CLEANUP_SET                         |
7701                 IGU_REGULAR_BCLEANUP;
7702
7703         ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT         |
7704               func_encode << IGU_CTRL_REG_FID_SHIFT             |
7705               IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
7706
7707         DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7708                          data, igu_addr_data);
7709         REG_WR(bp, igu_addr_data, data);
7710         mmiowb();
7711         barrier();
7712         DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7713                           ctl, igu_addr_ctl);
7714         REG_WR(bp, igu_addr_ctl, ctl);
7715         mmiowb();
7716         barrier();
7717
7718         /* wait for clean up to finish */
7719         while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
7720                 msleep(20);
7721
7722         if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
7723                 DP(NETIF_MSG_HW,
7724                    "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
7725                           idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
7726         }
7727 }
7728
7729 static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
7730 {
7731         bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
7732 }
7733
7734 static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
7735 {
7736         u32 i, base = FUNC_ILT_BASE(func);
7737         for (i = base; i < base + ILT_PER_FUNC; i++)
7738                 bnx2x_ilt_wr(bp, i, 0);
7739 }
7740
7741 static void bnx2x_init_searcher(struct bnx2x *bp)
7742 {
7743         int port = BP_PORT(bp);
7744         bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
7745         /* T1 hash bits value determines the T1 number of entries */
7746         REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
7747 }
7748
7749 static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend)
7750 {
7751         int rc;
7752         struct bnx2x_func_state_params func_params = {NULL};
7753         struct bnx2x_func_switch_update_params *switch_update_params =
7754                 &func_params.params.switch_update;
7755
7756         /* Prepare parameters for function state transitions */
7757         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7758         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
7759
7760         func_params.f_obj = &bp->func_obj;
7761         func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
7762
7763         /* Function parameters */
7764         __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND_CHNG,
7765                   &switch_update_params->changes);
7766         if (suspend)
7767                 __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND,
7768                           &switch_update_params->changes);
7769
7770         rc = bnx2x_func_state_change(bp, &func_params);
7771
7772         return rc;
7773 }
7774
7775 static int bnx2x_reset_nic_mode(struct bnx2x *bp)
7776 {
7777         int rc, i, port = BP_PORT(bp);
7778         int vlan_en = 0, mac_en[NUM_MACS];
7779
7780         /* Close input from network */
7781         if (bp->mf_mode == SINGLE_FUNCTION) {
7782                 bnx2x_set_rx_filter(&bp->link_params, 0);
7783         } else {
7784                 vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN :
7785                                    NIG_REG_LLH0_FUNC_EN);
7786                 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7787                           NIG_REG_LLH0_FUNC_EN, 0);
7788                 for (i = 0; i < NUM_MACS; i++) {
7789                         mac_en[i] = REG_RD(bp, port ?
7790                                              (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7791                                               4 * i) :
7792                                              (NIG_REG_LLH0_FUNC_MEM_ENABLE +
7793                                               4 * i));
7794                         REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7795                                               4 * i) :
7796                                   (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0);
7797                 }
7798         }
7799
7800         /* Close BMC to host */
7801         REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7802                NIG_REG_P1_TX_MNG_HOST_ENABLE, 0);
7803
7804         /* Suspend Tx switching to the PF. Completion of this ramrod
7805          * further guarantees that all the packets of that PF / child
7806          * VFs in BRB were processed by the Parser, so it is safe to
7807          * change the NIC_MODE register.
7808          */
7809         rc = bnx2x_func_switch_update(bp, 1);
7810         if (rc) {
7811                 BNX2X_ERR("Can't suspend tx-switching!\n");
7812                 return rc;
7813         }
7814
7815         /* Change NIC_MODE register */
7816         REG_WR(bp, PRS_REG_NIC_MODE, 0);
7817
7818         /* Open input from network */
7819         if (bp->mf_mode == SINGLE_FUNCTION) {
7820                 bnx2x_set_rx_filter(&bp->link_params, 1);
7821         } else {
7822                 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7823                           NIG_REG_LLH0_FUNC_EN, vlan_en);
7824                 for (i = 0; i < NUM_MACS; i++) {
7825                         REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7826                                               4 * i) :
7827                                   (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i),
7828                                   mac_en[i]);
7829                 }
7830         }
7831
7832         /* Enable BMC to host */
7833         REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7834                NIG_REG_P1_TX_MNG_HOST_ENABLE, 1);
7835
7836         /* Resume Tx switching to the PF */
7837         rc = bnx2x_func_switch_update(bp, 0);
7838         if (rc) {
7839                 BNX2X_ERR("Can't resume tx-switching!\n");
7840                 return rc;
7841         }
7842
7843         DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7844         return 0;
7845 }
7846
7847 int bnx2x_init_hw_func_cnic(struct bnx2x *bp)
7848 {
7849         int rc;
7850
7851         bnx2x_ilt_init_op_cnic(bp, INITOP_SET);
7852
7853         if (CONFIGURE_NIC_MODE(bp)) {
7854                 /* Configure searcher as part of function hw init */
7855                 bnx2x_init_searcher(bp);
7856
7857                 /* Reset NIC mode */
7858                 rc = bnx2x_reset_nic_mode(bp);
7859                 if (rc)
7860                         BNX2X_ERR("Can't change NIC mode!\n");
7861                 return rc;
7862         }
7863
7864         return 0;
7865 }
7866
7867 static int bnx2x_init_hw_func(struct bnx2x *bp)
7868 {
7869         int port = BP_PORT(bp);
7870         int func = BP_FUNC(bp);
7871         int init_phase = PHASE_PF0 + func;
7872         struct bnx2x_ilt *ilt = BP_ILT(bp);
7873         u16 cdu_ilt_start;
7874         u32 addr, val;
7875         u32 main_mem_base, main_mem_size, main_mem_prty_clr;
7876         int i, main_mem_width, rc;
7877
7878         DP(NETIF_MSG_HW, "starting func init  func %d\n", func);
7879
7880         /* FLR cleanup - hmmm */
7881         if (!CHIP_IS_E1x(bp)) {
7882                 rc = bnx2x_pf_flr_clnup(bp);
7883                 if (rc) {
7884                         bnx2x_fw_dump(bp);
7885                         return rc;
7886                 }
7887         }
7888
7889         /* set MSI reconfigure capability */
7890         if (bp->common.int_block == INT_BLOCK_HC) {
7891                 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
7892                 val = REG_RD(bp, addr);
7893                 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
7894                 REG_WR(bp, addr, val);
7895         }
7896
7897         bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7898         bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7899
7900         ilt = BP_ILT(bp);
7901         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7902
7903         if (IS_SRIOV(bp))
7904                 cdu_ilt_start += BNX2X_FIRST_VF_CID/ILT_PAGE_CIDS;
7905         cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start);
7906
7907         /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes
7908          * those of the VFs, so start line should be reset
7909          */
7910         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7911         for (i = 0; i < L2_ILT_LINES(bp); i++) {
7912                 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt;
7913                 ilt->lines[cdu_ilt_start + i].page_mapping =
7914                         bp->context[i].cxt_mapping;
7915                 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size;
7916         }
7917
7918         bnx2x_ilt_init_op(bp, INITOP_SET);
7919
7920         if (!CONFIGURE_NIC_MODE(bp)) {
7921                 bnx2x_init_searcher(bp);
7922                 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7923                 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7924         } else {
7925                 /* Set NIC mode */
7926                 REG_WR(bp, PRS_REG_NIC_MODE, 1);
7927                 DP(NETIF_MSG_IFUP, "NIC MODE configured\n");
7928         }
7929
7930         if (!CHIP_IS_E1x(bp)) {
7931                 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
7932
7933                 /* Turn on a single ISR mode in IGU if driver is going to use
7934                  * INT#x or MSI
7935                  */
7936                 if (!(bp->flags & USING_MSIX_FLAG))
7937                         pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
7938                 /*
7939                  * Timers workaround bug: function init part.
7940                  * Need to wait 20msec after initializing ILT,
7941                  * needed to make sure there are no requests in
7942                  * one of the PXP internal queues with "old" ILT addresses
7943                  */
7944                 msleep(20);
7945                 /*
7946                  * Master enable - Due to WB DMAE writes performed before this
7947                  * register is re-initialized as part of the regular function
7948                  * init
7949                  */
7950                 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7951                 /* Enable the function in IGU */
7952                 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
7953         }
7954
7955         bp->dmae_ready = 1;
7956
7957         bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7958
7959         if (!CHIP_IS_E1x(bp))
7960                 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
7961
7962         bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7963         bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7964         bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7965         bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7966         bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7967         bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7968         bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7969         bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7970         bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7971         bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7972         bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7973         bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7974         bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7975
7976         if (!CHIP_IS_E1x(bp))
7977                 REG_WR(bp, QM_REG_PF_EN, 1);
7978
7979         if (!CHIP_IS_E1x(bp)) {
7980                 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7981                 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7982                 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7983                 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7984         }
7985         bnx2x_init_block(bp, BLOCK_QM, init_phase);
7986
7987         bnx2x_init_block(bp, BLOCK_TM, init_phase);
7988         bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7989         REG_WR(bp, DORQ_REG_MODE_ACT, 1); /* no dpm */
7990
7991         bnx2x_iov_init_dq(bp);
7992
7993         bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7994         bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7995         bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7996         bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7997         bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7998         bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7999         bnx2x_init_block(bp, BLOCK_UPB, init_phase);
8000         bnx2x_init_block(bp, BLOCK_XPB, init_phase);
8001         bnx2x_init_block(bp, BLOCK_PBF, init_phase);
8002         if (!CHIP_IS_E1x(bp))
8003                 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
8004
8005         bnx2x_init_block(bp, BLOCK_CDU, init_phase);
8006
8007         bnx2x_init_block(bp, BLOCK_CFC, init_phase);
8008
8009         if (!CHIP_IS_E1x(bp))
8010                 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
8011
8012         if (IS_MF(bp)) {
8013                 if (!(IS_MF_UFP(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))) {
8014                         REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
8015                         REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8,
8016                                bp->mf_ov);
8017                 }
8018         }
8019
8020         bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
8021
8022         /* HC init per function */
8023         if (bp->common.int_block == INT_BLOCK_HC) {
8024                 if (CHIP_IS_E1H(bp)) {
8025                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
8026
8027                         REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8028                         REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8029                 }
8030                 bnx2x_init_block(bp, BLOCK_HC, init_phase);
8031
8032         } else {
8033                 int num_segs, sb_idx, prod_offset;
8034
8035                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
8036
8037                 if (!CHIP_IS_E1x(bp)) {
8038                         REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8039                         REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8040                 }
8041
8042                 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
8043
8044                 if (!CHIP_IS_E1x(bp)) {
8045                         int dsb_idx = 0;
8046                         /**
8047                          * Producer memory:
8048                          * E2 mode: address 0-135 match to the mapping memory;
8049                          * 136 - PF0 default prod; 137 - PF1 default prod;
8050                          * 138 - PF2 default prod; 139 - PF3 default prod;
8051                          * 140 - PF0 attn prod;    141 - PF1 attn prod;
8052                          * 142 - PF2 attn prod;    143 - PF3 attn prod;
8053                          * 144-147 reserved.
8054                          *
8055                          * E1.5 mode - In backward compatible mode;
8056                          * for non default SB; each even line in the memory
8057                          * holds the U producer and each odd line hold
8058                          * the C producer. The first 128 producers are for
8059                          * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
8060                          * producers are for the DSB for each PF.
8061                          * Each PF has five segments: (the order inside each
8062                          * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
8063                          * 132-135 C prods; 136-139 X prods; 140-143 T prods;
8064                          * 144-147 attn prods;
8065                          */
8066                         /* non-default-status-blocks */
8067                         num_segs = CHIP_INT_MODE_IS_BC(bp) ?
8068                                 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
8069                         for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
8070                                 prod_offset = (bp->igu_base_sb + sb_idx) *
8071                                         num_segs;
8072
8073                                 for (i = 0; i < num_segs; i++) {
8074                                         addr = IGU_REG_PROD_CONS_MEMORY +
8075                                                         (prod_offset + i) * 4;
8076                                         REG_WR(bp, addr, 0);
8077                                 }
8078                                 /* send consumer update with value 0 */
8079                                 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
8080                                              USTORM_ID, 0, IGU_INT_NOP, 1);
8081                                 bnx2x_igu_clear_sb(bp,
8082                                                    bp->igu_base_sb + sb_idx);
8083                         }
8084
8085                         /* default-status-blocks */
8086                         num_segs = CHIP_INT_MODE_IS_BC(bp) ?
8087                                 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
8088
8089                         if (CHIP_MODE_IS_4_PORT(bp))
8090                                 dsb_idx = BP_FUNC(bp);
8091                         else
8092                                 dsb_idx = BP_VN(bp);
8093
8094                         prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
8095                                        IGU_BC_BASE_DSB_PROD + dsb_idx :
8096                                        IGU_NORM_BASE_DSB_PROD + dsb_idx);
8097
8098                         /*
8099                          * igu prods come in chunks of E1HVN_MAX (4) -
8100                          * does not matters what is the current chip mode
8101                          */
8102                         for (i = 0; i < (num_segs * E1HVN_MAX);
8103                              i += E1HVN_MAX) {
8104                                 addr = IGU_REG_PROD_CONS_MEMORY +
8105                                                         (prod_offset + i)*4;
8106                                 REG_WR(bp, addr, 0);
8107                         }
8108                         /* send consumer update with 0 */
8109                         if (CHIP_INT_MODE_IS_BC(bp)) {
8110                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8111                                              USTORM_ID, 0, IGU_INT_NOP, 1);
8112                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8113                                              CSTORM_ID, 0, IGU_INT_NOP, 1);
8114                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8115                                              XSTORM_ID, 0, IGU_INT_NOP, 1);
8116                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8117                                              TSTORM_ID, 0, IGU_INT_NOP, 1);
8118                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8119                                              ATTENTION_ID, 0, IGU_INT_NOP, 1);
8120                         } else {
8121                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8122                                              USTORM_ID, 0, IGU_INT_NOP, 1);
8123                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8124                                              ATTENTION_ID, 0, IGU_INT_NOP, 1);
8125                         }
8126                         bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
8127
8128                         /* !!! These should become driver const once
8129                            rf-tool supports split-68 const */
8130                         REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
8131                         REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
8132                         REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
8133                         REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
8134                         REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
8135                         REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
8136                 }
8137         }
8138
8139         /* Reset PCIE errors for debug */
8140         REG_WR(bp, 0x2114, 0xffffffff);
8141         REG_WR(bp, 0x2120, 0xffffffff);
8142
8143         if (CHIP_IS_E1x(bp)) {
8144                 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
8145                 main_mem_base = HC_REG_MAIN_MEMORY +
8146                                 BP_PORT(bp) * (main_mem_size * 4);
8147                 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
8148                 main_mem_width = 8;
8149
8150                 val = REG_RD(bp, main_mem_prty_clr);
8151                 if (val)
8152                         DP(NETIF_MSG_HW,
8153                            "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
8154                            val);
8155
8156                 /* Clear "false" parity errors in MSI-X table */
8157                 for (i = main_mem_base;
8158                      i < main_mem_base + main_mem_size * 4;
8159                      i += main_mem_width) {
8160                         bnx2x_read_dmae(bp, i, main_mem_width / 4);
8161                         bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
8162                                          i, main_mem_width / 4);
8163                 }
8164                 /* Clear HC parity attention */
8165                 REG_RD(bp, main_mem_prty_clr);
8166         }
8167
8168 #ifdef BNX2X_STOP_ON_ERROR
8169         /* Enable STORMs SP logging */
8170         REG_WR8(bp, BAR_USTRORM_INTMEM +
8171                USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8172         REG_WR8(bp, BAR_TSTRORM_INTMEM +
8173                TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8174         REG_WR8(bp, BAR_CSTRORM_INTMEM +
8175                CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8176         REG_WR8(bp, BAR_XSTRORM_INTMEM +
8177                XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8178 #endif
8179
8180         bnx2x_phy_probe(&bp->link_params);
8181
8182         return 0;
8183 }
8184
8185 void bnx2x_free_mem_cnic(struct bnx2x *bp)
8186 {
8187         bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE);
8188
8189         if (!CHIP_IS_E1x(bp))
8190                 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
8191                                sizeof(struct host_hc_status_block_e2));
8192         else
8193                 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
8194                                sizeof(struct host_hc_status_block_e1x));
8195
8196         BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
8197 }
8198
8199 void bnx2x_free_mem(struct bnx2x *bp)
8200 {
8201         int i;
8202
8203         BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
8204                        bp->fw_stats_data_sz + bp->fw_stats_req_sz);
8205
8206         if (IS_VF(bp))
8207                 return;
8208
8209         BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
8210                        sizeof(struct host_sp_status_block));
8211
8212         BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
8213                        sizeof(struct bnx2x_slowpath));
8214
8215         for (i = 0; i < L2_ILT_LINES(bp); i++)
8216                 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping,
8217                                bp->context[i].size);
8218         bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
8219
8220         BNX2X_FREE(bp->ilt->lines);
8221
8222         BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
8223
8224         BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
8225                        BCM_PAGE_SIZE * NUM_EQ_PAGES);
8226
8227         BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
8228
8229         bnx2x_iov_free_mem(bp);
8230 }
8231
8232 int bnx2x_alloc_mem_cnic(struct bnx2x *bp)
8233 {
8234         if (!CHIP_IS_E1x(bp)) {
8235                 /* size = the status block + ramrod buffers */
8236                 bp->cnic_sb.e2_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping,
8237                                                     sizeof(struct host_hc_status_block_e2));
8238                 if (!bp->cnic_sb.e2_sb)
8239                         goto alloc_mem_err;
8240         } else {
8241                 bp->cnic_sb.e1x_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping,
8242                                                      sizeof(struct host_hc_status_block_e1x));
8243                 if (!bp->cnic_sb.e1x_sb)
8244                         goto alloc_mem_err;
8245         }
8246
8247         if (CONFIGURE_NIC_MODE(bp) && !bp->t2) {
8248                 /* allocate searcher T2 table, as it wasn't allocated before */
8249                 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ);
8250                 if (!bp->t2)
8251                         goto alloc_mem_err;
8252         }
8253
8254         /* write address to which L5 should insert its values */
8255         bp->cnic_eth_dev.addr_drv_info_to_mcp =
8256                 &bp->slowpath->drv_info_to_mcp;
8257
8258         if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC))
8259                 goto alloc_mem_err;
8260
8261         return 0;
8262
8263 alloc_mem_err:
8264         bnx2x_free_mem_cnic(bp);
8265         BNX2X_ERR("Can't allocate memory\n");
8266         return -ENOMEM;
8267 }
8268
8269 int bnx2x_alloc_mem(struct bnx2x *bp)
8270 {
8271         int i, allocated, context_size;
8272
8273         if (!CONFIGURE_NIC_MODE(bp) && !bp->t2) {
8274                 /* allocate searcher T2 table */
8275                 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ);
8276                 if (!bp->t2)
8277                         goto alloc_mem_err;
8278         }
8279
8280         bp->def_status_blk = BNX2X_PCI_ALLOC(&bp->def_status_blk_mapping,
8281                                              sizeof(struct host_sp_status_block));
8282         if (!bp->def_status_blk)
8283                 goto alloc_mem_err;
8284
8285         bp->slowpath = BNX2X_PCI_ALLOC(&bp->slowpath_mapping,
8286                                        sizeof(struct bnx2x_slowpath));
8287         if (!bp->slowpath)
8288                 goto alloc_mem_err;
8289
8290         /* Allocate memory for CDU context:
8291          * This memory is allocated separately and not in the generic ILT
8292          * functions because CDU differs in few aspects:
8293          * 1. There are multiple entities allocating memory for context -
8294          * 'regular' driver, CNIC and SRIOV driver. Each separately controls
8295          * its own ILT lines.
8296          * 2. Since CDU page-size is not a single 4KB page (which is the case
8297          * for the other ILT clients), to be efficient we want to support
8298          * allocation of sub-page-size in the last entry.
8299          * 3. Context pointers are used by the driver to pass to FW / update
8300          * the context (for the other ILT clients the pointers are used just to
8301          * free the memory during unload).
8302          */
8303         context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
8304
8305         for (i = 0, allocated = 0; allocated < context_size; i++) {
8306                 bp->context[i].size = min(CDU_ILT_PAGE_SZ,
8307                                           (context_size - allocated));
8308                 bp->context[i].vcxt = BNX2X_PCI_ALLOC(&bp->context[i].cxt_mapping,
8309                                                       bp->context[i].size);
8310                 if (!bp->context[i].vcxt)
8311                         goto alloc_mem_err;
8312                 allocated += bp->context[i].size;
8313         }
8314         bp->ilt->lines = kcalloc(ILT_MAX_LINES, sizeof(struct ilt_line),
8315                                  GFP_KERNEL);
8316         if (!bp->ilt->lines)
8317                 goto alloc_mem_err;
8318
8319         if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
8320                 goto alloc_mem_err;
8321
8322         if (bnx2x_iov_alloc_mem(bp))
8323                 goto alloc_mem_err;
8324
8325         /* Slow path ring */
8326         bp->spq = BNX2X_PCI_ALLOC(&bp->spq_mapping, BCM_PAGE_SIZE);
8327         if (!bp->spq)
8328                 goto alloc_mem_err;
8329
8330         /* EQ */
8331         bp->eq_ring = BNX2X_PCI_ALLOC(&bp->eq_mapping,
8332                                       BCM_PAGE_SIZE * NUM_EQ_PAGES);
8333         if (!bp->eq_ring)
8334                 goto alloc_mem_err;
8335
8336         return 0;
8337
8338 alloc_mem_err:
8339         bnx2x_free_mem(bp);
8340         BNX2X_ERR("Can't allocate memory\n");
8341         return -ENOMEM;
8342 }
8343
8344 /*
8345  * Init service functions
8346  */
8347
8348 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
8349                       struct bnx2x_vlan_mac_obj *obj, bool set,
8350                       int mac_type, unsigned long *ramrod_flags)
8351 {
8352         int rc;
8353         struct bnx2x_vlan_mac_ramrod_params ramrod_param;
8354
8355         memset(&ramrod_param, 0, sizeof(ramrod_param));
8356
8357         /* Fill general parameters */
8358         ramrod_param.vlan_mac_obj = obj;
8359         ramrod_param.ramrod_flags = *ramrod_flags;
8360
8361         /* Fill a user request section if needed */
8362         if (!test_bit(RAMROD_CONT, ramrod_flags)) {
8363                 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
8364
8365                 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
8366
8367                 /* Set the command: ADD or DEL */
8368                 if (set)
8369                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
8370                 else
8371                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
8372         }
8373
8374         rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
8375
8376         if (rc == -EEXIST) {
8377                 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
8378                 /* do not treat adding same MAC as error */
8379                 rc = 0;
8380         } else if (rc < 0)
8381                 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
8382
8383         return rc;
8384 }
8385
8386 int bnx2x_del_all_macs(struct bnx2x *bp,
8387                        struct bnx2x_vlan_mac_obj *mac_obj,
8388                        int mac_type, bool wait_for_comp)
8389 {
8390         int rc;
8391         unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
8392
8393         /* Wait for completion of requested */
8394         if (wait_for_comp)
8395                 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8396
8397         /* Set the mac type of addresses we want to clear */
8398         __set_bit(mac_type, &vlan_mac_flags);
8399
8400         rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
8401         if (rc < 0)
8402                 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
8403
8404         return rc;
8405 }
8406
8407 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
8408 {
8409         if (IS_PF(bp)) {
8410                 unsigned long ramrod_flags = 0;
8411
8412                 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
8413                 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8414                 return bnx2x_set_mac_one(bp, bp->dev->dev_addr,
8415                                          &bp->sp_objs->mac_obj, set,
8416                                          BNX2X_ETH_MAC, &ramrod_flags);
8417         } else { /* vf */
8418                 return bnx2x_vfpf_config_mac(bp, bp->dev->dev_addr,
8419                                              bp->fp->index, true);
8420         }
8421 }
8422
8423 int bnx2x_setup_leading(struct bnx2x *bp)
8424 {
8425         if (IS_PF(bp))
8426                 return bnx2x_setup_queue(bp, &bp->fp[0], true);
8427         else /* VF */
8428                 return bnx2x_vfpf_setup_q(bp, &bp->fp[0], true);
8429 }
8430
8431 /**
8432  * bnx2x_set_int_mode - configure interrupt mode
8433  *
8434  * @bp:         driver handle
8435  *
8436  * In case of MSI-X it will also try to enable MSI-X.
8437  */
8438 int bnx2x_set_int_mode(struct bnx2x *bp)
8439 {
8440         int rc = 0;
8441
8442         if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX) {
8443                 BNX2X_ERR("VF not loaded since interrupt mode not msix\n");
8444                 return -EINVAL;
8445         }
8446
8447         switch (int_mode) {
8448         case BNX2X_INT_MODE_MSIX:
8449                 /* attempt to enable msix */
8450                 rc = bnx2x_enable_msix(bp);
8451
8452                 /* msix attained */
8453                 if (!rc)
8454                         return 0;
8455
8456                 /* vfs use only msix */
8457                 if (rc && IS_VF(bp))
8458                         return rc;
8459
8460                 /* failed to enable multiple MSI-X */
8461                 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
8462                                bp->num_queues,
8463                                1 + bp->num_cnic_queues);
8464
8465                 /* falling through... */
8466         case BNX2X_INT_MODE_MSI:
8467                 bnx2x_enable_msi(bp);
8468
8469                 /* falling through... */
8470         case BNX2X_INT_MODE_INTX:
8471                 bp->num_ethernet_queues = 1;
8472                 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
8473                 BNX2X_DEV_INFO("set number of queues to 1\n");
8474                 break;
8475         default:
8476                 BNX2X_DEV_INFO("unknown value in int_mode module parameter\n");
8477                 return -EINVAL;
8478         }
8479         return 0;
8480 }
8481
8482 /* must be called prior to any HW initializations */
8483 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
8484 {
8485         if (IS_SRIOV(bp))
8486                 return (BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)/ILT_PAGE_CIDS;
8487         return L2_ILT_LINES(bp);
8488 }
8489
8490 void bnx2x_ilt_set_info(struct bnx2x *bp)
8491 {
8492         struct ilt_client_info *ilt_client;
8493         struct bnx2x_ilt *ilt = BP_ILT(bp);
8494         u16 line = 0;
8495
8496         ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
8497         DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
8498
8499         /* CDU */
8500         ilt_client = &ilt->clients[ILT_CLIENT_CDU];
8501         ilt_client->client_num = ILT_CLIENT_CDU;
8502         ilt_client->page_size = CDU_ILT_PAGE_SZ;
8503         ilt_client->flags = ILT_CLIENT_SKIP_MEM;
8504         ilt_client->start = line;
8505         line += bnx2x_cid_ilt_lines(bp);
8506
8507         if (CNIC_SUPPORT(bp))
8508                 line += CNIC_ILT_LINES;
8509         ilt_client->end = line - 1;
8510
8511         DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8512            ilt_client->start,
8513            ilt_client->end,
8514            ilt_client->page_size,
8515            ilt_client->flags,
8516            ilog2(ilt_client->page_size >> 12));
8517
8518         /* QM */
8519         if (QM_INIT(bp->qm_cid_count)) {
8520                 ilt_client = &ilt->clients[ILT_CLIENT_QM];
8521                 ilt_client->client_num = ILT_CLIENT_QM;
8522                 ilt_client->page_size = QM_ILT_PAGE_SZ;
8523                 ilt_client->flags = 0;
8524                 ilt_client->start = line;
8525
8526                 /* 4 bytes for each cid */
8527                 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
8528                                                          QM_ILT_PAGE_SZ);
8529
8530                 ilt_client->end = line - 1;
8531
8532                 DP(NETIF_MSG_IFUP,
8533                    "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8534                    ilt_client->start,
8535                    ilt_client->end,
8536                    ilt_client->page_size,
8537                    ilt_client->flags,
8538                    ilog2(ilt_client->page_size >> 12));
8539         }
8540
8541         if (CNIC_SUPPORT(bp)) {
8542                 /* SRC */
8543                 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
8544                 ilt_client->client_num = ILT_CLIENT_SRC;
8545                 ilt_client->page_size = SRC_ILT_PAGE_SZ;
8546                 ilt_client->flags = 0;
8547                 ilt_client->start = line;
8548                 line += SRC_ILT_LINES;
8549                 ilt_client->end = line - 1;
8550
8551                 DP(NETIF_MSG_IFUP,
8552                    "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8553                    ilt_client->start,
8554                    ilt_client->end,
8555                    ilt_client->page_size,
8556                    ilt_client->flags,
8557                    ilog2(ilt_client->page_size >> 12));
8558
8559                 /* TM */
8560                 ilt_client = &ilt->clients[ILT_CLIENT_TM];
8561                 ilt_client->client_num = ILT_CLIENT_TM;
8562                 ilt_client->page_size = TM_ILT_PAGE_SZ;
8563                 ilt_client->flags = 0;
8564                 ilt_client->start = line;
8565                 line += TM_ILT_LINES;
8566                 ilt_client->end = line - 1;
8567
8568                 DP(NETIF_MSG_IFUP,
8569                    "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8570                    ilt_client->start,
8571                    ilt_client->end,
8572                    ilt_client->page_size,
8573                    ilt_client->flags,
8574                    ilog2(ilt_client->page_size >> 12));
8575         }
8576
8577         BUG_ON(line > ILT_MAX_LINES);
8578 }
8579
8580 /**
8581  * bnx2x_pf_q_prep_init - prepare INIT transition parameters
8582  *
8583  * @bp:                 driver handle
8584  * @fp:                 pointer to fastpath
8585  * @init_params:        pointer to parameters structure
8586  *
8587  * parameters configured:
8588  *      - HC configuration
8589  *      - Queue's CDU context
8590  */
8591 static void bnx2x_pf_q_prep_init(struct bnx2x *bp,
8592         struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
8593 {
8594         u8 cos;
8595         int cxt_index, cxt_offset;
8596
8597         /* FCoE Queue uses Default SB, thus has no HC capabilities */
8598         if (!IS_FCOE_FP(fp)) {
8599                 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
8600                 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
8601
8602                 /* If HC is supported, enable host coalescing in the transition
8603                  * to INIT state.
8604                  */
8605                 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
8606                 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
8607
8608                 /* HC rate */
8609                 init_params->rx.hc_rate = bp->rx_ticks ?
8610                         (1000000 / bp->rx_ticks) : 0;
8611                 init_params->tx.hc_rate = bp->tx_ticks ?
8612                         (1000000 / bp->tx_ticks) : 0;
8613
8614                 /* FW SB ID */
8615                 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
8616                         fp->fw_sb_id;
8617
8618                 /*
8619                  * CQ index among the SB indices: FCoE clients uses the default
8620                  * SB, therefore it's different.
8621                  */
8622                 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
8623                 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
8624         }
8625
8626         /* set maximum number of COSs supported by this queue */
8627         init_params->max_cos = fp->max_cos;
8628
8629         DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n",
8630             fp->index, init_params->max_cos);
8631
8632         /* set the context pointers queue object */
8633         for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
8634                 cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS;
8635                 cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index *
8636                                 ILT_PAGE_CIDS);
8637                 init_params->cxts[cos] =
8638                         &bp->context[cxt_index].vcxt[cxt_offset].eth;
8639         }
8640 }
8641
8642 static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8643                         struct bnx2x_queue_state_params *q_params,
8644                         struct bnx2x_queue_setup_tx_only_params *tx_only_params,
8645                         int tx_index, bool leading)
8646 {
8647         memset(tx_only_params, 0, sizeof(*tx_only_params));
8648
8649         /* Set the command */
8650         q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
8651
8652         /* Set tx-only QUEUE flags: don't zero statistics */
8653         tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
8654
8655         /* choose the index of the cid to send the slow path on */
8656         tx_only_params->cid_index = tx_index;
8657
8658         /* Set general TX_ONLY_SETUP parameters */
8659         bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
8660
8661         /* Set Tx TX_ONLY_SETUP parameters */
8662         bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
8663
8664         DP(NETIF_MSG_IFUP,
8665            "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
8666            tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
8667            q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
8668            tx_only_params->gen_params.spcl_id, tx_only_params->flags);
8669
8670         /* send the ramrod */
8671         return bnx2x_queue_state_change(bp, q_params);
8672 }
8673
8674 /**
8675  * bnx2x_setup_queue - setup queue
8676  *
8677  * @bp:         driver handle
8678  * @fp:         pointer to fastpath
8679  * @leading:    is leading
8680  *
8681  * This function performs 2 steps in a Queue state machine
8682  *      actually: 1) RESET->INIT 2) INIT->SETUP
8683  */
8684
8685 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8686                        bool leading)
8687 {
8688         struct bnx2x_queue_state_params q_params = {NULL};
8689         struct bnx2x_queue_setup_params *setup_params =
8690                                                 &q_params.params.setup;
8691         struct bnx2x_queue_setup_tx_only_params *tx_only_params =
8692                                                 &q_params.params.tx_only;
8693         int rc;
8694         u8 tx_index;
8695
8696         DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index);
8697
8698         /* reset IGU state skip FCoE L2 queue */
8699         if (!IS_FCOE_FP(fp))
8700                 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
8701                              IGU_INT_ENABLE, 0);
8702
8703         q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8704         /* We want to wait for completion in this context */
8705         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8706
8707         /* Prepare the INIT parameters */
8708         bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
8709
8710         /* Set the command */
8711         q_params.cmd = BNX2X_Q_CMD_INIT;
8712
8713         /* Change the state to INIT */
8714         rc = bnx2x_queue_state_change(bp, &q_params);
8715         if (rc) {
8716                 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
8717                 return rc;
8718         }
8719
8720         DP(NETIF_MSG_IFUP, "init complete\n");
8721
8722         /* Now move the Queue to the SETUP state... */
8723         memset(setup_params, 0, sizeof(*setup_params));
8724
8725         /* Set QUEUE flags */
8726         setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
8727
8728         /* Set general SETUP parameters */
8729         bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
8730                                 FIRST_TX_COS_INDEX);
8731
8732         bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
8733                             &setup_params->rxq_params);
8734
8735         bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
8736                            FIRST_TX_COS_INDEX);
8737
8738         /* Set the command */
8739         q_params.cmd = BNX2X_Q_CMD_SETUP;
8740
8741         if (IS_FCOE_FP(fp))
8742                 bp->fcoe_init = true;
8743
8744         /* Change the state to SETUP */
8745         rc = bnx2x_queue_state_change(bp, &q_params);
8746         if (rc) {
8747                 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
8748                 return rc;
8749         }
8750
8751         /* loop through the relevant tx-only indices */
8752         for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8753               tx_index < fp->max_cos;
8754               tx_index++) {
8755
8756                 /* prepare and send tx-only ramrod*/
8757                 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
8758                                           tx_only_params, tx_index, leading);
8759                 if (rc) {
8760                         BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
8761                                   fp->index, tx_index);
8762                         return rc;
8763                 }
8764         }
8765
8766         return rc;
8767 }
8768
8769 static int bnx2x_stop_queue(struct bnx2x *bp, int index)
8770 {
8771         struct bnx2x_fastpath *fp = &bp->fp[index];
8772         struct bnx2x_fp_txdata *txdata;
8773         struct bnx2x_queue_state_params q_params = {NULL};
8774         int rc, tx_index;
8775
8776         DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid);
8777
8778         q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8779         /* We want to wait for completion in this context */
8780         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8781
8782         /* close tx-only connections */
8783         for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8784              tx_index < fp->max_cos;
8785              tx_index++){
8786
8787                 /* ascertain this is a normal queue*/
8788                 txdata = fp->txdata_ptr[tx_index];
8789
8790                 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n",
8791                                                         txdata->txq_index);
8792
8793                 /* send halt terminate on tx-only connection */
8794                 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8795                 memset(&q_params.params.terminate, 0,
8796                        sizeof(q_params.params.terminate));
8797                 q_params.params.terminate.cid_index = tx_index;
8798
8799                 rc = bnx2x_queue_state_change(bp, &q_params);
8800                 if (rc)
8801                         return rc;
8802
8803                 /* send halt terminate on tx-only connection */
8804                 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8805                 memset(&q_params.params.cfc_del, 0,
8806                        sizeof(q_params.params.cfc_del));
8807                 q_params.params.cfc_del.cid_index = tx_index;
8808                 rc = bnx2x_queue_state_change(bp, &q_params);
8809                 if (rc)
8810                         return rc;
8811         }
8812         /* Stop the primary connection: */
8813         /* ...halt the connection */
8814         q_params.cmd = BNX2X_Q_CMD_HALT;
8815         rc = bnx2x_queue_state_change(bp, &q_params);
8816         if (rc)
8817                 return rc;
8818
8819         /* ...terminate the connection */
8820         q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8821         memset(&q_params.params.terminate, 0,
8822                sizeof(q_params.params.terminate));
8823         q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
8824         rc = bnx2x_queue_state_change(bp, &q_params);
8825         if (rc)
8826                 return rc;
8827         /* ...delete cfc entry */
8828         q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8829         memset(&q_params.params.cfc_del, 0,
8830                sizeof(q_params.params.cfc_del));
8831         q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
8832         return bnx2x_queue_state_change(bp, &q_params);
8833 }
8834
8835 static void bnx2x_reset_func(struct bnx2x *bp)
8836 {
8837         int port = BP_PORT(bp);
8838         int func = BP_FUNC(bp);
8839         int i;
8840
8841         /* Disable the function in the FW */
8842         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
8843         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
8844         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
8845         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
8846
8847         /* FP SBs */
8848         for_each_eth_queue(bp, i) {
8849                 struct bnx2x_fastpath *fp = &bp->fp[i];
8850                 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8851                            CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
8852                            SB_DISABLED);
8853         }
8854
8855         if (CNIC_LOADED(bp))
8856                 /* CNIC SB */
8857                 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8858                         CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET
8859                         (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED);
8860
8861         /* SP SB */
8862         REG_WR8(bp, BAR_CSTRORM_INTMEM +
8863                 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
8864                 SB_DISABLED);
8865
8866         for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
8867                 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
8868                        0);
8869
8870         /* Configure IGU */
8871         if (bp->common.int_block == INT_BLOCK_HC) {
8872                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8873                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8874         } else {
8875                 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8876                 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8877         }
8878
8879         if (CNIC_LOADED(bp)) {
8880                 /* Disable Timer scan */
8881                 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
8882                 /*
8883                  * Wait for at least 10ms and up to 2 second for the timers
8884                  * scan to complete
8885                  */
8886                 for (i = 0; i < 200; i++) {
8887                         usleep_range(10000, 20000);
8888                         if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
8889                                 break;
8890                 }
8891         }
8892         /* Clear ILT */
8893         bnx2x_clear_func_ilt(bp, func);
8894
8895         /* Timers workaround bug for E2: if this is vnic-3,
8896          * we need to set the entire ilt range for this timers.
8897          */
8898         if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
8899                 struct ilt_client_info ilt_cli;
8900                 /* use dummy TM client */
8901                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
8902                 ilt_cli.start = 0;
8903                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
8904                 ilt_cli.client_num = ILT_CLIENT_TM;
8905
8906                 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
8907         }
8908
8909         /* this assumes that reset_port() called before reset_func()*/
8910         if (!CHIP_IS_E1x(bp))
8911                 bnx2x_pf_disable(bp);
8912
8913         bp->dmae_ready = 0;
8914 }
8915
8916 static void bnx2x_reset_port(struct bnx2x *bp)
8917 {
8918         int port = BP_PORT(bp);
8919         u32 val;
8920
8921         /* Reset physical Link */
8922         bnx2x__link_reset(bp);
8923
8924         REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
8925
8926         /* Do not rcv packets to BRB */
8927         REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
8928         /* Do not direct rcv packets that are not for MCP to the BRB */
8929         REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8930                            NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
8931
8932         /* Configure AEU */
8933         REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
8934
8935         msleep(100);
8936         /* Check for BRB port occupancy */
8937         val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
8938         if (val)
8939                 DP(NETIF_MSG_IFDOWN,
8940                    "BRB1 is not empty  %d blocks are occupied\n", val);
8941
8942         /* TODO: Close Doorbell port? */
8943 }
8944
8945 static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
8946 {
8947         struct bnx2x_func_state_params func_params = {NULL};
8948
8949         /* Prepare parameters for function state transitions */
8950         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8951
8952         func_params.f_obj = &bp->func_obj;
8953         func_params.cmd = BNX2X_F_CMD_HW_RESET;
8954
8955         func_params.params.hw_init.load_phase = load_code;
8956
8957         return bnx2x_func_state_change(bp, &func_params);
8958 }
8959
8960 static int bnx2x_func_stop(struct bnx2x *bp)
8961 {
8962         struct bnx2x_func_state_params func_params = {NULL};
8963         int rc;
8964
8965         /* Prepare parameters for function state transitions */
8966         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8967         func_params.f_obj = &bp->func_obj;
8968         func_params.cmd = BNX2X_F_CMD_STOP;
8969
8970         /*
8971          * Try to stop the function the 'good way'. If fails (in case
8972          * of a parity error during bnx2x_chip_cleanup()) and we are
8973          * not in a debug mode, perform a state transaction in order to
8974          * enable further HW_RESET transaction.
8975          */
8976         rc = bnx2x_func_state_change(bp, &func_params);
8977         if (rc) {
8978 #ifdef BNX2X_STOP_ON_ERROR
8979                 return rc;
8980 #else
8981                 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
8982                 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
8983                 return bnx2x_func_state_change(bp, &func_params);
8984 #endif
8985         }
8986
8987         return 0;
8988 }
8989
8990 /**
8991  * bnx2x_send_unload_req - request unload mode from the MCP.
8992  *
8993  * @bp:                 driver handle
8994  * @unload_mode:        requested function's unload mode
8995  *
8996  * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
8997  */
8998 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
8999 {
9000         u32 reset_code = 0;
9001         int port = BP_PORT(bp);
9002
9003         /* Select the UNLOAD request mode */
9004         if (unload_mode == UNLOAD_NORMAL)
9005                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
9006
9007         else if (bp->flags & NO_WOL_FLAG)
9008                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
9009
9010         else if (bp->wol) {
9011                 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
9012                 u8 *mac_addr = bp->dev->dev_addr;
9013                 struct pci_dev *pdev = bp->pdev;
9014                 u32 val;
9015                 u16 pmc;
9016
9017                 /* The mac address is written to entries 1-4 to
9018                  * preserve entry 0 which is used by the PMF
9019                  */
9020                 u8 entry = (BP_VN(bp) + 1)*8;
9021
9022                 val = (mac_addr[0] << 8) | mac_addr[1];
9023                 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
9024
9025                 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
9026                       (mac_addr[4] << 8) | mac_addr[5];
9027                 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
9028
9029                 /* Enable the PME and clear the status */
9030                 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &pmc);
9031                 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
9032                 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, pmc);
9033
9034                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
9035
9036         } else
9037                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
9038
9039         /* Send the request to the MCP */
9040         if (!BP_NOMCP(bp))
9041                 reset_code = bnx2x_fw_command(bp, reset_code, 0);
9042         else {
9043                 int path = BP_PATH(bp);
9044
9045                 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d]      %d, %d, %d\n",
9046                    path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
9047                    bnx2x_load_count[path][2]);
9048                 bnx2x_load_count[path][0]--;
9049                 bnx2x_load_count[path][1 + port]--;
9050                 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d]  %d, %d, %d\n",
9051                    path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
9052                    bnx2x_load_count[path][2]);
9053                 if (bnx2x_load_count[path][0] == 0)
9054                         reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
9055                 else if (bnx2x_load_count[path][1 + port] == 0)
9056                         reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
9057                 else
9058                         reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
9059         }
9060
9061         return reset_code;
9062 }
9063
9064 /**
9065  * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
9066  *
9067  * @bp:         driver handle
9068  * @keep_link:          true iff link should be kept up
9069  */
9070 void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link)
9071 {
9072         u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
9073
9074         /* Report UNLOAD_DONE to MCP */
9075         if (!BP_NOMCP(bp))
9076                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
9077 }
9078
9079 static int bnx2x_func_wait_started(struct bnx2x *bp)
9080 {
9081         int tout = 50;
9082         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
9083
9084         if (!bp->port.pmf)
9085                 return 0;
9086
9087         /*
9088          * (assumption: No Attention from MCP at this stage)
9089          * PMF probably in the middle of TX disable/enable transaction
9090          * 1. Sync IRS for default SB
9091          * 2. Sync SP queue - this guarantees us that attention handling started
9092          * 3. Wait, that TX disable/enable transaction completes
9093          *
9094          * 1+2 guarantee that if DCBx attention was scheduled it already changed
9095          * pending bit of transaction from STARTED-->TX_STOPPED, if we already
9096          * received completion for the transaction the state is TX_STOPPED.
9097          * State will return to STARTED after completion of TX_STOPPED-->STARTED
9098          * transaction.
9099          */
9100
9101         /* make sure default SB ISR is done */
9102         if (msix)
9103                 synchronize_irq(bp->msix_table[0].vector);
9104         else
9105                 synchronize_irq(bp->pdev->irq);
9106
9107         flush_workqueue(bnx2x_wq);
9108         flush_workqueue(bnx2x_iov_wq);
9109
9110         while (bnx2x_func_get_state(bp, &bp->func_obj) !=
9111                                 BNX2X_F_STATE_STARTED && tout--)
9112                 msleep(20);
9113
9114         if (bnx2x_func_get_state(bp, &bp->func_obj) !=
9115                                                 BNX2X_F_STATE_STARTED) {
9116 #ifdef BNX2X_STOP_ON_ERROR
9117                 BNX2X_ERR("Wrong function state\n");
9118                 return -EBUSY;
9119 #else
9120                 /*
9121                  * Failed to complete the transaction in a "good way"
9122                  * Force both transactions with CLR bit
9123                  */
9124                 struct bnx2x_func_state_params func_params = {NULL};
9125
9126                 DP(NETIF_MSG_IFDOWN,
9127                    "Hmmm... Unexpected function state! Forcing STARTED-->TX_STOPPED-->STARTED\n");
9128
9129                 func_params.f_obj = &bp->func_obj;
9130                 __set_bit(RAMROD_DRV_CLR_ONLY,
9131                                         &func_params.ramrod_flags);
9132
9133                 /* STARTED-->TX_ST0PPED */
9134                 func_params.cmd = BNX2X_F_CMD_TX_STOP;
9135                 bnx2x_func_state_change(bp, &func_params);
9136
9137                 /* TX_ST0PPED-->STARTED */
9138                 func_params.cmd = BNX2X_F_CMD_TX_START;
9139                 return bnx2x_func_state_change(bp, &func_params);
9140 #endif
9141         }
9142
9143         return 0;
9144 }
9145
9146 static void bnx2x_disable_ptp(struct bnx2x *bp)
9147 {
9148         int port = BP_PORT(bp);
9149
9150         /* Disable sending PTP packets to host */
9151         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
9152                NIG_REG_P0_LLH_PTP_TO_HOST, 0x0);
9153
9154         /* Reset PTP event detection rules */
9155         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
9156                NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF);
9157         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
9158                NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF);
9159         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
9160                NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF);
9161         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
9162                NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF);
9163
9164         /* Disable the PTP feature */
9165         REG_WR(bp, port ? NIG_REG_P1_PTP_EN :
9166                NIG_REG_P0_PTP_EN, 0x0);
9167 }
9168
9169 /* Called during unload, to stop PTP-related stuff */
9170 void bnx2x_stop_ptp(struct bnx2x *bp)
9171 {
9172         /* Cancel PTP work queue. Should be done after the Tx queues are
9173          * drained to prevent additional scheduling.
9174          */
9175         cancel_work_sync(&bp->ptp_task);
9176
9177         if (bp->ptp_tx_skb) {
9178                 dev_kfree_skb_any(bp->ptp_tx_skb);
9179                 bp->ptp_tx_skb = NULL;
9180         }
9181
9182         /* Disable PTP in HW */
9183         bnx2x_disable_ptp(bp);
9184
9185         DP(BNX2X_MSG_PTP, "PTP stop ended successfully\n");
9186 }
9187
9188 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link)
9189 {
9190         int port = BP_PORT(bp);
9191         int i, rc = 0;
9192         u8 cos;
9193         struct bnx2x_mcast_ramrod_params rparam = {NULL};
9194         u32 reset_code;
9195
9196         /* Wait until tx fastpath tasks complete */
9197         for_each_tx_queue(bp, i) {
9198                 struct bnx2x_fastpath *fp = &bp->fp[i];
9199
9200                 for_each_cos_in_tx_queue(fp, cos)
9201                         rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
9202 #ifdef BNX2X_STOP_ON_ERROR
9203                 if (rc)
9204                         return;
9205 #endif
9206         }
9207
9208         /* Give HW time to discard old tx messages */
9209         usleep_range(1000, 2000);
9210
9211         /* Clean all ETH MACs */
9212         rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC,
9213                                 false);
9214         if (rc < 0)
9215                 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
9216
9217         /* Clean up UC list  */
9218         rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC,
9219                                 true);
9220         if (rc < 0)
9221                 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
9222                           rc);
9223
9224         /* Disable LLH */
9225         if (!CHIP_IS_E1(bp))
9226                 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
9227
9228         /* Set "drop all" (stop Rx).
9229          * We need to take a netif_addr_lock() here in order to prevent
9230          * a race between the completion code and this code.
9231          */
9232         netif_addr_lock_bh(bp->dev);
9233         /* Schedule the rx_mode command */
9234         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
9235                 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
9236         else
9237                 bnx2x_set_storm_rx_mode(bp);
9238
9239         /* Cleanup multicast configuration */
9240         rparam.mcast_obj = &bp->mcast_obj;
9241         rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
9242         if (rc < 0)
9243                 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
9244
9245         netif_addr_unlock_bh(bp->dev);
9246
9247         bnx2x_iov_chip_cleanup(bp);
9248
9249         /*
9250          * Send the UNLOAD_REQUEST to the MCP. This will return if
9251          * this function should perform FUNC, PORT or COMMON HW
9252          * reset.
9253          */
9254         reset_code = bnx2x_send_unload_req(bp, unload_mode);
9255
9256         /*
9257          * (assumption: No Attention from MCP at this stage)
9258          * PMF probably in the middle of TX disable/enable transaction
9259          */
9260         rc = bnx2x_func_wait_started(bp);
9261         if (rc) {
9262                 BNX2X_ERR("bnx2x_func_wait_started failed\n");
9263 #ifdef BNX2X_STOP_ON_ERROR
9264                 return;
9265 #endif
9266         }
9267
9268         /* Close multi and leading connections
9269          * Completions for ramrods are collected in a synchronous way
9270          */
9271         for_each_eth_queue(bp, i)
9272                 if (bnx2x_stop_queue(bp, i))
9273 #ifdef BNX2X_STOP_ON_ERROR
9274                         return;
9275 #else
9276                         goto unload_error;
9277 #endif
9278
9279         if (CNIC_LOADED(bp)) {
9280                 for_each_cnic_queue(bp, i)
9281                         if (bnx2x_stop_queue(bp, i))
9282 #ifdef BNX2X_STOP_ON_ERROR
9283                                 return;
9284 #else
9285                                 goto unload_error;
9286 #endif
9287         }
9288
9289         /* If SP settings didn't get completed so far - something
9290          * very wrong has happen.
9291          */
9292         if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
9293                 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
9294
9295 #ifndef BNX2X_STOP_ON_ERROR
9296 unload_error:
9297 #endif
9298         rc = bnx2x_func_stop(bp);
9299         if (rc) {
9300                 BNX2X_ERR("Function stop failed!\n");
9301 #ifdef BNX2X_STOP_ON_ERROR
9302                 return;
9303 #endif
9304         }
9305
9306         /* stop_ptp should be after the Tx queues are drained to prevent
9307          * scheduling to the cancelled PTP work queue. It should also be after
9308          * function stop ramrod is sent, since as part of this ramrod FW access
9309          * PTP registers.
9310          */
9311         bnx2x_stop_ptp(bp);
9312
9313         /* Disable HW interrupts, NAPI */
9314         bnx2x_netif_stop(bp, 1);
9315         /* Delete all NAPI objects */
9316         bnx2x_del_all_napi(bp);
9317         if (CNIC_LOADED(bp))
9318                 bnx2x_del_all_napi_cnic(bp);
9319
9320         /* Release IRQs */
9321         bnx2x_free_irq(bp);
9322
9323         /* Reset the chip */
9324         rc = bnx2x_reset_hw(bp, reset_code);
9325         if (rc)
9326                 BNX2X_ERR("HW_RESET failed\n");
9327
9328         /* Report UNLOAD_DONE to MCP */
9329         bnx2x_send_unload_done(bp, keep_link);
9330 }
9331
9332 void bnx2x_disable_close_the_gate(struct bnx2x *bp)
9333 {
9334         u32 val;
9335
9336         DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n");
9337
9338         if (CHIP_IS_E1(bp)) {
9339                 int port = BP_PORT(bp);
9340                 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
9341                         MISC_REG_AEU_MASK_ATTN_FUNC_0;
9342
9343                 val = REG_RD(bp, addr);
9344                 val &= ~(0x300);
9345                 REG_WR(bp, addr, val);
9346         } else {
9347                 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
9348                 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
9349                          MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
9350                 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
9351         }
9352 }
9353
9354 /* Close gates #2, #3 and #4: */
9355 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
9356 {
9357         u32 val;
9358
9359         /* Gates #2 and #4a are closed/opened for "not E1" only */
9360         if (!CHIP_IS_E1(bp)) {
9361                 /* #4 */
9362                 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
9363                 /* #2 */
9364                 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
9365         }
9366
9367         /* #3 */
9368         if (CHIP_IS_E1x(bp)) {
9369                 /* Prevent interrupts from HC on both ports */
9370                 val = REG_RD(bp, HC_REG_CONFIG_1);
9371                 REG_WR(bp, HC_REG_CONFIG_1,
9372                        (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
9373                        (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
9374
9375                 val = REG_RD(bp, HC_REG_CONFIG_0);
9376                 REG_WR(bp, HC_REG_CONFIG_0,
9377                        (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
9378                        (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
9379         } else {
9380                 /* Prevent incoming interrupts in IGU */
9381                 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
9382
9383                 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
9384                        (!close) ?
9385                        (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
9386                        (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
9387         }
9388
9389         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
9390                 close ? "closing" : "opening");
9391         mmiowb();
9392 }
9393
9394 #define SHARED_MF_CLP_MAGIC  0x80000000 /* `magic' bit */
9395
9396 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
9397 {
9398         /* Do some magic... */
9399         u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9400         *magic_val = val & SHARED_MF_CLP_MAGIC;
9401         MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
9402 }
9403
9404 /**
9405  * bnx2x_clp_reset_done - restore the value of the `magic' bit.
9406  *
9407  * @bp:         driver handle
9408  * @magic_val:  old value of the `magic' bit.
9409  */
9410 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
9411 {
9412         /* Restore the `magic' bit value... */
9413         u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9414         MF_CFG_WR(bp, shared_mf_config.clp_mb,
9415                 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
9416 }
9417
9418 /**
9419  * bnx2x_reset_mcp_prep - prepare for MCP reset.
9420  *
9421  * @bp:         driver handle
9422  * @magic_val:  old value of 'magic' bit.
9423  *
9424  * Takes care of CLP configurations.
9425  */
9426 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
9427 {
9428         u32 shmem;
9429         u32 validity_offset;
9430
9431         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n");
9432
9433         /* Set `magic' bit in order to save MF config */
9434         if (!CHIP_IS_E1(bp))
9435                 bnx2x_clp_reset_prep(bp, magic_val);
9436
9437         /* Get shmem offset */
9438         shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9439         validity_offset =
9440                 offsetof(struct shmem_region, validity_map[BP_PORT(bp)]);
9441
9442         /* Clear validity map flags */
9443         if (shmem > 0)
9444                 REG_WR(bp, shmem + validity_offset, 0);
9445 }
9446
9447 #define MCP_TIMEOUT      5000   /* 5 seconds (in ms) */
9448 #define MCP_ONE_TIMEOUT  100    /* 100 ms */
9449
9450 /**
9451  * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
9452  *
9453  * @bp: driver handle
9454  */
9455 static void bnx2x_mcp_wait_one(struct bnx2x *bp)
9456 {
9457         /* special handling for emulation and FPGA,
9458            wait 10 times longer */
9459         if (CHIP_REV_IS_SLOW(bp))
9460                 msleep(MCP_ONE_TIMEOUT*10);
9461         else
9462                 msleep(MCP_ONE_TIMEOUT);
9463 }
9464
9465 /*
9466  * initializes bp->common.shmem_base and waits for validity signature to appear
9467  */
9468 static int bnx2x_init_shmem(struct bnx2x *bp)
9469 {
9470         int cnt = 0;
9471         u32 val = 0;
9472
9473         do {
9474                 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9475                 if (bp->common.shmem_base) {
9476                         val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
9477                         if (val & SHR_MEM_VALIDITY_MB)
9478                                 return 0;
9479                 }
9480
9481                 bnx2x_mcp_wait_one(bp);
9482
9483         } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
9484
9485         BNX2X_ERR("BAD MCP validity signature\n");
9486
9487         return -ENODEV;
9488 }
9489
9490 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
9491 {
9492         int rc = bnx2x_init_shmem(bp);
9493
9494         /* Restore the `magic' bit value */
9495         if (!CHIP_IS_E1(bp))
9496                 bnx2x_clp_reset_done(bp, magic_val);
9497
9498         return rc;
9499 }
9500
9501 static void bnx2x_pxp_prep(struct bnx2x *bp)
9502 {
9503         if (!CHIP_IS_E1(bp)) {
9504                 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
9505                 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
9506                 mmiowb();
9507         }
9508 }
9509
9510 /*
9511  * Reset the whole chip except for:
9512  *      - PCIE core
9513  *      - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
9514  *              one reset bit)
9515  *      - IGU
9516  *      - MISC (including AEU)
9517  *      - GRC
9518  *      - RBCN, RBCP
9519  */
9520 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
9521 {
9522         u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
9523         u32 global_bits2, stay_reset2;
9524
9525         /*
9526          * Bits that have to be set in reset_mask2 if we want to reset 'global'
9527          * (per chip) blocks.
9528          */
9529         global_bits2 =
9530                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
9531                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
9532
9533         /* Don't reset the following blocks.
9534          * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
9535          *            reset, as in 4 port device they might still be owned
9536          *            by the MCP (there is only one leader per path).
9537          */
9538         not_reset_mask1 =
9539                 MISC_REGISTERS_RESET_REG_1_RST_HC |
9540                 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
9541                 MISC_REGISTERS_RESET_REG_1_RST_PXP;
9542
9543         not_reset_mask2 =
9544                 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
9545                 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
9546                 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
9547                 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
9548                 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
9549                 MISC_REGISTERS_RESET_REG_2_RST_GRC  |
9550                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
9551                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
9552                 MISC_REGISTERS_RESET_REG_2_RST_ATC |
9553                 MISC_REGISTERS_RESET_REG_2_PGLC |
9554                 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
9555                 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
9556                 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
9557                 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
9558                 MISC_REGISTERS_RESET_REG_2_UMAC0 |
9559                 MISC_REGISTERS_RESET_REG_2_UMAC1;
9560
9561         /*
9562          * Keep the following blocks in reset:
9563          *  - all xxMACs are handled by the bnx2x_link code.
9564          */
9565         stay_reset2 =
9566                 MISC_REGISTERS_RESET_REG_2_XMAC |
9567                 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
9568
9569         /* Full reset masks according to the chip */
9570         reset_mask1 = 0xffffffff;
9571
9572         if (CHIP_IS_E1(bp))
9573                 reset_mask2 = 0xffff;
9574         else if (CHIP_IS_E1H(bp))
9575                 reset_mask2 = 0x1ffff;
9576         else if (CHIP_IS_E2(bp))
9577                 reset_mask2 = 0xfffff;
9578         else /* CHIP_IS_E3 */
9579                 reset_mask2 = 0x3ffffff;
9580
9581         /* Don't reset global blocks unless we need to */
9582         if (!global)
9583                 reset_mask2 &= ~global_bits2;
9584
9585         /*
9586          * In case of attention in the QM, we need to reset PXP
9587          * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
9588          * because otherwise QM reset would release 'close the gates' shortly
9589          * before resetting the PXP, then the PSWRQ would send a write
9590          * request to PGLUE. Then when PXP is reset, PGLUE would try to
9591          * read the payload data from PSWWR, but PSWWR would not
9592          * respond. The write queue in PGLUE would stuck, dmae commands
9593          * would not return. Therefore it's important to reset the second
9594          * reset register (containing the
9595          * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
9596          * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
9597          * bit).
9598          */
9599         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
9600                reset_mask2 & (~not_reset_mask2));
9601
9602         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
9603                reset_mask1 & (~not_reset_mask1));
9604
9605         barrier();
9606         mmiowb();
9607
9608         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
9609                reset_mask2 & (~stay_reset2));
9610
9611         barrier();
9612         mmiowb();
9613
9614         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
9615         mmiowb();
9616 }
9617
9618 /**
9619  * bnx2x_er_poll_igu_vq - poll for pending writes bit.
9620  * It should get cleared in no more than 1s.
9621  *
9622  * @bp: driver handle
9623  *
9624  * It should get cleared in no more than 1s. Returns 0 if
9625  * pending writes bit gets cleared.
9626  */
9627 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
9628 {
9629         u32 cnt = 1000;
9630         u32 pend_bits = 0;
9631
9632         do {
9633                 pend_bits  = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
9634
9635                 if (pend_bits == 0)
9636                         break;
9637
9638                 usleep_range(1000, 2000);
9639         } while (cnt-- > 0);
9640
9641         if (cnt <= 0) {
9642                 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
9643                           pend_bits);
9644                 return -EBUSY;
9645         }
9646
9647         return 0;
9648 }
9649
9650 static int bnx2x_process_kill(struct bnx2x *bp, bool global)
9651 {
9652         int cnt = 1000;
9653         u32 val = 0;
9654         u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
9655         u32 tags_63_32 = 0;
9656
9657         /* Empty the Tetris buffer, wait for 1s */
9658         do {
9659                 sr_cnt  = REG_RD(bp, PXP2_REG_RD_SR_CNT);
9660                 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
9661                 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
9662                 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
9663                 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
9664                 if (CHIP_IS_E3(bp))
9665                         tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32);
9666
9667                 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
9668                     ((port_is_idle_0 & 0x1) == 0x1) &&
9669                     ((port_is_idle_1 & 0x1) == 0x1) &&
9670                     (pgl_exp_rom2 == 0xffffffff) &&
9671                     (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff)))
9672                         break;
9673                 usleep_range(1000, 2000);
9674         } while (cnt-- > 0);
9675
9676         if (cnt <= 0) {
9677                 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
9678                 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
9679                           sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
9680                           pgl_exp_rom2);
9681                 return -EAGAIN;
9682         }
9683
9684         barrier();
9685
9686         /* Close gates #2, #3 and #4 */
9687         bnx2x_set_234_gates(bp, true);
9688
9689         /* Poll for IGU VQs for 57712 and newer chips */
9690         if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
9691                 return -EAGAIN;
9692
9693         /* TBD: Indicate that "process kill" is in progress to MCP */
9694
9695         /* Clear "unprepared" bit */
9696         REG_WR(bp, MISC_REG_UNPREPARED, 0);
9697         barrier();
9698
9699         /* Make sure all is written to the chip before the reset */
9700         mmiowb();
9701
9702         /* Wait for 1ms to empty GLUE and PCI-E core queues,
9703          * PSWHST, GRC and PSWRD Tetris buffer.
9704          */
9705         usleep_range(1000, 2000);
9706
9707         /* Prepare to chip reset: */
9708         /* MCP */
9709         if (global)
9710                 bnx2x_reset_mcp_prep(bp, &val);
9711
9712         /* PXP */
9713         bnx2x_pxp_prep(bp);
9714         barrier();
9715
9716         /* reset the chip */
9717         bnx2x_process_kill_chip_reset(bp, global);
9718         barrier();
9719
9720         /* clear errors in PGB */
9721         if (!CHIP_IS_E1x(bp))
9722                 REG_WR(bp, PGLUE_B_REG_LATCHED_ERRORS_CLR, 0x7f);
9723
9724         /* Recover after reset: */
9725         /* MCP */
9726         if (global && bnx2x_reset_mcp_comp(bp, val))
9727                 return -EAGAIN;
9728
9729         /* TBD: Add resetting the NO_MCP mode DB here */
9730
9731         /* Open the gates #2, #3 and #4 */
9732         bnx2x_set_234_gates(bp, false);
9733
9734         /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
9735          * reset state, re-enable attentions. */
9736
9737         return 0;
9738 }
9739
9740 static int bnx2x_leader_reset(struct bnx2x *bp)
9741 {
9742         int rc = 0;
9743         bool global = bnx2x_reset_is_global(bp);
9744         u32 load_code;
9745
9746         /* if not going to reset MCP - load "fake" driver to reset HW while
9747          * driver is owner of the HW
9748          */
9749         if (!global && !BP_NOMCP(bp)) {
9750                 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ,
9751                                              DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
9752                 if (!load_code) {
9753                         BNX2X_ERR("MCP response failure, aborting\n");
9754                         rc = -EAGAIN;
9755                         goto exit_leader_reset;
9756                 }
9757                 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
9758                     (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
9759                         BNX2X_ERR("MCP unexpected resp, aborting\n");
9760                         rc = -EAGAIN;
9761                         goto exit_leader_reset2;
9762                 }
9763                 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
9764                 if (!load_code) {
9765                         BNX2X_ERR("MCP response failure, aborting\n");
9766                         rc = -EAGAIN;
9767                         goto exit_leader_reset2;
9768                 }
9769         }
9770
9771         /* Try to recover after the failure */
9772         if (bnx2x_process_kill(bp, global)) {
9773                 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
9774                           BP_PATH(bp));
9775                 rc = -EAGAIN;
9776                 goto exit_leader_reset2;
9777         }
9778
9779         /*
9780          * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
9781          * state.
9782          */
9783         bnx2x_set_reset_done(bp);
9784         if (global)
9785                 bnx2x_clear_reset_global(bp);
9786
9787 exit_leader_reset2:
9788         /* unload "fake driver" if it was loaded */
9789         if (!global && !BP_NOMCP(bp)) {
9790                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
9791                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
9792         }
9793 exit_leader_reset:
9794         bp->is_leader = 0;
9795         bnx2x_release_leader_lock(bp);
9796         smp_mb();
9797         return rc;
9798 }
9799
9800 static void bnx2x_recovery_failed(struct bnx2x *bp)
9801 {
9802         netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
9803
9804         /* Disconnect this device */
9805         netif_device_detach(bp->dev);
9806
9807         /*
9808          * Block ifup for all function on this engine until "process kill"
9809          * or power cycle.
9810          */
9811         bnx2x_set_reset_in_progress(bp);
9812
9813         /* Shut down the power */
9814         bnx2x_set_power_state(bp, PCI_D3hot);
9815
9816         bp->recovery_state = BNX2X_RECOVERY_FAILED;
9817
9818         smp_mb();
9819 }
9820
9821 /*
9822  * Assumption: runs under rtnl lock. This together with the fact
9823  * that it's called only from bnx2x_sp_rtnl() ensure that it
9824  * will never be called when netif_running(bp->dev) is false.
9825  */
9826 static void bnx2x_parity_recover(struct bnx2x *bp)
9827 {
9828         bool global = false;
9829         u32 error_recovered, error_unrecovered;
9830         bool is_parity;
9831
9832         DP(NETIF_MSG_HW, "Handling parity\n");
9833         while (1) {
9834                 switch (bp->recovery_state) {
9835                 case BNX2X_RECOVERY_INIT:
9836                         DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
9837                         is_parity = bnx2x_chk_parity_attn(bp, &global, false);
9838                         WARN_ON(!is_parity);
9839
9840                         /* Try to get a LEADER_LOCK HW lock */
9841                         if (bnx2x_trylock_leader_lock(bp)) {
9842                                 bnx2x_set_reset_in_progress(bp);
9843                                 /*
9844                                  * Check if there is a global attention and if
9845                                  * there was a global attention, set the global
9846                                  * reset bit.
9847                                  */
9848
9849                                 if (global)
9850                                         bnx2x_set_reset_global(bp);
9851
9852                                 bp->is_leader = 1;
9853                         }
9854
9855                         /* Stop the driver */
9856                         /* If interface has been removed - break */
9857                         if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false))
9858                                 return;
9859
9860                         bp->recovery_state = BNX2X_RECOVERY_WAIT;
9861
9862                         /* Ensure "is_leader", MCP command sequence and
9863                          * "recovery_state" update values are seen on other
9864                          * CPUs.
9865                          */
9866                         smp_mb();
9867                         break;
9868
9869                 case BNX2X_RECOVERY_WAIT:
9870                         DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
9871                         if (bp->is_leader) {
9872                                 int other_engine = BP_PATH(bp) ? 0 : 1;
9873                                 bool other_load_status =
9874                                         bnx2x_get_load_status(bp, other_engine);
9875                                 bool load_status =
9876                                         bnx2x_get_load_status(bp, BP_PATH(bp));
9877                                 global = bnx2x_reset_is_global(bp);
9878
9879                                 /*
9880                                  * In case of a parity in a global block, let
9881                                  * the first leader that performs a
9882                                  * leader_reset() reset the global blocks in
9883                                  * order to clear global attentions. Otherwise
9884                                  * the gates will remain closed for that
9885                                  * engine.
9886                                  */
9887                                 if (load_status ||
9888                                     (global && other_load_status)) {
9889                                         /* Wait until all other functions get
9890                                          * down.
9891                                          */
9892                                         schedule_delayed_work(&bp->sp_rtnl_task,
9893                                                                 HZ/10);
9894                                         return;
9895                                 } else {
9896                                         /* If all other functions got down -
9897                                          * try to bring the chip back to
9898                                          * normal. In any case it's an exit
9899                                          * point for a leader.
9900                                          */
9901                                         if (bnx2x_leader_reset(bp)) {
9902                                                 bnx2x_recovery_failed(bp);
9903                                                 return;
9904                                         }
9905
9906                                         /* If we are here, means that the
9907                                          * leader has succeeded and doesn't
9908                                          * want to be a leader any more. Try
9909                                          * to continue as a none-leader.
9910                                          */
9911                                         break;
9912                                 }
9913                         } else { /* non-leader */
9914                                 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
9915                                         /* Try to get a LEADER_LOCK HW lock as
9916                                          * long as a former leader may have
9917                                          * been unloaded by the user or
9918                                          * released a leadership by another
9919                                          * reason.
9920                                          */
9921                                         if (bnx2x_trylock_leader_lock(bp)) {
9922                                                 /* I'm a leader now! Restart a
9923                                                  * switch case.
9924                                                  */
9925                                                 bp->is_leader = 1;
9926                                                 break;
9927                                         }
9928
9929                                         schedule_delayed_work(&bp->sp_rtnl_task,
9930                                                                 HZ/10);
9931                                         return;
9932
9933                                 } else {
9934                                         /*
9935                                          * If there was a global attention, wait
9936                                          * for it to be cleared.
9937                                          */
9938                                         if (bnx2x_reset_is_global(bp)) {
9939                                                 schedule_delayed_work(
9940                                                         &bp->sp_rtnl_task,
9941                                                         HZ/10);
9942                                                 return;
9943                                         }
9944
9945                                         error_recovered =
9946                                           bp->eth_stats.recoverable_error;
9947                                         error_unrecovered =
9948                                           bp->eth_stats.unrecoverable_error;
9949                                         bp->recovery_state =
9950                                                 BNX2X_RECOVERY_NIC_LOADING;
9951                                         if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
9952                                                 error_unrecovered++;
9953                                                 netdev_err(bp->dev,
9954                                                            "Recovery failed. Power cycle needed\n");
9955                                                 /* Disconnect this device */
9956                                                 netif_device_detach(bp->dev);
9957                                                 /* Shut down the power */
9958                                                 bnx2x_set_power_state(
9959                                                         bp, PCI_D3hot);
9960                                                 smp_mb();
9961                                         } else {
9962                                                 bp->recovery_state =
9963                                                         BNX2X_RECOVERY_DONE;
9964                                                 error_recovered++;
9965                                                 smp_mb();
9966                                         }
9967                                         bp->eth_stats.recoverable_error =
9968                                                 error_recovered;
9969                                         bp->eth_stats.unrecoverable_error =
9970                                                 error_unrecovered;
9971
9972                                         return;
9973                                 }
9974                         }
9975                 default:
9976                         return;
9977                 }
9978         }
9979 }
9980
9981 static int bnx2x_close(struct net_device *dev);
9982
9983 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
9984  * scheduled on a general queue in order to prevent a dead lock.
9985  */
9986 static void bnx2x_sp_rtnl_task(struct work_struct *work)
9987 {
9988         struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
9989
9990         rtnl_lock();
9991
9992         if (!netif_running(bp->dev)) {
9993                 rtnl_unlock();
9994                 return;
9995         }
9996
9997         if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
9998 #ifdef BNX2X_STOP_ON_ERROR
9999                 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
10000                           "you will need to reboot when done\n");
10001                 goto sp_rtnl_not_reset;
10002 #endif
10003                 /*
10004                  * Clear all pending SP commands as we are going to reset the
10005                  * function anyway.
10006                  */
10007                 bp->sp_rtnl_state = 0;
10008                 smp_mb();
10009
10010                 bnx2x_parity_recover(bp);
10011
10012                 rtnl_unlock();
10013                 return;
10014         }
10015
10016         if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
10017 #ifdef BNX2X_STOP_ON_ERROR
10018                 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
10019                           "you will need to reboot when done\n");
10020                 goto sp_rtnl_not_reset;
10021 #endif
10022
10023                 /*
10024                  * Clear all pending SP commands as we are going to reset the
10025                  * function anyway.
10026                  */
10027                 bp->sp_rtnl_state = 0;
10028                 smp_mb();
10029
10030                 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
10031                 bnx2x_nic_load(bp, LOAD_NORMAL);
10032
10033                 rtnl_unlock();
10034                 return;
10035         }
10036 #ifdef BNX2X_STOP_ON_ERROR
10037 sp_rtnl_not_reset:
10038 #endif
10039         if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
10040                 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
10041         if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state))
10042                 bnx2x_after_function_update(bp);
10043         /*
10044          * in case of fan failure we need to reset id if the "stop on error"
10045          * debug flag is set, since we trying to prevent permanent overheating
10046          * damage
10047          */
10048         if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
10049                 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n");
10050                 netif_device_detach(bp->dev);
10051                 bnx2x_close(bp->dev);
10052                 rtnl_unlock();
10053                 return;
10054         }
10055
10056         if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) {
10057                 DP(BNX2X_MSG_SP,
10058                    "sending set mcast vf pf channel message from rtnl sp-task\n");
10059                 bnx2x_vfpf_set_mcast(bp->dev);
10060         }
10061         if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN,
10062                                &bp->sp_rtnl_state)){
10063                 if (!test_bit(__LINK_STATE_NOCARRIER, &bp->dev->state)) {
10064                         bnx2x_tx_disable(bp);
10065                         BNX2X_ERR("PF indicated channel is not servicable anymore. This means this VF device is no longer operational\n");
10066                 }
10067         }
10068
10069         if (test_and_clear_bit(BNX2X_SP_RTNL_RX_MODE, &bp->sp_rtnl_state)) {
10070                 DP(BNX2X_MSG_SP, "Handling Rx Mode setting\n");
10071                 bnx2x_set_rx_mode_inner(bp);
10072         }
10073
10074         if (test_and_clear_bit(BNX2X_SP_RTNL_HYPERVISOR_VLAN,
10075                                &bp->sp_rtnl_state))
10076                 bnx2x_pf_set_vfs_vlan(bp);
10077
10078         if (test_and_clear_bit(BNX2X_SP_RTNL_TX_STOP, &bp->sp_rtnl_state)) {
10079                 bnx2x_dcbx_stop_hw_tx(bp);
10080                 bnx2x_dcbx_resume_hw_tx(bp);
10081         }
10082
10083         if (test_and_clear_bit(BNX2X_SP_RTNL_GET_DRV_VERSION,
10084                                &bp->sp_rtnl_state))
10085                 bnx2x_update_mng_version(bp);
10086
10087         /* work which needs rtnl lock not-taken (as it takes the lock itself and
10088          * can be called from other contexts as well)
10089          */
10090         rtnl_unlock();
10091
10092         /* enable SR-IOV if applicable */
10093         if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV,
10094                                                &bp->sp_rtnl_state)) {
10095                 bnx2x_disable_sriov(bp);
10096                 bnx2x_enable_sriov(bp);
10097         }
10098 }
10099
10100 static void bnx2x_period_task(struct work_struct *work)
10101 {
10102         struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
10103
10104         if (!netif_running(bp->dev))
10105                 goto period_task_exit;
10106
10107         if (CHIP_REV_IS_SLOW(bp)) {
10108                 BNX2X_ERR("period task called on emulation, ignoring\n");
10109                 goto period_task_exit;
10110         }
10111
10112         bnx2x_acquire_phy_lock(bp);
10113         /*
10114          * The barrier is needed to ensure the ordering between the writing to
10115          * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
10116          * the reading here.
10117          */
10118         smp_mb();
10119         if (bp->port.pmf) {
10120                 bnx2x_period_func(&bp->link_params, &bp->link_vars);
10121
10122                 /* Re-queue task in 1 sec */
10123                 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
10124         }
10125
10126         bnx2x_release_phy_lock(bp);
10127 period_task_exit:
10128         return;
10129 }
10130
10131 /*
10132  * Init service functions
10133  */
10134
10135 static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
10136 {
10137         u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
10138         u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
10139         return base + (BP_ABS_FUNC(bp)) * stride;
10140 }
10141
10142 static void bnx2x_prev_unload_close_mac(struct bnx2x *bp,
10143                                         struct bnx2x_mac_vals *vals)
10144 {
10145         u32 val, base_addr, offset, mask, reset_reg;
10146         bool mac_stopped = false;
10147         u8 port = BP_PORT(bp);
10148
10149         /* reset addresses as they also mark which values were changed */
10150         vals->bmac_addr = 0;
10151         vals->umac_addr = 0;
10152         vals->xmac_addr = 0;
10153         vals->emac_addr = 0;
10154
10155         reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);
10156
10157         if (!CHIP_IS_E3(bp)) {
10158                 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
10159                 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
10160                 if ((mask & reset_reg) && val) {
10161                         u32 wb_data[2];
10162                         BNX2X_DEV_INFO("Disable bmac Rx\n");
10163                         base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM
10164                                                 : NIG_REG_INGRESS_BMAC0_MEM;
10165                         offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL
10166                                                 : BIGMAC_REGISTER_BMAC_CONTROL;
10167
10168                         /*
10169                          * use rd/wr since we cannot use dmae. This is safe
10170                          * since MCP won't access the bus due to the request
10171                          * to unload, and no function on the path can be
10172                          * loaded at this time.
10173                          */
10174                         wb_data[0] = REG_RD(bp, base_addr + offset);
10175                         wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);
10176                         vals->bmac_addr = base_addr + offset;
10177                         vals->bmac_val[0] = wb_data[0];
10178                         vals->bmac_val[1] = wb_data[1];
10179                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
10180                         REG_WR(bp, vals->bmac_addr, wb_data[0]);
10181                         REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]);
10182                 }
10183                 BNX2X_DEV_INFO("Disable emac Rx\n");
10184                 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4;
10185                 vals->emac_val = REG_RD(bp, vals->emac_addr);
10186                 REG_WR(bp, vals->emac_addr, 0);
10187                 mac_stopped = true;
10188         } else {
10189                 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
10190                         BNX2X_DEV_INFO("Disable xmac Rx\n");
10191                         base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
10192                         val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);
10193                         REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
10194                                val & ~(1 << 1));
10195                         REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
10196                                val | (1 << 1));
10197                         vals->xmac_addr = base_addr + XMAC_REG_CTRL;
10198                         vals->xmac_val = REG_RD(bp, vals->xmac_addr);
10199                         REG_WR(bp, vals->xmac_addr, 0);
10200                         mac_stopped = true;
10201                 }
10202                 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
10203                 if (mask & reset_reg) {
10204                         BNX2X_DEV_INFO("Disable umac Rx\n");
10205                         base_addr = BP_PORT(bp) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
10206                         vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;
10207                         vals->umac_val = REG_RD(bp, vals->umac_addr);
10208                         REG_WR(bp, vals->umac_addr, 0);
10209                         mac_stopped = true;
10210                 }
10211         }
10212
10213         if (mac_stopped)
10214                 msleep(20);
10215 }
10216
10217 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
10218 #define BNX2X_PREV_UNDI_PROD_ADDR_H(f) (BAR_TSTRORM_INTMEM + \
10219                                         0x1848 + ((f) << 4))
10220 #define BNX2X_PREV_UNDI_RCQ(val)        ((val) & 0xffff)
10221 #define BNX2X_PREV_UNDI_BD(val)         ((val) >> 16 & 0xffff)
10222 #define BNX2X_PREV_UNDI_PROD(rcq, bd)   ((bd) << 16 | (rcq))
10223
10224 #define BCM_5710_UNDI_FW_MF_MAJOR       (0x07)
10225 #define BCM_5710_UNDI_FW_MF_MINOR       (0x08)
10226 #define BCM_5710_UNDI_FW_MF_VERS        (0x05)
10227
10228 static bool bnx2x_prev_is_after_undi(struct bnx2x *bp)
10229 {
10230         /* UNDI marks its presence in DORQ -
10231          * it initializes CID offset for normal bell to 0x7
10232          */
10233         if (!(REG_RD(bp, MISC_REG_RESET_REG_1) &
10234             MISC_REGISTERS_RESET_REG_1_RST_DORQ))
10235                 return false;
10236
10237         if (REG_RD(bp, DORQ_REG_NORM_CID_OFST) == 0x7) {
10238                 BNX2X_DEV_INFO("UNDI previously loaded\n");
10239                 return true;
10240         }
10241
10242         return false;
10243 }
10244
10245 static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 inc)
10246 {
10247         u16 rcq, bd;
10248         u32 addr, tmp_reg;
10249
10250         if (BP_FUNC(bp) < 2)
10251                 addr = BNX2X_PREV_UNDI_PROD_ADDR(BP_PORT(bp));
10252         else
10253                 addr = BNX2X_PREV_UNDI_PROD_ADDR_H(BP_FUNC(bp) - 2);
10254
10255         tmp_reg = REG_RD(bp, addr);
10256         rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
10257         bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
10258
10259         tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
10260         REG_WR(bp, addr, tmp_reg);
10261
10262         BNX2X_DEV_INFO("UNDI producer [%d/%d][%08x] rings bd -> 0x%04x, rcq -> 0x%04x\n",
10263                        BP_PORT(bp), BP_FUNC(bp), addr, bd, rcq);
10264 }
10265
10266 static int bnx2x_prev_mcp_done(struct bnx2x *bp)
10267 {
10268         u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE,
10269                                   DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
10270         if (!rc) {
10271                 BNX2X_ERR("MCP response failure, aborting\n");
10272                 return -EBUSY;
10273         }
10274
10275         return 0;
10276 }
10277
10278 static struct bnx2x_prev_path_list *
10279                 bnx2x_prev_path_get_entry(struct bnx2x *bp)
10280 {
10281         struct bnx2x_prev_path_list *tmp_list;
10282
10283         list_for_each_entry(tmp_list, &bnx2x_prev_list, list)
10284                 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
10285                     bp->pdev->bus->number == tmp_list->bus &&
10286                     BP_PATH(bp) == tmp_list->path)
10287                         return tmp_list;
10288
10289         return NULL;
10290 }
10291
10292 static int bnx2x_prev_path_mark_eeh(struct bnx2x *bp)
10293 {
10294         struct bnx2x_prev_path_list *tmp_list;
10295         int rc;
10296
10297         rc = down_interruptible(&bnx2x_prev_sem);
10298         if (rc) {
10299                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10300                 return rc;
10301         }
10302
10303         tmp_list = bnx2x_prev_path_get_entry(bp);
10304         if (tmp_list) {
10305                 tmp_list->aer = 1;
10306                 rc = 0;
10307         } else {
10308                 BNX2X_ERR("path %d: Entry does not exist for eeh; Flow occurs before initial insmod is over ?\n",
10309                           BP_PATH(bp));
10310         }
10311
10312         up(&bnx2x_prev_sem);
10313
10314         return rc;
10315 }
10316
10317 static bool bnx2x_prev_is_path_marked(struct bnx2x *bp)
10318 {
10319         struct bnx2x_prev_path_list *tmp_list;
10320         bool rc = false;
10321
10322         if (down_trylock(&bnx2x_prev_sem))
10323                 return false;
10324
10325         tmp_list = bnx2x_prev_path_get_entry(bp);
10326         if (tmp_list) {
10327                 if (tmp_list->aer) {
10328                         DP(NETIF_MSG_HW, "Path %d was marked by AER\n",
10329                            BP_PATH(bp));
10330                 } else {
10331                         rc = true;
10332                         BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
10333                                        BP_PATH(bp));
10334                 }
10335         }
10336
10337         up(&bnx2x_prev_sem);
10338
10339         return rc;
10340 }
10341
10342 bool bnx2x_port_after_undi(struct bnx2x *bp)
10343 {
10344         struct bnx2x_prev_path_list *entry;
10345         bool val;
10346
10347         down(&bnx2x_prev_sem);
10348
10349         entry = bnx2x_prev_path_get_entry(bp);
10350         val = !!(entry && (entry->undi & (1 << BP_PORT(bp))));
10351
10352         up(&bnx2x_prev_sem);
10353
10354         return val;
10355 }
10356
10357 static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi)
10358 {
10359         struct bnx2x_prev_path_list *tmp_list;
10360         int rc;
10361
10362         rc = down_interruptible(&bnx2x_prev_sem);
10363         if (rc) {
10364                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10365                 return rc;
10366         }
10367
10368         /* Check whether the entry for this path already exists */
10369         tmp_list = bnx2x_prev_path_get_entry(bp);
10370         if (tmp_list) {
10371                 if (!tmp_list->aer) {
10372                         BNX2X_ERR("Re-Marking the path.\n");
10373                 } else {
10374                         DP(NETIF_MSG_HW, "Removing AER indication from path %d\n",
10375                            BP_PATH(bp));
10376                         tmp_list->aer = 0;
10377                 }
10378                 up(&bnx2x_prev_sem);
10379                 return 0;
10380         }
10381         up(&bnx2x_prev_sem);
10382
10383         /* Create an entry for this path and add it */
10384         tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL);
10385         if (!tmp_list) {
10386                 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
10387                 return -ENOMEM;
10388         }
10389
10390         tmp_list->bus = bp->pdev->bus->number;
10391         tmp_list->slot = PCI_SLOT(bp->pdev->devfn);
10392         tmp_list->path = BP_PATH(bp);
10393         tmp_list->aer = 0;
10394         tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0;
10395
10396         rc = down_interruptible(&bnx2x_prev_sem);
10397         if (rc) {
10398                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10399                 kfree(tmp_list);
10400         } else {
10401                 DP(NETIF_MSG_HW, "Marked path [%d] - finished previous unload\n",
10402                    BP_PATH(bp));
10403                 list_add(&tmp_list->list, &bnx2x_prev_list);
10404                 up(&bnx2x_prev_sem);
10405         }
10406
10407         return rc;
10408 }
10409
10410 static int bnx2x_do_flr(struct bnx2x *bp)
10411 {
10412         struct pci_dev *dev = bp->pdev;
10413
10414         if (CHIP_IS_E1x(bp)) {
10415                 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n");
10416                 return -EINVAL;
10417         }
10418
10419         /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
10420         if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
10421                 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
10422                           bp->common.bc_ver);
10423                 return -EINVAL;
10424         }
10425
10426         if (!pci_wait_for_pending_transaction(dev))
10427                 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
10428
10429         BNX2X_DEV_INFO("Initiating FLR\n");
10430         bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0);
10431
10432         return 0;
10433 }
10434
10435 static int bnx2x_prev_unload_uncommon(struct bnx2x *bp)
10436 {
10437         int rc;
10438
10439         BNX2X_DEV_INFO("Uncommon unload Flow\n");
10440
10441         /* Test if previous unload process was already finished for this path */
10442         if (bnx2x_prev_is_path_marked(bp))
10443                 return bnx2x_prev_mcp_done(bp);
10444
10445         BNX2X_DEV_INFO("Path is unmarked\n");
10446
10447         /* Cannot proceed with FLR if UNDI is loaded, since FW does not match */
10448         if (bnx2x_prev_is_after_undi(bp))
10449                 goto out;
10450
10451         /* If function has FLR capabilities, and existing FW version matches
10452          * the one required, then FLR will be sufficient to clean any residue
10453          * left by previous driver
10454          */
10455         rc = bnx2x_compare_fw_ver(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION, false);
10456
10457         if (!rc) {
10458                 /* fw version is good */
10459                 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
10460                 rc = bnx2x_do_flr(bp);
10461         }
10462
10463         if (!rc) {
10464                 /* FLR was performed */
10465                 BNX2X_DEV_INFO("FLR successful\n");
10466                 return 0;
10467         }
10468
10469         BNX2X_DEV_INFO("Could not FLR\n");
10470
10471 out:
10472         /* Close the MCP request, return failure*/
10473         rc = bnx2x_prev_mcp_done(bp);
10474         if (!rc)
10475                 rc = BNX2X_PREV_WAIT_NEEDED;
10476
10477         return rc;
10478 }
10479
10480 static int bnx2x_prev_unload_common(struct bnx2x *bp)
10481 {
10482         u32 reset_reg, tmp_reg = 0, rc;
10483         bool prev_undi = false;
10484         struct bnx2x_mac_vals mac_vals;
10485
10486         /* It is possible a previous function received 'common' answer,
10487          * but hasn't loaded yet, therefore creating a scenario of
10488          * multiple functions receiving 'common' on the same path.
10489          */
10490         BNX2X_DEV_INFO("Common unload Flow\n");
10491
10492         memset(&mac_vals, 0, sizeof(mac_vals));
10493
10494         if (bnx2x_prev_is_path_marked(bp))
10495                 return bnx2x_prev_mcp_done(bp);
10496
10497         reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
10498
10499         /* Reset should be performed after BRB is emptied */
10500         if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
10501                 u32 timer_count = 1000;
10502
10503                 /* Close the MAC Rx to prevent BRB from filling up */
10504                 bnx2x_prev_unload_close_mac(bp, &mac_vals);
10505
10506                 /* close LLH filters towards the BRB */
10507                 bnx2x_set_rx_filter(&bp->link_params, 0);
10508
10509                 /* Check if the UNDI driver was previously loaded */
10510                 if (bnx2x_prev_is_after_undi(bp)) {
10511                         prev_undi = true;
10512                         /* clear the UNDI indication */
10513                         REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
10514                         /* clear possible idle check errors */
10515                         REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0);
10516                 }
10517                 if (!CHIP_IS_E1x(bp))
10518                         /* block FW from writing to host */
10519                         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10520
10521                 /* wait until BRB is empty */
10522                 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10523                 while (timer_count) {
10524                         u32 prev_brb = tmp_reg;
10525
10526                         tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10527                         if (!tmp_reg)
10528                                 break;
10529
10530                         BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg);
10531
10532                         /* reset timer as long as BRB actually gets emptied */
10533                         if (prev_brb > tmp_reg)
10534                                 timer_count = 1000;
10535                         else
10536                                 timer_count--;
10537
10538                         /* If UNDI resides in memory, manually increment it */
10539                         if (prev_undi)
10540                                 bnx2x_prev_unload_undi_inc(bp, 1);
10541
10542                         udelay(10);
10543                 }
10544
10545                 if (!timer_count)
10546                         BNX2X_ERR("Failed to empty BRB, hope for the best\n");
10547         }
10548
10549         /* No packets are in the pipeline, path is ready for reset */
10550         bnx2x_reset_common(bp);
10551
10552         if (mac_vals.xmac_addr)
10553                 REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val);
10554         if (mac_vals.umac_addr)
10555                 REG_WR(bp, mac_vals.umac_addr, mac_vals.umac_val);
10556         if (mac_vals.emac_addr)
10557                 REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val);
10558         if (mac_vals.bmac_addr) {
10559                 REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
10560                 REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
10561         }
10562
10563         rc = bnx2x_prev_mark_path(bp, prev_undi);
10564         if (rc) {
10565                 bnx2x_prev_mcp_done(bp);
10566                 return rc;
10567         }
10568
10569         return bnx2x_prev_mcp_done(bp);
10570 }
10571
10572 /* previous driver DMAE transaction may have occurred when pre-boot stage ended
10573  * and boot began, or when kdump kernel was loaded. Either case would invalidate
10574  * the addresses of the transaction, resulting in was-error bit set in the pci
10575  * causing all hw-to-host pcie transactions to timeout. If this happened we want
10576  * to clear the interrupt which detected this from the pglueb and the was done
10577  * bit
10578  */
10579 static void bnx2x_prev_interrupted_dmae(struct bnx2x *bp)
10580 {
10581         if (!CHIP_IS_E1x(bp)) {
10582                 u32 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS);
10583                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
10584                         DP(BNX2X_MSG_SP,
10585                            "'was error' bit was found to be set in pglueb upon startup. Clearing\n");
10586                         REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
10587                                1 << BP_FUNC(bp));
10588                 }
10589         }
10590 }
10591
10592 static int bnx2x_prev_unload(struct bnx2x *bp)
10593 {
10594         int time_counter = 10;
10595         u32 rc, fw, hw_lock_reg, hw_lock_val;
10596         BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
10597
10598         /* clear hw from errors which may have resulted from an interrupted
10599          * dmae transaction.
10600          */
10601         bnx2x_prev_interrupted_dmae(bp);
10602
10603         /* Release previously held locks */
10604         hw_lock_reg = (BP_FUNC(bp) <= 5) ?
10605                       (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) :
10606                       (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8);
10607
10608         hw_lock_val = REG_RD(bp, hw_lock_reg);
10609         if (hw_lock_val) {
10610                 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
10611                         BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
10612                         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
10613                                (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp)));
10614                 }
10615
10616                 BNX2X_DEV_INFO("Release Previously held hw lock\n");
10617                 REG_WR(bp, hw_lock_reg, 0xffffffff);
10618         } else
10619                 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
10620
10621         if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {
10622                 BNX2X_DEV_INFO("Release previously held alr\n");
10623                 bnx2x_release_alr(bp);
10624         }
10625
10626         do {
10627                 int aer = 0;
10628                 /* Lock MCP using an unload request */
10629                 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
10630                 if (!fw) {
10631                         BNX2X_ERR("MCP response failure, aborting\n");
10632                         rc = -EBUSY;
10633                         break;
10634                 }
10635
10636                 rc = down_interruptible(&bnx2x_prev_sem);
10637                 if (rc) {
10638                         BNX2X_ERR("Cannot check for AER; Received %d when tried to take lock\n",
10639                                   rc);
10640                 } else {
10641                         /* If Path is marked by EEH, ignore unload status */
10642                         aer = !!(bnx2x_prev_path_get_entry(bp) &&
10643                                  bnx2x_prev_path_get_entry(bp)->aer);
10644                         up(&bnx2x_prev_sem);
10645                 }
10646
10647                 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON || aer) {
10648                         rc = bnx2x_prev_unload_common(bp);
10649                         break;
10650                 }
10651
10652                 /* non-common reply from MCP might require looping */
10653                 rc = bnx2x_prev_unload_uncommon(bp);
10654                 if (rc != BNX2X_PREV_WAIT_NEEDED)
10655                         break;
10656
10657                 msleep(20);
10658         } while (--time_counter);
10659
10660         if (!time_counter || rc) {
10661                 BNX2X_DEV_INFO("Unloading previous driver did not occur, Possibly due to MF UNDI\n");
10662                 rc = -EPROBE_DEFER;
10663         }
10664
10665         /* Mark function if its port was used to boot from SAN */
10666         if (bnx2x_port_after_undi(bp))
10667                 bp->link_params.feature_config_flags |=
10668                         FEATURE_CONFIG_BOOT_FROM_SAN;
10669
10670         BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc);
10671
10672         return rc;
10673 }
10674
10675 static void bnx2x_get_common_hwinfo(struct bnx2x *bp)
10676 {
10677         u32 val, val2, val3, val4, id, boot_mode;
10678         u16 pmc;
10679
10680         /* Get the chip revision id and number. */
10681         /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
10682         val = REG_RD(bp, MISC_REG_CHIP_NUM);
10683         id = ((val & 0xffff) << 16);
10684         val = REG_RD(bp, MISC_REG_CHIP_REV);
10685         id |= ((val & 0xf) << 12);
10686
10687         /* Metal is read from PCI regs, but we can't access >=0x400 from
10688          * the configuration space (so we need to reg_rd)
10689          */
10690         val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3);
10691         id |= (((val >> 24) & 0xf) << 4);
10692         val = REG_RD(bp, MISC_REG_BOND_ID);
10693         id |= (val & 0xf);
10694         bp->common.chip_id = id;
10695
10696         /* force 57811 according to MISC register */
10697         if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
10698                 if (CHIP_IS_57810(bp))
10699                         bp->common.chip_id = (CHIP_NUM_57811 << 16) |
10700                                 (bp->common.chip_id & 0x0000FFFF);
10701                 else if (CHIP_IS_57810_MF(bp))
10702                         bp->common.chip_id = (CHIP_NUM_57811_MF << 16) |
10703                                 (bp->common.chip_id & 0x0000FFFF);
10704                 bp->common.chip_id |= 0x1;
10705         }
10706
10707         /* Set doorbell size */
10708         bp->db_size = (1 << BNX2X_DB_SHIFT);
10709
10710         if (!CHIP_IS_E1x(bp)) {
10711                 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
10712                 if ((val & 1) == 0)
10713                         val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
10714                 else
10715                         val = (val >> 1) & 1;
10716                 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
10717                                                        "2_PORT_MODE");
10718                 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
10719                                                  CHIP_2_PORT_MODE;
10720
10721                 if (CHIP_MODE_IS_4_PORT(bp))
10722                         bp->pfid = (bp->pf_num >> 1);   /* 0..3 */
10723                 else
10724                         bp->pfid = (bp->pf_num & 0x6);  /* 0, 2, 4, 6 */
10725         } else {
10726                 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
10727                 bp->pfid = bp->pf_num;                  /* 0..7 */
10728         }
10729
10730         BNX2X_DEV_INFO("pf_id: %x", bp->pfid);
10731
10732         bp->link_params.chip_id = bp->common.chip_id;
10733         BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
10734
10735         val = (REG_RD(bp, 0x2874) & 0x55);
10736         if ((bp->common.chip_id & 0x1) ||
10737             (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
10738                 bp->flags |= ONE_PORT_FLAG;
10739                 BNX2X_DEV_INFO("single port device\n");
10740         }
10741
10742         val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
10743         bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
10744                                  (val & MCPR_NVM_CFG4_FLASH_SIZE));
10745         BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
10746                        bp->common.flash_size, bp->common.flash_size);
10747
10748         bnx2x_init_shmem(bp);
10749
10750         bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
10751                                         MISC_REG_GENERIC_CR_1 :
10752                                         MISC_REG_GENERIC_CR_0));
10753
10754         bp->link_params.shmem_base = bp->common.shmem_base;
10755         bp->link_params.shmem2_base = bp->common.shmem2_base;
10756         if (SHMEM2_RD(bp, size) >
10757             (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
10758                 bp->link_params.lfa_base =
10759                 REG_RD(bp, bp->common.shmem2_base +
10760                        (u32)offsetof(struct shmem2_region,
10761                                      lfa_host_addr[BP_PORT(bp)]));
10762         else
10763                 bp->link_params.lfa_base = 0;
10764         BNX2X_DEV_INFO("shmem offset 0x%x  shmem2 offset 0x%x\n",
10765                        bp->common.shmem_base, bp->common.shmem2_base);
10766
10767         if (!bp->common.shmem_base) {
10768                 BNX2X_DEV_INFO("MCP not active\n");
10769                 bp->flags |= NO_MCP_FLAG;
10770                 return;
10771         }
10772
10773         bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
10774         BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
10775
10776         bp->link_params.hw_led_mode = ((bp->common.hw_config &
10777                                         SHARED_HW_CFG_LED_MODE_MASK) >>
10778                                        SHARED_HW_CFG_LED_MODE_SHIFT);
10779
10780         bp->link_params.feature_config_flags = 0;
10781         val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
10782         if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
10783                 bp->link_params.feature_config_flags |=
10784                                 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10785         else
10786                 bp->link_params.feature_config_flags &=
10787                                 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10788
10789         val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
10790         bp->common.bc_ver = val;
10791         BNX2X_DEV_INFO("bc_ver %X\n", val);
10792         if (val < BNX2X_BC_VER) {
10793                 /* for now only warn
10794                  * later we might need to enforce this */
10795                 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
10796                           BNX2X_BC_VER, val);
10797         }
10798         bp->link_params.feature_config_flags |=
10799                                 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
10800                                 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
10801
10802         bp->link_params.feature_config_flags |=
10803                 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
10804                 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
10805         bp->link_params.feature_config_flags |=
10806                 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
10807                 FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
10808         bp->link_params.feature_config_flags |=
10809                 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
10810                 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
10811
10812         bp->link_params.feature_config_flags |=
10813                 (val >= REQ_BC_VER_4_MT_SUPPORTED) ?
10814                 FEATURE_CONFIG_MT_SUPPORT : 0;
10815
10816         bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
10817                         BC_SUPPORTS_PFC_STATS : 0;
10818
10819         bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ?
10820                         BC_SUPPORTS_FCOE_FEATURES : 0;
10821
10822         bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ?
10823                         BC_SUPPORTS_DCBX_MSG_NON_PMF : 0;
10824
10825         bp->flags |= (val >= REQ_BC_VER_4_RMMOD_CMD) ?
10826                         BC_SUPPORTS_RMMOD_CMD : 0;
10827
10828         boot_mode = SHMEM_RD(bp,
10829                         dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
10830                         PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK;
10831         switch (boot_mode) {
10832         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE:
10833                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
10834                 break;
10835         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB:
10836                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
10837                 break;
10838         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT:
10839                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
10840                 break;
10841         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE:
10842                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
10843                 break;
10844         }
10845
10846         pci_read_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_PMC, &pmc);
10847         bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
10848
10849         BNX2X_DEV_INFO("%sWoL capable\n",
10850                        (bp->flags & NO_WOL_FLAG) ? "not " : "");
10851
10852         val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
10853         val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
10854         val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
10855         val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
10856
10857         dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
10858                  val, val2, val3, val4);
10859 }
10860
10861 #define IGU_FID(val)    GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
10862 #define IGU_VEC(val)    GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
10863
10864 static int bnx2x_get_igu_cam_info(struct bnx2x *bp)
10865 {
10866         int pfid = BP_FUNC(bp);
10867         int igu_sb_id;
10868         u32 val;
10869         u8 fid, igu_sb_cnt = 0;
10870
10871         bp->igu_base_sb = 0xff;
10872         if (CHIP_INT_MODE_IS_BC(bp)) {
10873                 int vn = BP_VN(bp);
10874                 igu_sb_cnt = bp->igu_sb_cnt;
10875                 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
10876                         FP_SB_MAX_E1x;
10877
10878                 bp->igu_dsb_id =  E1HVN_MAX * FP_SB_MAX_E1x +
10879                         (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
10880
10881                 return 0;
10882         }
10883
10884         /* IGU in normal mode - read CAM */
10885         for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
10886              igu_sb_id++) {
10887                 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
10888                 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
10889                         continue;
10890                 fid = IGU_FID(val);
10891                 if ((fid & IGU_FID_ENCODE_IS_PF)) {
10892                         if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
10893                                 continue;
10894                         if (IGU_VEC(val) == 0)
10895                                 /* default status block */
10896                                 bp->igu_dsb_id = igu_sb_id;
10897                         else {
10898                                 if (bp->igu_base_sb == 0xff)
10899                                         bp->igu_base_sb = igu_sb_id;
10900                                 igu_sb_cnt++;
10901                         }
10902                 }
10903         }
10904
10905 #ifdef CONFIG_PCI_MSI
10906         /* Due to new PF resource allocation by MFW T7.4 and above, it's
10907          * optional that number of CAM entries will not be equal to the value
10908          * advertised in PCI.
10909          * Driver should use the minimal value of both as the actual status
10910          * block count
10911          */
10912         bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt);
10913 #endif
10914
10915         if (igu_sb_cnt == 0) {
10916                 BNX2X_ERR("CAM configuration error\n");
10917                 return -EINVAL;
10918         }
10919
10920         return 0;
10921 }
10922
10923 static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
10924 {
10925         int cfg_size = 0, idx, port = BP_PORT(bp);
10926
10927         /* Aggregation of supported attributes of all external phys */
10928         bp->port.supported[0] = 0;
10929         bp->port.supported[1] = 0;
10930         switch (bp->link_params.num_phys) {
10931         case 1:
10932                 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
10933                 cfg_size = 1;
10934                 break;
10935         case 2:
10936                 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
10937                 cfg_size = 1;
10938                 break;
10939         case 3:
10940                 if (bp->link_params.multi_phy_config &
10941                     PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
10942                         bp->port.supported[1] =
10943                                 bp->link_params.phy[EXT_PHY1].supported;
10944                         bp->port.supported[0] =
10945                                 bp->link_params.phy[EXT_PHY2].supported;
10946                 } else {
10947                         bp->port.supported[0] =
10948                                 bp->link_params.phy[EXT_PHY1].supported;
10949                         bp->port.supported[1] =
10950                                 bp->link_params.phy[EXT_PHY2].supported;
10951                 }
10952                 cfg_size = 2;
10953                 break;
10954         }
10955
10956         if (!(bp->port.supported[0] || bp->port.supported[1])) {
10957                 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
10958                            SHMEM_RD(bp,
10959                            dev_info.port_hw_config[port].external_phy_config),
10960                            SHMEM_RD(bp,
10961                            dev_info.port_hw_config[port].external_phy_config2));
10962                         return;
10963         }
10964
10965         if (CHIP_IS_E3(bp))
10966                 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
10967         else {
10968                 switch (switch_cfg) {
10969                 case SWITCH_CFG_1G:
10970                         bp->port.phy_addr = REG_RD(
10971                                 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
10972                         break;
10973                 case SWITCH_CFG_10G:
10974                         bp->port.phy_addr = REG_RD(
10975                                 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
10976                         break;
10977                 default:
10978                         BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
10979                                   bp->port.link_config[0]);
10980                         return;
10981                 }
10982         }
10983         BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
10984         /* mask what we support according to speed_cap_mask per configuration */
10985         for (idx = 0; idx < cfg_size; idx++) {
10986                 if (!(bp->link_params.speed_cap_mask[idx] &
10987                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
10988                         bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
10989
10990                 if (!(bp->link_params.speed_cap_mask[idx] &
10991                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
10992                         bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
10993
10994                 if (!(bp->link_params.speed_cap_mask[idx] &
10995                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
10996                         bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
10997
10998                 if (!(bp->link_params.speed_cap_mask[idx] &
10999                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
11000                         bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
11001
11002                 if (!(bp->link_params.speed_cap_mask[idx] &
11003                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
11004                         bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
11005                                                      SUPPORTED_1000baseT_Full);
11006
11007                 if (!(bp->link_params.speed_cap_mask[idx] &
11008                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
11009                         bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
11010
11011                 if (!(bp->link_params.speed_cap_mask[idx] &
11012                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
11013                         bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
11014
11015                 if (!(bp->link_params.speed_cap_mask[idx] &
11016                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))
11017                         bp->port.supported[idx] &= ~SUPPORTED_20000baseKR2_Full;
11018         }
11019
11020         BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
11021                        bp->port.supported[1]);
11022 }
11023
11024 static void bnx2x_link_settings_requested(struct bnx2x *bp)
11025 {
11026         u32 link_config, idx, cfg_size = 0;
11027         bp->port.advertising[0] = 0;
11028         bp->port.advertising[1] = 0;
11029         switch (bp->link_params.num_phys) {
11030         case 1:
11031         case 2:
11032                 cfg_size = 1;
11033                 break;
11034         case 3:
11035                 cfg_size = 2;
11036                 break;
11037         }
11038         for (idx = 0; idx < cfg_size; idx++) {
11039                 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
11040                 link_config = bp->port.link_config[idx];
11041                 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
11042                 case PORT_FEATURE_LINK_SPEED_AUTO:
11043                         if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
11044                                 bp->link_params.req_line_speed[idx] =
11045                                         SPEED_AUTO_NEG;
11046                                 bp->port.advertising[idx] |=
11047                                         bp->port.supported[idx];
11048                                 if (bp->link_params.phy[EXT_PHY1].type ==
11049                                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
11050                                         bp->port.advertising[idx] |=
11051                                         (SUPPORTED_100baseT_Half |
11052                                          SUPPORTED_100baseT_Full);
11053                         } else {
11054                                 /* force 10G, no AN */
11055                                 bp->link_params.req_line_speed[idx] =
11056                                         SPEED_10000;
11057                                 bp->port.advertising[idx] |=
11058                                         (ADVERTISED_10000baseT_Full |
11059                                          ADVERTISED_FIBRE);
11060                                 continue;
11061                         }
11062                         break;
11063
11064                 case PORT_FEATURE_LINK_SPEED_10M_FULL:
11065                         if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
11066                                 bp->link_params.req_line_speed[idx] =
11067                                         SPEED_10;
11068                                 bp->port.advertising[idx] |=
11069                                         (ADVERTISED_10baseT_Full |
11070                                          ADVERTISED_TP);
11071                         } else {
11072                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11073                                             link_config,
11074                                     bp->link_params.speed_cap_mask[idx]);
11075                                 return;
11076                         }
11077                         break;
11078
11079                 case PORT_FEATURE_LINK_SPEED_10M_HALF:
11080                         if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
11081                                 bp->link_params.req_line_speed[idx] =
11082                                         SPEED_10;
11083                                 bp->link_params.req_duplex[idx] =
11084                                         DUPLEX_HALF;
11085                                 bp->port.advertising[idx] |=
11086                                         (ADVERTISED_10baseT_Half |
11087                                          ADVERTISED_TP);
11088                         } else {
11089                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11090                                             link_config,
11091                                           bp->link_params.speed_cap_mask[idx]);
11092                                 return;
11093                         }
11094                         break;
11095
11096                 case PORT_FEATURE_LINK_SPEED_100M_FULL:
11097                         if (bp->port.supported[idx] &
11098                             SUPPORTED_100baseT_Full) {
11099                                 bp->link_params.req_line_speed[idx] =
11100                                         SPEED_100;
11101                                 bp->port.advertising[idx] |=
11102                                         (ADVERTISED_100baseT_Full |
11103                                          ADVERTISED_TP);
11104                         } else {
11105                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11106                                             link_config,
11107                                           bp->link_params.speed_cap_mask[idx]);
11108                                 return;
11109                         }
11110                         break;
11111
11112                 case PORT_FEATURE_LINK_SPEED_100M_HALF:
11113                         if (bp->port.supported[idx] &
11114                             SUPPORTED_100baseT_Half) {
11115                                 bp->link_params.req_line_speed[idx] =
11116                                                                 SPEED_100;
11117                                 bp->link_params.req_duplex[idx] =
11118                                                                 DUPLEX_HALF;
11119                                 bp->port.advertising[idx] |=
11120                                         (ADVERTISED_100baseT_Half |
11121                                          ADVERTISED_TP);
11122                         } else {
11123                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11124                                     link_config,
11125                                     bp->link_params.speed_cap_mask[idx]);
11126                                 return;
11127                         }
11128                         break;
11129
11130                 case PORT_FEATURE_LINK_SPEED_1G:
11131                         if (bp->port.supported[idx] &
11132                             SUPPORTED_1000baseT_Full) {
11133                                 bp->link_params.req_line_speed[idx] =
11134                                         SPEED_1000;
11135                                 bp->port.advertising[idx] |=
11136                                         (ADVERTISED_1000baseT_Full |
11137                                          ADVERTISED_TP);
11138                         } else {
11139                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11140                                     link_config,
11141                                     bp->link_params.speed_cap_mask[idx]);
11142                                 return;
11143                         }
11144                         break;
11145
11146                 case PORT_FEATURE_LINK_SPEED_2_5G:
11147                         if (bp->port.supported[idx] &
11148                             SUPPORTED_2500baseX_Full) {
11149                                 bp->link_params.req_line_speed[idx] =
11150                                         SPEED_2500;
11151                                 bp->port.advertising[idx] |=
11152                                         (ADVERTISED_2500baseX_Full |
11153                                                 ADVERTISED_TP);
11154                         } else {
11155                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11156                                     link_config,
11157                                     bp->link_params.speed_cap_mask[idx]);
11158                                 return;
11159                         }
11160                         break;
11161
11162                 case PORT_FEATURE_LINK_SPEED_10G_CX4:
11163                         if (bp->port.supported[idx] &
11164                             SUPPORTED_10000baseT_Full) {
11165                                 bp->link_params.req_line_speed[idx] =
11166                                         SPEED_10000;
11167                                 bp->port.advertising[idx] |=
11168                                         (ADVERTISED_10000baseT_Full |
11169                                                 ADVERTISED_FIBRE);
11170                         } else {
11171                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11172                                     link_config,
11173                                     bp->link_params.speed_cap_mask[idx]);
11174                                 return;
11175                         }
11176                         break;
11177                 case PORT_FEATURE_LINK_SPEED_20G:
11178                         bp->link_params.req_line_speed[idx] = SPEED_20000;
11179
11180                         break;
11181                 default:
11182                         BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
11183                                   link_config);
11184                                 bp->link_params.req_line_speed[idx] =
11185                                                         SPEED_AUTO_NEG;
11186                                 bp->port.advertising[idx] =
11187                                                 bp->port.supported[idx];
11188                         break;
11189                 }
11190
11191                 bp->link_params.req_flow_ctrl[idx] = (link_config &
11192                                          PORT_FEATURE_FLOW_CONTROL_MASK);
11193                 if (bp->link_params.req_flow_ctrl[idx] ==
11194                     BNX2X_FLOW_CTRL_AUTO) {
11195                         if (!(bp->port.supported[idx] & SUPPORTED_Autoneg))
11196                                 bp->link_params.req_flow_ctrl[idx] =
11197                                                         BNX2X_FLOW_CTRL_NONE;
11198                         else
11199                                 bnx2x_set_requested_fc(bp);
11200                 }
11201
11202                 BNX2X_DEV_INFO("req_line_speed %d  req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
11203                                bp->link_params.req_line_speed[idx],
11204                                bp->link_params.req_duplex[idx],
11205                                bp->link_params.req_flow_ctrl[idx],
11206                                bp->port.advertising[idx]);
11207         }
11208 }
11209
11210 static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
11211 {
11212         __be16 mac_hi_be = cpu_to_be16(mac_hi);
11213         __be32 mac_lo_be = cpu_to_be32(mac_lo);
11214         memcpy(mac_buf, &mac_hi_be, sizeof(mac_hi_be));
11215         memcpy(mac_buf + sizeof(mac_hi_be), &mac_lo_be, sizeof(mac_lo_be));
11216 }
11217
11218 static void bnx2x_get_port_hwinfo(struct bnx2x *bp)
11219 {
11220         int port = BP_PORT(bp);
11221         u32 config;
11222         u32 ext_phy_type, ext_phy_config, eee_mode;
11223
11224         bp->link_params.bp = bp;
11225         bp->link_params.port = port;
11226
11227         bp->link_params.lane_config =
11228                 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
11229
11230         bp->link_params.speed_cap_mask[0] =
11231                 SHMEM_RD(bp,
11232                          dev_info.port_hw_config[port].speed_capability_mask) &
11233                 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
11234         bp->link_params.speed_cap_mask[1] =
11235                 SHMEM_RD(bp,
11236                          dev_info.port_hw_config[port].speed_capability_mask2) &
11237                 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
11238         bp->port.link_config[0] =
11239                 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
11240
11241         bp->port.link_config[1] =
11242                 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
11243
11244         bp->link_params.multi_phy_config =
11245                 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
11246         /* If the device is capable of WoL, set the default state according
11247          * to the HW
11248          */
11249         config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
11250         bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
11251                    (config & PORT_FEATURE_WOL_ENABLED));
11252
11253         if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
11254             PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE && !IS_MF(bp))
11255                 bp->flags |= NO_ISCSI_FLAG;
11256         if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
11257             PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI && !(IS_MF(bp)))
11258                 bp->flags |= NO_FCOE_FLAG;
11259
11260         BNX2X_DEV_INFO("lane_config 0x%08x  speed_cap_mask0 0x%08x  link_config0 0x%08x\n",
11261                        bp->link_params.lane_config,
11262                        bp->link_params.speed_cap_mask[0],
11263                        bp->port.link_config[0]);
11264
11265         bp->link_params.switch_cfg = (bp->port.link_config[0] &
11266                                       PORT_FEATURE_CONNECTED_SWITCH_MASK);
11267         bnx2x_phy_probe(&bp->link_params);
11268         bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
11269
11270         bnx2x_link_settings_requested(bp);
11271
11272         /*
11273          * If connected directly, work with the internal PHY, otherwise, work
11274          * with the external PHY
11275          */
11276         ext_phy_config =
11277                 SHMEM_RD(bp,
11278                          dev_info.port_hw_config[port].external_phy_config);
11279         ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
11280         if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
11281                 bp->mdio.prtad = bp->port.phy_addr;
11282
11283         else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
11284                  (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
11285                 bp->mdio.prtad =
11286                         XGXS_EXT_PHY_ADDR(ext_phy_config);
11287
11288         /* Configure link feature according to nvram value */
11289         eee_mode = (((SHMEM_RD(bp, dev_info.
11290                       port_feature_config[port].eee_power_mode)) &
11291                      PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
11292                     PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
11293         if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
11294                 bp->link_params.eee_mode = EEE_MODE_ADV_LPI |
11295                                            EEE_MODE_ENABLE_LPI |
11296                                            EEE_MODE_OUTPUT_TIME;
11297         } else {
11298                 bp->link_params.eee_mode = 0;
11299         }
11300 }
11301
11302 void bnx2x_get_iscsi_info(struct bnx2x *bp)
11303 {
11304         u32 no_flags = NO_ISCSI_FLAG;
11305         int port = BP_PORT(bp);
11306         u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
11307                                 drv_lic_key[port].max_iscsi_conn);
11308
11309         if (!CNIC_SUPPORT(bp)) {
11310                 bp->flags |= no_flags;
11311                 return;
11312         }
11313
11314         /* Get the number of maximum allowed iSCSI connections */
11315         bp->cnic_eth_dev.max_iscsi_conn =
11316                 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
11317                 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
11318
11319         BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
11320                        bp->cnic_eth_dev.max_iscsi_conn);
11321
11322         /*
11323          * If maximum allowed number of connections is zero -
11324          * disable the feature.
11325          */
11326         if (!bp->cnic_eth_dev.max_iscsi_conn)
11327                 bp->flags |= no_flags;
11328 }
11329
11330 static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func)
11331 {
11332         /* Port info */
11333         bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11334                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper);
11335         bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11336                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower);
11337
11338         /* Node info */
11339         bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11340                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper);
11341         bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11342                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower);
11343 }
11344
11345 static int bnx2x_shared_fcoe_funcs(struct bnx2x *bp)
11346 {
11347         u8 count = 0;
11348
11349         if (IS_MF(bp)) {
11350                 u8 fid;
11351
11352                 /* iterate over absolute function ids for this path: */
11353                 for (fid = BP_PATH(bp); fid < E2_FUNC_MAX * 2; fid += 2) {
11354                         if (IS_MF_SD(bp)) {
11355                                 u32 cfg = MF_CFG_RD(bp,
11356                                                     func_mf_config[fid].config);
11357
11358                                 if (!(cfg & FUNC_MF_CFG_FUNC_HIDE) &&
11359                                     ((cfg & FUNC_MF_CFG_PROTOCOL_MASK) ==
11360                                             FUNC_MF_CFG_PROTOCOL_FCOE))
11361                                         count++;
11362                         } else {
11363                                 u32 cfg = MF_CFG_RD(bp,
11364                                                     func_ext_config[fid].
11365                                                                       func_cfg);
11366
11367                                 if ((cfg & MACP_FUNC_CFG_FLAGS_ENABLED) &&
11368                                     (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD))
11369                                         count++;
11370                         }
11371                 }
11372         } else { /* SF */
11373                 int port, port_cnt = CHIP_MODE_IS_4_PORT(bp) ? 2 : 1;
11374
11375                 for (port = 0; port < port_cnt; port++) {
11376                         u32 lic = SHMEM_RD(bp,
11377                                            drv_lic_key[port].max_fcoe_conn) ^
11378                                   FW_ENCODE_32BIT_PATTERN;
11379                         if (lic)
11380                                 count++;
11381                 }
11382         }
11383
11384         return count;
11385 }
11386
11387 static void bnx2x_get_fcoe_info(struct bnx2x *bp)
11388 {
11389         int port = BP_PORT(bp);
11390         int func = BP_ABS_FUNC(bp);
11391         u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
11392                                 drv_lic_key[port].max_fcoe_conn);
11393         u8 num_fcoe_func = bnx2x_shared_fcoe_funcs(bp);
11394
11395         if (!CNIC_SUPPORT(bp)) {
11396                 bp->flags |= NO_FCOE_FLAG;
11397                 return;
11398         }
11399
11400         /* Get the number of maximum allowed FCoE connections */
11401         bp->cnic_eth_dev.max_fcoe_conn =
11402                 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
11403                 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
11404
11405         /* Calculate the number of maximum allowed FCoE tasks */
11406         bp->cnic_eth_dev.max_fcoe_exchanges = MAX_NUM_FCOE_TASKS_PER_ENGINE;
11407
11408         /* check if FCoE resources must be shared between different functions */
11409         if (num_fcoe_func)
11410                 bp->cnic_eth_dev.max_fcoe_exchanges /= num_fcoe_func;
11411
11412         /* Read the WWN: */
11413         if (!IS_MF(bp)) {
11414                 /* Port info */
11415                 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11416                         SHMEM_RD(bp,
11417                                  dev_info.port_hw_config[port].
11418                                  fcoe_wwn_port_name_upper);
11419                 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11420                         SHMEM_RD(bp,
11421                                  dev_info.port_hw_config[port].
11422                                  fcoe_wwn_port_name_lower);
11423
11424                 /* Node info */
11425                 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11426                         SHMEM_RD(bp,
11427                                  dev_info.port_hw_config[port].
11428                                  fcoe_wwn_node_name_upper);
11429                 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11430                         SHMEM_RD(bp,
11431                                  dev_info.port_hw_config[port].
11432                                  fcoe_wwn_node_name_lower);
11433         } else if (!IS_MF_SD(bp)) {
11434                 /* Read the WWN info only if the FCoE feature is enabled for
11435                  * this function.
11436                  */
11437                 if (BNX2X_HAS_MF_EXT_PROTOCOL_FCOE(bp))
11438                         bnx2x_get_ext_wwn_info(bp, func);
11439         } else {
11440                 if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp))
11441                         bnx2x_get_ext_wwn_info(bp, func);
11442         }
11443
11444         BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
11445
11446         /*
11447          * If maximum allowed number of connections is zero -
11448          * disable the feature.
11449          */
11450         if (!bp->cnic_eth_dev.max_fcoe_conn)
11451                 bp->flags |= NO_FCOE_FLAG;
11452 }
11453
11454 static void bnx2x_get_cnic_info(struct bnx2x *bp)
11455 {
11456         /*
11457          * iSCSI may be dynamically disabled but reading
11458          * info here we will decrease memory usage by driver
11459          * if the feature is disabled for good
11460          */
11461         bnx2x_get_iscsi_info(bp);
11462         bnx2x_get_fcoe_info(bp);
11463 }
11464
11465 static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp)
11466 {
11467         u32 val, val2;
11468         int func = BP_ABS_FUNC(bp);
11469         int port = BP_PORT(bp);
11470         u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
11471         u8 *fip_mac = bp->fip_mac;
11472
11473         if (IS_MF(bp)) {
11474                 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
11475                  * FCoE MAC then the appropriate feature should be disabled.
11476                  * In non SD mode features configuration comes from struct
11477                  * func_ext_config.
11478                  */
11479                 if (!IS_MF_SD(bp)) {
11480                         u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
11481                         if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
11482                                 val2 = MF_CFG_RD(bp, func_ext_config[func].
11483                                                  iscsi_mac_addr_upper);
11484                                 val = MF_CFG_RD(bp, func_ext_config[func].
11485                                                 iscsi_mac_addr_lower);
11486                                 bnx2x_set_mac_buf(iscsi_mac, val, val2);
11487                                 BNX2X_DEV_INFO
11488                                         ("Read iSCSI MAC: %pM\n", iscsi_mac);
11489                         } else {
11490                                 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
11491                         }
11492
11493                         if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
11494                                 val2 = MF_CFG_RD(bp, func_ext_config[func].
11495                                                  fcoe_mac_addr_upper);
11496                                 val = MF_CFG_RD(bp, func_ext_config[func].
11497                                                 fcoe_mac_addr_lower);
11498                                 bnx2x_set_mac_buf(fip_mac, val, val2);
11499                                 BNX2X_DEV_INFO
11500                                         ("Read FCoE L2 MAC: %pM\n", fip_mac);
11501                         } else {
11502                                 bp->flags |= NO_FCOE_FLAG;
11503                         }
11504
11505                         bp->mf_ext_config = cfg;
11506
11507                 } else { /* SD MODE */
11508                         if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) {
11509                                 /* use primary mac as iscsi mac */
11510                                 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN);
11511
11512                                 BNX2X_DEV_INFO("SD ISCSI MODE\n");
11513                                 BNX2X_DEV_INFO
11514                                         ("Read iSCSI MAC: %pM\n", iscsi_mac);
11515                         } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) {
11516                                 /* use primary mac as fip mac */
11517                                 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
11518                                 BNX2X_DEV_INFO("SD FCoE MODE\n");
11519                                 BNX2X_DEV_INFO
11520                                         ("Read FIP MAC: %pM\n", fip_mac);
11521                         }
11522                 }
11523
11524                 /* If this is a storage-only interface, use SAN mac as
11525                  * primary MAC. Notice that for SD this is already the case,
11526                  * as the SAN mac was copied from the primary MAC.
11527                  */
11528                 if (IS_MF_FCOE_AFEX(bp))
11529                         memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN);
11530         } else {
11531                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
11532                                 iscsi_mac_upper);
11533                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
11534                                iscsi_mac_lower);
11535                 bnx2x_set_mac_buf(iscsi_mac, val, val2);
11536
11537                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
11538                                 fcoe_fip_mac_upper);
11539                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
11540                                fcoe_fip_mac_lower);
11541                 bnx2x_set_mac_buf(fip_mac, val, val2);
11542         }
11543
11544         /* Disable iSCSI OOO if MAC configuration is invalid. */
11545         if (!is_valid_ether_addr(iscsi_mac)) {
11546                 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
11547                 memset(iscsi_mac, 0, ETH_ALEN);
11548         }
11549
11550         /* Disable FCoE if MAC configuration is invalid. */
11551         if (!is_valid_ether_addr(fip_mac)) {
11552                 bp->flags |= NO_FCOE_FLAG;
11553                 memset(bp->fip_mac, 0, ETH_ALEN);
11554         }
11555 }
11556
11557 static void bnx2x_get_mac_hwinfo(struct bnx2x *bp)
11558 {
11559         u32 val, val2;
11560         int func = BP_ABS_FUNC(bp);
11561         int port = BP_PORT(bp);
11562
11563         /* Zero primary MAC configuration */
11564         memset(bp->dev->dev_addr, 0, ETH_ALEN);
11565
11566         if (BP_NOMCP(bp)) {
11567                 BNX2X_ERROR("warning: random MAC workaround active\n");
11568                 eth_hw_addr_random(bp->dev);
11569         } else if (IS_MF(bp)) {
11570                 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
11571                 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
11572                 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
11573                     (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
11574                         bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11575
11576                 if (CNIC_SUPPORT(bp))
11577                         bnx2x_get_cnic_mac_hwinfo(bp);
11578         } else {
11579                 /* in SF read MACs from port configuration */
11580                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11581                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11582                 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11583
11584                 if (CNIC_SUPPORT(bp))
11585                         bnx2x_get_cnic_mac_hwinfo(bp);
11586         }
11587
11588         if (!BP_NOMCP(bp)) {
11589                 /* Read physical port identifier from shmem */
11590                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11591                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11592                 bnx2x_set_mac_buf(bp->phys_port_id, val, val2);
11593                 bp->flags |= HAS_PHYS_PORT_ID;
11594         }
11595
11596         memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
11597
11598         if (!is_valid_ether_addr(bp->dev->dev_addr))
11599                 dev_err(&bp->pdev->dev,
11600                         "bad Ethernet MAC address configuration: %pM\n"
11601                         "change it manually before bringing up the appropriate network interface\n",
11602                         bp->dev->dev_addr);
11603 }
11604
11605 static bool bnx2x_get_dropless_info(struct bnx2x *bp)
11606 {
11607         int tmp;
11608         u32 cfg;
11609
11610         if (IS_VF(bp))
11611                 return 0;
11612
11613         if (IS_MF(bp) && !CHIP_IS_E1x(bp)) {
11614                 /* Take function: tmp = func */
11615                 tmp = BP_ABS_FUNC(bp);
11616                 cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg);
11617                 cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING);
11618         } else {
11619                 /* Take port: tmp = port */
11620                 tmp = BP_PORT(bp);
11621                 cfg = SHMEM_RD(bp,
11622                                dev_info.port_hw_config[tmp].generic_features);
11623                 cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED);
11624         }
11625         return cfg;
11626 }
11627
11628 static void validate_set_si_mode(struct bnx2x *bp)
11629 {
11630         u8 func = BP_ABS_FUNC(bp);
11631         u32 val;
11632
11633         val = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
11634
11635         /* check for legal mac (upper bytes) */
11636         if (val != 0xffff) {
11637                 bp->mf_mode = MULTI_FUNCTION_SI;
11638                 bp->mf_config[BP_VN(bp)] =
11639                         MF_CFG_RD(bp, func_mf_config[func].config);
11640         } else
11641                 BNX2X_DEV_INFO("illegal MAC address for SI\n");
11642 }
11643
11644 static int bnx2x_get_hwinfo(struct bnx2x *bp)
11645 {
11646         int /*abs*/func = BP_ABS_FUNC(bp);
11647         int vn;
11648         u32 val = 0, val2 = 0;
11649         int rc = 0;
11650
11651         bnx2x_get_common_hwinfo(bp);
11652
11653         /*
11654          * initialize IGU parameters
11655          */
11656         if (CHIP_IS_E1x(bp)) {
11657                 bp->common.int_block = INT_BLOCK_HC;
11658
11659                 bp->igu_dsb_id = DEF_SB_IGU_ID;
11660                 bp->igu_base_sb = 0;
11661         } else {
11662                 bp->common.int_block = INT_BLOCK_IGU;
11663
11664                 /* do not allow device reset during IGU info processing */
11665                 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11666
11667                 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
11668
11669                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11670                         int tout = 5000;
11671
11672                         BNX2X_DEV_INFO("FORCING Normal Mode\n");
11673
11674                         val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
11675                         REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
11676                         REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
11677
11678                         while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11679                                 tout--;
11680                                 usleep_range(1000, 2000);
11681                         }
11682
11683                         if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11684                                 dev_err(&bp->pdev->dev,
11685                                         "FORCING Normal Mode failed!!!\n");
11686                                 bnx2x_release_hw_lock(bp,
11687                                                       HW_LOCK_RESOURCE_RESET);
11688                                 return -EPERM;
11689                         }
11690                 }
11691
11692                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11693                         BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
11694                         bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
11695                 } else
11696                         BNX2X_DEV_INFO("IGU Normal Mode\n");
11697
11698                 rc = bnx2x_get_igu_cam_info(bp);
11699                 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11700                 if (rc)
11701                         return rc;
11702         }
11703
11704         /*
11705          * set base FW non-default (fast path) status block id, this value is
11706          * used to initialize the fw_sb_id saved on the fp/queue structure to
11707          * determine the id used by the FW.
11708          */
11709         if (CHIP_IS_E1x(bp))
11710                 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
11711         else /*
11712               * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
11713               * the same queue are indicated on the same IGU SB). So we prefer
11714               * FW and IGU SBs to be the same value.
11715               */
11716                 bp->base_fw_ndsb = bp->igu_base_sb;
11717
11718         BNX2X_DEV_INFO("igu_dsb_id %d  igu_base_sb %d  igu_sb_cnt %d\n"
11719                        "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
11720                        bp->igu_sb_cnt, bp->base_fw_ndsb);
11721
11722         /*
11723          * Initialize MF configuration
11724          */
11725
11726         bp->mf_ov = 0;
11727         bp->mf_mode = 0;
11728         bp->mf_sub_mode = 0;
11729         vn = BP_VN(bp);
11730
11731         if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
11732                 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
11733                                bp->common.shmem2_base, SHMEM2_RD(bp, size),
11734                               (u32)offsetof(struct shmem2_region, mf_cfg_addr));
11735
11736                 if (SHMEM2_HAS(bp, mf_cfg_addr))
11737                         bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
11738                 else
11739                         bp->common.mf_cfg_base = bp->common.shmem_base +
11740                                 offsetof(struct shmem_region, func_mb) +
11741                                 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
11742                 /*
11743                  * get mf configuration:
11744                  * 1. Existence of MF configuration
11745                  * 2. MAC address must be legal (check only upper bytes)
11746                  *    for  Switch-Independent mode;
11747                  *    OVLAN must be legal for Switch-Dependent mode
11748                  * 3. SF_MODE configures specific MF mode
11749                  */
11750                 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11751                         /* get mf configuration */
11752                         val = SHMEM_RD(bp,
11753                                        dev_info.shared_feature_config.config);
11754                         val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
11755
11756                         switch (val) {
11757                         case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
11758                                 validate_set_si_mode(bp);
11759                                 break;
11760                         case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
11761                                 if ((!CHIP_IS_E1x(bp)) &&
11762                                     (MF_CFG_RD(bp, func_mf_config[func].
11763                                                mac_upper) != 0xffff) &&
11764                                     (SHMEM2_HAS(bp,
11765                                                 afex_driver_support))) {
11766                                         bp->mf_mode = MULTI_FUNCTION_AFEX;
11767                                         bp->mf_config[vn] = MF_CFG_RD(bp,
11768                                                 func_mf_config[func].config);
11769                                 } else {
11770                                         BNX2X_DEV_INFO("can not configure afex mode\n");
11771                                 }
11772                                 break;
11773                         case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
11774                                 /* get OV configuration */
11775                                 val = MF_CFG_RD(bp,
11776                                         func_mf_config[FUNC_0].e1hov_tag);
11777                                 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
11778
11779                                 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11780                                         bp->mf_mode = MULTI_FUNCTION_SD;
11781                                         bp->mf_config[vn] = MF_CFG_RD(bp,
11782                                                 func_mf_config[func].config);
11783                                 } else
11784                                         BNX2X_DEV_INFO("illegal OV for SD\n");
11785                                 break;
11786                         case SHARED_FEAT_CFG_FORCE_SF_MODE_UFP_MODE:
11787                                 bp->mf_mode = MULTI_FUNCTION_SD;
11788                                 bp->mf_sub_mode = SUB_MF_MODE_UFP;
11789                                 bp->mf_config[vn] =
11790                                         MF_CFG_RD(bp,
11791                                                   func_mf_config[func].config);
11792                                 break;
11793                         case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
11794                                 bp->mf_config[vn] = 0;
11795                                 break;
11796                         case SHARED_FEAT_CFG_FORCE_SF_MODE_EXTENDED_MODE:
11797                                 val2 = SHMEM_RD(bp,
11798                                         dev_info.shared_hw_config.config_3);
11799                                 val2 &= SHARED_HW_CFG_EXTENDED_MF_MODE_MASK;
11800                                 switch (val2) {
11801                                 case SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR1_DOT_5:
11802                                         validate_set_si_mode(bp);
11803                                         bp->mf_sub_mode =
11804                                                         SUB_MF_MODE_NPAR1_DOT_5;
11805                                         break;
11806                                 default:
11807                                         /* Unknown configuration */
11808                                         bp->mf_config[vn] = 0;
11809                                         BNX2X_DEV_INFO("unknown extended MF mode 0x%x\n",
11810                                                        val);
11811                                 }
11812                                 break;
11813                         default:
11814                                 /* Unknown configuration: reset mf_config */
11815                                 bp->mf_config[vn] = 0;
11816                                 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val);
11817                         }
11818                 }
11819
11820                 BNX2X_DEV_INFO("%s function mode\n",
11821                                IS_MF(bp) ? "multi" : "single");
11822
11823                 switch (bp->mf_mode) {
11824                 case MULTI_FUNCTION_SD:
11825                         val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
11826                               FUNC_MF_CFG_E1HOV_TAG_MASK;
11827                         if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11828                                 bp->mf_ov = val;
11829                                 bp->path_has_ovlan = true;
11830
11831                                 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
11832                                                func, bp->mf_ov, bp->mf_ov);
11833                         } else if (bp->mf_sub_mode == SUB_MF_MODE_UFP) {
11834                                 dev_err(&bp->pdev->dev,
11835                                         "Unexpected - no valid MF OV for func %d in UFP mode\n",
11836                                         func);
11837                                 bp->path_has_ovlan = true;
11838                         } else {
11839                                 dev_err(&bp->pdev->dev,
11840                                         "No valid MF OV for func %d, aborting\n",
11841                                         func);
11842                                 return -EPERM;
11843                         }
11844                         break;
11845                 case MULTI_FUNCTION_AFEX:
11846                         BNX2X_DEV_INFO("func %d is in MF afex mode\n", func);
11847                         break;
11848                 case MULTI_FUNCTION_SI:
11849                         BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
11850                                        func);
11851                         break;
11852                 default:
11853                         if (vn) {
11854                                 dev_err(&bp->pdev->dev,
11855                                         "VN %d is in a single function mode, aborting\n",
11856                                         vn);
11857                                 return -EPERM;
11858                         }
11859                         break;
11860                 }
11861
11862                 /* check if other port on the path needs ovlan:
11863                  * Since MF configuration is shared between ports
11864                  * Possible mixed modes are only
11865                  * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
11866                  */
11867                 if (CHIP_MODE_IS_4_PORT(bp) &&
11868                     !bp->path_has_ovlan &&
11869                     !IS_MF(bp) &&
11870                     bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11871                         u8 other_port = !BP_PORT(bp);
11872                         u8 other_func = BP_PATH(bp) + 2*other_port;
11873                         val = MF_CFG_RD(bp,
11874                                         func_mf_config[other_func].e1hov_tag);
11875                         if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
11876                                 bp->path_has_ovlan = true;
11877                 }
11878         }
11879
11880         /* adjust igu_sb_cnt to MF for E1H */
11881         if (CHIP_IS_E1H(bp) && IS_MF(bp))
11882                 bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt, E1H_MAX_MF_SB_COUNT);
11883
11884         /* port info */
11885         bnx2x_get_port_hwinfo(bp);
11886
11887         /* Get MAC addresses */
11888         bnx2x_get_mac_hwinfo(bp);
11889
11890         bnx2x_get_cnic_info(bp);
11891
11892         return rc;
11893 }
11894
11895 static void bnx2x_read_fwinfo(struct bnx2x *bp)
11896 {
11897         int cnt, i, block_end, rodi;
11898         char vpd_start[BNX2X_VPD_LEN+1];
11899         char str_id_reg[VENDOR_ID_LEN+1];
11900         char str_id_cap[VENDOR_ID_LEN+1];
11901         char *vpd_data;
11902         char *vpd_extended_data = NULL;
11903         u8 len;
11904
11905         cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start);
11906         memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
11907
11908         if (cnt < BNX2X_VPD_LEN)
11909                 goto out_not_found;
11910
11911         /* VPD RO tag should be first tag after identifier string, hence
11912          * we should be able to find it in first BNX2X_VPD_LEN chars
11913          */
11914         i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN,
11915                              PCI_VPD_LRDT_RO_DATA);
11916         if (i < 0)
11917                 goto out_not_found;
11918
11919         block_end = i + PCI_VPD_LRDT_TAG_SIZE +
11920                     pci_vpd_lrdt_size(&vpd_start[i]);
11921
11922         i += PCI_VPD_LRDT_TAG_SIZE;
11923
11924         if (block_end > BNX2X_VPD_LEN) {
11925                 vpd_extended_data = kmalloc(block_end, GFP_KERNEL);
11926                 if (vpd_extended_data  == NULL)
11927                         goto out_not_found;
11928
11929                 /* read rest of vpd image into vpd_extended_data */
11930                 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN);
11931                 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN,
11932                                    block_end - BNX2X_VPD_LEN,
11933                                    vpd_extended_data + BNX2X_VPD_LEN);
11934                 if (cnt < (block_end - BNX2X_VPD_LEN))
11935                         goto out_not_found;
11936                 vpd_data = vpd_extended_data;
11937         } else
11938                 vpd_data = vpd_start;
11939
11940         /* now vpd_data holds full vpd content in both cases */
11941
11942         rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11943                                    PCI_VPD_RO_KEYWORD_MFR_ID);
11944         if (rodi < 0)
11945                 goto out_not_found;
11946
11947         len = pci_vpd_info_field_size(&vpd_data[rodi]);
11948
11949         if (len != VENDOR_ID_LEN)
11950                 goto out_not_found;
11951
11952         rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11953
11954         /* vendor specific info */
11955         snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
11956         snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
11957         if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
11958             !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
11959
11960                 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11961                                                 PCI_VPD_RO_KEYWORD_VENDOR0);
11962                 if (rodi >= 0) {
11963                         len = pci_vpd_info_field_size(&vpd_data[rodi]);
11964
11965                         rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11966
11967                         if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
11968                                 memcpy(bp->fw_ver, &vpd_data[rodi], len);
11969                                 bp->fw_ver[len] = ' ';
11970                         }
11971                 }
11972                 kfree(vpd_extended_data);
11973                 return;
11974         }
11975 out_not_found:
11976         kfree(vpd_extended_data);
11977         return;
11978 }
11979
11980 static void bnx2x_set_modes_bitmap(struct bnx2x *bp)
11981 {
11982         u32 flags = 0;
11983
11984         if (CHIP_REV_IS_FPGA(bp))
11985                 SET_FLAGS(flags, MODE_FPGA);
11986         else if (CHIP_REV_IS_EMUL(bp))
11987                 SET_FLAGS(flags, MODE_EMUL);
11988         else
11989                 SET_FLAGS(flags, MODE_ASIC);
11990
11991         if (CHIP_MODE_IS_4_PORT(bp))
11992                 SET_FLAGS(flags, MODE_PORT4);
11993         else
11994                 SET_FLAGS(flags, MODE_PORT2);
11995
11996         if (CHIP_IS_E2(bp))
11997                 SET_FLAGS(flags, MODE_E2);
11998         else if (CHIP_IS_E3(bp)) {
11999                 SET_FLAGS(flags, MODE_E3);
12000                 if (CHIP_REV(bp) == CHIP_REV_Ax)
12001                         SET_FLAGS(flags, MODE_E3_A0);
12002                 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
12003                         SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
12004         }
12005
12006         if (IS_MF(bp)) {
12007                 SET_FLAGS(flags, MODE_MF);
12008                 switch (bp->mf_mode) {
12009                 case MULTI_FUNCTION_SD:
12010                         SET_FLAGS(flags, MODE_MF_SD);
12011                         break;
12012                 case MULTI_FUNCTION_SI:
12013                         SET_FLAGS(flags, MODE_MF_SI);
12014                         break;
12015                 case MULTI_FUNCTION_AFEX:
12016                         SET_FLAGS(flags, MODE_MF_AFEX);
12017                         break;
12018                 }
12019         } else
12020                 SET_FLAGS(flags, MODE_SF);
12021
12022 #if defined(__LITTLE_ENDIAN)
12023         SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
12024 #else /*(__BIG_ENDIAN)*/
12025         SET_FLAGS(flags, MODE_BIG_ENDIAN);
12026 #endif
12027         INIT_MODE_FLAGS(bp) = flags;
12028 }
12029
12030 static int bnx2x_init_bp(struct bnx2x *bp)
12031 {
12032         int func;
12033         int rc;
12034
12035         mutex_init(&bp->port.phy_mutex);
12036         mutex_init(&bp->fw_mb_mutex);
12037         mutex_init(&bp->drv_info_mutex);
12038         bp->drv_info_mng_owner = false;
12039         spin_lock_init(&bp->stats_lock);
12040         sema_init(&bp->stats_sema, 1);
12041
12042         INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
12043         INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
12044         INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
12045         INIT_DELAYED_WORK(&bp->iov_task, bnx2x_iov_task);
12046         if (IS_PF(bp)) {
12047                 rc = bnx2x_get_hwinfo(bp);
12048                 if (rc)
12049                         return rc;
12050         } else {
12051                 eth_zero_addr(bp->dev->dev_addr);
12052         }
12053
12054         bnx2x_set_modes_bitmap(bp);
12055
12056         rc = bnx2x_alloc_mem_bp(bp);
12057         if (rc)
12058                 return rc;
12059
12060         bnx2x_read_fwinfo(bp);
12061
12062         func = BP_FUNC(bp);
12063
12064         /* need to reset chip if undi was active */
12065         if (IS_PF(bp) && !BP_NOMCP(bp)) {
12066                 /* init fw_seq */
12067                 bp->fw_seq =
12068                         SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
12069                                                         DRV_MSG_SEQ_NUMBER_MASK;
12070                 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
12071
12072                 rc = bnx2x_prev_unload(bp);
12073                 if (rc) {
12074                         bnx2x_free_mem_bp(bp);
12075                         return rc;
12076                 }
12077         }
12078
12079         if (CHIP_REV_IS_FPGA(bp))
12080                 dev_err(&bp->pdev->dev, "FPGA detected\n");
12081
12082         if (BP_NOMCP(bp) && (func == 0))
12083                 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
12084
12085         bp->disable_tpa = disable_tpa;
12086         bp->disable_tpa |= !!IS_MF_STORAGE_ONLY(bp);
12087         /* Reduce memory usage in kdump environment by disabling TPA */
12088         bp->disable_tpa |= is_kdump_kernel();
12089
12090         /* Set TPA flags */
12091         if (bp->disable_tpa) {
12092                 bp->flags &= ~(TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
12093                 bp->dev->features &= ~NETIF_F_LRO;
12094         } else {
12095                 bp->flags |= (TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
12096                 bp->dev->features |= NETIF_F_LRO;
12097         }
12098
12099         if (CHIP_IS_E1(bp))
12100                 bp->dropless_fc = 0;
12101         else
12102                 bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp);
12103
12104         bp->mrrs = mrrs;
12105
12106         bp->tx_ring_size = IS_MF_STORAGE_ONLY(bp) ? 0 : MAX_TX_AVAIL;
12107         if (IS_VF(bp))
12108                 bp->rx_ring_size = MAX_RX_AVAIL;
12109
12110         /* make sure that the numbers are in the right granularity */
12111         bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
12112         bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
12113
12114         bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ;
12115
12116         init_timer(&bp->timer);
12117         bp->timer.expires = jiffies + bp->current_interval;
12118         bp->timer.data = (unsigned long) bp;
12119         bp->timer.function = bnx2x_timer;
12120
12121         if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) &&
12122             SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) &&
12123             SHMEM2_RD(bp, dcbx_lldp_params_offset) &&
12124             SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset)) {
12125                 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
12126                 bnx2x_dcbx_init_params(bp);
12127         } else {
12128                 bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF);
12129         }
12130
12131         if (CHIP_IS_E1x(bp))
12132                 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
12133         else
12134                 bp->cnic_base_cl_id = FP_SB_MAX_E2;
12135
12136         /* multiple tx priority */
12137         if (IS_VF(bp))
12138                 bp->max_cos = 1;
12139         else if (CHIP_IS_E1x(bp))
12140                 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
12141         else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
12142                 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
12143         else if (CHIP_IS_E3B0(bp))
12144                 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
12145         else
12146                 BNX2X_ERR("unknown chip %x revision %x\n",
12147                           CHIP_NUM(bp), CHIP_REV(bp));
12148         BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos);
12149
12150         /* We need at least one default status block for slow-path events,
12151          * second status block for the L2 queue, and a third status block for
12152          * CNIC if supported.
12153          */
12154         if (IS_VF(bp))
12155                 bp->min_msix_vec_cnt = 1;
12156         else if (CNIC_SUPPORT(bp))
12157                 bp->min_msix_vec_cnt = 3;
12158         else /* PF w/o cnic */
12159                 bp->min_msix_vec_cnt = 2;
12160         BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt);
12161
12162         bp->dump_preset_idx = 1;
12163
12164         if (CHIP_IS_E3B0(bp))
12165                 bp->flags |= PTP_SUPPORTED;
12166
12167         return rc;
12168 }
12169
12170 /****************************************************************************
12171 * General service functions
12172 ****************************************************************************/
12173
12174 /*
12175  * net_device service functions
12176  */
12177
12178 /* called with rtnl_lock */
12179 static int bnx2x_open(struct net_device *dev)
12180 {
12181         struct bnx2x *bp = netdev_priv(dev);
12182         int rc;
12183
12184         bp->stats_init = true;
12185
12186         netif_carrier_off(dev);
12187
12188         bnx2x_set_power_state(bp, PCI_D0);
12189
12190         /* If parity had happen during the unload, then attentions
12191          * and/or RECOVERY_IN_PROGRES may still be set. In this case we
12192          * want the first function loaded on the current engine to
12193          * complete the recovery.
12194          * Parity recovery is only relevant for PF driver.
12195          */
12196         if (IS_PF(bp)) {
12197                 int other_engine = BP_PATH(bp) ? 0 : 1;
12198                 bool other_load_status, load_status;
12199                 bool global = false;
12200
12201                 other_load_status = bnx2x_get_load_status(bp, other_engine);
12202                 load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
12203                 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
12204                     bnx2x_chk_parity_attn(bp, &global, true)) {
12205                         do {
12206                                 /* If there are attentions and they are in a
12207                                  * global blocks, set the GLOBAL_RESET bit
12208                                  * regardless whether it will be this function
12209                                  * that will complete the recovery or not.
12210                                  */
12211                                 if (global)
12212                                         bnx2x_set_reset_global(bp);
12213
12214                                 /* Only the first function on the current
12215                                  * engine should try to recover in open. In case
12216                                  * of attentions in global blocks only the first
12217                                  * in the chip should try to recover.
12218                                  */
12219                                 if ((!load_status &&
12220                                      (!global || !other_load_status)) &&
12221                                       bnx2x_trylock_leader_lock(bp) &&
12222                                       !bnx2x_leader_reset(bp)) {
12223                                         netdev_info(bp->dev,
12224                                                     "Recovered in open\n");
12225                                         break;
12226                                 }
12227
12228                                 /* recovery has failed... */
12229                                 bnx2x_set_power_state(bp, PCI_D3hot);
12230                                 bp->recovery_state = BNX2X_RECOVERY_FAILED;
12231
12232                                 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
12233                                           "If you still see this message after a few retries then power cycle is required.\n");
12234
12235                                 return -EAGAIN;
12236                         } while (0);
12237                 }
12238         }
12239
12240         bp->recovery_state = BNX2X_RECOVERY_DONE;
12241         rc = bnx2x_nic_load(bp, LOAD_OPEN);
12242         if (rc)
12243                 return rc;
12244         return 0;
12245 }
12246
12247 /* called with rtnl_lock */
12248 static int bnx2x_close(struct net_device *dev)
12249 {
12250         struct bnx2x *bp = netdev_priv(dev);
12251
12252         /* Unload the driver, release IRQs */
12253         bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
12254
12255         return 0;
12256 }
12257
12258 static int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
12259                                       struct bnx2x_mcast_ramrod_params *p)
12260 {
12261         int mc_count = netdev_mc_count(bp->dev);
12262         struct bnx2x_mcast_list_elem *mc_mac =
12263                 kcalloc(mc_count, sizeof(*mc_mac), GFP_ATOMIC);
12264         struct netdev_hw_addr *ha;
12265
12266         if (!mc_mac)
12267                 return -ENOMEM;
12268
12269         INIT_LIST_HEAD(&p->mcast_list);
12270
12271         netdev_for_each_mc_addr(ha, bp->dev) {
12272                 mc_mac->mac = bnx2x_mc_addr(ha);
12273                 list_add_tail(&mc_mac->link, &p->mcast_list);
12274                 mc_mac++;
12275         }
12276
12277         p->mcast_list_len = mc_count;
12278
12279         return 0;
12280 }
12281
12282 static void bnx2x_free_mcast_macs_list(
12283         struct bnx2x_mcast_ramrod_params *p)
12284 {
12285         struct bnx2x_mcast_list_elem *mc_mac =
12286                 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
12287                                  link);
12288
12289         WARN_ON(!mc_mac);
12290         kfree(mc_mac);
12291 }
12292
12293 /**
12294  * bnx2x_set_uc_list - configure a new unicast MACs list.
12295  *
12296  * @bp: driver handle
12297  *
12298  * We will use zero (0) as a MAC type for these MACs.
12299  */
12300 static int bnx2x_set_uc_list(struct bnx2x *bp)
12301 {
12302         int rc;
12303         struct net_device *dev = bp->dev;
12304         struct netdev_hw_addr *ha;
12305         struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
12306         unsigned long ramrod_flags = 0;
12307
12308         /* First schedule a cleanup up of old configuration */
12309         rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
12310         if (rc < 0) {
12311                 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
12312                 return rc;
12313         }
12314
12315         netdev_for_each_uc_addr(ha, dev) {
12316                 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
12317                                        BNX2X_UC_LIST_MAC, &ramrod_flags);
12318                 if (rc == -EEXIST) {
12319                         DP(BNX2X_MSG_SP,
12320                            "Failed to schedule ADD operations: %d\n", rc);
12321                         /* do not treat adding same MAC as error */
12322                         rc = 0;
12323
12324                 } else if (rc < 0) {
12325
12326                         BNX2X_ERR("Failed to schedule ADD operations: %d\n",
12327                                   rc);
12328                         return rc;
12329                 }
12330         }
12331
12332         /* Execute the pending commands */
12333         __set_bit(RAMROD_CONT, &ramrod_flags);
12334         return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
12335                                  BNX2X_UC_LIST_MAC, &ramrod_flags);
12336 }
12337
12338 static int bnx2x_set_mc_list(struct bnx2x *bp)
12339 {
12340         struct net_device *dev = bp->dev;
12341         struct bnx2x_mcast_ramrod_params rparam = {NULL};
12342         int rc = 0;
12343
12344         rparam.mcast_obj = &bp->mcast_obj;
12345
12346         /* first, clear all configured multicast MACs */
12347         rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
12348         if (rc < 0) {
12349                 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc);
12350                 return rc;
12351         }
12352
12353         /* then, configure a new MACs list */
12354         if (netdev_mc_count(dev)) {
12355                 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
12356                 if (rc) {
12357                         BNX2X_ERR("Failed to create multicast MACs list: %d\n",
12358                                   rc);
12359                         return rc;
12360                 }
12361
12362                 /* Now add the new MACs */
12363                 rc = bnx2x_config_mcast(bp, &rparam,
12364                                         BNX2X_MCAST_CMD_ADD);
12365                 if (rc < 0)
12366                         BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
12367                                   rc);
12368
12369                 bnx2x_free_mcast_macs_list(&rparam);
12370         }
12371
12372         return rc;
12373 }
12374
12375 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
12376 static void bnx2x_set_rx_mode(struct net_device *dev)
12377 {
12378         struct bnx2x *bp = netdev_priv(dev);
12379
12380         if (bp->state != BNX2X_STATE_OPEN) {
12381                 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
12382                 return;
12383         } else {
12384                 /* Schedule an SP task to handle rest of change */
12385                 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_RX_MODE,
12386                                        NETIF_MSG_IFUP);
12387         }
12388 }
12389
12390 void bnx2x_set_rx_mode_inner(struct bnx2x *bp)
12391 {
12392         u32 rx_mode = BNX2X_RX_MODE_NORMAL;
12393
12394         DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
12395
12396         netif_addr_lock_bh(bp->dev);
12397
12398         if (bp->dev->flags & IFF_PROMISC) {
12399                 rx_mode = BNX2X_RX_MODE_PROMISC;
12400         } else if ((bp->dev->flags & IFF_ALLMULTI) ||
12401                    ((netdev_mc_count(bp->dev) > BNX2X_MAX_MULTICAST) &&
12402                     CHIP_IS_E1(bp))) {
12403                 rx_mode = BNX2X_RX_MODE_ALLMULTI;
12404         } else {
12405                 if (IS_PF(bp)) {
12406                         /* some multicasts */
12407                         if (bnx2x_set_mc_list(bp) < 0)
12408                                 rx_mode = BNX2X_RX_MODE_ALLMULTI;
12409
12410                         /* release bh lock, as bnx2x_set_uc_list might sleep */
12411                         netif_addr_unlock_bh(bp->dev);
12412                         if (bnx2x_set_uc_list(bp) < 0)
12413                                 rx_mode = BNX2X_RX_MODE_PROMISC;
12414                         netif_addr_lock_bh(bp->dev);
12415                 } else {
12416                         /* configuring mcast to a vf involves sleeping (when we
12417                          * wait for the pf's response).
12418                          */
12419                         bnx2x_schedule_sp_rtnl(bp,
12420                                                BNX2X_SP_RTNL_VFPF_MCAST, 0);
12421                 }
12422         }
12423
12424         bp->rx_mode = rx_mode;
12425         /* handle ISCSI SD mode */
12426         if (IS_MF_ISCSI_ONLY(bp))
12427                 bp->rx_mode = BNX2X_RX_MODE_NONE;
12428
12429         /* Schedule the rx_mode command */
12430         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
12431                 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
12432                 netif_addr_unlock_bh(bp->dev);
12433                 return;
12434         }
12435
12436         if (IS_PF(bp)) {
12437                 bnx2x_set_storm_rx_mode(bp);
12438                 netif_addr_unlock_bh(bp->dev);
12439         } else {
12440                 /* VF will need to request the PF to make this change, and so
12441                  * the VF needs to release the bottom-half lock prior to the
12442                  * request (as it will likely require sleep on the VF side)
12443                  */
12444                 netif_addr_unlock_bh(bp->dev);
12445                 bnx2x_vfpf_storm_rx_mode(bp);
12446         }
12447 }
12448
12449 /* called with rtnl_lock */
12450 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
12451                            int devad, u16 addr)
12452 {
12453         struct bnx2x *bp = netdev_priv(netdev);
12454         u16 value;
12455         int rc;
12456
12457         DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
12458            prtad, devad, addr);
12459
12460         /* The HW expects different devad if CL22 is used */
12461         devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
12462
12463         bnx2x_acquire_phy_lock(bp);
12464         rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
12465         bnx2x_release_phy_lock(bp);
12466         DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
12467
12468         if (!rc)
12469                 rc = value;
12470         return rc;
12471 }
12472
12473 /* called with rtnl_lock */
12474 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
12475                             u16 addr, u16 value)
12476 {
12477         struct bnx2x *bp = netdev_priv(netdev);
12478         int rc;
12479
12480         DP(NETIF_MSG_LINK,
12481            "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
12482            prtad, devad, addr, value);
12483
12484         /* The HW expects different devad if CL22 is used */
12485         devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
12486
12487         bnx2x_acquire_phy_lock(bp);
12488         rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
12489         bnx2x_release_phy_lock(bp);
12490         return rc;
12491 }
12492
12493 /* called with rtnl_lock */
12494 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
12495 {
12496         struct bnx2x *bp = netdev_priv(dev);
12497         struct mii_ioctl_data *mdio = if_mii(ifr);
12498
12499         if (!netif_running(dev))
12500                 return -EAGAIN;
12501
12502         switch (cmd) {
12503         case SIOCSHWTSTAMP:
12504                 return bnx2x_hwtstamp_ioctl(bp, ifr);
12505         default:
12506                 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
12507                    mdio->phy_id, mdio->reg_num, mdio->val_in);
12508                 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
12509         }
12510 }
12511
12512 #ifdef CONFIG_NET_POLL_CONTROLLER
12513 static void poll_bnx2x(struct net_device *dev)
12514 {
12515         struct bnx2x *bp = netdev_priv(dev);
12516         int i;
12517
12518         for_each_eth_queue(bp, i) {
12519                 struct bnx2x_fastpath *fp = &bp->fp[i];
12520                 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
12521         }
12522 }
12523 #endif
12524
12525 static int bnx2x_validate_addr(struct net_device *dev)
12526 {
12527         struct bnx2x *bp = netdev_priv(dev);
12528
12529         /* query the bulletin board for mac address configured by the PF */
12530         if (IS_VF(bp))
12531                 bnx2x_sample_bulletin(bp);
12532
12533         if (!is_valid_ether_addr(dev->dev_addr)) {
12534                 BNX2X_ERR("Non-valid Ethernet address\n");
12535                 return -EADDRNOTAVAIL;
12536         }
12537         return 0;
12538 }
12539
12540 static int bnx2x_get_phys_port_id(struct net_device *netdev,
12541                                   struct netdev_phys_port_id *ppid)
12542 {
12543         struct bnx2x *bp = netdev_priv(netdev);
12544
12545         if (!(bp->flags & HAS_PHYS_PORT_ID))
12546                 return -EOPNOTSUPP;
12547
12548         ppid->id_len = sizeof(bp->phys_port_id);
12549         memcpy(ppid->id, bp->phys_port_id, ppid->id_len);
12550
12551         return 0;
12552 }
12553
12554 static bool bnx2x_gso_check(struct sk_buff *skb, struct net_device *dev)
12555 {
12556         return vxlan_gso_check(skb);
12557 }
12558
12559 static const struct net_device_ops bnx2x_netdev_ops = {
12560         .ndo_open               = bnx2x_open,
12561         .ndo_stop               = bnx2x_close,
12562         .ndo_start_xmit         = bnx2x_start_xmit,
12563         .ndo_select_queue       = bnx2x_select_queue,
12564         .ndo_set_rx_mode        = bnx2x_set_rx_mode,
12565         .ndo_set_mac_address    = bnx2x_change_mac_addr,
12566         .ndo_validate_addr      = bnx2x_validate_addr,
12567         .ndo_do_ioctl           = bnx2x_ioctl,
12568         .ndo_change_mtu         = bnx2x_change_mtu,
12569         .ndo_fix_features       = bnx2x_fix_features,
12570         .ndo_set_features       = bnx2x_set_features,
12571         .ndo_tx_timeout         = bnx2x_tx_timeout,
12572 #ifdef CONFIG_NET_POLL_CONTROLLER
12573         .ndo_poll_controller    = poll_bnx2x,
12574 #endif
12575         .ndo_setup_tc           = bnx2x_setup_tc,
12576 #ifdef CONFIG_BNX2X_SRIOV
12577         .ndo_set_vf_mac         = bnx2x_set_vf_mac,
12578         .ndo_set_vf_vlan        = bnx2x_set_vf_vlan,
12579         .ndo_get_vf_config      = bnx2x_get_vf_config,
12580 #endif
12581 #ifdef NETDEV_FCOE_WWNN
12582         .ndo_fcoe_get_wwn       = bnx2x_fcoe_get_wwn,
12583 #endif
12584
12585 #ifdef CONFIG_NET_RX_BUSY_POLL
12586         .ndo_busy_poll          = bnx2x_low_latency_recv,
12587 #endif
12588         .ndo_get_phys_port_id   = bnx2x_get_phys_port_id,
12589         .ndo_set_vf_link_state  = bnx2x_set_vf_link_state,
12590         .ndo_gso_check          = bnx2x_gso_check,
12591 };
12592
12593 static int bnx2x_set_coherency_mask(struct bnx2x *bp)
12594 {
12595         struct device *dev = &bp->pdev->dev;
12596
12597         if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)) != 0 &&
12598             dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)) != 0) {
12599                 dev_err(dev, "System does not support DMA, aborting\n");
12600                 return -EIO;
12601         }
12602
12603         return 0;
12604 }
12605
12606 static void bnx2x_disable_pcie_error_reporting(struct bnx2x *bp)
12607 {
12608         if (bp->flags & AER_ENABLED) {
12609                 pci_disable_pcie_error_reporting(bp->pdev);
12610                 bp->flags &= ~AER_ENABLED;
12611         }
12612 }
12613
12614 static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev,
12615                           struct net_device *dev, unsigned long board_type)
12616 {
12617         int rc;
12618         u32 pci_cfg_dword;
12619         bool chip_is_e1x = (board_type == BCM57710 ||
12620                             board_type == BCM57711 ||
12621                             board_type == BCM57711E);
12622
12623         SET_NETDEV_DEV(dev, &pdev->dev);
12624
12625         bp->dev = dev;
12626         bp->pdev = pdev;
12627
12628         rc = pci_enable_device(pdev);
12629         if (rc) {
12630                 dev_err(&bp->pdev->dev,
12631                         "Cannot enable PCI device, aborting\n");
12632                 goto err_out;
12633         }
12634
12635         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
12636                 dev_err(&bp->pdev->dev,
12637                         "Cannot find PCI device base address, aborting\n");
12638                 rc = -ENODEV;
12639                 goto err_out_disable;
12640         }
12641
12642         if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
12643                 dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n");
12644                 rc = -ENODEV;
12645                 goto err_out_disable;
12646         }
12647
12648         pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword);
12649         if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) ==
12650             PCICFG_REVESION_ID_ERROR_VAL) {
12651                 pr_err("PCI device error, probably due to fan failure, aborting\n");
12652                 rc = -ENODEV;
12653                 goto err_out_disable;
12654         }
12655
12656         if (atomic_read(&pdev->enable_cnt) == 1) {
12657                 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
12658                 if (rc) {
12659                         dev_err(&bp->pdev->dev,
12660                                 "Cannot obtain PCI resources, aborting\n");
12661                         goto err_out_disable;
12662                 }
12663
12664                 pci_set_master(pdev);
12665                 pci_save_state(pdev);
12666         }
12667
12668         if (IS_PF(bp)) {
12669                 if (!pdev->pm_cap) {
12670                         dev_err(&bp->pdev->dev,
12671                                 "Cannot find power management capability, aborting\n");
12672                         rc = -EIO;
12673                         goto err_out_release;
12674                 }
12675         }
12676
12677         if (!pci_is_pcie(pdev)) {
12678                 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
12679                 rc = -EIO;
12680                 goto err_out_release;
12681         }
12682
12683         rc = bnx2x_set_coherency_mask(bp);
12684         if (rc)
12685                 goto err_out_release;
12686
12687         dev->mem_start = pci_resource_start(pdev, 0);
12688         dev->base_addr = dev->mem_start;
12689         dev->mem_end = pci_resource_end(pdev, 0);
12690
12691         dev->irq = pdev->irq;
12692
12693         bp->regview = pci_ioremap_bar(pdev, 0);
12694         if (!bp->regview) {
12695                 dev_err(&bp->pdev->dev,
12696                         "Cannot map register space, aborting\n");
12697                 rc = -ENOMEM;
12698                 goto err_out_release;
12699         }
12700
12701         /* In E1/E1H use pci device function given by kernel.
12702          * In E2/E3 read physical function from ME register since these chips
12703          * support Physical Device Assignment where kernel BDF maybe arbitrary
12704          * (depending on hypervisor).
12705          */
12706         if (chip_is_e1x) {
12707                 bp->pf_num = PCI_FUNC(pdev->devfn);
12708         } else {
12709                 /* chip is E2/3*/
12710                 pci_read_config_dword(bp->pdev,
12711                                       PCICFG_ME_REGISTER, &pci_cfg_dword);
12712                 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
12713                                   ME_REG_ABS_PF_NUM_SHIFT);
12714         }
12715         BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
12716
12717         /* clean indirect addresses */
12718         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
12719                                PCICFG_VENDOR_ID_OFFSET);
12720
12721         /* AER (Advanced Error reporting) configuration */
12722         rc = pci_enable_pcie_error_reporting(pdev);
12723         if (!rc)
12724                 bp->flags |= AER_ENABLED;
12725         else
12726                 BNX2X_DEV_INFO("Failed To configure PCIe AER [%d]\n", rc);
12727
12728         /*
12729          * Clean the following indirect addresses for all functions since it
12730          * is not used by the driver.
12731          */
12732         if (IS_PF(bp)) {
12733                 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
12734                 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
12735                 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
12736                 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
12737
12738                 if (chip_is_e1x) {
12739                         REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
12740                         REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
12741                         REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
12742                         REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
12743                 }
12744
12745                 /* Enable internal target-read (in case we are probed after PF
12746                  * FLR). Must be done prior to any BAR read access. Only for
12747                  * 57712 and up
12748                  */
12749                 if (!chip_is_e1x)
12750                         REG_WR(bp,
12751                                PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
12752         }
12753
12754         dev->watchdog_timeo = TX_TIMEOUT;
12755
12756         dev->netdev_ops = &bnx2x_netdev_ops;
12757         bnx2x_set_ethtool_ops(bp, dev);
12758
12759         dev->priv_flags |= IFF_UNICAST_FLT;
12760
12761         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
12762                 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
12763                 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO |
12764                 NETIF_F_RXHASH | NETIF_F_HW_VLAN_CTAG_TX;
12765         if (!CHIP_IS_E1x(bp)) {
12766                 dev->hw_features |= NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL |
12767                                     NETIF_F_GSO_IPIP | NETIF_F_GSO_SIT;
12768                 dev->hw_enc_features =
12769                         NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
12770                         NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
12771                         NETIF_F_GSO_IPIP |
12772                         NETIF_F_GSO_SIT |
12773                         NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL;
12774         }
12775
12776         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
12777                 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
12778
12779         dev->features |= dev->hw_features | NETIF_F_HW_VLAN_CTAG_RX;
12780         dev->features |= NETIF_F_HIGHDMA;
12781
12782         /* Add Loopback capability to the device */
12783         dev->hw_features |= NETIF_F_LOOPBACK;
12784
12785 #ifdef BCM_DCBNL
12786         dev->dcbnl_ops = &bnx2x_dcbnl_ops;
12787 #endif
12788
12789         /* get_port_hwinfo() will set prtad and mmds properly */
12790         bp->mdio.prtad = MDIO_PRTAD_NONE;
12791         bp->mdio.mmds = 0;
12792         bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
12793         bp->mdio.dev = dev;
12794         bp->mdio.mdio_read = bnx2x_mdio_read;
12795         bp->mdio.mdio_write = bnx2x_mdio_write;
12796
12797         return 0;
12798
12799 err_out_release:
12800         if (atomic_read(&pdev->enable_cnt) == 1)
12801                 pci_release_regions(pdev);
12802
12803 err_out_disable:
12804         pci_disable_device(pdev);
12805
12806 err_out:
12807         return rc;
12808 }
12809
12810 static int bnx2x_check_firmware(struct bnx2x *bp)
12811 {
12812         const struct firmware *firmware = bp->firmware;
12813         struct bnx2x_fw_file_hdr *fw_hdr;
12814         struct bnx2x_fw_file_section *sections;
12815         u32 offset, len, num_ops;
12816         __be16 *ops_offsets;
12817         int i;
12818         const u8 *fw_ver;
12819
12820         if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) {
12821                 BNX2X_ERR("Wrong FW size\n");
12822                 return -EINVAL;
12823         }
12824
12825         fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
12826         sections = (struct bnx2x_fw_file_section *)fw_hdr;
12827
12828         /* Make sure none of the offsets and sizes make us read beyond
12829          * the end of the firmware data */
12830         for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
12831                 offset = be32_to_cpu(sections[i].offset);
12832                 len = be32_to_cpu(sections[i].len);
12833                 if (offset + len > firmware->size) {
12834                         BNX2X_ERR("Section %d length is out of bounds\n", i);
12835                         return -EINVAL;
12836                 }
12837         }
12838
12839         /* Likewise for the init_ops offsets */
12840         offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
12841         ops_offsets = (__force __be16 *)(firmware->data + offset);
12842         num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
12843
12844         for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
12845                 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
12846                         BNX2X_ERR("Section offset %d is out of bounds\n", i);
12847                         return -EINVAL;
12848                 }
12849         }
12850
12851         /* Check FW version */
12852         offset = be32_to_cpu(fw_hdr->fw_version.offset);
12853         fw_ver = firmware->data + offset;
12854         if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
12855             (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
12856             (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
12857             (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
12858                 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
12859                        fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3],
12860                        BCM_5710_FW_MAJOR_VERSION,
12861                        BCM_5710_FW_MINOR_VERSION,
12862                        BCM_5710_FW_REVISION_VERSION,
12863                        BCM_5710_FW_ENGINEERING_VERSION);
12864                 return -EINVAL;
12865         }
12866
12867         return 0;
12868 }
12869
12870 static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
12871 {
12872         const __be32 *source = (const __be32 *)_source;
12873         u32 *target = (u32 *)_target;
12874         u32 i;
12875
12876         for (i = 0; i < n/4; i++)
12877                 target[i] = be32_to_cpu(source[i]);
12878 }
12879
12880 /*
12881    Ops array is stored in the following format:
12882    {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
12883  */
12884 static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
12885 {
12886         const __be32 *source = (const __be32 *)_source;
12887         struct raw_op *target = (struct raw_op *)_target;
12888         u32 i, j, tmp;
12889
12890         for (i = 0, j = 0; i < n/8; i++, j += 2) {
12891                 tmp = be32_to_cpu(source[j]);
12892                 target[i].op = (tmp >> 24) & 0xff;
12893                 target[i].offset = tmp & 0xffffff;
12894                 target[i].raw_data = be32_to_cpu(source[j + 1]);
12895         }
12896 }
12897
12898 /* IRO array is stored in the following format:
12899  * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
12900  */
12901 static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
12902 {
12903         const __be32 *source = (const __be32 *)_source;
12904         struct iro *target = (struct iro *)_target;
12905         u32 i, j, tmp;
12906
12907         for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
12908                 target[i].base = be32_to_cpu(source[j]);
12909                 j++;
12910                 tmp = be32_to_cpu(source[j]);
12911                 target[i].m1 = (tmp >> 16) & 0xffff;
12912                 target[i].m2 = tmp & 0xffff;
12913                 j++;
12914                 tmp = be32_to_cpu(source[j]);
12915                 target[i].m3 = (tmp >> 16) & 0xffff;
12916                 target[i].size = tmp & 0xffff;
12917                 j++;
12918         }
12919 }
12920
12921 static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
12922 {
12923         const __be16 *source = (const __be16 *)_source;
12924         u16 *target = (u16 *)_target;
12925         u32 i;
12926
12927         for (i = 0; i < n/2; i++)
12928                 target[i] = be16_to_cpu(source[i]);
12929 }
12930
12931 #define BNX2X_ALLOC_AND_SET(arr, lbl, func)                             \
12932 do {                                                                    \
12933         u32 len = be32_to_cpu(fw_hdr->arr.len);                         \
12934         bp->arr = kmalloc(len, GFP_KERNEL);                             \
12935         if (!bp->arr)                                                   \
12936                 goto lbl;                                               \
12937         func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset),      \
12938              (u8 *)bp->arr, len);                                       \
12939 } while (0)
12940
12941 static int bnx2x_init_firmware(struct bnx2x *bp)
12942 {
12943         const char *fw_file_name;
12944         struct bnx2x_fw_file_hdr *fw_hdr;
12945         int rc;
12946
12947         if (bp->firmware)
12948                 return 0;
12949
12950         if (CHIP_IS_E1(bp))
12951                 fw_file_name = FW_FILE_NAME_E1;
12952         else if (CHIP_IS_E1H(bp))
12953                 fw_file_name = FW_FILE_NAME_E1H;
12954         else if (!CHIP_IS_E1x(bp))
12955                 fw_file_name = FW_FILE_NAME_E2;
12956         else {
12957                 BNX2X_ERR("Unsupported chip revision\n");
12958                 return -EINVAL;
12959         }
12960         BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
12961
12962         rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
12963         if (rc) {
12964                 BNX2X_ERR("Can't load firmware file %s\n",
12965                           fw_file_name);
12966                 goto request_firmware_exit;
12967         }
12968
12969         rc = bnx2x_check_firmware(bp);
12970         if (rc) {
12971                 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
12972                 goto request_firmware_exit;
12973         }
12974
12975         fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
12976
12977         /* Initialize the pointers to the init arrays */
12978         /* Blob */
12979         BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
12980
12981         /* Opcodes */
12982         BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
12983
12984         /* Offsets */
12985         BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
12986                             be16_to_cpu_n);
12987
12988         /* STORMs firmware */
12989         INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12990                         be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
12991         INIT_TSEM_PRAM_DATA(bp)      = bp->firmware->data +
12992                         be32_to_cpu(fw_hdr->tsem_pram_data.offset);
12993         INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12994                         be32_to_cpu(fw_hdr->usem_int_table_data.offset);
12995         INIT_USEM_PRAM_DATA(bp)      = bp->firmware->data +
12996                         be32_to_cpu(fw_hdr->usem_pram_data.offset);
12997         INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12998                         be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
12999         INIT_XSEM_PRAM_DATA(bp)      = bp->firmware->data +
13000                         be32_to_cpu(fw_hdr->xsem_pram_data.offset);
13001         INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
13002                         be32_to_cpu(fw_hdr->csem_int_table_data.offset);
13003         INIT_CSEM_PRAM_DATA(bp)      = bp->firmware->data +
13004                         be32_to_cpu(fw_hdr->csem_pram_data.offset);
13005         /* IRO */
13006         BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
13007
13008         return 0;
13009
13010 iro_alloc_err:
13011         kfree(bp->init_ops_offsets);
13012 init_offsets_alloc_err:
13013         kfree(bp->init_ops);
13014 init_ops_alloc_err:
13015         kfree(bp->init_data);
13016 request_firmware_exit:
13017         release_firmware(bp->firmware);
13018         bp->firmware = NULL;
13019
13020         return rc;
13021 }
13022
13023 static void bnx2x_release_firmware(struct bnx2x *bp)
13024 {
13025         kfree(bp->init_ops_offsets);
13026         kfree(bp->init_ops);
13027         kfree(bp->init_data);
13028         release_firmware(bp->firmware);
13029         bp->firmware = NULL;
13030 }
13031
13032 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
13033         .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
13034         .init_hw_cmn      = bnx2x_init_hw_common,
13035         .init_hw_port     = bnx2x_init_hw_port,
13036         .init_hw_func     = bnx2x_init_hw_func,
13037
13038         .reset_hw_cmn     = bnx2x_reset_common,
13039         .reset_hw_port    = bnx2x_reset_port,
13040         .reset_hw_func    = bnx2x_reset_func,
13041
13042         .gunzip_init      = bnx2x_gunzip_init,
13043         .gunzip_end       = bnx2x_gunzip_end,
13044
13045         .init_fw          = bnx2x_init_firmware,
13046         .release_fw       = bnx2x_release_firmware,
13047 };
13048
13049 void bnx2x__init_func_obj(struct bnx2x *bp)
13050 {
13051         /* Prepare DMAE related driver resources */
13052         bnx2x_setup_dmae(bp);
13053
13054         bnx2x_init_func_obj(bp, &bp->func_obj,
13055                             bnx2x_sp(bp, func_rdata),
13056                             bnx2x_sp_mapping(bp, func_rdata),
13057                             bnx2x_sp(bp, func_afex_rdata),
13058                             bnx2x_sp_mapping(bp, func_afex_rdata),
13059                             &bnx2x_func_sp_drv);
13060 }
13061
13062 /* must be called after sriov-enable */
13063 static int bnx2x_set_qm_cid_count(struct bnx2x *bp)
13064 {
13065         int cid_count = BNX2X_L2_MAX_CID(bp);
13066
13067         if (IS_SRIOV(bp))
13068                 cid_count += BNX2X_VF_CIDS;
13069
13070         if (CNIC_SUPPORT(bp))
13071                 cid_count += CNIC_CID_MAX;
13072
13073         return roundup(cid_count, QM_CID_ROUND);
13074 }
13075
13076 /**
13077  * bnx2x_get_num_none_def_sbs - return the number of none default SBs
13078  *
13079  * @dev:        pci device
13080  *
13081  */
13082 static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev, int cnic_cnt)
13083 {
13084         int index;
13085         u16 control = 0;
13086
13087         /*
13088          * If MSI-X is not supported - return number of SBs needed to support
13089          * one fast path queue: one FP queue + SB for CNIC
13090          */
13091         if (!pdev->msix_cap) {
13092                 dev_info(&pdev->dev, "no msix capability found\n");
13093                 return 1 + cnic_cnt;
13094         }
13095         dev_info(&pdev->dev, "msix capability found\n");
13096
13097         /*
13098          * The value in the PCI configuration space is the index of the last
13099          * entry, namely one less than the actual size of the table, which is
13100          * exactly what we want to return from this function: number of all SBs
13101          * without the default SB.
13102          * For VFs there is no default SB, then we return (index+1).
13103          */
13104         pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &control);
13105
13106         index = control & PCI_MSIX_FLAGS_QSIZE;
13107
13108         return index;
13109 }
13110
13111 static int set_max_cos_est(int chip_id)
13112 {
13113         switch (chip_id) {
13114         case BCM57710:
13115         case BCM57711:
13116         case BCM57711E:
13117                 return BNX2X_MULTI_TX_COS_E1X;
13118         case BCM57712:
13119         case BCM57712_MF:
13120                 return BNX2X_MULTI_TX_COS_E2_E3A0;
13121         case BCM57800:
13122         case BCM57800_MF:
13123         case BCM57810:
13124         case BCM57810_MF:
13125         case BCM57840_4_10:
13126         case BCM57840_2_20:
13127         case BCM57840_O:
13128         case BCM57840_MFO:
13129         case BCM57840_MF:
13130         case BCM57811:
13131         case BCM57811_MF:
13132                 return BNX2X_MULTI_TX_COS_E3B0;
13133         case BCM57712_VF:
13134         case BCM57800_VF:
13135         case BCM57810_VF:
13136         case BCM57840_VF:
13137         case BCM57811_VF:
13138                 return 1;
13139         default:
13140                 pr_err("Unknown board_type (%d), aborting\n", chip_id);
13141                 return -ENODEV;
13142         }
13143 }
13144
13145 static int set_is_vf(int chip_id)
13146 {
13147         switch (chip_id) {
13148         case BCM57712_VF:
13149         case BCM57800_VF:
13150         case BCM57810_VF:
13151         case BCM57840_VF:
13152         case BCM57811_VF:
13153                 return true;
13154         default:
13155                 return false;
13156         }
13157 }
13158
13159 /* nig_tsgen registers relative address */
13160 #define tsgen_ctrl 0x0
13161 #define tsgen_freecount 0x10
13162 #define tsgen_synctime_t0 0x20
13163 #define tsgen_offset_t0 0x28
13164 #define tsgen_drift_t0 0x30
13165 #define tsgen_synctime_t1 0x58
13166 #define tsgen_offset_t1 0x60
13167 #define tsgen_drift_t1 0x68
13168
13169 /* FW workaround for setting drift */
13170 static int bnx2x_send_update_drift_ramrod(struct bnx2x *bp, int drift_dir,
13171                                           int best_val, int best_period)
13172 {
13173         struct bnx2x_func_state_params func_params = {NULL};
13174         struct bnx2x_func_set_timesync_params *set_timesync_params =
13175                 &func_params.params.set_timesync;
13176
13177         /* Prepare parameters for function state transitions */
13178         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
13179         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
13180
13181         func_params.f_obj = &bp->func_obj;
13182         func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC;
13183
13184         /* Function parameters */
13185         set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_SET;
13186         set_timesync_params->offset_cmd = TS_OFFSET_KEEP;
13187         set_timesync_params->add_sub_drift_adjust_value =
13188                 drift_dir ? TS_ADD_VALUE : TS_SUB_VALUE;
13189         set_timesync_params->drift_adjust_value = best_val;
13190         set_timesync_params->drift_adjust_period = best_period;
13191
13192         return bnx2x_func_state_change(bp, &func_params);
13193 }
13194
13195 static int bnx2x_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
13196 {
13197         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13198         int rc;
13199         int drift_dir = 1;
13200         int val, period, period1, period2, dif, dif1, dif2;
13201         int best_dif = BNX2X_MAX_PHC_DRIFT, best_period = 0, best_val = 0;
13202
13203         DP(BNX2X_MSG_PTP, "PTP adjfreq called, ppb = %d\n", ppb);
13204
13205         if (!netif_running(bp->dev)) {
13206                 DP(BNX2X_MSG_PTP,
13207                    "PTP adjfreq called while the interface is down\n");
13208                 return -EFAULT;
13209         }
13210
13211         if (ppb < 0) {
13212                 ppb = -ppb;
13213                 drift_dir = 0;
13214         }
13215
13216         if (ppb == 0) {
13217                 best_val = 1;
13218                 best_period = 0x1FFFFFF;
13219         } else if (ppb >= BNX2X_MAX_PHC_DRIFT) {
13220                 best_val = 31;
13221                 best_period = 1;
13222         } else {
13223                 /* Changed not to allow val = 8, 16, 24 as these values
13224                  * are not supported in workaround.
13225                  */
13226                 for (val = 0; val <= 31; val++) {
13227                         if ((val & 0x7) == 0)
13228                                 continue;
13229                         period1 = val * 1000000 / ppb;
13230                         period2 = period1 + 1;
13231                         if (period1 != 0)
13232                                 dif1 = ppb - (val * 1000000 / period1);
13233                         else
13234                                 dif1 = BNX2X_MAX_PHC_DRIFT;
13235                         if (dif1 < 0)
13236                                 dif1 = -dif1;
13237                         dif2 = ppb - (val * 1000000 / period2);
13238                         if (dif2 < 0)
13239                                 dif2 = -dif2;
13240                         dif = (dif1 < dif2) ? dif1 : dif2;
13241                         period = (dif1 < dif2) ? period1 : period2;
13242                         if (dif < best_dif) {
13243                                 best_dif = dif;
13244                                 best_val = val;
13245                                 best_period = period;
13246                         }
13247                 }
13248         }
13249
13250         rc = bnx2x_send_update_drift_ramrod(bp, drift_dir, best_val,
13251                                             best_period);
13252         if (rc) {
13253                 BNX2X_ERR("Failed to set drift\n");
13254                 return -EFAULT;
13255         }
13256
13257         DP(BNX2X_MSG_PTP, "Configrued val = %d, period = %d\n", best_val,
13258            best_period);
13259
13260         return 0;
13261 }
13262
13263 static int bnx2x_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
13264 {
13265         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13266         u64 now;
13267
13268         DP(BNX2X_MSG_PTP, "PTP adjtime called, delta = %llx\n", delta);
13269
13270         now = timecounter_read(&bp->timecounter);
13271         now += delta;
13272         /* Re-init the timecounter */
13273         timecounter_init(&bp->timecounter, &bp->cyclecounter, now);
13274
13275         return 0;
13276 }
13277
13278 static int bnx2x_ptp_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
13279 {
13280         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13281         u64 ns;
13282         u32 remainder;
13283
13284         ns = timecounter_read(&bp->timecounter);
13285
13286         DP(BNX2X_MSG_PTP, "PTP gettime called, ns = %llu\n", ns);
13287
13288         ts->tv_sec = div_u64_rem(ns, 1000000000ULL, &remainder);
13289         ts->tv_nsec = remainder;
13290
13291         return 0;
13292 }
13293
13294 static int bnx2x_ptp_settime(struct ptp_clock_info *ptp,
13295                              const struct timespec *ts)
13296 {
13297         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13298         u64 ns;
13299
13300         ns = ts->tv_sec * 1000000000ULL;
13301         ns += ts->tv_nsec;
13302
13303         DP(BNX2X_MSG_PTP, "PTP settime called, ns = %llu\n", ns);
13304
13305         /* Re-init the timecounter */
13306         timecounter_init(&bp->timecounter, &bp->cyclecounter, ns);
13307
13308         return 0;
13309 }
13310
13311 /* Enable (or disable) ancillary features of the phc subsystem */
13312 static int bnx2x_ptp_enable(struct ptp_clock_info *ptp,
13313                             struct ptp_clock_request *rq, int on)
13314 {
13315         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13316
13317         BNX2X_ERR("PHC ancillary features are not supported\n");
13318         return -ENOTSUPP;
13319 }
13320
13321 void bnx2x_register_phc(struct bnx2x *bp)
13322 {
13323         /* Fill the ptp_clock_info struct and register PTP clock*/
13324         bp->ptp_clock_info.owner = THIS_MODULE;
13325         snprintf(bp->ptp_clock_info.name, 16, "%s", bp->dev->name);
13326         bp->ptp_clock_info.max_adj = BNX2X_MAX_PHC_DRIFT; /* In PPB */
13327         bp->ptp_clock_info.n_alarm = 0;
13328         bp->ptp_clock_info.n_ext_ts = 0;
13329         bp->ptp_clock_info.n_per_out = 0;
13330         bp->ptp_clock_info.pps = 0;
13331         bp->ptp_clock_info.adjfreq = bnx2x_ptp_adjfreq;
13332         bp->ptp_clock_info.adjtime = bnx2x_ptp_adjtime;
13333         bp->ptp_clock_info.gettime = bnx2x_ptp_gettime;
13334         bp->ptp_clock_info.settime = bnx2x_ptp_settime;
13335         bp->ptp_clock_info.enable = bnx2x_ptp_enable;
13336
13337         bp->ptp_clock = ptp_clock_register(&bp->ptp_clock_info, &bp->pdev->dev);
13338         if (IS_ERR(bp->ptp_clock)) {
13339                 bp->ptp_clock = NULL;
13340                 BNX2X_ERR("PTP clock registeration failed\n");
13341         }
13342 }
13343
13344 static int bnx2x_init_one(struct pci_dev *pdev,
13345                                     const struct pci_device_id *ent)
13346 {
13347         struct net_device *dev = NULL;
13348         struct bnx2x *bp;
13349         enum pcie_link_width pcie_width;
13350         enum pci_bus_speed pcie_speed;
13351         int rc, max_non_def_sbs;
13352         int rx_count, tx_count, rss_count, doorbell_size;
13353         int max_cos_est;
13354         bool is_vf;
13355         int cnic_cnt;
13356
13357         /* An estimated maximum supported CoS number according to the chip
13358          * version.
13359          * We will try to roughly estimate the maximum number of CoSes this chip
13360          * may support in order to minimize the memory allocated for Tx
13361          * netdev_queue's. This number will be accurately calculated during the
13362          * initialization of bp->max_cos based on the chip versions AND chip
13363          * revision in the bnx2x_init_bp().
13364          */
13365         max_cos_est = set_max_cos_est(ent->driver_data);
13366         if (max_cos_est < 0)
13367                 return max_cos_est;
13368         is_vf = set_is_vf(ent->driver_data);
13369         cnic_cnt = is_vf ? 0 : 1;
13370
13371         max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt);
13372
13373         /* add another SB for VF as it has no default SB */
13374         max_non_def_sbs += is_vf ? 1 : 0;
13375
13376         /* Maximum number of RSS queues: one IGU SB goes to CNIC */
13377         rss_count = max_non_def_sbs - cnic_cnt;
13378
13379         if (rss_count < 1)
13380                 return -EINVAL;
13381
13382         /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
13383         rx_count = rss_count + cnic_cnt;
13384
13385         /* Maximum number of netdev Tx queues:
13386          * Maximum TSS queues * Maximum supported number of CoS  + FCoE L2
13387          */
13388         tx_count = rss_count * max_cos_est + cnic_cnt;
13389
13390         /* dev zeroed in init_etherdev */
13391         dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
13392         if (!dev)
13393                 return -ENOMEM;
13394
13395         bp = netdev_priv(dev);
13396
13397         bp->flags = 0;
13398         if (is_vf)
13399                 bp->flags |= IS_VF_FLAG;
13400
13401         bp->igu_sb_cnt = max_non_def_sbs;
13402         bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
13403         bp->msg_enable = debug;
13404         bp->cnic_support = cnic_cnt;
13405         bp->cnic_probe = bnx2x_cnic_probe;
13406
13407         pci_set_drvdata(pdev, dev);
13408
13409         rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data);
13410         if (rc < 0) {
13411                 free_netdev(dev);
13412                 return rc;
13413         }
13414
13415         BNX2X_DEV_INFO("This is a %s function\n",
13416                        IS_PF(bp) ? "physical" : "virtual");
13417         BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off");
13418         BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs);
13419         BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
13420                        tx_count, rx_count);
13421
13422         rc = bnx2x_init_bp(bp);
13423         if (rc)
13424                 goto init_one_exit;
13425
13426         /* Map doorbells here as we need the real value of bp->max_cos which
13427          * is initialized in bnx2x_init_bp() to determine the number of
13428          * l2 connections.
13429          */
13430         if (IS_VF(bp)) {
13431                 bp->doorbells = bnx2x_vf_doorbells(bp);
13432                 rc = bnx2x_vf_pci_alloc(bp);
13433                 if (rc)
13434                         goto init_one_exit;
13435         } else {
13436                 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT);
13437                 if (doorbell_size > pci_resource_len(pdev, 2)) {
13438                         dev_err(&bp->pdev->dev,
13439                                 "Cannot map doorbells, bar size too small, aborting\n");
13440                         rc = -ENOMEM;
13441                         goto init_one_exit;
13442                 }
13443                 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
13444                                                 doorbell_size);
13445         }
13446         if (!bp->doorbells) {
13447                 dev_err(&bp->pdev->dev,
13448                         "Cannot map doorbell space, aborting\n");
13449                 rc = -ENOMEM;
13450                 goto init_one_exit;
13451         }
13452
13453         if (IS_VF(bp)) {
13454                 rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count);
13455                 if (rc)
13456                         goto init_one_exit;
13457         }
13458
13459         /* Enable SRIOV if capability found in configuration space */
13460         rc = bnx2x_iov_init_one(bp, int_mode, BNX2X_MAX_NUM_OF_VFS);
13461         if (rc)
13462                 goto init_one_exit;
13463
13464         /* calc qm_cid_count */
13465         bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
13466         BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count);
13467
13468         /* disable FCOE L2 queue for E1x*/
13469         if (CHIP_IS_E1x(bp))
13470                 bp->flags |= NO_FCOE_FLAG;
13471
13472         /* Set bp->num_queues for MSI-X mode*/
13473         bnx2x_set_num_queues(bp);
13474
13475         /* Configure interrupt mode: try to enable MSI-X/MSI if
13476          * needed.
13477          */
13478         rc = bnx2x_set_int_mode(bp);
13479         if (rc) {
13480                 dev_err(&pdev->dev, "Cannot set interrupts\n");
13481                 goto init_one_exit;
13482         }
13483         BNX2X_DEV_INFO("set interrupts successfully\n");
13484
13485         /* register the net device */
13486         rc = register_netdev(dev);
13487         if (rc) {
13488                 dev_err(&pdev->dev, "Cannot register net device\n");
13489                 goto init_one_exit;
13490         }
13491         BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name);
13492
13493         if (!NO_FCOE(bp)) {
13494                 /* Add storage MAC address */
13495                 rtnl_lock();
13496                 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
13497                 rtnl_unlock();
13498         }
13499         if (pcie_get_minimum_link(bp->pdev, &pcie_speed, &pcie_width) ||
13500             pcie_speed == PCI_SPEED_UNKNOWN ||
13501             pcie_width == PCIE_LNK_WIDTH_UNKNOWN)
13502                 BNX2X_DEV_INFO("Failed to determine PCI Express Bandwidth\n");
13503         else
13504                 BNX2X_DEV_INFO(
13505                        "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
13506                        board_info[ent->driver_data].name,
13507                        (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
13508                        pcie_width,
13509                        pcie_speed == PCIE_SPEED_2_5GT ? "2.5GHz" :
13510                        pcie_speed == PCIE_SPEED_5_0GT ? "5.0GHz" :
13511                        pcie_speed == PCIE_SPEED_8_0GT ? "8.0GHz" :
13512                        "Unknown",
13513                        dev->base_addr, bp->pdev->irq, dev->dev_addr);
13514
13515         bnx2x_register_phc(bp);
13516
13517         return 0;
13518
13519 init_one_exit:
13520         bnx2x_disable_pcie_error_reporting(bp);
13521
13522         if (bp->regview)
13523                 iounmap(bp->regview);
13524
13525         if (IS_PF(bp) && bp->doorbells)
13526                 iounmap(bp->doorbells);
13527
13528         free_netdev(dev);
13529
13530         if (atomic_read(&pdev->enable_cnt) == 1)
13531                 pci_release_regions(pdev);
13532
13533         pci_disable_device(pdev);
13534
13535         return rc;
13536 }
13537
13538 static void __bnx2x_remove(struct pci_dev *pdev,
13539                            struct net_device *dev,
13540                            struct bnx2x *bp,
13541                            bool remove_netdev)
13542 {
13543         if (bp->ptp_clock) {
13544                 ptp_clock_unregister(bp->ptp_clock);
13545                 bp->ptp_clock = NULL;
13546         }
13547
13548         /* Delete storage MAC address */
13549         if (!NO_FCOE(bp)) {
13550                 rtnl_lock();
13551                 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
13552                 rtnl_unlock();
13553         }
13554
13555 #ifdef BCM_DCBNL
13556         /* Delete app tlvs from dcbnl */
13557         bnx2x_dcbnl_update_applist(bp, true);
13558 #endif
13559
13560         if (IS_PF(bp) &&
13561             !BP_NOMCP(bp) &&
13562             (bp->flags & BC_SUPPORTS_RMMOD_CMD))
13563                 bnx2x_fw_command(bp, DRV_MSG_CODE_RMMOD, 0);
13564
13565         /* Close the interface - either directly or implicitly */
13566         if (remove_netdev) {
13567                 unregister_netdev(dev);
13568         } else {
13569                 rtnl_lock();
13570                 dev_close(dev);
13571                 rtnl_unlock();
13572         }
13573
13574         bnx2x_iov_remove_one(bp);
13575
13576         /* Power on: we can't let PCI layer write to us while we are in D3 */
13577         if (IS_PF(bp)) {
13578                 bnx2x_set_power_state(bp, PCI_D0);
13579
13580                 /* Set endianity registers to reset values in case next driver
13581                  * boots in different endianty environment.
13582                  */
13583                 bnx2x_reset_endianity(bp);
13584         }
13585
13586         /* Disable MSI/MSI-X */
13587         bnx2x_disable_msi(bp);
13588
13589         /* Power off */
13590         if (IS_PF(bp))
13591                 bnx2x_set_power_state(bp, PCI_D3hot);
13592
13593         /* Make sure RESET task is not scheduled before continuing */
13594         cancel_delayed_work_sync(&bp->sp_rtnl_task);
13595
13596         /* send message via vfpf channel to release the resources of this vf */
13597         if (IS_VF(bp))
13598                 bnx2x_vfpf_release(bp);
13599
13600         /* Assumes no further PCIe PM changes will occur */
13601         if (system_state == SYSTEM_POWER_OFF) {
13602                 pci_wake_from_d3(pdev, bp->wol);
13603                 pci_set_power_state(pdev, PCI_D3hot);
13604         }
13605
13606         bnx2x_disable_pcie_error_reporting(bp);
13607         if (remove_netdev) {
13608                 if (bp->regview)
13609                         iounmap(bp->regview);
13610
13611                 /* For vfs, doorbells are part of the regview and were unmapped
13612                  * along with it. FW is only loaded by PF.
13613                  */
13614                 if (IS_PF(bp)) {
13615                         if (bp->doorbells)
13616                                 iounmap(bp->doorbells);
13617
13618                         bnx2x_release_firmware(bp);
13619                 } else {
13620                         bnx2x_vf_pci_dealloc(bp);
13621                 }
13622                 bnx2x_free_mem_bp(bp);
13623
13624                 free_netdev(dev);
13625
13626                 if (atomic_read(&pdev->enable_cnt) == 1)
13627                         pci_release_regions(pdev);
13628
13629                 pci_disable_device(pdev);
13630         }
13631 }
13632
13633 static void bnx2x_remove_one(struct pci_dev *pdev)
13634 {
13635         struct net_device *dev = pci_get_drvdata(pdev);
13636         struct bnx2x *bp;
13637
13638         if (!dev) {
13639                 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
13640                 return;
13641         }
13642         bp = netdev_priv(dev);
13643
13644         __bnx2x_remove(pdev, dev, bp, true);
13645 }
13646
13647 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
13648 {
13649         bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;
13650
13651         bp->rx_mode = BNX2X_RX_MODE_NONE;
13652
13653         if (CNIC_LOADED(bp))
13654                 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
13655
13656         /* Stop Tx */
13657         bnx2x_tx_disable(bp);
13658         /* Delete all NAPI objects */
13659         bnx2x_del_all_napi(bp);
13660         if (CNIC_LOADED(bp))
13661                 bnx2x_del_all_napi_cnic(bp);
13662         netdev_reset_tc(bp->dev);
13663
13664         del_timer_sync(&bp->timer);
13665         cancel_delayed_work_sync(&bp->sp_task);
13666         cancel_delayed_work_sync(&bp->period_task);
13667
13668         spin_lock_bh(&bp->stats_lock);
13669         bp->stats_state = STATS_STATE_DISABLED;
13670         spin_unlock_bh(&bp->stats_lock);
13671
13672         bnx2x_save_statistics(bp);
13673
13674         netif_carrier_off(bp->dev);
13675
13676         return 0;
13677 }
13678
13679 /**
13680  * bnx2x_io_error_detected - called when PCI error is detected
13681  * @pdev: Pointer to PCI device
13682  * @state: The current pci connection state
13683  *
13684  * This function is called after a PCI bus error affecting
13685  * this device has been detected.
13686  */
13687 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
13688                                                 pci_channel_state_t state)
13689 {
13690         struct net_device *dev = pci_get_drvdata(pdev);
13691         struct bnx2x *bp = netdev_priv(dev);
13692
13693         rtnl_lock();
13694
13695         BNX2X_ERR("IO error detected\n");
13696
13697         netif_device_detach(dev);
13698
13699         if (state == pci_channel_io_perm_failure) {
13700                 rtnl_unlock();
13701                 return PCI_ERS_RESULT_DISCONNECT;
13702         }
13703
13704         if (netif_running(dev))
13705                 bnx2x_eeh_nic_unload(bp);
13706
13707         bnx2x_prev_path_mark_eeh(bp);
13708
13709         pci_disable_device(pdev);
13710
13711         rtnl_unlock();
13712
13713         /* Request a slot reset */
13714         return PCI_ERS_RESULT_NEED_RESET;
13715 }
13716
13717 /**
13718  * bnx2x_io_slot_reset - called after the PCI bus has been reset
13719  * @pdev: Pointer to PCI device
13720  *
13721  * Restart the card from scratch, as if from a cold-boot.
13722  */
13723 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
13724 {
13725         struct net_device *dev = pci_get_drvdata(pdev);
13726         struct bnx2x *bp = netdev_priv(dev);
13727         int i;
13728
13729         rtnl_lock();
13730         BNX2X_ERR("IO slot reset initializing...\n");
13731         if (pci_enable_device(pdev)) {
13732                 dev_err(&pdev->dev,
13733                         "Cannot re-enable PCI device after reset\n");
13734                 rtnl_unlock();
13735                 return PCI_ERS_RESULT_DISCONNECT;
13736         }
13737
13738         pci_set_master(pdev);
13739         pci_restore_state(pdev);
13740         pci_save_state(pdev);
13741
13742         if (netif_running(dev))
13743                 bnx2x_set_power_state(bp, PCI_D0);
13744
13745         if (netif_running(dev)) {
13746                 BNX2X_ERR("IO slot reset --> driver unload\n");
13747
13748                 /* MCP should have been reset; Need to wait for validity */
13749                 bnx2x_init_shmem(bp);
13750
13751                 if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
13752                         u32 v;
13753
13754                         v = SHMEM2_RD(bp,
13755                                       drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
13756                         SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
13757                                   v & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
13758                 }
13759                 bnx2x_drain_tx_queues(bp);
13760                 bnx2x_send_unload_req(bp, UNLOAD_RECOVERY);
13761                 bnx2x_netif_stop(bp, 1);
13762                 bnx2x_free_irq(bp);
13763
13764                 /* Report UNLOAD_DONE to MCP */
13765                 bnx2x_send_unload_done(bp, true);
13766
13767                 bp->sp_state = 0;
13768                 bp->port.pmf = 0;
13769
13770                 bnx2x_prev_unload(bp);
13771
13772                 /* We should have reseted the engine, so It's fair to
13773                  * assume the FW will no longer write to the bnx2x driver.
13774                  */
13775                 bnx2x_squeeze_objects(bp);
13776                 bnx2x_free_skbs(bp);
13777                 for_each_rx_queue(bp, i)
13778                         bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
13779                 bnx2x_free_fp_mem(bp);
13780                 bnx2x_free_mem(bp);
13781
13782                 bp->state = BNX2X_STATE_CLOSED;
13783         }
13784
13785         rtnl_unlock();
13786
13787         /* If AER, perform cleanup of the PCIe registers */
13788         if (bp->flags & AER_ENABLED) {
13789                 if (pci_cleanup_aer_uncorrect_error_status(pdev))
13790                         BNX2X_ERR("pci_cleanup_aer_uncorrect_error_status failed\n");
13791                 else
13792                         DP(NETIF_MSG_HW, "pci_cleanup_aer_uncorrect_error_status succeeded\n");
13793         }
13794
13795         return PCI_ERS_RESULT_RECOVERED;
13796 }
13797
13798 /**
13799  * bnx2x_io_resume - called when traffic can start flowing again
13800  * @pdev: Pointer to PCI device
13801  *
13802  * This callback is called when the error recovery driver tells us that
13803  * its OK to resume normal operation.
13804  */
13805 static void bnx2x_io_resume(struct pci_dev *pdev)
13806 {
13807         struct net_device *dev = pci_get_drvdata(pdev);
13808         struct bnx2x *bp = netdev_priv(dev);
13809
13810         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
13811                 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n");
13812                 return;
13813         }
13814
13815         rtnl_lock();
13816
13817         bp->fw_seq = SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
13818                                                         DRV_MSG_SEQ_NUMBER_MASK;
13819
13820         if (netif_running(dev))
13821                 bnx2x_nic_load(bp, LOAD_NORMAL);
13822
13823         netif_device_attach(dev);
13824
13825         rtnl_unlock();
13826 }
13827
13828 static const struct pci_error_handlers bnx2x_err_handler = {
13829         .error_detected = bnx2x_io_error_detected,
13830         .slot_reset     = bnx2x_io_slot_reset,
13831         .resume         = bnx2x_io_resume,
13832 };
13833
13834 static void bnx2x_shutdown(struct pci_dev *pdev)
13835 {
13836         struct net_device *dev = pci_get_drvdata(pdev);
13837         struct bnx2x *bp;
13838
13839         if (!dev)
13840                 return;
13841
13842         bp = netdev_priv(dev);
13843         if (!bp)
13844                 return;
13845
13846         rtnl_lock();
13847         netif_device_detach(dev);
13848         rtnl_unlock();
13849
13850         /* Don't remove the netdevice, as there are scenarios which will cause
13851          * the kernel to hang, e.g., when trying to remove bnx2i while the
13852          * rootfs is mounted from SAN.
13853          */
13854         __bnx2x_remove(pdev, dev, bp, false);
13855 }
13856
13857 static struct pci_driver bnx2x_pci_driver = {
13858         .name        = DRV_MODULE_NAME,
13859         .id_table    = bnx2x_pci_tbl,
13860         .probe       = bnx2x_init_one,
13861         .remove      = bnx2x_remove_one,
13862         .suspend     = bnx2x_suspend,
13863         .resume      = bnx2x_resume,
13864         .err_handler = &bnx2x_err_handler,
13865 #ifdef CONFIG_BNX2X_SRIOV
13866         .sriov_configure = bnx2x_sriov_configure,
13867 #endif
13868         .shutdown    = bnx2x_shutdown,
13869 };
13870
13871 static int __init bnx2x_init(void)
13872 {
13873         int ret;
13874
13875         pr_info("%s", version);
13876
13877         bnx2x_wq = create_singlethread_workqueue("bnx2x");
13878         if (bnx2x_wq == NULL) {
13879                 pr_err("Cannot create workqueue\n");
13880                 return -ENOMEM;
13881         }
13882         bnx2x_iov_wq = create_singlethread_workqueue("bnx2x_iov");
13883         if (!bnx2x_iov_wq) {
13884                 pr_err("Cannot create iov workqueue\n");
13885                 destroy_workqueue(bnx2x_wq);
13886                 return -ENOMEM;
13887         }
13888
13889         ret = pci_register_driver(&bnx2x_pci_driver);
13890         if (ret) {
13891                 pr_err("Cannot register driver\n");
13892                 destroy_workqueue(bnx2x_wq);
13893                 destroy_workqueue(bnx2x_iov_wq);
13894         }
13895         return ret;
13896 }
13897
13898 static void __exit bnx2x_cleanup(void)
13899 {
13900         struct list_head *pos, *q;
13901
13902         pci_unregister_driver(&bnx2x_pci_driver);
13903
13904         destroy_workqueue(bnx2x_wq);
13905         destroy_workqueue(bnx2x_iov_wq);
13906
13907         /* Free globally allocated resources */
13908         list_for_each_safe(pos, q, &bnx2x_prev_list) {
13909                 struct bnx2x_prev_path_list *tmp =
13910                         list_entry(pos, struct bnx2x_prev_path_list, list);
13911                 list_del(pos);
13912                 kfree(tmp);
13913         }
13914 }
13915
13916 void bnx2x_notify_link_changed(struct bnx2x *bp)
13917 {
13918         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
13919 }
13920
13921 module_init(bnx2x_init);
13922 module_exit(bnx2x_cleanup);
13923
13924 /**
13925  * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
13926  *
13927  * @bp:         driver handle
13928  * @set:        set or clear the CAM entry
13929  *
13930  * This function will wait until the ramrod completion returns.
13931  * Return 0 if success, -ENODEV if ramrod doesn't return.
13932  */
13933 static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
13934 {
13935         unsigned long ramrod_flags = 0;
13936
13937         __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
13938         return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
13939                                  &bp->iscsi_l2_mac_obj, true,
13940                                  BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
13941 }
13942
13943 /* count denotes the number of new completions we have seen */
13944 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
13945 {
13946         struct eth_spe *spe;
13947         int cxt_index, cxt_offset;
13948
13949 #ifdef BNX2X_STOP_ON_ERROR
13950         if (unlikely(bp->panic))
13951                 return;
13952 #endif
13953
13954         spin_lock_bh(&bp->spq_lock);
13955         BUG_ON(bp->cnic_spq_pending < count);
13956         bp->cnic_spq_pending -= count;
13957
13958         for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
13959                 u16 type =  (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
13960                                 & SPE_HDR_CONN_TYPE) >>
13961                                 SPE_HDR_CONN_TYPE_SHIFT;
13962                 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
13963                                 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
13964
13965                 /* Set validation for iSCSI L2 client before sending SETUP
13966                  *  ramrod
13967                  */
13968                 if (type == ETH_CONNECTION_TYPE) {
13969                         if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) {
13970                                 cxt_index = BNX2X_ISCSI_ETH_CID(bp) /
13971                                         ILT_PAGE_CIDS;
13972                                 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) -
13973                                         (cxt_index * ILT_PAGE_CIDS);
13974                                 bnx2x_set_ctx_validation(bp,
13975                                         &bp->context[cxt_index].
13976                                                          vcxt[cxt_offset].eth,
13977                                         BNX2X_ISCSI_ETH_CID(bp));
13978                         }
13979                 }
13980
13981                 /*
13982                  * There may be not more than 8 L2, not more than 8 L5 SPEs
13983                  * and in the air. We also check that number of outstanding
13984                  * COMMON ramrods is not more than the EQ and SPQ can
13985                  * accommodate.
13986                  */
13987                 if (type == ETH_CONNECTION_TYPE) {
13988                         if (!atomic_read(&bp->cq_spq_left))
13989                                 break;
13990                         else
13991                                 atomic_dec(&bp->cq_spq_left);
13992                 } else if (type == NONE_CONNECTION_TYPE) {
13993                         if (!atomic_read(&bp->eq_spq_left))
13994                                 break;
13995                         else
13996                                 atomic_dec(&bp->eq_spq_left);
13997                 } else if ((type == ISCSI_CONNECTION_TYPE) ||
13998                            (type == FCOE_CONNECTION_TYPE)) {
13999                         if (bp->cnic_spq_pending >=
14000                             bp->cnic_eth_dev.max_kwqe_pending)
14001                                 break;
14002                         else
14003                                 bp->cnic_spq_pending++;
14004                 } else {
14005                         BNX2X_ERR("Unknown SPE type: %d\n", type);
14006                         bnx2x_panic();
14007                         break;
14008                 }
14009
14010                 spe = bnx2x_sp_get_next(bp);
14011                 *spe = *bp->cnic_kwq_cons;
14012
14013                 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n",
14014                    bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
14015
14016                 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
14017                         bp->cnic_kwq_cons = bp->cnic_kwq;
14018                 else
14019                         bp->cnic_kwq_cons++;
14020         }
14021         bnx2x_sp_prod_update(bp);
14022         spin_unlock_bh(&bp->spq_lock);
14023 }
14024
14025 static int bnx2x_cnic_sp_queue(struct net_device *dev,
14026                                struct kwqe_16 *kwqes[], u32 count)
14027 {
14028         struct bnx2x *bp = netdev_priv(dev);
14029         int i;
14030
14031 #ifdef BNX2X_STOP_ON_ERROR
14032         if (unlikely(bp->panic)) {
14033                 BNX2X_ERR("Can't post to SP queue while panic\n");
14034                 return -EIO;
14035         }
14036 #endif
14037
14038         if ((bp->recovery_state != BNX2X_RECOVERY_DONE) &&
14039             (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
14040                 BNX2X_ERR("Handling parity error recovery. Try again later\n");
14041                 return -EAGAIN;
14042         }
14043
14044         spin_lock_bh(&bp->spq_lock);
14045
14046         for (i = 0; i < count; i++) {
14047                 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
14048
14049                 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
14050                         break;
14051
14052                 *bp->cnic_kwq_prod = *spe;
14053
14054                 bp->cnic_kwq_pending++;
14055
14056                 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n",
14057                    spe->hdr.conn_and_cmd_data, spe->hdr.type,
14058                    spe->data.update_data_addr.hi,
14059                    spe->data.update_data_addr.lo,
14060                    bp->cnic_kwq_pending);
14061
14062                 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
14063                         bp->cnic_kwq_prod = bp->cnic_kwq;
14064                 else
14065                         bp->cnic_kwq_prod++;
14066         }
14067
14068         spin_unlock_bh(&bp->spq_lock);
14069
14070         if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
14071                 bnx2x_cnic_sp_post(bp, 0);
14072
14073         return i;
14074 }
14075
14076 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
14077 {
14078         struct cnic_ops *c_ops;
14079         int rc = 0;
14080
14081         mutex_lock(&bp->cnic_mutex);
14082         c_ops = rcu_dereference_protected(bp->cnic_ops,
14083                                           lockdep_is_held(&bp->cnic_mutex));
14084         if (c_ops)
14085                 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
14086         mutex_unlock(&bp->cnic_mutex);
14087
14088         return rc;
14089 }
14090
14091 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
14092 {
14093         struct cnic_ops *c_ops;
14094         int rc = 0;
14095
14096         rcu_read_lock();
14097         c_ops = rcu_dereference(bp->cnic_ops);
14098         if (c_ops)
14099                 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
14100         rcu_read_unlock();
14101
14102         return rc;
14103 }
14104
14105 /*
14106  * for commands that have no data
14107  */
14108 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
14109 {
14110         struct cnic_ctl_info ctl = {0};
14111
14112         ctl.cmd = cmd;
14113
14114         return bnx2x_cnic_ctl_send(bp, &ctl);
14115 }
14116
14117 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
14118 {
14119         struct cnic_ctl_info ctl = {0};
14120
14121         /* first we tell CNIC and only then we count this as a completion */
14122         ctl.cmd = CNIC_CTL_COMPLETION_CMD;
14123         ctl.data.comp.cid = cid;
14124         ctl.data.comp.error = err;
14125
14126         bnx2x_cnic_ctl_send_bh(bp, &ctl);
14127         bnx2x_cnic_sp_post(bp, 0);
14128 }
14129
14130 /* Called with netif_addr_lock_bh() taken.
14131  * Sets an rx_mode config for an iSCSI ETH client.
14132  * Doesn't block.
14133  * Completion should be checked outside.
14134  */
14135 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
14136 {
14137         unsigned long accept_flags = 0, ramrod_flags = 0;
14138         u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
14139         int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
14140
14141         if (start) {
14142                 /* Start accepting on iSCSI L2 ring. Accept all multicasts
14143                  * because it's the only way for UIO Queue to accept
14144                  * multicasts (in non-promiscuous mode only one Queue per
14145                  * function will receive multicast packets (leading in our
14146                  * case).
14147                  */
14148                 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
14149                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
14150                 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
14151                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
14152
14153                 /* Clear STOP_PENDING bit if START is requested */
14154                 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
14155
14156                 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
14157         } else
14158                 /* Clear START_PENDING bit if STOP is requested */
14159                 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
14160
14161         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
14162                 set_bit(sched_state, &bp->sp_state);
14163         else {
14164                 __set_bit(RAMROD_RX, &ramrod_flags);
14165                 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
14166                                     ramrod_flags);
14167         }
14168 }
14169
14170 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
14171 {
14172         struct bnx2x *bp = netdev_priv(dev);
14173         int rc = 0;
14174
14175         switch (ctl->cmd) {
14176         case DRV_CTL_CTXTBL_WR_CMD: {
14177                 u32 index = ctl->data.io.offset;
14178                 dma_addr_t addr = ctl->data.io.dma_addr;
14179
14180                 bnx2x_ilt_wr(bp, index, addr);
14181                 break;
14182         }
14183
14184         case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
14185                 int count = ctl->data.credit.credit_count;
14186
14187                 bnx2x_cnic_sp_post(bp, count);
14188                 break;
14189         }
14190
14191         /* rtnl_lock is held.  */
14192         case DRV_CTL_START_L2_CMD: {
14193                 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14194                 unsigned long sp_bits = 0;
14195
14196                 /* Configure the iSCSI classification object */
14197                 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
14198                                    cp->iscsi_l2_client_id,
14199                                    cp->iscsi_l2_cid, BP_FUNC(bp),
14200                                    bnx2x_sp(bp, mac_rdata),
14201                                    bnx2x_sp_mapping(bp, mac_rdata),
14202                                    BNX2X_FILTER_MAC_PENDING,
14203                                    &bp->sp_state, BNX2X_OBJ_TYPE_RX,
14204                                    &bp->macs_pool);
14205
14206                 /* Set iSCSI MAC address */
14207                 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
14208                 if (rc)
14209                         break;
14210
14211                 mmiowb();
14212                 barrier();
14213
14214                 /* Start accepting on iSCSI L2 ring */
14215
14216                 netif_addr_lock_bh(dev);
14217                 bnx2x_set_iscsi_eth_rx_mode(bp, true);
14218                 netif_addr_unlock_bh(dev);
14219
14220                 /* bits to wait on */
14221                 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
14222                 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
14223
14224                 if (!bnx2x_wait_sp_comp(bp, sp_bits))
14225                         BNX2X_ERR("rx_mode completion timed out!\n");
14226
14227                 break;
14228         }
14229
14230         /* rtnl_lock is held.  */
14231         case DRV_CTL_STOP_L2_CMD: {
14232                 unsigned long sp_bits = 0;
14233
14234                 /* Stop accepting on iSCSI L2 ring */
14235                 netif_addr_lock_bh(dev);
14236                 bnx2x_set_iscsi_eth_rx_mode(bp, false);
14237                 netif_addr_unlock_bh(dev);
14238
14239                 /* bits to wait on */
14240                 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
14241                 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
14242
14243                 if (!bnx2x_wait_sp_comp(bp, sp_bits))
14244                         BNX2X_ERR("rx_mode completion timed out!\n");
14245
14246                 mmiowb();
14247                 barrier();
14248
14249                 /* Unset iSCSI L2 MAC */
14250                 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
14251                                         BNX2X_ISCSI_ETH_MAC, true);
14252                 break;
14253         }
14254         case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
14255                 int count = ctl->data.credit.credit_count;
14256
14257                 smp_mb__before_atomic();
14258                 atomic_add(count, &bp->cq_spq_left);
14259                 smp_mb__after_atomic();
14260                 break;
14261         }
14262         case DRV_CTL_ULP_REGISTER_CMD: {
14263                 int ulp_type = ctl->data.register_data.ulp_type;
14264
14265                 if (CHIP_IS_E3(bp)) {
14266                         int idx = BP_FW_MB_IDX(bp);
14267                         u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
14268                         int path = BP_PATH(bp);
14269                         int port = BP_PORT(bp);
14270                         int i;
14271                         u32 scratch_offset;
14272                         u32 *host_addr;
14273
14274                         /* first write capability to shmem2 */
14275                         if (ulp_type == CNIC_ULP_ISCSI)
14276                                 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
14277                         else if (ulp_type == CNIC_ULP_FCOE)
14278                                 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
14279                         SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
14280
14281                         if ((ulp_type != CNIC_ULP_FCOE) ||
14282                             (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) ||
14283                             (!(bp->flags &  BC_SUPPORTS_FCOE_FEATURES)))
14284                                 break;
14285
14286                         /* if reached here - should write fcoe capabilities */
14287                         scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr);
14288                         if (!scratch_offset)
14289                                 break;
14290                         scratch_offset += offsetof(struct glob_ncsi_oem_data,
14291                                                    fcoe_features[path][port]);
14292                         host_addr = (u32 *) &(ctl->data.register_data.
14293                                               fcoe_features);
14294                         for (i = 0; i < sizeof(struct fcoe_capabilities);
14295                              i += 4)
14296                                 REG_WR(bp, scratch_offset + i,
14297                                        *(host_addr + i/4));
14298                 }
14299                 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14300                 break;
14301         }
14302
14303         case DRV_CTL_ULP_UNREGISTER_CMD: {
14304                 int ulp_type = ctl->data.ulp_type;
14305
14306                 if (CHIP_IS_E3(bp)) {
14307                         int idx = BP_FW_MB_IDX(bp);
14308                         u32 cap;
14309
14310                         cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
14311                         if (ulp_type == CNIC_ULP_ISCSI)
14312                                 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
14313                         else if (ulp_type == CNIC_ULP_FCOE)
14314                                 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
14315                         SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
14316                 }
14317                 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14318                 break;
14319         }
14320
14321         default:
14322                 BNX2X_ERR("unknown command %x\n", ctl->cmd);
14323                 rc = -EINVAL;
14324         }
14325
14326         return rc;
14327 }
14328
14329 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
14330 {
14331         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14332
14333         if (bp->flags & USING_MSIX_FLAG) {
14334                 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
14335                 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
14336                 cp->irq_arr[0].vector = bp->msix_table[1].vector;
14337         } else {
14338                 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
14339                 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
14340         }
14341         if (!CHIP_IS_E1x(bp))
14342                 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
14343         else
14344                 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
14345
14346         cp->irq_arr[0].status_blk_num =  bnx2x_cnic_fw_sb_id(bp);
14347         cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
14348         cp->irq_arr[1].status_blk = bp->def_status_blk;
14349         cp->irq_arr[1].status_blk_num = DEF_SB_ID;
14350         cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
14351
14352         cp->num_irq = 2;
14353 }
14354
14355 void bnx2x_setup_cnic_info(struct bnx2x *bp)
14356 {
14357         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14358
14359         cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
14360                              bnx2x_cid_ilt_lines(bp);
14361         cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
14362         cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
14363         cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
14364
14365         DP(NETIF_MSG_IFUP, "BNX2X_1st_NON_L2_ETH_CID(bp) %x, cp->starting_cid %x, cp->fcoe_init_cid %x, cp->iscsi_l2_cid %x\n",
14366            BNX2X_1st_NON_L2_ETH_CID(bp), cp->starting_cid, cp->fcoe_init_cid,
14367            cp->iscsi_l2_cid);
14368
14369         if (NO_ISCSI_OOO(bp))
14370                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
14371 }
14372
14373 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
14374                                void *data)
14375 {
14376         struct bnx2x *bp = netdev_priv(dev);
14377         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14378         int rc;
14379
14380         DP(NETIF_MSG_IFUP, "Register_cnic called\n");
14381
14382         if (ops == NULL) {
14383                 BNX2X_ERR("NULL ops received\n");
14384                 return -EINVAL;
14385         }
14386
14387         if (!CNIC_SUPPORT(bp)) {
14388                 BNX2X_ERR("Can't register CNIC when not supported\n");
14389                 return -EOPNOTSUPP;
14390         }
14391
14392         if (!CNIC_LOADED(bp)) {
14393                 rc = bnx2x_load_cnic(bp);
14394                 if (rc) {
14395                         BNX2X_ERR("CNIC-related load failed\n");
14396                         return rc;
14397                 }
14398         }
14399
14400         bp->cnic_enabled = true;
14401
14402         bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
14403         if (!bp->cnic_kwq)
14404                 return -ENOMEM;
14405
14406         bp->cnic_kwq_cons = bp->cnic_kwq;
14407         bp->cnic_kwq_prod = bp->cnic_kwq;
14408         bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
14409
14410         bp->cnic_spq_pending = 0;
14411         bp->cnic_kwq_pending = 0;
14412
14413         bp->cnic_data = data;
14414
14415         cp->num_irq = 0;
14416         cp->drv_state |= CNIC_DRV_STATE_REGD;
14417         cp->iro_arr = bp->iro_arr;
14418
14419         bnx2x_setup_cnic_irq_info(bp);
14420
14421         rcu_assign_pointer(bp->cnic_ops, ops);
14422
14423         /* Schedule driver to read CNIC driver versions */
14424         bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14425
14426         return 0;
14427 }
14428
14429 static int bnx2x_unregister_cnic(struct net_device *dev)
14430 {
14431         struct bnx2x *bp = netdev_priv(dev);
14432         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14433
14434         mutex_lock(&bp->cnic_mutex);
14435         cp->drv_state = 0;
14436         RCU_INIT_POINTER(bp->cnic_ops, NULL);
14437         mutex_unlock(&bp->cnic_mutex);
14438         synchronize_rcu();
14439         bp->cnic_enabled = false;
14440         kfree(bp->cnic_kwq);
14441         bp->cnic_kwq = NULL;
14442
14443         return 0;
14444 }
14445
14446 static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
14447 {
14448         struct bnx2x *bp = netdev_priv(dev);
14449         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14450
14451         /* If both iSCSI and FCoE are disabled - return NULL in
14452          * order to indicate CNIC that it should not try to work
14453          * with this device.
14454          */
14455         if (NO_ISCSI(bp) && NO_FCOE(bp))
14456                 return NULL;
14457
14458         cp->drv_owner = THIS_MODULE;
14459         cp->chip_id = CHIP_ID(bp);
14460         cp->pdev = bp->pdev;
14461         cp->io_base = bp->regview;
14462         cp->io_base2 = bp->doorbells;
14463         cp->max_kwqe_pending = 8;
14464         cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
14465         cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
14466                              bnx2x_cid_ilt_lines(bp);
14467         cp->ctx_tbl_len = CNIC_ILT_LINES;
14468         cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
14469         cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
14470         cp->drv_ctl = bnx2x_drv_ctl;
14471         cp->drv_register_cnic = bnx2x_register_cnic;
14472         cp->drv_unregister_cnic = bnx2x_unregister_cnic;
14473         cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
14474         cp->iscsi_l2_client_id =
14475                 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
14476         cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
14477
14478         if (NO_ISCSI_OOO(bp))
14479                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
14480
14481         if (NO_ISCSI(bp))
14482                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
14483
14484         if (NO_FCOE(bp))
14485                 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
14486
14487         BNX2X_DEV_INFO(
14488                 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
14489            cp->ctx_blk_size,
14490            cp->ctx_tbl_offset,
14491            cp->ctx_tbl_len,
14492            cp->starting_cid);
14493         return cp;
14494 }
14495
14496 static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp)
14497 {
14498         struct bnx2x *bp = fp->bp;
14499         u32 offset = BAR_USTRORM_INTMEM;
14500
14501         if (IS_VF(bp))
14502                 return bnx2x_vf_ustorm_prods_offset(bp, fp);
14503         else if (!CHIP_IS_E1x(bp))
14504                 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
14505         else
14506                 offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id);
14507
14508         return offset;
14509 }
14510
14511 /* called only on E1H or E2.
14512  * When pretending to be PF, the pretend value is the function number 0...7
14513  * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
14514  * combination
14515  */
14516 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val)
14517 {
14518         u32 pretend_reg;
14519
14520         if (CHIP_IS_E1H(bp) && pretend_func_val >= E1H_FUNC_MAX)
14521                 return -1;
14522
14523         /* get my own pretend register */
14524         pretend_reg = bnx2x_get_pretend_reg(bp);
14525         REG_WR(bp, pretend_reg, pretend_func_val);
14526         REG_RD(bp, pretend_reg);
14527         return 0;
14528 }
14529
14530 static void bnx2x_ptp_task(struct work_struct *work)
14531 {
14532         struct bnx2x *bp = container_of(work, struct bnx2x, ptp_task);
14533         int port = BP_PORT(bp);
14534         u32 val_seq;
14535         u64 timestamp, ns;
14536         struct skb_shared_hwtstamps shhwtstamps;
14537
14538         /* Read Tx timestamp registers */
14539         val_seq = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
14540                          NIG_REG_P0_TLLH_PTP_BUF_SEQID);
14541         if (val_seq & 0x10000) {
14542                 /* There is a valid timestamp value */
14543                 timestamp = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_MSB :
14544                                    NIG_REG_P0_TLLH_PTP_BUF_TS_MSB);
14545                 timestamp <<= 32;
14546                 timestamp |= REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_LSB :
14547                                     NIG_REG_P0_TLLH_PTP_BUF_TS_LSB);
14548                 /* Reset timestamp register to allow new timestamp */
14549                 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
14550                        NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000);
14551                 ns = timecounter_cyc2time(&bp->timecounter, timestamp);
14552
14553                 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
14554                 shhwtstamps.hwtstamp = ns_to_ktime(ns);
14555                 skb_tstamp_tx(bp->ptp_tx_skb, &shhwtstamps);
14556                 dev_kfree_skb_any(bp->ptp_tx_skb);
14557                 bp->ptp_tx_skb = NULL;
14558
14559                 DP(BNX2X_MSG_PTP, "Tx timestamp, timestamp cycles = %llu, ns = %llu\n",
14560                    timestamp, ns);
14561         } else {
14562                 DP(BNX2X_MSG_PTP, "There is no valid Tx timestamp yet\n");
14563                 /* Reschedule to keep checking for a valid timestamp value */
14564                 schedule_work(&bp->ptp_task);
14565         }
14566 }
14567
14568 void bnx2x_set_rx_ts(struct bnx2x *bp, struct sk_buff *skb)
14569 {
14570         int port = BP_PORT(bp);
14571         u64 timestamp, ns;
14572
14573         timestamp = REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_MSB :
14574                             NIG_REG_P0_LLH_PTP_HOST_BUF_TS_MSB);
14575         timestamp <<= 32;
14576         timestamp |= REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_LSB :
14577                             NIG_REG_P0_LLH_PTP_HOST_BUF_TS_LSB);
14578
14579         /* Reset timestamp register to allow new timestamp */
14580         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID :
14581                NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000);
14582
14583         ns = timecounter_cyc2time(&bp->timecounter, timestamp);
14584
14585         skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(ns);
14586
14587         DP(BNX2X_MSG_PTP, "Rx timestamp, timestamp cycles = %llu, ns = %llu\n",
14588            timestamp, ns);
14589 }
14590
14591 /* Read the PHC */
14592 static cycle_t bnx2x_cyclecounter_read(const struct cyclecounter *cc)
14593 {
14594         struct bnx2x *bp = container_of(cc, struct bnx2x, cyclecounter);
14595         int port = BP_PORT(bp);
14596         u32 wb_data[2];
14597         u64 phc_cycles;
14598
14599         REG_RD_DMAE(bp, port ? NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t1 :
14600                     NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t0, wb_data, 2);
14601         phc_cycles = wb_data[1];
14602         phc_cycles = (phc_cycles << 32) + wb_data[0];
14603
14604         DP(BNX2X_MSG_PTP, "PHC read cycles = %llu\n", phc_cycles);
14605
14606         return phc_cycles;
14607 }
14608
14609 static void bnx2x_init_cyclecounter(struct bnx2x *bp)
14610 {
14611         memset(&bp->cyclecounter, 0, sizeof(bp->cyclecounter));
14612         bp->cyclecounter.read = bnx2x_cyclecounter_read;
14613         bp->cyclecounter.mask = CLOCKSOURCE_MASK(64);
14614         bp->cyclecounter.shift = 1;
14615         bp->cyclecounter.mult = 1;
14616 }
14617
14618 static int bnx2x_send_reset_timesync_ramrod(struct bnx2x *bp)
14619 {
14620         struct bnx2x_func_state_params func_params = {NULL};
14621         struct bnx2x_func_set_timesync_params *set_timesync_params =
14622                 &func_params.params.set_timesync;
14623
14624         /* Prepare parameters for function state transitions */
14625         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
14626         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
14627
14628         func_params.f_obj = &bp->func_obj;
14629         func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC;
14630
14631         /* Function parameters */
14632         set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_RESET;
14633         set_timesync_params->offset_cmd = TS_OFFSET_KEEP;
14634
14635         return bnx2x_func_state_change(bp, &func_params);
14636 }
14637
14638 int bnx2x_enable_ptp_packets(struct bnx2x *bp)
14639 {
14640         struct bnx2x_queue_state_params q_params;
14641         int rc, i;
14642
14643         /* send queue update ramrod to enable PTP packets */
14644         memset(&q_params, 0, sizeof(q_params));
14645         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
14646         q_params.cmd = BNX2X_Q_CMD_UPDATE;
14647         __set_bit(BNX2X_Q_UPDATE_PTP_PKTS_CHNG,
14648                   &q_params.params.update.update_flags);
14649         __set_bit(BNX2X_Q_UPDATE_PTP_PKTS,
14650                   &q_params.params.update.update_flags);
14651
14652         /* send the ramrod on all the queues of the PF */
14653         for_each_eth_queue(bp, i) {
14654                 struct bnx2x_fastpath *fp = &bp->fp[i];
14655
14656                 /* Set the appropriate Queue object */
14657                 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
14658
14659                 /* Update the Queue state */
14660                 rc = bnx2x_queue_state_change(bp, &q_params);
14661                 if (rc) {
14662                         BNX2X_ERR("Failed to enable PTP packets\n");
14663                         return rc;
14664                 }
14665         }
14666
14667         return 0;
14668 }
14669
14670 int bnx2x_configure_ptp_filters(struct bnx2x *bp)
14671 {
14672         int port = BP_PORT(bp);
14673         int rc;
14674
14675         if (!bp->hwtstamp_ioctl_called)
14676                 return 0;
14677
14678         switch (bp->tx_type) {
14679         case HWTSTAMP_TX_ON:
14680                 bp->flags |= TX_TIMESTAMPING_EN;
14681                 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
14682                        NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x6AA);
14683                 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
14684                        NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3EEE);
14685                 break;
14686         case HWTSTAMP_TX_ONESTEP_SYNC:
14687                 BNX2X_ERR("One-step timestamping is not supported\n");
14688                 return -ERANGE;
14689         }
14690
14691         switch (bp->rx_filter) {
14692         case HWTSTAMP_FILTER_NONE:
14693                 break;
14694         case HWTSTAMP_FILTER_ALL:
14695         case HWTSTAMP_FILTER_SOME:
14696                 bp->rx_filter = HWTSTAMP_FILTER_NONE;
14697                 break;
14698         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
14699         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
14700         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
14701                 bp->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
14702                 /* Initialize PTP detection for UDP/IPv4 events */
14703                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14704                        NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EE);
14705                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14706                        NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFE);
14707                 break;
14708         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
14709         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
14710         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
14711                 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
14712                 /* Initialize PTP detection for UDP/IPv4 or UDP/IPv6 events */
14713                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14714                        NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EA);
14715                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14716                        NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FEE);
14717                 break;
14718         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
14719         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
14720         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
14721                 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
14722                 /* Initialize PTP detection L2 events */
14723                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14724                        NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6BF);
14725                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14726                        NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EFF);
14727
14728                 break;
14729         case HWTSTAMP_FILTER_PTP_V2_EVENT:
14730         case HWTSTAMP_FILTER_PTP_V2_SYNC:
14731         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
14732                 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
14733                 /* Initialize PTP detection L2, UDP/IPv4 or UDP/IPv6 events */
14734                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14735                        NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6AA);
14736                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14737                        NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EEE);
14738                 break;
14739         }
14740
14741         /* Indicate to FW that this PF expects recorded PTP packets */
14742         rc = bnx2x_enable_ptp_packets(bp);
14743         if (rc)
14744                 return rc;
14745
14746         /* Enable sending PTP packets to host */
14747         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
14748                NIG_REG_P0_LLH_PTP_TO_HOST, 0x1);
14749
14750         return 0;
14751 }
14752
14753 static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr)
14754 {
14755         struct hwtstamp_config config;
14756         int rc;
14757
14758         DP(BNX2X_MSG_PTP, "HWTSTAMP IOCTL called\n");
14759
14760         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
14761                 return -EFAULT;
14762
14763         DP(BNX2X_MSG_PTP, "Requested tx_type: %d, requested rx_filters = %d\n",
14764            config.tx_type, config.rx_filter);
14765
14766         if (config.flags) {
14767                 BNX2X_ERR("config.flags is reserved for future use\n");
14768                 return -EINVAL;
14769         }
14770
14771         bp->hwtstamp_ioctl_called = 1;
14772         bp->tx_type = config.tx_type;
14773         bp->rx_filter = config.rx_filter;
14774
14775         rc = bnx2x_configure_ptp_filters(bp);
14776         if (rc)
14777                 return rc;
14778
14779         config.rx_filter = bp->rx_filter;
14780
14781         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
14782                 -EFAULT : 0;
14783 }
14784
14785 /* Configrues HW for PTP */
14786 static int bnx2x_configure_ptp(struct bnx2x *bp)
14787 {
14788         int rc, port = BP_PORT(bp);
14789         u32 wb_data[2];
14790
14791         /* Reset PTP event detection rules - will be configured in the IOCTL */
14792         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14793                NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF);
14794         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14795                NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF);
14796         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
14797                NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF);
14798         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
14799                NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF);
14800
14801         /* Disable PTP packets to host - will be configured in the IOCTL*/
14802         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
14803                NIG_REG_P0_LLH_PTP_TO_HOST, 0x0);
14804
14805         /* Enable the PTP feature */
14806         REG_WR(bp, port ? NIG_REG_P1_PTP_EN :
14807                NIG_REG_P0_PTP_EN, 0x3F);
14808
14809         /* Enable the free-running counter */
14810         wb_data[0] = 0;
14811         wb_data[1] = 0;
14812         REG_WR_DMAE(bp, NIG_REG_TIMESYNC_GEN_REG + tsgen_ctrl, wb_data, 2);
14813
14814         /* Reset drift register (offset register is not reset) */
14815         rc = bnx2x_send_reset_timesync_ramrod(bp);
14816         if (rc) {
14817                 BNX2X_ERR("Failed to reset PHC drift register\n");
14818                 return -EFAULT;
14819         }
14820
14821         /* Reset possibly old timestamps */
14822         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID :
14823                NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000);
14824         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
14825                NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000);
14826
14827         return 0;
14828 }
14829
14830 /* Called during load, to initialize PTP-related stuff */
14831 void bnx2x_init_ptp(struct bnx2x *bp)
14832 {
14833         int rc;
14834
14835         /* Configure PTP in HW */
14836         rc = bnx2x_configure_ptp(bp);
14837         if (rc) {
14838                 BNX2X_ERR("Stopping PTP initialization\n");
14839                 return;
14840         }
14841
14842         /* Init work queue for Tx timestamping */
14843         INIT_WORK(&bp->ptp_task, bnx2x_ptp_task);
14844
14845         /* Init cyclecounter and timecounter. This is done only in the first
14846          * load. If done in every load, PTP application will fail when doing
14847          * unload / load (e.g. MTU change) while it is running.
14848          */
14849         if (!bp->timecounter_init_done) {
14850                 bnx2x_init_cyclecounter(bp);
14851                 timecounter_init(&bp->timecounter, &bp->cyclecounter,
14852                                  ktime_to_ns(ktime_get_real()));
14853                 bp->timecounter_init_done = 1;
14854         }
14855
14856         DP(BNX2X_MSG_PTP, "PTP initialization ended successfully\n");
14857 }