drivers/net/ethernet/broadcom/bnxt/bnxt.c

   1 /* Broadcom NetXtreme-C/E network driver.
   2  *
   3  * Copyright (c) 2014-2015 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  */
   9
  10 #include <linux/module.h>
  11
  12 #include <linux/stringify.h>
  13 #include <linux/kernel.h>
  14 #include <linux/timer.h>
  15 #include <linux/errno.h>
  16 #include <linux/ioport.h>
  17 #include <linux/slab.h>
  18 #include <linux/vmalloc.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/pci.h>
  21 #include <linux/netdevice.h>
  22 #include <linux/etherdevice.h>
  23 #include <linux/skbuff.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/bitops.h>
  26 #include <linux/io.h>
  27 #include <linux/irq.h>
  28 #include <linux/delay.h>
  29 #include <asm/byteorder.h>
  30 #include <asm/page.h>
  31 #include <linux/time.h>
  32 #include <linux/mii.h>
  33 #include <linux/if.h>
  34 #include <linux/if_vlan.h>
  35 #include <net/ip.h>
  36 #include <net/tcp.h>
  37 #include <net/udp.h>
  38 #include <net/checksum.h>
  39 #include <net/ip6_checksum.h>
  40 #if defined(CONFIG_VXLAN) || defined(CONFIG_VXLAN_MODULE)
  41 #include <net/vxlan.h>
  42 #endif
  43 #ifdef CONFIG_NET_RX_BUSY_POLL
  44 #include <net/busy_poll.h>
  45 #endif
  46 #include <linux/workqueue.h>
  47 #include <linux/prefetch.h>
  48 #include <linux/cache.h>
  49 #include <linux/log2.h>
  50 #include <linux/aer.h>
  51 #include <linux/bitmap.h>
  52 #include <linux/cpu_rmap.h>
  53
  54 #include "bnxt_hsi.h"
  55 #include "bnxt.h"
  56 #include "bnxt_sriov.h"
  57 #include "bnxt_ethtool.h"
  58
  59 #define BNXT_TX_TIMEOUT         (5 * HZ)
  60
  61 static const char version[] =
  62         "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION "\n";
  63
  64 MODULE_LICENSE("GPL");
  65 MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
  66 MODULE_VERSION(DRV_MODULE_VERSION);
  67
  68 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
  69 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD
  70 #define BNXT_RX_COPY_THRESH 256
  71
  72 #define BNXT_TX_PUSH_THRESH 164
  73
  74 enum board_idx {
  75         BCM57301,
  76         BCM57302,
  77         BCM57304,
  78         BCM57402,
  79         BCM57404,
  80         BCM57406,
  81         BCM57304_VF,
  82         BCM57404_VF,
  83 };
  84
  85 /* indexed by enum above */
  86 static const struct {
  87         char *name;
  88 } board_info[] = {
  89         { "Broadcom BCM57301 NetXtreme-C Single-port 10Gb Ethernet" },
  90         { "Broadcom BCM57302 NetXtreme-C Dual-port 10Gb/25Gb Ethernet" },
  91         { "Broadcom BCM57304 NetXtreme-C Dual-port 10Gb/25Gb/40Gb/50Gb Ethernet" },
  92         { "Broadcom BCM57402 NetXtreme-E Dual-port 10Gb Ethernet" },
  93         { "Broadcom BCM57404 NetXtreme-E Dual-port 10Gb/25Gb Ethernet" },
  94         { "Broadcom BCM57406 NetXtreme-E Dual-port 10GBase-T Ethernet" },
  95         { "Broadcom BCM57304 NetXtreme-C Ethernet Virtual Function" },
  96         { "Broadcom BCM57404 NetXtreme-E Ethernet Virtual Function" },
  97 };
  98
  99 static const struct pci_device_id bnxt_pci_tbl[] = {
 100         { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 },
 101         { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 },
 102         { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 },
 103         { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 },
 104         { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 },
 105         { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 },
 106 #ifdef CONFIG_BNXT_SRIOV
 107         { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = BCM57304_VF },
 108         { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = BCM57404_VF },
 109 #endif
 110         { 0 }
 111 };
 112
 113 MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl);
 114
 115 static const u16 bnxt_vf_req_snif[] = {
 116         HWRM_FUNC_CFG,
 117         HWRM_PORT_PHY_QCFG,
 118         HWRM_CFA_L2_FILTER_ALLOC,
 119 };
 120
 121 static bool bnxt_vf_pciid(enum board_idx idx)
 122 {
 123         return (idx == BCM57304_VF || idx == BCM57404_VF);
 124 }
 125
 126 #define DB_CP_REARM_FLAGS       (DB_KEY_CP | DB_IDX_VALID)
 127 #define DB_CP_FLAGS             (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
 128 #define DB_CP_IRQ_DIS_FLAGS     (DB_KEY_CP | DB_IRQ_DIS)
 129
 130 #define BNXT_CP_DB_REARM(db, raw_cons)                                  \
 131                 writel(DB_CP_REARM_FLAGS | RING_CMP(raw_cons), db)
 132
 133 #define BNXT_CP_DB(db, raw_cons)                                        \
 134                 writel(DB_CP_FLAGS | RING_CMP(raw_cons), db)
 135
 136 #define BNXT_CP_DB_IRQ_DIS(db)                                          \
 137                 writel(DB_CP_IRQ_DIS_FLAGS, db)
 138
 139 static inline u32 bnxt_tx_avail(struct bnxt *bp, struct bnxt_tx_ring_info *txr)
 140 {
 141         /* Tell compiler to fetch tx indices from memory. */
 142         barrier();
 143
 144         return bp->tx_ring_size -
 145                 ((txr->tx_prod - txr->tx_cons) & bp->tx_ring_mask);
 146 }
 147
 148 static const u16 bnxt_lhint_arr[] = {
 149         TX_BD_FLAGS_LHINT_512_AND_SMALLER,
 150         TX_BD_FLAGS_LHINT_512_TO_1023,
 151         TX_BD_FLAGS_LHINT_1024_TO_2047,
 152         TX_BD_FLAGS_LHINT_1024_TO_2047,
 153         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 154         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 155         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 156         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 157         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 158         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 159         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 160         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 161         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 162         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 163         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 164         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 165         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 166         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 167         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 168 };
 169
 170 static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev)
 171 {
 172         struct bnxt *bp = netdev_priv(dev);
 173         struct tx_bd *txbd;
 174         struct tx_bd_ext *txbd1;
 175         struct netdev_queue *txq;
 176         int i;
 177         dma_addr_t mapping;
 178         unsigned int length, pad = 0;
 179         u32 len, free_size, vlan_tag_flags, cfa_action, flags;
 180         u16 prod, last_frag;
 181         struct pci_dev *pdev = bp->pdev;
 182         struct bnxt_tx_ring_info *txr;
 183         struct bnxt_sw_tx_bd *tx_buf;
 184
 185         i = skb_get_queue_mapping(skb);
 186         if (unlikely(i >= bp->tx_nr_rings)) {
 187                 dev_kfree_skb_any(skb);
 188                 return NETDEV_TX_OK;
 189         }
 190
 191         txr = &bp->tx_ring[i];
 192         txq = netdev_get_tx_queue(dev, i);
 193         prod = txr->tx_prod;
 194
 195         free_size = bnxt_tx_avail(bp, txr);
 196         if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) {
 197                 netif_tx_stop_queue(txq);
 198                 return NETDEV_TX_BUSY;
 199         }
 200
 201         length = skb->len;
 202         len = skb_headlen(skb);
 203         last_frag = skb_shinfo(skb)->nr_frags;
 204
 205         txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 206
 207         txbd->tx_bd_opaque = prod;
 208
 209         tx_buf = &txr->tx_buf_ring[prod];
 210         tx_buf->skb = skb;
 211         tx_buf->nr_frags = last_frag;
 212
 213         vlan_tag_flags = 0;
 214         cfa_action = 0;
 215         if (skb_vlan_tag_present(skb)) {
 216                 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN |
 217                                  skb_vlan_tag_get(skb);
 218                 /* Currently supports 8021Q, 8021AD vlan offloads
 219                  * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
 220                  */
 221                 if (skb->vlan_proto == htons(ETH_P_8021Q))
 222                         vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT;
 223         }
 224
 225         if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) {
 226                 struct tx_push_buffer *tx_push_buf = txr->tx_push;
 227                 struct tx_push_bd *tx_push = &tx_push_buf->push_bd;
 228                 struct tx_bd_ext *tx_push1 = &tx_push->txbd2;
 229                 void *pdata = tx_push_buf->data;
 230                 u64 *end;
 231                 int j, push_len;
 232
 233                 /* Set COAL_NOW to be ready quickly for the next push */
 234                 tx_push->tx_bd_len_flags_type =
 235                         cpu_to_le32((length << TX_BD_LEN_SHIFT) |
 236                                         TX_BD_TYPE_LONG_TX_BD |
 237                                         TX_BD_FLAGS_LHINT_512_AND_SMALLER |
 238                                         TX_BD_FLAGS_COAL_NOW |
 239                                         TX_BD_FLAGS_PACKET_END |
 240                                         (2 << TX_BD_FLAGS_BD_CNT_SHIFT));
 241
 242                 if (skb->ip_summed == CHECKSUM_PARTIAL)
 243                         tx_push1->tx_bd_hsize_lflags =
 244                                         cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
 245                 else
 246                         tx_push1->tx_bd_hsize_lflags = 0;
 247
 248                 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
 249                 tx_push1->tx_bd_cfa_action = cpu_to_le32(cfa_action);
 250
 251                 end = pdata + length;
 252                 end = PTR_ALIGN(end, 8) - 1;
 253                 *end = 0;
 254
 255                 skb_copy_from_linear_data(skb, pdata, len);
 256                 pdata += len;
 257                 for (j = 0; j < last_frag; j++) {
 258                         skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
 259                         void *fptr;
 260
 261                         fptr = skb_frag_address_safe(frag);
 262                         if (!fptr)
 263                                 goto normal_tx;
 264
 265                         memcpy(pdata, fptr, skb_frag_size(frag));
 266                         pdata += skb_frag_size(frag);
 267                 }
 268
 269                 txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type;
 270                 txbd->tx_bd_haddr = txr->data_mapping;
 271                 prod = NEXT_TX(prod);
 272                 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 273                 memcpy(txbd, tx_push1, sizeof(*txbd));
 274                 prod = NEXT_TX(prod);
 275                 tx_push->doorbell =
 276                         cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod);
 277                 txr->tx_prod = prod;
 278
 279                 netdev_tx_sent_queue(txq, skb->len);
 280
 281                 push_len = (length + sizeof(*tx_push) + 7) / 8;
 282                 if (push_len > 16) {
 283                         __iowrite64_copy(txr->tx_doorbell, tx_push_buf, 16);
 284                         __iowrite64_copy(txr->tx_doorbell + 4, tx_push_buf + 1,
 285                                          push_len - 16);
 286                 } else {
 287                         __iowrite64_copy(txr->tx_doorbell, tx_push_buf,
 288                                          push_len);
 289                 }
 290
 291                 tx_buf->is_push = 1;
 292                 goto tx_done;
 293         }
 294
 295 normal_tx:
 296         if (length < BNXT_MIN_PKT_SIZE) {
 297                 pad = BNXT_MIN_PKT_SIZE - length;
 298                 if (skb_pad(skb, pad)) {
 299                         /* SKB already freed. */
 300                         tx_buf->skb = NULL;
 301                         return NETDEV_TX_OK;
 302                 }
 303                 length = BNXT_MIN_PKT_SIZE;
 304         }
 305
 306         mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE);
 307
 308         if (unlikely(dma_mapping_error(&pdev->dev, mapping))) {
 309                 dev_kfree_skb_any(skb);
 310                 tx_buf->skb = NULL;
 311                 return NETDEV_TX_OK;
 312         }
 313
 314         dma_unmap_addr_set(tx_buf, mapping, mapping);
 315         flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD |
 316                 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT);
 317
 318         txbd->tx_bd_haddr = cpu_to_le64(mapping);
 319
 320         prod = NEXT_TX(prod);
 321         txbd1 = (struct tx_bd_ext *)
 322                 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 323
 324         txbd1->tx_bd_hsize_lflags = 0;
 325         if (skb_is_gso(skb)) {
 326                 u32 hdr_len;
 327
 328                 if (skb->encapsulation)
 329                         hdr_len = skb_inner_network_offset(skb) +
 330                                 skb_inner_network_header_len(skb) +
 331                                 inner_tcp_hdrlen(skb);
 332                 else
 333                         hdr_len = skb_transport_offset(skb) +
 334                                 tcp_hdrlen(skb);
 335
 336                 txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO |
 337                                         TX_BD_FLAGS_T_IPID |
 338                                         (hdr_len << (TX_BD_HSIZE_SHIFT - 1)));
 339                 length = skb_shinfo(skb)->gso_size;
 340                 txbd1->tx_bd_mss = cpu_to_le32(length);
 341                 length += hdr_len;
 342         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
 343                 txbd1->tx_bd_hsize_lflags =
 344                         cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
 345                 txbd1->tx_bd_mss = 0;
 346         }
 347
 348         length >>= 9;
 349         flags |= bnxt_lhint_arr[length];
 350         txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
 351
 352         txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
 353         txbd1->tx_bd_cfa_action = cpu_to_le32(cfa_action);
 354         for (i = 0; i < last_frag; i++) {
 355                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
 356
 357                 prod = NEXT_TX(prod);
 358                 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 359
 360                 len = skb_frag_size(frag);
 361                 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len,
 362                                            DMA_TO_DEVICE);
 363
 364                 if (unlikely(dma_mapping_error(&pdev->dev, mapping)))
 365                         goto tx_dma_error;
 366
 367                 tx_buf = &txr->tx_buf_ring[prod];
 368                 dma_unmap_addr_set(tx_buf, mapping, mapping);
 369
 370                 txbd->tx_bd_haddr = cpu_to_le64(mapping);
 371
 372                 flags = len << TX_BD_LEN_SHIFT;
 373                 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
 374         }
 375
 376         flags &= ~TX_BD_LEN;
 377         txbd->tx_bd_len_flags_type =
 378                 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags |
 379                             TX_BD_FLAGS_PACKET_END);
 380
 381         netdev_tx_sent_queue(txq, skb->len);
 382
 383         /* Sync BD data before updating doorbell */
 384         wmb();
 385
 386         prod = NEXT_TX(prod);
 387         txr->tx_prod = prod;
 388
 389         writel(DB_KEY_TX | prod, txr->tx_doorbell);
 390         writel(DB_KEY_TX | prod, txr->tx_doorbell);
 391
 392 tx_done:
 393
 394         mmiowb();
 395
 396         if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) {
 397                 netif_tx_stop_queue(txq);
 398
 399                 /* netif_tx_stop_queue() must be done before checking
 400                  * tx index in bnxt_tx_avail() below, because in
 401                  * bnxt_tx_int(), we update tx index before checking for
 402                  * netif_tx_queue_stopped().
 403                  */
 404                 smp_mb();
 405                 if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)
 406                         netif_tx_wake_queue(txq);
 407         }
 408         return NETDEV_TX_OK;
 409
 410 tx_dma_error:
 411         last_frag = i;
 412
 413         /* start back at beginning and unmap skb */
 414         prod = txr->tx_prod;
 415         tx_buf = &txr->tx_buf_ring[prod];
 416         tx_buf->skb = NULL;
 417         dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 418                          skb_headlen(skb), PCI_DMA_TODEVICE);
 419         prod = NEXT_TX(prod);
 420
 421         /* unmap remaining mapped pages */
 422         for (i = 0; i < last_frag; i++) {
 423                 prod = NEXT_TX(prod);
 424                 tx_buf = &txr->tx_buf_ring[prod];
 425                 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 426                                skb_frag_size(&skb_shinfo(skb)->frags[i]),
 427                                PCI_DMA_TODEVICE);
 428         }
 429
 430         dev_kfree_skb_any(skb);
 431         return NETDEV_TX_OK;
 432 }
 433
 434 static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts)
 435 {
 436         struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
 437         int index = txr - &bp->tx_ring[0];
 438         struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, index);
 439         u16 cons = txr->tx_cons;
 440         struct pci_dev *pdev = bp->pdev;
 441         int i;
 442         unsigned int tx_bytes = 0;
 443
 444         for (i = 0; i < nr_pkts; i++) {
 445                 struct bnxt_sw_tx_bd *tx_buf;
 446                 struct sk_buff *skb;
 447                 int j, last;
 448
 449                 tx_buf = &txr->tx_buf_ring[cons];
 450                 cons = NEXT_TX(cons);
 451                 skb = tx_buf->skb;
 452                 tx_buf->skb = NULL;
 453
 454                 if (tx_buf->is_push) {
 455                         tx_buf->is_push = 0;
 456                         goto next_tx_int;
 457                 }
 458
 459                 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 460                                  skb_headlen(skb), PCI_DMA_TODEVICE);
 461                 last = tx_buf->nr_frags;
 462
 463                 for (j = 0; j < last; j++) {
 464                         cons = NEXT_TX(cons);
 465                         tx_buf = &txr->tx_buf_ring[cons];
 466                         dma_unmap_page(
 467                                 &pdev->dev,
 468                                 dma_unmap_addr(tx_buf, mapping),
 469                                 skb_frag_size(&skb_shinfo(skb)->frags[j]),
 470                                 PCI_DMA_TODEVICE);
 471                 }
 472
 473 next_tx_int:
 474                 cons = NEXT_TX(cons);
 475
 476                 tx_bytes += skb->len;
 477                 dev_kfree_skb_any(skb);
 478         }
 479
 480         netdev_tx_completed_queue(txq, nr_pkts, tx_bytes);
 481         txr->tx_cons = cons;
 482
 483         /* Need to make the tx_cons update visible to bnxt_start_xmit()
 484          * before checking for netif_tx_queue_stopped().  Without the
 485          * memory barrier, there is a small possibility that bnxt_start_xmit()
 486          * will miss it and cause the queue to be stopped forever.
 487          */
 488         smp_mb();
 489
 490         if (unlikely(netif_tx_queue_stopped(txq)) &&
 491             (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
 492                 __netif_tx_lock(txq, smp_processor_id());
 493                 if (netif_tx_queue_stopped(txq) &&
 494                     bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh &&
 495                     txr->dev_state != BNXT_DEV_STATE_CLOSING)
 496                         netif_tx_wake_queue(txq);
 497                 __netif_tx_unlock(txq);
 498         }
 499 }
 500
 501 static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping,
 502                                        gfp_t gfp)
 503 {
 504         u8 *data;
 505         struct pci_dev *pdev = bp->pdev;
 506
 507         data = kmalloc(bp->rx_buf_size, gfp);
 508         if (!data)
 509                 return NULL;
 510
 511         *mapping = dma_map_single(&pdev->dev, data + BNXT_RX_DMA_OFFSET,
 512                                   bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
 513
 514         if (dma_mapping_error(&pdev->dev, *mapping)) {
 515                 kfree(data);
 516                 data = NULL;
 517         }
 518         return data;
 519 }
 520
 521 static inline int bnxt_alloc_rx_data(struct bnxt *bp,
 522                                      struct bnxt_rx_ring_info *rxr,
 523                                      u16 prod, gfp_t gfp)
 524 {
 525         struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 526         struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod];
 527         u8 *data;
 528         dma_addr_t mapping;
 529
 530         data = __bnxt_alloc_rx_data(bp, &mapping, gfp);
 531         if (!data)
 532                 return -ENOMEM;
 533
 534         rx_buf->data = data;
 535         dma_unmap_addr_set(rx_buf, mapping, mapping);
 536
 537         rxbd->rx_bd_haddr = cpu_to_le64(mapping);
 538
 539         return 0;
 540 }
 541
 542 static void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons,
 543                                u8 *data)
 544 {
 545         u16 prod = rxr->rx_prod;
 546         struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
 547         struct rx_bd *cons_bd, *prod_bd;
 548
 549         prod_rx_buf = &rxr->rx_buf_ring[prod];
 550         cons_rx_buf = &rxr->rx_buf_ring[cons];
 551
 552         prod_rx_buf->data = data;
 553
 554         dma_unmap_addr_set(prod_rx_buf, mapping,
 555                            dma_unmap_addr(cons_rx_buf, mapping));
 556
 557         prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 558         cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
 559
 560         prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr;
 561 }
 562
 563 static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx)
 564 {
 565         u16 next, max = rxr->rx_agg_bmap_size;
 566
 567         next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx);
 568         if (next >= max)
 569                 next = find_first_zero_bit(rxr->rx_agg_bmap, max);
 570         return next;
 571 }
 572
 573 static inline int bnxt_alloc_rx_page(struct bnxt *bp,
 574                                      struct bnxt_rx_ring_info *rxr,
 575                                      u16 prod, gfp_t gfp)
 576 {
 577         struct rx_bd *rxbd =
 578                 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 579         struct bnxt_sw_rx_agg_bd *rx_agg_buf;
 580         struct pci_dev *pdev = bp->pdev;
 581         struct page *page;
 582         dma_addr_t mapping;
 583         u16 sw_prod = rxr->rx_sw_agg_prod;
 584         unsigned int offset = 0;
 585
 586         if (PAGE_SIZE > BNXT_RX_PAGE_SIZE) {
 587                 page = rxr->rx_page;
 588                 if (!page) {
 589                         page = alloc_page(gfp);
 590                         if (!page)
 591                                 return -ENOMEM;
 592                         rxr->rx_page = page;
 593                         rxr->rx_page_offset = 0;
 594                 }
 595                 offset = rxr->rx_page_offset;
 596                 rxr->rx_page_offset += BNXT_RX_PAGE_SIZE;
 597                 if (rxr->rx_page_offset == PAGE_SIZE)
 598                         rxr->rx_page = NULL;
 599                 else
 600                         get_page(page);
 601         } else {
 602                 page = alloc_page(gfp);
 603                 if (!page)
 604                         return -ENOMEM;
 605         }
 606
 607         mapping = dma_map_page(&pdev->dev, page, offset, BNXT_RX_PAGE_SIZE,
 608                                PCI_DMA_FROMDEVICE);
 609         if (dma_mapping_error(&pdev->dev, mapping)) {
 610                 __free_page(page);
 611                 return -EIO;
 612         }
 613
 614         if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
 615                 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
 616
 617         __set_bit(sw_prod, rxr->rx_agg_bmap);
 618         rx_agg_buf = &rxr->rx_agg_ring[sw_prod];
 619         rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod);
 620
 621         rx_agg_buf->page = page;
 622         rx_agg_buf->offset = offset;
 623         rx_agg_buf->mapping = mapping;
 624         rxbd->rx_bd_haddr = cpu_to_le64(mapping);
 625         rxbd->rx_bd_opaque = sw_prod;
 626         return 0;
 627 }
 628
 629 static void bnxt_reuse_rx_agg_bufs(struct bnxt_napi *bnapi, u16 cp_cons,
 630                                    u32 agg_bufs)
 631 {
 632         struct bnxt *bp = bnapi->bp;
 633         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
 634         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
 635         u16 prod = rxr->rx_agg_prod;
 636         u16 sw_prod = rxr->rx_sw_agg_prod;
 637         u32 i;
 638
 639         for (i = 0; i < agg_bufs; i++) {
 640                 u16 cons;
 641                 struct rx_agg_cmp *agg;
 642                 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf;
 643                 struct rx_bd *prod_bd;
 644                 struct page *page;
 645
 646                 agg = (struct rx_agg_cmp *)
 647                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
 648                 cons = agg->rx_agg_cmp_opaque;
 649                 __clear_bit(cons, rxr->rx_agg_bmap);
 650
 651                 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
 652                         sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
 653
 654                 __set_bit(sw_prod, rxr->rx_agg_bmap);
 655                 prod_rx_buf = &rxr->rx_agg_ring[sw_prod];
 656                 cons_rx_buf = &rxr->rx_agg_ring[cons];
 657
 658                 /* It is possible for sw_prod to be equal to cons, so
 659                  * set cons_rx_buf->page to NULL first.
 660                  */
 661                 page = cons_rx_buf->page;
 662                 cons_rx_buf->page = NULL;
 663                 prod_rx_buf->page = page;
 664                 prod_rx_buf->offset = cons_rx_buf->offset;
 665
 666                 prod_rx_buf->mapping = cons_rx_buf->mapping;
 667
 668                 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 669
 670                 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping);
 671                 prod_bd->rx_bd_opaque = sw_prod;
 672
 673                 prod = NEXT_RX_AGG(prod);
 674                 sw_prod = NEXT_RX_AGG(sw_prod);
 675                 cp_cons = NEXT_CMP(cp_cons);
 676         }
 677         rxr->rx_agg_prod = prod;
 678         rxr->rx_sw_agg_prod = sw_prod;
 679 }
 680
 681 static struct sk_buff *bnxt_rx_skb(struct bnxt *bp,
 682                                    struct bnxt_rx_ring_info *rxr, u16 cons,
 683                                    u16 prod, u8 *data, dma_addr_t dma_addr,
 684                                    unsigned int len)
 685 {
 686         int err;
 687         struct sk_buff *skb;
 688
 689         err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
 690         if (unlikely(err)) {
 691                 bnxt_reuse_rx_data(rxr, cons, data);
 692                 return NULL;
 693         }
 694
 695         skb = build_skb(data, 0);
 696         dma_unmap_single(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
 697                          PCI_DMA_FROMDEVICE);
 698         if (!skb) {
 699                 kfree(data);
 700                 return NULL;
 701         }
 702
 703         skb_reserve(skb, BNXT_RX_OFFSET);
 704         skb_put(skb, len);
 705         return skb;
 706 }
 707
 708 static struct sk_buff *bnxt_rx_pages(struct bnxt *bp, struct bnxt_napi *bnapi,
 709                                      struct sk_buff *skb, u16 cp_cons,
 710                                      u32 agg_bufs)
 711 {
 712         struct pci_dev *pdev = bp->pdev;
 713         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
 714         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
 715         u16 prod = rxr->rx_agg_prod;
 716         u32 i;
 717
 718         for (i = 0; i < agg_bufs; i++) {
 719                 u16 cons, frag_len;
 720                 struct rx_agg_cmp *agg;
 721                 struct bnxt_sw_rx_agg_bd *cons_rx_buf;
 722                 struct page *page;
 723                 dma_addr_t mapping;
 724
 725                 agg = (struct rx_agg_cmp *)
 726                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
 727                 cons = agg->rx_agg_cmp_opaque;
 728                 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) &
 729                             RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT;
 730
 731                 cons_rx_buf = &rxr->rx_agg_ring[cons];
 732                 skb_fill_page_desc(skb, i, cons_rx_buf->page,
 733                                    cons_rx_buf->offset, frag_len);
 734                 __clear_bit(cons, rxr->rx_agg_bmap);
 735
 736                 /* It is possible for bnxt_alloc_rx_page() to allocate
 737                  * a sw_prod index that equals the cons index, so we
 738                  * need to clear the cons entry now.
 739                  */
 740                 mapping = dma_unmap_addr(cons_rx_buf, mapping);
 741                 page = cons_rx_buf->page;
 742                 cons_rx_buf->page = NULL;
 743
 744                 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) {
 745                         struct skb_shared_info *shinfo;
 746                         unsigned int nr_frags;
 747
 748                         shinfo = skb_shinfo(skb);
 749                         nr_frags = --shinfo->nr_frags;
 750                         __skb_frag_set_page(&shinfo->frags[nr_frags], NULL);
 751
 752                         dev_kfree_skb(skb);
 753
 754                         cons_rx_buf->page = page;
 755
 756                         /* Update prod since possibly some pages have been
 757                          * allocated already.
 758                          */
 759                         rxr->rx_agg_prod = prod;
 760                         bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs - i);
 761                         return NULL;
 762                 }
 763
 764                 dma_unmap_page(&pdev->dev, mapping, BNXT_RX_PAGE_SIZE,
 765                                PCI_DMA_FROMDEVICE);
 766
 767                 skb->data_len += frag_len;
 768                 skb->len += frag_len;
 769                 skb->truesize += PAGE_SIZE;
 770
 771                 prod = NEXT_RX_AGG(prod);
 772                 cp_cons = NEXT_CMP(cp_cons);
 773         }
 774         rxr->rx_agg_prod = prod;
 775         return skb;
 776 }
 777
 778 static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
 779                                u8 agg_bufs, u32 *raw_cons)
 780 {
 781         u16 last;
 782         struct rx_agg_cmp *agg;
 783
 784         *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs);
 785         last = RING_CMP(*raw_cons);
 786         agg = (struct rx_agg_cmp *)
 787                 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)];
 788         return RX_AGG_CMP_VALID(agg, *raw_cons);
 789 }
 790
 791 static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data,
 792                                             unsigned int len,
 793                                             dma_addr_t mapping)
 794 {
 795         struct bnxt *bp = bnapi->bp;
 796         struct pci_dev *pdev = bp->pdev;
 797         struct sk_buff *skb;
 798
 799         skb = napi_alloc_skb(&bnapi->napi, len);
 800         if (!skb)
 801                 return NULL;
 802
 803         dma_sync_single_for_cpu(&pdev->dev, mapping,
 804                                 bp->rx_copy_thresh, PCI_DMA_FROMDEVICE);
 805
 806         memcpy(skb->data - BNXT_RX_OFFSET, data, len + BNXT_RX_OFFSET);
 807
 808         dma_sync_single_for_device(&pdev->dev, mapping,
 809                                    bp->rx_copy_thresh,
 810                                    PCI_DMA_FROMDEVICE);
 811
 812         skb_put(skb, len);
 813         return skb;
 814 }
 815
 816 static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
 817                            struct rx_tpa_start_cmp *tpa_start,
 818                            struct rx_tpa_start_cmp_ext *tpa_start1)
 819 {
 820         u8 agg_id = TPA_START_AGG_ID(tpa_start);
 821         u16 cons, prod;
 822         struct bnxt_tpa_info *tpa_info;
 823         struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
 824         struct rx_bd *prod_bd;
 825         dma_addr_t mapping;
 826
 827         cons = tpa_start->rx_tpa_start_cmp_opaque;
 828         prod = rxr->rx_prod;
 829         cons_rx_buf = &rxr->rx_buf_ring[cons];
 830         prod_rx_buf = &rxr->rx_buf_ring[prod];
 831         tpa_info = &rxr->rx_tpa[agg_id];
 832
 833         prod_rx_buf->data = tpa_info->data;
 834
 835         mapping = tpa_info->mapping;
 836         dma_unmap_addr_set(prod_rx_buf, mapping, mapping);
 837
 838         prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 839
 840         prod_bd->rx_bd_haddr = cpu_to_le64(mapping);
 841
 842         tpa_info->data = cons_rx_buf->data;
 843         cons_rx_buf->data = NULL;
 844         tpa_info->mapping = dma_unmap_addr(cons_rx_buf, mapping);
 845
 846         tpa_info->len =
 847                 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >>
 848                                 RX_TPA_START_CMP_LEN_SHIFT;
 849         if (likely(TPA_START_HASH_VALID(tpa_start))) {
 850                 u32 hash_type = TPA_START_HASH_TYPE(tpa_start);
 851
 852                 tpa_info->hash_type = PKT_HASH_TYPE_L4;
 853                 tpa_info->gso_type = SKB_GSO_TCPV4;
 854                 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
 855                 if (hash_type == 3)
 856                         tpa_info->gso_type = SKB_GSO_TCPV6;
 857                 tpa_info->rss_hash =
 858                         le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash);
 859         } else {
 860                 tpa_info->hash_type = PKT_HASH_TYPE_NONE;
 861                 tpa_info->gso_type = 0;
 862                 if (netif_msg_rx_err(bp))
 863                         netdev_warn(bp->dev, "TPA packet without valid hash\n");
 864         }
 865         tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2);
 866         tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata);
 867
 868         rxr->rx_prod = NEXT_RX(prod);
 869         cons = NEXT_RX(cons);
 870         cons_rx_buf = &rxr->rx_buf_ring[cons];
 871
 872         bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data);
 873         rxr->rx_prod = NEXT_RX(rxr->rx_prod);
 874         cons_rx_buf->data = NULL;
 875 }
 876
 877 static void bnxt_abort_tpa(struct bnxt *bp, struct bnxt_napi *bnapi,
 878                            u16 cp_cons, u32 agg_bufs)
 879 {
 880         if (agg_bufs)
 881                 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
 882 }
 883
 884 #define BNXT_IPV4_HDR_SIZE      (sizeof(struct iphdr) + sizeof(struct tcphdr))
 885 #define BNXT_IPV6_HDR_SIZE      (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
 886
 887 static inline struct sk_buff *bnxt_gro_skb(struct bnxt_tpa_info *tpa_info,
 888                                            struct rx_tpa_end_cmp *tpa_end,
 889                                            struct rx_tpa_end_cmp_ext *tpa_end1,
 890                                            struct sk_buff *skb)
 891 {
 892 #ifdef CONFIG_INET
 893         struct tcphdr *th;
 894         int payload_off, tcp_opt_len = 0;
 895         int len, nw_off;
 896         u16 segs;
 897
 898         segs = TPA_END_TPA_SEGS(tpa_end);
 899         if (segs == 1)
 900                 return skb;
 901
 902         NAPI_GRO_CB(skb)->count = segs;
 903         skb_shinfo(skb)->gso_size =
 904                 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len);
 905         skb_shinfo(skb)->gso_type = tpa_info->gso_type;
 906         payload_off = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
 907                        RX_TPA_END_CMP_PAYLOAD_OFFSET) >>
 908                       RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT;
 909         if (TPA_END_GRO_TS(tpa_end))
 910                 tcp_opt_len = 12;
 911
 912         if (tpa_info->gso_type == SKB_GSO_TCPV4) {
 913                 struct iphdr *iph;
 914
 915                 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len -
 916                          ETH_HLEN;
 917                 skb_set_network_header(skb, nw_off);
 918                 iph = ip_hdr(skb);
 919                 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
 920                 len = skb->len - skb_transport_offset(skb);
 921                 th = tcp_hdr(skb);
 922                 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
 923         } else if (tpa_info->gso_type == SKB_GSO_TCPV6) {
 924                 struct ipv6hdr *iph;
 925
 926                 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len -
 927                          ETH_HLEN;
 928                 skb_set_network_header(skb, nw_off);
 929                 iph = ipv6_hdr(skb);
 930                 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
 931                 len = skb->len - skb_transport_offset(skb);
 932                 th = tcp_hdr(skb);
 933                 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
 934         } else {
 935                 dev_kfree_skb_any(skb);
 936                 return NULL;
 937         }
 938         tcp_gro_complete(skb);
 939
 940         if (nw_off) { /* tunnel */
 941                 struct udphdr *uh = NULL;
 942
 943                 if (skb->protocol == htons(ETH_P_IP)) {
 944                         struct iphdr *iph = (struct iphdr *)skb->data;
 945
 946                         if (iph->protocol == IPPROTO_UDP)
 947                                 uh = (struct udphdr *)(iph + 1);
 948                 } else {
 949                         struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
 950
 951                         if (iph->nexthdr == IPPROTO_UDP)
 952                                 uh = (struct udphdr *)(iph + 1);
 953                 }
 954                 if (uh) {
 955                         if (uh->check)
 956                                 skb_shinfo(skb)->gso_type |=
 957                                         SKB_GSO_UDP_TUNNEL_CSUM;
 958                         else
 959                                 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
 960                 }
 961         }
 962 #endif
 963         return skb;
 964 }
 965
 966 static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp,
 967                                            struct bnxt_napi *bnapi,
 968                                            u32 *raw_cons,
 969                                            struct rx_tpa_end_cmp *tpa_end,
 970                                            struct rx_tpa_end_cmp_ext *tpa_end1,
 971                                            bool *agg_event)
 972 {
 973         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
 974         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
 975         u8 agg_id = TPA_END_AGG_ID(tpa_end);
 976         u8 *data, agg_bufs;
 977         u16 cp_cons = RING_CMP(*raw_cons);
 978         unsigned int len;
 979         struct bnxt_tpa_info *tpa_info;
 980         dma_addr_t mapping;
 981         struct sk_buff *skb;
 982
 983         tpa_info = &rxr->rx_tpa[agg_id];
 984         data = tpa_info->data;
 985         prefetch(data);
 986         len = tpa_info->len;
 987         mapping = tpa_info->mapping;
 988
 989         agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
 990                     RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT;
 991
 992         if (agg_bufs) {
 993                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons))
 994                         return ERR_PTR(-EBUSY);
 995
 996                 *agg_event = true;
 997                 cp_cons = NEXT_CMP(cp_cons);
 998         }
 999
1000         if (unlikely(agg_bufs > MAX_SKB_FRAGS)) {
1001                 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1002                 netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
1003                             agg_bufs, (int)MAX_SKB_FRAGS);
1004                 return NULL;
1005         }
1006
1007         if (len <= bp->rx_copy_thresh) {
1008                 skb = bnxt_copy_skb(bnapi, data, len, mapping);
1009                 if (!skb) {
1010                         bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1011                         return NULL;
1012                 }
1013         } else {
1014                 u8 *new_data;
1015                 dma_addr_t new_mapping;
1016
1017                 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC);
1018                 if (!new_data) {
1019                         bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1020                         return NULL;
1021                 }
1022
1023                 tpa_info->data = new_data;
1024                 tpa_info->mapping = new_mapping;
1025
1026                 skb = build_skb(data, 0);
1027                 dma_unmap_single(&bp->pdev->dev, mapping, bp->rx_buf_use_size,
1028                                  PCI_DMA_FROMDEVICE);
1029
1030                 if (!skb) {
1031                         kfree(data);
1032                         bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1033                         return NULL;
1034                 }
1035                 skb_reserve(skb, BNXT_RX_OFFSET);
1036                 skb_put(skb, len);
1037         }
1038
1039         if (agg_bufs) {
1040                 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1041                 if (!skb) {
1042                         /* Page reuse already handled by bnxt_rx_pages(). */
1043                         return NULL;
1044                 }
1045         }
1046         skb->protocol = eth_type_trans(skb, bp->dev);
1047
1048         if (tpa_info->hash_type != PKT_HASH_TYPE_NONE)
1049                 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type);
1050
1051         if (tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) {
1052                 netdev_features_t features = skb->dev->features;
1053                 u16 vlan_proto = tpa_info->metadata >>
1054                         RX_CMP_FLAGS2_METADATA_TPID_SFT;
1055
1056                 if (((features & NETIF_F_HW_VLAN_CTAG_RX) &&
1057                      vlan_proto == ETH_P_8021Q) ||
1058                     ((features & NETIF_F_HW_VLAN_STAG_RX) &&
1059                      vlan_proto == ETH_P_8021AD)) {
1060                         __vlan_hwaccel_put_tag(skb, htons(vlan_proto),
1061                                                tpa_info->metadata &
1062                                                RX_CMP_FLAGS2_METADATA_VID_MASK);
1063                 }
1064         }
1065
1066         skb_checksum_none_assert(skb);
1067         if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) {
1068                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1069                 skb->csum_level =
1070                         (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3;
1071         }
1072
1073         if (TPA_END_GRO(tpa_end))
1074                 skb = bnxt_gro_skb(tpa_info, tpa_end, tpa_end1, skb);
1075
1076         return skb;
1077 }
1078
1079 /* returns the following:
1080  * 1       - 1 packet successfully received
1081  * 0       - successful TPA_START, packet not completed yet
1082  * -EBUSY  - completion ring does not have all the agg buffers yet
1083  * -ENOMEM - packet aborted due to out of memory
1084  * -EIO    - packet aborted due to hw error indicated in BD
1085  */
1086 static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_napi *bnapi, u32 *raw_cons,
1087                        bool *agg_event)
1088 {
1089         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1090         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1091         struct net_device *dev = bp->dev;
1092         struct rx_cmp *rxcmp;
1093         struct rx_cmp_ext *rxcmp1;
1094         u32 tmp_raw_cons = *raw_cons;
1095         u16 cons, prod, cp_cons = RING_CMP(tmp_raw_cons);
1096         struct bnxt_sw_rx_bd *rx_buf;
1097         unsigned int len;
1098         u8 *data, agg_bufs, cmp_type;
1099         dma_addr_t dma_addr;
1100         struct sk_buff *skb;
1101         int rc = 0;
1102
1103         rxcmp = (struct rx_cmp *)
1104                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1105
1106         tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1107         cp_cons = RING_CMP(tmp_raw_cons);
1108         rxcmp1 = (struct rx_cmp_ext *)
1109                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1110
1111         if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1112                 return -EBUSY;
1113
1114         cmp_type = RX_CMP_TYPE(rxcmp);
1115
1116         prod = rxr->rx_prod;
1117
1118         if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) {
1119                 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp,
1120                                (struct rx_tpa_start_cmp_ext *)rxcmp1);
1121
1122                 goto next_rx_no_prod;
1123
1124         } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1125                 skb = bnxt_tpa_end(bp, bnapi, &tmp_raw_cons,
1126                                    (struct rx_tpa_end_cmp *)rxcmp,
1127                                    (struct rx_tpa_end_cmp_ext *)rxcmp1,
1128                                    agg_event);
1129
1130                 if (unlikely(IS_ERR(skb)))
1131                         return -EBUSY;
1132
1133                 rc = -ENOMEM;
1134                 if (likely(skb)) {
1135                         skb_record_rx_queue(skb, bnapi->index);
1136                         skb_mark_napi_id(skb, &bnapi->napi);
1137                         if (bnxt_busy_polling(bnapi))
1138                                 netif_receive_skb(skb);
1139                         else
1140                                 napi_gro_receive(&bnapi->napi, skb);
1141                         rc = 1;
1142                 }
1143                 goto next_rx_no_prod;
1144         }
1145
1146         cons = rxcmp->rx_cmp_opaque;
1147         rx_buf = &rxr->rx_buf_ring[cons];
1148         data = rx_buf->data;
1149         prefetch(data);
1150
1151         agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) & RX_CMP_AGG_BUFS) >>
1152                                 RX_CMP_AGG_BUFS_SHIFT;
1153
1154         if (agg_bufs) {
1155                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1156                         return -EBUSY;
1157
1158                 cp_cons = NEXT_CMP(cp_cons);
1159                 *agg_event = true;
1160         }
1161
1162         rx_buf->data = NULL;
1163         if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) {
1164                 bnxt_reuse_rx_data(rxr, cons, data);
1165                 if (agg_bufs)
1166                         bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
1167
1168                 rc = -EIO;
1169                 goto next_rx;
1170         }
1171
1172         len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT;
1173         dma_addr = dma_unmap_addr(rx_buf, mapping);
1174
1175         if (len <= bp->rx_copy_thresh) {
1176                 skb = bnxt_copy_skb(bnapi, data, len, dma_addr);
1177                 bnxt_reuse_rx_data(rxr, cons, data);
1178                 if (!skb) {
1179                         rc = -ENOMEM;
1180                         goto next_rx;
1181                 }
1182         } else {
1183                 skb = bnxt_rx_skb(bp, rxr, cons, prod, data, dma_addr, len);
1184                 if (!skb) {
1185                         rc = -ENOMEM;
1186                         goto next_rx;
1187                 }
1188         }
1189
1190         if (agg_bufs) {
1191                 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1192                 if (!skb) {
1193                         rc = -ENOMEM;
1194                         goto next_rx;
1195                 }
1196         }
1197
1198         if (RX_CMP_HASH_VALID(rxcmp)) {
1199                 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp);
1200                 enum pkt_hash_types type = PKT_HASH_TYPE_L4;
1201
1202                 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1203                 if (hash_type != 1 && hash_type != 3)
1204                         type = PKT_HASH_TYPE_L3;
1205                 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type);
1206         }
1207
1208         skb->protocol = eth_type_trans(skb, dev);
1209
1210         if (rxcmp1->rx_cmp_flags2 &
1211             cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) {
1212                 netdev_features_t features = skb->dev->features;
1213                 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data);
1214                 u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT;
1215
1216                 if (((features & NETIF_F_HW_VLAN_CTAG_RX) &&
1217                      vlan_proto == ETH_P_8021Q) ||
1218                     ((features & NETIF_F_HW_VLAN_STAG_RX) &&
1219                      vlan_proto == ETH_P_8021AD))
1220                         __vlan_hwaccel_put_tag(skb, htons(vlan_proto),
1221                                                meta_data &
1222                                                RX_CMP_FLAGS2_METADATA_VID_MASK);
1223         }
1224
1225         skb_checksum_none_assert(skb);
1226         if (RX_CMP_L4_CS_OK(rxcmp1)) {
1227                 if (dev->features & NETIF_F_RXCSUM) {
1228                         skb->ip_summed = CHECKSUM_UNNECESSARY;
1229                         skb->csum_level = RX_CMP_ENCAP(rxcmp1);
1230                 }
1231         } else {
1232                 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) {
1233                         if (dev->features & NETIF_F_RXCSUM)
1234                                 cpr->rx_l4_csum_errors++;
1235                 }
1236         }
1237
1238         skb_record_rx_queue(skb, bnapi->index);
1239         skb_mark_napi_id(skb, &bnapi->napi);
1240         if (bnxt_busy_polling(bnapi))
1241                 netif_receive_skb(skb);
1242         else
1243                 napi_gro_receive(&bnapi->napi, skb);
1244         rc = 1;
1245
1246 next_rx:
1247         rxr->rx_prod = NEXT_RX(prod);
1248
1249 next_rx_no_prod:
1250         *raw_cons = tmp_raw_cons;
1251
1252         return rc;
1253 }
1254
1255 static int bnxt_async_event_process(struct bnxt *bp,
1256                                     struct hwrm_async_event_cmpl *cmpl)
1257 {
1258         u16 event_id = le16_to_cpu(cmpl->event_id);
1259
1260         /* TODO CHIMP_FW: Define event id's for link change, error etc */
1261         switch (event_id) {
1262         case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE:
1263                 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event);
1264                 break;
1265         case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD:
1266                 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event);
1267                 break;
1268         default:
1269                 netdev_err(bp->dev, "unhandled ASYNC event (id 0x%x)\n",
1270                            event_id);
1271                 goto async_event_process_exit;
1272         }
1273         schedule_work(&bp->sp_task);
1274 async_event_process_exit:
1275         return 0;
1276 }
1277
1278 static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp)
1279 {
1280         u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id;
1281         struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp;
1282         struct hwrm_fwd_req_cmpl *fwd_req_cmpl =
1283                                 (struct hwrm_fwd_req_cmpl *)txcmp;
1284
1285         switch (cmpl_type) {
1286         case CMPL_BASE_TYPE_HWRM_DONE:
1287                 seq_id = le16_to_cpu(h_cmpl->sequence_id);
1288                 if (seq_id == bp->hwrm_intr_seq_id)
1289                         bp->hwrm_intr_seq_id = HWRM_SEQ_ID_INVALID;
1290                 else
1291                         netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id);
1292                 break;
1293
1294         case CMPL_BASE_TYPE_HWRM_FWD_REQ:
1295                 vf_id = le16_to_cpu(fwd_req_cmpl->source_id);
1296
1297                 if ((vf_id < bp->pf.first_vf_id) ||
1298                     (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) {
1299                         netdev_err(bp->dev, "Msg contains invalid VF id %x\n",
1300                                    vf_id);
1301                         return -EINVAL;
1302                 }
1303
1304                 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap);
1305                 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event);
1306                 schedule_work(&bp->sp_task);
1307                 break;
1308
1309         case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT:
1310                 bnxt_async_event_process(bp,
1311                                          (struct hwrm_async_event_cmpl *)txcmp);
1312
1313         default:
1314                 break;
1315         }
1316
1317         return 0;
1318 }
1319
1320 static irqreturn_t bnxt_msix(int irq, void *dev_instance)
1321 {
1322         struct bnxt_napi *bnapi = dev_instance;
1323         struct bnxt *bp = bnapi->bp;
1324         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1325         u32 cons = RING_CMP(cpr->cp_raw_cons);
1326
1327         prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1328         napi_schedule(&bnapi->napi);
1329         return IRQ_HANDLED;
1330 }
1331
1332 static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1333 {
1334         u32 raw_cons = cpr->cp_raw_cons;
1335         u16 cons = RING_CMP(raw_cons);
1336         struct tx_cmp *txcmp;
1337
1338         txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1339
1340         return TX_CMP_VALID(txcmp, raw_cons);
1341 }
1342
1343 static irqreturn_t bnxt_inta(int irq, void *dev_instance)
1344 {
1345         struct bnxt_napi *bnapi = dev_instance;
1346         struct bnxt *bp = bnapi->bp;
1347         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1348         u32 cons = RING_CMP(cpr->cp_raw_cons);
1349         u32 int_status;
1350
1351         prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1352
1353         if (!bnxt_has_work(bp, cpr)) {
1354                 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS);
1355                 /* return if erroneous interrupt */
1356                 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id)))
1357                         return IRQ_NONE;
1358         }
1359
1360         /* disable ring IRQ */
1361         BNXT_CP_DB_IRQ_DIS(cpr->cp_doorbell);
1362
1363         /* Return here if interrupt is shared and is disabled. */
1364         if (unlikely(atomic_read(&bp->intr_sem) != 0))
1365                 return IRQ_HANDLED;
1366
1367         napi_schedule(&bnapi->napi);
1368         return IRQ_HANDLED;
1369 }
1370
1371 static int bnxt_poll_work(struct bnxt *bp, struct bnxt_napi *bnapi, int budget)
1372 {
1373         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1374         u32 raw_cons = cpr->cp_raw_cons;
1375         u32 cons;
1376         int tx_pkts = 0;
1377         int rx_pkts = 0;
1378         bool rx_event = false;
1379         bool agg_event = false;
1380         struct tx_cmp *txcmp;
1381
1382         while (1) {
1383                 int rc;
1384
1385                 cons = RING_CMP(raw_cons);
1386                 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1387
1388                 if (!TX_CMP_VALID(txcmp, raw_cons))
1389                         break;
1390
1391                 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) {
1392                         tx_pkts++;
1393                         /* return full budget so NAPI will complete. */
1394                         if (unlikely(tx_pkts > bp->tx_wake_thresh))
1395                                 rx_pkts = budget;
1396                 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1397                         rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &agg_event);
1398                         if (likely(rc >= 0))
1399                                 rx_pkts += rc;
1400                         else if (rc == -EBUSY)  /* partial completion */
1401                                 break;
1402                         rx_event = true;
1403                 } else if (unlikely((TX_CMP_TYPE(txcmp) ==
1404                                      CMPL_BASE_TYPE_HWRM_DONE) ||
1405                                     (TX_CMP_TYPE(txcmp) ==
1406                                      CMPL_BASE_TYPE_HWRM_FWD_REQ) ||
1407                                     (TX_CMP_TYPE(txcmp) ==
1408                                      CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) {
1409                         bnxt_hwrm_handler(bp, txcmp);
1410                 }
1411                 raw_cons = NEXT_RAW_CMP(raw_cons);
1412
1413                 if (rx_pkts == budget)
1414                         break;
1415         }
1416
1417         cpr->cp_raw_cons = raw_cons;
1418         /* ACK completion ring before freeing tx ring and producing new
1419          * buffers in rx/agg rings to prevent overflowing the completion
1420          * ring.
1421          */
1422         BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
1423
1424         if (tx_pkts)
1425                 bnxt_tx_int(bp, bnapi, tx_pkts);
1426
1427         if (rx_event) {
1428                 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1429
1430                 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1431                 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1432                 if (agg_event) {
1433                         writel(DB_KEY_RX | rxr->rx_agg_prod,
1434                                rxr->rx_agg_doorbell);
1435                         writel(DB_KEY_RX | rxr->rx_agg_prod,
1436                                rxr->rx_agg_doorbell);
1437                 }
1438         }
1439         return rx_pkts;
1440 }
1441
1442 static int bnxt_poll(struct napi_struct *napi, int budget)
1443 {
1444         struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1445         struct bnxt *bp = bnapi->bp;
1446         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1447         int work_done = 0;
1448
1449         if (!bnxt_lock_napi(bnapi))
1450                 return budget;
1451
1452         while (1) {
1453                 work_done += bnxt_poll_work(bp, bnapi, budget - work_done);
1454
1455                 if (work_done >= budget)
1456                         break;
1457
1458                 if (!bnxt_has_work(bp, cpr)) {
1459                         napi_complete(napi);
1460                         BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
1461                         break;
1462                 }
1463         }
1464         mmiowb();
1465         bnxt_unlock_napi(bnapi);
1466         return work_done;
1467 }
1468
1469 #ifdef CONFIG_NET_RX_BUSY_POLL
1470 static int bnxt_busy_poll(struct napi_struct *napi)
1471 {
1472         struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1473         struct bnxt *bp = bnapi->bp;
1474         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1475         int rx_work, budget = 4;
1476
1477         if (atomic_read(&bp->intr_sem) != 0)
1478                 return LL_FLUSH_FAILED;
1479
1480         if (!bnxt_lock_poll(bnapi))
1481                 return LL_FLUSH_BUSY;
1482
1483         rx_work = bnxt_poll_work(bp, bnapi, budget);
1484
1485         BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
1486
1487         bnxt_unlock_poll(bnapi);
1488         return rx_work;
1489 }
1490 #endif
1491
1492 static void bnxt_free_tx_skbs(struct bnxt *bp)
1493 {
1494         int i, max_idx;
1495         struct pci_dev *pdev = bp->pdev;
1496
1497         if (!bp->tx_ring)
1498                 return;
1499
1500         max_idx = bp->tx_nr_pages * TX_DESC_CNT;
1501         for (i = 0; i < bp->tx_nr_rings; i++) {
1502                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
1503                 int j;
1504
1505                 for (j = 0; j < max_idx;) {
1506                         struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
1507                         struct sk_buff *skb = tx_buf->skb;
1508                         int k, last;
1509
1510                         if (!skb) {
1511                                 j++;
1512                                 continue;
1513                         }
1514
1515                         tx_buf->skb = NULL;
1516
1517                         if (tx_buf->is_push) {
1518                                 dev_kfree_skb(skb);
1519                                 j += 2;
1520                                 continue;
1521                         }
1522
1523                         dma_unmap_single(&pdev->dev,
1524                                          dma_unmap_addr(tx_buf, mapping),
1525                                          skb_headlen(skb),
1526                                          PCI_DMA_TODEVICE);
1527
1528                         last = tx_buf->nr_frags;
1529                         j += 2;
1530                         for (k = 0; k < last; k++, j++) {
1531                                 int ring_idx = j & bp->tx_ring_mask;
1532                                 skb_frag_t *frag = &skb_shinfo(skb)->frags[k];
1533
1534                                 tx_buf = &txr->tx_buf_ring[ring_idx];
1535                                 dma_unmap_page(
1536                                         &pdev->dev,
1537                                         dma_unmap_addr(tx_buf, mapping),
1538                                         skb_frag_size(frag), PCI_DMA_TODEVICE);
1539                         }
1540                         dev_kfree_skb(skb);
1541                 }
1542                 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));
1543         }
1544 }
1545
1546 static void bnxt_free_rx_skbs(struct bnxt *bp)
1547 {
1548         int i, max_idx, max_agg_idx;
1549         struct pci_dev *pdev = bp->pdev;
1550
1551         if (!bp->rx_ring)
1552                 return;
1553
1554         max_idx = bp->rx_nr_pages * RX_DESC_CNT;
1555         max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT;
1556         for (i = 0; i < bp->rx_nr_rings; i++) {
1557                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
1558                 int j;
1559
1560                 if (rxr->rx_tpa) {
1561                         for (j = 0; j < MAX_TPA; j++) {
1562                                 struct bnxt_tpa_info *tpa_info =
1563                                                         &rxr->rx_tpa[j];
1564                                 u8 *data = tpa_info->data;
1565
1566                                 if (!data)
1567                                         continue;
1568
1569                                 dma_unmap_single(
1570                                         &pdev->dev,
1571                                         dma_unmap_addr(tpa_info, mapping),
1572                                         bp->rx_buf_use_size,
1573                                         PCI_DMA_FROMDEVICE);
1574
1575                                 tpa_info->data = NULL;
1576
1577                                 kfree(data);
1578                         }
1579                 }
1580
1581                 for (j = 0; j < max_idx; j++) {
1582                         struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j];
1583                         u8 *data = rx_buf->data;
1584
1585                         if (!data)
1586                                 continue;
1587
1588                         dma_unmap_single(&pdev->dev,
1589                                          dma_unmap_addr(rx_buf, mapping),
1590                                          bp->rx_buf_use_size,
1591                                          PCI_DMA_FROMDEVICE);
1592
1593                         rx_buf->data = NULL;
1594
1595                         kfree(data);
1596                 }
1597
1598                 for (j = 0; j < max_agg_idx; j++) {
1599                         struct bnxt_sw_rx_agg_bd *rx_agg_buf =
1600                                 &rxr->rx_agg_ring[j];
1601                         struct page *page = rx_agg_buf->page;
1602
1603                         if (!page)
1604                                 continue;
1605
1606                         dma_unmap_page(&pdev->dev,
1607                                        dma_unmap_addr(rx_agg_buf, mapping),
1608                                        BNXT_RX_PAGE_SIZE, PCI_DMA_FROMDEVICE);
1609
1610                         rx_agg_buf->page = NULL;
1611                         __clear_bit(j, rxr->rx_agg_bmap);
1612
1613                         __free_page(page);
1614                 }
1615                 if (rxr->rx_page) {
1616                         __free_page(rxr->rx_page);
1617                         rxr->rx_page = NULL;
1618                 }
1619         }
1620 }
1621
1622 static void bnxt_free_skbs(struct bnxt *bp)
1623 {
1624         bnxt_free_tx_skbs(bp);
1625         bnxt_free_rx_skbs(bp);
1626 }
1627
1628 static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
1629 {
1630         struct pci_dev *pdev = bp->pdev;
1631         int i;
1632
1633         for (i = 0; i < ring->nr_pages; i++) {
1634                 if (!ring->pg_arr[i])
1635                         continue;
1636
1637                 dma_free_coherent(&pdev->dev, ring->page_size,
1638                                   ring->pg_arr[i], ring->dma_arr[i]);
1639
1640                 ring->pg_arr[i] = NULL;
1641         }
1642         if (ring->pg_tbl) {
1643                 dma_free_coherent(&pdev->dev, ring->nr_pages * 8,
1644                                   ring->pg_tbl, ring->pg_tbl_map);
1645                 ring->pg_tbl = NULL;
1646         }
1647         if (ring->vmem_size && *ring->vmem) {
1648                 vfree(*ring->vmem);
1649                 *ring->vmem = NULL;
1650         }
1651 }
1652
1653 static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
1654 {
1655         int i;
1656         struct pci_dev *pdev = bp->pdev;
1657
1658         if (ring->nr_pages > 1) {
1659                 ring->pg_tbl = dma_alloc_coherent(&pdev->dev,
1660                                                   ring->nr_pages * 8,
1661                                                   &ring->pg_tbl_map,
1662                                                   GFP_KERNEL);
1663                 if (!ring->pg_tbl)
1664                         return -ENOMEM;
1665         }
1666
1667         for (i = 0; i < ring->nr_pages; i++) {
1668                 ring->pg_arr[i] = dma_alloc_coherent(&pdev->dev,
1669                                                      ring->page_size,
1670                                                      &ring->dma_arr[i],
1671                                                      GFP_KERNEL);
1672                 if (!ring->pg_arr[i])
1673                         return -ENOMEM;
1674
1675                 if (ring->nr_pages > 1)
1676                         ring->pg_tbl[i] = cpu_to_le64(ring->dma_arr[i]);
1677         }
1678
1679         if (ring->vmem_size) {
1680                 *ring->vmem = vzalloc(ring->vmem_size);
1681                 if (!(*ring->vmem))
1682                         return -ENOMEM;
1683         }
1684         return 0;
1685 }
1686
1687 static void bnxt_free_rx_rings(struct bnxt *bp)
1688 {
1689         int i;
1690
1691         if (!bp->rx_ring)
1692                 return;
1693
1694         for (i = 0; i < bp->rx_nr_rings; i++) {
1695                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
1696                 struct bnxt_ring_struct *ring;
1697
1698                 kfree(rxr->rx_tpa);
1699                 rxr->rx_tpa = NULL;
1700
1701                 kfree(rxr->rx_agg_bmap);
1702                 rxr->rx_agg_bmap = NULL;
1703
1704                 ring = &rxr->rx_ring_struct;
1705                 bnxt_free_ring(bp, ring);
1706
1707                 ring = &rxr->rx_agg_ring_struct;
1708                 bnxt_free_ring(bp, ring);
1709         }
1710 }
1711
1712 static int bnxt_alloc_rx_rings(struct bnxt *bp)
1713 {
1714         int i, rc, agg_rings = 0, tpa_rings = 0;
1715
1716         if (!bp->rx_ring)
1717                 return -ENOMEM;
1718
1719         if (bp->flags & BNXT_FLAG_AGG_RINGS)
1720                 agg_rings = 1;
1721
1722         if (bp->flags & BNXT_FLAG_TPA)
1723                 tpa_rings = 1;
1724
1725         for (i = 0; i < bp->rx_nr_rings; i++) {
1726                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
1727                 struct bnxt_ring_struct *ring;
1728
1729                 ring = &rxr->rx_ring_struct;
1730
1731                 rc = bnxt_alloc_ring(bp, ring);
1732                 if (rc)
1733                         return rc;
1734
1735                 if (agg_rings) {
1736                         u16 mem_size;
1737
1738                         ring = &rxr->rx_agg_ring_struct;
1739                         rc = bnxt_alloc_ring(bp, ring);
1740                         if (rc)
1741                                 return rc;
1742
1743                         rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1;
1744                         mem_size = rxr->rx_agg_bmap_size / 8;
1745                         rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL);
1746                         if (!rxr->rx_agg_bmap)
1747                                 return -ENOMEM;
1748
1749                         if (tpa_rings) {
1750                                 rxr->rx_tpa = kcalloc(MAX_TPA,
1751                                                 sizeof(struct bnxt_tpa_info),
1752                                                 GFP_KERNEL);
1753                                 if (!rxr->rx_tpa)
1754                                         return -ENOMEM;
1755                         }
1756                 }
1757         }
1758         return 0;
1759 }
1760
1761 static void bnxt_free_tx_rings(struct bnxt *bp)
1762 {
1763         int i;
1764         struct pci_dev *pdev = bp->pdev;
1765
1766         if (!bp->tx_ring)
1767                 return;
1768
1769         for (i = 0; i < bp->tx_nr_rings; i++) {
1770                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
1771                 struct bnxt_ring_struct *ring;
1772
1773                 if (txr->tx_push) {
1774                         dma_free_coherent(&pdev->dev, bp->tx_push_size,
1775                                           txr->tx_push, txr->tx_push_mapping);
1776                         txr->tx_push = NULL;
1777                 }
1778
1779                 ring = &txr->tx_ring_struct;
1780
1781                 bnxt_free_ring(bp, ring);
1782         }
1783 }
1784
1785 static int bnxt_alloc_tx_rings(struct bnxt *bp)
1786 {
1787         int i, j, rc;
1788         struct pci_dev *pdev = bp->pdev;
1789
1790         bp->tx_push_size = 0;
1791         if (bp->tx_push_thresh) {
1792                 int push_size;
1793
1794                 push_size  = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) +
1795                                         bp->tx_push_thresh);
1796
1797                 if (push_size > 256) {
1798                         push_size = 0;
1799                         bp->tx_push_thresh = 0;
1800                 }
1801
1802                 bp->tx_push_size = push_size;
1803         }
1804
1805         for (i = 0, j = 0; i < bp->tx_nr_rings; i++) {
1806                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
1807                 struct bnxt_ring_struct *ring;
1808
1809                 ring = &txr->tx_ring_struct;
1810
1811                 rc = bnxt_alloc_ring(bp, ring);
1812                 if (rc)
1813                         return rc;
1814
1815                 if (bp->tx_push_size) {
1816                         dma_addr_t mapping;
1817
1818                         /* One pre-allocated DMA buffer to backup
1819                          * TX push operation
1820                          */
1821                         txr->tx_push = dma_alloc_coherent(&pdev->dev,
1822                                                 bp->tx_push_size,
1823                                                 &txr->tx_push_mapping,
1824                                                 GFP_KERNEL);
1825
1826                         if (!txr->tx_push)
1827                                 return -ENOMEM;
1828
1829                         mapping = txr->tx_push_mapping +
1830                                 sizeof(struct tx_push_bd);
1831                         txr->data_mapping = cpu_to_le64(mapping);
1832
1833                         memset(txr->tx_push, 0, sizeof(struct tx_push_bd));
1834                 }
1835                 ring->queue_id = bp->q_info[j].queue_id;
1836                 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1))
1837                         j++;
1838         }
1839         return 0;
1840 }
1841
1842 static void bnxt_free_cp_rings(struct bnxt *bp)
1843 {
1844         int i;
1845
1846         if (!bp->bnapi)
1847                 return;
1848
1849         for (i = 0; i < bp->cp_nr_rings; i++) {
1850                 struct bnxt_napi *bnapi = bp->bnapi[i];
1851                 struct bnxt_cp_ring_info *cpr;
1852                 struct bnxt_ring_struct *ring;
1853
1854                 if (!bnapi)
1855                         continue;
1856
1857                 cpr = &bnapi->cp_ring;
1858                 ring = &cpr->cp_ring_struct;
1859
1860                 bnxt_free_ring(bp, ring);
1861         }
1862 }
1863
1864 static int bnxt_alloc_cp_rings(struct bnxt *bp)
1865 {
1866         int i, rc;
1867
1868         for (i = 0; i < bp->cp_nr_rings; i++) {
1869                 struct bnxt_napi *bnapi = bp->bnapi[i];
1870                 struct bnxt_cp_ring_info *cpr;
1871                 struct bnxt_ring_struct *ring;
1872
1873                 if (!bnapi)
1874                         continue;
1875
1876                 cpr = &bnapi->cp_ring;
1877                 ring = &cpr->cp_ring_struct;
1878
1879                 rc = bnxt_alloc_ring(bp, ring);
1880                 if (rc)
1881                         return rc;
1882         }
1883         return 0;
1884 }
1885
1886 static void bnxt_init_ring_struct(struct bnxt *bp)
1887 {
1888         int i;
1889
1890         for (i = 0; i < bp->cp_nr_rings; i++) {
1891                 struct bnxt_napi *bnapi = bp->bnapi[i];
1892                 struct bnxt_cp_ring_info *cpr;
1893                 struct bnxt_rx_ring_info *rxr;
1894                 struct bnxt_tx_ring_info *txr;
1895                 struct bnxt_ring_struct *ring;
1896
1897                 if (!bnapi)
1898                         continue;
1899
1900                 cpr = &bnapi->cp_ring;
1901                 ring = &cpr->cp_ring_struct;
1902                 ring->nr_pages = bp->cp_nr_pages;
1903                 ring->page_size = HW_CMPD_RING_SIZE;
1904                 ring->pg_arr = (void **)cpr->cp_desc_ring;
1905                 ring->dma_arr = cpr->cp_desc_mapping;
1906                 ring->vmem_size = 0;
1907
1908                 rxr = bnapi->rx_ring;
1909                 if (!rxr)
1910                         goto skip_rx;
1911
1912                 ring = &rxr->rx_ring_struct;
1913                 ring->nr_pages = bp->rx_nr_pages;
1914                 ring->page_size = HW_RXBD_RING_SIZE;
1915                 ring->pg_arr = (void **)rxr->rx_desc_ring;
1916                 ring->dma_arr = rxr->rx_desc_mapping;
1917                 ring->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages;
1918                 ring->vmem = (void **)&rxr->rx_buf_ring;
1919
1920                 ring = &rxr->rx_agg_ring_struct;
1921                 ring->nr_pages = bp->rx_agg_nr_pages;
1922                 ring->page_size = HW_RXBD_RING_SIZE;
1923                 ring->pg_arr = (void **)rxr->rx_agg_desc_ring;
1924                 ring->dma_arr = rxr->rx_agg_desc_mapping;
1925                 ring->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages;
1926                 ring->vmem = (void **)&rxr->rx_agg_ring;
1927
1928 skip_rx:
1929                 txr = bnapi->tx_ring;
1930                 if (!txr)
1931                         continue;
1932
1933                 ring = &txr->tx_ring_struct;
1934                 ring->nr_pages = bp->tx_nr_pages;
1935                 ring->page_size = HW_RXBD_RING_SIZE;
1936                 ring->pg_arr = (void **)txr->tx_desc_ring;
1937                 ring->dma_arr = txr->tx_desc_mapping;
1938                 ring->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages;
1939                 ring->vmem = (void **)&txr->tx_buf_ring;
1940         }
1941 }
1942
1943 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type)
1944 {
1945         int i;
1946         u32 prod;
1947         struct rx_bd **rx_buf_ring;
1948
1949         rx_buf_ring = (struct rx_bd **)ring->pg_arr;
1950         for (i = 0, prod = 0; i < ring->nr_pages; i++) {
1951                 int j;
1952                 struct rx_bd *rxbd;
1953
1954                 rxbd = rx_buf_ring[i];
1955                 if (!rxbd)
1956                         continue;
1957
1958                 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) {
1959                         rxbd->rx_bd_len_flags_type = cpu_to_le32(type);
1960                         rxbd->rx_bd_opaque = prod;
1961                 }
1962         }
1963 }
1964
1965 static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr)
1966 {
1967         struct net_device *dev = bp->dev;
1968         struct bnxt_rx_ring_info *rxr;
1969         struct bnxt_ring_struct *ring;
1970         u32 prod, type;
1971         int i;
1972
1973         type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) |
1974                 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP;
1975
1976         if (NET_IP_ALIGN == 2)
1977                 type |= RX_BD_FLAGS_SOP;
1978
1979         rxr = &bp->rx_ring[ring_nr];
1980         ring = &rxr->rx_ring_struct;
1981         bnxt_init_rxbd_pages(ring, type);
1982
1983         prod = rxr->rx_prod;
1984         for (i = 0; i < bp->rx_ring_size; i++) {
1985                 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) {
1986                         netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n",
1987                                     ring_nr, i, bp->rx_ring_size);
1988                         break;
1989                 }
1990                 prod = NEXT_RX(prod);
1991         }
1992         rxr->rx_prod = prod;
1993         ring->fw_ring_id = INVALID_HW_RING_ID;
1994
1995         ring = &rxr->rx_agg_ring_struct;
1996         ring->fw_ring_id = INVALID_HW_RING_ID;
1997
1998         if (!(bp->flags & BNXT_FLAG_AGG_RINGS))
1999                 return 0;
2000
2001         type = ((u32)BNXT_RX_PAGE_SIZE << RX_BD_LEN_SHIFT) |
2002                 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP;
2003
2004         bnxt_init_rxbd_pages(ring, type);
2005
2006         prod = rxr->rx_agg_prod;
2007         for (i = 0; i < bp->rx_agg_ring_size; i++) {
2008                 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) {
2009                         netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n",
2010                                     ring_nr, i, bp->rx_ring_size);
2011                         break;
2012                 }
2013                 prod = NEXT_RX_AGG(prod);
2014         }
2015         rxr->rx_agg_prod = prod;
2016
2017         if (bp->flags & BNXT_FLAG_TPA) {
2018                 if (rxr->rx_tpa) {
2019                         u8 *data;
2020                         dma_addr_t mapping;
2021
2022                         for (i = 0; i < MAX_TPA; i++) {
2023                                 data = __bnxt_alloc_rx_data(bp, &mapping,
2024                                                             GFP_KERNEL);
2025                                 if (!data)
2026                                         return -ENOMEM;
2027
2028                                 rxr->rx_tpa[i].data = data;
2029                                 rxr->rx_tpa[i].mapping = mapping;
2030                         }
2031                 } else {
2032                         netdev_err(bp->dev, "No resource allocated for LRO/GRO\n");
2033                         return -ENOMEM;
2034                 }
2035         }
2036
2037         return 0;
2038 }
2039
2040 static int bnxt_init_rx_rings(struct bnxt *bp)
2041 {
2042         int i, rc = 0;
2043
2044         for (i = 0; i < bp->rx_nr_rings; i++) {
2045                 rc = bnxt_init_one_rx_ring(bp, i);
2046                 if (rc)
2047                         break;
2048         }
2049
2050         return rc;
2051 }
2052
2053 static int bnxt_init_tx_rings(struct bnxt *bp)
2054 {
2055         u16 i;
2056
2057         bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2,
2058                                    MAX_SKB_FRAGS + 1);
2059
2060         for (i = 0; i < bp->tx_nr_rings; i++) {
2061                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2062                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
2063
2064                 ring->fw_ring_id = INVALID_HW_RING_ID;
2065         }
2066
2067         return 0;
2068 }
2069
2070 static void bnxt_free_ring_grps(struct bnxt *bp)
2071 {
2072         kfree(bp->grp_info);
2073         bp->grp_info = NULL;
2074 }
2075
2076 static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init)
2077 {
2078         int i;
2079
2080         if (irq_re_init) {
2081                 bp->grp_info = kcalloc(bp->cp_nr_rings,
2082                                        sizeof(struct bnxt_ring_grp_info),
2083                                        GFP_KERNEL);
2084                 if (!bp->grp_info)
2085                         return -ENOMEM;
2086         }
2087         for (i = 0; i < bp->cp_nr_rings; i++) {
2088                 if (irq_re_init)
2089                         bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID;
2090                 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
2091                 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID;
2092                 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID;
2093                 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
2094         }
2095         return 0;
2096 }
2097
2098 static void bnxt_free_vnics(struct bnxt *bp)
2099 {
2100         kfree(bp->vnic_info);
2101         bp->vnic_info = NULL;
2102         bp->nr_vnics = 0;
2103 }
2104
2105 static int bnxt_alloc_vnics(struct bnxt *bp)
2106 {
2107         int num_vnics = 1;
2108
2109 #ifdef CONFIG_RFS_ACCEL
2110         if (bp->flags & BNXT_FLAG_RFS)
2111                 num_vnics += bp->rx_nr_rings;
2112 #endif
2113
2114         bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info),
2115                                 GFP_KERNEL);
2116         if (!bp->vnic_info)
2117                 return -ENOMEM;
2118
2119         bp->nr_vnics = num_vnics;
2120         return 0;
2121 }
2122
2123 static void bnxt_init_vnics(struct bnxt *bp)
2124 {
2125         int i;
2126
2127         for (i = 0; i < bp->nr_vnics; i++) {
2128                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2129
2130                 vnic->fw_vnic_id = INVALID_HW_RING_ID;
2131                 vnic->fw_rss_cos_lb_ctx = INVALID_HW_RING_ID;
2132                 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID;
2133
2134                 if (bp->vnic_info[i].rss_hash_key) {
2135                         if (i == 0)
2136                                 prandom_bytes(vnic->rss_hash_key,
2137                                               HW_HASH_KEY_SIZE);
2138                         else
2139                                 memcpy(vnic->rss_hash_key,
2140                                        bp->vnic_info[0].rss_hash_key,
2141                                        HW_HASH_KEY_SIZE);
2142                 }
2143         }
2144 }
2145
2146 static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg)
2147 {
2148         int pages;
2149
2150         pages = ring_size / desc_per_pg;
2151
2152         if (!pages)
2153                 return 1;
2154
2155         pages++;
2156
2157         while (pages & (pages - 1))
2158                 pages++;
2159
2160         return pages;
2161 }
2162
2163 static void bnxt_set_tpa_flags(struct bnxt *bp)
2164 {
2165         bp->flags &= ~BNXT_FLAG_TPA;
2166         if (bp->dev->features & NETIF_F_LRO)
2167                 bp->flags |= BNXT_FLAG_LRO;
2168         if ((bp->dev->features & NETIF_F_GRO) && (bp->pdev->revision > 0))
2169                 bp->flags |= BNXT_FLAG_GRO;
2170 }
2171
2172 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
2173  * be set on entry.
2174  */
2175 void bnxt_set_ring_params(struct bnxt *bp)
2176 {
2177         u32 ring_size, rx_size, rx_space;
2178         u32 agg_factor = 0, agg_ring_size = 0;
2179
2180         /* 8 for CRC and VLAN */
2181         rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8);
2182
2183         rx_space = rx_size + NET_SKB_PAD +
2184                 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2185
2186         bp->rx_copy_thresh = BNXT_RX_COPY_THRESH;
2187         ring_size = bp->rx_ring_size;
2188         bp->rx_agg_ring_size = 0;
2189         bp->rx_agg_nr_pages = 0;
2190
2191         if (bp->flags & BNXT_FLAG_TPA)
2192                 agg_factor = min_t(u32, 4, 65536 / BNXT_RX_PAGE_SIZE);
2193
2194         bp->flags &= ~BNXT_FLAG_JUMBO;
2195         if (rx_space > PAGE_SIZE) {
2196                 u32 jumbo_factor;
2197
2198                 bp->flags |= BNXT_FLAG_JUMBO;
2199                 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
2200                 if (jumbo_factor > agg_factor)
2201                         agg_factor = jumbo_factor;
2202         }
2203         agg_ring_size = ring_size * agg_factor;
2204
2205         if (agg_ring_size) {
2206                 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size,
2207                                                         RX_DESC_CNT);
2208                 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) {
2209                         u32 tmp = agg_ring_size;
2210
2211                         bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES;
2212                         agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1;
2213                         netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n",
2214                                     tmp, agg_ring_size);
2215                 }
2216                 bp->rx_agg_ring_size = agg_ring_size;
2217                 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1;
2218                 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN);
2219                 rx_space = rx_size + NET_SKB_PAD +
2220                         SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2221         }
2222
2223         bp->rx_buf_use_size = rx_size;
2224         bp->rx_buf_size = rx_space;
2225
2226         bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT);
2227         bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1;
2228
2229         ring_size = bp->tx_ring_size;
2230         bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT);
2231         bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1;
2232
2233         ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size;
2234         bp->cp_ring_size = ring_size;
2235
2236         bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT);
2237         if (bp->cp_nr_pages > MAX_CP_PAGES) {
2238                 bp->cp_nr_pages = MAX_CP_PAGES;
2239                 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1;
2240                 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n",
2241                             ring_size, bp->cp_ring_size);
2242         }
2243         bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT;
2244         bp->cp_ring_mask = bp->cp_bit - 1;
2245 }
2246
2247 static void bnxt_free_vnic_attributes(struct bnxt *bp)
2248 {
2249         int i;
2250         struct bnxt_vnic_info *vnic;
2251         struct pci_dev *pdev = bp->pdev;
2252
2253         if (!bp->vnic_info)
2254                 return;
2255
2256         for (i = 0; i < bp->nr_vnics; i++) {
2257                 vnic = &bp->vnic_info[i];
2258
2259                 kfree(vnic->fw_grp_ids);
2260                 vnic->fw_grp_ids = NULL;
2261
2262                 kfree(vnic->uc_list);
2263                 vnic->uc_list = NULL;
2264
2265                 if (vnic->mc_list) {
2266                         dma_free_coherent(&pdev->dev, vnic->mc_list_size,
2267                                           vnic->mc_list, vnic->mc_list_mapping);
2268                         vnic->mc_list = NULL;
2269                 }
2270
2271                 if (vnic->rss_table) {
2272                         dma_free_coherent(&pdev->dev, PAGE_SIZE,
2273                                           vnic->rss_table,
2274                                           vnic->rss_table_dma_addr);
2275                         vnic->rss_table = NULL;
2276                 }
2277
2278                 vnic->rss_hash_key = NULL;
2279                 vnic->flags = 0;
2280         }
2281 }
2282
2283 static int bnxt_alloc_vnic_attributes(struct bnxt *bp)
2284 {
2285         int i, rc = 0, size;
2286         struct bnxt_vnic_info *vnic;
2287         struct pci_dev *pdev = bp->pdev;
2288         int max_rings;
2289
2290         for (i = 0; i < bp->nr_vnics; i++) {
2291                 vnic = &bp->vnic_info[i];
2292
2293                 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) {
2294                         int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN;
2295
2296                         if (mem_size > 0) {
2297                                 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL);
2298                                 if (!vnic->uc_list) {
2299                                         rc = -ENOMEM;
2300                                         goto out;
2301                                 }
2302                         }
2303                 }
2304
2305                 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) {
2306                         vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN;
2307                         vnic->mc_list =
2308                                 dma_alloc_coherent(&pdev->dev,
2309                                                    vnic->mc_list_size,
2310                                                    &vnic->mc_list_mapping,
2311                                                    GFP_KERNEL);
2312                         if (!vnic->mc_list) {
2313                                 rc = -ENOMEM;
2314                                 goto out;
2315                         }
2316                 }
2317
2318                 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
2319                         max_rings = bp->rx_nr_rings;
2320                 else
2321                         max_rings = 1;
2322
2323                 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL);
2324                 if (!vnic->fw_grp_ids) {
2325                         rc = -ENOMEM;
2326                         goto out;
2327                 }
2328
2329                 /* Allocate rss table and hash key */
2330                 vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
2331                                                      &vnic->rss_table_dma_addr,
2332                                                      GFP_KERNEL);
2333                 if (!vnic->rss_table) {
2334                         rc = -ENOMEM;
2335                         goto out;
2336                 }
2337
2338                 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16));
2339
2340                 vnic->rss_hash_key = ((void *)vnic->rss_table) + size;
2341                 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size;
2342         }
2343         return 0;
2344
2345 out:
2346         return rc;
2347 }
2348
2349 static void bnxt_free_hwrm_resources(struct bnxt *bp)
2350 {
2351         struct pci_dev *pdev = bp->pdev;
2352
2353         dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr,
2354                           bp->hwrm_cmd_resp_dma_addr);
2355
2356         bp->hwrm_cmd_resp_addr = NULL;
2357         if (bp->hwrm_dbg_resp_addr) {
2358                 dma_free_coherent(&pdev->dev, HWRM_DBG_REG_BUF_SIZE,
2359                                   bp->hwrm_dbg_resp_addr,
2360                                   bp->hwrm_dbg_resp_dma_addr);
2361
2362                 bp->hwrm_dbg_resp_addr = NULL;
2363         }
2364 }
2365
2366 static int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2367 {
2368         struct pci_dev *pdev = bp->pdev;
2369
2370         bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
2371                                                    &bp->hwrm_cmd_resp_dma_addr,
2372                                                    GFP_KERNEL);
2373         if (!bp->hwrm_cmd_resp_addr)
2374                 return -ENOMEM;
2375         bp->hwrm_dbg_resp_addr = dma_alloc_coherent(&pdev->dev,
2376                                                     HWRM_DBG_REG_BUF_SIZE,
2377                                                     &bp->hwrm_dbg_resp_dma_addr,
2378                                                     GFP_KERNEL);
2379         if (!bp->hwrm_dbg_resp_addr)
2380                 netdev_warn(bp->dev, "fail to alloc debug register dma mem\n");
2381
2382         return 0;
2383 }
2384
2385 static void bnxt_free_stats(struct bnxt *bp)
2386 {
2387         u32 size, i;
2388         struct pci_dev *pdev = bp->pdev;
2389
2390         if (bp->hw_rx_port_stats) {
2391                 dma_free_coherent(&pdev->dev, bp->hw_port_stats_size,
2392                                   bp->hw_rx_port_stats,
2393                                   bp->hw_rx_port_stats_map);
2394                 bp->hw_rx_port_stats = NULL;
2395                 bp->flags &= ~BNXT_FLAG_PORT_STATS;
2396         }
2397
2398         if (!bp->bnapi)
2399                 return;
2400
2401         size = sizeof(struct ctx_hw_stats);
2402
2403         for (i = 0; i < bp->cp_nr_rings; i++) {
2404                 struct bnxt_napi *bnapi = bp->bnapi[i];
2405                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2406
2407                 if (cpr->hw_stats) {
2408                         dma_free_coherent(&pdev->dev, size, cpr->hw_stats,
2409                                           cpr->hw_stats_map);
2410                         cpr->hw_stats = NULL;
2411                 }
2412         }
2413 }
2414
2415 static int bnxt_alloc_stats(struct bnxt *bp)
2416 {
2417         u32 size, i;
2418         struct pci_dev *pdev = bp->pdev;
2419
2420         size = sizeof(struct ctx_hw_stats);
2421
2422         for (i = 0; i < bp->cp_nr_rings; i++) {
2423                 struct bnxt_napi *bnapi = bp->bnapi[i];
2424                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2425
2426                 cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size,
2427                                                    &cpr->hw_stats_map,
2428                                                    GFP_KERNEL);
2429                 if (!cpr->hw_stats)
2430                         return -ENOMEM;
2431
2432                 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
2433         }
2434
2435         if (BNXT_PF(bp)) {
2436                 bp->hw_port_stats_size = sizeof(struct rx_port_stats) +
2437                                          sizeof(struct tx_port_stats) + 1024;
2438
2439                 bp->hw_rx_port_stats =
2440                         dma_alloc_coherent(&pdev->dev, bp->hw_port_stats_size,
2441                                            &bp->hw_rx_port_stats_map,
2442                                            GFP_KERNEL);
2443                 if (!bp->hw_rx_port_stats)
2444                         return -ENOMEM;
2445
2446                 bp->hw_tx_port_stats = (void *)(bp->hw_rx_port_stats + 1) +
2447                                        512;
2448                 bp->hw_tx_port_stats_map = bp->hw_rx_port_stats_map +
2449                                            sizeof(struct rx_port_stats) + 512;
2450                 bp->flags |= BNXT_FLAG_PORT_STATS;
2451         }
2452         return 0;
2453 }
2454
2455 static void bnxt_clear_ring_indices(struct bnxt *bp)
2456 {
2457         int i;
2458
2459         if (!bp->bnapi)
2460                 return;
2461
2462         for (i = 0; i < bp->cp_nr_rings; i++) {
2463                 struct bnxt_napi *bnapi = bp->bnapi[i];
2464                 struct bnxt_cp_ring_info *cpr;
2465                 struct bnxt_rx_ring_info *rxr;
2466                 struct bnxt_tx_ring_info *txr;
2467
2468                 if (!bnapi)
2469                         continue;
2470
2471                 cpr = &bnapi->cp_ring;
2472                 cpr->cp_raw_cons = 0;
2473
2474                 txr = bnapi->tx_ring;
2475                 if (txr) {
2476                         txr->tx_prod = 0;
2477                         txr->tx_cons = 0;
2478                 }
2479
2480                 rxr = bnapi->rx_ring;
2481                 if (rxr) {
2482                         rxr->rx_prod = 0;
2483                         rxr->rx_agg_prod = 0;
2484                         rxr->rx_sw_agg_prod = 0;
2485                 }
2486         }
2487 }
2488
2489 static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit)
2490 {
2491 #ifdef CONFIG_RFS_ACCEL
2492         int i;
2493
2494         /* Under rtnl_lock and all our NAPIs have been disabled.  It's
2495          * safe to delete the hash table.
2496          */
2497         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
2498                 struct hlist_head *head;
2499                 struct hlist_node *tmp;
2500                 struct bnxt_ntuple_filter *fltr;
2501
2502                 head = &bp->ntp_fltr_hash_tbl[i];
2503                 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
2504                         hlist_del(&fltr->hash);
2505                         kfree(fltr);
2506                 }
2507         }
2508         if (irq_reinit) {
2509                 kfree(bp->ntp_fltr_bmap);
2510                 bp->ntp_fltr_bmap = NULL;
2511         }
2512         bp->ntp_fltr_count = 0;
2513 #endif
2514 }
2515
2516 static int bnxt_alloc_ntp_fltrs(struct bnxt *bp)
2517 {
2518 #ifdef CONFIG_RFS_ACCEL
2519         int i, rc = 0;
2520
2521         if (!(bp->flags & BNXT_FLAG_RFS))
2522                 return 0;
2523
2524         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++)
2525                 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]);
2526
2527         bp->ntp_fltr_count = 0;
2528         bp->ntp_fltr_bmap = kzalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR),
2529                                     GFP_KERNEL);
2530
2531         if (!bp->ntp_fltr_bmap)
2532                 rc = -ENOMEM;
2533
2534         return rc;
2535 #else
2536         return 0;
2537 #endif
2538 }
2539
2540 static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init)
2541 {
2542         bnxt_free_vnic_attributes(bp);
2543         bnxt_free_tx_rings(bp);
2544         bnxt_free_rx_rings(bp);
2545         bnxt_free_cp_rings(bp);
2546         bnxt_free_ntp_fltrs(bp, irq_re_init);
2547         if (irq_re_init) {
2548                 bnxt_free_stats(bp);
2549                 bnxt_free_ring_grps(bp);
2550                 bnxt_free_vnics(bp);
2551                 kfree(bp->tx_ring);
2552                 bp->tx_ring = NULL;
2553                 kfree(bp->rx_ring);
2554                 bp->rx_ring = NULL;
2555                 kfree(bp->bnapi);
2556                 bp->bnapi = NULL;
2557         } else {
2558                 bnxt_clear_ring_indices(bp);
2559         }
2560 }
2561
2562 static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init)
2563 {
2564         int i, j, rc, size, arr_size;
2565         void *bnapi;
2566
2567         if (irq_re_init) {
2568                 /* Allocate bnapi mem pointer array and mem block for
2569                  * all queues
2570                  */
2571                 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) *
2572                                 bp->cp_nr_rings);
2573                 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi));
2574                 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL);
2575                 if (!bnapi)
2576                         return -ENOMEM;
2577
2578                 bp->bnapi = bnapi;
2579                 bnapi += arr_size;
2580                 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) {
2581                         bp->bnapi[i] = bnapi;
2582                         bp->bnapi[i]->index = i;
2583                         bp->bnapi[i]->bp = bp;
2584                 }
2585
2586                 bp->rx_ring = kcalloc(bp->rx_nr_rings,
2587                                       sizeof(struct bnxt_rx_ring_info),
2588                                       GFP_KERNEL);
2589                 if (!bp->rx_ring)
2590                         return -ENOMEM;
2591
2592                 for (i = 0; i < bp->rx_nr_rings; i++) {
2593                         bp->rx_ring[i].bnapi = bp->bnapi[i];
2594                         bp->bnapi[i]->rx_ring = &bp->rx_ring[i];
2595                 }
2596
2597                 bp->tx_ring = kcalloc(bp->tx_nr_rings,
2598                                       sizeof(struct bnxt_tx_ring_info),
2599                                       GFP_KERNEL);
2600                 if (!bp->tx_ring)
2601                         return -ENOMEM;
2602
2603                 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
2604                         j = 0;
2605                 else
2606                         j = bp->rx_nr_rings;
2607
2608                 for (i = 0; i < bp->tx_nr_rings; i++, j++) {
2609                         bp->tx_ring[i].bnapi = bp->bnapi[j];
2610                         bp->bnapi[j]->tx_ring = &bp->tx_ring[i];
2611                 }
2612
2613                 rc = bnxt_alloc_stats(bp);
2614                 if (rc)
2615                         goto alloc_mem_err;
2616
2617                 rc = bnxt_alloc_ntp_fltrs(bp);
2618                 if (rc)
2619                         goto alloc_mem_err;
2620
2621                 rc = bnxt_alloc_vnics(bp);
2622                 if (rc)
2623                         goto alloc_mem_err;
2624         }
2625
2626         bnxt_init_ring_struct(bp);
2627
2628         rc = bnxt_alloc_rx_rings(bp);
2629         if (rc)
2630                 goto alloc_mem_err;
2631
2632         rc = bnxt_alloc_tx_rings(bp);
2633         if (rc)
2634                 goto alloc_mem_err;
2635
2636         rc = bnxt_alloc_cp_rings(bp);
2637         if (rc)
2638                 goto alloc_mem_err;
2639
2640         bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG |
2641                                   BNXT_VNIC_UCAST_FLAG;
2642         rc = bnxt_alloc_vnic_attributes(bp);
2643         if (rc)
2644                 goto alloc_mem_err;
2645         return 0;
2646
2647 alloc_mem_err:
2648         bnxt_free_mem(bp, true);
2649         return rc;
2650 }
2651
2652 void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type,
2653                             u16 cmpl_ring, u16 target_id)
2654 {
2655         struct input *req = request;
2656
2657         req->req_type = cpu_to_le16(req_type);
2658         req->cmpl_ring = cpu_to_le16(cmpl_ring);
2659         req->target_id = cpu_to_le16(target_id);
2660         req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr);
2661 }
2662
2663 static int bnxt_hwrm_do_send_msg(struct bnxt *bp, void *msg, u32 msg_len,
2664                                  int timeout, bool silent)
2665 {
2666         int i, intr_process, rc;
2667         struct input *req = msg;
2668         u32 *data = msg;
2669         __le32 *resp_len, *valid;
2670         u16 cp_ring_id, len = 0;
2671         struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr;
2672
2673         req->seq_id = cpu_to_le16(bp->hwrm_cmd_seq++);
2674         memset(resp, 0, PAGE_SIZE);
2675         cp_ring_id = le16_to_cpu(req->cmpl_ring);
2676         intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1;
2677
2678         /* Write request msg to hwrm channel */
2679         __iowrite32_copy(bp->bar0, data, msg_len / 4);
2680
2681         for (i = msg_len; i < BNXT_HWRM_MAX_REQ_LEN; i += 4)
2682                 writel(0, bp->bar0 + i);
2683
2684         /* currently supports only one outstanding message */
2685         if (intr_process)
2686                 bp->hwrm_intr_seq_id = le16_to_cpu(req->seq_id);
2687
2688         /* Ring channel doorbell */
2689         writel(1, bp->bar0 + 0x100);
2690
2691         if (!timeout)
2692                 timeout = DFLT_HWRM_CMD_TIMEOUT;
2693
2694         i = 0;
2695         if (intr_process) {
2696                 /* Wait until hwrm response cmpl interrupt is processed */
2697                 while (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID &&
2698                        i++ < timeout) {
2699                         usleep_range(600, 800);
2700                 }
2701
2702                 if (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID) {
2703                         netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n",
2704                                    le16_to_cpu(req->req_type));
2705                         return -1;
2706                 }
2707         } else {
2708                 /* Check if response len is updated */
2709                 resp_len = bp->hwrm_cmd_resp_addr + HWRM_RESP_LEN_OFFSET;
2710                 for (i = 0; i < timeout; i++) {
2711                         len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
2712                               HWRM_RESP_LEN_SFT;
2713                         if (len)
2714                                 break;
2715                         usleep_range(600, 800);
2716                 }
2717
2718                 if (i >= timeout) {
2719                         netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
2720                                    timeout, le16_to_cpu(req->req_type),
2721                                    le16_to_cpu(req->seq_id), *resp_len);
2722                         return -1;
2723                 }
2724
2725                 /* Last word of resp contains valid bit */
2726                 valid = bp->hwrm_cmd_resp_addr + len - 4;
2727                 for (i = 0; i < timeout; i++) {
2728                         if (le32_to_cpu(*valid) & HWRM_RESP_VALID_MASK)
2729                                 break;
2730                         usleep_range(600, 800);
2731                 }
2732
2733                 if (i >= timeout) {
2734                         netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
2735                                    timeout, le16_to_cpu(req->req_type),
2736                                    le16_to_cpu(req->seq_id), len, *valid);
2737                         return -1;
2738                 }
2739         }
2740
2741         rc = le16_to_cpu(resp->error_code);
2742         if (rc && !silent)
2743                 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
2744                            le16_to_cpu(resp->req_type),
2745                            le16_to_cpu(resp->seq_id), rc);
2746         return rc;
2747 }
2748
2749 int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
2750 {
2751         return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, false);
2752 }
2753
2754 int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
2755 {
2756         int rc;
2757
2758         mutex_lock(&bp->hwrm_cmd_lock);
2759         rc = _hwrm_send_message(bp, msg, msg_len, timeout);
2760         mutex_unlock(&bp->hwrm_cmd_lock);
2761         return rc;
2762 }
2763
2764 int hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
2765                              int timeout)
2766 {
2767         int rc;
2768
2769         mutex_lock(&bp->hwrm_cmd_lock);
2770         rc = bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
2771         mutex_unlock(&bp->hwrm_cmd_lock);
2772         return rc;
2773 }
2774
2775 static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp)
2776 {
2777         struct hwrm_func_drv_rgtr_input req = {0};
2778         int i;
2779
2780         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
2781
2782         req.enables =
2783                 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE |
2784                             FUNC_DRV_RGTR_REQ_ENABLES_VER |
2785                             FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
2786
2787         /* TODO: current async event fwd bits are not defined and the firmware
2788          * only checks if it is non-zero to enable async event forwarding
2789          */
2790         req.async_event_fwd[0] |= cpu_to_le32(1);
2791         req.os_type = cpu_to_le16(1);
2792         req.ver_maj = DRV_VER_MAJ;
2793         req.ver_min = DRV_VER_MIN;
2794         req.ver_upd = DRV_VER_UPD;
2795
2796         if (BNXT_PF(bp)) {
2797                 DECLARE_BITMAP(vf_req_snif_bmap, 256);
2798                 u32 *data = (u32 *)vf_req_snif_bmap;
2799
2800                 memset(vf_req_snif_bmap, 0, sizeof(vf_req_snif_bmap));
2801                 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++)
2802                         __set_bit(bnxt_vf_req_snif[i], vf_req_snif_bmap);
2803
2804                 for (i = 0; i < 8; i++)
2805                         req.vf_req_fwd[i] = cpu_to_le32(data[i]);
2806
2807                 req.enables |=
2808                         cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD);
2809         }
2810
2811         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2812 }
2813
2814 static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp)
2815 {
2816         struct hwrm_func_drv_unrgtr_input req = {0};
2817
2818         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1);
2819         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2820 }
2821
2822 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type)
2823 {
2824         u32 rc = 0;
2825         struct hwrm_tunnel_dst_port_free_input req = {0};
2826
2827         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1);
2828         req.tunnel_type = tunnel_type;
2829
2830         switch (tunnel_type) {
2831         case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN:
2832                 req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id;
2833                 break;
2834         case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE:
2835                 req.tunnel_dst_port_id = bp->nge_fw_dst_port_id;
2836                 break;
2837         default:
2838                 break;
2839         }
2840
2841         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2842         if (rc)
2843                 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
2844                            rc);
2845         return rc;
2846 }
2847
2848 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port,
2849                                            u8 tunnel_type)
2850 {
2851         u32 rc = 0;
2852         struct hwrm_tunnel_dst_port_alloc_input req = {0};
2853         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
2854
2855         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1);
2856
2857         req.tunnel_type = tunnel_type;
2858         req.tunnel_dst_port_val = port;
2859
2860         mutex_lock(&bp->hwrm_cmd_lock);
2861         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2862         if (rc) {
2863                 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
2864                            rc);
2865                 goto err_out;
2866         }
2867
2868         if (tunnel_type & TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN)
2869                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
2870
2871         else if (tunnel_type & TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE)
2872                 bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id;
2873 err_out:
2874         mutex_unlock(&bp->hwrm_cmd_lock);
2875         return rc;
2876 }
2877
2878 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id)
2879 {
2880         struct hwrm_cfa_l2_set_rx_mask_input req = {0};
2881         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2882
2883         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1);
2884         req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
2885
2886         req.num_mc_entries = cpu_to_le32(vnic->mc_list_count);
2887         req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping);
2888         req.mask = cpu_to_le32(vnic->rx_mask);
2889         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2890 }
2891
2892 #ifdef CONFIG_RFS_ACCEL
2893 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,
2894                                             struct bnxt_ntuple_filter *fltr)
2895 {
2896         struct hwrm_cfa_ntuple_filter_free_input req = {0};
2897
2898         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1);
2899         req.ntuple_filter_id = fltr->filter_id;
2900         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2901 }
2902
2903 #define BNXT_NTP_FLTR_FLAGS                                     \
2904         (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID |     \
2905          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE |        \
2906          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR |      \
2907          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE |      \
2908          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR |       \
2909          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK |  \
2910          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR |       \
2911          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK |  \
2912          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL |      \
2913          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT |         \
2914          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK |    \
2915          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT |         \
2916          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK |    \
2917          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID)
2918
2919 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,
2920                                              struct bnxt_ntuple_filter *fltr)
2921 {
2922         int rc = 0;
2923         struct hwrm_cfa_ntuple_filter_alloc_input req = {0};
2924         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
2925                 bp->hwrm_cmd_resp_addr;
2926         struct flow_keys *keys = &fltr->fkeys;
2927         struct bnxt_vnic_info *vnic = &bp->vnic_info[fltr->rxq + 1];
2928
2929         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1);
2930         req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[0];
2931
2932         req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS);
2933
2934         req.ethertype = htons(ETH_P_IP);
2935         memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN);
2936         req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4;
2937         req.ip_protocol = keys->basic.ip_proto;
2938
2939         req.src_ipaddr[0] = keys->addrs.v4addrs.src;
2940         req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
2941         req.dst_ipaddr[0] = keys->addrs.v4addrs.dst;
2942         req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
2943
2944         req.src_port = keys->ports.src;
2945         req.src_port_mask = cpu_to_be16(0xffff);
2946         req.dst_port = keys->ports.dst;
2947         req.dst_port_mask = cpu_to_be16(0xffff);
2948
2949         req.dst_id = cpu_to_le16(vnic->fw_vnic_id);
2950         mutex_lock(&bp->hwrm_cmd_lock);
2951         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2952         if (!rc)
2953                 fltr->filter_id = resp->ntuple_filter_id;
2954         mutex_unlock(&bp->hwrm_cmd_lock);
2955         return rc;
2956 }
2957 #endif
2958
2959 static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx,
2960                                      u8 *mac_addr)
2961 {
2962         u32 rc = 0;
2963         struct hwrm_cfa_l2_filter_alloc_input req = {0};
2964         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
2965
2966         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1);
2967         req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX |
2968                                 CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST);
2969         req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id);
2970         req.enables =
2971                 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR |
2972                             CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID |
2973                             CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK);
2974         memcpy(req.l2_addr, mac_addr, ETH_ALEN);
2975         req.l2_addr_mask[0] = 0xff;
2976         req.l2_addr_mask[1] = 0xff;
2977         req.l2_addr_mask[2] = 0xff;
2978         req.l2_addr_mask[3] = 0xff;
2979         req.l2_addr_mask[4] = 0xff;
2980         req.l2_addr_mask[5] = 0xff;
2981
2982         mutex_lock(&bp->hwrm_cmd_lock);
2983         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2984         if (!rc)
2985                 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] =
2986                                                         resp->l2_filter_id;
2987         mutex_unlock(&bp->hwrm_cmd_lock);
2988         return rc;
2989 }
2990
2991 static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp)
2992 {
2993         u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */
2994         int rc = 0;
2995
2996         /* Any associated ntuple filters will also be cleared by firmware. */
2997         mutex_lock(&bp->hwrm_cmd_lock);
2998         for (i = 0; i < num_of_vnics; i++) {
2999                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3000
3001                 for (j = 0; j < vnic->uc_filter_count; j++) {
3002                         struct hwrm_cfa_l2_filter_free_input req = {0};
3003
3004                         bnxt_hwrm_cmd_hdr_init(bp, &req,
3005                                                HWRM_CFA_L2_FILTER_FREE, -1, -1);
3006
3007                         req.l2_filter_id = vnic->fw_l2_filter_id[j];
3008
3009                         rc = _hwrm_send_message(bp, &req, sizeof(req),
3010                                                 HWRM_CMD_TIMEOUT);
3011                 }
3012                 vnic->uc_filter_count = 0;
3013         }
3014         mutex_unlock(&bp->hwrm_cmd_lock);
3015
3016         return rc;
3017 }
3018
3019 static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags)
3020 {
3021         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3022         struct hwrm_vnic_tpa_cfg_input req = {0};
3023
3024         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1);
3025
3026         if (tpa_flags) {
3027                 u16 mss = bp->dev->mtu - 40;
3028                 u32 nsegs, n, segs = 0, flags;
3029
3030                 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA |
3031                         VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA |
3032                         VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE |
3033                         VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN |
3034                         VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ;
3035                 if (tpa_flags & BNXT_FLAG_GRO)
3036                         flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO;
3037
3038                 req.flags = cpu_to_le32(flags);
3039
3040                 req.enables =
3041                         cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS |
3042                                     VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS |
3043                                     VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN);
3044
3045                 /* Number of segs are log2 units, and first packet is not
3046                  * included as part of this units.
3047                  */
3048                 if (mss <= BNXT_RX_PAGE_SIZE) {
3049                         n = BNXT_RX_PAGE_SIZE / mss;
3050                         nsegs = (MAX_SKB_FRAGS - 1) * n;
3051                 } else {
3052                         n = mss / BNXT_RX_PAGE_SIZE;
3053                         if (mss & (BNXT_RX_PAGE_SIZE - 1))
3054                                 n++;
3055                         nsegs = (MAX_SKB_FRAGS - n) / n;
3056                 }
3057
3058                 segs = ilog2(nsegs);
3059                 req.max_agg_segs = cpu_to_le16(segs);
3060                 req.max_aggs = cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX);
3061
3062                 req.min_agg_len = cpu_to_le32(512);
3063         }
3064         req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
3065
3066         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3067 }
3068
3069 static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss)
3070 {
3071         u32 i, j, max_rings;
3072         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3073         struct hwrm_vnic_rss_cfg_input req = {0};
3074
3075         if (vnic->fw_rss_cos_lb_ctx == INVALID_HW_RING_ID)
3076                 return 0;
3077
3078         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
3079         if (set_rss) {
3080                 vnic->hash_type = BNXT_RSS_HASH_TYPE_FLAG_IPV4 |
3081                                  BNXT_RSS_HASH_TYPE_FLAG_TCP_IPV4 |
3082                                  BNXT_RSS_HASH_TYPE_FLAG_IPV6 |
3083                                  BNXT_RSS_HASH_TYPE_FLAG_TCP_IPV6;
3084
3085                 req.hash_type = cpu_to_le32(vnic->hash_type);
3086
3087                 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
3088                         max_rings = bp->rx_nr_rings;
3089                 else
3090                         max_rings = 1;
3091
3092                 /* Fill the RSS indirection table with ring group ids */
3093                 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) {
3094                         if (j == max_rings)
3095                                 j = 0;
3096                         vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]);
3097                 }
3098
3099                 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
3100                 req.hash_key_tbl_addr =
3101                         cpu_to_le64(vnic->rss_hash_key_dma_addr);
3102         }
3103         req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx);
3104         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3105 }
3106
3107 static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id)
3108 {
3109         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3110         struct hwrm_vnic_plcmodes_cfg_input req = {0};
3111
3112         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1);
3113         req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT |
3114                                 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 |
3115                                 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6);
3116         req.enables =
3117                 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID |
3118                             VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID);
3119         /* thresholds not implemented in firmware yet */
3120         req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh);
3121         req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh);
3122         req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
3123         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3124 }
3125
3126 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id)
3127 {
3128         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0};
3129
3130         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1);
3131         req.rss_cos_lb_ctx_id =
3132                 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx);
3133
3134         hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3135         bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx = INVALID_HW_RING_ID;
3136 }
3137
3138 static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp)
3139 {
3140         int i;
3141
3142         for (i = 0; i < bp->nr_vnics; i++) {
3143                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3144
3145                 if (vnic->fw_rss_cos_lb_ctx != INVALID_HW_RING_ID)
3146                         bnxt_hwrm_vnic_ctx_free_one(bp, i);
3147         }
3148         bp->rsscos_nr_ctxs = 0;
3149 }
3150
3151 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id)
3152 {
3153         int rc;
3154         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0};
3155         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
3156                                                 bp->hwrm_cmd_resp_addr;
3157
3158         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1,
3159                                -1);
3160
3161         mutex_lock(&bp->hwrm_cmd_lock);
3162         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3163         if (!rc)
3164                 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx =
3165                         le16_to_cpu(resp->rss_cos_lb_ctx_id);
3166         mutex_unlock(&bp->hwrm_cmd_lock);
3167
3168         return rc;
3169 }
3170
3171 static int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id)
3172 {
3173         unsigned int ring = 0, grp_idx;
3174         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3175         struct hwrm_vnic_cfg_input req = {0};
3176
3177         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1);
3178         /* Only RSS support for now TBD: COS & LB */
3179         req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP |
3180                                   VNIC_CFG_REQ_ENABLES_RSS_RULE);
3181         req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx);
3182         req.cos_rule = cpu_to_le16(0xffff);
3183         if (vnic->flags & BNXT_VNIC_RSS_FLAG)
3184                 ring = 0;
3185         else if (vnic->flags & BNXT_VNIC_RFS_FLAG)
3186                 ring = vnic_id - 1;
3187
3188         grp_idx = bp->rx_ring[ring].bnapi->index;
3189         req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
3190         req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id);
3191
3192         req.lb_rule = cpu_to_le16(0xffff);
3193         req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + ETH_FCS_LEN +
3194                               VLAN_HLEN);
3195
3196         if (bp->flags & BNXT_FLAG_STRIP_VLAN)
3197                 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE);
3198
3199         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3200 }
3201
3202 static int bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id)
3203 {
3204         u32 rc = 0;
3205
3206         if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) {
3207                 struct hwrm_vnic_free_input req = {0};
3208
3209                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1);
3210                 req.vnic_id =
3211                         cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id);
3212
3213                 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3214                 if (rc)
3215                         return rc;
3216                 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID;
3217         }
3218         return rc;
3219 }
3220
3221 static void bnxt_hwrm_vnic_free(struct bnxt *bp)
3222 {
3223         u16 i;
3224
3225         for (i = 0; i < bp->nr_vnics; i++)
3226                 bnxt_hwrm_vnic_free_one(bp, i);
3227 }
3228
3229 static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id,
3230                                 unsigned int start_rx_ring_idx,
3231                                 unsigned int nr_rings)
3232 {
3233         int rc = 0;
3234         unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings;
3235         struct hwrm_vnic_alloc_input req = {0};
3236         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3237
3238         /* map ring groups to this vnic */
3239         for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) {
3240                 grp_idx = bp->rx_ring[i].bnapi->index;
3241                 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) {
3242                         netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n",
3243                                    j, nr_rings);
3244                         break;
3245                 }
3246                 bp->vnic_info[vnic_id].fw_grp_ids[j] =
3247                                         bp->grp_info[grp_idx].fw_grp_id;
3248         }
3249
3250         bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx = INVALID_HW_RING_ID;
3251         if (vnic_id == 0)
3252                 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT);
3253
3254         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1);
3255
3256         mutex_lock(&bp->hwrm_cmd_lock);
3257         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3258         if (!rc)
3259                 bp->vnic_info[vnic_id].fw_vnic_id = le32_to_cpu(resp->vnic_id);
3260         mutex_unlock(&bp->hwrm_cmd_lock);
3261         return rc;
3262 }
3263
3264 static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp)
3265 {
3266         u16 i;
3267         u32 rc = 0;
3268
3269         mutex_lock(&bp->hwrm_cmd_lock);
3270         for (i = 0; i < bp->rx_nr_rings; i++) {
3271                 struct hwrm_ring_grp_alloc_input req = {0};
3272                 struct hwrm_ring_grp_alloc_output *resp =
3273                                         bp->hwrm_cmd_resp_addr;
3274                 unsigned int grp_idx = bp->rx_ring[i].bnapi->index;
3275
3276                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1);
3277
3278                 req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id);
3279                 req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id);
3280                 req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id);
3281                 req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx);
3282
3283                 rc = _hwrm_send_message(bp, &req, sizeof(req),
3284                                         HWRM_CMD_TIMEOUT);
3285                 if (rc)
3286                         break;
3287
3288                 bp->grp_info[grp_idx].fw_grp_id =
3289                         le32_to_cpu(resp->ring_group_id);
3290         }
3291         mutex_unlock(&bp->hwrm_cmd_lock);
3292         return rc;
3293 }
3294
3295 static int bnxt_hwrm_ring_grp_free(struct bnxt *bp)
3296 {
3297         u16 i;
3298         u32 rc = 0;
3299         struct hwrm_ring_grp_free_input req = {0};
3300
3301         if (!bp->grp_info)
3302                 return 0;
3303
3304         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1);
3305
3306         mutex_lock(&bp->hwrm_cmd_lock);
3307         for (i = 0; i < bp->cp_nr_rings; i++) {
3308                 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID)
3309                         continue;
3310                 req.ring_group_id =
3311                         cpu_to_le32(bp->grp_info[i].fw_grp_id);
3312
3313                 rc = _hwrm_send_message(bp, &req, sizeof(req),
3314                                         HWRM_CMD_TIMEOUT);
3315                 if (rc)
3316                         break;
3317                 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
3318         }
3319         mutex_unlock(&bp->hwrm_cmd_lock);
3320         return rc;
3321 }
3322
3323 static int hwrm_ring_alloc_send_msg(struct bnxt *bp,
3324                                     struct bnxt_ring_struct *ring,
3325                                     u32 ring_type, u32 map_index,
3326                                     u32 stats_ctx_id)
3327 {
3328         int rc = 0, err = 0;
3329         struct hwrm_ring_alloc_input req = {0};
3330         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3331         u16 ring_id;
3332
3333         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1);
3334
3335         req.enables = 0;
3336         if (ring->nr_pages > 1) {
3337                 req.page_tbl_addr = cpu_to_le64(ring->pg_tbl_map);
3338                 /* Page size is in log2 units */
3339                 req.page_size = BNXT_PAGE_SHIFT;
3340                 req.page_tbl_depth = 1;
3341         } else {
3342                 req.page_tbl_addr =  cpu_to_le64(ring->dma_arr[0]);
3343         }
3344         req.fbo = 0;
3345         /* Association of ring index with doorbell index and MSIX number */
3346         req.logical_id = cpu_to_le16(map_index);
3347
3348         switch (ring_type) {
3349         case HWRM_RING_ALLOC_TX:
3350                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX;
3351                 /* Association of transmit ring with completion ring */
3352                 req.cmpl_ring_id =
3353                         cpu_to_le16(bp->grp_info[map_index].cp_fw_ring_id);
3354                 req.length = cpu_to_le32(bp->tx_ring_mask + 1);
3355                 req.stat_ctx_id = cpu_to_le32(stats_ctx_id);
3356                 req.queue_id = cpu_to_le16(ring->queue_id);
3357                 break;
3358         case HWRM_RING_ALLOC_RX:
3359                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
3360                 req.length = cpu_to_le32(bp->rx_ring_mask + 1);
3361                 break;
3362         case HWRM_RING_ALLOC_AGG:
3363                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
3364                 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1);
3365                 break;
3366         case HWRM_RING_ALLOC_CMPL:
3367                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_CMPL;
3368                 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
3369                 if (bp->flags & BNXT_FLAG_USING_MSIX)
3370                         req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
3371                 break;
3372         default:
3373                 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n",
3374                            ring_type);
3375                 return -1;
3376         }
3377
3378         mutex_lock(&bp->hwrm_cmd_lock);
3379         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3380         err = le16_to_cpu(resp->error_code);
3381         ring_id = le16_to_cpu(resp->ring_id);
3382         mutex_unlock(&bp->hwrm_cmd_lock);
3383
3384         if (rc || err) {
3385                 switch (ring_type) {
3386                 case RING_FREE_REQ_RING_TYPE_CMPL:
3387                         netdev_err(bp->dev, "hwrm_ring_alloc cp failed. rc:%x err:%x\n",
3388                                    rc, err);
3389                         return -1;
3390
3391                 case RING_FREE_REQ_RING_TYPE_RX:
3392                         netdev_err(bp->dev, "hwrm_ring_alloc rx failed. rc:%x err:%x\n",
3393                                    rc, err);
3394                         return -1;
3395
3396                 case RING_FREE_REQ_RING_TYPE_TX:
3397                         netdev_err(bp->dev, "hwrm_ring_alloc tx failed. rc:%x err:%x\n",
3398                                    rc, err);
3399                         return -1;
3400
3401                 default:
3402                         netdev_err(bp->dev, "Invalid ring\n");
3403                         return -1;
3404                 }
3405         }
3406         ring->fw_ring_id = ring_id;
3407         return rc;
3408 }
3409
3410 static int bnxt_hwrm_ring_alloc(struct bnxt *bp)
3411 {
3412         int i, rc = 0;
3413
3414         for (i = 0; i < bp->cp_nr_rings; i++) {
3415                 struct bnxt_napi *bnapi = bp->bnapi[i];
3416                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3417                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3418
3419                 cpr->cp_doorbell = bp->bar1 + i * 0x80;
3420                 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_CMPL, i,
3421                                               INVALID_STATS_CTX_ID);
3422                 if (rc)
3423                         goto err_out;
3424                 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
3425                 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id;
3426         }
3427
3428         for (i = 0; i < bp->tx_nr_rings; i++) {
3429                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
3430                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
3431                 u32 map_idx = txr->bnapi->index;
3432                 u16 fw_stats_ctx = bp->grp_info[map_idx].fw_stats_ctx;
3433
3434                 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_TX,
3435                                               map_idx, fw_stats_ctx);
3436                 if (rc)
3437                         goto err_out;
3438                 txr->tx_doorbell = bp->bar1 + map_idx * 0x80;
3439         }
3440
3441         for (i = 0; i < bp->rx_nr_rings; i++) {
3442                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3443                 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
3444                 u32 map_idx = rxr->bnapi->index;
3445
3446                 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_RX,
3447                                               map_idx, INVALID_STATS_CTX_ID);
3448                 if (rc)
3449                         goto err_out;
3450                 rxr->rx_doorbell = bp->bar1 + map_idx * 0x80;
3451                 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
3452                 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id;
3453         }
3454
3455         if (bp->flags & BNXT_FLAG_AGG_RINGS) {
3456                 for (i = 0; i < bp->rx_nr_rings; i++) {
3457                         struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3458                         struct bnxt_ring_struct *ring =
3459                                                 &rxr->rx_agg_ring_struct;
3460                         u32 grp_idx = rxr->bnapi->index;
3461                         u32 map_idx = grp_idx + bp->rx_nr_rings;
3462
3463                         rc = hwrm_ring_alloc_send_msg(bp, ring,
3464                                                       HWRM_RING_ALLOC_AGG,
3465                                                       map_idx,
3466                                                       INVALID_STATS_CTX_ID);
3467                         if (rc)
3468                                 goto err_out;
3469
3470                         rxr->rx_agg_doorbell = bp->bar1 + map_idx * 0x80;
3471                         writel(DB_KEY_RX | rxr->rx_agg_prod,
3472                                rxr->rx_agg_doorbell);
3473                         bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id;
3474                 }
3475         }
3476 err_out:
3477         return rc;
3478 }
3479
3480 static int hwrm_ring_free_send_msg(struct bnxt *bp,
3481                                    struct bnxt_ring_struct *ring,
3482                                    u32 ring_type, int cmpl_ring_id)
3483 {
3484         int rc;
3485         struct hwrm_ring_free_input req = {0};
3486         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
3487         u16 error_code;
3488
3489         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, cmpl_ring_id, -1);
3490         req.ring_type = ring_type;
3491         req.ring_id = cpu_to_le16(ring->fw_ring_id);
3492
3493         mutex_lock(&bp->hwrm_cmd_lock);
3494         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3495         error_code = le16_to_cpu(resp->error_code);
3496         mutex_unlock(&bp->hwrm_cmd_lock);
3497
3498         if (rc || error_code) {
3499                 switch (ring_type) {
3500                 case RING_FREE_REQ_RING_TYPE_CMPL:
3501                         netdev_err(bp->dev, "hwrm_ring_free cp failed. rc:%d\n",
3502                                    rc);
3503                         return rc;
3504                 case RING_FREE_REQ_RING_TYPE_RX:
3505                         netdev_err(bp->dev, "hwrm_ring_free rx failed. rc:%d\n",
3506                                    rc);
3507                         return rc;
3508                 case RING_FREE_REQ_RING_TYPE_TX:
3509                         netdev_err(bp->dev, "hwrm_ring_free tx failed. rc:%d\n",
3510                                    rc);
3511                         return rc;
3512                 default:
3513                         netdev_err(bp->dev, "Invalid ring\n");
3514                         return -1;
3515                 }
3516         }
3517         return 0;
3518 }
3519
3520 static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)
3521 {
3522         int i;
3523
3524         if (!bp->bnapi)
3525                 return;
3526
3527         for (i = 0; i < bp->tx_nr_rings; i++) {
3528                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
3529                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
3530                 u32 grp_idx = txr->bnapi->index;
3531                 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
3532
3533                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3534                         hwrm_ring_free_send_msg(bp, ring,
3535                                                 RING_FREE_REQ_RING_TYPE_TX,
3536                                                 close_path ? cmpl_ring_id :
3537                                                 INVALID_HW_RING_ID);
3538                         ring->fw_ring_id = INVALID_HW_RING_ID;
3539                 }
3540         }
3541
3542         for (i = 0; i < bp->rx_nr_rings; i++) {
3543                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3544                 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
3545                 u32 grp_idx = rxr->bnapi->index;
3546                 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
3547
3548                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3549                         hwrm_ring_free_send_msg(bp, ring,
3550                                                 RING_FREE_REQ_RING_TYPE_RX,
3551                                                 close_path ? cmpl_ring_id :
3552                                                 INVALID_HW_RING_ID);
3553                         ring->fw_ring_id = INVALID_HW_RING_ID;
3554                         bp->grp_info[grp_idx].rx_fw_ring_id =
3555                                 INVALID_HW_RING_ID;
3556                 }
3557         }
3558
3559         for (i = 0; i < bp->rx_nr_rings; i++) {
3560                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3561                 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct;
3562                 u32 grp_idx = rxr->bnapi->index;
3563                 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
3564
3565                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3566                         hwrm_ring_free_send_msg(bp, ring,
3567                                                 RING_FREE_REQ_RING_TYPE_RX,
3568                                                 close_path ? cmpl_ring_id :
3569                                                 INVALID_HW_RING_ID);
3570                         ring->fw_ring_id = INVALID_HW_RING_ID;
3571                         bp->grp_info[grp_idx].agg_fw_ring_id =
3572                                 INVALID_HW_RING_ID;
3573                 }
3574         }
3575
3576         for (i = 0; i < bp->cp_nr_rings; i++) {
3577                 struct bnxt_napi *bnapi = bp->bnapi[i];
3578                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3579                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3580
3581                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3582                         hwrm_ring_free_send_msg(bp, ring,
3583                                                 RING_FREE_REQ_RING_TYPE_CMPL,
3584                                                 INVALID_HW_RING_ID);
3585                         ring->fw_ring_id = INVALID_HW_RING_ID;
3586                         bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
3587                 }
3588         }
3589 }
3590
3591 static void bnxt_hwrm_set_coal_params(struct bnxt *bp, u32 max_bufs,
3592         u32 buf_tmrs, u16 flags,
3593         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
3594 {
3595         req->flags = cpu_to_le16(flags);
3596         req->num_cmpl_dma_aggr = cpu_to_le16((u16)max_bufs);
3597         req->num_cmpl_dma_aggr_during_int = cpu_to_le16(max_bufs >> 16);
3598         req->cmpl_aggr_dma_tmr = cpu_to_le16((u16)buf_tmrs);
3599         req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(buf_tmrs >> 16);
3600         /* Minimum time between 2 interrupts set to buf_tmr x 2 */
3601         req->int_lat_tmr_min = cpu_to_le16((u16)buf_tmrs * 2);
3602         req->int_lat_tmr_max = cpu_to_le16((u16)buf_tmrs * 4);
3603         req->num_cmpl_aggr_int = cpu_to_le16((u16)max_bufs * 4);
3604 }
3605
3606 int bnxt_hwrm_set_coal(struct bnxt *bp)
3607 {
3608         int i, rc = 0;
3609         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0},
3610                                                            req_tx = {0}, *req;
3611         u16 max_buf, max_buf_irq;
3612         u16 buf_tmr, buf_tmr_irq;
3613         u32 flags;
3614
3615         bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
3616                                HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
3617         bnxt_hwrm_cmd_hdr_init(bp, &req_tx,
3618                                HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
3619
3620         /* Each rx completion (2 records) should be DMAed immediately.
3621          * DMA 1/4 of the completion buffers at a time.
3622          */
3623         max_buf = min_t(u16, bp->rx_coal_bufs / 4, 2);
3624         /* max_buf must not be zero */
3625         max_buf = clamp_t(u16, max_buf, 1, 63);
3626         max_buf_irq = clamp_t(u16, bp->rx_coal_bufs_irq, 1, 63);
3627         buf_tmr = BNXT_USEC_TO_COAL_TIMER(bp->rx_coal_ticks);
3628         /* buf timer set to 1/4 of interrupt timer */
3629         buf_tmr = max_t(u16, buf_tmr / 4, 1);
3630         buf_tmr_irq = BNXT_USEC_TO_COAL_TIMER(bp->rx_coal_ticks_irq);
3631         buf_tmr_irq = max_t(u16, buf_tmr_irq, 1);
3632
3633         flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
3634
3635         /* RING_IDLE generates more IRQs for lower latency.  Enable it only
3636          * if coal_ticks is less than 25 us.
3637          */
3638         if (bp->rx_coal_ticks < 25)
3639                 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE;
3640
3641         bnxt_hwrm_set_coal_params(bp, max_buf_irq << 16 | max_buf,
3642                                   buf_tmr_irq << 16 | buf_tmr, flags, &req_rx);
3643
3644         /* max_buf must not be zero */
3645         max_buf = clamp_t(u16, bp->tx_coal_bufs, 1, 63);
3646         max_buf_irq = clamp_t(u16, bp->tx_coal_bufs_irq, 1, 63);
3647         buf_tmr = BNXT_USEC_TO_COAL_TIMER(bp->tx_coal_ticks);
3648         /* buf timer set to 1/4 of interrupt timer */
3649         buf_tmr = max_t(u16, buf_tmr / 4, 1);
3650         buf_tmr_irq = BNXT_USEC_TO_COAL_TIMER(bp->tx_coal_ticks_irq);
3651         buf_tmr_irq = max_t(u16, buf_tmr_irq, 1);
3652
3653         flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
3654         bnxt_hwrm_set_coal_params(bp, max_buf_irq << 16 | max_buf,
3655                                   buf_tmr_irq << 16 | buf_tmr, flags, &req_tx);
3656
3657         mutex_lock(&bp->hwrm_cmd_lock);
3658         for (i = 0; i < bp->cp_nr_rings; i++) {
3659                 struct bnxt_napi *bnapi = bp->bnapi[i];
3660
3661                 req = &req_rx;
3662                 if (!bnapi->rx_ring)
3663                         req = &req_tx;
3664                 req->ring_id = cpu_to_le16(bp->grp_info[i].cp_fw_ring_id);
3665
3666                 rc = _hwrm_send_message(bp, req, sizeof(*req),
3667                                         HWRM_CMD_TIMEOUT);
3668                 if (rc)
3669                         break;
3670         }
3671         mutex_unlock(&bp->hwrm_cmd_lock);
3672         return rc;
3673 }
3674
3675 static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp)
3676 {
3677         int rc = 0, i;
3678         struct hwrm_stat_ctx_free_input req = {0};
3679
3680         if (!bp->bnapi)
3681                 return 0;
3682
3683         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1);
3684
3685         mutex_lock(&bp->hwrm_cmd_lock);
3686         for (i = 0; i < bp->cp_nr_rings; i++) {
3687                 struct bnxt_napi *bnapi = bp->bnapi[i];
3688                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3689
3690                 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) {
3691                         req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id);
3692
3693                         rc = _hwrm_send_message(bp, &req, sizeof(req),
3694                                                 HWRM_CMD_TIMEOUT);
3695                         if (rc)
3696                                 break;
3697
3698                         cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
3699                 }
3700         }
3701         mutex_unlock(&bp->hwrm_cmd_lock);
3702         return rc;
3703 }
3704
3705 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp)
3706 {
3707         int rc = 0, i;
3708         struct hwrm_stat_ctx_alloc_input req = {0};
3709         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3710
3711         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1);
3712
3713         req.update_period_ms = cpu_to_le32(1000);
3714
3715         mutex_lock(&bp->hwrm_cmd_lock);
3716         for (i = 0; i < bp->cp_nr_rings; i++) {
3717                 struct bnxt_napi *bnapi = bp->bnapi[i];
3718                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3719
3720                 req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map);
3721
3722                 rc = _hwrm_send_message(bp, &req, sizeof(req),
3723                                         HWRM_CMD_TIMEOUT);
3724                 if (rc)
3725                         break;
3726
3727                 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id);
3728
3729                 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
3730         }
3731         mutex_unlock(&bp->hwrm_cmd_lock);
3732         return 0;
3733 }
3734
3735 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
3736 {
3737         int rc = 0;
3738         struct hwrm_func_qcaps_input req = {0};
3739         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3740
3741         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1);
3742         req.fid = cpu_to_le16(0xffff);
3743
3744         mutex_lock(&bp->hwrm_cmd_lock);
3745         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3746         if (rc)
3747                 goto hwrm_func_qcaps_exit;
3748
3749         if (BNXT_PF(bp)) {
3750                 struct bnxt_pf_info *pf = &bp->pf;
3751
3752                 pf->fw_fid = le16_to_cpu(resp->fid);
3753                 pf->port_id = le16_to_cpu(resp->port_id);
3754                 memcpy(pf->mac_addr, resp->perm_mac_address, ETH_ALEN);
3755                 memcpy(bp->dev->dev_addr, pf->mac_addr, ETH_ALEN);
3756                 pf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
3757                 pf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
3758                 pf->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
3759                 pf->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
3760                 pf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
3761                 if (!pf->max_hw_ring_grps)
3762                         pf->max_hw_ring_grps = pf->max_tx_rings;
3763                 pf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
3764                 pf->max_vnics = le16_to_cpu(resp->max_vnics);
3765                 pf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
3766                 pf->first_vf_id = le16_to_cpu(resp->first_vf_id);
3767                 pf->max_vfs = le16_to_cpu(resp->max_vfs);
3768                 pf->max_encap_records = le32_to_cpu(resp->max_encap_records);
3769                 pf->max_decap_records = le32_to_cpu(resp->max_decap_records);
3770                 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows);
3771                 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows);
3772                 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows);
3773                 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows);
3774         } else {
3775 #ifdef CONFIG_BNXT_SRIOV
3776                 struct bnxt_vf_info *vf = &bp->vf;
3777
3778                 vf->fw_fid = le16_to_cpu(resp->fid);
3779                 memcpy(vf->mac_addr, resp->perm_mac_address, ETH_ALEN);
3780                 if (is_valid_ether_addr(vf->mac_addr))
3781                         /* overwrite netdev dev_adr with admin VF MAC */
3782                         memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN);
3783                 else
3784                         random_ether_addr(bp->dev->dev_addr);
3785
3786                 vf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
3787                 vf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
3788                 vf->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
3789                 vf->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
3790                 vf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
3791                 if (!vf->max_hw_ring_grps)
3792                         vf->max_hw_ring_grps = vf->max_tx_rings;
3793                 vf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
3794                 vf->max_vnics = le16_to_cpu(resp->max_vnics);
3795                 vf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
3796 #endif
3797         }
3798
3799         bp->tx_push_thresh = 0;
3800         if (resp->flags &
3801             cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED))
3802                 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH;
3803
3804 hwrm_func_qcaps_exit:
3805         mutex_unlock(&bp->hwrm_cmd_lock);
3806         return rc;
3807 }
3808
3809 static int bnxt_hwrm_func_reset(struct bnxt *bp)
3810 {
3811         struct hwrm_func_reset_input req = {0};
3812
3813         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1);
3814         req.enables = 0;
3815
3816         return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT);
3817 }
3818
3819 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
3820 {
3821         int rc = 0;
3822         struct hwrm_queue_qportcfg_input req = {0};
3823         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
3824         u8 i, *qptr;
3825
3826         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1);
3827
3828         mutex_lock(&bp->hwrm_cmd_lock);
3829         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3830         if (rc)
3831                 goto qportcfg_exit;
3832
3833         if (!resp->max_configurable_queues) {
3834                 rc = -EINVAL;
3835                 goto qportcfg_exit;
3836         }
3837         bp->max_tc = resp->max_configurable_queues;
3838         if (bp->max_tc > BNXT_MAX_QUEUE)
3839                 bp->max_tc = BNXT_MAX_QUEUE;
3840
3841         qptr = &resp->queue_id0;
3842         for (i = 0; i < bp->max_tc; i++) {
3843                 bp->q_info[i].queue_id = *qptr++;
3844                 bp->q_info[i].queue_profile = *qptr++;
3845         }
3846
3847 qportcfg_exit:
3848         mutex_unlock(&bp->hwrm_cmd_lock);
3849         return rc;
3850 }
3851
3852 static int bnxt_hwrm_ver_get(struct bnxt *bp)
3853 {
3854         int rc;
3855         struct hwrm_ver_get_input req = {0};
3856         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
3857
3858         bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN;
3859         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1);
3860         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
3861         req.hwrm_intf_min = HWRM_VERSION_MINOR;
3862         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
3863         mutex_lock(&bp->hwrm_cmd_lock);
3864         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3865         if (rc)
3866                 goto hwrm_ver_get_exit;
3867
3868         memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output));
3869
3870         if (resp->hwrm_intf_maj < 1) {
3871                 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
3872                             resp->hwrm_intf_maj, resp->hwrm_intf_min,
3873                             resp->hwrm_intf_upd);
3874                 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
3875         }
3876         snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "%d.%d.%d/%d.%d.%d",
3877                  resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld,
3878                  resp->hwrm_intf_maj, resp->hwrm_intf_min, resp->hwrm_intf_upd);
3879
3880         bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout);
3881         if (!bp->hwrm_cmd_timeout)
3882                 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
3883
3884         if (resp->hwrm_intf_maj >= 1)
3885                 bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len);
3886
3887 hwrm_ver_get_exit:
3888         mutex_unlock(&bp->hwrm_cmd_lock);
3889         return rc;
3890 }
3891
3892 static int bnxt_hwrm_port_qstats(struct bnxt *bp)
3893 {
3894         int rc;
3895         struct bnxt_pf_info *pf = &bp->pf;
3896         struct hwrm_port_qstats_input req = {0};
3897
3898         if (!(bp->flags & BNXT_FLAG_PORT_STATS))
3899                 return 0;
3900
3901         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS, -1, -1);
3902         req.port_id = cpu_to_le16(pf->port_id);
3903         req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_map);
3904         req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_map);
3905         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3906         return rc;
3907 }
3908
3909 static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp)
3910 {
3911         if (bp->vxlan_port_cnt) {
3912                 bnxt_hwrm_tunnel_dst_port_free(
3913                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
3914         }
3915         bp->vxlan_port_cnt = 0;
3916         if (bp->nge_port_cnt) {
3917                 bnxt_hwrm_tunnel_dst_port_free(
3918                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
3919         }
3920         bp->nge_port_cnt = 0;
3921 }
3922
3923 static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa)
3924 {
3925         int rc, i;
3926         u32 tpa_flags = 0;
3927
3928         if (set_tpa)
3929                 tpa_flags = bp->flags & BNXT_FLAG_TPA;
3930         for (i = 0; i < bp->nr_vnics; i++) {
3931                 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags);
3932                 if (rc) {
3933                         netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
3934                                    rc, i);
3935                         return rc;
3936                 }
3937         }
3938         return 0;
3939 }
3940
3941 static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp)
3942 {
3943         int i;
3944
3945         for (i = 0; i < bp->nr_vnics; i++)
3946                 bnxt_hwrm_vnic_set_rss(bp, i, false);
3947 }
3948
3949 static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path,
3950                                     bool irq_re_init)
3951 {
3952         if (bp->vnic_info) {
3953                 bnxt_hwrm_clear_vnic_filter(bp);
3954                 /* clear all RSS setting before free vnic ctx */
3955                 bnxt_hwrm_clear_vnic_rss(bp);
3956                 bnxt_hwrm_vnic_ctx_free(bp);
3957                 /* before free the vnic, undo the vnic tpa settings */
3958                 if (bp->flags & BNXT_FLAG_TPA)
3959                         bnxt_set_tpa(bp, false);
3960                 bnxt_hwrm_vnic_free(bp);
3961         }
3962         bnxt_hwrm_ring_free(bp, close_path);
3963         bnxt_hwrm_ring_grp_free(bp);
3964         if (irq_re_init) {
3965                 bnxt_hwrm_stat_ctx_free(bp);
3966                 bnxt_hwrm_free_tunnel_ports(bp);
3967         }
3968 }
3969
3970 static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
3971 {
3972         int rc;
3973
3974         /* allocate context for vnic */
3975         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id);
3976         if (rc) {
3977                 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
3978                            vnic_id, rc);
3979                 goto vnic_setup_err;
3980         }
3981         bp->rsscos_nr_ctxs++;
3982
3983         /* configure default vnic, ring grp */
3984         rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
3985         if (rc) {
3986                 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
3987                            vnic_id, rc);
3988                 goto vnic_setup_err;
3989         }
3990
3991         /* Enable RSS hashing on vnic */
3992         rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true);
3993         if (rc) {
3994                 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n",
3995                            vnic_id, rc);
3996                 goto vnic_setup_err;
3997         }
3998
3999         if (bp->flags & BNXT_FLAG_AGG_RINGS) {
4000                 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
4001                 if (rc) {
4002                         netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
4003                                    vnic_id, rc);
4004                 }
4005         }
4006
4007 vnic_setup_err:
4008         return rc;
4009 }
4010
4011 static int bnxt_alloc_rfs_vnics(struct bnxt *bp)
4012 {
4013 #ifdef CONFIG_RFS_ACCEL
4014         int i, rc = 0;
4015
4016         for (i = 0; i < bp->rx_nr_rings; i++) {
4017                 u16 vnic_id = i + 1;
4018                 u16 ring_id = i;
4019
4020                 if (vnic_id >= bp->nr_vnics)
4021                         break;
4022
4023                 bp->vnic_info[vnic_id].flags |= BNXT_VNIC_RFS_FLAG;
4024                 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1);
4025                 if (rc) {
4026                         netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
4027                                    vnic_id, rc);
4028                         break;
4029                 }
4030                 rc = bnxt_setup_vnic(bp, vnic_id);
4031                 if (rc)
4032                         break;
4033         }
4034         return rc;
4035 #else
4036         return 0;
4037 #endif
4038 }
4039
4040 static int bnxt_cfg_rx_mode(struct bnxt *);
4041
4042 static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init)
4043 {
4044         int rc = 0;
4045
4046         if (irq_re_init) {
4047                 rc = bnxt_hwrm_stat_ctx_alloc(bp);
4048                 if (rc) {
4049                         netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n",
4050                                    rc);
4051                         goto err_out;
4052                 }
4053         }
4054
4055         rc = bnxt_hwrm_ring_alloc(bp);
4056         if (rc) {
4057                 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc);
4058                 goto err_out;
4059         }
4060
4061         rc = bnxt_hwrm_ring_grp_alloc(bp);
4062         if (rc) {
4063                 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc);
4064                 goto err_out;
4065         }
4066
4067         /* default vnic 0 */
4068         rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, bp->rx_nr_rings);
4069         if (rc) {
4070                 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc);
4071                 goto err_out;
4072         }
4073
4074         rc = bnxt_setup_vnic(bp, 0);
4075         if (rc)
4076                 goto err_out;
4077
4078         if (bp->flags & BNXT_FLAG_RFS) {
4079                 rc = bnxt_alloc_rfs_vnics(bp);
4080                 if (rc)
4081                         goto err_out;
4082         }
4083
4084         if (bp->flags & BNXT_FLAG_TPA) {
4085                 rc = bnxt_set_tpa(bp, true);
4086                 if (rc)
4087                         goto err_out;
4088         }
4089
4090         if (BNXT_VF(bp))
4091                 bnxt_update_vf_mac(bp);
4092
4093         /* Filter for default vnic 0 */
4094         rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr);
4095         if (rc) {
4096                 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc);
4097                 goto err_out;
4098         }
4099         bp->vnic_info[0].uc_filter_count = 1;
4100
4101         bp->vnic_info[0].rx_mask = CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
4102
4103         if ((bp->dev->flags & IFF_PROMISC) && BNXT_PF(bp))
4104                 bp->vnic_info[0].rx_mask |=
4105                                 CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
4106
4107         rc = bnxt_cfg_rx_mode(bp);
4108         if (rc)
4109                 goto err_out;
4110
4111         rc = bnxt_hwrm_set_coal(bp);
4112         if (rc)
4113                 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n",
4114                             rc);
4115
4116         return 0;
4117
4118 err_out:
4119         bnxt_hwrm_resource_free(bp, 0, true);
4120
4121         return rc;
4122 }
4123
4124 static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init)
4125 {
4126         bnxt_hwrm_resource_free(bp, 1, irq_re_init);
4127         return 0;
4128 }
4129
4130 static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init)
4131 {
4132         bnxt_init_rx_rings(bp);
4133         bnxt_init_tx_rings(bp);
4134         bnxt_init_ring_grps(bp, irq_re_init);
4135         bnxt_init_vnics(bp);
4136
4137         return bnxt_init_chip(bp, irq_re_init);
4138 }
4139
4140 static void bnxt_disable_int(struct bnxt *bp)
4141 {
4142         int i;
4143
4144         if (!bp->bnapi)
4145                 return;
4146
4147         for (i = 0; i < bp->cp_nr_rings; i++) {
4148                 struct bnxt_napi *bnapi = bp->bnapi[i];
4149                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4150
4151                 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
4152         }
4153 }
4154
4155 static void bnxt_enable_int(struct bnxt *bp)
4156 {
4157         int i;
4158
4159         atomic_set(&bp->intr_sem, 0);
4160         for (i = 0; i < bp->cp_nr_rings; i++) {
4161                 struct bnxt_napi *bnapi = bp->bnapi[i];
4162                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4163
4164                 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
4165         }
4166 }
4167
4168 static int bnxt_set_real_num_queues(struct bnxt *bp)
4169 {
4170         int rc;
4171         struct net_device *dev = bp->dev;
4172
4173         rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings);
4174         if (rc)
4175                 return rc;
4176
4177         rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings);
4178         if (rc)
4179                 return rc;
4180
4181 #ifdef CONFIG_RFS_ACCEL
4182         if (bp->flags & BNXT_FLAG_RFS)
4183                 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings);
4184 #endif
4185
4186         return rc;
4187 }
4188
4189 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
4190                            bool shared)
4191 {
4192         int _rx = *rx, _tx = *tx;
4193
4194         if (shared) {
4195                 *rx = min_t(int, _rx, max);
4196                 *tx = min_t(int, _tx, max);
4197         } else {
4198                 if (max < 2)
4199                         return -ENOMEM;
4200
4201                 while (_rx + _tx > max) {
4202                         if (_rx > _tx && _rx > 1)
4203                                 _rx--;
4204                         else if (_tx > 1)
4205                                 _tx--;
4206                 }
4207                 *rx = _rx;
4208                 *tx = _tx;
4209         }
4210         return 0;
4211 }
4212
4213 static int bnxt_setup_msix(struct bnxt *bp)
4214 {
4215         struct msix_entry *msix_ent;
4216         struct net_device *dev = bp->dev;
4217         int i, total_vecs, rc = 0, min = 1;
4218         const int len = sizeof(bp->irq_tbl[0].name);
4219
4220         bp->flags &= ~BNXT_FLAG_USING_MSIX;
4221         total_vecs = bp->cp_nr_rings;
4222
4223         msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL);
4224         if (!msix_ent)
4225                 return -ENOMEM;
4226
4227         for (i = 0; i < total_vecs; i++) {
4228                 msix_ent[i].entry = i;
4229                 msix_ent[i].vector = 0;
4230         }
4231
4232         if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
4233                 min = 2;
4234
4235         total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs);
4236         if (total_vecs < 0) {
4237                 rc = -ENODEV;
4238                 goto msix_setup_exit;
4239         }
4240
4241         bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL);
4242         if (bp->irq_tbl) {
4243                 int tcs;
4244
4245                 /* Trim rings based upon num of vectors allocated */
4246                 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings,
4247                                      total_vecs, min == 1);
4248                 if (rc)
4249                         goto msix_setup_exit;
4250
4251                 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
4252                 tcs = netdev_get_num_tc(dev);
4253                 if (tcs > 1) {
4254                         bp->tx_nr_rings_per_tc = bp->tx_nr_rings / tcs;
4255                         if (bp->tx_nr_rings_per_tc == 0) {
4256                                 netdev_reset_tc(dev);
4257                                 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
4258                         } else {
4259                                 int i, off, count;
4260
4261                                 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tcs;
4262                                 for (i = 0; i < tcs; i++) {
4263                                         count = bp->tx_nr_rings_per_tc;
4264                                         off = i * count;
4265                                         netdev_set_tc_queue(dev, i, count, off);
4266                                 }
4267                         }
4268                 }
4269                 bp->cp_nr_rings = total_vecs;
4270
4271                 for (i = 0; i < bp->cp_nr_rings; i++) {
4272                         char *attr;
4273
4274                         bp->irq_tbl[i].vector = msix_ent[i].vector;
4275                         if (bp->flags & BNXT_FLAG_SHARED_RINGS)
4276                                 attr = "TxRx";
4277                         else if (i < bp->rx_nr_rings)
4278                                 attr = "rx";
4279                         else
4280                                 attr = "tx";
4281
4282                         snprintf(bp->irq_tbl[i].name, len,
4283                                  "%s-%s-%d", dev->name, attr, i);
4284                         bp->irq_tbl[i].handler = bnxt_msix;
4285                 }
4286                 rc = bnxt_set_real_num_queues(bp);
4287                 if (rc)
4288                         goto msix_setup_exit;
4289         } else {
4290                 rc = -ENOMEM;
4291                 goto msix_setup_exit;
4292         }
4293         bp->flags |= BNXT_FLAG_USING_MSIX;
4294         kfree(msix_ent);
4295         return 0;
4296
4297 msix_setup_exit:
4298         netdev_err(bp->dev, "bnxt_setup_msix err: %x\n", rc);
4299         pci_disable_msix(bp->pdev);
4300         kfree(msix_ent);
4301         return rc;
4302 }
4303
4304 static int bnxt_setup_inta(struct bnxt *bp)
4305 {
4306         int rc;
4307         const int len = sizeof(bp->irq_tbl[0].name);
4308
4309         if (netdev_get_num_tc(bp->dev))
4310                 netdev_reset_tc(bp->dev);
4311
4312         bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL);
4313         if (!bp->irq_tbl) {
4314                 rc = -ENOMEM;
4315                 return rc;
4316         }
4317         bp->rx_nr_rings = 1;
4318         bp->tx_nr_rings = 1;
4319         bp->cp_nr_rings = 1;
4320         bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
4321         bp->flags |= BNXT_FLAG_SHARED_RINGS;
4322         bp->irq_tbl[0].vector = bp->pdev->irq;
4323         snprintf(bp->irq_tbl[0].name, len,
4324                  "%s-%s-%d", bp->dev->name, "TxRx", 0);
4325         bp->irq_tbl[0].handler = bnxt_inta;
4326         rc = bnxt_set_real_num_queues(bp);
4327         return rc;
4328 }
4329
4330 static int bnxt_setup_int_mode(struct bnxt *bp)
4331 {
4332         int rc = 0;
4333
4334         if (bp->flags & BNXT_FLAG_MSIX_CAP)
4335                 rc = bnxt_setup_msix(bp);
4336
4337         if (!(bp->flags & BNXT_FLAG_USING_MSIX) && BNXT_PF(bp)) {
4338                 /* fallback to INTA */
4339                 rc = bnxt_setup_inta(bp);
4340         }
4341         return rc;
4342 }
4343
4344 static void bnxt_free_irq(struct bnxt *bp)
4345 {
4346         struct bnxt_irq *irq;
4347         int i;
4348
4349 #ifdef CONFIG_RFS_ACCEL
4350         free_irq_cpu_rmap(bp->dev->rx_cpu_rmap);
4351         bp->dev->rx_cpu_rmap = NULL;
4352 #endif
4353         if (!bp->irq_tbl)
4354                 return;
4355
4356         for (i = 0; i < bp->cp_nr_rings; i++) {
4357                 irq = &bp->irq_tbl[i];
4358                 if (irq->requested)
4359                         free_irq(irq->vector, bp->bnapi[i]);
4360                 irq->requested = 0;
4361         }
4362         if (bp->flags & BNXT_FLAG_USING_MSIX)
4363                 pci_disable_msix(bp->pdev);
4364         kfree(bp->irq_tbl);
4365         bp->irq_tbl = NULL;
4366 }
4367
4368 static int bnxt_request_irq(struct bnxt *bp)
4369 {
4370         int i, j, rc = 0;
4371         unsigned long flags = 0;
4372 #ifdef CONFIG_RFS_ACCEL
4373         struct cpu_rmap *rmap = bp->dev->rx_cpu_rmap;
4374 #endif
4375
4376         if (!(bp->flags & BNXT_FLAG_USING_MSIX))
4377                 flags = IRQF_SHARED;
4378
4379         for (i = 0, j = 0; i < bp->cp_nr_rings; i++) {
4380                 struct bnxt_irq *irq = &bp->irq_tbl[i];
4381 #ifdef CONFIG_RFS_ACCEL
4382                 if (rmap && bp->bnapi[i]->rx_ring) {
4383                         rc = irq_cpu_rmap_add(rmap, irq->vector);
4384                         if (rc)
4385                                 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n",
4386                                             j);
4387                         j++;
4388                 }
4389 #endif
4390                 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
4391                                  bp->bnapi[i]);
4392                 if (rc)
4393                         break;
4394
4395                 irq->requested = 1;
4396         }
4397         return rc;
4398 }
4399
4400 static void bnxt_del_napi(struct bnxt *bp)
4401 {
4402         int i;
4403
4404         if (!bp->bnapi)
4405                 return;
4406
4407         for (i = 0; i < bp->cp_nr_rings; i++) {
4408                 struct bnxt_napi *bnapi = bp->bnapi[i];
4409
4410                 napi_hash_del(&bnapi->napi);
4411                 netif_napi_del(&bnapi->napi);
4412         }
4413 }
4414
4415 static void bnxt_init_napi(struct bnxt *bp)
4416 {
4417         int i;
4418         struct bnxt_napi *bnapi;
4419
4420         if (bp->flags & BNXT_FLAG_USING_MSIX) {
4421                 for (i = 0; i < bp->cp_nr_rings; i++) {
4422                         bnapi = bp->bnapi[i];
4423                         netif_napi_add(bp->dev, &bnapi->napi,
4424                                        bnxt_poll, 64);
4425                 }
4426         } else {
4427                 bnapi = bp->bnapi[0];
4428                 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64);
4429         }
4430 }
4431
4432 static void bnxt_disable_napi(struct bnxt *bp)
4433 {
4434         int i;
4435
4436         if (!bp->bnapi)
4437                 return;
4438
4439         for (i = 0; i < bp->cp_nr_rings; i++) {
4440                 napi_disable(&bp->bnapi[i]->napi);
4441                 bnxt_disable_poll(bp->bnapi[i]);
4442         }
4443 }
4444
4445 static void bnxt_enable_napi(struct bnxt *bp)
4446 {
4447         int i;
4448
4449         for (i = 0; i < bp->cp_nr_rings; i++) {
4450                 bnxt_enable_poll(bp->bnapi[i]);
4451                 napi_enable(&bp->bnapi[i]->napi);
4452         }
4453 }
4454
4455 static void bnxt_tx_disable(struct bnxt *bp)
4456 {
4457         int i;
4458         struct bnxt_tx_ring_info *txr;
4459         struct netdev_queue *txq;
4460
4461         if (bp->tx_ring) {
4462                 for (i = 0; i < bp->tx_nr_rings; i++) {
4463                         txr = &bp->tx_ring[i];
4464                         txq = netdev_get_tx_queue(bp->dev, i);
4465                         __netif_tx_lock(txq, smp_processor_id());
4466                         txr->dev_state = BNXT_DEV_STATE_CLOSING;
4467                         __netif_tx_unlock(txq);
4468                 }
4469         }
4470         /* Stop all TX queues */
4471         netif_tx_disable(bp->dev);
4472         netif_carrier_off(bp->dev);
4473 }
4474
4475 static void bnxt_tx_enable(struct bnxt *bp)
4476 {
4477         int i;
4478         struct bnxt_tx_ring_info *txr;
4479         struct netdev_queue *txq;
4480
4481         for (i = 0; i < bp->tx_nr_rings; i++) {
4482                 txr = &bp->tx_ring[i];
4483                 txq = netdev_get_tx_queue(bp->dev, i);
4484                 txr->dev_state = 0;
4485         }
4486         netif_tx_wake_all_queues(bp->dev);
4487         if (bp->link_info.link_up)
4488                 netif_carrier_on(bp->dev);
4489 }
4490
4491 static void bnxt_report_link(struct bnxt *bp)
4492 {
4493         if (bp->link_info.link_up) {
4494                 const char *duplex;
4495                 const char *flow_ctrl;
4496                 u16 speed;
4497
4498                 netif_carrier_on(bp->dev);
4499                 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL)
4500                         duplex = "full";
4501                 else
4502                         duplex = "half";
4503                 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH)
4504                         flow_ctrl = "ON - receive & transmit";
4505                 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX)
4506                         flow_ctrl = "ON - transmit";
4507                 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX)
4508                         flow_ctrl = "ON - receive";
4509                 else
4510                         flow_ctrl = "none";
4511                 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed);
4512                 netdev_info(bp->dev, "NIC Link is Up, %d Mbps %s duplex, Flow control: %s\n",
4513                             speed, duplex, flow_ctrl);
4514         } else {
4515                 netif_carrier_off(bp->dev);
4516                 netdev_err(bp->dev, "NIC Link is Down\n");
4517         }
4518 }
4519
4520 static int bnxt_update_link(struct bnxt *bp, bool chng_link_state)
4521 {
4522         int rc = 0;
4523         struct bnxt_link_info *link_info = &bp->link_info;
4524         struct hwrm_port_phy_qcfg_input req = {0};
4525         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4526         u8 link_up = link_info->link_up;
4527
4528         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1);
4529
4530         mutex_lock(&bp->hwrm_cmd_lock);
4531         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4532         if (rc) {
4533                 mutex_unlock(&bp->hwrm_cmd_lock);
4534                 return rc;
4535         }
4536
4537         memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp));
4538         link_info->phy_link_status = resp->link;
4539         link_info->duplex =  resp->duplex;
4540         link_info->pause = resp->pause;
4541         link_info->auto_mode = resp->auto_mode;
4542         link_info->auto_pause_setting = resp->auto_pause;
4543         link_info->lp_pause = resp->link_partner_adv_pause;
4544         link_info->force_pause_setting = resp->force_pause;
4545         link_info->duplex_setting = resp->duplex;
4546         if (link_info->phy_link_status == BNXT_LINK_LINK)
4547                 link_info->link_speed = le16_to_cpu(resp->link_speed);
4548         else
4549                 link_info->link_speed = 0;
4550         link_info->force_link_speed = le16_to_cpu(resp->force_link_speed);
4551         link_info->auto_link_speed = le16_to_cpu(resp->auto_link_speed);
4552         link_info->support_speeds = le16_to_cpu(resp->support_speeds);
4553         link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask);
4554         link_info->lp_auto_link_speeds =
4555                 le16_to_cpu(resp->link_partner_adv_speeds);
4556         link_info->preemphasis = le32_to_cpu(resp->preemphasis);
4557         link_info->phy_ver[0] = resp->phy_maj;
4558         link_info->phy_ver[1] = resp->phy_min;
4559         link_info->phy_ver[2] = resp->phy_bld;
4560         link_info->media_type = resp->media_type;
4561         link_info->transceiver = resp->transceiver_type;
4562         link_info->phy_addr = resp->phy_addr;
4563
4564         /* TODO: need to add more logic to report VF link */
4565         if (chng_link_state) {
4566                 if (link_info->phy_link_status == BNXT_LINK_LINK)
4567                         link_info->link_up = 1;
4568                 else
4569                         link_info->link_up = 0;
4570                 if (link_up != link_info->link_up)
4571                         bnxt_report_link(bp);
4572         } else {
4573                 /* alwasy link down if not require to update link state */
4574                 link_info->link_up = 0;
4575         }
4576         mutex_unlock(&bp->hwrm_cmd_lock);
4577         return 0;
4578 }
4579
4580 static void
4581 bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req)
4582 {
4583         if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) {
4584                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
4585                         req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
4586                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
4587                         req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX;
4588                 req->enables |=
4589                         cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
4590         } else {
4591                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
4592                         req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX;
4593                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
4594                         req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX;
4595                 req->enables |=
4596                         cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE);
4597         }
4598 }
4599
4600 static void bnxt_hwrm_set_link_common(struct bnxt *bp,
4601                                       struct hwrm_port_phy_cfg_input *req)
4602 {
4603         u8 autoneg = bp->link_info.autoneg;
4604         u16 fw_link_speed = bp->link_info.req_link_speed;
4605         u32 advertising = bp->link_info.advertising;
4606
4607         if (autoneg & BNXT_AUTONEG_SPEED) {
4608                 req->auto_mode |=
4609                         PORT_PHY_CFG_REQ_AUTO_MODE_MASK;
4610
4611                 req->enables |= cpu_to_le32(
4612                         PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK);
4613                 req->auto_link_speed_mask = cpu_to_le16(advertising);
4614
4615                 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE);
4616                 req->flags |=
4617                         cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG);
4618         } else {
4619                 req->force_link_speed = cpu_to_le16(fw_link_speed);
4620                 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE);
4621         }
4622
4623         /* currently don't support half duplex */
4624         req->auto_duplex = PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL;
4625         req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX);
4626         /* tell chimp that the setting takes effect immediately */
4627         req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
4628 }
4629
4630 int bnxt_hwrm_set_pause(struct bnxt *bp)
4631 {
4632         struct hwrm_port_phy_cfg_input req = {0};
4633         int rc;
4634
4635         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
4636         bnxt_hwrm_set_pause_common(bp, &req);
4637
4638         if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) ||
4639             bp->link_info.force_link_chng)
4640                 bnxt_hwrm_set_link_common(bp, &req);
4641
4642         mutex_lock(&bp->hwrm_cmd_lock);
4643         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4644         if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) {
4645                 /* since changing of pause setting doesn't trigger any link
4646                  * change event, the driver needs to update the current pause
4647                  * result upon successfully return of the phy_cfg command
4648                  */
4649                 bp->link_info.pause =
4650                 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl;
4651                 bp->link_info.auto_pause_setting = 0;
4652                 if (!bp->link_info.force_link_chng)
4653                         bnxt_report_link(bp);
4654         }
4655         bp->link_info.force_link_chng = false;
4656         mutex_unlock(&bp->hwrm_cmd_lock);
4657         return rc;
4658 }
4659
4660 int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause)
4661 {
4662         struct hwrm_port_phy_cfg_input req = {0};
4663
4664         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
4665         if (set_pause)
4666                 bnxt_hwrm_set_pause_common(bp, &req);
4667
4668         bnxt_hwrm_set_link_common(bp, &req);
4669         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4670 }
4671
4672 static int bnxt_update_phy_setting(struct bnxt *bp)
4673 {
4674         int rc;
4675         bool update_link = false;
4676         bool update_pause = false;
4677         struct bnxt_link_info *link_info = &bp->link_info;
4678
4679         rc = bnxt_update_link(bp, true);
4680         if (rc) {
4681                 netdev_err(bp->dev, "failed to update link (rc: %x)\n",
4682                            rc);
4683                 return rc;
4684         }
4685         if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
4686             link_info->auto_pause_setting != link_info->req_flow_ctrl)
4687                 update_pause = true;
4688         if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
4689             link_info->force_pause_setting != link_info->req_flow_ctrl)
4690                 update_pause = true;
4691         if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
4692                 if (BNXT_AUTO_MODE(link_info->auto_mode))
4693                         update_link = true;
4694                 if (link_info->req_link_speed != link_info->force_link_speed)
4695                         update_link = true;
4696                 if (link_info->req_duplex != link_info->duplex_setting)
4697                         update_link = true;
4698         } else {
4699                 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE)
4700                         update_link = true;
4701                 if (link_info->advertising != link_info->auto_link_speeds)
4702                         update_link = true;
4703         }
4704
4705         if (update_link)
4706                 rc = bnxt_hwrm_set_link_setting(bp, update_pause);
4707         else if (update_pause)
4708                 rc = bnxt_hwrm_set_pause(bp);
4709         if (rc) {
4710                 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n",
4711                            rc);
4712                 return rc;
4713         }
4714
4715         return rc;
4716 }
4717
4718 /* Common routine to pre-map certain register block to different GRC window.
4719  * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
4720  * in PF and 3 windows in VF that can be customized to map in different
4721  * register blocks.
4722  */
4723 static void bnxt_preset_reg_win(struct bnxt *bp)
4724 {
4725         if (BNXT_PF(bp)) {
4726                 /* CAG registers map to GRC window #4 */
4727                 writel(BNXT_CAG_REG_BASE,
4728                        bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12);
4729         }
4730 }
4731
4732 static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
4733 {
4734         int rc = 0;
4735
4736         bnxt_preset_reg_win(bp);
4737         netif_carrier_off(bp->dev);
4738         if (irq_re_init) {
4739                 rc = bnxt_setup_int_mode(bp);
4740                 if (rc) {
4741                         netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n",
4742                                    rc);
4743                         return rc;
4744                 }
4745         }
4746         if ((bp->flags & BNXT_FLAG_RFS) &&
4747             !(bp->flags & BNXT_FLAG_USING_MSIX)) {
4748                 /* disable RFS if falling back to INTA */
4749                 bp->dev->hw_features &= ~NETIF_F_NTUPLE;
4750                 bp->flags &= ~BNXT_FLAG_RFS;
4751         }
4752
4753         rc = bnxt_alloc_mem(bp, irq_re_init);
4754         if (rc) {
4755                 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
4756                 goto open_err_free_mem;
4757         }
4758
4759         if (irq_re_init) {
4760                 bnxt_init_napi(bp);
4761                 rc = bnxt_request_irq(bp);
4762                 if (rc) {
4763                         netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc);
4764                         goto open_err;
4765                 }
4766         }
4767
4768         bnxt_enable_napi(bp);
4769
4770         rc = bnxt_init_nic(bp, irq_re_init);
4771         if (rc) {
4772                 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
4773                 goto open_err;
4774         }
4775
4776         if (link_re_init) {
4777                 rc = bnxt_update_phy_setting(bp);
4778                 if (rc)
4779                         netdev_warn(bp->dev, "failed to update phy settings\n");
4780         }
4781
4782         if (irq_re_init) {
4783 #if defined(CONFIG_VXLAN) || defined(CONFIG_VXLAN_MODULE)
4784                 vxlan_get_rx_port(bp->dev);
4785 #endif
4786                 if (!bnxt_hwrm_tunnel_dst_port_alloc(
4787                                 bp, htons(0x17c1),
4788                                 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE))
4789                         bp->nge_port_cnt = 1;
4790         }
4791
4792         set_bit(BNXT_STATE_OPEN, &bp->state);
4793         bnxt_enable_int(bp);
4794         /* Enable TX queues */
4795         bnxt_tx_enable(bp);
4796         mod_timer(&bp->timer, jiffies + bp->current_interval);
4797         bnxt_update_link(bp, true);
4798
4799         return 0;
4800
4801 open_err:
4802         bnxt_disable_napi(bp);
4803         bnxt_del_napi(bp);
4804
4805 open_err_free_mem:
4806         bnxt_free_skbs(bp);
4807         bnxt_free_irq(bp);
4808         bnxt_free_mem(bp, true);
4809         return rc;
4810 }
4811
4812 /* rtnl_lock held */
4813 int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
4814 {
4815         int rc = 0;
4816
4817         rc = __bnxt_open_nic(bp, irq_re_init, link_re_init);
4818         if (rc) {
4819                 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc);
4820                 dev_close(bp->dev);
4821         }
4822         return rc;
4823 }
4824
4825 static int bnxt_open(struct net_device *dev)
4826 {
4827         struct bnxt *bp = netdev_priv(dev);
4828         int rc = 0;
4829
4830         rc = bnxt_hwrm_func_reset(bp);
4831         if (rc) {
4832                 netdev_err(bp->dev, "hwrm chip reset failure rc: %x\n",
4833                            rc);
4834                 rc = -1;
4835                 return rc;
4836         }
4837         return __bnxt_open_nic(bp, true, true);
4838 }
4839
4840 static void bnxt_disable_int_sync(struct bnxt *bp)
4841 {
4842         int i;
4843
4844         atomic_inc(&bp->intr_sem);
4845         if (!netif_running(bp->dev))
4846                 return;
4847
4848         bnxt_disable_int(bp);
4849         for (i = 0; i < bp->cp_nr_rings; i++)
4850                 synchronize_irq(bp->irq_tbl[i].vector);
4851 }
4852
4853 int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
4854 {
4855         int rc = 0;
4856
4857 #ifdef CONFIG_BNXT_SRIOV
4858         if (bp->sriov_cfg) {
4859                 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait,
4860                                                       !bp->sriov_cfg,
4861                                                       BNXT_SRIOV_CFG_WAIT_TMO);
4862                 if (rc)
4863                         netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n");
4864         }
4865 #endif
4866         /* Change device state to avoid TX queue wake up's */
4867         bnxt_tx_disable(bp);
4868
4869         clear_bit(BNXT_STATE_OPEN, &bp->state);
4870         smp_mb__after_atomic();
4871         while (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state))
4872                 msleep(20);
4873
4874         /* Flush rings before disabling interrupts */
4875         bnxt_shutdown_nic(bp, irq_re_init);
4876
4877         /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
4878
4879         bnxt_disable_napi(bp);
4880         bnxt_disable_int_sync(bp);
4881         del_timer_sync(&bp->timer);
4882         bnxt_free_skbs(bp);
4883
4884         if (irq_re_init) {
4885                 bnxt_free_irq(bp);
4886                 bnxt_del_napi(bp);
4887         }
4888         bnxt_free_mem(bp, irq_re_init);
4889         return rc;
4890 }
4891
4892 static int bnxt_close(struct net_device *dev)
4893 {
4894         struct bnxt *bp = netdev_priv(dev);
4895
4896         bnxt_close_nic(bp, true, true);
4897         return 0;
4898 }
4899
4900 /* rtnl_lock held */
4901 static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4902 {
4903         switch (cmd) {
4904         case SIOCGMIIPHY:
4905                 /* fallthru */
4906         case SIOCGMIIREG: {
4907                 if (!netif_running(dev))
4908                         return -EAGAIN;
4909
4910                 return 0;
4911         }
4912
4913         case SIOCSMIIREG:
4914                 if (!netif_running(dev))
4915                         return -EAGAIN;
4916
4917                 return 0;
4918
4919         default:
4920                 /* do nothing */
4921                 break;
4922         }
4923         return -EOPNOTSUPP;
4924 }
4925
4926 static struct rtnl_link_stats64 *
4927 bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
4928 {
4929         u32 i;
4930         struct bnxt *bp = netdev_priv(dev);
4931
4932         memset(stats, 0, sizeof(struct rtnl_link_stats64));
4933
4934         if (!bp->bnapi)
4935                 return stats;
4936
4937         /* TODO check if we need to synchronize with bnxt_close path */
4938         for (i = 0; i < bp->cp_nr_rings; i++) {
4939                 struct bnxt_napi *bnapi = bp->bnapi[i];
4940                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4941                 struct ctx_hw_stats *hw_stats = cpr->hw_stats;
4942
4943                 stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts);
4944                 stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts);
4945                 stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts);
4946
4947                 stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts);
4948                 stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts);
4949                 stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts);
4950
4951                 stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes);
4952                 stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes);
4953                 stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes);
4954
4955                 stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes);
4956                 stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes);
4957                 stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes);
4958
4959                 stats->rx_missed_errors +=
4960                         le64_to_cpu(hw_stats->rx_discard_pkts);
4961
4962                 stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts);
4963
4964                 stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts);
4965         }
4966
4967         if (bp->flags & BNXT_FLAG_PORT_STATS) {
4968                 struct rx_port_stats *rx = bp->hw_rx_port_stats;
4969                 struct tx_port_stats *tx = bp->hw_tx_port_stats;
4970
4971                 stats->rx_crc_errors = le64_to_cpu(rx->rx_fcs_err_frames);
4972                 stats->rx_frame_errors = le64_to_cpu(rx->rx_align_err_frames);
4973                 stats->rx_length_errors = le64_to_cpu(rx->rx_undrsz_frames) +
4974                                           le64_to_cpu(rx->rx_ovrsz_frames) +
4975                                           le64_to_cpu(rx->rx_runt_frames);
4976                 stats->rx_errors = le64_to_cpu(rx->rx_false_carrier_frames) +
4977                                    le64_to_cpu(rx->rx_jbr_frames);
4978                 stats->collisions = le64_to_cpu(tx->tx_total_collisions);
4979                 stats->tx_fifo_errors = le64_to_cpu(tx->tx_fifo_underruns);
4980                 stats->tx_errors = le64_to_cpu(tx->tx_err);
4981         }
4982
4983         return stats;
4984 }
4985
4986 static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask)
4987 {
4988         struct net_device *dev = bp->dev;
4989         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
4990         struct netdev_hw_addr *ha;
4991         u8 *haddr;
4992         int mc_count = 0;
4993         bool update = false;
4994         int off = 0;
4995
4996         netdev_for_each_mc_addr(ha, dev) {
4997                 if (mc_count >= BNXT_MAX_MC_ADDRS) {
4998                         *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
4999                         vnic->mc_list_count = 0;
5000                         return false;
5001                 }
5002                 haddr = ha->addr;
5003                 if (!ether_addr_equal(haddr, vnic->mc_list + off)) {
5004                         memcpy(vnic->mc_list + off, haddr, ETH_ALEN);
5005                         update = true;
5006                 }
5007                 off += ETH_ALEN;
5008                 mc_count++;
5009         }
5010         if (mc_count)
5011                 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST;
5012
5013         if (mc_count != vnic->mc_list_count) {
5014                 vnic->mc_list_count = mc_count;
5015                 update = true;
5016         }
5017         return update;
5018 }
5019
5020 static bool bnxt_uc_list_updated(struct bnxt *bp)
5021 {
5022         struct net_device *dev = bp->dev;
5023         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
5024         struct netdev_hw_addr *ha;
5025         int off = 0;
5026
5027         if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1))
5028                 return true;
5029
5030         netdev_for_each_uc_addr(ha, dev) {
5031                 if (!ether_addr_equal(ha->addr, vnic->uc_list + off))
5032                         return true;
5033
5034                 off += ETH_ALEN;
5035         }
5036         return false;
5037 }
5038
5039 static void bnxt_set_rx_mode(struct net_device *dev)
5040 {
5041         struct bnxt *bp = netdev_priv(dev);
5042         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
5043         u32 mask = vnic->rx_mask;
5044         bool mc_update = false;
5045         bool uc_update;
5046
5047         if (!netif_running(dev))
5048                 return;
5049
5050         mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS |
5051                   CFA_L2_SET_RX_MASK_REQ_MASK_MCAST |
5052                   CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST);
5053
5054         /* Only allow PF to be in promiscuous mode */
5055         if ((dev->flags & IFF_PROMISC) && BNXT_PF(bp))
5056                 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
5057
5058         uc_update = bnxt_uc_list_updated(bp);
5059
5060         if (dev->flags & IFF_ALLMULTI) {
5061                 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
5062                 vnic->mc_list_count = 0;
5063         } else {
5064                 mc_update = bnxt_mc_list_updated(bp, &mask);
5065         }
5066
5067         if (mask != vnic->rx_mask || uc_update || mc_update) {
5068                 vnic->rx_mask = mask;
5069
5070                 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event);
5071                 schedule_work(&bp->sp_task);
5072         }
5073 }
5074
5075 static int bnxt_cfg_rx_mode(struct bnxt *bp)
5076 {
5077         struct net_device *dev = bp->dev;
5078         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
5079         struct netdev_hw_addr *ha;
5080         int i, off = 0, rc;
5081         bool uc_update;
5082
5083         netif_addr_lock_bh(dev);
5084         uc_update = bnxt_uc_list_updated(bp);
5085         netif_addr_unlock_bh(dev);
5086
5087         if (!uc_update)
5088                 goto skip_uc;
5089
5090         mutex_lock(&bp->hwrm_cmd_lock);
5091         for (i = 1; i < vnic->uc_filter_count; i++) {
5092                 struct hwrm_cfa_l2_filter_free_input req = {0};
5093
5094                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1,
5095                                        -1);
5096
5097                 req.l2_filter_id = vnic->fw_l2_filter_id[i];
5098
5099                 rc = _hwrm_send_message(bp, &req, sizeof(req),
5100                                         HWRM_CMD_TIMEOUT);
5101         }
5102         mutex_unlock(&bp->hwrm_cmd_lock);
5103
5104         vnic->uc_filter_count = 1;
5105
5106         netif_addr_lock_bh(dev);
5107         if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) {
5108                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
5109         } else {
5110                 netdev_for_each_uc_addr(ha, dev) {
5111                         memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN);
5112                         off += ETH_ALEN;
5113                         vnic->uc_filter_count++;
5114                 }
5115         }
5116         netif_addr_unlock_bh(dev);
5117
5118         for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) {
5119                 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off);
5120                 if (rc) {
5121                         netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n",
5122                                    rc);
5123                         vnic->uc_filter_count = i;
5124                         return rc;
5125                 }
5126         }
5127
5128 skip_uc:
5129         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
5130         if (rc)
5131                 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %x\n",
5132                            rc);
5133
5134         return rc;
5135 }
5136
5137 static bool bnxt_rfs_capable(struct bnxt *bp)
5138 {
5139 #ifdef CONFIG_RFS_ACCEL
5140         struct bnxt_pf_info *pf = &bp->pf;
5141         int vnics;
5142
5143         if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_MSIX_CAP))
5144                 return false;
5145
5146         vnics = 1 + bp->rx_nr_rings;
5147         if (vnics > pf->max_rsscos_ctxs || vnics > pf->max_vnics)
5148                 return false;
5149
5150         return true;
5151 #else
5152         return false;
5153 #endif
5154 }
5155
5156 static netdev_features_t bnxt_fix_features(struct net_device *dev,
5157                                            netdev_features_t features)
5158 {
5159         struct bnxt *bp = netdev_priv(dev);
5160
5161         if (!bnxt_rfs_capable(bp))
5162                 features &= ~NETIF_F_NTUPLE;
5163         return features;
5164 }
5165
5166 static int bnxt_set_features(struct net_device *dev, netdev_features_t features)
5167 {
5168         struct bnxt *bp = netdev_priv(dev);
5169         u32 flags = bp->flags;
5170         u32 changes;
5171         int rc = 0;
5172         bool re_init = false;
5173         bool update_tpa = false;
5174
5175         flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS;
5176         if ((features & NETIF_F_GRO) && (bp->pdev->revision > 0))
5177                 flags |= BNXT_FLAG_GRO;
5178         if (features & NETIF_F_LRO)
5179                 flags |= BNXT_FLAG_LRO;
5180
5181         if (features & NETIF_F_HW_VLAN_CTAG_RX)
5182                 flags |= BNXT_FLAG_STRIP_VLAN;
5183
5184         if (features & NETIF_F_NTUPLE)
5185                 flags |= BNXT_FLAG_RFS;
5186
5187         changes = flags ^ bp->flags;
5188         if (changes & BNXT_FLAG_TPA) {
5189                 update_tpa = true;
5190                 if ((bp->flags & BNXT_FLAG_TPA) == 0 ||
5191                     (flags & BNXT_FLAG_TPA) == 0)
5192                         re_init = true;
5193         }
5194
5195         if (changes & ~BNXT_FLAG_TPA)
5196                 re_init = true;
5197
5198         if (flags != bp->flags) {
5199                 u32 old_flags = bp->flags;
5200
5201                 bp->flags = flags;
5202
5203                 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
5204                         if (update_tpa)
5205                                 bnxt_set_ring_params(bp);
5206                         return rc;
5207                 }
5208
5209                 if (re_init) {
5210                         bnxt_close_nic(bp, false, false);
5211                         if (update_tpa)
5212                                 bnxt_set_ring_params(bp);
5213
5214                         return bnxt_open_nic(bp, false, false);
5215                 }
5216                 if (update_tpa) {
5217                         rc = bnxt_set_tpa(bp,
5218                                           (flags & BNXT_FLAG_TPA) ?
5219                                           true : false);
5220                         if (rc)
5221                                 bp->flags = old_flags;
5222                 }
5223         }
5224         return rc;
5225 }
5226
5227 static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi)
5228 {
5229         struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
5230         int i = bnapi->index;
5231
5232         if (!txr)
5233                 return;
5234
5235         netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
5236                     i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod,
5237                     txr->tx_cons);
5238 }
5239
5240 static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi)
5241 {
5242         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
5243         int i = bnapi->index;
5244
5245         if (!rxr)
5246                 return;
5247
5248         netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
5249                     i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod,
5250                     rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod,
5251                     rxr->rx_sw_agg_prod);
5252 }
5253
5254 static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi)
5255 {
5256         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5257         int i = bnapi->index;
5258
5259         netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
5260                     i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons);
5261 }
5262
5263 static void bnxt_dbg_dump_states(struct bnxt *bp)
5264 {
5265         int i;
5266         struct bnxt_napi *bnapi;
5267
5268         for (i = 0; i < bp->cp_nr_rings; i++) {
5269                 bnapi = bp->bnapi[i];
5270                 if (netif_msg_drv(bp)) {
5271                         bnxt_dump_tx_sw_state(bnapi);
5272                         bnxt_dump_rx_sw_state(bnapi);
5273                         bnxt_dump_cp_sw_state(bnapi);
5274                 }
5275         }
5276 }
5277
5278 static void bnxt_reset_task(struct bnxt *bp)
5279 {
5280         bnxt_dbg_dump_states(bp);
5281         if (netif_running(bp->dev)) {
5282                 bnxt_close_nic(bp, false, false);
5283                 bnxt_open_nic(bp, false, false);
5284         }
5285 }
5286
5287 static void bnxt_tx_timeout(struct net_device *dev)
5288 {
5289         struct bnxt *bp = netdev_priv(dev);
5290
5291         netdev_err(bp->dev,  "TX timeout detected, starting reset task!\n");
5292         set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
5293         schedule_work(&bp->sp_task);
5294 }
5295
5296 #ifdef CONFIG_NET_POLL_CONTROLLER
5297 static void bnxt_poll_controller(struct net_device *dev)
5298 {
5299         struct bnxt *bp = netdev_priv(dev);
5300         int i;
5301
5302         for (i = 0; i < bp->cp_nr_rings; i++) {
5303                 struct bnxt_irq *irq = &bp->irq_tbl[i];
5304
5305                 disable_irq(irq->vector);
5306                 irq->handler(irq->vector, bp->bnapi[i]);
5307                 enable_irq(irq->vector);
5308         }
5309 }
5310 #endif
5311
5312 static void bnxt_timer(unsigned long data)
5313 {
5314         struct bnxt *bp = (struct bnxt *)data;
5315         struct net_device *dev = bp->dev;
5316
5317         if (!netif_running(dev))
5318                 return;
5319
5320         if (atomic_read(&bp->intr_sem) != 0)
5321                 goto bnxt_restart_timer;
5322
5323         if (bp->link_info.link_up && (bp->flags & BNXT_FLAG_PORT_STATS)) {
5324                 set_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event);
5325                 schedule_work(&bp->sp_task);
5326         }
5327 bnxt_restart_timer:
5328         mod_timer(&bp->timer, jiffies + bp->current_interval);
5329 }
5330
5331 static void bnxt_cfg_ntp_filters(struct bnxt *);
5332
5333 static void bnxt_sp_task(struct work_struct *work)
5334 {
5335         struct bnxt *bp = container_of(work, struct bnxt, sp_task);
5336         int rc;
5337
5338         set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
5339         smp_mb__after_atomic();
5340         if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
5341                 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
5342                 return;
5343         }
5344
5345         if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event))
5346                 bnxt_cfg_rx_mode(bp);
5347
5348         if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event))
5349                 bnxt_cfg_ntp_filters(bp);
5350         if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) {
5351                 rc = bnxt_update_link(bp, true);
5352                 if (rc)
5353                         netdev_err(bp->dev, "SP task can't update link (rc: %x)\n",
5354                                    rc);
5355         }
5356         if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event))
5357                 bnxt_hwrm_exec_fwd_req(bp);
5358         if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) {
5359                 bnxt_hwrm_tunnel_dst_port_alloc(
5360                         bp, bp->vxlan_port,
5361                         TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
5362         }
5363         if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) {
5364                 bnxt_hwrm_tunnel_dst_port_free(
5365                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
5366         }
5367         if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event)) {
5368                 /* bnxt_reset_task() calls bnxt_close_nic() which waits
5369                  * for BNXT_STATE_IN_SP_TASK to clear.
5370                  */
5371                 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
5372                 rtnl_lock();
5373                 bnxt_reset_task(bp);
5374                 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
5375                 rtnl_unlock();
5376         }
5377
5378         if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event))
5379                 bnxt_hwrm_port_qstats(bp);
5380
5381         smp_mb__before_atomic();
5382         clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
5383 }
5384
5385 static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev)
5386 {
5387         int rc;
5388         struct bnxt *bp = netdev_priv(dev);
5389
5390         SET_NETDEV_DEV(dev, &pdev->dev);
5391
5392         /* enable device (incl. PCI PM wakeup), and bus-mastering */
5393         rc = pci_enable_device(pdev);
5394         if (rc) {
5395                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
5396                 goto init_err;
5397         }
5398
5399         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
5400                 dev_err(&pdev->dev,
5401                         "Cannot find PCI device base address, aborting\n");
5402                 rc = -ENODEV;
5403                 goto init_err_disable;
5404         }
5405
5406         rc = pci_request_regions(pdev, DRV_MODULE_NAME);
5407         if (rc) {
5408                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
5409                 goto init_err_disable;
5410         }
5411
5412         if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 &&
5413             dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
5414                 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
5415                 goto init_err_disable;
5416         }
5417
5418         pci_set_master(pdev);
5419
5420         bp->dev = dev;
5421         bp->pdev = pdev;
5422
5423         bp->bar0 = pci_ioremap_bar(pdev, 0);
5424         if (!bp->bar0) {
5425                 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
5426                 rc = -ENOMEM;
5427                 goto init_err_release;
5428         }
5429
5430         bp->bar1 = pci_ioremap_bar(pdev, 2);
5431         if (!bp->bar1) {
5432                 dev_err(&pdev->dev, "Cannot map doorbell registers, aborting\n");
5433                 rc = -ENOMEM;
5434                 goto init_err_release;
5435         }
5436
5437         bp->bar2 = pci_ioremap_bar(pdev, 4);
5438         if (!bp->bar2) {
5439                 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n");
5440                 rc = -ENOMEM;
5441                 goto init_err_release;
5442         }
5443
5444         pci_enable_pcie_error_reporting(pdev);
5445
5446         INIT_WORK(&bp->sp_task, bnxt_sp_task);
5447
5448         spin_lock_init(&bp->ntp_fltr_lock);
5449
5450         bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE;
5451         bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE;
5452
5453         /* tick values in micro seconds */
5454         bp->rx_coal_ticks = 12;
5455         bp->rx_coal_bufs = 30;
5456         bp->rx_coal_ticks_irq = 1;
5457         bp->rx_coal_bufs_irq = 2;
5458
5459         bp->tx_coal_ticks = 25;
5460         bp->tx_coal_bufs = 30;
5461         bp->tx_coal_ticks_irq = 2;
5462         bp->tx_coal_bufs_irq = 2;
5463
5464         init_timer(&bp->timer);
5465         bp->timer.data = (unsigned long)bp;
5466         bp->timer.function = bnxt_timer;
5467         bp->current_interval = BNXT_TIMER_INTERVAL;
5468
5469         clear_bit(BNXT_STATE_OPEN, &bp->state);
5470
5471         return 0;
5472
5473 init_err_release:
5474         if (bp->bar2) {
5475                 pci_iounmap(pdev, bp->bar2);
5476                 bp->bar2 = NULL;
5477         }
5478
5479         if (bp->bar1) {
5480                 pci_iounmap(pdev, bp->bar1);
5481                 bp->bar1 = NULL;
5482         }
5483
5484         if (bp->bar0) {
5485                 pci_iounmap(pdev, bp->bar0);
5486                 bp->bar0 = NULL;
5487         }
5488
5489         pci_release_regions(pdev);
5490
5491 init_err_disable:
5492         pci_disable_device(pdev);
5493
5494 init_err:
5495         return rc;
5496 }
5497
5498 /* rtnl_lock held */
5499 static int bnxt_change_mac_addr(struct net_device *dev, void *p)
5500 {
5501         struct sockaddr *addr = p;
5502         struct bnxt *bp = netdev_priv(dev);
5503         int rc = 0;
5504
5505         if (!is_valid_ether_addr(addr->sa_data))
5506                 return -EADDRNOTAVAIL;
5507
5508 #ifdef CONFIG_BNXT_SRIOV
5509         if (BNXT_VF(bp) && is_valid_ether_addr(bp->vf.mac_addr))
5510                 return -EADDRNOTAVAIL;
5511 #endif
5512
5513         if (ether_addr_equal(addr->sa_data, dev->dev_addr))
5514                 return 0;
5515
5516         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5517         if (netif_running(dev)) {
5518                 bnxt_close_nic(bp, false, false);
5519                 rc = bnxt_open_nic(bp, false, false);
5520         }
5521
5522         return rc;
5523 }
5524
5525 /* rtnl_lock held */
5526 static int bnxt_change_mtu(struct net_device *dev, int new_mtu)
5527 {
5528         struct bnxt *bp = netdev_priv(dev);
5529
5530         if (new_mtu < 60 || new_mtu > 9000)
5531                 return -EINVAL;
5532
5533         if (netif_running(dev))
5534                 bnxt_close_nic(bp, false, false);
5535
5536         dev->mtu = new_mtu;
5537         bnxt_set_ring_params(bp);
5538
5539         if (netif_running(dev))
5540                 return bnxt_open_nic(bp, false, false);
5541
5542         return 0;
5543 }
5544
5545 static int bnxt_setup_tc(struct net_device *dev, u32 handle, __be16 proto,
5546                          struct tc_to_netdev *ntc)
5547 {
5548         struct bnxt *bp = netdev_priv(dev);
5549         u8 tc;
5550
5551         if (ntc->type != TC_SETUP_MQPRIO)
5552                 return -EINVAL;
5553
5554         tc = ntc->tc;
5555
5556         if (tc > bp->max_tc) {
5557                 netdev_err(dev, "too many traffic classes requested: %d Max supported is %d\n",
5558                            tc, bp->max_tc);
5559                 return -EINVAL;
5560         }
5561
5562         if (netdev_get_num_tc(dev) == tc)
5563                 return 0;
5564
5565         if (tc) {
5566                 int max_rx_rings, max_tx_rings, rc;
5567                 bool sh = false;
5568
5569                 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
5570                         sh = true;
5571
5572                 rc = bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, sh);
5573                 if (rc || bp->tx_nr_rings_per_tc * tc > max_tx_rings)
5574                         return -ENOMEM;
5575         }
5576
5577         /* Needs to close the device and do hw resource re-allocations */
5578         if (netif_running(bp->dev))
5579                 bnxt_close_nic(bp, true, false);
5580
5581         if (tc) {
5582                 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc;
5583                 netdev_set_num_tc(dev, tc);
5584         } else {
5585                 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
5586                 netdev_reset_tc(dev);
5587         }
5588         bp->cp_nr_rings = max_t(int, bp->tx_nr_rings, bp->rx_nr_rings);
5589         bp->num_stat_ctxs = bp->cp_nr_rings;
5590
5591         if (netif_running(bp->dev))
5592                 return bnxt_open_nic(bp, true, false);
5593
5594         return 0;
5595 }
5596
5597 #ifdef CONFIG_RFS_ACCEL
5598 static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1,
5599                             struct bnxt_ntuple_filter *f2)
5600 {
5601         struct flow_keys *keys1 = &f1->fkeys;
5602         struct flow_keys *keys2 = &f2->fkeys;
5603
5604         if (keys1->addrs.v4addrs.src == keys2->addrs.v4addrs.src &&
5605             keys1->addrs.v4addrs.dst == keys2->addrs.v4addrs.dst &&
5606             keys1->ports.ports == keys2->ports.ports &&
5607             keys1->basic.ip_proto == keys2->basic.ip_proto &&
5608             keys1->basic.n_proto == keys2->basic.n_proto &&
5609             ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr))
5610                 return true;
5611
5612         return false;
5613 }
5614
5615 static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
5616                               u16 rxq_index, u32 flow_id)
5617 {
5618         struct bnxt *bp = netdev_priv(dev);
5619         struct bnxt_ntuple_filter *fltr, *new_fltr;
5620         struct flow_keys *fkeys;
5621         struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb);
5622         int rc = 0, idx, bit_id;
5623         struct hlist_head *head;
5624
5625         if (skb->encapsulation)
5626                 return -EPROTONOSUPPORT;
5627
5628         new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC);
5629         if (!new_fltr)
5630                 return -ENOMEM;
5631
5632         fkeys = &new_fltr->fkeys;
5633         if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) {
5634                 rc = -EPROTONOSUPPORT;
5635                 goto err_free;
5636         }
5637
5638         if ((fkeys->basic.n_proto != htons(ETH_P_IP)) ||
5639             ((fkeys->basic.ip_proto != IPPROTO_TCP) &&
5640              (fkeys->basic.ip_proto != IPPROTO_UDP))) {
5641                 rc = -EPROTONOSUPPORT;
5642                 goto err_free;
5643         }
5644
5645         memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN);
5646
5647         idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK;
5648         head = &bp->ntp_fltr_hash_tbl[idx];
5649         rcu_read_lock();
5650         hlist_for_each_entry_rcu(fltr, head, hash) {
5651                 if (bnxt_fltr_match(fltr, new_fltr)) {
5652                         rcu_read_unlock();
5653                         rc = 0;
5654                         goto err_free;
5655                 }
5656         }
5657         rcu_read_unlock();
5658
5659         spin_lock_bh(&bp->ntp_fltr_lock);
5660         bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap,
5661                                          BNXT_NTP_FLTR_MAX_FLTR, 0);
5662         if (bit_id < 0) {
5663                 spin_unlock_bh(&bp->ntp_fltr_lock);
5664                 rc = -ENOMEM;
5665                 goto err_free;
5666         }
5667
5668         new_fltr->sw_id = (u16)bit_id;
5669         new_fltr->flow_id = flow_id;
5670         new_fltr->rxq = rxq_index;
5671         hlist_add_head_rcu(&new_fltr->hash, head);
5672         bp->ntp_fltr_count++;
5673         spin_unlock_bh(&bp->ntp_fltr_lock);
5674
5675         set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event);
5676         schedule_work(&bp->sp_task);
5677
5678         return new_fltr->sw_id;
5679
5680 err_free:
5681         kfree(new_fltr);
5682         return rc;
5683 }
5684
5685 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
5686 {
5687         int i;
5688
5689         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
5690                 struct hlist_head *head;
5691                 struct hlist_node *tmp;
5692                 struct bnxt_ntuple_filter *fltr;
5693                 int rc;
5694
5695                 head = &bp->ntp_fltr_hash_tbl[i];
5696                 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
5697                         bool del = false;
5698
5699                         if (test_bit(BNXT_FLTR_VALID, &fltr->state)) {
5700                                 if (rps_may_expire_flow(bp->dev, fltr->rxq,
5701                                                         fltr->flow_id,
5702                                                         fltr->sw_id)) {
5703                                         bnxt_hwrm_cfa_ntuple_filter_free(bp,
5704                                                                          fltr);
5705                                         del = true;
5706                                 }
5707                         } else {
5708                                 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp,
5709                                                                        fltr);
5710                                 if (rc)
5711                                         del = true;
5712                                 else
5713                                         set_bit(BNXT_FLTR_VALID, &fltr->state);
5714                         }
5715
5716                         if (del) {
5717                                 spin_lock_bh(&bp->ntp_fltr_lock);
5718                                 hlist_del_rcu(&fltr->hash);
5719                                 bp->ntp_fltr_count--;
5720                                 spin_unlock_bh(&bp->ntp_fltr_lock);
5721                                 synchronize_rcu();
5722                                 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap);
5723                                 kfree(fltr);
5724                         }
5725                 }
5726         }
5727         if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event))
5728                 netdev_info(bp->dev, "Receive PF driver unload event!");
5729 }
5730
5731 #else
5732
5733 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
5734 {
5735 }
5736
5737 #endif /* CONFIG_RFS_ACCEL */
5738
5739 static void bnxt_add_vxlan_port(struct net_device *dev, sa_family_t sa_family,
5740                                 __be16 port)
5741 {
5742         struct bnxt *bp = netdev_priv(dev);
5743
5744         if (!netif_running(dev))
5745                 return;
5746
5747         if (sa_family != AF_INET6 && sa_family != AF_INET)
5748                 return;
5749
5750         if (bp->vxlan_port_cnt && bp->vxlan_port != port)
5751                 return;
5752
5753         bp->vxlan_port_cnt++;
5754         if (bp->vxlan_port_cnt == 1) {
5755                 bp->vxlan_port = port;
5756                 set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event);
5757                 schedule_work(&bp->sp_task);
5758         }
5759 }
5760
5761 static void bnxt_del_vxlan_port(struct net_device *dev, sa_family_t sa_family,
5762                                 __be16 port)
5763 {
5764         struct bnxt *bp = netdev_priv(dev);
5765
5766         if (!netif_running(dev))
5767                 return;
5768
5769         if (sa_family != AF_INET6 && sa_family != AF_INET)
5770                 return;
5771
5772         if (bp->vxlan_port_cnt && bp->vxlan_port == port) {
5773                 bp->vxlan_port_cnt--;
5774
5775                 if (bp->vxlan_port_cnt == 0) {
5776                         set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event);
5777                         schedule_work(&bp->sp_task);
5778                 }
5779         }
5780 }
5781
5782 static const struct net_device_ops bnxt_netdev_ops = {
5783         .ndo_open               = bnxt_open,
5784         .ndo_start_xmit         = bnxt_start_xmit,
5785         .ndo_stop               = bnxt_close,
5786         .ndo_get_stats64        = bnxt_get_stats64,
5787         .ndo_set_rx_mode        = bnxt_set_rx_mode,
5788         .ndo_do_ioctl           = bnxt_ioctl,
5789         .ndo_validate_addr      = eth_validate_addr,
5790         .ndo_set_mac_address    = bnxt_change_mac_addr,
5791         .ndo_change_mtu         = bnxt_change_mtu,
5792         .ndo_fix_features       = bnxt_fix_features,
5793         .ndo_set_features       = bnxt_set_features,
5794         .ndo_tx_timeout         = bnxt_tx_timeout,
5795 #ifdef CONFIG_BNXT_SRIOV
5796         .ndo_get_vf_config      = bnxt_get_vf_config,
5797         .ndo_set_vf_mac         = bnxt_set_vf_mac,
5798         .ndo_set_vf_vlan        = bnxt_set_vf_vlan,
5799         .ndo_set_vf_rate        = bnxt_set_vf_bw,
5800         .ndo_set_vf_link_state  = bnxt_set_vf_link_state,
5801         .ndo_set_vf_spoofchk    = bnxt_set_vf_spoofchk,
5802 #endif
5803 #ifdef CONFIG_NET_POLL_CONTROLLER
5804         .ndo_poll_controller    = bnxt_poll_controller,
5805 #endif
5806         .ndo_setup_tc           = bnxt_setup_tc,
5807 #ifdef CONFIG_RFS_ACCEL
5808         .ndo_rx_flow_steer      = bnxt_rx_flow_steer,
5809 #endif
5810         .ndo_add_vxlan_port     = bnxt_add_vxlan_port,
5811         .ndo_del_vxlan_port     = bnxt_del_vxlan_port,
5812 #ifdef CONFIG_NET_RX_BUSY_POLL
5813         .ndo_busy_poll          = bnxt_busy_poll,
5814 #endif
5815 };
5816
5817 static void bnxt_remove_one(struct pci_dev *pdev)
5818 {
5819         struct net_device *dev = pci_get_drvdata(pdev);
5820         struct bnxt *bp = netdev_priv(dev);
5821
5822         if (BNXT_PF(bp))
5823                 bnxt_sriov_disable(bp);
5824
5825         pci_disable_pcie_error_reporting(pdev);
5826         unregister_netdev(dev);
5827         cancel_work_sync(&bp->sp_task);
5828         bp->sp_event = 0;
5829
5830         bnxt_hwrm_func_drv_unrgtr(bp);
5831         bnxt_free_hwrm_resources(bp);
5832         pci_iounmap(pdev, bp->bar2);
5833         pci_iounmap(pdev, bp->bar1);
5834         pci_iounmap(pdev, bp->bar0);
5835         free_netdev(dev);
5836
5837         pci_release_regions(pdev);
5838         pci_disable_device(pdev);
5839 }
5840
5841 static int bnxt_probe_phy(struct bnxt *bp)
5842 {
5843         int rc = 0;
5844         struct bnxt_link_info *link_info = &bp->link_info;
5845
5846         rc = bnxt_update_link(bp, false);
5847         if (rc) {
5848                 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n",
5849                            rc);
5850                 return rc;
5851         }
5852
5853         /*initialize the ethool setting copy with NVM settings */
5854         if (BNXT_AUTO_MODE(link_info->auto_mode)) {
5855                 link_info->autoneg = BNXT_AUTONEG_SPEED |
5856                                      BNXT_AUTONEG_FLOW_CTRL;
5857                 link_info->advertising = link_info->auto_link_speeds;
5858                 link_info->req_flow_ctrl = link_info->auto_pause_setting;
5859         } else {
5860                 link_info->req_link_speed = link_info->force_link_speed;
5861                 link_info->req_duplex = link_info->duplex_setting;
5862                 link_info->req_flow_ctrl = link_info->force_pause_setting;
5863         }
5864         return rc;
5865 }
5866
5867 static int bnxt_get_max_irq(struct pci_dev *pdev)
5868 {
5869         u16 ctrl;
5870
5871         if (!pdev->msix_cap)
5872                 return 1;
5873
5874         pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
5875         return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
5876 }
5877
5878 static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx,
5879                                 int *max_cp)
5880 {
5881         int max_ring_grps = 0;
5882
5883 #ifdef CONFIG_BNXT_SRIOV
5884         if (!BNXT_PF(bp)) {
5885                 *max_tx = bp->vf.max_tx_rings;
5886                 *max_rx = bp->vf.max_rx_rings;
5887                 *max_cp = min_t(int, bp->vf.max_irqs, bp->vf.max_cp_rings);
5888                 *max_cp = min_t(int, *max_cp, bp->vf.max_stat_ctxs);
5889                 max_ring_grps = bp->vf.max_hw_ring_grps;
5890         } else
5891 #endif
5892         {
5893                 *max_tx = bp->pf.max_tx_rings;
5894                 *max_rx = bp->pf.max_rx_rings;
5895                 *max_cp = min_t(int, bp->pf.max_irqs, bp->pf.max_cp_rings);
5896                 *max_cp = min_t(int, *max_cp, bp->pf.max_stat_ctxs);
5897                 max_ring_grps = bp->pf.max_hw_ring_grps;
5898         }
5899
5900         if (bp->flags & BNXT_FLAG_AGG_RINGS)
5901                 *max_rx >>= 1;
5902         *max_rx = min_t(int, *max_rx, max_ring_grps);
5903 }
5904
5905 int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared)
5906 {
5907         int rx, tx, cp;
5908
5909         _bnxt_get_max_rings(bp, &rx, &tx, &cp);
5910         if (!rx || !tx || !cp)
5911                 return -ENOMEM;
5912
5913         *max_rx = rx;
5914         *max_tx = tx;
5915         return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared);
5916 }
5917
5918 static int bnxt_set_dflt_rings(struct bnxt *bp)
5919 {
5920         int dflt_rings, max_rx_rings, max_tx_rings, rc;
5921         bool sh = true;
5922
5923         if (sh)
5924                 bp->flags |= BNXT_FLAG_SHARED_RINGS;
5925         dflt_rings = netif_get_num_default_rss_queues();
5926         rc = bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, sh);
5927         if (rc)
5928                 return rc;
5929         bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings);
5930         bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings);
5931         bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
5932         bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
5933                                bp->tx_nr_rings + bp->rx_nr_rings;
5934         bp->num_stat_ctxs = bp->cp_nr_rings;
5935         return rc;
5936 }
5937
5938 static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
5939 {
5940         static int version_printed;
5941         struct net_device *dev;
5942         struct bnxt *bp;
5943         int rc, max_irqs;
5944
5945         if (version_printed++ == 0)
5946                 pr_info("%s", version);
5947
5948         max_irqs = bnxt_get_max_irq(pdev);
5949         dev = alloc_etherdev_mq(sizeof(*bp), max_irqs);
5950         if (!dev)
5951                 return -ENOMEM;
5952
5953         bp = netdev_priv(dev);
5954
5955         if (bnxt_vf_pciid(ent->driver_data))
5956                 bp->flags |= BNXT_FLAG_VF;
5957
5958         if (pdev->msix_cap)
5959                 bp->flags |= BNXT_FLAG_MSIX_CAP;
5960
5961         rc = bnxt_init_board(pdev, dev);
5962         if (rc < 0)
5963                 goto init_err_free;
5964
5965         dev->netdev_ops = &bnxt_netdev_ops;
5966         dev->watchdog_timeo = BNXT_TX_TIMEOUT;
5967         dev->ethtool_ops = &bnxt_ethtool_ops;
5968
5969         pci_set_drvdata(pdev, dev);
5970
5971         dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
5972                            NETIF_F_TSO | NETIF_F_TSO6 |
5973                            NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
5974                            NETIF_F_GSO_IPIP | NETIF_F_GSO_SIT |
5975                            NETIF_F_RXHASH |
5976                            NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO;
5977
5978         dev->hw_enc_features =
5979                         NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
5980                         NETIF_F_TSO | NETIF_F_TSO6 |
5981                         NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
5982                         NETIF_F_GSO_IPIP | NETIF_F_GSO_SIT;
5983         dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA;
5984         dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
5985                             NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX;
5986         dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
5987         dev->priv_flags |= IFF_UNICAST_FLT;
5988
5989 #ifdef CONFIG_BNXT_SRIOV
5990         init_waitqueue_head(&bp->sriov_cfg_wait);
5991 #endif
5992         rc = bnxt_alloc_hwrm_resources(bp);
5993         if (rc)
5994                 goto init_err;
5995
5996         mutex_init(&bp->hwrm_cmd_lock);
5997         bnxt_hwrm_ver_get(bp);
5998
5999         rc = bnxt_hwrm_func_drv_rgtr(bp);
6000         if (rc)
6001                 goto init_err;
6002
6003         /* Get the MAX capabilities for this function */
6004         rc = bnxt_hwrm_func_qcaps(bp);
6005         if (rc) {
6006                 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n",
6007                            rc);
6008                 rc = -1;
6009                 goto init_err;
6010         }
6011
6012         rc = bnxt_hwrm_queue_qportcfg(bp);
6013         if (rc) {
6014                 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %x\n",
6015                            rc);
6016                 rc = -1;
6017                 goto init_err;
6018         }
6019
6020         bnxt_set_tpa_flags(bp);
6021         bnxt_set_ring_params(bp);
6022         if (BNXT_PF(bp))
6023                 bp->pf.max_irqs = max_irqs;
6024 #if defined(CONFIG_BNXT_SRIOV)
6025         else
6026                 bp->vf.max_irqs = max_irqs;
6027 #endif
6028         bnxt_set_dflt_rings(bp);
6029
6030         if (BNXT_PF(bp)) {
6031                 dev->hw_features |= NETIF_F_NTUPLE;
6032                 if (bnxt_rfs_capable(bp)) {
6033                         bp->flags |= BNXT_FLAG_RFS;
6034                         dev->features |= NETIF_F_NTUPLE;
6035                 }
6036         }
6037
6038         if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX)
6039                 bp->flags |= BNXT_FLAG_STRIP_VLAN;
6040
6041         rc = bnxt_probe_phy(bp);
6042         if (rc)
6043                 goto init_err;
6044
6045         rc = register_netdev(dev);
6046         if (rc)
6047                 goto init_err;
6048
6049         netdev_info(dev, "%s found at mem %lx, node addr %pM\n",
6050                     board_info[ent->driver_data].name,
6051                     (long)pci_resource_start(pdev, 0), dev->dev_addr);
6052
6053         return 0;
6054
6055 init_err:
6056         pci_iounmap(pdev, bp->bar0);
6057         pci_release_regions(pdev);
6058         pci_disable_device(pdev);
6059
6060 init_err_free:
6061         free_netdev(dev);
6062         return rc;
6063 }
6064
6065 /**
6066  * bnxt_io_error_detected - called when PCI error is detected
6067  * @pdev: Pointer to PCI device
6068  * @state: The current pci connection state
6069  *
6070  * This function is called after a PCI bus error affecting
6071  * this device has been detected.
6072  */
6073 static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev,
6074                                                pci_channel_state_t state)
6075 {
6076         struct net_device *netdev = pci_get_drvdata(pdev);
6077
6078         netdev_info(netdev, "PCI I/O error detected\n");
6079
6080         rtnl_lock();
6081         netif_device_detach(netdev);
6082
6083         if (state == pci_channel_io_perm_failure) {
6084                 rtnl_unlock();
6085                 return PCI_ERS_RESULT_DISCONNECT;
6086         }
6087
6088         if (netif_running(netdev))
6089                 bnxt_close(netdev);
6090
6091         pci_disable_device(pdev);
6092         rtnl_unlock();
6093
6094         /* Request a slot slot reset. */
6095         return PCI_ERS_RESULT_NEED_RESET;
6096 }
6097
6098 /**
6099  * bnxt_io_slot_reset - called after the pci bus has been reset.
6100  * @pdev: Pointer to PCI device
6101  *
6102  * Restart the card from scratch, as if from a cold-boot.
6103  * At this point, the card has exprienced a hard reset,
6104  * followed by fixups by BIOS, and has its config space
6105  * set up identically to what it was at cold boot.
6106  */
6107 static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev)
6108 {
6109         struct net_device *netdev = pci_get_drvdata(pdev);
6110         struct bnxt *bp = netdev_priv(netdev);
6111         int err = 0;
6112         pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT;
6113
6114         netdev_info(bp->dev, "PCI Slot Reset\n");
6115
6116         rtnl_lock();
6117
6118         if (pci_enable_device(pdev)) {
6119                 dev_err(&pdev->dev,
6120                         "Cannot re-enable PCI device after reset.\n");
6121         } else {
6122                 pci_set_master(pdev);
6123
6124                 if (netif_running(netdev))
6125                         err = bnxt_open(netdev);
6126
6127                 if (!err)
6128                         result = PCI_ERS_RESULT_RECOVERED;
6129         }
6130
6131         if (result != PCI_ERS_RESULT_RECOVERED && netif_running(netdev))
6132                 dev_close(netdev);
6133
6134         rtnl_unlock();
6135
6136         err = pci_cleanup_aer_uncorrect_error_status(pdev);
6137         if (err) {
6138                 dev_err(&pdev->dev,
6139                         "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
6140                          err); /* non-fatal, continue */
6141         }
6142
6143         return PCI_ERS_RESULT_RECOVERED;
6144 }
6145
6146 /**
6147  * bnxt_io_resume - called when traffic can start flowing again.
6148  * @pdev: Pointer to PCI device
6149  *
6150  * This callback is called when the error recovery driver tells
6151  * us that its OK to resume normal operation.
6152  */
6153 static void bnxt_io_resume(struct pci_dev *pdev)
6154 {
6155         struct net_device *netdev = pci_get_drvdata(pdev);
6156
6157         rtnl_lock();
6158
6159         netif_device_attach(netdev);
6160
6161         rtnl_unlock();
6162 }
6163
6164 static const struct pci_error_handlers bnxt_err_handler = {
6165         .error_detected = bnxt_io_error_detected,
6166         .slot_reset     = bnxt_io_slot_reset,
6167         .resume         = bnxt_io_resume
6168 };
6169
6170 static struct pci_driver bnxt_pci_driver = {
6171         .name           = DRV_MODULE_NAME,
6172         .id_table       = bnxt_pci_tbl,
6173         .probe          = bnxt_init_one,
6174         .remove         = bnxt_remove_one,
6175         .err_handler    = &bnxt_err_handler,
6176 #if defined(CONFIG_BNXT_SRIOV)
6177         .sriov_configure = bnxt_sriov_configure,
6178 #endif
6179 };
6180
6181 module_pci_driver(bnxt_pci_driver);