Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
[cascardo/linux.git] / drivers / net / ethernet / broadcom / bnxt / bnxt.h
1 /* Broadcom NetXtreme-C/E network driver.
2  *
3  * Copyright (c) 2014-2016 Broadcom Corporation
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation.
8  */
9
10 #ifndef BNXT_H
11 #define BNXT_H
12
13 #define DRV_MODULE_NAME         "bnxt_en"
14 #define DRV_MODULE_VERSION      "1.2.0"
15
16 #define DRV_VER_MAJ     1
17 #define DRV_VER_MIN     0
18 #define DRV_VER_UPD     0
19
20 struct tx_bd {
21         __le32 tx_bd_len_flags_type;
22         #define TX_BD_TYPE                                      (0x3f << 0)
23          #define TX_BD_TYPE_SHORT_TX_BD                          (0x00 << 0)
24          #define TX_BD_TYPE_LONG_TX_BD                           (0x10 << 0)
25         #define TX_BD_FLAGS_PACKET_END                          (1 << 6)
26         #define TX_BD_FLAGS_NO_CMPL                             (1 << 7)
27         #define TX_BD_FLAGS_BD_CNT                              (0x1f << 8)
28          #define TX_BD_FLAGS_BD_CNT_SHIFT                        8
29         #define TX_BD_FLAGS_LHINT                               (3 << 13)
30          #define TX_BD_FLAGS_LHINT_SHIFT                         13
31          #define TX_BD_FLAGS_LHINT_512_AND_SMALLER               (0 << 13)
32          #define TX_BD_FLAGS_LHINT_512_TO_1023                   (1 << 13)
33          #define TX_BD_FLAGS_LHINT_1024_TO_2047                  (2 << 13)
34          #define TX_BD_FLAGS_LHINT_2048_AND_LARGER               (3 << 13)
35         #define TX_BD_FLAGS_COAL_NOW                            (1 << 15)
36         #define TX_BD_LEN                                       (0xffff << 16)
37          #define TX_BD_LEN_SHIFT                                 16
38
39         u32 tx_bd_opaque;
40         __le64 tx_bd_haddr;
41 } __packed;
42
43 struct tx_bd_ext {
44         __le32 tx_bd_hsize_lflags;
45         #define TX_BD_FLAGS_TCP_UDP_CHKSUM                      (1 << 0)
46         #define TX_BD_FLAGS_IP_CKSUM                            (1 << 1)
47         #define TX_BD_FLAGS_NO_CRC                              (1 << 2)
48         #define TX_BD_FLAGS_STAMP                               (1 << 3)
49         #define TX_BD_FLAGS_T_IP_CHKSUM                         (1 << 4)
50         #define TX_BD_FLAGS_LSO                                 (1 << 5)
51         #define TX_BD_FLAGS_IPID_FMT                            (1 << 6)
52         #define TX_BD_FLAGS_T_IPID                              (1 << 7)
53         #define TX_BD_HSIZE                                     (0xff << 16)
54          #define TX_BD_HSIZE_SHIFT                               16
55
56         __le32 tx_bd_mss;
57         __le32 tx_bd_cfa_action;
58         #define TX_BD_CFA_ACTION                                (0xffff << 16)
59          #define TX_BD_CFA_ACTION_SHIFT                          16
60
61         __le32 tx_bd_cfa_meta;
62         #define TX_BD_CFA_META_MASK                             0xfffffff
63         #define TX_BD_CFA_META_VID_MASK                         0xfff
64         #define TX_BD_CFA_META_PRI_MASK                         (0xf << 12)
65          #define TX_BD_CFA_META_PRI_SHIFT                        12
66         #define TX_BD_CFA_META_TPID_MASK                        (3 << 16)
67          #define TX_BD_CFA_META_TPID_SHIFT                       16
68         #define TX_BD_CFA_META_KEY                              (0xf << 28)
69          #define TX_BD_CFA_META_KEY_SHIFT                        28
70         #define TX_BD_CFA_META_KEY_VLAN                         (1 << 28)
71 };
72
73 struct rx_bd {
74         __le32 rx_bd_len_flags_type;
75         #define RX_BD_TYPE                                      (0x3f << 0)
76          #define RX_BD_TYPE_RX_PACKET_BD                         0x4
77          #define RX_BD_TYPE_RX_BUFFER_BD                         0x5
78          #define RX_BD_TYPE_RX_AGG_BD                            0x6
79          #define RX_BD_TYPE_16B_BD_SIZE                          (0 << 4)
80          #define RX_BD_TYPE_32B_BD_SIZE                          (1 << 4)
81          #define RX_BD_TYPE_48B_BD_SIZE                          (2 << 4)
82          #define RX_BD_TYPE_64B_BD_SIZE                          (3 << 4)
83         #define RX_BD_FLAGS_SOP                                 (1 << 6)
84         #define RX_BD_FLAGS_EOP                                 (1 << 7)
85         #define RX_BD_FLAGS_BUFFERS                             (3 << 8)
86          #define RX_BD_FLAGS_1_BUFFER_PACKET                     (0 << 8)
87          #define RX_BD_FLAGS_2_BUFFER_PACKET                     (1 << 8)
88          #define RX_BD_FLAGS_3_BUFFER_PACKET                     (2 << 8)
89          #define RX_BD_FLAGS_4_BUFFER_PACKET                     (3 << 8)
90         #define RX_BD_LEN                                       (0xffff << 16)
91          #define RX_BD_LEN_SHIFT                                 16
92
93         u32 rx_bd_opaque;
94         __le64 rx_bd_haddr;
95 };
96
97 struct tx_cmp {
98         __le32 tx_cmp_flags_type;
99         #define CMP_TYPE                                        (0x3f << 0)
100          #define CMP_TYPE_TX_L2_CMP                              0
101          #define CMP_TYPE_RX_L2_CMP                              17
102          #define CMP_TYPE_RX_AGG_CMP                             18
103          #define CMP_TYPE_RX_L2_TPA_START_CMP                    19
104          #define CMP_TYPE_RX_L2_TPA_END_CMP                      21
105          #define CMP_TYPE_STATUS_CMP                             32
106          #define CMP_TYPE_REMOTE_DRIVER_REQ                      34
107          #define CMP_TYPE_REMOTE_DRIVER_RESP                     36
108          #define CMP_TYPE_ERROR_STATUS                           48
109          #define CMPL_BASE_TYPE_STAT_EJECT                       (0x1aUL << 0)
110          #define CMPL_BASE_TYPE_HWRM_DONE                        (0x20UL << 0)
111          #define CMPL_BASE_TYPE_HWRM_FWD_REQ                     (0x22UL << 0)
112          #define CMPL_BASE_TYPE_HWRM_FWD_RESP                    (0x24UL << 0)
113          #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT                 (0x2eUL << 0)
114
115         #define TX_CMP_FLAGS_ERROR                              (1 << 6)
116         #define TX_CMP_FLAGS_PUSH                               (1 << 7)
117
118         u32 tx_cmp_opaque;
119         __le32 tx_cmp_errors_v;
120         #define TX_CMP_V                                        (1 << 0)
121         #define TX_CMP_ERRORS_BUFFER_ERROR                      (7 << 1)
122          #define TX_CMP_ERRORS_BUFFER_ERROR_NO_ERROR             0
123          #define TX_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT           2
124          #define TX_CMP_ERRORS_BUFFER_ERROR_INVALID_STAG         4
125          #define TX_CMP_ERRORS_BUFFER_ERROR_STAG_BOUNDS          5
126          #define TX_CMP_ERRORS_ZERO_LENGTH_PKT                   (1 << 4)
127          #define TX_CMP_ERRORS_EXCESSIVE_BD_LEN                  (1 << 5)
128          #define TX_CMP_ERRORS_DMA_ERROR                         (1 << 6)
129          #define TX_CMP_ERRORS_HINT_TOO_SHORT                    (1 << 7)
130
131         __le32 tx_cmp_unsed_3;
132 };
133
134 struct rx_cmp {
135         __le32 rx_cmp_len_flags_type;
136         #define RX_CMP_CMP_TYPE                                 (0x3f << 0)
137         #define RX_CMP_FLAGS_ERROR                              (1 << 6)
138         #define RX_CMP_FLAGS_PLACEMENT                          (7 << 7)
139         #define RX_CMP_FLAGS_RSS_VALID                          (1 << 10)
140         #define RX_CMP_FLAGS_UNUSED                             (1 << 11)
141          #define RX_CMP_FLAGS_ITYPES_SHIFT                       12
142          #define RX_CMP_FLAGS_ITYPE_UNKNOWN                      (0 << 12)
143          #define RX_CMP_FLAGS_ITYPE_IP                           (1 << 12)
144          #define RX_CMP_FLAGS_ITYPE_TCP                          (2 << 12)
145          #define RX_CMP_FLAGS_ITYPE_UDP                          (3 << 12)
146          #define RX_CMP_FLAGS_ITYPE_FCOE                         (4 << 12)
147          #define RX_CMP_FLAGS_ITYPE_ROCE                         (5 << 12)
148          #define RX_CMP_FLAGS_ITYPE_PTP_WO_TS                    (8 << 12)
149          #define RX_CMP_FLAGS_ITYPE_PTP_W_TS                     (9 << 12)
150         #define RX_CMP_LEN                                      (0xffff << 16)
151          #define RX_CMP_LEN_SHIFT                                16
152
153         u32 rx_cmp_opaque;
154         __le32 rx_cmp_misc_v1;
155         #define RX_CMP_V1                                       (1 << 0)
156         #define RX_CMP_AGG_BUFS                                 (0x1f << 1)
157          #define RX_CMP_AGG_BUFS_SHIFT                           1
158         #define RX_CMP_RSS_HASH_TYPE                            (0x7f << 9)
159          #define RX_CMP_RSS_HASH_TYPE_SHIFT                      9
160         #define RX_CMP_PAYLOAD_OFFSET                           (0xff << 16)
161          #define RX_CMP_PAYLOAD_OFFSET_SHIFT                     16
162
163         __le32 rx_cmp_rss_hash;
164 };
165
166 #define RX_CMP_HASH_VALID(rxcmp)                                \
167         ((rxcmp)->rx_cmp_len_flags_type & cpu_to_le32(RX_CMP_FLAGS_RSS_VALID))
168
169 #define RSS_PROFILE_ID_MASK     0x1f
170
171 #define RX_CMP_HASH_TYPE(rxcmp)                                 \
172         (((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_RSS_HASH_TYPE) >>\
173           RX_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
174
175 struct rx_cmp_ext {
176         __le32 rx_cmp_flags2;
177         #define RX_CMP_FLAGS2_IP_CS_CALC                        0x1
178         #define RX_CMP_FLAGS2_L4_CS_CALC                        (0x1 << 1)
179         #define RX_CMP_FLAGS2_T_IP_CS_CALC                      (0x1 << 2)
180         #define RX_CMP_FLAGS2_T_L4_CS_CALC                      (0x1 << 3)
181         #define RX_CMP_FLAGS2_META_FORMAT_VLAN                  (0x1 << 4)
182         __le32 rx_cmp_meta_data;
183         #define RX_CMP_FLAGS2_METADATA_VID_MASK                 0xfff
184         #define RX_CMP_FLAGS2_METADATA_TPID_MASK                0xffff0000
185          #define RX_CMP_FLAGS2_METADATA_TPID_SFT                 16
186         __le32 rx_cmp_cfa_code_errors_v2;
187         #define RX_CMP_V                                        (1 << 0)
188         #define RX_CMPL_ERRORS_MASK                             (0x7fff << 1)
189          #define RX_CMPL_ERRORS_SFT                              1
190         #define RX_CMPL_ERRORS_BUFFER_ERROR_MASK                (0x7 << 1)
191          #define RX_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER           (0x0 << 1)
192          #define RX_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT         (0x1 << 1)
193          #define RX_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP         (0x2 << 1)
194          #define RX_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT          (0x3 << 1)
195         #define RX_CMPL_ERRORS_IP_CS_ERROR                      (0x1 << 4)
196         #define RX_CMPL_ERRORS_L4_CS_ERROR                      (0x1 << 5)
197         #define RX_CMPL_ERRORS_T_IP_CS_ERROR                    (0x1 << 6)
198         #define RX_CMPL_ERRORS_T_L4_CS_ERROR                    (0x1 << 7)
199         #define RX_CMPL_ERRORS_CRC_ERROR                        (0x1 << 8)
200         #define RX_CMPL_ERRORS_T_PKT_ERROR_MASK                 (0x7 << 9)
201          #define RX_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR             (0x0 << 9)
202          #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION     (0x1 << 9)
203          #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN     (0x2 << 9)
204          #define RX_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR   (0x3 << 9)
205          #define RX_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR     (0x4 << 9)
206          #define RX_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR    (0x5 << 9)
207          #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL         (0x6 << 9)
208         #define RX_CMPL_ERRORS_PKT_ERROR_MASK                   (0xf << 12)
209          #define RX_CMPL_ERRORS_PKT_ERROR_NO_ERROR               (0x0 << 12)
210          #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION         (0x1 << 12)
211          #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN         (0x2 << 12)
212          #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL             (0x3 << 12)
213          #define RX_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR         (0x4 << 12)
214          #define RX_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR        (0x5 << 12)
215          #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN         (0x6 << 12)
216          #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (0x7 << 12)
217          #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN         (0x8 << 12)
218
219         #define RX_CMPL_CFA_CODE_MASK                           (0xffff << 16)
220          #define RX_CMPL_CFA_CODE_SFT                            16
221
222         __le32 rx_cmp_unused3;
223 };
224
225 #define RX_CMP_L2_ERRORS                                                \
226         cpu_to_le32(RX_CMPL_ERRORS_BUFFER_ERROR_MASK | RX_CMPL_ERRORS_CRC_ERROR)
227
228 #define RX_CMP_L4_CS_BITS                                               \
229         (cpu_to_le32(RX_CMP_FLAGS2_L4_CS_CALC | RX_CMP_FLAGS2_T_L4_CS_CALC))
230
231 #define RX_CMP_L4_CS_ERR_BITS                                           \
232         (cpu_to_le32(RX_CMPL_ERRORS_L4_CS_ERROR | RX_CMPL_ERRORS_T_L4_CS_ERROR))
233
234 #define RX_CMP_L4_CS_OK(rxcmp1)                                         \
235             (((rxcmp1)->rx_cmp_flags2 & RX_CMP_L4_CS_BITS) &&           \
236              !((rxcmp1)->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS))
237
238 #define RX_CMP_ENCAP(rxcmp1)                                            \
239             ((le32_to_cpu((rxcmp1)->rx_cmp_flags2) &                    \
240              RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3)
241
242 struct rx_agg_cmp {
243         __le32 rx_agg_cmp_len_flags_type;
244         #define RX_AGG_CMP_TYPE                                 (0x3f << 0)
245         #define RX_AGG_CMP_LEN                                  (0xffff << 16)
246          #define RX_AGG_CMP_LEN_SHIFT                            16
247         u32 rx_agg_cmp_opaque;
248         __le32 rx_agg_cmp_v;
249         #define RX_AGG_CMP_V                                    (1 << 0)
250         __le32 rx_agg_cmp_unused;
251 };
252
253 struct rx_tpa_start_cmp {
254         __le32 rx_tpa_start_cmp_len_flags_type;
255         #define RX_TPA_START_CMP_TYPE                           (0x3f << 0)
256         #define RX_TPA_START_CMP_FLAGS                          (0x3ff << 6)
257          #define RX_TPA_START_CMP_FLAGS_SHIFT                    6
258         #define RX_TPA_START_CMP_FLAGS_PLACEMENT                (0x7 << 7)
259          #define RX_TPA_START_CMP_FLAGS_PLACEMENT_SHIFT          7
260          #define RX_TPA_START_CMP_FLAGS_PLACEMENT_JUMBO          (0x1 << 7)
261          #define RX_TPA_START_CMP_FLAGS_PLACEMENT_HDS            (0x2 << 7)
262          #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_JUMBO      (0x5 << 7)
263          #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_HDS        (0x6 << 7)
264         #define RX_TPA_START_CMP_FLAGS_RSS_VALID                (0x1 << 10)
265         #define RX_TPA_START_CMP_FLAGS_ITYPES                   (0xf << 12)
266          #define RX_TPA_START_CMP_FLAGS_ITYPES_SHIFT             12
267          #define RX_TPA_START_CMP_FLAGS_ITYPE_TCP                (0x2 << 12)
268         #define RX_TPA_START_CMP_LEN                            (0xffff << 16)
269          #define RX_TPA_START_CMP_LEN_SHIFT                      16
270
271         u32 rx_tpa_start_cmp_opaque;
272         __le32 rx_tpa_start_cmp_misc_v1;
273         #define RX_TPA_START_CMP_V1                             (0x1 << 0)
274         #define RX_TPA_START_CMP_RSS_HASH_TYPE                  (0x7f << 9)
275          #define RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT            9
276         #define RX_TPA_START_CMP_AGG_ID                         (0x7f << 25)
277          #define RX_TPA_START_CMP_AGG_ID_SHIFT                   25
278
279         __le32 rx_tpa_start_cmp_rss_hash;
280 };
281
282 #define TPA_START_HASH_VALID(rx_tpa_start)                              \
283         ((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type &              \
284          cpu_to_le32(RX_TPA_START_CMP_FLAGS_RSS_VALID))
285
286 #define TPA_START_HASH_TYPE(rx_tpa_start)                               \
287         (((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) &      \
288            RX_TPA_START_CMP_RSS_HASH_TYPE) >>                           \
289           RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
290
291 #define TPA_START_AGG_ID(rx_tpa_start)                                  \
292         ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) &       \
293          RX_TPA_START_CMP_AGG_ID) >> RX_TPA_START_CMP_AGG_ID_SHIFT)
294
295 struct rx_tpa_start_cmp_ext {
296         __le32 rx_tpa_start_cmp_flags2;
297         #define RX_TPA_START_CMP_FLAGS2_IP_CS_CALC              (0x1 << 0)
298         #define RX_TPA_START_CMP_FLAGS2_L4_CS_CALC              (0x1 << 1)
299         #define RX_TPA_START_CMP_FLAGS2_T_IP_CS_CALC            (0x1 << 2)
300         #define RX_TPA_START_CMP_FLAGS2_T_L4_CS_CALC            (0x1 << 3)
301
302         __le32 rx_tpa_start_cmp_metadata;
303         __le32 rx_tpa_start_cmp_cfa_code_v2;
304         #define RX_TPA_START_CMP_V2                             (0x1 << 0)
305         #define RX_TPA_START_CMP_CFA_CODE                       (0xffff << 16)
306          #define RX_TPA_START_CMPL_CFA_CODE_SHIFT                16
307         __le32 rx_tpa_start_cmp_unused5;
308 };
309
310 struct rx_tpa_end_cmp {
311         __le32 rx_tpa_end_cmp_len_flags_type;
312         #define RX_TPA_END_CMP_TYPE                             (0x3f << 0)
313         #define RX_TPA_END_CMP_FLAGS                            (0x3ff << 6)
314          #define RX_TPA_END_CMP_FLAGS_SHIFT                      6
315         #define RX_TPA_END_CMP_FLAGS_PLACEMENT                  (0x7 << 7)
316          #define RX_TPA_END_CMP_FLAGS_PLACEMENT_SHIFT            7
317          #define RX_TPA_END_CMP_FLAGS_PLACEMENT_JUMBO            (0x1 << 7)
318          #define RX_TPA_END_CMP_FLAGS_PLACEMENT_HDS              (0x2 << 7)
319          #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO        (0x5 << 7)
320          #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS          (0x6 << 7)
321         #define RX_TPA_END_CMP_FLAGS_RSS_VALID                  (0x1 << 10)
322         #define RX_TPA_END_CMP_FLAGS_ITYPES                     (0xf << 12)
323          #define RX_TPA_END_CMP_FLAGS_ITYPES_SHIFT               12
324          #define RX_TPA_END_CMP_FLAGS_ITYPE_TCP                  (0x2 << 12)
325         #define RX_TPA_END_CMP_LEN                              (0xffff << 16)
326          #define RX_TPA_END_CMP_LEN_SHIFT                        16
327
328         u32 rx_tpa_end_cmp_opaque;
329         __le32 rx_tpa_end_cmp_misc_v1;
330         #define RX_TPA_END_CMP_V1                               (0x1 << 0)
331         #define RX_TPA_END_CMP_AGG_BUFS                         (0x3f << 1)
332          #define RX_TPA_END_CMP_AGG_BUFS_SHIFT                   1
333         #define RX_TPA_END_CMP_TPA_SEGS                         (0xff << 8)
334          #define RX_TPA_END_CMP_TPA_SEGS_SHIFT                   8
335         #define RX_TPA_END_CMP_PAYLOAD_OFFSET                   (0xff << 16)
336          #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT             16
337         #define RX_TPA_END_CMP_AGG_ID                           (0x7f << 25)
338          #define RX_TPA_END_CMP_AGG_ID_SHIFT                     25
339
340         __le32 rx_tpa_end_cmp_tsdelta;
341         #define RX_TPA_END_GRO_TS                               (0x1 << 31)
342 };
343
344 #define TPA_END_AGG_ID(rx_tpa_end)                                      \
345         ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &           \
346          RX_TPA_END_CMP_AGG_ID) >> RX_TPA_END_CMP_AGG_ID_SHIFT)
347
348 #define TPA_END_TPA_SEGS(rx_tpa_end)                                    \
349         ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) &           \
350          RX_TPA_END_CMP_TPA_SEGS) >> RX_TPA_END_CMP_TPA_SEGS_SHIFT)
351
352 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO                          \
353         cpu_to_le32(RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO &          \
354                     RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS)
355
356 #define TPA_END_GRO(rx_tpa_end)                                         \
357         ((rx_tpa_end)->rx_tpa_end_cmp_len_flags_type &                  \
358          RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO)
359
360 #define TPA_END_GRO_TS(rx_tpa_end)                                      \
361         ((rx_tpa_end)->rx_tpa_end_cmp_tsdelta & cpu_to_le32(RX_TPA_END_GRO_TS))
362
363 struct rx_tpa_end_cmp_ext {
364         __le32 rx_tpa_end_cmp_dup_acks;
365         #define RX_TPA_END_CMP_TPA_DUP_ACKS                     (0xf << 0)
366
367         __le32 rx_tpa_end_cmp_seg_len;
368         #define RX_TPA_END_CMP_TPA_SEG_LEN                      (0xffff << 0)
369
370         __le32 rx_tpa_end_cmp_errors_v2;
371         #define RX_TPA_END_CMP_V2                               (0x1 << 0)
372         #define RX_TPA_END_CMP_ERRORS                           (0x7fff << 1)
373         #define RX_TPA_END_CMPL_ERRORS_SHIFT                     1
374
375         u32 rx_tpa_end_cmp_start_opaque;
376 };
377
378 #define DB_IDX_MASK                                             0xffffff
379 #define DB_IDX_VALID                                            (0x1 << 26)
380 #define DB_IRQ_DIS                                              (0x1 << 27)
381 #define DB_KEY_TX                                               (0x0 << 28)
382 #define DB_KEY_RX                                               (0x1 << 28)
383 #define DB_KEY_CP                                               (0x2 << 28)
384 #define DB_KEY_ST                                               (0x3 << 28)
385 #define DB_KEY_TX_PUSH                                          (0x4 << 28)
386 #define DB_LONG_TX_PUSH                                         (0x2 << 24)
387
388 #define INVALID_HW_RING_ID      ((u16)-1)
389
390 #define BNXT_RSS_HASH_TYPE_FLAG_IPV4            0x01
391 #define BNXT_RSS_HASH_TYPE_FLAG_TCP_IPV4        0x02
392 #define BNXT_RSS_HASH_TYPE_FLAG_IPV6            0x04
393 #define BNXT_RSS_HASH_TYPE_FLAG_TCP_IPV6        0x08
394
395 /* The hardware supports certain page sizes.  Use the supported page sizes
396  * to allocate the rings.
397  */
398 #if (PAGE_SHIFT < 12)
399 #define BNXT_PAGE_SHIFT 12
400 #elif (PAGE_SHIFT <= 13)
401 #define BNXT_PAGE_SHIFT PAGE_SHIFT
402 #elif (PAGE_SHIFT < 16)
403 #define BNXT_PAGE_SHIFT 13
404 #else
405 #define BNXT_PAGE_SHIFT 16
406 #endif
407
408 #define BNXT_PAGE_SIZE  (1 << BNXT_PAGE_SHIFT)
409
410 /* The RXBD length is 16-bit so we can only support page sizes < 64K */
411 #if (PAGE_SHIFT > 15)
412 #define BNXT_RX_PAGE_SHIFT 15
413 #else
414 #define BNXT_RX_PAGE_SHIFT PAGE_SHIFT
415 #endif
416
417 #define BNXT_RX_PAGE_SIZE (1 << BNXT_RX_PAGE_SHIFT)
418
419 #define BNXT_MIN_PKT_SIZE       45
420
421 #define BNXT_NUM_TESTS(bp)      0
422
423 #define BNXT_DEFAULT_RX_RING_SIZE       511
424 #define BNXT_DEFAULT_TX_RING_SIZE       511
425
426 #define MAX_TPA         64
427
428 #define MAX_RX_PAGES    8
429 #define MAX_RX_AGG_PAGES        32
430 #define MAX_TX_PAGES    8
431 #define MAX_CP_PAGES    64
432
433 #define RX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct rx_bd))
434 #define TX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_bd))
435 #define CP_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_cmp))
436
437 #define SW_RXBD_RING_SIZE (sizeof(struct bnxt_sw_rx_bd) * RX_DESC_CNT)
438 #define HW_RXBD_RING_SIZE (sizeof(struct rx_bd) * RX_DESC_CNT)
439
440 #define SW_RXBD_AGG_RING_SIZE (sizeof(struct bnxt_sw_rx_agg_bd) * RX_DESC_CNT)
441
442 #define SW_TXBD_RING_SIZE (sizeof(struct bnxt_sw_tx_bd) * TX_DESC_CNT)
443 #define HW_TXBD_RING_SIZE (sizeof(struct tx_bd) * TX_DESC_CNT)
444
445 #define HW_CMPD_RING_SIZE (sizeof(struct tx_cmp) * CP_DESC_CNT)
446
447 #define BNXT_MAX_RX_DESC_CNT            (RX_DESC_CNT * MAX_RX_PAGES - 1)
448 #define BNXT_MAX_RX_JUM_DESC_CNT        (RX_DESC_CNT * MAX_RX_AGG_PAGES - 1)
449 #define BNXT_MAX_TX_DESC_CNT            (TX_DESC_CNT * MAX_TX_PAGES - 1)
450
451 #define RX_RING(x)      (((x) & ~(RX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
452 #define RX_IDX(x)       ((x) & (RX_DESC_CNT - 1))
453
454 #define TX_RING(x)      (((x) & ~(TX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
455 #define TX_IDX(x)       ((x) & (TX_DESC_CNT - 1))
456
457 #define CP_RING(x)      (((x) & ~(CP_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
458 #define CP_IDX(x)       ((x) & (CP_DESC_CNT - 1))
459
460 #define TX_CMP_VALID(txcmp, raw_cons)                                   \
461         (!!((txcmp)->tx_cmp_errors_v & cpu_to_le32(TX_CMP_V)) ==        \
462          !((raw_cons) & bp->cp_bit))
463
464 #define RX_CMP_VALID(rxcmp1, raw_cons)                                  \
465         (!!((rxcmp1)->rx_cmp_cfa_code_errors_v2 & cpu_to_le32(RX_CMP_V)) ==\
466          !((raw_cons) & bp->cp_bit))
467
468 #define RX_AGG_CMP_VALID(agg, raw_cons)                         \
469         (!!((agg)->rx_agg_cmp_v & cpu_to_le32(RX_AGG_CMP_V)) == \
470          !((raw_cons) & bp->cp_bit))
471
472 #define TX_CMP_TYPE(txcmp)                                      \
473         (le32_to_cpu((txcmp)->tx_cmp_flags_type) & CMP_TYPE)
474
475 #define RX_CMP_TYPE(rxcmp)                                      \
476         (le32_to_cpu((rxcmp)->rx_cmp_len_flags_type) & RX_CMP_CMP_TYPE)
477
478 #define NEXT_RX(idx)            (((idx) + 1) & bp->rx_ring_mask)
479
480 #define NEXT_RX_AGG(idx)        (((idx) + 1) & bp->rx_agg_ring_mask)
481
482 #define NEXT_TX(idx)            (((idx) + 1) & bp->tx_ring_mask)
483
484 #define ADV_RAW_CMP(idx, n)     ((idx) + (n))
485 #define NEXT_RAW_CMP(idx)       ADV_RAW_CMP(idx, 1)
486 #define RING_CMP(idx)           ((idx) & bp->cp_ring_mask)
487 #define NEXT_CMP(idx)           RING_CMP(ADV_RAW_CMP(idx, 1))
488
489 #define BNXT_HWRM_MAX_REQ_LEN           (bp->hwrm_max_req_len)
490 #define DFLT_HWRM_CMD_TIMEOUT           500
491 #define HWRM_CMD_TIMEOUT                (bp->hwrm_cmd_timeout)
492 #define HWRM_RESET_TIMEOUT              ((HWRM_CMD_TIMEOUT) * 4)
493 #define HWRM_RESP_ERR_CODE_MASK         0xffff
494 #define HWRM_RESP_LEN_OFFSET            4
495 #define HWRM_RESP_LEN_MASK              0xffff0000
496 #define HWRM_RESP_LEN_SFT               16
497 #define HWRM_RESP_VALID_MASK            0xff000000
498 #define HWRM_SEQ_ID_INVALID             -1
499 #define BNXT_HWRM_REQ_MAX_SIZE          128
500 #define BNXT_HWRM_REQS_PER_PAGE         (BNXT_PAGE_SIZE /       \
501                                          BNXT_HWRM_REQ_MAX_SIZE)
502
503 struct bnxt_sw_tx_bd {
504         struct sk_buff          *skb;
505         DEFINE_DMA_UNMAP_ADDR(mapping);
506         u8                      is_gso;
507         u8                      is_push;
508         unsigned short          nr_frags;
509 };
510
511 struct bnxt_sw_rx_bd {
512         u8                      *data;
513         DEFINE_DMA_UNMAP_ADDR(mapping);
514 };
515
516 struct bnxt_sw_rx_agg_bd {
517         struct page             *page;
518         unsigned int            offset;
519         dma_addr_t              mapping;
520 };
521
522 struct bnxt_ring_struct {
523         int                     nr_pages;
524         int                     page_size;
525         void                    **pg_arr;
526         dma_addr_t              *dma_arr;
527
528         __le64                  *pg_tbl;
529         dma_addr_t              pg_tbl_map;
530
531         int                     vmem_size;
532         void                    **vmem;
533
534         u16                     fw_ring_id; /* Ring id filled by Chimp FW */
535         u8                      queue_id;
536 };
537
538 struct tx_push_bd {
539         __le32                  doorbell;
540         __le32                  tx_bd_len_flags_type;
541         u32                     tx_bd_opaque;
542         struct tx_bd_ext        txbd2;
543 };
544
545 struct tx_push_buffer {
546         struct tx_push_bd       push_bd;
547         u32                     data[25];
548 };
549
550 struct bnxt_tx_ring_info {
551         struct bnxt_napi        *bnapi;
552         u16                     tx_prod;
553         u16                     tx_cons;
554         void __iomem            *tx_doorbell;
555
556         struct tx_bd            *tx_desc_ring[MAX_TX_PAGES];
557         struct bnxt_sw_tx_bd    *tx_buf_ring;
558
559         dma_addr_t              tx_desc_mapping[MAX_TX_PAGES];
560
561         struct tx_push_buffer   *tx_push;
562         dma_addr_t              tx_push_mapping;
563         __le64                  data_mapping;
564
565 #define BNXT_DEV_STATE_CLOSING  0x1
566         u32                     dev_state;
567
568         struct bnxt_ring_struct tx_ring_struct;
569 };
570
571 struct bnxt_tpa_info {
572         u8                      *data;
573         dma_addr_t              mapping;
574         u16                     len;
575         unsigned short          gso_type;
576         u32                     flags2;
577         u32                     metadata;
578         enum pkt_hash_types     hash_type;
579         u32                     rss_hash;
580 };
581
582 struct bnxt_rx_ring_info {
583         struct bnxt_napi        *bnapi;
584         u16                     rx_prod;
585         u16                     rx_agg_prod;
586         u16                     rx_sw_agg_prod;
587         u16                     rx_next_cons;
588         void __iomem            *rx_doorbell;
589         void __iomem            *rx_agg_doorbell;
590
591         struct rx_bd            *rx_desc_ring[MAX_RX_PAGES];
592         struct bnxt_sw_rx_bd    *rx_buf_ring;
593
594         struct rx_bd            *rx_agg_desc_ring[MAX_RX_AGG_PAGES];
595         struct bnxt_sw_rx_agg_bd        *rx_agg_ring;
596
597         unsigned long           *rx_agg_bmap;
598         u16                     rx_agg_bmap_size;
599
600         struct page             *rx_page;
601         unsigned int            rx_page_offset;
602
603         dma_addr_t              rx_desc_mapping[MAX_RX_PAGES];
604         dma_addr_t              rx_agg_desc_mapping[MAX_RX_AGG_PAGES];
605
606         struct bnxt_tpa_info    *rx_tpa;
607
608         struct bnxt_ring_struct rx_ring_struct;
609         struct bnxt_ring_struct rx_agg_ring_struct;
610 };
611
612 struct bnxt_cp_ring_info {
613         u32                     cp_raw_cons;
614         void __iomem            *cp_doorbell;
615
616         struct tx_cmp           *cp_desc_ring[MAX_CP_PAGES];
617
618         dma_addr_t              cp_desc_mapping[MAX_CP_PAGES];
619
620         struct ctx_hw_stats     *hw_stats;
621         dma_addr_t              hw_stats_map;
622         u32                     hw_stats_ctx_id;
623         u64                     rx_l4_csum_errors;
624
625         struct bnxt_ring_struct cp_ring_struct;
626 };
627
628 struct bnxt_napi {
629         struct napi_struct      napi;
630         struct bnxt             *bp;
631
632         int                     index;
633         struct bnxt_cp_ring_info        cp_ring;
634         struct bnxt_rx_ring_info        *rx_ring;
635         struct bnxt_tx_ring_info        *tx_ring;
636
637 #ifdef CONFIG_NET_RX_BUSY_POLL
638         atomic_t                poll_state;
639 #endif
640         bool                    in_reset;
641 };
642
643 #ifdef CONFIG_NET_RX_BUSY_POLL
644 enum bnxt_poll_state_t {
645         BNXT_STATE_IDLE = 0,
646         BNXT_STATE_NAPI,
647         BNXT_STATE_POLL,
648         BNXT_STATE_DISABLE,
649 };
650 #endif
651
652 struct bnxt_irq {
653         irq_handler_t   handler;
654         unsigned int    vector;
655         u8              requested;
656         char            name[IFNAMSIZ + 2];
657 };
658
659 #define HWRM_RING_ALLOC_TX      0x1
660 #define HWRM_RING_ALLOC_RX      0x2
661 #define HWRM_RING_ALLOC_AGG     0x4
662 #define HWRM_RING_ALLOC_CMPL    0x8
663
664 #define INVALID_STATS_CTX_ID    -1
665
666 struct bnxt_ring_grp_info {
667         u16     fw_stats_ctx;
668         u16     fw_grp_id;
669         u16     rx_fw_ring_id;
670         u16     agg_fw_ring_id;
671         u16     cp_fw_ring_id;
672 };
673
674 struct bnxt_vnic_info {
675         u16             fw_vnic_id; /* returned by Chimp during alloc */
676         u16             fw_rss_cos_lb_ctx;
677         u16             fw_l2_ctx_id;
678 #define BNXT_MAX_UC_ADDRS       4
679         __le64          fw_l2_filter_id[BNXT_MAX_UC_ADDRS];
680                                 /* index 0 always dev_addr */
681         u16             uc_filter_count;
682         u8              *uc_list;
683
684         u16             *fw_grp_ids;
685         u16             hash_type;
686         dma_addr_t      rss_table_dma_addr;
687         __le16          *rss_table;
688         dma_addr_t      rss_hash_key_dma_addr;
689         u64             *rss_hash_key;
690         u32             rx_mask;
691
692         u8              *mc_list;
693         int             mc_list_size;
694         int             mc_list_count;
695         dma_addr_t      mc_list_mapping;
696 #define BNXT_MAX_MC_ADDRS       16
697
698         u32             flags;
699 #define BNXT_VNIC_RSS_FLAG      1
700 #define BNXT_VNIC_RFS_FLAG      2
701 #define BNXT_VNIC_MCAST_FLAG    4
702 #define BNXT_VNIC_UCAST_FLAG    8
703 };
704
705 #if defined(CONFIG_BNXT_SRIOV)
706 struct bnxt_vf_info {
707         u16     fw_fid;
708         u8      mac_addr[ETH_ALEN];
709         u16     max_rsscos_ctxs;
710         u16     max_cp_rings;
711         u16     max_tx_rings;
712         u16     max_rx_rings;
713         u16     max_hw_ring_grps;
714         u16     max_l2_ctxs;
715         u16     max_irqs;
716         u16     max_vnics;
717         u16     max_stat_ctxs;
718         u16     vlan;
719         u32     flags;
720 #define BNXT_VF_QOS             0x1
721 #define BNXT_VF_SPOOFCHK        0x2
722 #define BNXT_VF_LINK_FORCED     0x4
723 #define BNXT_VF_LINK_UP         0x8
724         u32     func_flags; /* func cfg flags */
725         u32     min_tx_rate;
726         u32     max_tx_rate;
727         void    *hwrm_cmd_req_addr;
728         dma_addr_t      hwrm_cmd_req_dma_addr;
729 };
730 #endif
731
732 struct bnxt_pf_info {
733 #define BNXT_FIRST_PF_FID       1
734 #define BNXT_FIRST_VF_FID       128
735         u32     fw_fid;
736         u8      port_id;
737         u8      mac_addr[ETH_ALEN];
738         u16     max_rsscos_ctxs;
739         u16     max_cp_rings;
740         u16     max_tx_rings; /* HW assigned max tx rings for this PF */
741         u16     max_rx_rings; /* HW assigned max rx rings for this PF */
742         u16     max_hw_ring_grps;
743         u16     max_irqs;
744         u16     max_l2_ctxs;
745         u16     max_vnics;
746         u16     max_stat_ctxs;
747         u32     first_vf_id;
748         u16     active_vfs;
749         u16     max_vfs;
750         u32     max_encap_records;
751         u32     max_decap_records;
752         u32     max_tx_em_flows;
753         u32     max_tx_wm_flows;
754         u32     max_rx_em_flows;
755         u32     max_rx_wm_flows;
756         unsigned long   *vf_event_bmap;
757         u16     hwrm_cmd_req_pages;
758         void                    *hwrm_cmd_req_addr[4];
759         dma_addr_t              hwrm_cmd_req_dma_addr[4];
760         struct bnxt_vf_info     *vf;
761 };
762
763 struct bnxt_ntuple_filter {
764         struct hlist_node       hash;
765         u8                      src_mac_addr[ETH_ALEN];
766         struct flow_keys        fkeys;
767         __le64                  filter_id;
768         u16                     sw_id;
769         u16                     rxq;
770         u32                     flow_id;
771         unsigned long           state;
772 #define BNXT_FLTR_VALID         0
773 #define BNXT_FLTR_UPDATE        1
774 };
775
776 struct bnxt_link_info {
777         u8                      phy_type;
778         u8                      media_type;
779         u8                      transceiver;
780         u8                      phy_addr;
781         u8                      phy_link_status;
782 #define BNXT_LINK_NO_LINK       PORT_PHY_QCFG_RESP_LINK_NO_LINK
783 #define BNXT_LINK_SIGNAL        PORT_PHY_QCFG_RESP_LINK_SIGNAL
784 #define BNXT_LINK_LINK          PORT_PHY_QCFG_RESP_LINK_LINK
785         u8                      wire_speed;
786         u8                      loop_back;
787         u8                      link_up;
788         u8                      duplex;
789 #define BNXT_LINK_DUPLEX_HALF   PORT_PHY_QCFG_RESP_DUPLEX_HALF
790 #define BNXT_LINK_DUPLEX_FULL   PORT_PHY_QCFG_RESP_DUPLEX_FULL
791         u8                      pause;
792 #define BNXT_LINK_PAUSE_TX      PORT_PHY_QCFG_RESP_PAUSE_TX
793 #define BNXT_LINK_PAUSE_RX      PORT_PHY_QCFG_RESP_PAUSE_RX
794 #define BNXT_LINK_PAUSE_BOTH    (PORT_PHY_QCFG_RESP_PAUSE_RX | \
795                                  PORT_PHY_QCFG_RESP_PAUSE_TX)
796         u8                      lp_pause;
797         u8                      auto_pause_setting;
798         u8                      force_pause_setting;
799         u8                      duplex_setting;
800         u8                      auto_mode;
801 #define BNXT_AUTO_MODE(mode)    ((mode) > BNXT_LINK_AUTO_NONE && \
802                                  (mode) <= BNXT_LINK_AUTO_MSK)
803 #define BNXT_LINK_AUTO_NONE     PORT_PHY_QCFG_RESP_AUTO_MODE_NONE
804 #define BNXT_LINK_AUTO_ALLSPDS  PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS
805 #define BNXT_LINK_AUTO_ONESPD   PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED
806 #define BNXT_LINK_AUTO_ONEORBELOW PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW
807 #define BNXT_LINK_AUTO_MSK      PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK
808 #define PHY_VER_LEN             3
809         u8                      phy_ver[PHY_VER_LEN];
810         u16                     link_speed;
811 #define BNXT_LINK_SPEED_100MB   PORT_PHY_QCFG_RESP_LINK_SPEED_100MB
812 #define BNXT_LINK_SPEED_1GB     PORT_PHY_QCFG_RESP_LINK_SPEED_1GB
813 #define BNXT_LINK_SPEED_2GB     PORT_PHY_QCFG_RESP_LINK_SPEED_2GB
814 #define BNXT_LINK_SPEED_2_5GB   PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB
815 #define BNXT_LINK_SPEED_10GB    PORT_PHY_QCFG_RESP_LINK_SPEED_10GB
816 #define BNXT_LINK_SPEED_20GB    PORT_PHY_QCFG_RESP_LINK_SPEED_20GB
817 #define BNXT_LINK_SPEED_25GB    PORT_PHY_QCFG_RESP_LINK_SPEED_25GB
818 #define BNXT_LINK_SPEED_40GB    PORT_PHY_QCFG_RESP_LINK_SPEED_40GB
819 #define BNXT_LINK_SPEED_50GB    PORT_PHY_QCFG_RESP_LINK_SPEED_50GB
820         u16                     support_speeds;
821         u16                     auto_link_speeds;
822 #define BNXT_LINK_SPEED_MSK_100MB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB
823 #define BNXT_LINK_SPEED_MSK_1GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB
824 #define BNXT_LINK_SPEED_MSK_2GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB
825 #define BNXT_LINK_SPEED_MSK_10GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB
826 #define BNXT_LINK_SPEED_MSK_2_5GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB
827 #define BNXT_LINK_SPEED_MSK_20GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB
828 #define BNXT_LINK_SPEED_MSK_25GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB
829 #define BNXT_LINK_SPEED_MSK_40GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB
830 #define BNXT_LINK_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB
831         u16                     lp_auto_link_speeds;
832         u16                     force_link_speed;
833         u32                     preemphasis;
834
835         /* copy of requested setting from ethtool cmd */
836         u8                      autoneg;
837 #define BNXT_AUTONEG_SPEED              1
838 #define BNXT_AUTONEG_FLOW_CTRL          2
839         u8                      req_duplex;
840         u8                      req_flow_ctrl;
841         u16                     req_link_speed;
842         u32                     advertising;
843         bool                    force_link_chng;
844
845         u8                      last_port_module_event;
846         /* a copy of phy_qcfg output used to report link
847          * info to VF
848          */
849         struct hwrm_port_phy_qcfg_output phy_qcfg_resp;
850 };
851
852 #define BNXT_MAX_QUEUE  8
853
854 struct bnxt_queue_info {
855         u8      queue_id;
856         u8      queue_profile;
857 };
858
859 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT  0x400
860 #define BNXT_CAG_REG_LEGACY_INT_STATUS  0x4014
861 #define BNXT_CAG_REG_BASE               0x300000
862
863 struct bnxt {
864         void __iomem            *bar0;
865         void __iomem            *bar1;
866         void __iomem            *bar2;
867
868         u32                     reg_base;
869
870         struct net_device       *dev;
871         struct pci_dev          *pdev;
872
873         atomic_t                intr_sem;
874
875         u32                     flags;
876         #define BNXT_FLAG_DCB_ENABLED   0x1
877         #define BNXT_FLAG_VF            0x2
878         #define BNXT_FLAG_LRO           0x4
879 #ifdef CONFIG_INET
880         #define BNXT_FLAG_GRO           0x8
881 #else
882         /* Cannot support hardware GRO if CONFIG_INET is not set */
883         #define BNXT_FLAG_GRO           0x0
884 #endif
885         #define BNXT_FLAG_TPA           (BNXT_FLAG_LRO | BNXT_FLAG_GRO)
886         #define BNXT_FLAG_JUMBO         0x10
887         #define BNXT_FLAG_STRIP_VLAN    0x20
888         #define BNXT_FLAG_AGG_RINGS     (BNXT_FLAG_JUMBO | BNXT_FLAG_GRO | \
889                                          BNXT_FLAG_LRO)
890         #define BNXT_FLAG_USING_MSIX    0x40
891         #define BNXT_FLAG_MSIX_CAP      0x80
892         #define BNXT_FLAG_RFS           0x100
893         #define BNXT_FLAG_SHARED_RINGS  0x200
894         #define BNXT_FLAG_PORT_STATS    0x400
895         #define BNXT_FLAG_EEE_CAP       0x1000
896
897         #define BNXT_FLAG_ALL_CONFIG_FEATS (BNXT_FLAG_TPA |             \
898                                             BNXT_FLAG_RFS |             \
899                                             BNXT_FLAG_STRIP_VLAN)
900
901 #define BNXT_PF(bp)             (!((bp)->flags & BNXT_FLAG_VF))
902 #define BNXT_VF(bp)             ((bp)->flags & BNXT_FLAG_VF)
903
904         struct bnxt_napi        **bnapi;
905
906         struct bnxt_rx_ring_info        *rx_ring;
907         struct bnxt_tx_ring_info        *tx_ring;
908
909         u32                     rx_buf_size;
910         u32                     rx_buf_use_size;        /* useable size */
911         u32                     rx_ring_size;
912         u32                     rx_agg_ring_size;
913         u32                     rx_copy_thresh;
914         u32                     rx_ring_mask;
915         u32                     rx_agg_ring_mask;
916         int                     rx_nr_pages;
917         int                     rx_agg_nr_pages;
918         int                     rx_nr_rings;
919         int                     rsscos_nr_ctxs;
920
921         u32                     tx_ring_size;
922         u32                     tx_ring_mask;
923         int                     tx_nr_pages;
924         int                     tx_nr_rings;
925         int                     tx_nr_rings_per_tc;
926
927         int                     tx_wake_thresh;
928         int                     tx_push_thresh;
929         int                     tx_push_size;
930
931         u32                     cp_ring_size;
932         u32                     cp_ring_mask;
933         u32                     cp_bit;
934         int                     cp_nr_pages;
935         int                     cp_nr_rings;
936
937         int                     num_stat_ctxs;
938
939         /* grp_info indexed by completion ring index */
940         struct bnxt_ring_grp_info       *grp_info;
941         struct bnxt_vnic_info   *vnic_info;
942         int                     nr_vnics;
943
944         u8                      max_tc;
945         struct bnxt_queue_info  q_info[BNXT_MAX_QUEUE];
946
947         unsigned int            current_interval;
948 #define BNXT_TIMER_INTERVAL     HZ
949
950         struct timer_list       timer;
951
952         unsigned long           state;
953 #define BNXT_STATE_OPEN         0
954 #define BNXT_STATE_IN_SP_TASK   1
955
956         struct bnxt_irq *irq_tbl;
957         u8                      mac_addr[ETH_ALEN];
958
959         u32                     msg_enable;
960
961         u32                     hwrm_spec_code;
962         u16                     hwrm_cmd_seq;
963         u32                     hwrm_intr_seq_id;
964         void                    *hwrm_cmd_resp_addr;
965         dma_addr_t              hwrm_cmd_resp_dma_addr;
966         void                    *hwrm_dbg_resp_addr;
967         dma_addr_t              hwrm_dbg_resp_dma_addr;
968 #define HWRM_DBG_REG_BUF_SIZE   128
969
970         struct rx_port_stats    *hw_rx_port_stats;
971         struct tx_port_stats    *hw_tx_port_stats;
972         dma_addr_t              hw_rx_port_stats_map;
973         dma_addr_t              hw_tx_port_stats_map;
974         int                     hw_port_stats_size;
975
976         u16                     hwrm_max_req_len;
977         int                     hwrm_cmd_timeout;
978         struct mutex            hwrm_cmd_lock;  /* serialize hwrm messages */
979         struct hwrm_ver_get_output      ver_resp;
980 #define FW_VER_STR_LEN          32
981 #define BC_HWRM_STR_LEN         21
982 #define PHY_VER_STR_LEN         (FW_VER_STR_LEN - BC_HWRM_STR_LEN)
983         char                    fw_ver_str[FW_VER_STR_LEN];
984         __be16                  vxlan_port;
985         u8                      vxlan_port_cnt;
986         __le16                  vxlan_fw_dst_port_id;
987         u8                      nge_port_cnt;
988         __le16                  nge_fw_dst_port_id;
989
990         u16                     rx_coal_ticks;
991         u16                     rx_coal_ticks_irq;
992         u16                     rx_coal_bufs;
993         u16                     rx_coal_bufs_irq;
994         u16                     tx_coal_ticks;
995         u16                     tx_coal_ticks_irq;
996         u16                     tx_coal_bufs;
997         u16                     tx_coal_bufs_irq;
998
999 #define BNXT_USEC_TO_COAL_TIMER(x)      ((x) * 25 / 2)
1000
1001         struct work_struct      sp_task;
1002         unsigned long           sp_event;
1003 #define BNXT_RX_MASK_SP_EVENT           0
1004 #define BNXT_RX_NTP_FLTR_SP_EVENT       1
1005 #define BNXT_LINK_CHNG_SP_EVENT         2
1006 #define BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT 3
1007 #define BNXT_VXLAN_ADD_PORT_SP_EVENT    4
1008 #define BNXT_VXLAN_DEL_PORT_SP_EVENT    5
1009 #define BNXT_RESET_TASK_SP_EVENT        6
1010 #define BNXT_RST_RING_SP_EVENT          7
1011 #define BNXT_HWRM_PF_UNLOAD_SP_EVENT    8
1012 #define BNXT_PERIODIC_STATS_SP_EVENT    9
1013 #define BNXT_HWRM_PORT_MODULE_SP_EVENT  10
1014
1015         struct bnxt_pf_info     pf;
1016 #ifdef CONFIG_BNXT_SRIOV
1017         int                     nr_vfs;
1018         struct bnxt_vf_info     vf;
1019         wait_queue_head_t       sriov_cfg_wait;
1020         bool                    sriov_cfg;
1021 #define BNXT_SRIOV_CFG_WAIT_TMO msecs_to_jiffies(10000)
1022 #endif
1023
1024 #define BNXT_NTP_FLTR_MAX_FLTR  4096
1025 #define BNXT_NTP_FLTR_HASH_SIZE 512
1026 #define BNXT_NTP_FLTR_HASH_MASK (BNXT_NTP_FLTR_HASH_SIZE - 1)
1027         struct hlist_head       ntp_fltr_hash_tbl[BNXT_NTP_FLTR_HASH_SIZE];
1028         spinlock_t              ntp_fltr_lock;  /* for hash table add, del */
1029
1030         unsigned long           *ntp_fltr_bmap;
1031         int                     ntp_fltr_count;
1032
1033         struct bnxt_link_info   link_info;
1034         struct ethtool_eee      eee;
1035         u32                     lpi_tmr_lo;
1036         u32                     lpi_tmr_hi;
1037 };
1038
1039 #ifdef CONFIG_NET_RX_BUSY_POLL
1040 static inline void bnxt_enable_poll(struct bnxt_napi *bnapi)
1041 {
1042         atomic_set(&bnapi->poll_state, BNXT_STATE_IDLE);
1043 }
1044
1045 /* called from the NAPI poll routine to get ownership of a bnapi */
1046 static inline bool bnxt_lock_napi(struct bnxt_napi *bnapi)
1047 {
1048         int rc = atomic_cmpxchg(&bnapi->poll_state, BNXT_STATE_IDLE,
1049                                 BNXT_STATE_NAPI);
1050
1051         return rc == BNXT_STATE_IDLE;
1052 }
1053
1054 static inline void bnxt_unlock_napi(struct bnxt_napi *bnapi)
1055 {
1056         atomic_set(&bnapi->poll_state, BNXT_STATE_IDLE);
1057 }
1058
1059 /* called from the busy poll routine to get ownership of a bnapi */
1060 static inline bool bnxt_lock_poll(struct bnxt_napi *bnapi)
1061 {
1062         int rc = atomic_cmpxchg(&bnapi->poll_state, BNXT_STATE_IDLE,
1063                                 BNXT_STATE_POLL);
1064
1065         return rc == BNXT_STATE_IDLE;
1066 }
1067
1068 static inline void bnxt_unlock_poll(struct bnxt_napi *bnapi)
1069 {
1070         atomic_set(&bnapi->poll_state, BNXT_STATE_IDLE);
1071 }
1072
1073 static inline bool bnxt_busy_polling(struct bnxt_napi *bnapi)
1074 {
1075         return atomic_read(&bnapi->poll_state) == BNXT_STATE_POLL;
1076 }
1077
1078 static inline void bnxt_disable_poll(struct bnxt_napi *bnapi)
1079 {
1080         int old;
1081
1082         while (1) {
1083                 old = atomic_cmpxchg(&bnapi->poll_state, BNXT_STATE_IDLE,
1084                                      BNXT_STATE_DISABLE);
1085                 if (old == BNXT_STATE_IDLE)
1086                         break;
1087                 usleep_range(500, 5000);
1088         }
1089 }
1090
1091 #else
1092
1093 static inline void bnxt_enable_poll(struct bnxt_napi *bnapi)
1094 {
1095 }
1096
1097 static inline bool bnxt_lock_napi(struct bnxt_napi *bnapi)
1098 {
1099         return true;
1100 }
1101
1102 static inline void bnxt_unlock_napi(struct bnxt_napi *bnapi)
1103 {
1104 }
1105
1106 static inline bool bnxt_lock_poll(struct bnxt_napi *bnapi)
1107 {
1108         return false;
1109 }
1110
1111 static inline void bnxt_unlock_poll(struct bnxt_napi *bnapi)
1112 {
1113 }
1114
1115 static inline bool bnxt_busy_polling(struct bnxt_napi *bnapi)
1116 {
1117         return false;
1118 }
1119
1120 static inline void bnxt_disable_poll(struct bnxt_napi *bnapi)
1121 {
1122 }
1123
1124 #endif
1125
1126 void bnxt_set_ring_params(struct bnxt *);
1127 void bnxt_hwrm_cmd_hdr_init(struct bnxt *, void *, u16, u16, u16);
1128 int _hwrm_send_message(struct bnxt *, void *, u32, int);
1129 int hwrm_send_message(struct bnxt *, void *, u32, int);
1130 int hwrm_send_message_silent(struct bnxt *, void *, u32, int);
1131 int bnxt_hwrm_set_coal(struct bnxt *);
1132 int bnxt_hwrm_func_qcaps(struct bnxt *);
1133 int bnxt_hwrm_set_pause(struct bnxt *);
1134 int bnxt_hwrm_set_link_setting(struct bnxt *, bool, bool);
1135 int bnxt_open_nic(struct bnxt *, bool, bool);
1136 int bnxt_close_nic(struct bnxt *, bool, bool);
1137 int bnxt_get_max_rings(struct bnxt *, int *, int *, bool);
1138 #endif