drivers/net/ethernet/chelsio/cxgb/sge.c

   1 /*****************************************************************************
   2  *                                                                           *
   3  * File: sge.c                                                               *
   4  * $Revision: 1.26 $                                                         *
   5  * $Date: 2005/06/21 18:29:48 $                                              *
   6  * Description:                                                              *
   7  *  DMA engine.                                                              *
   8  *  part of the Chelsio 10Gb Ethernet Driver.                                *
   9  *                                                                           *
  10  * This program is free software; you can redistribute it and/or modify      *
  11  * it under the terms of the GNU General Public License, version 2, as       *
  12  * published by the Free Software Foundation.                                *
  13  *                                                                           *
  14  * You should have received a copy of the GNU General Public License along   *
  15  * with this program; if not, write to the Free Software Foundation, Inc.,   *
  16  * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.                 *
  17  *                                                                           *
  18  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED    *
  19  * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF      *
  20  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.                     *
  21  *                                                                           *
  22  * http://www.chelsio.com                                                    *
  23  *                                                                           *
  24  * Copyright (c) 2003 - 2005 Chelsio Communications, Inc.                    *
  25  * All rights reserved.                                                      *
  26  *                                                                           *
  27  * Maintainers: maintainers@chelsio.com                                      *
  28  *                                                                           *
  29  * Authors: Dimitrios Michailidis   <dm@chelsio.com>                         *
  30  *          Tina Yang               <tainay@chelsio.com>                     *
  31  *          Felix Marti             <felix@chelsio.com>                      *
  32  *          Scott Bardone           <sbardone@chelsio.com>                   *
  33  *          Kurt Ottaway            <kottaway@chelsio.com>                   *
  34  *          Frank DiMambro          <frank@chelsio.com>                      *
  35  *                                                                           *
  36  * History:                                                                  *
  37  *                                                                           *
  38  ****************************************************************************/
  39
  40 #include "common.h"
  41
  42 #include <linux/types.h>
  43 #include <linux/errno.h>
  44 #include <linux/pci.h>
  45 #include <linux/ktime.h>
  46 #include <linux/netdevice.h>
  47 #include <linux/etherdevice.h>
  48 #include <linux/if_vlan.h>
  49 #include <linux/skbuff.h>
  50 #include <linux/init.h>
  51 #include <linux/mm.h>
  52 #include <linux/tcp.h>
  53 #include <linux/ip.h>
  54 #include <linux/in.h>
  55 #include <linux/if_arp.h>
  56 #include <linux/slab.h>
  57 #include <linux/prefetch.h>
  58
  59 #include "cpl5_cmd.h"
  60 #include "sge.h"
  61 #include "regs.h"
  62 #include "espi.h"
  63
  64 /* This belongs in if_ether.h */
  65 #define ETH_P_CPL5 0xf
  66
  67 #define SGE_CMDQ_N              2
  68 #define SGE_FREELQ_N            2
  69 #define SGE_CMDQ0_E_N           1024
  70 #define SGE_CMDQ1_E_N           128
  71 #define SGE_FREEL_SIZE          4096
  72 #define SGE_JUMBO_FREEL_SIZE    512
  73 #define SGE_FREEL_REFILL_THRESH 16
  74 #define SGE_RESPQ_E_N           1024
  75 #define SGE_INTRTIMER_NRES      1000
  76 #define SGE_RX_SM_BUF_SIZE      1536
  77 #define SGE_TX_DESC_MAX_PLEN    16384
  78
  79 #define SGE_RESPQ_REPLENISH_THRES (SGE_RESPQ_E_N / 4)
  80
  81 /*
  82  * Period of the TX buffer reclaim timer.  This timer does not need to run
  83  * frequently as TX buffers are usually reclaimed by new TX packets.
  84  */
  85 #define TX_RECLAIM_PERIOD (HZ / 4)
  86
  87 #define M_CMD_LEN       0x7fffffff
  88 #define V_CMD_LEN(v)    (v)
  89 #define G_CMD_LEN(v)    ((v) & M_CMD_LEN)
  90 #define V_CMD_GEN1(v)   ((v) << 31)
  91 #define V_CMD_GEN2(v)   (v)
  92 #define F_CMD_DATAVALID (1 << 1)
  93 #define F_CMD_SOP       (1 << 2)
  94 #define V_CMD_EOP(v)    ((v) << 3)
  95
  96 /*
  97  * Command queue, receive buffer list, and response queue descriptors.
  98  */
  99 #if defined(__BIG_ENDIAN_BITFIELD)
 100 struct cmdQ_e {
 101         u32 addr_lo;
 102         u32 len_gen;
 103         u32 flags;
 104         u32 addr_hi;
 105 };
 106
 107 struct freelQ_e {
 108         u32 addr_lo;
 109         u32 len_gen;
 110         u32 gen2;
 111         u32 addr_hi;
 112 };
 113
 114 struct respQ_e {
 115         u32 Qsleeping           : 4;
 116         u32 Cmdq1CreditReturn   : 5;
 117         u32 Cmdq1DmaComplete    : 5;
 118         u32 Cmdq0CreditReturn   : 5;
 119         u32 Cmdq0DmaComplete    : 5;
 120         u32 FreelistQid         : 2;
 121         u32 CreditValid         : 1;
 122         u32 DataValid           : 1;
 123         u32 Offload             : 1;
 124         u32 Eop                 : 1;
 125         u32 Sop                 : 1;
 126         u32 GenerationBit       : 1;
 127         u32 BufferLength;
 128 };
 129 #elif defined(__LITTLE_ENDIAN_BITFIELD)
 130 struct cmdQ_e {
 131         u32 len_gen;
 132         u32 addr_lo;
 133         u32 addr_hi;
 134         u32 flags;
 135 };
 136
 137 struct freelQ_e {
 138         u32 len_gen;
 139         u32 addr_lo;
 140         u32 addr_hi;
 141         u32 gen2;
 142 };
 143
 144 struct respQ_e {
 145         u32 BufferLength;
 146         u32 GenerationBit       : 1;
 147         u32 Sop                 : 1;
 148         u32 Eop                 : 1;
 149         u32 Offload             : 1;
 150         u32 DataValid           : 1;
 151         u32 CreditValid         : 1;
 152         u32 FreelistQid         : 2;
 153         u32 Cmdq0DmaComplete    : 5;
 154         u32 Cmdq0CreditReturn   : 5;
 155         u32 Cmdq1DmaComplete    : 5;
 156         u32 Cmdq1CreditReturn   : 5;
 157         u32 Qsleeping           : 4;
 158 } ;
 159 #endif
 160
 161 /*
 162  * SW Context Command and Freelist Queue Descriptors
 163  */
 164 struct cmdQ_ce {
 165         struct sk_buff *skb;
 166         DEFINE_DMA_UNMAP_ADDR(dma_addr);
 167         DEFINE_DMA_UNMAP_LEN(dma_len);
 168 };
 169
 170 struct freelQ_ce {
 171         struct sk_buff *skb;
 172         DEFINE_DMA_UNMAP_ADDR(dma_addr);
 173         DEFINE_DMA_UNMAP_LEN(dma_len);
 174 };
 175
 176 /*
 177  * SW command, freelist and response rings
 178  */
 179 struct cmdQ {
 180         unsigned long   status;         /* HW DMA fetch status */
 181         unsigned int    in_use;         /* # of in-use command descriptors */
 182         unsigned int    size;           /* # of descriptors */
 183         unsigned int    processed;      /* total # of descs HW has processed */
 184         unsigned int    cleaned;        /* total # of descs SW has reclaimed */
 185         unsigned int    stop_thres;     /* SW TX queue suspend threshold */
 186         u16             pidx;           /* producer index (SW) */
 187         u16             cidx;           /* consumer index (HW) */
 188         u8              genbit;         /* current generation (=valid) bit */
 189         u8              sop;            /* is next entry start of packet? */
 190         struct cmdQ_e  *entries;        /* HW command descriptor Q */
 191         struct cmdQ_ce *centries;       /* SW command context descriptor Q */
 192         dma_addr_t      dma_addr;       /* DMA addr HW command descriptor Q */
 193         spinlock_t      lock;           /* Lock to protect cmdQ enqueuing */
 194 };
 195
 196 struct freelQ {
 197         unsigned int    credits;        /* # of available RX buffers */
 198         unsigned int    size;           /* free list capacity */
 199         u16             pidx;           /* producer index (SW) */
 200         u16             cidx;           /* consumer index (HW) */
 201         u16             rx_buffer_size; /* Buffer size on this free list */
 202         u16             dma_offset;     /* DMA offset to align IP headers */
 203         u16             recycleq_idx;   /* skb recycle q to use */
 204         u8              genbit;         /* current generation (=valid) bit */
 205         struct freelQ_e *entries;       /* HW freelist descriptor Q */
 206         struct freelQ_ce *centries;     /* SW freelist context descriptor Q */
 207         dma_addr_t      dma_addr;       /* DMA addr HW freelist descriptor Q */
 208 };
 209
 210 struct respQ {
 211         unsigned int    credits;        /* credits to be returned to SGE */
 212         unsigned int    size;           /* # of response Q descriptors */
 213         u16             cidx;           /* consumer index (SW) */
 214         u8              genbit;         /* current generation(=valid) bit */
 215         struct respQ_e *entries;        /* HW response descriptor Q */
 216         dma_addr_t      dma_addr;       /* DMA addr HW response descriptor Q */
 217 };
 218
 219 /* Bit flags for cmdQ.status */
 220 enum {
 221         CMDQ_STAT_RUNNING = 1,          /* fetch engine is running */
 222         CMDQ_STAT_LAST_PKT_DB = 2       /* last packet rung the doorbell */
 223 };
 224
 225 /* T204 TX SW scheduler */
 226
 227 /* Per T204 TX port */
 228 struct sched_port {
 229         unsigned int    avail;          /* available bits - quota */
 230         unsigned int    drain_bits_per_1024ns; /* drain rate */
 231         unsigned int    speed;          /* drain rate, mbps */
 232         unsigned int    mtu;            /* mtu size */
 233         struct sk_buff_head skbq;       /* pending skbs */
 234 };
 235
 236 /* Per T204 device */
 237 struct sched {
 238         ktime_t         last_updated;   /* last time quotas were computed */
 239         unsigned int    max_avail;      /* max bits to be sent to any port */
 240         unsigned int    port;           /* port index (round robin ports) */
 241         unsigned int    num;            /* num skbs in per port queues */
 242         struct sched_port p[MAX_NPORTS];
 243         struct tasklet_struct sched_tsk;/* tasklet used to run scheduler */
 244 };
 245 static void restart_sched(unsigned long);
 246
 247
 248 /*
 249  * Main SGE data structure
 250  *
 251  * Interrupts are handled by a single CPU and it is likely that on a MP system
 252  * the application is migrated to another CPU. In that scenario, we try to
 253  * separate the RX(in irq context) and TX state in order to decrease memory
 254  * contention.
 255  */
 256 struct sge {
 257         struct adapter *adapter;        /* adapter backpointer */
 258         struct net_device *netdev;      /* netdevice backpointer */
 259         struct freelQ   freelQ[SGE_FREELQ_N]; /* buffer free lists */
 260         struct respQ    respQ;          /* response Q */
 261         unsigned long   stopped_tx_queues; /* bitmap of suspended Tx queues */
 262         unsigned int    rx_pkt_pad;     /* RX padding for L2 packets */
 263         unsigned int    jumbo_fl;       /* jumbo freelist Q index */
 264         unsigned int    intrtimer_nres; /* no-resource interrupt timer */
 265         unsigned int    fixed_intrtimer;/* non-adaptive interrupt timer */
 266         struct timer_list tx_reclaim_timer; /* reclaims TX buffers */
 267         struct timer_list espibug_timer;
 268         unsigned long   espibug_timeout;
 269         struct sk_buff  *espibug_skb[MAX_NPORTS];
 270         u32             sge_control;    /* shadow value of sge control reg */
 271         struct sge_intr_counts stats;
 272         struct sge_port_stats __percpu *port_stats[MAX_NPORTS];
 273         struct sched    *tx_sched;
 274         struct cmdQ cmdQ[SGE_CMDQ_N] ____cacheline_aligned_in_smp;
 275 };
 276
 277 static const u8 ch_mac_addr[ETH_ALEN] = {
 278         0x0, 0x7, 0x43, 0x0, 0x0, 0x0
 279 };
 280
 281 /*
 282  * stop tasklet and free all pending skb's
 283  */
 284 static void tx_sched_stop(struct sge *sge)
 285 {
 286         struct sched *s = sge->tx_sched;
 287         int i;
 288
 289         tasklet_kill(&s->sched_tsk);
 290
 291         for (i = 0; i < MAX_NPORTS; i++)
 292                 __skb_queue_purge(&s->p[s->port].skbq);
 293 }
 294
 295 /*
 296  * t1_sched_update_parms() is called when the MTU or link speed changes. It
 297  * re-computes scheduler parameters to scope with the change.
 298  */
 299 unsigned int t1_sched_update_parms(struct sge *sge, unsigned int port,
 300                                    unsigned int mtu, unsigned int speed)
 301 {
 302         struct sched *s = sge->tx_sched;
 303         struct sched_port *p = &s->p[port];
 304         unsigned int max_avail_segs;
 305
 306         pr_debug("t1_sched_update_params mtu=%d speed=%d\n", mtu, speed);
 307         if (speed)
 308                 p->speed = speed;
 309         if (mtu)
 310                 p->mtu = mtu;
 311
 312         if (speed || mtu) {
 313                 unsigned long long drain = 1024ULL * p->speed * (p->mtu - 40);
 314                 do_div(drain, (p->mtu + 50) * 1000);
 315                 p->drain_bits_per_1024ns = (unsigned int) drain;
 316
 317                 if (p->speed < 1000)
 318                         p->drain_bits_per_1024ns =
 319                                 90 * p->drain_bits_per_1024ns / 100;
 320         }
 321
 322         if (board_info(sge->adapter)->board == CHBT_BOARD_CHT204) {
 323                 p->drain_bits_per_1024ns -= 16;
 324                 s->max_avail = max(4096U, p->mtu + 16 + 14 + 4);
 325                 max_avail_segs = max(1U, 4096 / (p->mtu - 40));
 326         } else {
 327                 s->max_avail = 16384;
 328                 max_avail_segs = max(1U, 9000 / (p->mtu - 40));
 329         }
 330
 331         pr_debug("t1_sched_update_parms: mtu %u speed %u max_avail %u "
 332                  "max_avail_segs %u drain_bits_per_1024ns %u\n", p->mtu,
 333                  p->speed, s->max_avail, max_avail_segs,
 334                  p->drain_bits_per_1024ns);
 335
 336         return max_avail_segs * (p->mtu - 40);
 337 }
 338
 339 #if 0
 340
 341 /*
 342  * t1_sched_max_avail_bytes() tells the scheduler the maximum amount of
 343  * data that can be pushed per port.
 344  */
 345 void t1_sched_set_max_avail_bytes(struct sge *sge, unsigned int val)
 346 {
 347         struct sched *s = sge->tx_sched;
 348         unsigned int i;
 349
 350         s->max_avail = val;
 351         for (i = 0; i < MAX_NPORTS; i++)
 352                 t1_sched_update_parms(sge, i, 0, 0);
 353 }
 354
 355 /*
 356  * t1_sched_set_drain_bits_per_us() tells the scheduler at which rate a port
 357  * is draining.
 358  */
 359 void t1_sched_set_drain_bits_per_us(struct sge *sge, unsigned int port,
 360                                          unsigned int val)
 361 {
 362         struct sched *s = sge->tx_sched;
 363         struct sched_port *p = &s->p[port];
 364         p->drain_bits_per_1024ns = val * 1024 / 1000;
 365         t1_sched_update_parms(sge, port, 0, 0);
 366 }
 367
 368 #endif  /*  0  */
 369
 370 /*
 371  * tx_sched_init() allocates resources and does basic initialization.
 372  */
 373 static int tx_sched_init(struct sge *sge)
 374 {
 375         struct sched *s;
 376         int i;
 377
 378         s = kzalloc(sizeof (struct sched), GFP_KERNEL);
 379         if (!s)
 380                 return -ENOMEM;
 381
 382         pr_debug("tx_sched_init\n");
 383         tasklet_init(&s->sched_tsk, restart_sched, (unsigned long) sge);
 384         sge->tx_sched = s;
 385
 386         for (i = 0; i < MAX_NPORTS; i++) {
 387                 skb_queue_head_init(&s->p[i].skbq);
 388                 t1_sched_update_parms(sge, i, 1500, 1000);
 389         }
 390
 391         return 0;
 392 }
 393
 394 /*
 395  * sched_update_avail() computes the delta since the last time it was called
 396  * and updates the per port quota (number of bits that can be sent to the any
 397  * port).
 398  */
 399 static inline int sched_update_avail(struct sge *sge)
 400 {
 401         struct sched *s = sge->tx_sched;
 402         ktime_t now = ktime_get();
 403         unsigned int i;
 404         long long delta_time_ns;
 405
 406         delta_time_ns = ktime_to_ns(ktime_sub(now, s->last_updated));
 407
 408         pr_debug("sched_update_avail delta=%lld\n", delta_time_ns);
 409         if (delta_time_ns < 15000)
 410                 return 0;
 411
 412         for (i = 0; i < MAX_NPORTS; i++) {
 413                 struct sched_port *p = &s->p[i];
 414                 unsigned int delta_avail;
 415
 416                 delta_avail = (p->drain_bits_per_1024ns * delta_time_ns) >> 13;
 417                 p->avail = min(p->avail + delta_avail, s->max_avail);
 418         }
 419
 420         s->last_updated = now;
 421
 422         return 1;
 423 }
 424
 425 /*
 426  * sched_skb() is called from two different places. In the tx path, any
 427  * packet generating load on an output port will call sched_skb()
 428  * (skb != NULL). In addition, sched_skb() is called from the irq/soft irq
 429  * context (skb == NULL).
 430  * The scheduler only returns a skb (which will then be sent) if the
 431  * length of the skb is <= the current quota of the output port.
 432  */
 433 static struct sk_buff *sched_skb(struct sge *sge, struct sk_buff *skb,
 434                                 unsigned int credits)
 435 {
 436         struct sched *s = sge->tx_sched;
 437         struct sk_buff_head *skbq;
 438         unsigned int i, len, update = 1;
 439
 440         pr_debug("sched_skb %p\n", skb);
 441         if (!skb) {
 442                 if (!s->num)
 443                         return NULL;
 444         } else {
 445                 skbq = &s->p[skb->dev->if_port].skbq;
 446                 __skb_queue_tail(skbq, skb);
 447                 s->num++;
 448                 skb = NULL;
 449         }
 450
 451         if (credits < MAX_SKB_FRAGS + 1)
 452                 goto out;
 453
 454 again:
 455         for (i = 0; i < MAX_NPORTS; i++) {
 456                 s->port = (s->port + 1) & (MAX_NPORTS - 1);
 457                 skbq = &s->p[s->port].skbq;
 458
 459                 skb = skb_peek(skbq);
 460
 461                 if (!skb)
 462                         continue;
 463
 464                 len = skb->len;
 465                 if (len <= s->p[s->port].avail) {
 466                         s->p[s->port].avail -= len;
 467                         s->num--;
 468                         __skb_unlink(skb, skbq);
 469                         goto out;
 470                 }
 471                 skb = NULL;
 472         }
 473
 474         if (update-- && sched_update_avail(sge))
 475                 goto again;
 476
 477 out:
 478         /* If there are more pending skbs, we use the hardware to schedule us
 479          * again.
 480          */
 481         if (s->num && !skb) {
 482                 struct cmdQ *q = &sge->cmdQ[0];
 483                 clear_bit(CMDQ_STAT_LAST_PKT_DB, &q->status);
 484                 if (test_and_set_bit(CMDQ_STAT_RUNNING, &q->status) == 0) {
 485                         set_bit(CMDQ_STAT_LAST_PKT_DB, &q->status);
 486                         writel(F_CMDQ0_ENABLE, sge->adapter->regs + A_SG_DOORBELL);
 487                 }
 488         }
 489         pr_debug("sched_skb ret %p\n", skb);
 490
 491         return skb;
 492 }
 493
 494 /*
 495  * PIO to indicate that memory mapped Q contains valid descriptor(s).
 496  */
 497 static inline void doorbell_pio(struct adapter *adapter, u32 val)
 498 {
 499         wmb();
 500         writel(val, adapter->regs + A_SG_DOORBELL);
 501 }
 502
 503 /*
 504  * Frees all RX buffers on the freelist Q. The caller must make sure that
 505  * the SGE is turned off before calling this function.
 506  */
 507 static void free_freelQ_buffers(struct pci_dev *pdev, struct freelQ *q)
 508 {
 509         unsigned int cidx = q->cidx;
 510
 511         while (q->credits--) {
 512                 struct freelQ_ce *ce = &q->centries[cidx];
 513
 514                 pci_unmap_single(pdev, dma_unmap_addr(ce, dma_addr),
 515                                  dma_unmap_len(ce, dma_len),
 516                                  PCI_DMA_FROMDEVICE);
 517                 dev_kfree_skb(ce->skb);
 518                 ce->skb = NULL;
 519                 if (++cidx == q->size)
 520                         cidx = 0;
 521         }
 522 }
 523
 524 /*
 525  * Free RX free list and response queue resources.
 526  */
 527 static void free_rx_resources(struct sge *sge)
 528 {
 529         struct pci_dev *pdev = sge->adapter->pdev;
 530         unsigned int size, i;
 531
 532         if (sge->respQ.entries) {
 533                 size = sizeof(struct respQ_e) * sge->respQ.size;
 534                 pci_free_consistent(pdev, size, sge->respQ.entries,
 535                                     sge->respQ.dma_addr);
 536         }
 537
 538         for (i = 0; i < SGE_FREELQ_N; i++) {
 539                 struct freelQ *q = &sge->freelQ[i];
 540
 541                 if (q->centries) {
 542                         free_freelQ_buffers(pdev, q);
 543                         kfree(q->centries);
 544                 }
 545                 if (q->entries) {
 546                         size = sizeof(struct freelQ_e) * q->size;
 547                         pci_free_consistent(pdev, size, q->entries,
 548                                             q->dma_addr);
 549                 }
 550         }
 551 }
 552
 553 /*
 554  * Allocates basic RX resources, consisting of memory mapped freelist Qs and a
 555  * response queue.
 556  */
 557 static int alloc_rx_resources(struct sge *sge, struct sge_params *p)
 558 {
 559         struct pci_dev *pdev = sge->adapter->pdev;
 560         unsigned int size, i;
 561
 562         for (i = 0; i < SGE_FREELQ_N; i++) {
 563                 struct freelQ *q = &sge->freelQ[i];
 564
 565                 q->genbit = 1;
 566                 q->size = p->freelQ_size[i];
 567                 q->dma_offset = sge->rx_pkt_pad ? 0 : NET_IP_ALIGN;
 568                 size = sizeof(struct freelQ_e) * q->size;
 569                 q->entries = pci_alloc_consistent(pdev, size, &q->dma_addr);
 570                 if (!q->entries)
 571                         goto err_no_mem;
 572
 573                 size = sizeof(struct freelQ_ce) * q->size;
 574                 q->centries = kzalloc(size, GFP_KERNEL);
 575                 if (!q->centries)
 576                         goto err_no_mem;
 577         }
 578
 579         /*
 580          * Calculate the buffer sizes for the two free lists.  FL0 accommodates
 581          * regular sized Ethernet frames, FL1 is sized not to exceed 16K,
 582          * including all the sk_buff overhead.
 583          *
 584          * Note: For T2 FL0 and FL1 are reversed.
 585          */
 586         sge->freelQ[!sge->jumbo_fl].rx_buffer_size = SGE_RX_SM_BUF_SIZE +
 587                 sizeof(struct cpl_rx_data) +
 588                 sge->freelQ[!sge->jumbo_fl].dma_offset;
 589
 590                 size = (16 * 1024) -
 591                     SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
 592
 593         sge->freelQ[sge->jumbo_fl].rx_buffer_size = size;
 594
 595         /*
 596          * Setup which skb recycle Q should be used when recycling buffers from
 597          * each free list.
 598          */
 599         sge->freelQ[!sge->jumbo_fl].recycleq_idx = 0;
 600         sge->freelQ[sge->jumbo_fl].recycleq_idx = 1;
 601
 602         sge->respQ.genbit = 1;
 603         sge->respQ.size = SGE_RESPQ_E_N;
 604         sge->respQ.credits = 0;
 605         size = sizeof(struct respQ_e) * sge->respQ.size;
 606         sge->respQ.entries =
 607                 pci_alloc_consistent(pdev, size, &sge->respQ.dma_addr);
 608         if (!sge->respQ.entries)
 609                 goto err_no_mem;
 610         return 0;
 611
 612 err_no_mem:
 613         free_rx_resources(sge);
 614         return -ENOMEM;
 615 }
 616
 617 /*
 618  * Reclaims n TX descriptors and frees the buffers associated with them.
 619  */
 620 static void free_cmdQ_buffers(struct sge *sge, struct cmdQ *q, unsigned int n)
 621 {
 622         struct cmdQ_ce *ce;
 623         struct pci_dev *pdev = sge->adapter->pdev;
 624         unsigned int cidx = q->cidx;
 625
 626         q->in_use -= n;
 627         ce = &q->centries[cidx];
 628         while (n--) {
 629                 if (likely(dma_unmap_len(ce, dma_len))) {
 630                         pci_unmap_single(pdev, dma_unmap_addr(ce, dma_addr),
 631                                          dma_unmap_len(ce, dma_len),
 632                                          PCI_DMA_TODEVICE);
 633                         if (q->sop)
 634                                 q->sop = 0;
 635                 }
 636                 if (ce->skb) {
 637                         dev_kfree_skb_any(ce->skb);
 638                         q->sop = 1;
 639                 }
 640                 ce++;
 641                 if (++cidx == q->size) {
 642                         cidx = 0;
 643                         ce = q->centries;
 644                 }
 645         }
 646         q->cidx = cidx;
 647 }
 648
 649 /*
 650  * Free TX resources.
 651  *
 652  * Assumes that SGE is stopped and all interrupts are disabled.
 653  */
 654 static void free_tx_resources(struct sge *sge)
 655 {
 656         struct pci_dev *pdev = sge->adapter->pdev;
 657         unsigned int size, i;
 658
 659         for (i = 0; i < SGE_CMDQ_N; i++) {
 660                 struct cmdQ *q = &sge->cmdQ[i];
 661
 662                 if (q->centries) {
 663                         if (q->in_use)
 664                                 free_cmdQ_buffers(sge, q, q->in_use);
 665                         kfree(q->centries);
 666                 }
 667                 if (q->entries) {
 668                         size = sizeof(struct cmdQ_e) * q->size;
 669                         pci_free_consistent(pdev, size, q->entries,
 670                                             q->dma_addr);
 671                 }
 672         }
 673 }
 674
 675 /*
 676  * Allocates basic TX resources, consisting of memory mapped command Qs.
 677  */
 678 static int alloc_tx_resources(struct sge *sge, struct sge_params *p)
 679 {
 680         struct pci_dev *pdev = sge->adapter->pdev;
 681         unsigned int size, i;
 682
 683         for (i = 0; i < SGE_CMDQ_N; i++) {
 684                 struct cmdQ *q = &sge->cmdQ[i];
 685
 686                 q->genbit = 1;
 687                 q->sop = 1;
 688                 q->size = p->cmdQ_size[i];
 689                 q->in_use = 0;
 690                 q->status = 0;
 691                 q->processed = q->cleaned = 0;
 692                 q->stop_thres = 0;
 693                 spin_lock_init(&q->lock);
 694                 size = sizeof(struct cmdQ_e) * q->size;
 695                 q->entries = pci_alloc_consistent(pdev, size, &q->dma_addr);
 696                 if (!q->entries)
 697                         goto err_no_mem;
 698
 699                 size = sizeof(struct cmdQ_ce) * q->size;
 700                 q->centries = kzalloc(size, GFP_KERNEL);
 701                 if (!q->centries)
 702                         goto err_no_mem;
 703         }
 704
 705         /*
 706          * CommandQ 0 handles Ethernet and TOE packets, while queue 1 is TOE
 707          * only.  For queue 0 set the stop threshold so we can handle one more
 708          * packet from each port, plus reserve an additional 24 entries for
 709          * Ethernet packets only.  Queue 1 never suspends nor do we reserve
 710          * space for Ethernet packets.
 711          */
 712         sge->cmdQ[0].stop_thres = sge->adapter->params.nports *
 713                 (MAX_SKB_FRAGS + 1);
 714         return 0;
 715
 716 err_no_mem:
 717         free_tx_resources(sge);
 718         return -ENOMEM;
 719 }
 720
 721 static inline void setup_ring_params(struct adapter *adapter, u64 addr,
 722                                      u32 size, int base_reg_lo,
 723                                      int base_reg_hi, int size_reg)
 724 {
 725         writel((u32)addr, adapter->regs + base_reg_lo);
 726         writel(addr >> 32, adapter->regs + base_reg_hi);
 727         writel(size, adapter->regs + size_reg);
 728 }
 729
 730 /*
 731  * Enable/disable VLAN acceleration.
 732  */
 733 void t1_vlan_mode(struct adapter *adapter, netdev_features_t features)
 734 {
 735         struct sge *sge = adapter->sge;
 736
 737         if (features & NETIF_F_HW_VLAN_RX)
 738                 sge->sge_control |= F_VLAN_XTRACT;
 739         else
 740                 sge->sge_control &= ~F_VLAN_XTRACT;
 741         if (adapter->open_device_map) {
 742                 writel(sge->sge_control, adapter->regs + A_SG_CONTROL);
 743                 readl(adapter->regs + A_SG_CONTROL);   /* flush */
 744         }
 745 }
 746
 747 /*
 748  * Programs the various SGE registers. However, the engine is not yet enabled,
 749  * but sge->sge_control is setup and ready to go.
 750  */
 751 static void configure_sge(struct sge *sge, struct sge_params *p)
 752 {
 753         struct adapter *ap = sge->adapter;
 754
 755         writel(0, ap->regs + A_SG_CONTROL);
 756         setup_ring_params(ap, sge->cmdQ[0].dma_addr, sge->cmdQ[0].size,
 757                           A_SG_CMD0BASELWR, A_SG_CMD0BASEUPR, A_SG_CMD0SIZE);
 758         setup_ring_params(ap, sge->cmdQ[1].dma_addr, sge->cmdQ[1].size,
 759                           A_SG_CMD1BASELWR, A_SG_CMD1BASEUPR, A_SG_CMD1SIZE);
 760         setup_ring_params(ap, sge->freelQ[0].dma_addr,
 761                           sge->freelQ[0].size, A_SG_FL0BASELWR,
 762                           A_SG_FL0BASEUPR, A_SG_FL0SIZE);
 763         setup_ring_params(ap, sge->freelQ[1].dma_addr,
 764                           sge->freelQ[1].size, A_SG_FL1BASELWR,
 765                           A_SG_FL1BASEUPR, A_SG_FL1SIZE);
 766
 767         /* The threshold comparison uses <. */
 768         writel(SGE_RX_SM_BUF_SIZE + 1, ap->regs + A_SG_FLTHRESHOLD);
 769
 770         setup_ring_params(ap, sge->respQ.dma_addr, sge->respQ.size,
 771                           A_SG_RSPBASELWR, A_SG_RSPBASEUPR, A_SG_RSPSIZE);
 772         writel((u32)sge->respQ.size - 1, ap->regs + A_SG_RSPQUEUECREDIT);
 773
 774         sge->sge_control = F_CMDQ0_ENABLE | F_CMDQ1_ENABLE | F_FL0_ENABLE |
 775                 F_FL1_ENABLE | F_CPL_ENABLE | F_RESPONSE_QUEUE_ENABLE |
 776                 V_CMDQ_PRIORITY(2) | F_DISABLE_CMDQ1_GTS | F_ISCSI_COALESCE |
 777                 V_RX_PKT_OFFSET(sge->rx_pkt_pad);
 778
 779 #if defined(__BIG_ENDIAN_BITFIELD)
 780         sge->sge_control |= F_ENABLE_BIG_ENDIAN;
 781 #endif
 782
 783         /* Initialize no-resource timer */
 784         sge->intrtimer_nres = SGE_INTRTIMER_NRES * core_ticks_per_usec(ap);
 785
 786         t1_sge_set_coalesce_params(sge, p);
 787 }
 788
 789 /*
 790  * Return the payload capacity of the jumbo free-list buffers.
 791  */
 792 static inline unsigned int jumbo_payload_capacity(const struct sge *sge)
 793 {
 794         return sge->freelQ[sge->jumbo_fl].rx_buffer_size -
 795                 sge->freelQ[sge->jumbo_fl].dma_offset -
 796                 sizeof(struct cpl_rx_data);
 797 }
 798
 799 /*
 800  * Frees all SGE related resources and the sge structure itself
 801  */
 802 void t1_sge_destroy(struct sge *sge)
 803 {
 804         int i;
 805
 806         for_each_port(sge->adapter, i)
 807                 free_percpu(sge->port_stats[i]);
 808
 809         kfree(sge->tx_sched);
 810         free_tx_resources(sge);
 811         free_rx_resources(sge);
 812         kfree(sge);
 813 }
 814
 815 /*
 816  * Allocates new RX buffers on the freelist Q (and tracks them on the freelist
 817  * context Q) until the Q is full or alloc_skb fails.
 818  *
 819  * It is possible that the generation bits already match, indicating that the
 820  * buffer is already valid and nothing needs to be done. This happens when we
 821  * copied a received buffer into a new sk_buff during the interrupt processing.
 822  *
 823  * If the SGE doesn't automatically align packets properly (!sge->rx_pkt_pad),
 824  * we specify a RX_OFFSET in order to make sure that the IP header is 4B
 825  * aligned.
 826  */
 827 static void refill_free_list(struct sge *sge, struct freelQ *q)
 828 {
 829         struct pci_dev *pdev = sge->adapter->pdev;
 830         struct freelQ_ce *ce = &q->centries[q->pidx];
 831         struct freelQ_e *e = &q->entries[q->pidx];
 832         unsigned int dma_len = q->rx_buffer_size - q->dma_offset;
 833
 834         while (q->credits < q->size) {
 835                 struct sk_buff *skb;
 836                 dma_addr_t mapping;
 837
 838                 skb = alloc_skb(q->rx_buffer_size, GFP_ATOMIC);
 839                 if (!skb)
 840                         break;
 841
 842                 skb_reserve(skb, q->dma_offset);
 843                 mapping = pci_map_single(pdev, skb->data, dma_len,
 844                                          PCI_DMA_FROMDEVICE);
 845                 skb_reserve(skb, sge->rx_pkt_pad);
 846
 847                 ce->skb = skb;
 848                 dma_unmap_addr_set(ce, dma_addr, mapping);
 849                 dma_unmap_len_set(ce, dma_len, dma_len);
 850                 e->addr_lo = (u32)mapping;
 851                 e->addr_hi = (u64)mapping >> 32;
 852                 e->len_gen = V_CMD_LEN(dma_len) | V_CMD_GEN1(q->genbit);
 853                 wmb();
 854                 e->gen2 = V_CMD_GEN2(q->genbit);
 855
 856                 e++;
 857                 ce++;
 858                 if (++q->pidx == q->size) {
 859                         q->pidx = 0;
 860                         q->genbit ^= 1;
 861                         ce = q->centries;
 862                         e = q->entries;
 863                 }
 864                 q->credits++;
 865         }
 866 }
 867
 868 /*
 869  * Calls refill_free_list for both free lists. If we cannot fill at least 1/4
 870  * of both rings, we go into 'few interrupt mode' in order to give the system
 871  * time to free up resources.
 872  */
 873 static void freelQs_empty(struct sge *sge)
 874 {
 875         struct adapter *adapter = sge->adapter;
 876         u32 irq_reg = readl(adapter->regs + A_SG_INT_ENABLE);
 877         u32 irqholdoff_reg;
 878
 879         refill_free_list(sge, &sge->freelQ[0]);
 880         refill_free_list(sge, &sge->freelQ[1]);
 881
 882         if (sge->freelQ[0].credits > (sge->freelQ[0].size >> 2) &&
 883             sge->freelQ[1].credits > (sge->freelQ[1].size >> 2)) {
 884                 irq_reg |= F_FL_EXHAUSTED;
 885                 irqholdoff_reg = sge->fixed_intrtimer;
 886         } else {
 887                 /* Clear the F_FL_EXHAUSTED interrupts for now */
 888                 irq_reg &= ~F_FL_EXHAUSTED;
 889                 irqholdoff_reg = sge->intrtimer_nres;
 890         }
 891         writel(irqholdoff_reg, adapter->regs + A_SG_INTRTIMER);
 892         writel(irq_reg, adapter->regs + A_SG_INT_ENABLE);
 893
 894         /* We reenable the Qs to force a freelist GTS interrupt later */
 895         doorbell_pio(adapter, F_FL0_ENABLE | F_FL1_ENABLE);
 896 }
 897
 898 #define SGE_PL_INTR_MASK (F_PL_INTR_SGE_ERR | F_PL_INTR_SGE_DATA)
 899 #define SGE_INT_FATAL (F_RESPQ_OVERFLOW | F_PACKET_TOO_BIG | F_PACKET_MISMATCH)
 900 #define SGE_INT_ENABLE (F_RESPQ_EXHAUSTED | F_RESPQ_OVERFLOW | \
 901                         F_FL_EXHAUSTED | F_PACKET_TOO_BIG | F_PACKET_MISMATCH)
 902
 903 /*
 904  * Disable SGE Interrupts
 905  */
 906 void t1_sge_intr_disable(struct sge *sge)
 907 {
 908         u32 val = readl(sge->adapter->regs + A_PL_ENABLE);
 909
 910         writel(val & ~SGE_PL_INTR_MASK, sge->adapter->regs + A_PL_ENABLE);
 911         writel(0, sge->adapter->regs + A_SG_INT_ENABLE);
 912 }
 913
 914 /*
 915  * Enable SGE interrupts.
 916  */
 917 void t1_sge_intr_enable(struct sge *sge)
 918 {
 919         u32 en = SGE_INT_ENABLE;
 920         u32 val = readl(sge->adapter->regs + A_PL_ENABLE);
 921
 922         if (sge->adapter->port[0].dev->hw_features & NETIF_F_TSO)
 923                 en &= ~F_PACKET_TOO_BIG;
 924         writel(en, sge->adapter->regs + A_SG_INT_ENABLE);
 925         writel(val | SGE_PL_INTR_MASK, sge->adapter->regs + A_PL_ENABLE);
 926 }
 927
 928 /*
 929  * Clear SGE interrupts.
 930  */
 931 void t1_sge_intr_clear(struct sge *sge)
 932 {
 933         writel(SGE_PL_INTR_MASK, sge->adapter->regs + A_PL_CAUSE);
 934         writel(0xffffffff, sge->adapter->regs + A_SG_INT_CAUSE);
 935 }
 936
 937 /*
 938  * SGE 'Error' interrupt handler
 939  */
 940 int t1_sge_intr_error_handler(struct sge *sge)
 941 {
 942         struct adapter *adapter = sge->adapter;
 943         u32 cause = readl(adapter->regs + A_SG_INT_CAUSE);
 944
 945         if (adapter->port[0].dev->hw_features & NETIF_F_TSO)
 946                 cause &= ~F_PACKET_TOO_BIG;
 947         if (cause & F_RESPQ_EXHAUSTED)
 948                 sge->stats.respQ_empty++;
 949         if (cause & F_RESPQ_OVERFLOW) {
 950                 sge->stats.respQ_overflow++;
 951                 pr_alert("%s: SGE response queue overflow\n",
 952                          adapter->name);
 953         }
 954         if (cause & F_FL_EXHAUSTED) {
 955                 sge->stats.freelistQ_empty++;
 956                 freelQs_empty(sge);
 957         }
 958         if (cause & F_PACKET_TOO_BIG) {
 959                 sge->stats.pkt_too_big++;
 960                 pr_alert("%s: SGE max packet size exceeded\n",
 961                          adapter->name);
 962         }
 963         if (cause & F_PACKET_MISMATCH) {
 964                 sge->stats.pkt_mismatch++;
 965                 pr_alert("%s: SGE packet mismatch\n", adapter->name);
 966         }
 967         if (cause & SGE_INT_FATAL)
 968                 t1_fatal_err(adapter);
 969
 970         writel(cause, adapter->regs + A_SG_INT_CAUSE);
 971         return 0;
 972 }
 973
 974 const struct sge_intr_counts *t1_sge_get_intr_counts(const struct sge *sge)
 975 {
 976         return &sge->stats;
 977 }
 978
 979 void t1_sge_get_port_stats(const struct sge *sge, int port,
 980                            struct sge_port_stats *ss)
 981 {
 982         int cpu;
 983
 984         memset(ss, 0, sizeof(*ss));
 985         for_each_possible_cpu(cpu) {
 986                 struct sge_port_stats *st = per_cpu_ptr(sge->port_stats[port], cpu);
 987
 988                 ss->rx_cso_good += st->rx_cso_good;
 989                 ss->tx_cso += st->tx_cso;
 990                 ss->tx_tso += st->tx_tso;
 991                 ss->tx_need_hdrroom += st->tx_need_hdrroom;
 992                 ss->vlan_xtract += st->vlan_xtract;
 993                 ss->vlan_insert += st->vlan_insert;
 994         }
 995 }
 996
 997 /**
 998  *      recycle_fl_buf - recycle a free list buffer
 999  *      @fl: the free list
1000  *      @idx: index of buffer to recycle
1001  *
1002  *      Recycles the specified buffer on the given free list by adding it at
1003  *      the next available slot on the list.
1004  */
1005 static void recycle_fl_buf(struct freelQ *fl, int idx)
1006 {
1007         struct freelQ_e *from = &fl->entries[idx];
1008         struct freelQ_e *to = &fl->entries[fl->pidx];
1009
1010         fl->centries[fl->pidx] = fl->centries[idx];
1011         to->addr_lo = from->addr_lo;
1012         to->addr_hi = from->addr_hi;
1013         to->len_gen = G_CMD_LEN(from->len_gen) | V_CMD_GEN1(fl->genbit);
1014         wmb();
1015         to->gen2 = V_CMD_GEN2(fl->genbit);
1016         fl->credits++;
1017
1018         if (++fl->pidx == fl->size) {
1019                 fl->pidx = 0;
1020                 fl->genbit ^= 1;
1021         }
1022 }
1023
1024 static int copybreak __read_mostly = 256;
1025 module_param(copybreak, int, 0);
1026 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
1027
1028 /**
1029  *      get_packet - return the next ingress packet buffer
1030  *      @pdev: the PCI device that received the packet
1031  *      @fl: the SGE free list holding the packet
1032  *      @len: the actual packet length, excluding any SGE padding
1033  *
1034  *      Get the next packet from a free list and complete setup of the
1035  *      sk_buff.  If the packet is small we make a copy and recycle the
1036  *      original buffer, otherwise we use the original buffer itself.  If a
1037  *      positive drop threshold is supplied packets are dropped and their
1038  *      buffers recycled if (a) the number of remaining buffers is under the
1039  *      threshold and the packet is too big to copy, or (b) the packet should
1040  *      be copied but there is no memory for the copy.
1041  */
1042 static inline struct sk_buff *get_packet(struct pci_dev *pdev,
1043                                          struct freelQ *fl, unsigned int len)
1044 {
1045         struct sk_buff *skb;
1046         const struct freelQ_ce *ce = &fl->centries[fl->cidx];
1047
1048         if (len < copybreak) {
1049                 skb = alloc_skb(len + 2, GFP_ATOMIC);
1050                 if (!skb)
1051                         goto use_orig_buf;
1052
1053                 skb_reserve(skb, 2);    /* align IP header */
1054                 skb_put(skb, len);
1055                 pci_dma_sync_single_for_cpu(pdev,
1056                                             dma_unmap_addr(ce, dma_addr),
1057                                             dma_unmap_len(ce, dma_len),
1058                                             PCI_DMA_FROMDEVICE);
1059                 skb_copy_from_linear_data(ce->skb, skb->data, len);
1060                 pci_dma_sync_single_for_device(pdev,
1061                                                dma_unmap_addr(ce, dma_addr),
1062                                                dma_unmap_len(ce, dma_len),
1063                                                PCI_DMA_FROMDEVICE);
1064                 recycle_fl_buf(fl, fl->cidx);
1065                 return skb;
1066         }
1067
1068 use_orig_buf:
1069         if (fl->credits < 2) {
1070                 recycle_fl_buf(fl, fl->cidx);
1071                 return NULL;
1072         }
1073
1074         pci_unmap_single(pdev, dma_unmap_addr(ce, dma_addr),
1075                          dma_unmap_len(ce, dma_len), PCI_DMA_FROMDEVICE);
1076         skb = ce->skb;
1077         prefetch(skb->data);
1078
1079         skb_put(skb, len);
1080         return skb;
1081 }
1082
1083 /**
1084  *      unexpected_offload - handle an unexpected offload packet
1085  *      @adapter: the adapter
1086  *      @fl: the free list that received the packet
1087  *
1088  *      Called when we receive an unexpected offload packet (e.g., the TOE
1089  *      function is disabled or the card is a NIC).  Prints a message and
1090  *      recycles the buffer.
1091  */
1092 static void unexpected_offload(struct adapter *adapter, struct freelQ *fl)
1093 {
1094         struct freelQ_ce *ce = &fl->centries[fl->cidx];
1095         struct sk_buff *skb = ce->skb;
1096
1097         pci_dma_sync_single_for_cpu(adapter->pdev, dma_unmap_addr(ce, dma_addr),
1098                             dma_unmap_len(ce, dma_len), PCI_DMA_FROMDEVICE);
1099         pr_err("%s: unexpected offload packet, cmd %u\n",
1100                adapter->name, *skb->data);
1101         recycle_fl_buf(fl, fl->cidx);
1102 }
1103
1104 /*
1105  * T1/T2 SGE limits the maximum DMA size per TX descriptor to
1106  * SGE_TX_DESC_MAX_PLEN (16KB). If the PAGE_SIZE is larger than 16KB, the
1107  * stack might send more than SGE_TX_DESC_MAX_PLEN in a contiguous manner.
1108  * Note that the *_large_page_tx_descs stuff will be optimized out when
1109  * PAGE_SIZE <= SGE_TX_DESC_MAX_PLEN.
1110  *
1111  * compute_large_page_descs() computes how many additional descriptors are
1112  * required to break down the stack's request.
1113  */
1114 static inline unsigned int compute_large_page_tx_descs(struct sk_buff *skb)
1115 {
1116         unsigned int count = 0;
1117
1118         if (PAGE_SIZE > SGE_TX_DESC_MAX_PLEN) {
1119                 unsigned int nfrags = skb_shinfo(skb)->nr_frags;
1120                 unsigned int i, len = skb_headlen(skb);
1121                 while (len > SGE_TX_DESC_MAX_PLEN) {
1122                         count++;
1123                         len -= SGE_TX_DESC_MAX_PLEN;
1124                 }
1125                 for (i = 0; nfrags--; i++) {
1126                         const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1127                         len = skb_frag_size(frag);
1128                         while (len > SGE_TX_DESC_MAX_PLEN) {
1129                                 count++;
1130                                 len -= SGE_TX_DESC_MAX_PLEN;
1131                         }
1132                 }
1133         }
1134         return count;
1135 }
1136
1137 /*
1138  * Write a cmdQ entry.
1139  *
1140  * Since this function writes the 'flags' field, it must not be used to
1141  * write the first cmdQ entry.
1142  */
1143 static inline void write_tx_desc(struct cmdQ_e *e, dma_addr_t mapping,
1144                                  unsigned int len, unsigned int gen,
1145                                  unsigned int eop)
1146 {
1147         BUG_ON(len > SGE_TX_DESC_MAX_PLEN);
1148
1149         e->addr_lo = (u32)mapping;
1150         e->addr_hi = (u64)mapping >> 32;
1151         e->len_gen = V_CMD_LEN(len) | V_CMD_GEN1(gen);
1152         e->flags = F_CMD_DATAVALID | V_CMD_EOP(eop) | V_CMD_GEN2(gen);
1153 }
1154
1155 /*
1156  * See comment for previous function.
1157  *
1158  * write_tx_descs_large_page() writes additional SGE tx descriptors if
1159  * *desc_len exceeds HW's capability.
1160  */
1161 static inline unsigned int write_large_page_tx_descs(unsigned int pidx,
1162                                                      struct cmdQ_e **e,
1163                                                      struct cmdQ_ce **ce,
1164                                                      unsigned int *gen,
1165                                                      dma_addr_t *desc_mapping,
1166                                                      unsigned int *desc_len,
1167                                                      unsigned int nfrags,
1168                                                      struct cmdQ *q)
1169 {
1170         if (PAGE_SIZE > SGE_TX_DESC_MAX_PLEN) {
1171                 struct cmdQ_e *e1 = *e;
1172                 struct cmdQ_ce *ce1 = *ce;
1173
1174                 while (*desc_len > SGE_TX_DESC_MAX_PLEN) {
1175                         *desc_len -= SGE_TX_DESC_MAX_PLEN;
1176                         write_tx_desc(e1, *desc_mapping, SGE_TX_DESC_MAX_PLEN,
1177                                       *gen, nfrags == 0 && *desc_len == 0);
1178                         ce1->skb = NULL;
1179                         dma_unmap_len_set(ce1, dma_len, 0);
1180                         *desc_mapping += SGE_TX_DESC_MAX_PLEN;
1181                         if (*desc_len) {
1182                                 ce1++;
1183                                 e1++;
1184                                 if (++pidx == q->size) {
1185                                         pidx = 0;
1186                                         *gen ^= 1;
1187                                         ce1 = q->centries;
1188                                         e1 = q->entries;
1189                                 }
1190                         }
1191                 }
1192                 *e = e1;
1193                 *ce = ce1;
1194         }
1195         return pidx;
1196 }
1197
1198 /*
1199  * Write the command descriptors to transmit the given skb starting at
1200  * descriptor pidx with the given generation.
1201  */
1202 static inline void write_tx_descs(struct adapter *adapter, struct sk_buff *skb,
1203                                   unsigned int pidx, unsigned int gen,
1204                                   struct cmdQ *q)
1205 {
1206         dma_addr_t mapping, desc_mapping;
1207         struct cmdQ_e *e, *e1;
1208         struct cmdQ_ce *ce;
1209         unsigned int i, flags, first_desc_len, desc_len,
1210             nfrags = skb_shinfo(skb)->nr_frags;
1211
1212         e = e1 = &q->entries[pidx];
1213         ce = &q->centries[pidx];
1214
1215         mapping = pci_map_single(adapter->pdev, skb->data,
1216                                  skb_headlen(skb), PCI_DMA_TODEVICE);
1217
1218         desc_mapping = mapping;
1219         desc_len = skb_headlen(skb);
1220
1221         flags = F_CMD_DATAVALID | F_CMD_SOP |
1222             V_CMD_EOP(nfrags == 0 && desc_len <= SGE_TX_DESC_MAX_PLEN) |
1223             V_CMD_GEN2(gen);
1224         first_desc_len = (desc_len <= SGE_TX_DESC_MAX_PLEN) ?
1225             desc_len : SGE_TX_DESC_MAX_PLEN;
1226         e->addr_lo = (u32)desc_mapping;
1227         e->addr_hi = (u64)desc_mapping >> 32;
1228         e->len_gen = V_CMD_LEN(first_desc_len) | V_CMD_GEN1(gen);
1229         ce->skb = NULL;
1230         dma_unmap_len_set(ce, dma_len, 0);
1231
1232         if (PAGE_SIZE > SGE_TX_DESC_MAX_PLEN &&
1233             desc_len > SGE_TX_DESC_MAX_PLEN) {
1234                 desc_mapping += first_desc_len;
1235                 desc_len -= first_desc_len;
1236                 e1++;
1237                 ce++;
1238                 if (++pidx == q->size) {
1239                         pidx = 0;
1240                         gen ^= 1;
1241                         e1 = q->entries;
1242                         ce = q->centries;
1243                 }
1244                 pidx = write_large_page_tx_descs(pidx, &e1, &ce, &gen,
1245                                                  &desc_mapping, &desc_len,
1246                                                  nfrags, q);
1247
1248                 if (likely(desc_len))
1249                         write_tx_desc(e1, desc_mapping, desc_len, gen,
1250                                       nfrags == 0);
1251         }
1252
1253         ce->skb = NULL;
1254         dma_unmap_addr_set(ce, dma_addr, mapping);
1255         dma_unmap_len_set(ce, dma_len, skb_headlen(skb));
1256
1257         for (i = 0; nfrags--; i++) {
1258                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1259                 e1++;
1260                 ce++;
1261                 if (++pidx == q->size) {
1262                         pidx = 0;
1263                         gen ^= 1;
1264                         e1 = q->entries;
1265                         ce = q->centries;
1266                 }
1267
1268                 mapping = skb_frag_dma_map(&adapter->pdev->dev, frag, 0,
1269                                            skb_frag_size(frag), DMA_TO_DEVICE);
1270                 desc_mapping = mapping;
1271                 desc_len = skb_frag_size(frag);
1272
1273                 pidx = write_large_page_tx_descs(pidx, &e1, &ce, &gen,
1274                                                  &desc_mapping, &desc_len,
1275                                                  nfrags, q);
1276                 if (likely(desc_len))
1277                         write_tx_desc(e1, desc_mapping, desc_len, gen,
1278                                       nfrags == 0);
1279                 ce->skb = NULL;
1280                 dma_unmap_addr_set(ce, dma_addr, mapping);
1281                 dma_unmap_len_set(ce, dma_len, skb_frag_size(frag));
1282         }
1283         ce->skb = skb;
1284         wmb();
1285         e->flags = flags;
1286 }
1287
1288 /*
1289  * Clean up completed Tx buffers.
1290  */
1291 static inline void reclaim_completed_tx(struct sge *sge, struct cmdQ *q)
1292 {
1293         unsigned int reclaim = q->processed - q->cleaned;
1294
1295         if (reclaim) {
1296                 pr_debug("reclaim_completed_tx processed:%d cleaned:%d\n",
1297                          q->processed, q->cleaned);
1298                 free_cmdQ_buffers(sge, q, reclaim);
1299                 q->cleaned += reclaim;
1300         }
1301 }
1302
1303 /*
1304  * Called from tasklet. Checks the scheduler for any
1305  * pending skbs that can be sent.
1306  */
1307 static void restart_sched(unsigned long arg)
1308 {
1309         struct sge *sge = (struct sge *) arg;
1310         struct adapter *adapter = sge->adapter;
1311         struct cmdQ *q = &sge->cmdQ[0];
1312         struct sk_buff *skb;
1313         unsigned int credits, queued_skb = 0;
1314
1315         spin_lock(&q->lock);
1316         reclaim_completed_tx(sge, q);
1317
1318         credits = q->size - q->in_use;
1319         pr_debug("restart_sched credits=%d\n", credits);
1320         while ((skb = sched_skb(sge, NULL, credits)) != NULL) {
1321                 unsigned int genbit, pidx, count;
1322                 count = 1 + skb_shinfo(skb)->nr_frags;
1323                 count += compute_large_page_tx_descs(skb);
1324                 q->in_use += count;
1325                 genbit = q->genbit;
1326                 pidx = q->pidx;
1327                 q->pidx += count;
1328                 if (q->pidx >= q->size) {
1329                         q->pidx -= q->size;
1330                         q->genbit ^= 1;
1331                 }
1332                 write_tx_descs(adapter, skb, pidx, genbit, q);
1333                 credits = q->size - q->in_use;
1334                 queued_skb = 1;
1335         }
1336
1337         if (queued_skb) {
1338                 clear_bit(CMDQ_STAT_LAST_PKT_DB, &q->status);
1339                 if (test_and_set_bit(CMDQ_STAT_RUNNING, &q->status) == 0) {
1340                         set_bit(CMDQ_STAT_LAST_PKT_DB, &q->status);
1341                         writel(F_CMDQ0_ENABLE, adapter->regs + A_SG_DOORBELL);
1342                 }
1343         }
1344         spin_unlock(&q->lock);
1345 }
1346
1347 /**
1348  *      sge_rx - process an ingress ethernet packet
1349  *      @sge: the sge structure
1350  *      @fl: the free list that contains the packet buffer
1351  *      @len: the packet length
1352  *
1353  *      Process an ingress ethernet pakcet and deliver it to the stack.
1354  */
1355 static void sge_rx(struct sge *sge, struct freelQ *fl, unsigned int len)
1356 {
1357         struct sk_buff *skb;
1358         const struct cpl_rx_pkt *p;
1359         struct adapter *adapter = sge->adapter;
1360         struct sge_port_stats *st;
1361         struct net_device *dev;
1362
1363         skb = get_packet(adapter->pdev, fl, len - sge->rx_pkt_pad);
1364         if (unlikely(!skb)) {
1365                 sge->stats.rx_drops++;
1366                 return;
1367         }
1368
1369         p = (const struct cpl_rx_pkt *) skb->data;
1370         if (p->iff >= adapter->params.nports) {
1371                 kfree_skb(skb);
1372                 return;
1373         }
1374         __skb_pull(skb, sizeof(*p));
1375
1376         st = this_cpu_ptr(sge->port_stats[p->iff]);
1377         dev = adapter->port[p->iff].dev;
1378
1379         skb->protocol = eth_type_trans(skb, dev);
1380         if ((dev->features & NETIF_F_RXCSUM) && p->csum == 0xffff &&
1381             skb->protocol == htons(ETH_P_IP) &&
1382             (skb->data[9] == IPPROTO_TCP || skb->data[9] == IPPROTO_UDP)) {
1383                 ++st->rx_cso_good;
1384                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1385         } else
1386                 skb_checksum_none_assert(skb);
1387
1388         if (p->vlan_valid) {
1389                 st->vlan_xtract++;
1390                 __vlan_hwaccel_put_tag(skb, ntohs(p->vlan));
1391         }
1392         netif_receive_skb(skb);
1393 }
1394
1395 /*
1396  * Returns true if a command queue has enough available descriptors that
1397  * we can resume Tx operation after temporarily disabling its packet queue.
1398  */
1399 static inline int enough_free_Tx_descs(const struct cmdQ *q)
1400 {
1401         unsigned int r = q->processed - q->cleaned;
1402
1403         return q->in_use - r < (q->size >> 1);
1404 }
1405
1406 /*
1407  * Called when sufficient space has become available in the SGE command queues
1408  * after the Tx packet schedulers have been suspended to restart the Tx path.
1409  */
1410 static void restart_tx_queues(struct sge *sge)
1411 {
1412         struct adapter *adap = sge->adapter;
1413         int i;
1414
1415         if (!enough_free_Tx_descs(&sge->cmdQ[0]))
1416                 return;
1417
1418         for_each_port(adap, i) {
1419                 struct net_device *nd = adap->port[i].dev;
1420
1421                 if (test_and_clear_bit(nd->if_port, &sge->stopped_tx_queues) &&
1422                     netif_running(nd)) {
1423                         sge->stats.cmdQ_restarted[2]++;
1424                         netif_wake_queue(nd);
1425                 }
1426         }
1427 }
1428
1429 /*
1430  * update_tx_info is called from the interrupt handler/NAPI to return cmdQ0
1431  * information.
1432  */
1433 static unsigned int update_tx_info(struct adapter *adapter,
1434                                           unsigned int flags,
1435                                           unsigned int pr0)
1436 {
1437         struct sge *sge = adapter->sge;
1438         struct cmdQ *cmdq = &sge->cmdQ[0];
1439
1440         cmdq->processed += pr0;
1441         if (flags & (F_FL0_ENABLE | F_FL1_ENABLE)) {
1442                 freelQs_empty(sge);
1443                 flags &= ~(F_FL0_ENABLE | F_FL1_ENABLE);
1444         }
1445         if (flags & F_CMDQ0_ENABLE) {
1446                 clear_bit(CMDQ_STAT_RUNNING, &cmdq->status);
1447
1448                 if (cmdq->cleaned + cmdq->in_use != cmdq->processed &&
1449                     !test_and_set_bit(CMDQ_STAT_LAST_PKT_DB, &cmdq->status)) {
1450                         set_bit(CMDQ_STAT_RUNNING, &cmdq->status);
1451                         writel(F_CMDQ0_ENABLE, adapter->regs + A_SG_DOORBELL);
1452                 }
1453                 if (sge->tx_sched)
1454                         tasklet_hi_schedule(&sge->tx_sched->sched_tsk);
1455
1456                 flags &= ~F_CMDQ0_ENABLE;
1457         }
1458
1459         if (unlikely(sge->stopped_tx_queues != 0))
1460                 restart_tx_queues(sge);
1461
1462         return flags;
1463 }
1464
1465 /*
1466  * Process SGE responses, up to the supplied budget.  Returns the number of
1467  * responses processed.  A negative budget is effectively unlimited.
1468  */
1469 static int process_responses(struct adapter *adapter, int budget)
1470 {
1471         struct sge *sge = adapter->sge;
1472         struct respQ *q = &sge->respQ;
1473         struct respQ_e *e = &q->entries[q->cidx];
1474         int done = 0;
1475         unsigned int flags = 0;
1476         unsigned int cmdq_processed[SGE_CMDQ_N] = {0, 0};
1477
1478         while (done < budget && e->GenerationBit == q->genbit) {
1479                 flags |= e->Qsleeping;
1480
1481                 cmdq_processed[0] += e->Cmdq0CreditReturn;
1482                 cmdq_processed[1] += e->Cmdq1CreditReturn;
1483
1484                 /* We batch updates to the TX side to avoid cacheline
1485                  * ping-pong of TX state information on MP where the sender
1486                  * might run on a different CPU than this function...
1487                  */
1488                 if (unlikely((flags & F_CMDQ0_ENABLE) || cmdq_processed[0] > 64)) {
1489                         flags = update_tx_info(adapter, flags, cmdq_processed[0]);
1490                         cmdq_processed[0] = 0;
1491                 }
1492
1493                 if (unlikely(cmdq_processed[1] > 16)) {
1494                         sge->cmdQ[1].processed += cmdq_processed[1];
1495                         cmdq_processed[1] = 0;
1496                 }
1497
1498                 if (likely(e->DataValid)) {
1499                         struct freelQ *fl = &sge->freelQ[e->FreelistQid];
1500
1501                         BUG_ON(!e->Sop || !e->Eop);
1502                         if (unlikely(e->Offload))
1503                                 unexpected_offload(adapter, fl);
1504                         else
1505                                 sge_rx(sge, fl, e->BufferLength);
1506
1507                         ++done;
1508
1509                         /*
1510                          * Note: this depends on each packet consuming a
1511                          * single free-list buffer; cf. the BUG above.
1512                          */
1513                         if (++fl->cidx == fl->size)
1514                                 fl->cidx = 0;
1515                         prefetch(fl->centries[fl->cidx].skb);
1516
1517                         if (unlikely(--fl->credits <
1518                                      fl->size - SGE_FREEL_REFILL_THRESH))
1519                                 refill_free_list(sge, fl);
1520                 } else
1521                         sge->stats.pure_rsps++;
1522
1523                 e++;
1524                 if (unlikely(++q->cidx == q->size)) {
1525                         q->cidx = 0;
1526                         q->genbit ^= 1;
1527                         e = q->entries;
1528                 }
1529                 prefetch(e);
1530
1531                 if (++q->credits > SGE_RESPQ_REPLENISH_THRES) {
1532                         writel(q->credits, adapter->regs + A_SG_RSPQUEUECREDIT);
1533                         q->credits = 0;
1534                 }
1535         }
1536
1537         flags = update_tx_info(adapter, flags, cmdq_processed[0]);
1538         sge->cmdQ[1].processed += cmdq_processed[1];
1539
1540         return done;
1541 }
1542
1543 static inline int responses_pending(const struct adapter *adapter)
1544 {
1545         const struct respQ *Q = &adapter->sge->respQ;
1546         const struct respQ_e *e = &Q->entries[Q->cidx];
1547
1548         return e->GenerationBit == Q->genbit;
1549 }
1550
1551 /*
1552  * A simpler version of process_responses() that handles only pure (i.e.,
1553  * non data-carrying) responses.  Such respones are too light-weight to justify
1554  * calling a softirq when using NAPI, so we handle them specially in hard
1555  * interrupt context.  The function is called with a pointer to a response,
1556  * which the caller must ensure is a valid pure response.  Returns 1 if it
1557  * encounters a valid data-carrying response, 0 otherwise.
1558  */
1559 static int process_pure_responses(struct adapter *adapter)
1560 {
1561         struct sge *sge = adapter->sge;
1562         struct respQ *q = &sge->respQ;
1563         struct respQ_e *e = &q->entries[q->cidx];
1564         const struct freelQ *fl = &sge->freelQ[e->FreelistQid];
1565         unsigned int flags = 0;
1566         unsigned int cmdq_processed[SGE_CMDQ_N] = {0, 0};
1567
1568         prefetch(fl->centries[fl->cidx].skb);
1569         if (e->DataValid)
1570                 return 1;
1571
1572         do {
1573                 flags |= e->Qsleeping;
1574
1575                 cmdq_processed[0] += e->Cmdq0CreditReturn;
1576                 cmdq_processed[1] += e->Cmdq1CreditReturn;
1577
1578                 e++;
1579                 if (unlikely(++q->cidx == q->size)) {
1580                         q->cidx = 0;
1581                         q->genbit ^= 1;
1582                         e = q->entries;
1583                 }
1584                 prefetch(e);
1585
1586                 if (++q->credits > SGE_RESPQ_REPLENISH_THRES) {
1587                         writel(q->credits, adapter->regs + A_SG_RSPQUEUECREDIT);
1588                         q->credits = 0;
1589                 }
1590                 sge->stats.pure_rsps++;
1591         } while (e->GenerationBit == q->genbit && !e->DataValid);
1592
1593         flags = update_tx_info(adapter, flags, cmdq_processed[0]);
1594         sge->cmdQ[1].processed += cmdq_processed[1];
1595
1596         return e->GenerationBit == q->genbit;
1597 }
1598
1599 /*
1600  * Handler for new data events when using NAPI.  This does not need any locking
1601  * or protection from interrupts as data interrupts are off at this point and
1602  * other adapter interrupts do not interfere.
1603  */
1604 int t1_poll(struct napi_struct *napi, int budget)
1605 {
1606         struct adapter *adapter = container_of(napi, struct adapter, napi);
1607         int work_done = process_responses(adapter, budget);
1608
1609         if (likely(work_done < budget)) {
1610                 napi_complete(napi);
1611                 writel(adapter->sge->respQ.cidx,
1612                        adapter->regs + A_SG_SLEEPING);
1613         }
1614         return work_done;
1615 }
1616
1617 irqreturn_t t1_interrupt(int irq, void *data)
1618 {
1619         struct adapter *adapter = data;
1620         struct sge *sge = adapter->sge;
1621         int handled;
1622
1623         if (likely(responses_pending(adapter))) {
1624                 writel(F_PL_INTR_SGE_DATA, adapter->regs + A_PL_CAUSE);
1625
1626                 if (napi_schedule_prep(&adapter->napi)) {
1627                         if (process_pure_responses(adapter))
1628                                 __napi_schedule(&adapter->napi);
1629                         else {
1630                                 /* no data, no NAPI needed */
1631                                 writel(sge->respQ.cidx, adapter->regs + A_SG_SLEEPING);
1632                                 /* undo schedule_prep */
1633                                 napi_enable(&adapter->napi);
1634                         }
1635                 }
1636                 return IRQ_HANDLED;
1637         }
1638
1639         spin_lock(&adapter->async_lock);
1640         handled = t1_slow_intr_handler(adapter);
1641         spin_unlock(&adapter->async_lock);
1642
1643         if (!handled)
1644                 sge->stats.unhandled_irqs++;
1645
1646         return IRQ_RETVAL(handled != 0);
1647 }
1648
1649 /*
1650  * Enqueues the sk_buff onto the cmdQ[qid] and has hardware fetch it.
1651  *
1652  * The code figures out how many entries the sk_buff will require in the
1653  * cmdQ and updates the cmdQ data structure with the state once the enqueue
1654  * has complete. Then, it doesn't access the global structure anymore, but
1655  * uses the corresponding fields on the stack. In conjunction with a spinlock
1656  * around that code, we can make the function reentrant without holding the
1657  * lock when we actually enqueue (which might be expensive, especially on
1658  * architectures with IO MMUs).
1659  *
1660  * This runs with softirqs disabled.
1661  */
1662 static int t1_sge_tx(struct sk_buff *skb, struct adapter *adapter,
1663                      unsigned int qid, struct net_device *dev)
1664 {
1665         struct sge *sge = adapter->sge;
1666         struct cmdQ *q = &sge->cmdQ[qid];
1667         unsigned int credits, pidx, genbit, count, use_sched_skb = 0;
1668
1669         if (!spin_trylock(&q->lock))
1670                 return NETDEV_TX_LOCKED;
1671
1672         reclaim_completed_tx(sge, q);
1673
1674         pidx = q->pidx;
1675         credits = q->size - q->in_use;
1676         count = 1 + skb_shinfo(skb)->nr_frags;
1677         count += compute_large_page_tx_descs(skb);
1678
1679         /* Ethernet packet */
1680         if (unlikely(credits < count)) {
1681                 if (!netif_queue_stopped(dev)) {
1682                         netif_stop_queue(dev);
1683                         set_bit(dev->if_port, &sge->stopped_tx_queues);
1684                         sge->stats.cmdQ_full[2]++;
1685                         pr_err("%s: Tx ring full while queue awake!\n",
1686                                adapter->name);
1687                 }
1688                 spin_unlock(&q->lock);
1689                 return NETDEV_TX_BUSY;
1690         }
1691
1692         if (unlikely(credits - count < q->stop_thres)) {
1693                 netif_stop_queue(dev);
1694                 set_bit(dev->if_port, &sge->stopped_tx_queues);
1695                 sge->stats.cmdQ_full[2]++;
1696         }
1697
1698         /* T204 cmdQ0 skbs that are destined for a certain port have to go
1699          * through the scheduler.
1700          */
1701         if (sge->tx_sched && !qid && skb->dev) {
1702 use_sched:
1703                 use_sched_skb = 1;
1704                 /* Note that the scheduler might return a different skb than
1705                  * the one passed in.
1706                  */
1707                 skb = sched_skb(sge, skb, credits);
1708                 if (!skb) {
1709                         spin_unlock(&q->lock);
1710                         return NETDEV_TX_OK;
1711                 }
1712                 pidx = q->pidx;
1713                 count = 1 + skb_shinfo(skb)->nr_frags;
1714                 count += compute_large_page_tx_descs(skb);
1715         }
1716
1717         q->in_use += count;
1718         genbit = q->genbit;
1719         pidx = q->pidx;
1720         q->pidx += count;
1721         if (q->pidx >= q->size) {
1722                 q->pidx -= q->size;
1723                 q->genbit ^= 1;
1724         }
1725         spin_unlock(&q->lock);
1726
1727         write_tx_descs(adapter, skb, pidx, genbit, q);
1728
1729         /*
1730          * We always ring the doorbell for cmdQ1.  For cmdQ0, we only ring
1731          * the doorbell if the Q is asleep. There is a natural race, where
1732          * the hardware is going to sleep just after we checked, however,
1733          * then the interrupt handler will detect the outstanding TX packet
1734          * and ring the doorbell for us.
1735          */
1736         if (qid)
1737                 doorbell_pio(adapter, F_CMDQ1_ENABLE);
1738         else {
1739                 clear_bit(CMDQ_STAT_LAST_PKT_DB, &q->status);
1740                 if (test_and_set_bit(CMDQ_STAT_RUNNING, &q->status) == 0) {
1741                         set_bit(CMDQ_STAT_LAST_PKT_DB, &q->status);
1742                         writel(F_CMDQ0_ENABLE, adapter->regs + A_SG_DOORBELL);
1743                 }
1744         }
1745
1746         if (use_sched_skb) {
1747                 if (spin_trylock(&q->lock)) {
1748                         credits = q->size - q->in_use;
1749                         skb = NULL;
1750                         goto use_sched;
1751                 }
1752         }
1753         return NETDEV_TX_OK;
1754 }
1755
1756 #define MK_ETH_TYPE_MSS(type, mss) (((mss) & 0x3FFF) | ((type) << 14))
1757
1758 /*
1759  *      eth_hdr_len - return the length of an Ethernet header
1760  *      @data: pointer to the start of the Ethernet header
1761  *
1762  *      Returns the length of an Ethernet header, including optional VLAN tag.
1763  */
1764 static inline int eth_hdr_len(const void *data)
1765 {
1766         const struct ethhdr *e = data;
1767
1768         return e->h_proto == htons(ETH_P_8021Q) ? VLAN_ETH_HLEN : ETH_HLEN;
1769 }
1770
1771 /*
1772  * Adds the CPL header to the sk_buff and passes it to t1_sge_tx.
1773  */
1774 netdev_tx_t t1_start_xmit(struct sk_buff *skb, struct net_device *dev)
1775 {
1776         struct adapter *adapter = dev->ml_priv;
1777         struct sge *sge = adapter->sge;
1778         struct sge_port_stats *st = this_cpu_ptr(sge->port_stats[dev->if_port]);
1779         struct cpl_tx_pkt *cpl;
1780         struct sk_buff *orig_skb = skb;
1781         int ret;
1782
1783         if (skb->protocol == htons(ETH_P_CPL5))
1784                 goto send;
1785
1786         /*
1787          * We are using a non-standard hard_header_len.
1788          * Allocate more header room in the rare cases it is not big enough.
1789          */
1790         if (unlikely(skb_headroom(skb) < dev->hard_header_len - ETH_HLEN)) {
1791                 skb = skb_realloc_headroom(skb, sizeof(struct cpl_tx_pkt_lso));
1792                 ++st->tx_need_hdrroom;
1793                 dev_kfree_skb_any(orig_skb);
1794                 if (!skb)
1795                         return NETDEV_TX_OK;
1796         }
1797
1798         if (skb_shinfo(skb)->gso_size) {
1799                 int eth_type;
1800                 struct cpl_tx_pkt_lso *hdr;
1801
1802                 ++st->tx_tso;
1803
1804                 eth_type = skb_network_offset(skb) == ETH_HLEN ?
1805                         CPL_ETH_II : CPL_ETH_II_VLAN;
1806
1807                 hdr = (struct cpl_tx_pkt_lso *)skb_push(skb, sizeof(*hdr));
1808                 hdr->opcode = CPL_TX_PKT_LSO;
1809                 hdr->ip_csum_dis = hdr->l4_csum_dis = 0;
1810                 hdr->ip_hdr_words = ip_hdr(skb)->ihl;
1811                 hdr->tcp_hdr_words = tcp_hdr(skb)->doff;
1812                 hdr->eth_type_mss = htons(MK_ETH_TYPE_MSS(eth_type,
1813                                                           skb_shinfo(skb)->gso_size));
1814                 hdr->len = htonl(skb->len - sizeof(*hdr));
1815                 cpl = (struct cpl_tx_pkt *)hdr;
1816         } else {
1817                 /*
1818                  * Packets shorter than ETH_HLEN can break the MAC, drop them
1819                  * early.  Also, we may get oversized packets because some
1820                  * parts of the kernel don't handle our unusual hard_header_len
1821                  * right, drop those too.
1822                  */
1823                 if (unlikely(skb->len < ETH_HLEN ||
1824                              skb->len > dev->mtu + eth_hdr_len(skb->data))) {
1825                         pr_debug("%s: packet size %d hdr %d mtu%d\n", dev->name,
1826                                  skb->len, eth_hdr_len(skb->data), dev->mtu);
1827                         dev_kfree_skb_any(skb);
1828                         return NETDEV_TX_OK;
1829                 }
1830
1831                 if (skb->ip_summed == CHECKSUM_PARTIAL &&
1832                     ip_hdr(skb)->protocol == IPPROTO_UDP) {
1833                         if (unlikely(skb_checksum_help(skb))) {
1834                                 pr_debug("%s: unable to do udp checksum\n", dev->name);
1835                                 dev_kfree_skb_any(skb);
1836                                 return NETDEV_TX_OK;
1837                         }
1838                 }
1839
1840                 /* Hmmm, assuming to catch the gratious arp... and we'll use
1841                  * it to flush out stuck espi packets...
1842                  */
1843                 if ((unlikely(!adapter->sge->espibug_skb[dev->if_port]))) {
1844                         if (skb->protocol == htons(ETH_P_ARP) &&
1845                             arp_hdr(skb)->ar_op == htons(ARPOP_REQUEST)) {
1846                                 adapter->sge->espibug_skb[dev->if_port] = skb;
1847                                 /* We want to re-use this skb later. We
1848                                  * simply bump the reference count and it
1849                                  * will not be freed...
1850                                  */
1851                                 skb = skb_get(skb);
1852                         }
1853                 }
1854
1855                 cpl = (struct cpl_tx_pkt *)__skb_push(skb, sizeof(*cpl));
1856                 cpl->opcode = CPL_TX_PKT;
1857                 cpl->ip_csum_dis = 1;    /* SW calculates IP csum */
1858                 cpl->l4_csum_dis = skb->ip_summed == CHECKSUM_PARTIAL ? 0 : 1;
1859                 /* the length field isn't used so don't bother setting it */
1860
1861                 st->tx_cso += (skb->ip_summed == CHECKSUM_PARTIAL);
1862         }
1863         cpl->iff = dev->if_port;
1864
1865         if (vlan_tx_tag_present(skb)) {
1866                 cpl->vlan_valid = 1;
1867                 cpl->vlan = htons(vlan_tx_tag_get(skb));
1868                 st->vlan_insert++;
1869         } else
1870                 cpl->vlan_valid = 0;
1871
1872 send:
1873         ret = t1_sge_tx(skb, adapter, 0, dev);
1874
1875         /* If transmit busy, and we reallocated skb's due to headroom limit,
1876          * then silently discard to avoid leak.
1877          */
1878         if (unlikely(ret != NETDEV_TX_OK && skb != orig_skb)) {
1879                 dev_kfree_skb_any(skb);
1880                 ret = NETDEV_TX_OK;
1881         }
1882         return ret;
1883 }
1884
1885 /*
1886  * Callback for the Tx buffer reclaim timer.  Runs with softirqs disabled.
1887  */
1888 static void sge_tx_reclaim_cb(unsigned long data)
1889 {
1890         int i;
1891         struct sge *sge = (struct sge *)data;
1892
1893         for (i = 0; i < SGE_CMDQ_N; ++i) {
1894                 struct cmdQ *q = &sge->cmdQ[i];
1895
1896                 if (!spin_trylock(&q->lock))
1897                         continue;
1898
1899                 reclaim_completed_tx(sge, q);
1900                 if (i == 0 && q->in_use) {    /* flush pending credits */
1901                         writel(F_CMDQ0_ENABLE, sge->adapter->regs + A_SG_DOORBELL);
1902                 }
1903                 spin_unlock(&q->lock);
1904         }
1905         mod_timer(&sge->tx_reclaim_timer, jiffies + TX_RECLAIM_PERIOD);
1906 }
1907
1908 /*
1909  * Propagate changes of the SGE coalescing parameters to the HW.
1910  */
1911 int t1_sge_set_coalesce_params(struct sge *sge, struct sge_params *p)
1912 {
1913         sge->fixed_intrtimer = p->rx_coalesce_usecs *
1914                 core_ticks_per_usec(sge->adapter);
1915         writel(sge->fixed_intrtimer, sge->adapter->regs + A_SG_INTRTIMER);
1916         return 0;
1917 }
1918
1919 /*
1920  * Allocates both RX and TX resources and configures the SGE. However,
1921  * the hardware is not enabled yet.
1922  */
1923 int t1_sge_configure(struct sge *sge, struct sge_params *p)
1924 {
1925         if (alloc_rx_resources(sge, p))
1926                 return -ENOMEM;
1927         if (alloc_tx_resources(sge, p)) {
1928                 free_rx_resources(sge);
1929                 return -ENOMEM;
1930         }
1931         configure_sge(sge, p);
1932
1933         /*
1934          * Now that we have sized the free lists calculate the payload
1935          * capacity of the large buffers.  Other parts of the driver use
1936          * this to set the max offload coalescing size so that RX packets
1937          * do not overflow our large buffers.
1938          */
1939         p->large_buf_capacity = jumbo_payload_capacity(sge);
1940         return 0;
1941 }
1942
1943 /*
1944  * Disables the DMA engine.
1945  */
1946 void t1_sge_stop(struct sge *sge)
1947 {
1948         int i;
1949         writel(0, sge->adapter->regs + A_SG_CONTROL);
1950         readl(sge->adapter->regs + A_SG_CONTROL); /* flush */
1951
1952         if (is_T2(sge->adapter))
1953                 del_timer_sync(&sge->espibug_timer);
1954
1955         del_timer_sync(&sge->tx_reclaim_timer);
1956         if (sge->tx_sched)
1957                 tx_sched_stop(sge);
1958
1959         for (i = 0; i < MAX_NPORTS; i++)
1960                 kfree_skb(sge->espibug_skb[i]);
1961 }
1962
1963 /*
1964  * Enables the DMA engine.
1965  */
1966 void t1_sge_start(struct sge *sge)
1967 {
1968         refill_free_list(sge, &sge->freelQ[0]);
1969         refill_free_list(sge, &sge->freelQ[1]);
1970
1971         writel(sge->sge_control, sge->adapter->regs + A_SG_CONTROL);
1972         doorbell_pio(sge->adapter, F_FL0_ENABLE | F_FL1_ENABLE);
1973         readl(sge->adapter->regs + A_SG_CONTROL); /* flush */
1974
1975         mod_timer(&sge->tx_reclaim_timer, jiffies + TX_RECLAIM_PERIOD);
1976
1977         if (is_T2(sge->adapter))
1978                 mod_timer(&sge->espibug_timer, jiffies + sge->espibug_timeout);
1979 }
1980
1981 /*
1982  * Callback for the T2 ESPI 'stuck packet feature' workaorund
1983  */
1984 static void espibug_workaround_t204(unsigned long data)
1985 {
1986         struct adapter *adapter = (struct adapter *)data;
1987         struct sge *sge = adapter->sge;
1988         unsigned int nports = adapter->params.nports;
1989         u32 seop[MAX_NPORTS];
1990
1991         if (adapter->open_device_map & PORT_MASK) {
1992                 int i;
1993
1994                 if (t1_espi_get_mon_t204(adapter, &(seop[0]), 0) < 0)
1995                         return;
1996
1997                 for (i = 0; i < nports; i++) {
1998                         struct sk_buff *skb = sge->espibug_skb[i];
1999
2000                         if (!netif_running(adapter->port[i].dev) ||
2001                             netif_queue_stopped(adapter->port[i].dev) ||
2002                             !seop[i] || ((seop[i] & 0xfff) != 0) || !skb)
2003                                 continue;
2004
2005                         if (!skb->cb[0]) {
2006                                 skb_copy_to_linear_data_offset(skb,
2007                                                     sizeof(struct cpl_tx_pkt),
2008                                                                ch_mac_addr,
2009                                                                ETH_ALEN);
2010                                 skb_copy_to_linear_data_offset(skb,
2011                                                                skb->len - 10,
2012                                                                ch_mac_addr,
2013                                                                ETH_ALEN);
2014                                 skb->cb[0] = 0xff;
2015                         }
2016
2017                         /* bump the reference count to avoid freeing of
2018                          * the skb once the DMA has completed.
2019                          */
2020                         skb = skb_get(skb);
2021                         t1_sge_tx(skb, adapter, 0, adapter->port[i].dev);
2022                 }
2023         }
2024         mod_timer(&sge->espibug_timer, jiffies + sge->espibug_timeout);
2025 }
2026
2027 static void espibug_workaround(unsigned long data)
2028 {
2029         struct adapter *adapter = (struct adapter *)data;
2030         struct sge *sge = adapter->sge;
2031
2032         if (netif_running(adapter->port[0].dev)) {
2033                 struct sk_buff *skb = sge->espibug_skb[0];
2034                 u32 seop = t1_espi_get_mon(adapter, 0x930, 0);
2035
2036                 if ((seop & 0xfff0fff) == 0xfff && skb) {
2037                         if (!skb->cb[0]) {
2038                                 skb_copy_to_linear_data_offset(skb,
2039                                                      sizeof(struct cpl_tx_pkt),
2040                                                                ch_mac_addr,
2041                                                                ETH_ALEN);
2042                                 skb_copy_to_linear_data_offset(skb,
2043                                                                skb->len - 10,
2044                                                                ch_mac_addr,
2045                                                                ETH_ALEN);
2046                                 skb->cb[0] = 0xff;
2047                         }
2048
2049                         /* bump the reference count to avoid freeing of the
2050                          * skb once the DMA has completed.
2051                          */
2052                         skb = skb_get(skb);
2053                         t1_sge_tx(skb, adapter, 0, adapter->port[0].dev);
2054                 }
2055         }
2056         mod_timer(&sge->espibug_timer, jiffies + sge->espibug_timeout);
2057 }
2058
2059 /*
2060  * Creates a t1_sge structure and returns suggested resource parameters.
2061  */
2062 struct sge *t1_sge_create(struct adapter *adapter,
2063                                      struct sge_params *p)
2064 {
2065         struct sge *sge = kzalloc(sizeof(*sge), GFP_KERNEL);
2066         int i;
2067
2068         if (!sge)
2069                 return NULL;
2070
2071         sge->adapter = adapter;
2072         sge->netdev = adapter->port[0].dev;
2073         sge->rx_pkt_pad = t1_is_T1B(adapter) ? 0 : 2;
2074         sge->jumbo_fl = t1_is_T1B(adapter) ? 1 : 0;
2075
2076         for_each_port(adapter, i) {
2077                 sge->port_stats[i] = alloc_percpu(struct sge_port_stats);
2078                 if (!sge->port_stats[i])
2079                         goto nomem_port;
2080         }
2081
2082         init_timer(&sge->tx_reclaim_timer);
2083         sge->tx_reclaim_timer.data = (unsigned long)sge;
2084         sge->tx_reclaim_timer.function = sge_tx_reclaim_cb;
2085
2086         if (is_T2(sge->adapter)) {
2087                 init_timer(&sge->espibug_timer);
2088
2089                 if (adapter->params.nports > 1) {
2090                         tx_sched_init(sge);
2091                         sge->espibug_timer.function = espibug_workaround_t204;
2092                 } else
2093                         sge->espibug_timer.function = espibug_workaround;
2094                 sge->espibug_timer.data = (unsigned long)sge->adapter;
2095
2096                 sge->espibug_timeout = 1;
2097                 /* for T204, every 10ms */
2098                 if (adapter->params.nports > 1)
2099                         sge->espibug_timeout = HZ/100;
2100         }
2101
2102
2103         p->cmdQ_size[0] = SGE_CMDQ0_E_N;
2104         p->cmdQ_size[1] = SGE_CMDQ1_E_N;
2105         p->freelQ_size[!sge->jumbo_fl] = SGE_FREEL_SIZE;
2106         p->freelQ_size[sge->jumbo_fl] = SGE_JUMBO_FREEL_SIZE;
2107         if (sge->tx_sched) {
2108                 if (board_info(sge->adapter)->board == CHBT_BOARD_CHT204)
2109                         p->rx_coalesce_usecs = 15;
2110                 else
2111                         p->rx_coalesce_usecs = 50;
2112         } else
2113                 p->rx_coalesce_usecs = 50;
2114
2115         p->coalesce_enable = 0;
2116         p->sample_interval_usecs = 0;
2117
2118         return sge;
2119 nomem_port:
2120         while (i >= 0) {
2121                 free_percpu(sge->port_stats[i]);
2122                 --i;
2123         }
2124         kfree(sge);
2125         return NULL;
2126
2127 }