2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2010 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
38 #include <linux/types.h>
41 CPL_PASS_OPEN_REQ = 0x1,
42 CPL_PASS_ACCEPT_RPL = 0x2,
43 CPL_ACT_OPEN_REQ = 0x3,
44 CPL_SET_TCB_FIELD = 0x5,
46 CPL_CLOSE_CON_REQ = 0x8,
47 CPL_CLOSE_LISTSRV_REQ = 0x9,
50 CPL_RX_DATA_ACK = 0xD,
52 CPL_L2T_WRITE_REQ = 0x12,
53 CPL_TID_RELEASE = 0x1A,
55 CPL_CLOSE_LISTSRV_RPL = 0x20,
56 CPL_L2T_WRITE_RPL = 0x23,
57 CPL_PASS_OPEN_RPL = 0x24,
58 CPL_ACT_OPEN_RPL = 0x25,
59 CPL_PEER_CLOSE = 0x26,
60 CPL_ABORT_REQ_RSS = 0x2B,
61 CPL_ABORT_RPL_RSS = 0x2D,
63 CPL_CLOSE_CON_RPL = 0x32,
66 CPL_RDMA_CQE_READ_RSP = 0x36,
67 CPL_RDMA_CQE_ERR = 0x37,
69 CPL_SET_TCB_RPL = 0x3A,
71 CPL_RX_DDP_COMPLETE = 0x3F,
73 CPL_ACT_ESTABLISH = 0x40,
74 CPL_PASS_ESTABLISH = 0x41,
75 CPL_RX_DATA_DDP = 0x42,
76 CPL_PASS_ACCEPT_REQ = 0x44,
77 CPL_TRACE_PKT_T5 = 0x48,
79 CPL_RDMA_READ_REQ = 0x60,
81 CPL_PASS_OPEN_REQ6 = 0x81,
82 CPL_ACT_OPEN_REQ6 = 0x83,
84 CPL_RDMA_TERMINATE = 0xA2,
85 CPL_RDMA_WRITE = 0xA4,
86 CPL_SGE_EGR_UPDATE = 0xA5,
96 CPL_TX_PKT_LSO = 0xED,
104 CPL_ERR_TCAM_FULL = 3,
105 CPL_ERR_BAD_LENGTH = 15,
106 CPL_ERR_BAD_ROUTE = 18,
107 CPL_ERR_CONN_RESET = 20,
108 CPL_ERR_CONN_EXIST_SYNRECV = 21,
109 CPL_ERR_CONN_EXIST = 22,
110 CPL_ERR_ARP_MISS = 23,
111 CPL_ERR_BAD_SYN = 24,
112 CPL_ERR_CONN_TIMEDOUT = 30,
113 CPL_ERR_XMIT_TIMEDOUT = 31,
114 CPL_ERR_PERSIST_TIMEDOUT = 32,
115 CPL_ERR_FINWAIT2_TIMEDOUT = 33,
116 CPL_ERR_KEEPALIVE_TIMEDOUT = 34,
117 CPL_ERR_RTX_NEG_ADVICE = 35,
118 CPL_ERR_PERSIST_NEG_ADVICE = 36,
119 CPL_ERR_KEEPALV_NEG_ADVICE = 37,
120 CPL_ERR_ABORT_FAILED = 42,
121 CPL_ERR_IWARP_FLM = 50,
133 ULP_CRC_HEADER = 1 << 0,
134 ULP_CRC_DATA = 1 << 1
138 CPL_ABORT_SEND_RST = 0,
142 enum { /* TX_PKT_XT checksum types */
161 #define CPL_OPCODE(x) ((x) << 24)
162 #define G_CPL_OPCODE(x) (((x) >> 24) & 0xFF)
163 #define MK_OPCODE_TID(opcode, tid) (CPL_OPCODE(opcode) | (tid))
164 #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid)
165 #define GET_TID(cmd) (ntohl(OPCODE_TID(cmd)) & 0xFFFFFF)
167 /* partitioning of TID fields that also carry a queue id */
168 #define GET_TID_TID(x) ((x) & 0x3fff)
169 #define GET_TID_QID(x) (((x) >> 14) & 0x3ff)
170 #define TID_QID(x) ((x) << 14)
174 #if defined(__LITTLE_ENDIAN_BITFIELD)
193 struct work_request_hdr {
201 #define V_WR_OP(x) ((__u64)(x) << S_WR_OP)
203 #define WR_HDR struct work_request_hdr wr
205 /* option 0 fields */
207 #define M_MSS_IDX 0xF
208 #define V_MSS_IDX(x) ((__u64)(x) << S_MSS_IDX)
209 #define G_MSS_IDX(x) (((x) >> S_MSS_IDX) & M_MSS_IDX)
211 /* option 2 fields */
212 #define S_RSS_QUEUE 0
213 #define M_RSS_QUEUE 0x3FF
214 #define V_RSS_QUEUE(x) ((x) << S_RSS_QUEUE)
215 #define G_RSS_QUEUE(x) (((x) >> S_RSS_QUEUE) & M_RSS_QUEUE)
217 struct cpl_pass_open_req {
225 #define TX_CHAN(x) ((x) << 2)
226 #define NO_CONG(x) ((x) << 4)
227 #define DELACK(x) ((x) << 5)
228 #define ULP_MODE(x) ((x) << 8)
229 #define RCV_BUFSIZ(x) ((x) << 12)
230 #define DSCP(x) ((x) << 22)
231 #define SMAC_SEL(x) ((u64)(x) << 28)
232 #define L2T_IDX(x) ((u64)(x) << 36)
233 #define TCAM_BYPASS(x) ((u64)(x) << 48)
234 #define NAGLE(x) ((u64)(x) << 49)
235 #define WND_SCALE(x) ((u64)(x) << 50)
236 #define KEEP_ALIVE(x) ((u64)(x) << 54)
237 #define MSS_IDX(x) ((u64)(x) << 60)
239 #define SYN_RSS_ENABLE (1 << 0)
240 #define SYN_RSS_QUEUE(x) ((x) << 2)
241 #define CONN_POLICY_ASK (1 << 22)
244 struct cpl_pass_open_req6 {
257 struct cpl_pass_open_rpl {
263 struct cpl_pass_accept_rpl {
267 #define RSS_QUEUE(x) ((x) << 0)
268 #define RSS_QUEUE_VALID (1 << 10)
269 #define RX_COALESCE_VALID(x) ((x) << 11)
270 #define RX_COALESCE(x) ((x) << 12)
271 #define PACE(x) ((x) << 16)
272 #define TX_QUEUE(x) ((x) << 23)
273 #define RX_CHANNEL(x) ((x) << 26)
274 #define CCTRL_ECN(x) ((x) << 27)
275 #define WND_SCALE_EN(x) ((x) << 28)
276 #define TSTAMPS_EN(x) ((x) << 29)
277 #define SACK_EN(x) ((x) << 30)
281 struct cpl_act_open_req {
293 #define S_FILTER_TUPLE 24
294 #define M_FILTER_TUPLE 0xFFFFFFFFFF
295 #define V_FILTER_TUPLE(x) ((x) << S_FILTER_TUPLE)
296 #define G_FILTER_TUPLE(x) (((x) >> S_FILTER_TUPLE) & M_FILTER_TUPLE)
297 struct cpl_t5_act_open_req {
310 struct cpl_act_open_req6 {
324 struct cpl_t5_act_open_req6 {
339 struct cpl_act_open_rpl {
342 #define GET_AOPEN_STATUS(x) ((x) & 0xff)
343 #define GET_AOPEN_ATID(x) (((x) >> 8) & 0xffffff)
346 struct cpl_pass_establish {
350 #define PASS_OPEN_TID(x) ((x) << 0)
351 #define PASS_OPEN_TOS(x) ((x) << 24)
352 #define GET_PASS_OPEN_TID(x) (((x) >> 0) & 0xFFFFFF)
353 #define GET_POPEN_TID(x) ((x) & 0xffffff)
354 #define GET_POPEN_TOS(x) (((x) >> 24) & 0xff)
357 #define GET_TCPOPT_WSCALE_OK(x) (((x) >> 5) & 1)
358 #define GET_TCPOPT_SACK(x) (((x) >> 6) & 1)
359 #define GET_TCPOPT_TSTAMP(x) (((x) >> 7) & 1)
360 #define GET_TCPOPT_SND_WSCALE(x) (((x) >> 8) & 0xf)
361 #define GET_TCPOPT_MSS(x) (((x) >> 12) & 0xf)
366 struct cpl_act_establish {
380 #define QUEUENO(x) ((x) << 0)
381 #define REPLY_CHAN(x) ((x) << 14)
382 #define NO_REPLY(x) ((x) << 15)
386 struct cpl_set_tcb_field {
391 #define TCB_WORD(x) ((x) << 0)
392 #define TCB_COOKIE(x) ((x) << 5)
393 #define GET_TCB_COOKIE(x) (((x) >> 5) & 7)
398 struct cpl_set_tcb_rpl {
406 struct cpl_close_con_req {
412 struct cpl_close_con_rpl {
420 struct cpl_close_listsvr_req {
424 #define LISTSVR_IPV6(x) ((x) << 14)
428 struct cpl_close_listsvr_rpl {
434 struct cpl_abort_req_rss {
440 struct cpl_abort_req {
449 struct cpl_abort_rpl_rss {
455 struct cpl_abort_rpl {
464 struct cpl_peer_close {
469 struct cpl_tid_release {
475 struct cpl_tx_pkt_core {
477 #define TXPKT_VF(x) ((x) << 0)
478 #define TXPKT_PF(x) ((x) << 8)
479 #define TXPKT_VF_VLD (1 << 11)
480 #define TXPKT_OVLAN_IDX(x) ((x) << 12)
481 #define TXPKT_INTF(x) ((x) << 16)
482 #define TXPKT_INS_OVLAN (1 << 21)
483 #define TXPKT_OPCODE(x) ((x) << 24)
487 #define TXPKT_CSUM_END(x) ((x) << 12)
488 #define TXPKT_CSUM_START(x) ((x) << 20)
489 #define TXPKT_IPHDR_LEN(x) ((u64)(x) << 20)
490 #define TXPKT_CSUM_LOC(x) ((u64)(x) << 30)
491 #define TXPKT_ETHHDR_LEN(x) ((u64)(x) << 34)
492 #define TXPKT_CSUM_TYPE(x) ((u64)(x) << 40)
493 #define TXPKT_VLAN(x) ((u64)(x) << 44)
494 #define TXPKT_VLAN_VLD (1ULL << 60)
495 #define TXPKT_IPCSUM_DIS (1ULL << 62)
496 #define TXPKT_L4CSUM_DIS (1ULL << 63)
501 struct cpl_tx_pkt_core c;
504 #define cpl_tx_pkt_xt cpl_tx_pkt
506 struct cpl_tx_pkt_lso_core {
508 #define LSO_TCPHDR_LEN(x) ((x) << 0)
509 #define LSO_IPHDR_LEN(x) ((x) << 4)
510 #define LSO_ETHHDR_LEN(x) ((x) << 16)
511 #define LSO_IPV6(x) ((x) << 20)
512 #define LSO_LAST_SLICE (1 << 22)
513 #define LSO_FIRST_SLICE (1 << 23)
514 #define LSO_OPCODE(x) ((x) << 24)
519 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */
522 struct cpl_tx_pkt_lso {
524 struct cpl_tx_pkt_lso_core c;
525 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */
528 struct cpl_iscsi_hdr {
531 #define ISCSI_PDU_LEN(x) ((x) & 0x7FFF)
532 #define ISCSI_DDP (1 << 15)
546 #if defined(__LITTLE_ENDIAN_BITFIELD)
562 struct cpl_rx_data_ack {
566 #define RX_CREDITS(x) ((x) << 0)
567 #define RX_FORCE_ACK(x) ((x) << 28)
571 struct rss_header rsshdr;
573 #if defined(__LITTLE_ENDIAN_BITFIELD)
590 #define RXF_UDP (1 << 22)
591 #define RXF_TCP (1 << 23)
592 #define RXF_IP (1 << 24)
593 #define RXF_IP6 (1 << 25)
598 /* rx_pkt.l2info fields */
599 #define S_RX_ETHHDR_LEN 0
600 #define M_RX_ETHHDR_LEN 0x1F
601 #define V_RX_ETHHDR_LEN(x) ((x) << S_RX_ETHHDR_LEN)
602 #define G_RX_ETHHDR_LEN(x) (((x) >> S_RX_ETHHDR_LEN) & M_RX_ETHHDR_LEN)
604 #define S_RX_T5_ETHHDR_LEN 0
605 #define M_RX_T5_ETHHDR_LEN 0x3F
606 #define V_RX_T5_ETHHDR_LEN(x) ((x) << S_RX_T5_ETHHDR_LEN)
607 #define G_RX_T5_ETHHDR_LEN(x) (((x) >> S_RX_T5_ETHHDR_LEN) & M_RX_T5_ETHHDR_LEN)
609 #define S_RX_MACIDX 8
610 #define M_RX_MACIDX 0x1FF
611 #define V_RX_MACIDX(x) ((x) << S_RX_MACIDX)
612 #define G_RX_MACIDX(x) (((x) >> S_RX_MACIDX) & M_RX_MACIDX)
615 #define V_RXF_SYN(x) ((x) << S_RXF_SYN)
616 #define F_RXF_SYN V_RXF_SYN(1U)
619 #define M_RX_CHAN 0xF
620 #define V_RX_CHAN(x) ((x) << S_RX_CHAN)
621 #define G_RX_CHAN(x) (((x) >> S_RX_CHAN) & M_RX_CHAN)
623 /* rx_pkt.hdr_len fields */
624 #define S_RX_TCPHDR_LEN 0
625 #define M_RX_TCPHDR_LEN 0x3F
626 #define V_RX_TCPHDR_LEN(x) ((x) << S_RX_TCPHDR_LEN)
627 #define G_RX_TCPHDR_LEN(x) (((x) >> S_RX_TCPHDR_LEN) & M_RX_TCPHDR_LEN)
629 #define S_RX_IPHDR_LEN 6
630 #define M_RX_IPHDR_LEN 0x3FF
631 #define V_RX_IPHDR_LEN(x) ((x) << S_RX_IPHDR_LEN)
632 #define G_RX_IPHDR_LEN(x) (((x) >> S_RX_IPHDR_LEN) & M_RX_IPHDR_LEN)
634 struct cpl_trace_pkt {
637 #if defined(__LITTLE_ENDIAN_BITFIELD)
655 struct cpl_t5_trace_pkt {
658 #if defined(__LITTLE_ENDIAN_BITFIELD)
677 struct cpl_l2t_write_req {
681 #define L2T_W_INFO(x) ((x) << 2)
682 #define L2T_W_PORT(x) ((x) << 8)
683 #define L2T_W_NOREPLY(x) ((x) << 15)
689 struct cpl_l2t_write_rpl {
695 struct cpl_rdma_terminate {
701 struct cpl_sge_egr_update {
703 #define EGR_QID(x) ((x) & 0x1FFFF)
708 /* cpl_fw*.type values */
713 FW_TYPE_OFLD_CONNECTION_WR_RPL = 3,
760 /* cpl_fw6_msg.type values */
762 FW6_TYPE_CMD_RPL = 0,
765 FW6_TYPE_OFLD_CONNECTION_WR_RPL = 3,
766 FW6_TYPE_RSSCPL = FW_TYPE_RSSCPL,
769 struct cpl_fw6_msg_ofld_connection_wr_rpl {
771 __be32 tid; /* or atid in case of active failure */
779 ULP_TX_MEM_WRITE = 3,
784 ULP_TX_SC_NOOP = 0x80,
785 ULP_TX_SC_IMM = 0x81,
786 ULP_TX_SC_DSGL = 0x82,
787 ULP_TX_SC_ISGL = 0x83
790 struct ulptx_sge_pair {
797 #define ULPTX_CMD(x) ((x) << 24)
798 #define ULPTX_NSGE(x) ((x) << 0)
799 #define ULPTX_MORE (1U << 23)
802 struct ulptx_sge_pair sge[0];
808 #define ULP_MEMIO_ORDER(x) ((x) << 23)
809 __be32 len16; /* command length */
810 __be32 dlen; /* data length in 32-byte units */
811 #define ULP_MEMIO_DATA_LEN(x) ((x) << 0)
813 #define ULP_MEMIO_ADDR(x) ((x) << 0)
814 #define ULP_MEMIO_LOCK(x) ((x) << 31)
817 #define S_T5_ULP_MEMIO_IMM 23
818 #define V_T5_ULP_MEMIO_IMM(x) ((x) << S_T5_ULP_MEMIO_IMM)
819 #define F_T5_ULP_MEMIO_IMM V_T5_ULP_MEMIO_IMM(1U)
821 #define S_T5_ULP_MEMIO_ORDER 22
822 #define V_T5_ULP_MEMIO_ORDER(x) ((x) << S_T5_ULP_MEMIO_ORDER)
823 #define F_T5_ULP_MEMIO_ORDER V_T5_ULP_MEMIO_ORDER(1U)
825 #endif /* __T4_MSG_H */