2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
38 #define MYPF_BASE 0x1b000
39 #define MYPF_REG(reg_addr) (MYPF_BASE + (reg_addr))
41 #define PF0_BASE 0x1e000
42 #define PF0_REG(reg_addr) (PF0_BASE + (reg_addr))
44 #define PF_STRIDE 0x400
45 #define PF_BASE(idx) (PF0_BASE + (idx) * PF_STRIDE)
46 #define PF_REG(idx, reg) (PF_BASE(idx) + (reg))
48 #define MYPORT_BASE 0x1c000
49 #define MYPORT_REG(reg_addr) (MYPORT_BASE + (reg_addr))
51 #define PORT0_BASE 0x20000
52 #define PORT0_REG(reg_addr) (PORT0_BASE + (reg_addr))
54 #define PORT_STRIDE 0x2000
55 #define PORT_BASE(idx) (PORT0_BASE + (idx) * PORT_STRIDE)
56 #define PORT_REG(idx, reg) (PORT_BASE(idx) + (reg))
58 #define EDC_STRIDE (EDC_1_BASE_ADDR - EDC_0_BASE_ADDR)
59 #define EDC_REG(reg, idx) (reg + EDC_STRIDE * idx)
61 #define PCIE_MEM_ACCESS_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
62 #define PCIE_MAILBOX_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
63 #define MC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
64 #define EDC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
66 #define SGE_PF_KDOORBELL 0x0
67 #define QID_MASK 0xffff8000U
69 #define QID(x) ((x) << QID_SHIFT)
70 #define DBPRIO(x) ((x) << 14)
71 #define DBTYPE(x) ((x) << 13)
72 #define PIDX_MASK 0x00003fffU
74 #define PIDX(x) ((x) << PIDX_SHIFT)
75 #define PIDX_SHIFT_T5 0
76 #define PIDX_T5(x) ((x) << PIDX_SHIFT_T5)
79 #define SGE_TIMERREGS 6
80 #define SGE_PF_GTS 0x4
81 #define INGRESSQID_MASK 0xffff0000U
82 #define INGRESSQID_SHIFT 16
83 #define INGRESSQID(x) ((x) << INGRESSQID_SHIFT)
84 #define TIMERREG_MASK 0x0000e000U
85 #define TIMERREG_SHIFT 13
86 #define TIMERREG(x) ((x) << TIMERREG_SHIFT)
87 #define SEINTARM_MASK 0x00001000U
88 #define SEINTARM_SHIFT 12
89 #define SEINTARM(x) ((x) << SEINTARM_SHIFT)
90 #define CIDXINC_MASK 0x00000fffU
91 #define CIDXINC_SHIFT 0
92 #define CIDXINC(x) ((x) << CIDXINC_SHIFT)
94 #define X_RXPKTCPLMODE_SPLIT 1
95 #define X_INGPADBOUNDARY_SHIFT 5
97 #define SGE_CONTROL 0x1008
98 #define DCASYSTYPE 0x00080000U
99 #define RXPKTCPLMODE_MASK 0x00040000U
100 #define RXPKTCPLMODE_SHIFT 18
101 #define RXPKTCPLMODE(x) ((x) << RXPKTCPLMODE_SHIFT)
102 #define EGRSTATUSPAGESIZE_MASK 0x00020000U
103 #define EGRSTATUSPAGESIZE_SHIFT 17
104 #define EGRSTATUSPAGESIZE(x) ((x) << EGRSTATUSPAGESIZE_SHIFT)
105 #define PKTSHIFT_MASK 0x00001c00U
106 #define PKTSHIFT_SHIFT 10
107 #define PKTSHIFT(x) ((x) << PKTSHIFT_SHIFT)
108 #define PKTSHIFT_GET(x) (((x) & PKTSHIFT_MASK) >> PKTSHIFT_SHIFT)
109 #define INGPCIEBOUNDARY_MASK 0x00000380U
110 #define INGPCIEBOUNDARY_SHIFT 7
111 #define INGPCIEBOUNDARY(x) ((x) << INGPCIEBOUNDARY_SHIFT)
112 #define INGPADBOUNDARY_MASK 0x00000070U
113 #define INGPADBOUNDARY_SHIFT 4
114 #define INGPADBOUNDARY(x) ((x) << INGPADBOUNDARY_SHIFT)
115 #define INGPADBOUNDARY_GET(x) (((x) & INGPADBOUNDARY_MASK) \
116 >> INGPADBOUNDARY_SHIFT)
117 #define EGRPCIEBOUNDARY_MASK 0x0000000eU
118 #define EGRPCIEBOUNDARY_SHIFT 1
119 #define EGRPCIEBOUNDARY(x) ((x) << EGRPCIEBOUNDARY_SHIFT)
120 #define GLOBALENABLE 0x00000001U
122 #define SGE_HOST_PAGE_SIZE 0x100c
124 #define HOSTPAGESIZEPF7_MASK 0x0000000fU
125 #define HOSTPAGESIZEPF7_SHIFT 28
126 #define HOSTPAGESIZEPF7(x) ((x) << HOSTPAGESIZEPF7_SHIFT)
128 #define HOSTPAGESIZEPF6_MASK 0x0000000fU
129 #define HOSTPAGESIZEPF6_SHIFT 24
130 #define HOSTPAGESIZEPF6(x) ((x) << HOSTPAGESIZEPF6_SHIFT)
132 #define HOSTPAGESIZEPF5_MASK 0x0000000fU
133 #define HOSTPAGESIZEPF5_SHIFT 20
134 #define HOSTPAGESIZEPF5(x) ((x) << HOSTPAGESIZEPF5_SHIFT)
136 #define HOSTPAGESIZEPF4_MASK 0x0000000fU
137 #define HOSTPAGESIZEPF4_SHIFT 16
138 #define HOSTPAGESIZEPF4(x) ((x) << HOSTPAGESIZEPF4_SHIFT)
140 #define HOSTPAGESIZEPF3_MASK 0x0000000fU
141 #define HOSTPAGESIZEPF3_SHIFT 12
142 #define HOSTPAGESIZEPF3(x) ((x) << HOSTPAGESIZEPF3_SHIFT)
144 #define HOSTPAGESIZEPF2_MASK 0x0000000fU
145 #define HOSTPAGESIZEPF2_SHIFT 8
146 #define HOSTPAGESIZEPF2(x) ((x) << HOSTPAGESIZEPF2_SHIFT)
148 #define HOSTPAGESIZEPF1_MASK 0x0000000fU
149 #define HOSTPAGESIZEPF1_SHIFT 4
150 #define HOSTPAGESIZEPF1(x) ((x) << HOSTPAGESIZEPF1_SHIFT)
152 #define HOSTPAGESIZEPF0_MASK 0x0000000fU
153 #define HOSTPAGESIZEPF0_SHIFT 0
154 #define HOSTPAGESIZEPF0(x) ((x) << HOSTPAGESIZEPF0_SHIFT)
156 #define SGE_EGRESS_QUEUES_PER_PAGE_PF 0x1010
157 #define QUEUESPERPAGEPF0_MASK 0x0000000fU
158 #define QUEUESPERPAGEPF0_GET(x) ((x) & QUEUESPERPAGEPF0_MASK)
160 #define QUEUESPERPAGEPF0 0
161 #define QUEUESPERPAGEPF1 4
163 /* T5 and later support a new BAR2-based doorbell mechanism for Egress Queues.
164 * The User Doorbells are each 128 bytes in length with a Simple Doorbell at
165 * offsets 8x and a Write Combining single 64-byte Egress Queue Unit
166 * (X_IDXSIZE_UNIT) Gather Buffer interface at offset 64. For Ingress Queues,
167 * we have a Going To Sleep register at offsets 8x+4.
169 * As noted above, we have many instances of the Simple Doorbell and Going To
170 * Sleep registers at offsets 8x and 8x+4, respectively. We want to use a
171 * non-64-byte aligned offset for the Simple Doorbell in order to attempt to
172 * avoid buffering of the writes to the Simple Doorbell and we want to use a
173 * non-contiguous offset for the Going To Sleep writes in order to avoid
174 * possible combining between them.
176 #define SGE_UDB_SIZE 128
177 #define SGE_UDB_KDOORBELL 8
178 #define SGE_UDB_GTS 20
179 #define SGE_UDB_WCDOORBELL 64
181 #define SGE_INT_CAUSE1 0x1024
182 #define SGE_INT_CAUSE2 0x1030
183 #define SGE_INT_CAUSE3 0x103c
184 #define ERR_FLM_DBP 0x80000000U
185 #define ERR_FLM_IDMA1 0x40000000U
186 #define ERR_FLM_IDMA0 0x20000000U
187 #define ERR_FLM_HINT 0x10000000U
188 #define ERR_PCIE_ERROR3 0x08000000U
189 #define ERR_PCIE_ERROR2 0x04000000U
190 #define ERR_PCIE_ERROR1 0x02000000U
191 #define ERR_PCIE_ERROR0 0x01000000U
192 #define ERR_TIMER_ABOVE_MAX_QID 0x00800000U
193 #define ERR_CPL_EXCEED_IQE_SIZE 0x00400000U
194 #define ERR_INVALID_CIDX_INC 0x00200000U
195 #define ERR_ITP_TIME_PAUSED 0x00100000U
196 #define ERR_CPL_OPCODE_0 0x00080000U
197 #define ERR_DROPPED_DB 0x00040000U
198 #define ERR_DATA_CPL_ON_HIGH_QID1 0x00020000U
199 #define ERR_DATA_CPL_ON_HIGH_QID0 0x00010000U
200 #define ERR_BAD_DB_PIDX3 0x00008000U
201 #define ERR_BAD_DB_PIDX2 0x00004000U
202 #define ERR_BAD_DB_PIDX1 0x00002000U
203 #define ERR_BAD_DB_PIDX0 0x00001000U
204 #define ERR_ING_PCIE_CHAN 0x00000800U
205 #define ERR_ING_CTXT_PRIO 0x00000400U
206 #define ERR_EGR_CTXT_PRIO 0x00000200U
207 #define DBFIFO_HP_INT 0x00000100U
208 #define DBFIFO_LP_INT 0x00000080U
209 #define REG_ADDRESS_ERR 0x00000040U
210 #define INGRESS_SIZE_ERR 0x00000020U
211 #define EGRESS_SIZE_ERR 0x00000010U
212 #define ERR_INV_CTXT3 0x00000008U
213 #define ERR_INV_CTXT2 0x00000004U
214 #define ERR_INV_CTXT1 0x00000002U
215 #define ERR_INV_CTXT0 0x00000001U
217 #define SGE_INT_ENABLE3 0x1040
218 #define SGE_FL_BUFFER_SIZE0 0x1044
219 #define SGE_FL_BUFFER_SIZE1 0x1048
220 #define SGE_FL_BUFFER_SIZE2 0x104c
221 #define SGE_FL_BUFFER_SIZE3 0x1050
222 #define SGE_FL_BUFFER_SIZE4 0x1054
223 #define SGE_FL_BUFFER_SIZE5 0x1058
224 #define SGE_FL_BUFFER_SIZE6 0x105c
225 #define SGE_FL_BUFFER_SIZE7 0x1060
226 #define SGE_FL_BUFFER_SIZE8 0x1064
228 #define SGE_INGRESS_RX_THRESHOLD 0x10a0
229 #define THRESHOLD_0_MASK 0x3f000000U
230 #define THRESHOLD_0_SHIFT 24
231 #define THRESHOLD_0(x) ((x) << THRESHOLD_0_SHIFT)
232 #define THRESHOLD_0_GET(x) (((x) & THRESHOLD_0_MASK) >> THRESHOLD_0_SHIFT)
233 #define THRESHOLD_1_MASK 0x003f0000U
234 #define THRESHOLD_1_SHIFT 16
235 #define THRESHOLD_1(x) ((x) << THRESHOLD_1_SHIFT)
236 #define THRESHOLD_1_GET(x) (((x) & THRESHOLD_1_MASK) >> THRESHOLD_1_SHIFT)
237 #define THRESHOLD_2_MASK 0x00003f00U
238 #define THRESHOLD_2_SHIFT 8
239 #define THRESHOLD_2(x) ((x) << THRESHOLD_2_SHIFT)
240 #define THRESHOLD_2_GET(x) (((x) & THRESHOLD_2_MASK) >> THRESHOLD_2_SHIFT)
241 #define THRESHOLD_3_MASK 0x0000003fU
242 #define THRESHOLD_3_SHIFT 0
243 #define THRESHOLD_3(x) ((x) << THRESHOLD_3_SHIFT)
244 #define THRESHOLD_3_GET(x) (((x) & THRESHOLD_3_MASK) >> THRESHOLD_3_SHIFT)
246 #define SGE_CONM_CTRL 0x1094
247 #define EGRTHRESHOLD_MASK 0x00003f00U
248 #define EGRTHRESHOLDshift 8
249 #define EGRTHRESHOLD(x) ((x) << EGRTHRESHOLDshift)
250 #define EGRTHRESHOLD_GET(x) (((x) & EGRTHRESHOLD_MASK) >> EGRTHRESHOLDshift)
252 #define EGRTHRESHOLDPACKING_MASK 0x3fU
253 #define EGRTHRESHOLDPACKING_SHIFT 14
254 #define EGRTHRESHOLDPACKING(x) ((x) << EGRTHRESHOLDPACKING_SHIFT)
255 #define EGRTHRESHOLDPACKING_GET(x) (((x) >> EGRTHRESHOLDPACKING_SHIFT) & \
256 EGRTHRESHOLDPACKING_MASK)
258 #define SGE_DBFIFO_STATUS 0x10a4
259 #define HP_INT_THRESH_SHIFT 28
260 #define HP_INT_THRESH_MASK 0xfU
261 #define HP_INT_THRESH(x) ((x) << HP_INT_THRESH_SHIFT)
262 #define LP_INT_THRESH_SHIFT 12
263 #define LP_INT_THRESH_MASK 0xfU
264 #define LP_INT_THRESH(x) ((x) << LP_INT_THRESH_SHIFT)
266 #define SGE_DOORBELL_CONTROL 0x10a8
267 #define ENABLE_DROP (1 << 13)
269 #define S_NOCOALESCE 26
270 #define V_NOCOALESCE(x) ((x) << S_NOCOALESCE)
271 #define F_NOCOALESCE V_NOCOALESCE(1U)
273 #define SGE_TIMESTAMP_LO 0x1098
274 #define SGE_TIMESTAMP_HI 0x109c
276 #define M_TSVAL 0xfffffffU
277 #define GET_TSVAL(x) (((x) >> S_TSVAL) & M_TSVAL)
279 #define SGE_TIMER_VALUE_0_AND_1 0x10b8
280 #define TIMERVALUE0_MASK 0xffff0000U
281 #define TIMERVALUE0_SHIFT 16
282 #define TIMERVALUE0(x) ((x) << TIMERVALUE0_SHIFT)
283 #define TIMERVALUE0_GET(x) (((x) & TIMERVALUE0_MASK) >> TIMERVALUE0_SHIFT)
284 #define TIMERVALUE1_MASK 0x0000ffffU
285 #define TIMERVALUE1_SHIFT 0
286 #define TIMERVALUE1(x) ((x) << TIMERVALUE1_SHIFT)
287 #define TIMERVALUE1_GET(x) (((x) & TIMERVALUE1_MASK) >> TIMERVALUE1_SHIFT)
289 #define SGE_TIMER_VALUE_2_AND_3 0x10bc
290 #define TIMERVALUE2_MASK 0xffff0000U
291 #define TIMERVALUE2_SHIFT 16
292 #define TIMERVALUE2(x) ((x) << TIMERVALUE2_SHIFT)
293 #define TIMERVALUE2_GET(x) (((x) & TIMERVALUE2_MASK) >> TIMERVALUE2_SHIFT)
294 #define TIMERVALUE3_MASK 0x0000ffffU
295 #define TIMERVALUE3_SHIFT 0
296 #define TIMERVALUE3(x) ((x) << TIMERVALUE3_SHIFT)
297 #define TIMERVALUE3_GET(x) (((x) & TIMERVALUE3_MASK) >> TIMERVALUE3_SHIFT)
299 #define SGE_TIMER_VALUE_4_AND_5 0x10c0
300 #define TIMERVALUE4_MASK 0xffff0000U
301 #define TIMERVALUE4_SHIFT 16
302 #define TIMERVALUE4(x) ((x) << TIMERVALUE4_SHIFT)
303 #define TIMERVALUE4_GET(x) (((x) & TIMERVALUE4_MASK) >> TIMERVALUE4_SHIFT)
304 #define TIMERVALUE5_MASK 0x0000ffffU
305 #define TIMERVALUE5_SHIFT 0
306 #define TIMERVALUE5(x) ((x) << TIMERVALUE5_SHIFT)
307 #define TIMERVALUE5_GET(x) (((x) & TIMERVALUE5_MASK) >> TIMERVALUE5_SHIFT)
309 #define SGE_DEBUG_INDEX 0x10cc
310 #define SGE_DEBUG_DATA_HIGH 0x10d0
311 #define SGE_DEBUG_DATA_LOW 0x10d4
312 #define SGE_DEBUG_DATA_LOW_INDEX_2 0x12c8
313 #define SGE_DEBUG_DATA_LOW_INDEX_3 0x12cc
314 #define SGE_DEBUG_DATA_HIGH_INDEX_10 0x12a8
315 #define SGE_INGRESS_QUEUES_PER_PAGE_PF 0x10f4
317 #define S_HP_INT_THRESH 28
318 #define M_HP_INT_THRESH 0xfU
319 #define V_HP_INT_THRESH(x) ((x) << S_HP_INT_THRESH)
320 #define S_LP_INT_THRESH_T5 18
321 #define V_LP_INT_THRESH_T5(x) ((x) << S_LP_INT_THRESH_T5)
322 #define M_LP_COUNT_T5 0x3ffffU
323 #define G_LP_COUNT_T5(x) (((x) >> S_LP_COUNT) & M_LP_COUNT_T5)
324 #define M_HP_COUNT 0x7ffU
325 #define S_HP_COUNT 16
326 #define G_HP_COUNT(x) (((x) >> S_HP_COUNT) & M_HP_COUNT)
327 #define S_LP_INT_THRESH 12
328 #define M_LP_INT_THRESH 0xfU
329 #define M_LP_INT_THRESH_T5 0xfffU
330 #define V_LP_INT_THRESH(x) ((x) << S_LP_INT_THRESH)
331 #define M_LP_COUNT 0x7ffU
333 #define G_LP_COUNT(x) (((x) >> S_LP_COUNT) & M_LP_COUNT)
334 #define A_SGE_DBFIFO_STATUS 0x10a4
336 #define SGE_STAT_TOTAL 0x10e4
337 #define SGE_STAT_MATCH 0x10e8
339 #define SGE_STAT_CFG 0x10ec
340 #define S_STATSOURCE_T5 9
341 #define STATSOURCE_T5(x) ((x) << S_STATSOURCE_T5)
343 #define SGE_DBFIFO_STATUS2 0x1118
344 #define M_HP_COUNT_T5 0x3ffU
345 #define G_HP_COUNT_T5(x) ((x) & M_HP_COUNT_T5)
346 #define S_HP_INT_THRESH_T5 10
347 #define M_HP_INT_THRESH_T5 0xfU
348 #define V_HP_INT_THRESH_T5(x) ((x) << S_HP_INT_THRESH_T5)
350 #define S_ENABLE_DROP 13
351 #define V_ENABLE_DROP(x) ((x) << S_ENABLE_DROP)
352 #define F_ENABLE_DROP V_ENABLE_DROP(1U)
353 #define S_DROPPED_DB 0
354 #define V_DROPPED_DB(x) ((x) << S_DROPPED_DB)
355 #define F_DROPPED_DB V_DROPPED_DB(1U)
356 #define A_SGE_DOORBELL_CONTROL 0x10a8
358 #define A_SGE_CTXT_CMD 0x11fc
359 #define A_SGE_DBQ_CTXT_BADDR 0x1084
361 #define PCIE_PF_CFG 0x40
362 #define AIVEC(x) ((x) << 4)
363 #define AIVEC_MASK 0x3ffU
365 #define PCIE_PF_CLI 0x44
366 #define PCIE_INT_CAUSE 0x3004
367 #define UNXSPLCPLERR 0x20000000U
368 #define PCIEPINT 0x10000000U
369 #define PCIESINT 0x08000000U
370 #define RPLPERR 0x04000000U
371 #define RXWRPERR 0x02000000U
372 #define RXCPLPERR 0x01000000U
373 #define PIOTAGPERR 0x00800000U
374 #define MATAGPERR 0x00400000U
375 #define INTXCLRPERR 0x00200000U
376 #define FIDPERR 0x00100000U
377 #define CFGSNPPERR 0x00080000U
378 #define HRSPPERR 0x00040000U
379 #define HREQPERR 0x00020000U
380 #define HCNTPERR 0x00010000U
381 #define DRSPPERR 0x00008000U
382 #define DREQPERR 0x00004000U
383 #define DCNTPERR 0x00002000U
384 #define CRSPPERR 0x00001000U
385 #define CREQPERR 0x00000800U
386 #define CCNTPERR 0x00000400U
387 #define TARTAGPERR 0x00000200U
388 #define PIOREQPERR 0x00000100U
389 #define PIOCPLPERR 0x00000080U
390 #define MSIXDIPERR 0x00000040U
391 #define MSIXDATAPERR 0x00000020U
392 #define MSIXADDRHPERR 0x00000010U
393 #define MSIXADDRLPERR 0x00000008U
394 #define MSIDATAPERR 0x00000004U
395 #define MSIADDRHPERR 0x00000002U
396 #define MSIADDRLPERR 0x00000001U
398 #define READRSPERR 0x20000000U
399 #define TRGT1GRPPERR 0x10000000U
400 #define IPSOTPERR 0x08000000U
401 #define IPRXDATAGRPPERR 0x02000000U
402 #define IPRXHDRGRPPERR 0x01000000U
403 #define MAGRPPERR 0x00400000U
404 #define VFIDPERR 0x00200000U
405 #define HREQWRPERR 0x00010000U
406 #define DREQWRPERR 0x00002000U
407 #define MSTTAGQPERR 0x00000400U
408 #define PIOREQGRPPERR 0x00000100U
409 #define PIOCPLGRPPERR 0x00000080U
410 #define MSIXSTIPERR 0x00000004U
411 #define MSTTIMEOUTPERR 0x00000002U
412 #define MSTGRPPERR 0x00000001U
414 #define PCIE_NONFAT_ERR 0x3010
415 #define PCIE_CFG_SPACE_REQ 0x3060
416 #define PCIE_CFG_SPACE_DATA 0x3064
417 #define PCIE_MEM_ACCESS_BASE_WIN 0x3068
418 #define S_PCIEOFST 10
419 #define M_PCIEOFST 0x3fffffU
420 #define GET_PCIEOFST(x) (((x) >> S_PCIEOFST) & M_PCIEOFST)
421 #define PCIEOFST_MASK 0xfffffc00U
422 #define BIR_MASK 0x00000300U
424 #define BIR(x) ((x) << BIR_SHIFT)
425 #define WINDOW_MASK 0x000000ffU
426 #define WINDOW_SHIFT 0
427 #define WINDOW(x) ((x) << WINDOW_SHIFT)
428 #define GET_WINDOW(x) (((x) >> WINDOW_SHIFT) & WINDOW_MASK)
429 #define PCIE_MEM_ACCESS_OFFSET 0x306c
430 #define ENABLE (1U << 30)
431 #define FUNCTION(x) ((x) << 12)
432 #define F_LOCALCFG (1U << 28)
435 #define V_PFNUM(x) ((x) << S_PFNUM)
437 #define PCIE_FW 0x30b8
438 #define PCIE_FW_ERR 0x80000000U
439 #define PCIE_FW_INIT 0x40000000U
440 #define PCIE_FW_HALT 0x20000000U
441 #define PCIE_FW_MASTER_VLD 0x00008000U
442 #define PCIE_FW_MASTER(x) ((x) << 12)
443 #define PCIE_FW_MASTER_MASK 0x7
444 #define PCIE_FW_MASTER_GET(x) (((x) >> 12) & PCIE_FW_MASTER_MASK)
446 #define PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS 0x5908
447 #define RNPP 0x80000000U
448 #define RPCP 0x20000000U
449 #define RCIP 0x08000000U
450 #define RCCP 0x04000000U
451 #define RFTP 0x00800000U
452 #define PTRP 0x00100000U
454 #define PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS 0x59a4
455 #define TPCP 0x40000000U
456 #define TNPP 0x20000000U
457 #define TFTP 0x10000000U
458 #define TCAP 0x08000000U
459 #define TCIP 0x04000000U
460 #define RCAP 0x02000000U
461 #define PLUP 0x00800000U
462 #define PLDN 0x00400000U
463 #define OTDD 0x00200000U
464 #define GTRP 0x00100000U
465 #define RDPE 0x00040000U
466 #define TDCE 0x00020000U
467 #define TDUE 0x00010000U
469 #define MC_INT_CAUSE 0x7518
470 #define MC_P_INT_CAUSE 0x41318
471 #define ECC_UE_INT_CAUSE 0x00000004U
472 #define ECC_CE_INT_CAUSE 0x00000002U
473 #define PERR_INT_CAUSE 0x00000001U
475 #define MC_ECC_STATUS 0x751c
476 #define MC_P_ECC_STATUS 0x4131c
477 #define ECC_CECNT_MASK 0xffff0000U
478 #define ECC_CECNT_SHIFT 16
479 #define ECC_CECNT(x) ((x) << ECC_CECNT_SHIFT)
480 #define ECC_CECNT_GET(x) (((x) & ECC_CECNT_MASK) >> ECC_CECNT_SHIFT)
481 #define ECC_UECNT_MASK 0x0000ffffU
482 #define ECC_UECNT_SHIFT 0
483 #define ECC_UECNT(x) ((x) << ECC_UECNT_SHIFT)
484 #define ECC_UECNT_GET(x) (((x) & ECC_UECNT_MASK) >> ECC_UECNT_SHIFT)
486 #define MC_BIST_CMD 0x7600
487 #define START_BIST 0x80000000U
488 #define BIST_CMD_GAP_MASK 0x0000ff00U
489 #define BIST_CMD_GAP_SHIFT 8
490 #define BIST_CMD_GAP(x) ((x) << BIST_CMD_GAP_SHIFT)
491 #define BIST_OPCODE_MASK 0x00000003U
492 #define BIST_OPCODE_SHIFT 0
493 #define BIST_OPCODE(x) ((x) << BIST_OPCODE_SHIFT)
495 #define MC_BIST_CMD_ADDR 0x7604
496 #define MC_BIST_CMD_LEN 0x7608
497 #define MC_BIST_DATA_PATTERN 0x760c
498 #define BIST_DATA_TYPE_MASK 0x0000000fU
499 #define BIST_DATA_TYPE_SHIFT 0
500 #define BIST_DATA_TYPE(x) ((x) << BIST_DATA_TYPE_SHIFT)
502 #define MC_BIST_STATUS_RDATA 0x7688
504 #define MA_EDRAM0_BAR_A 0x77c0
506 #define EDRAM0_SIZE_S 0
507 #define EDRAM0_SIZE_M 0xfffU
508 #define EDRAM0_SIZE_V(x) ((x) << EDRAM0_SIZE_S)
509 #define EDRAM0_SIZE_G(x) (((x) >> EDRAM0_SIZE_S) & EDRAM0_SIZE_M)
511 #define MA_EDRAM1_BAR_A 0x77c4
513 #define EDRAM1_SIZE_S 0
514 #define EDRAM1_SIZE_M 0xfffU
515 #define EDRAM1_SIZE_V(x) ((x) << EDRAM1_SIZE_S)
516 #define EDRAM1_SIZE_G(x) (((x) >> EDRAM1_SIZE_S) & EDRAM1_SIZE_M)
518 #define MA_EXT_MEMORY_BAR_A 0x77c8
520 #define EXT_MEM_SIZE_S 0
521 #define EXT_MEM_SIZE_M 0xfffU
522 #define EXT_MEM_SIZE_V(x) ((x) << EXT_MEM_SIZE_S)
523 #define EXT_MEM_SIZE_G(x) (((x) >> EXT_MEM_SIZE_S) & EXT_MEM_SIZE_M)
525 #define MA_EXT_MEMORY1_BAR_A 0x7808
527 #define EXT_MEM1_SIZE_S 0
528 #define EXT_MEM1_SIZE_M 0xfffU
529 #define EXT_MEM1_SIZE_V(x) ((x) << EXT_MEM1_SIZE_S)
530 #define EXT_MEM1_SIZE_G(x) (((x) >> EXT_MEM1_SIZE_S) & EXT_MEM1_SIZE_M)
532 #define MA_EXT_MEMORY0_BAR_A 0x77c8
534 #define EXT_MEM0_SIZE_S 0
535 #define EXT_MEM0_SIZE_M 0xfffU
536 #define EXT_MEM0_SIZE_V(x) ((x) << EXT_MEM0_SIZE_S)
537 #define EXT_MEM0_SIZE_G(x) (((x) >> EXT_MEM0_SIZE_S) & EXT_MEM0_SIZE_M)
539 #define MA_TARGET_MEM_ENABLE_A 0x77d8
541 #define EXT_MEM_ENABLE_S 2
542 #define EXT_MEM_ENABLE_V(x) ((x) << EXT_MEM_ENABLE_S)
543 #define EXT_MEM_ENABLE_F EXT_MEM_ENABLE_V(1U)
545 #define EDRAM1_ENABLE_S 1
546 #define EDRAM1_ENABLE_V(x) ((x) << EDRAM1_ENABLE_S)
547 #define EDRAM1_ENABLE_F EDRAM1_ENABLE_V(1U)
549 #define EDRAM0_ENABLE_S 0
550 #define EDRAM0_ENABLE_V(x) ((x) << EDRAM0_ENABLE_S)
551 #define EDRAM0_ENABLE_F EDRAM0_ENABLE_V(1U)
553 #define EXT_MEM1_ENABLE_S 4
554 #define EXT_MEM1_ENABLE_V(x) ((x) << EXT_MEM1_ENABLE_S)
555 #define EXT_MEM1_ENABLE_F EXT_MEM1_ENABLE_V(1U)
557 #define EXT_MEM0_ENABLE_S 2
558 #define EXT_MEM0_ENABLE_V(x) ((x) << EXT_MEM0_ENABLE_S)
559 #define EXT_MEM0_ENABLE_F EXT_MEM0_ENABLE_V(1U)
561 #define MA_INT_CAUSE 0x77e0
562 #define MEM_PERR_INT_CAUSE 0x00000002U
563 #define MEM_WRAP_INT_CAUSE 0x00000001U
565 #define MA_INT_WRAP_STATUS 0x77e4
566 #define MEM_WRAP_ADDRESS_MASK 0xfffffff0U
567 #define MEM_WRAP_ADDRESS_SHIFT 4
568 #define MEM_WRAP_ADDRESS_GET(x) (((x) & MEM_WRAP_ADDRESS_MASK) >> MEM_WRAP_ADDRESS_SHIFT)
569 #define MEM_WRAP_CLIENT_NUM_MASK 0x0000000fU
570 #define MEM_WRAP_CLIENT_NUM_SHIFT 0
571 #define MEM_WRAP_CLIENT_NUM_GET(x) (((x) & MEM_WRAP_CLIENT_NUM_MASK) >> MEM_WRAP_CLIENT_NUM_SHIFT)
572 #define MA_PCIE_FW 0x30b8
573 #define MA_PARITY_ERROR_STATUS 0x77f4
574 #define MA_PARITY_ERROR_STATUS2 0x7804
576 #define EDC_0_BASE_ADDR 0x7900
578 #define EDC_BIST_CMD 0x7904
579 #define EDC_BIST_CMD_ADDR 0x7908
580 #define EDC_BIST_CMD_LEN 0x790c
581 #define EDC_BIST_DATA_PATTERN 0x7910
582 #define EDC_BIST_STATUS_RDATA 0x7928
583 #define EDC_INT_CAUSE 0x7978
584 #define ECC_UE_PAR 0x00000020U
585 #define ECC_CE_PAR 0x00000010U
586 #define PERR_PAR_CAUSE 0x00000008U
588 #define EDC_ECC_STATUS 0x797c
590 #define EDC_1_BASE_ADDR 0x7980
592 #define CIM_BOOT_CFG 0x7b00
593 #define BOOTADDR_MASK 0xffffff00U
596 #define CIM_PF_MAILBOX_DATA 0x240
597 #define CIM_PF_MAILBOX_CTRL 0x280
598 #define MBMSGVALID 0x00000008U
599 #define MBINTREQ 0x00000004U
600 #define MBOWNER_MASK 0x00000003U
601 #define MBOWNER_SHIFT 0
602 #define MBOWNER(x) ((x) << MBOWNER_SHIFT)
603 #define MBOWNER_GET(x) (((x) & MBOWNER_MASK) >> MBOWNER_SHIFT)
605 #define CIM_PF_HOST_INT_ENABLE 0x288
606 #define MBMSGRDYINTEN(x) ((x) << 19)
608 #define CIM_PF_HOST_INT_CAUSE 0x28c
609 #define MBMSGRDYINT 0x00080000U
611 #define CIM_HOST_INT_CAUSE 0x7b2c
612 #define TIEQOUTPARERRINT 0x00100000U
613 #define TIEQINPARERRINT 0x00080000U
614 #define MBHOSTPARERR 0x00040000U
615 #define MBUPPARERR 0x00020000U
616 #define IBQPARERR 0x0001f800U
617 #define IBQTP0PARERR 0x00010000U
618 #define IBQTP1PARERR 0x00008000U
619 #define IBQULPPARERR 0x00004000U
620 #define IBQSGELOPARERR 0x00002000U
621 #define IBQSGEHIPARERR 0x00001000U
622 #define IBQNCSIPARERR 0x00000800U
623 #define OBQPARERR 0x000007e0U
624 #define OBQULP0PARERR 0x00000400U
625 #define OBQULP1PARERR 0x00000200U
626 #define OBQULP2PARERR 0x00000100U
627 #define OBQULP3PARERR 0x00000080U
628 #define OBQSGEPARERR 0x00000040U
629 #define OBQNCSIPARERR 0x00000020U
630 #define PREFDROPINT 0x00000002U
631 #define UPACCNONZERO 0x00000001U
633 #define CIM_HOST_UPACC_INT_CAUSE 0x7b34
634 #define EEPROMWRINT 0x40000000U
635 #define TIMEOUTMAINT 0x20000000U
636 #define TIMEOUTINT 0x10000000U
637 #define RSPOVRLOOKUPINT 0x08000000U
638 #define REQOVRLOOKUPINT 0x04000000U
639 #define BLKWRPLINT 0x02000000U
640 #define BLKRDPLINT 0x01000000U
641 #define SGLWRPLINT 0x00800000U
642 #define SGLRDPLINT 0x00400000U
643 #define BLKWRCTLINT 0x00200000U
644 #define BLKRDCTLINT 0x00100000U
645 #define SGLWRCTLINT 0x00080000U
646 #define SGLRDCTLINT 0x00040000U
647 #define BLKWREEPROMINT 0x00020000U
648 #define BLKRDEEPROMINT 0x00010000U
649 #define SGLWREEPROMINT 0x00008000U
650 #define SGLRDEEPROMINT 0x00004000U
651 #define BLKWRFLASHINT 0x00002000U
652 #define BLKRDFLASHINT 0x00001000U
653 #define SGLWRFLASHINT 0x00000800U
654 #define SGLRDFLASHINT 0x00000400U
655 #define BLKWRBOOTINT 0x00000200U
656 #define BLKRDBOOTINT 0x00000100U
657 #define SGLWRBOOTINT 0x00000080U
658 #define SGLRDBOOTINT 0x00000040U
659 #define ILLWRBEINT 0x00000020U
660 #define ILLRDBEINT 0x00000010U
661 #define ILLRDINT 0x00000008U
662 #define ILLWRINT 0x00000004U
663 #define ILLTRANSINT 0x00000002U
664 #define RSVDSPACEINT 0x00000001U
666 #define TP_OUT_CONFIG 0x7d04
667 #define VLANEXTENABLE_MASK 0x0000f000U
668 #define VLANEXTENABLE_SHIFT 12
670 #define TP_GLOBAL_CONFIG 0x7d08
671 #define FIVETUPLELOOKUP_SHIFT 17
672 #define FIVETUPLELOOKUP_MASK 0x00060000U
673 #define FIVETUPLELOOKUP(x) ((x) << FIVETUPLELOOKUP_SHIFT)
674 #define FIVETUPLELOOKUP_GET(x) (((x) & FIVETUPLELOOKUP_MASK) >> \
675 FIVETUPLELOOKUP_SHIFT)
677 #define TP_PARA_REG2 0x7d68
678 #define MAXRXDATA_MASK 0xffff0000U
679 #define MAXRXDATA_SHIFT 16
680 #define MAXRXDATA_GET(x) (((x) & MAXRXDATA_MASK) >> MAXRXDATA_SHIFT)
682 #define TP_TIMER_RESOLUTION 0x7d90
683 #define TIMERRESOLUTION_MASK 0x00ff0000U
684 #define TIMERRESOLUTION_SHIFT 16
685 #define TIMERRESOLUTION_GET(x) (((x) & TIMERRESOLUTION_MASK) >> TIMERRESOLUTION_SHIFT)
686 #define DELAYEDACKRESOLUTION_MASK 0x000000ffU
687 #define DELAYEDACKRESOLUTION_SHIFT 0
688 #define DELAYEDACKRESOLUTION_GET(x) \
689 (((x) & DELAYEDACKRESOLUTION_MASK) >> DELAYEDACKRESOLUTION_SHIFT)
691 #define TP_SHIFT_CNT 0x7dc0
692 #define SYNSHIFTMAX_SHIFT 24
693 #define SYNSHIFTMAX_MASK 0xff000000U
694 #define SYNSHIFTMAX(x) ((x) << SYNSHIFTMAX_SHIFT)
695 #define SYNSHIFTMAX_GET(x) (((x) & SYNSHIFTMAX_MASK) >> \
697 #define RXTSHIFTMAXR1_SHIFT 20
698 #define RXTSHIFTMAXR1_MASK 0x00f00000U
699 #define RXTSHIFTMAXR1(x) ((x) << RXTSHIFTMAXR1_SHIFT)
700 #define RXTSHIFTMAXR1_GET(x) (((x) & RXTSHIFTMAXR1_MASK) >> \
702 #define RXTSHIFTMAXR2_SHIFT 16
703 #define RXTSHIFTMAXR2_MASK 0x000f0000U
704 #define RXTSHIFTMAXR2(x) ((x) << RXTSHIFTMAXR2_SHIFT)
705 #define RXTSHIFTMAXR2_GET(x) (((x) & RXTSHIFTMAXR2_MASK) >> \
707 #define PERSHIFTBACKOFFMAX_SHIFT 12
708 #define PERSHIFTBACKOFFMAX_MASK 0x0000f000U
709 #define PERSHIFTBACKOFFMAX(x) ((x) << PERSHIFTBACKOFFMAX_SHIFT)
710 #define PERSHIFTBACKOFFMAX_GET(x) (((x) & PERSHIFTBACKOFFMAX_MASK) >> \
711 PERSHIFTBACKOFFMAX_SHIFT)
712 #define PERSHIFTMAX_SHIFT 8
713 #define PERSHIFTMAX_MASK 0x00000f00U
714 #define PERSHIFTMAX(x) ((x) << PERSHIFTMAX_SHIFT)
715 #define PERSHIFTMAX_GET(x) (((x) & PERSHIFTMAX_MASK) >> \
717 #define KEEPALIVEMAXR1_SHIFT 4
718 #define KEEPALIVEMAXR1_MASK 0x000000f0U
719 #define KEEPALIVEMAXR1(x) ((x) << KEEPALIVEMAXR1_SHIFT)
720 #define KEEPALIVEMAXR1_GET(x) (((x) & KEEPALIVEMAXR1_MASK) >> \
721 KEEPALIVEMAXR1_SHIFT)
722 #define KEEPALIVEMAXR2_SHIFT 0
723 #define KEEPALIVEMAXR2_MASK 0x0000000fU
724 #define KEEPALIVEMAXR2(x) ((x) << KEEPALIVEMAXR2_SHIFT)
725 #define KEEPALIVEMAXR2_GET(x) (((x) & KEEPALIVEMAXR2_MASK) >> \
726 KEEPALIVEMAXR2_SHIFT)
728 #define TP_CCTRL_TABLE 0x7ddc
729 #define TP_MTU_TABLE 0x7de4
730 #define MTUINDEX_MASK 0xff000000U
731 #define MTUINDEX_SHIFT 24
732 #define MTUINDEX(x) ((x) << MTUINDEX_SHIFT)
733 #define MTUWIDTH_MASK 0x000f0000U
734 #define MTUWIDTH_SHIFT 16
735 #define MTUWIDTH(x) ((x) << MTUWIDTH_SHIFT)
736 #define MTUWIDTH_GET(x) (((x) & MTUWIDTH_MASK) >> MTUWIDTH_SHIFT)
737 #define MTUVALUE_MASK 0x00003fffU
738 #define MTUVALUE_SHIFT 0
739 #define MTUVALUE(x) ((x) << MTUVALUE_SHIFT)
740 #define MTUVALUE_GET(x) (((x) & MTUVALUE_MASK) >> MTUVALUE_SHIFT)
742 #define TP_RSS_LKP_TABLE 0x7dec
743 #define LKPTBLROWVLD 0x80000000U
744 #define LKPTBLQUEUE1_MASK 0x000ffc00U
745 #define LKPTBLQUEUE1_SHIFT 10
746 #define LKPTBLQUEUE1(x) ((x) << LKPTBLQUEUE1_SHIFT)
747 #define LKPTBLQUEUE1_GET(x) (((x) & LKPTBLQUEUE1_MASK) >> LKPTBLQUEUE1_SHIFT)
748 #define LKPTBLQUEUE0_MASK 0x000003ffU
749 #define LKPTBLQUEUE0_SHIFT 0
750 #define LKPTBLQUEUE0(x) ((x) << LKPTBLQUEUE0_SHIFT)
751 #define LKPTBLQUEUE0_GET(x) (((x) & LKPTBLQUEUE0_MASK) >> LKPTBLQUEUE0_SHIFT)
753 #define TP_PIO_ADDR 0x7e40
754 #define TP_PIO_DATA 0x7e44
755 #define TP_MIB_INDEX 0x7e50
756 #define TP_MIB_DATA 0x7e54
757 #define TP_INT_CAUSE 0x7e74
758 #define FLMTXFLSTEMPTY 0x40000000U
760 #define TP_VLAN_PRI_MAP 0x140
761 #define FRAGMENTATION_SHIFT 9
762 #define FRAGMENTATION_MASK 0x00000200U
763 #define MPSHITTYPE_MASK 0x00000100U
764 #define MACMATCH_MASK 0x00000080U
765 #define ETHERTYPE_MASK 0x00000040U
766 #define PROTOCOL_MASK 0x00000020U
767 #define TOS_MASK 0x00000010U
768 #define VLAN_MASK 0x00000008U
769 #define VNIC_ID_MASK 0x00000004U
770 #define PORT_MASK 0x00000002U
772 #define FCOE_MASK 0x00000001U
774 #define TP_INGRESS_CONFIG 0x141
775 #define VNIC 0x00000800U
776 #define CSUM_HAS_PSEUDO_HDR 0x00000400U
777 #define RM_OVLAN 0x00000200U
778 #define LOOKUPEVERYPKT 0x00000100U
780 #define TP_MIB_MAC_IN_ERR_0 0x0
781 #define TP_MIB_TCP_OUT_RST 0xc
782 #define TP_MIB_TCP_IN_SEG_HI 0x10
783 #define TP_MIB_TCP_IN_SEG_LO 0x11
784 #define TP_MIB_TCP_OUT_SEG_HI 0x12
785 #define TP_MIB_TCP_OUT_SEG_LO 0x13
786 #define TP_MIB_TCP_RXT_SEG_HI 0x14
787 #define TP_MIB_TCP_RXT_SEG_LO 0x15
788 #define TP_MIB_TNL_CNG_DROP_0 0x18
789 #define TP_MIB_TCP_V6IN_ERR_0 0x28
790 #define TP_MIB_TCP_V6OUT_RST 0x2c
791 #define TP_MIB_OFD_ARP_DROP 0x36
792 #define TP_MIB_TNL_DROP_0 0x44
793 #define TP_MIB_OFD_VLN_DROP_0 0x58
795 #define ULP_TX_INT_CAUSE 0x8dcc
796 #define PBL_BOUND_ERR_CH3 0x80000000U
797 #define PBL_BOUND_ERR_CH2 0x40000000U
798 #define PBL_BOUND_ERR_CH1 0x20000000U
799 #define PBL_BOUND_ERR_CH0 0x10000000U
801 #define PM_RX_INT_CAUSE 0x8fdc
802 #define ZERO_E_CMD_ERROR 0x00400000U
803 #define PMRX_FRAMING_ERROR 0x003ffff0U
804 #define OCSPI_PAR_ERROR 0x00000008U
805 #define DB_OPTIONS_PAR_ERROR 0x00000004U
806 #define IESPI_PAR_ERROR 0x00000002U
807 #define E_PCMD_PAR_ERROR 0x00000001U
809 #define PM_TX_INT_CAUSE 0x8ffc
810 #define PCMD_LEN_OVFL0 0x80000000U
811 #define PCMD_LEN_OVFL1 0x40000000U
812 #define PCMD_LEN_OVFL2 0x20000000U
813 #define ZERO_C_CMD_ERROR 0x10000000U
814 #define PMTX_FRAMING_ERROR 0x0ffffff0U
815 #define OESPI_PAR_ERROR 0x00000008U
816 #define ICSPI_PAR_ERROR 0x00000002U
817 #define C_PCMD_PAR_ERROR 0x00000001U
819 #define MPS_PORT_STAT_TX_PORT_BYTES_L 0x400
820 #define MPS_PORT_STAT_TX_PORT_BYTES_H 0x404
821 #define MPS_PORT_STAT_TX_PORT_FRAMES_L 0x408
822 #define MPS_PORT_STAT_TX_PORT_FRAMES_H 0x40c
823 #define MPS_PORT_STAT_TX_PORT_BCAST_L 0x410
824 #define MPS_PORT_STAT_TX_PORT_BCAST_H 0x414
825 #define MPS_PORT_STAT_TX_PORT_MCAST_L 0x418
826 #define MPS_PORT_STAT_TX_PORT_MCAST_H 0x41c
827 #define MPS_PORT_STAT_TX_PORT_UCAST_L 0x420
828 #define MPS_PORT_STAT_TX_PORT_UCAST_H 0x424
829 #define MPS_PORT_STAT_TX_PORT_ERROR_L 0x428
830 #define MPS_PORT_STAT_TX_PORT_ERROR_H 0x42c
831 #define MPS_PORT_STAT_TX_PORT_64B_L 0x430
832 #define MPS_PORT_STAT_TX_PORT_64B_H 0x434
833 #define MPS_PORT_STAT_TX_PORT_65B_127B_L 0x438
834 #define MPS_PORT_STAT_TX_PORT_65B_127B_H 0x43c
835 #define MPS_PORT_STAT_TX_PORT_128B_255B_L 0x440
836 #define MPS_PORT_STAT_TX_PORT_128B_255B_H 0x444
837 #define MPS_PORT_STAT_TX_PORT_256B_511B_L 0x448
838 #define MPS_PORT_STAT_TX_PORT_256B_511B_H 0x44c
839 #define MPS_PORT_STAT_TX_PORT_512B_1023B_L 0x450
840 #define MPS_PORT_STAT_TX_PORT_512B_1023B_H 0x454
841 #define MPS_PORT_STAT_TX_PORT_1024B_1518B_L 0x458
842 #define MPS_PORT_STAT_TX_PORT_1024B_1518B_H 0x45c
843 #define MPS_PORT_STAT_TX_PORT_1519B_MAX_L 0x460
844 #define MPS_PORT_STAT_TX_PORT_1519B_MAX_H 0x464
845 #define MPS_PORT_STAT_TX_PORT_DROP_L 0x468
846 #define MPS_PORT_STAT_TX_PORT_DROP_H 0x46c
847 #define MPS_PORT_STAT_TX_PORT_PAUSE_L 0x470
848 #define MPS_PORT_STAT_TX_PORT_PAUSE_H 0x474
849 #define MPS_PORT_STAT_TX_PORT_PPP0_L 0x478
850 #define MPS_PORT_STAT_TX_PORT_PPP0_H 0x47c
851 #define MPS_PORT_STAT_TX_PORT_PPP1_L 0x480
852 #define MPS_PORT_STAT_TX_PORT_PPP1_H 0x484
853 #define MPS_PORT_STAT_TX_PORT_PPP2_L 0x488
854 #define MPS_PORT_STAT_TX_PORT_PPP2_H 0x48c
855 #define MPS_PORT_STAT_TX_PORT_PPP3_L 0x490
856 #define MPS_PORT_STAT_TX_PORT_PPP3_H 0x494
857 #define MPS_PORT_STAT_TX_PORT_PPP4_L 0x498
858 #define MPS_PORT_STAT_TX_PORT_PPP4_H 0x49c
859 #define MPS_PORT_STAT_TX_PORT_PPP5_L 0x4a0
860 #define MPS_PORT_STAT_TX_PORT_PPP5_H 0x4a4
861 #define MPS_PORT_STAT_TX_PORT_PPP6_L 0x4a8
862 #define MPS_PORT_STAT_TX_PORT_PPP6_H 0x4ac
863 #define MPS_PORT_STAT_TX_PORT_PPP7_L 0x4b0
864 #define MPS_PORT_STAT_TX_PORT_PPP7_H 0x4b4
865 #define MPS_PORT_STAT_LB_PORT_BYTES_L 0x4c0
866 #define MPS_PORT_STAT_LB_PORT_BYTES_H 0x4c4
867 #define MPS_PORT_STAT_LB_PORT_FRAMES_L 0x4c8
868 #define MPS_PORT_STAT_LB_PORT_FRAMES_H 0x4cc
869 #define MPS_PORT_STAT_LB_PORT_BCAST_L 0x4d0
870 #define MPS_PORT_STAT_LB_PORT_BCAST_H 0x4d4
871 #define MPS_PORT_STAT_LB_PORT_MCAST_L 0x4d8
872 #define MPS_PORT_STAT_LB_PORT_MCAST_H 0x4dc
873 #define MPS_PORT_STAT_LB_PORT_UCAST_L 0x4e0
874 #define MPS_PORT_STAT_LB_PORT_UCAST_H 0x4e4
875 #define MPS_PORT_STAT_LB_PORT_ERROR_L 0x4e8
876 #define MPS_PORT_STAT_LB_PORT_ERROR_H 0x4ec
877 #define MPS_PORT_STAT_LB_PORT_64B_L 0x4f0
878 #define MPS_PORT_STAT_LB_PORT_64B_H 0x4f4
879 #define MPS_PORT_STAT_LB_PORT_65B_127B_L 0x4f8
880 #define MPS_PORT_STAT_LB_PORT_65B_127B_H 0x4fc
881 #define MPS_PORT_STAT_LB_PORT_128B_255B_L 0x500
882 #define MPS_PORT_STAT_LB_PORT_128B_255B_H 0x504
883 #define MPS_PORT_STAT_LB_PORT_256B_511B_L 0x508
884 #define MPS_PORT_STAT_LB_PORT_256B_511B_H 0x50c
885 #define MPS_PORT_STAT_LB_PORT_512B_1023B_L 0x510
886 #define MPS_PORT_STAT_LB_PORT_512B_1023B_H 0x514
887 #define MPS_PORT_STAT_LB_PORT_1024B_1518B_L 0x518
888 #define MPS_PORT_STAT_LB_PORT_1024B_1518B_H 0x51c
889 #define MPS_PORT_STAT_LB_PORT_1519B_MAX_L 0x520
890 #define MPS_PORT_STAT_LB_PORT_1519B_MAX_H 0x524
891 #define MPS_PORT_STAT_LB_PORT_DROP_FRAMES 0x528
892 #define MPS_PORT_STAT_RX_PORT_BYTES_L 0x540
893 #define MPS_PORT_STAT_RX_PORT_BYTES_H 0x544
894 #define MPS_PORT_STAT_RX_PORT_FRAMES_L 0x548
895 #define MPS_PORT_STAT_RX_PORT_FRAMES_H 0x54c
896 #define MPS_PORT_STAT_RX_PORT_BCAST_L 0x550
897 #define MPS_PORT_STAT_RX_PORT_BCAST_H 0x554
898 #define MPS_PORT_STAT_RX_PORT_MCAST_L 0x558
899 #define MPS_PORT_STAT_RX_PORT_MCAST_H 0x55c
900 #define MPS_PORT_STAT_RX_PORT_UCAST_L 0x560
901 #define MPS_PORT_STAT_RX_PORT_UCAST_H 0x564
902 #define MPS_PORT_STAT_RX_PORT_MTU_ERROR_L 0x568
903 #define MPS_PORT_STAT_RX_PORT_MTU_ERROR_H 0x56c
904 #define MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L 0x570
905 #define MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H 0x574
906 #define MPS_PORT_STAT_RX_PORT_CRC_ERROR_L 0x578
907 #define MPS_PORT_STAT_RX_PORT_CRC_ERROR_H 0x57c
908 #define MPS_PORT_STAT_RX_PORT_LEN_ERROR_L 0x580
909 #define MPS_PORT_STAT_RX_PORT_LEN_ERROR_H 0x584
910 #define MPS_PORT_STAT_RX_PORT_SYM_ERROR_L 0x588
911 #define MPS_PORT_STAT_RX_PORT_SYM_ERROR_H 0x58c
912 #define MPS_PORT_STAT_RX_PORT_64B_L 0x590
913 #define MPS_PORT_STAT_RX_PORT_64B_H 0x594
914 #define MPS_PORT_STAT_RX_PORT_65B_127B_L 0x598
915 #define MPS_PORT_STAT_RX_PORT_65B_127B_H 0x59c
916 #define MPS_PORT_STAT_RX_PORT_128B_255B_L 0x5a0
917 #define MPS_PORT_STAT_RX_PORT_128B_255B_H 0x5a4
918 #define MPS_PORT_STAT_RX_PORT_256B_511B_L 0x5a8
919 #define MPS_PORT_STAT_RX_PORT_256B_511B_H 0x5ac
920 #define MPS_PORT_STAT_RX_PORT_512B_1023B_L 0x5b0
921 #define MPS_PORT_STAT_RX_PORT_512B_1023B_H 0x5b4
922 #define MPS_PORT_STAT_RX_PORT_1024B_1518B_L 0x5b8
923 #define MPS_PORT_STAT_RX_PORT_1024B_1518B_H 0x5bc
924 #define MPS_PORT_STAT_RX_PORT_1519B_MAX_L 0x5c0
925 #define MPS_PORT_STAT_RX_PORT_1519B_MAX_H 0x5c4
926 #define MPS_PORT_STAT_RX_PORT_PAUSE_L 0x5c8
927 #define MPS_PORT_STAT_RX_PORT_PAUSE_H 0x5cc
928 #define MPS_PORT_STAT_RX_PORT_PPP0_L 0x5d0
929 #define MPS_PORT_STAT_RX_PORT_PPP0_H 0x5d4
930 #define MPS_PORT_STAT_RX_PORT_PPP1_L 0x5d8
931 #define MPS_PORT_STAT_RX_PORT_PPP1_H 0x5dc
932 #define MPS_PORT_STAT_RX_PORT_PPP2_L 0x5e0
933 #define MPS_PORT_STAT_RX_PORT_PPP2_H 0x5e4
934 #define MPS_PORT_STAT_RX_PORT_PPP3_L 0x5e8
935 #define MPS_PORT_STAT_RX_PORT_PPP3_H 0x5ec
936 #define MPS_PORT_STAT_RX_PORT_PPP4_L 0x5f0
937 #define MPS_PORT_STAT_RX_PORT_PPP4_H 0x5f4
938 #define MPS_PORT_STAT_RX_PORT_PPP5_L 0x5f8
939 #define MPS_PORT_STAT_RX_PORT_PPP5_H 0x5fc
940 #define MPS_PORT_STAT_RX_PORT_PPP6_L 0x600
941 #define MPS_PORT_STAT_RX_PORT_PPP6_H 0x604
942 #define MPS_PORT_STAT_RX_PORT_PPP7_L 0x608
943 #define MPS_PORT_STAT_RX_PORT_PPP7_H 0x60c
944 #define MPS_PORT_STAT_RX_PORT_LESS_64B_L 0x610
945 #define MPS_PORT_STAT_RX_PORT_LESS_64B_H 0x614
946 #define MAC_PORT_CFG2 0x818
947 #define MAC_PORT_MAGIC_MACID_LO 0x824
948 #define MAC_PORT_MAGIC_MACID_HI 0x828
949 #define MAC_PORT_EPIO_DATA0 0x8c0
950 #define MAC_PORT_EPIO_DATA1 0x8c4
951 #define MAC_PORT_EPIO_DATA2 0x8c8
952 #define MAC_PORT_EPIO_DATA3 0x8cc
953 #define MAC_PORT_EPIO_OP 0x8d0
955 #define MPS_CMN_CTL 0x9000
956 #define NUMPORTS_MASK 0x00000003U
957 #define NUMPORTS_SHIFT 0
958 #define NUMPORTS_GET(x) (((x) & NUMPORTS_MASK) >> NUMPORTS_SHIFT)
960 #define MPS_INT_CAUSE 0x9008
961 #define STATINT 0x00000020U
962 #define TXINT 0x00000010U
963 #define RXINT 0x00000008U
964 #define TRCINT 0x00000004U
965 #define CLSINT 0x00000002U
966 #define PLINT 0x00000001U
968 #define MPS_TX_INT_CAUSE 0x9408
969 #define PORTERR 0x00010000U
970 #define FRMERR 0x00008000U
971 #define SECNTERR 0x00004000U
972 #define BUBBLE 0x00002000U
973 #define TXDESCFIFO 0x00001e00U
974 #define TXDATAFIFO 0x000001e0U
975 #define NCSIFIFO 0x00000010U
976 #define TPFIFO 0x0000000fU
978 #define MPS_STAT_PERR_INT_CAUSE_SRAM 0x9614
979 #define MPS_STAT_PERR_INT_CAUSE_TX_FIFO 0x9620
980 #define MPS_STAT_PERR_INT_CAUSE_RX_FIFO 0x962c
982 #define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L 0x9640
983 #define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_H 0x9644
984 #define MPS_STAT_RX_BG_1_MAC_DROP_FRAME_L 0x9648
985 #define MPS_STAT_RX_BG_1_MAC_DROP_FRAME_H 0x964c
986 #define MPS_STAT_RX_BG_2_MAC_DROP_FRAME_L 0x9650
987 #define MPS_STAT_RX_BG_2_MAC_DROP_FRAME_H 0x9654
988 #define MPS_STAT_RX_BG_3_MAC_DROP_FRAME_L 0x9658
989 #define MPS_STAT_RX_BG_3_MAC_DROP_FRAME_H 0x965c
990 #define MPS_STAT_RX_BG_0_LB_DROP_FRAME_L 0x9660
991 #define MPS_STAT_RX_BG_0_LB_DROP_FRAME_H 0x9664
992 #define MPS_STAT_RX_BG_1_LB_DROP_FRAME_L 0x9668
993 #define MPS_STAT_RX_BG_1_LB_DROP_FRAME_H 0x966c
994 #define MPS_STAT_RX_BG_2_LB_DROP_FRAME_L 0x9670
995 #define MPS_STAT_RX_BG_2_LB_DROP_FRAME_H 0x9674
996 #define MPS_STAT_RX_BG_3_LB_DROP_FRAME_L 0x9678
997 #define MPS_STAT_RX_BG_3_LB_DROP_FRAME_H 0x967c
998 #define MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L 0x9680
999 #define MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_H 0x9684
1000 #define MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_L 0x9688
1001 #define MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_H 0x968c
1002 #define MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_L 0x9690
1003 #define MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_H 0x9694
1004 #define MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_L 0x9698
1005 #define MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_H 0x969c
1006 #define MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_L 0x96a0
1007 #define MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_H 0x96a4
1008 #define MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_L 0x96a8
1009 #define MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_H 0x96ac
1010 #define MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_L 0x96b0
1011 #define MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_H 0x96b4
1012 #define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_L 0x96b8
1013 #define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_H 0x96bc
1014 #define MPS_TRC_CFG 0x9800
1015 #define TRCFIFOEMPTY 0x00000010U
1016 #define TRCIGNOREDROPINPUT 0x00000008U
1017 #define TRCKEEPDUPLICATES 0x00000004U
1018 #define TRCEN 0x00000002U
1019 #define TRCMULTIFILTER 0x00000001U
1021 #define MPS_TRC_RSS_CONTROL 0x9808
1022 #define MPS_T5_TRC_RSS_CONTROL 0xa00c
1023 #define RSSCONTROL_MASK 0x00ff0000U
1024 #define RSSCONTROL_SHIFT 16
1025 #define RSSCONTROL(x) ((x) << RSSCONTROL_SHIFT)
1026 #define QUEUENUMBER_MASK 0x0000ffffU
1027 #define QUEUENUMBER_SHIFT 0
1028 #define QUEUENUMBER(x) ((x) << QUEUENUMBER_SHIFT)
1030 #define MPS_TRC_FILTER_MATCH_CTL_A 0x9810
1031 #define TFINVERTMATCH 0x01000000U
1032 #define TFPKTTOOLARGE 0x00800000U
1033 #define TFEN 0x00400000U
1034 #define TFPORT_MASK 0x003c0000U
1035 #define TFPORT_SHIFT 18
1036 #define TFPORT(x) ((x) << TFPORT_SHIFT)
1037 #define TFPORT_GET(x) (((x) & TFPORT_MASK) >> TFPORT_SHIFT)
1038 #define TFDROP 0x00020000U
1039 #define TFSOPEOPERR 0x00010000U
1040 #define TFLENGTH_MASK 0x00001f00U
1041 #define TFLENGTH_SHIFT 8
1042 #define TFLENGTH(x) ((x) << TFLENGTH_SHIFT)
1043 #define TFLENGTH_GET(x) (((x) & TFLENGTH_MASK) >> TFLENGTH_SHIFT)
1044 #define TFOFFSET_MASK 0x0000001fU
1045 #define TFOFFSET_SHIFT 0
1046 #define TFOFFSET(x) ((x) << TFOFFSET_SHIFT)
1047 #define TFOFFSET_GET(x) (((x) & TFOFFSET_MASK) >> TFOFFSET_SHIFT)
1049 #define MPS_TRC_FILTER_MATCH_CTL_B 0x9820
1050 #define TFMINPKTSIZE_MASK 0x01ff0000U
1051 #define TFMINPKTSIZE_SHIFT 16
1052 #define TFMINPKTSIZE(x) ((x) << TFMINPKTSIZE_SHIFT)
1053 #define TFMINPKTSIZE_GET(x) (((x) & TFMINPKTSIZE_MASK) >> TFMINPKTSIZE_SHIFT)
1054 #define TFCAPTUREMAX_MASK 0x00003fffU
1055 #define TFCAPTUREMAX_SHIFT 0
1056 #define TFCAPTUREMAX(x) ((x) << TFCAPTUREMAX_SHIFT)
1057 #define TFCAPTUREMAX_GET(x) (((x) & TFCAPTUREMAX_MASK) >> TFCAPTUREMAX_SHIFT)
1059 #define MPS_TRC_INT_CAUSE 0x985c
1060 #define MISCPERR 0x00000100U
1061 #define PKTFIFO 0x000000f0U
1062 #define FILTMEM 0x0000000fU
1064 #define MPS_TRC_FILTER0_MATCH 0x9c00
1065 #define MPS_TRC_FILTER0_DONT_CARE 0x9c80
1066 #define MPS_TRC_FILTER1_MATCH 0x9d00
1067 #define MPS_CLS_INT_CAUSE 0xd028
1068 #define PLERRENB 0x00000008U
1069 #define HASHSRAM 0x00000004U
1070 #define MATCHTCAM 0x00000002U
1071 #define MATCHSRAM 0x00000001U
1073 #define MPS_RX_PERR_INT_CAUSE 0x11074
1075 #define CPL_INTR_CAUSE 0x19054
1076 #define CIM_OP_MAP_PERR 0x00000020U
1077 #define CIM_OVFL_ERROR 0x00000010U
1078 #define TP_FRAMING_ERROR 0x00000008U
1079 #define SGE_FRAMING_ERROR 0x00000004U
1080 #define CIM_FRAMING_ERROR 0x00000002U
1081 #define ZERO_SWITCH_ERROR 0x00000001U
1083 #define SMB_INT_CAUSE 0x19090
1084 #define MSTTXFIFOPARINT 0x00200000U
1085 #define MSTRXFIFOPARINT 0x00100000U
1086 #define SLVFIFOPARINT 0x00080000U
1088 #define ULP_RX_INT_CAUSE 0x19158
1089 #define ULP_RX_ISCSI_TAGMASK 0x19164
1090 #define ULP_RX_ISCSI_PSZ 0x19168
1091 #define HPZ3_MASK 0x0f000000U
1092 #define HPZ3_SHIFT 24
1093 #define HPZ3(x) ((x) << HPZ3_SHIFT)
1094 #define HPZ2_MASK 0x000f0000U
1095 #define HPZ2_SHIFT 16
1096 #define HPZ2(x) ((x) << HPZ2_SHIFT)
1097 #define HPZ1_MASK 0x00000f00U
1098 #define HPZ1_SHIFT 8
1099 #define HPZ1(x) ((x) << HPZ1_SHIFT)
1100 #define HPZ0_MASK 0x0000000fU
1101 #define HPZ0_SHIFT 0
1102 #define HPZ0(x) ((x) << HPZ0_SHIFT)
1104 #define ULP_RX_TDDP_PSZ 0x19178
1106 #define SF_DATA 0x193f8
1107 #define SF_OP 0x193fc
1108 #define SF_BUSY 0x80000000U
1109 #define SF_LOCK 0x00000010U
1110 #define SF_CONT 0x00000008U
1111 #define BYTECNT_MASK 0x00000006U
1112 #define BYTECNT_SHIFT 1
1113 #define BYTECNT(x) ((x) << BYTECNT_SHIFT)
1114 #define OP_WR 0x00000001U
1116 #define PL_PF_INT_CAUSE 0x3c0
1117 #define PFSW 0x00000008U
1118 #define PFSGE 0x00000004U
1119 #define PFCIM 0x00000002U
1120 #define PFMPS 0x00000001U
1122 #define PL_PF_INT_ENABLE 0x3c4
1123 #define PL_PF_CTL 0x3c8
1124 #define SWINT 0x00000001U
1126 #define PL_WHOAMI 0x19400
1127 #define SOURCEPF_MASK 0x00000700U
1128 #define SOURCEPF_SHIFT 8
1129 #define SOURCEPF(x) ((x) << SOURCEPF_SHIFT)
1130 #define SOURCEPF_GET(x) (((x) & SOURCEPF_MASK) >> SOURCEPF_SHIFT)
1131 #define ISVF 0x00000080U
1132 #define VFID_MASK 0x0000007fU
1133 #define VFID_SHIFT 0
1134 #define VFID(x) ((x) << VFID_SHIFT)
1135 #define VFID_GET(x) (((x) & VFID_MASK) >> VFID_SHIFT)
1137 #define PL_INT_CAUSE 0x1940c
1138 #define ULP_TX 0x08000000U
1139 #define SGE 0x04000000U
1140 #define HMA 0x02000000U
1141 #define CPL_SWITCH 0x01000000U
1142 #define ULP_RX 0x00800000U
1143 #define PM_RX 0x00400000U
1144 #define PM_TX 0x00200000U
1145 #define MA 0x00100000U
1146 #define TP 0x00080000U
1147 #define LE 0x00040000U
1148 #define EDC1 0x00020000U
1149 #define EDC0 0x00010000U
1150 #define MC 0x00008000U
1151 #define PCIE 0x00004000U
1152 #define PMU 0x00002000U
1153 #define XGMAC_KR1 0x00001000U
1154 #define XGMAC_KR0 0x00000800U
1155 #define XGMAC1 0x00000400U
1156 #define XGMAC0 0x00000200U
1157 #define SMB 0x00000100U
1158 #define SF 0x00000080U
1159 #define PL 0x00000040U
1160 #define NCSI 0x00000020U
1161 #define MPS 0x00000010U
1162 #define MI 0x00000008U
1163 #define DBG 0x00000004U
1164 #define I2CM 0x00000002U
1165 #define CIM 0x00000001U
1168 #define PL_INT_ENABLE 0x19410
1169 #define PL_INT_MAP0 0x19414
1170 #define PL_RST 0x19428
1171 #define PIORST 0x00000002U
1172 #define PIORSTMODE 0x00000001U
1174 #define PL_PL_INT_CAUSE 0x19430
1175 #define FATALPERR 0x00000010U
1176 #define PERRVFID 0x00000001U
1178 #define PL_REV 0x1943c
1182 #define V_REV(x) ((x) << S_REV)
1183 #define G_REV(x) (((x) >> S_REV) & M_REV)
1185 #define LE_DB_CONFIG 0x19c04
1186 #define HASHEN 0x00100000U
1188 #define LE_DB_SERVER_INDEX 0x19c18
1189 #define LE_DB_ACT_CNT_IPV4 0x19c20
1190 #define LE_DB_ACT_CNT_IPV6 0x19c24
1192 #define LE_DB_INT_CAUSE 0x19c3c
1193 #define REQQPARERR 0x00010000U
1194 #define UNKNOWNCMD 0x00008000U
1195 #define PARITYERR 0x00000040U
1196 #define LIPMISS 0x00000020U
1197 #define LIP0 0x00000010U
1199 #define LE_DB_TID_HASHBASE 0x19df8
1201 #define NCSI_INT_CAUSE 0x1a0d8
1202 #define CIM_DM_PRTY_ERR 0x00000100U
1203 #define MPS_DM_PRTY_ERR 0x00000080U
1204 #define TXFIFO_PRTY_ERR 0x00000002U
1205 #define RXFIFO_PRTY_ERR 0x00000001U
1207 #define XGMAC_PORT_CFG2 0x1018
1208 #define PATEN 0x00040000U
1209 #define MAGICEN 0x00020000U
1211 #define XGMAC_PORT_MAGIC_MACID_LO 0x1024
1212 #define XGMAC_PORT_MAGIC_MACID_HI 0x1028
1214 #define XGMAC_PORT_EPIO_DATA0 0x10c0
1215 #define XGMAC_PORT_EPIO_DATA1 0x10c4
1216 #define XGMAC_PORT_EPIO_DATA2 0x10c8
1217 #define XGMAC_PORT_EPIO_DATA3 0x10cc
1218 #define XGMAC_PORT_EPIO_OP 0x10d0
1219 #define EPIOWR 0x00000100U
1220 #define ADDRESS_MASK 0x000000ffU
1221 #define ADDRESS_SHIFT 0
1222 #define ADDRESS(x) ((x) << ADDRESS_SHIFT)
1224 #define MAC_PORT_INT_CAUSE 0x8dc
1225 #define XGMAC_PORT_INT_CAUSE 0x10dc
1227 #define A_TP_TX_MOD_QUEUE_REQ_MAP 0x7e28
1229 #define A_TP_TX_MOD_CHANNEL_WEIGHT 0x7e34
1231 #define S_TX_MOD_QUEUE_REQ_MAP 0
1232 #define M_TX_MOD_QUEUE_REQ_MAP 0xffffU
1233 #define V_TX_MOD_QUEUE_REQ_MAP(x) ((x) << S_TX_MOD_QUEUE_REQ_MAP)
1235 #define A_TP_TX_MOD_QUEUE_WEIGHT0 0x7e30
1237 #define S_TX_MODQ_WEIGHT3 24
1238 #define M_TX_MODQ_WEIGHT3 0xffU
1239 #define V_TX_MODQ_WEIGHT3(x) ((x) << S_TX_MODQ_WEIGHT3)
1241 #define S_TX_MODQ_WEIGHT2 16
1242 #define M_TX_MODQ_WEIGHT2 0xffU
1243 #define V_TX_MODQ_WEIGHT2(x) ((x) << S_TX_MODQ_WEIGHT2)
1245 #define S_TX_MODQ_WEIGHT1 8
1246 #define M_TX_MODQ_WEIGHT1 0xffU
1247 #define V_TX_MODQ_WEIGHT1(x) ((x) << S_TX_MODQ_WEIGHT1)
1249 #define S_TX_MODQ_WEIGHT0 0
1250 #define M_TX_MODQ_WEIGHT0 0xffU
1251 #define V_TX_MODQ_WEIGHT0(x) ((x) << S_TX_MODQ_WEIGHT0)
1253 #define A_TP_TX_SCHED_HDR 0x23
1255 #define A_TP_TX_SCHED_FIFO 0x24
1257 #define A_TP_TX_SCHED_PCMD 0x25
1260 #define V_VNIC(x) ((x) << S_VNIC)
1261 #define F_VNIC V_VNIC(1U)
1263 #define S_FRAGMENTATION 9
1264 #define V_FRAGMENTATION(x) ((x) << S_FRAGMENTATION)
1265 #define F_FRAGMENTATION V_FRAGMENTATION(1U)
1267 #define S_MPSHITTYPE 8
1268 #define V_MPSHITTYPE(x) ((x) << S_MPSHITTYPE)
1269 #define F_MPSHITTYPE V_MPSHITTYPE(1U)
1271 #define S_MACMATCH 7
1272 #define V_MACMATCH(x) ((x) << S_MACMATCH)
1273 #define F_MACMATCH V_MACMATCH(1U)
1275 #define S_ETHERTYPE 6
1276 #define V_ETHERTYPE(x) ((x) << S_ETHERTYPE)
1277 #define F_ETHERTYPE V_ETHERTYPE(1U)
1279 #define S_PROTOCOL 5
1280 #define V_PROTOCOL(x) ((x) << S_PROTOCOL)
1281 #define F_PROTOCOL V_PROTOCOL(1U)
1284 #define V_TOS(x) ((x) << S_TOS)
1285 #define F_TOS V_TOS(1U)
1288 #define V_VLAN(x) ((x) << S_VLAN)
1289 #define F_VLAN V_VLAN(1U)
1292 #define V_VNIC_ID(x) ((x) << S_VNIC_ID)
1293 #define F_VNIC_ID V_VNIC_ID(1U)
1296 #define V_PORT(x) ((x) << S_PORT)
1297 #define F_PORT V_PORT(1U)
1300 #define V_FCOE(x) ((x) << S_FCOE)
1301 #define F_FCOE V_FCOE(1U)
1303 #define NUM_MPS_CLS_SRAM_L_INSTANCES 336
1304 #define NUM_MPS_T5_CLS_SRAM_L_INSTANCES 512
1306 #define T5_PORT0_BASE 0x30000
1307 #define T5_PORT_STRIDE 0x4000
1308 #define T5_PORT_BASE(idx) (T5_PORT0_BASE + (idx) * T5_PORT_STRIDE)
1309 #define T5_PORT_REG(idx, reg) (T5_PORT_BASE(idx) + (reg))
1311 #define MC_0_BASE_ADDR 0x40000
1312 #define MC_1_BASE_ADDR 0x48000
1313 #define MC_STRIDE (MC_1_BASE_ADDR - MC_0_BASE_ADDR)
1314 #define MC_REG(reg, idx) (reg + MC_STRIDE * idx)
1316 #define MC_P_BIST_CMD 0x41400
1317 #define MC_P_BIST_CMD_ADDR 0x41404
1318 #define MC_P_BIST_CMD_LEN 0x41408
1319 #define MC_P_BIST_DATA_PATTERN 0x4140c
1320 #define MC_P_BIST_STATUS_RDATA 0x41488
1321 #define EDC_T50_BASE_ADDR 0x50000
1322 #define EDC_H_BIST_CMD 0x50004
1323 #define EDC_H_BIST_CMD_ADDR 0x50008
1324 #define EDC_H_BIST_CMD_LEN 0x5000c
1325 #define EDC_H_BIST_DATA_PATTERN 0x50010
1326 #define EDC_H_BIST_STATUS_RDATA 0x50028
1328 #define EDC_T51_BASE_ADDR 0x50800
1329 #define EDC_STRIDE_T5 (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR)
1330 #define EDC_REG_T5(reg, idx) (reg + EDC_STRIDE_T5 * idx)
1332 #define A_PL_VF_REV 0x4
1333 #define A_PL_VF_WHOAMI 0x0
1334 #define A_PL_VF_REVISION 0x8
1337 #define M_CHIPID 0xfU
1338 #define V_CHIPID(x) ((x) << S_CHIPID)
1339 #define G_CHIPID(x) (((x) >> S_CHIPID) & M_CHIPID)
1341 /* TP_VLAN_PRI_MAP controls which subset of fields will be present in the
1342 * Compressed Filter Tuple for LE filters. Each bit set in TP_VLAN_PRI_MAP
1343 * selects for a particular field being present. These fields, when present
1344 * in the Compressed Filter Tuple, have the following widths in bits.
1348 #define W_FT_VNIC_ID 17
1349 #define W_FT_VLAN 17
1351 #define W_FT_PROTOCOL 8
1352 #define W_FT_ETHERTYPE 16
1353 #define W_FT_MACMATCH 9
1354 #define W_FT_MPSHITTYPE 3
1355 #define W_FT_FRAGMENTATION 1
1357 /* Some of the Compressed Filter Tuple fields have internal structure. These
1358 * bit shifts/masks describe those structures. All shifts are relative to the
1359 * base position of the fields within the Compressed Filter Tuple
1361 #define S_FT_VLAN_VLD 16
1362 #define V_FT_VLAN_VLD(x) ((x) << S_FT_VLAN_VLD)
1363 #define F_FT_VLAN_VLD V_FT_VLAN_VLD(1U)
1365 #define S_FT_VNID_ID_VF 0
1366 #define V_FT_VNID_ID_VF(x) ((x) << S_FT_VNID_ID_VF)
1368 #define S_FT_VNID_ID_PF 7
1369 #define V_FT_VNID_ID_PF(x) ((x) << S_FT_VNID_ID_PF)
1371 #define S_FT_VNID_ID_VLD 16
1372 #define V_FT_VNID_ID_VLD(x) ((x) << S_FT_VNID_ID_VLD)
1374 #endif /* __T4_REGS_H */