2 * This file is part of the Chelsio T4 PCI-E SR-IOV Virtual Function Ethernet
5 * Copyright (c) 2009-2010 Chelsio Communications, Inc. All rights reserved.
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/skbuff.h>
37 #include <linux/netdevice.h>
38 #include <linux/etherdevice.h>
39 #include <linux/if_vlan.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/prefetch.h>
46 #include "t4vf_common.h"
47 #include "t4vf_defs.h"
49 #include "../cxgb4/t4_regs.h"
50 #include "../cxgb4/t4fw_api.h"
51 #include "../cxgb4/t4_msg.h"
58 * Egress Queue sizes, producer and consumer indices are all in units
59 * of Egress Context Units bytes. Note that as far as the hardware is
60 * concerned, the free list is an Egress Queue (the host produces free
61 * buffers which the hardware consumes) and free list entries are
62 * 64-bit PCI DMA addresses.
64 EQ_UNIT = SGE_EQ_IDXSIZE,
65 FL_PER_EQ_UNIT = EQ_UNIT / sizeof(__be64),
66 TXD_PER_EQ_UNIT = EQ_UNIT / sizeof(__be64),
69 * Max number of TX descriptors we clean up at a time. Should be
70 * modest as freeing skbs isn't cheap and it happens while holding
71 * locks. We just need to free packets faster than they arrive, we
72 * eventually catch up and keep the amortized cost reasonable.
77 * Max number of Rx buffers we replenish at a time. Again keep this
78 * modest, allocating buffers isn't cheap either.
83 * Period of the Rx queue check timer. This timer is infrequent as it
84 * has something to do only when the system experiences severe memory
87 RX_QCHECK_PERIOD = (HZ / 2),
90 * Period of the TX queue check timer and the maximum number of TX
91 * descriptors to be reclaimed by the TX timer.
93 TX_QCHECK_PERIOD = (HZ / 2),
94 MAX_TIMER_TX_RECLAIM = 100,
97 * Suspend an Ethernet TX queue with fewer available descriptors than
98 * this. We always want to have room for a maximum sized packet:
99 * inline immediate data + MAX_SKB_FRAGS. This is the same as
100 * calc_tx_flits() for a TSO packet with nr_frags == MAX_SKB_FRAGS
101 * (see that function and its helpers for a description of the
104 ETHTXQ_MAX_FRAGS = MAX_SKB_FRAGS + 1,
105 ETHTXQ_MAX_SGL_LEN = ((3 * (ETHTXQ_MAX_FRAGS-1))/2 +
106 ((ETHTXQ_MAX_FRAGS-1) & 1) +
108 ETHTXQ_MAX_HDR = (sizeof(struct fw_eth_tx_pkt_vm_wr) +
109 sizeof(struct cpl_tx_pkt_lso_core) +
110 sizeof(struct cpl_tx_pkt_core)) / sizeof(__be64),
111 ETHTXQ_MAX_FLITS = ETHTXQ_MAX_SGL_LEN + ETHTXQ_MAX_HDR,
113 ETHTXQ_STOP_THRES = 1 + DIV_ROUND_UP(ETHTXQ_MAX_FLITS, TXD_PER_EQ_UNIT),
116 * Max TX descriptor space we allow for an Ethernet packet to be
117 * inlined into a WR. This is limited by the maximum value which
118 * we can specify for immediate data in the firmware Ethernet TX
121 MAX_IMM_TX_PKT_LEN = FW_WR_IMMDLEN_MASK,
124 * Max size of a WR sent through a control TX queue.
126 MAX_CTRL_WR_LEN = 256,
129 * Maximum amount of data which we'll ever need to inline into a
130 * TX ring: max(MAX_IMM_TX_PKT_LEN, MAX_CTRL_WR_LEN).
132 MAX_IMM_TX_LEN = (MAX_IMM_TX_PKT_LEN > MAX_CTRL_WR_LEN
137 * For incoming packets less than RX_COPY_THRES, we copy the data into
138 * an skb rather than referencing the data. We allocate enough
139 * in-line room in skb's to accommodate pulling in RX_PULL_LEN bytes
140 * of the data (header).
146 * Main body length for sk_buffs used for RX Ethernet packets with
147 * fragments. Should be >= RX_PULL_LEN but possibly bigger to give
148 * pskb_may_pull() some room.
154 * Software state per TX descriptor.
157 struct sk_buff *skb; /* socket buffer of TX data source */
158 struct ulptx_sgl *sgl; /* scatter/gather list in TX Queue */
162 * Software state per RX Free List descriptor. We keep track of the allocated
163 * FL page, its size, and its PCI DMA address (if the page is mapped). The FL
164 * page size and its PCI DMA mapped state are stored in the low bits of the
165 * PCI DMA address as per below.
168 struct page *page; /* Free List page buffer */
169 dma_addr_t dma_addr; /* PCI DMA address (if mapped) */
170 /* and flags (see below) */
174 * The low bits of rx_sw_desc.dma_addr have special meaning. Note that the
175 * SGE also uses the low 4 bits to determine the size of the buffer. It uses
176 * those bits to index into the SGE_FL_BUFFER_SIZE[index] register array.
177 * Since we only use SGE_FL_BUFFER_SIZE0 and SGE_FL_BUFFER_SIZE1, these low 4
178 * bits can only contain a 0 or a 1 to indicate which size buffer we're giving
179 * to the SGE. Thus, our software state of "is the buffer mapped for DMA" is
180 * maintained in an inverse sense so the hardware never sees that bit high.
183 RX_LARGE_BUF = 1 << 0, /* buffer is SGE_FL_BUFFER_SIZE[1] */
184 RX_UNMAPPED_BUF = 1 << 1, /* buffer is not mapped */
188 * get_buf_addr - return DMA buffer address of software descriptor
189 * @sdesc: pointer to the software buffer descriptor
191 * Return the DMA buffer address of a software descriptor (stripping out
192 * our low-order flag bits).
194 static inline dma_addr_t get_buf_addr(const struct rx_sw_desc *sdesc)
196 return sdesc->dma_addr & ~(dma_addr_t)(RX_LARGE_BUF | RX_UNMAPPED_BUF);
200 * is_buf_mapped - is buffer mapped for DMA?
201 * @sdesc: pointer to the software buffer descriptor
203 * Determine whether the buffer associated with a software descriptor in
204 * mapped for DMA or not.
206 static inline bool is_buf_mapped(const struct rx_sw_desc *sdesc)
208 return !(sdesc->dma_addr & RX_UNMAPPED_BUF);
212 * need_skb_unmap - does the platform need unmapping of sk_buffs?
214 * Returns true if the platform needs sk_buff unmapping. The compiler
215 * optimizes away unnecessary code if this returns true.
217 static inline int need_skb_unmap(void)
219 #ifdef CONFIG_NEED_DMA_MAP_STATE
227 * txq_avail - return the number of available slots in a TX queue
230 * Returns the number of available descriptors in a TX queue.
232 static inline unsigned int txq_avail(const struct sge_txq *tq)
234 return tq->size - 1 - tq->in_use;
238 * fl_cap - return the capacity of a Free List
241 * Returns the capacity of a Free List. The capacity is less than the
242 * size because an Egress Queue Index Unit worth of descriptors needs to
243 * be left unpopulated, otherwise the Producer and Consumer indices PIDX
244 * and CIDX will match and the hardware will think the FL is empty.
246 static inline unsigned int fl_cap(const struct sge_fl *fl)
248 return fl->size - FL_PER_EQ_UNIT;
252 * fl_starving - return whether a Free List is starving.
253 * @adapter: pointer to the adapter
256 * Tests specified Free List to see whether the number of buffers
257 * available to the hardware has falled below our "starvation"
260 static inline bool fl_starving(const struct adapter *adapter,
261 const struct sge_fl *fl)
263 const struct sge *s = &adapter->sge;
265 return fl->avail - fl->pend_cred <= s->fl_starve_thres;
269 * map_skb - map an skb for DMA to the device
270 * @dev: the egress net device
271 * @skb: the packet to map
272 * @addr: a pointer to the base of the DMA mapping array
274 * Map an skb for DMA to the device and return an array of DMA addresses.
276 static int map_skb(struct device *dev, const struct sk_buff *skb,
279 const skb_frag_t *fp, *end;
280 const struct skb_shared_info *si;
282 *addr = dma_map_single(dev, skb->data, skb_headlen(skb), DMA_TO_DEVICE);
283 if (dma_mapping_error(dev, *addr))
286 si = skb_shinfo(skb);
287 end = &si->frags[si->nr_frags];
288 for (fp = si->frags; fp < end; fp++) {
289 *++addr = skb_frag_dma_map(dev, fp, 0, skb_frag_size(fp),
291 if (dma_mapping_error(dev, *addr))
297 while (fp-- > si->frags)
298 dma_unmap_page(dev, *--addr, skb_frag_size(fp), DMA_TO_DEVICE);
299 dma_unmap_single(dev, addr[-1], skb_headlen(skb), DMA_TO_DEVICE);
305 static void unmap_sgl(struct device *dev, const struct sk_buff *skb,
306 const struct ulptx_sgl *sgl, const struct sge_txq *tq)
308 const struct ulptx_sge_pair *p;
309 unsigned int nfrags = skb_shinfo(skb)->nr_frags;
311 if (likely(skb_headlen(skb)))
312 dma_unmap_single(dev, be64_to_cpu(sgl->addr0),
313 be32_to_cpu(sgl->len0), DMA_TO_DEVICE);
315 dma_unmap_page(dev, be64_to_cpu(sgl->addr0),
316 be32_to_cpu(sgl->len0), DMA_TO_DEVICE);
321 * the complexity below is because of the possibility of a wrap-around
322 * in the middle of an SGL
324 for (p = sgl->sge; nfrags >= 2; nfrags -= 2) {
325 if (likely((u8 *)(p + 1) <= (u8 *)tq->stat)) {
327 dma_unmap_page(dev, be64_to_cpu(p->addr[0]),
328 be32_to_cpu(p->len[0]), DMA_TO_DEVICE);
329 dma_unmap_page(dev, be64_to_cpu(p->addr[1]),
330 be32_to_cpu(p->len[1]), DMA_TO_DEVICE);
332 } else if ((u8 *)p == (u8 *)tq->stat) {
333 p = (const struct ulptx_sge_pair *)tq->desc;
335 } else if ((u8 *)p + 8 == (u8 *)tq->stat) {
336 const __be64 *addr = (const __be64 *)tq->desc;
338 dma_unmap_page(dev, be64_to_cpu(addr[0]),
339 be32_to_cpu(p->len[0]), DMA_TO_DEVICE);
340 dma_unmap_page(dev, be64_to_cpu(addr[1]),
341 be32_to_cpu(p->len[1]), DMA_TO_DEVICE);
342 p = (const struct ulptx_sge_pair *)&addr[2];
344 const __be64 *addr = (const __be64 *)tq->desc;
346 dma_unmap_page(dev, be64_to_cpu(p->addr[0]),
347 be32_to_cpu(p->len[0]), DMA_TO_DEVICE);
348 dma_unmap_page(dev, be64_to_cpu(addr[0]),
349 be32_to_cpu(p->len[1]), DMA_TO_DEVICE);
350 p = (const struct ulptx_sge_pair *)&addr[1];
356 if ((u8 *)p == (u8 *)tq->stat)
357 p = (const struct ulptx_sge_pair *)tq->desc;
358 addr = ((u8 *)p + 16 <= (u8 *)tq->stat
360 : *(const __be64 *)tq->desc);
361 dma_unmap_page(dev, be64_to_cpu(addr), be32_to_cpu(p->len[0]),
367 * free_tx_desc - reclaims TX descriptors and their buffers
368 * @adapter: the adapter
369 * @tq: the TX queue to reclaim descriptors from
370 * @n: the number of descriptors to reclaim
371 * @unmap: whether the buffers should be unmapped for DMA
373 * Reclaims TX descriptors from an SGE TX queue and frees the associated
374 * TX buffers. Called with the TX queue lock held.
376 static void free_tx_desc(struct adapter *adapter, struct sge_txq *tq,
377 unsigned int n, bool unmap)
379 struct tx_sw_desc *sdesc;
380 unsigned int cidx = tq->cidx;
381 struct device *dev = adapter->pdev_dev;
383 const int need_unmap = need_skb_unmap() && unmap;
385 sdesc = &tq->sdesc[cidx];
388 * If we kept a reference to the original TX skb, we need to
389 * unmap it from PCI DMA space (if required) and free it.
393 unmap_sgl(dev, sdesc->skb, sdesc->sgl, tq);
394 dev_consume_skb_any(sdesc->skb);
399 if (++cidx == tq->size) {
408 * Return the number of reclaimable descriptors in a TX queue.
410 static inline int reclaimable(const struct sge_txq *tq)
412 int hw_cidx = be16_to_cpu(tq->stat->cidx);
413 int reclaimable = hw_cidx - tq->cidx;
415 reclaimable += tq->size;
420 * reclaim_completed_tx - reclaims completed TX descriptors
421 * @adapter: the adapter
422 * @tq: the TX queue to reclaim completed descriptors from
423 * @unmap: whether the buffers should be unmapped for DMA
425 * Reclaims TX descriptors that the SGE has indicated it has processed,
426 * and frees the associated buffers if possible. Called with the TX
429 static inline void reclaim_completed_tx(struct adapter *adapter,
433 int avail = reclaimable(tq);
437 * Limit the amount of clean up work we do at a time to keep
438 * the TX lock hold time O(1).
440 if (avail > MAX_TX_RECLAIM)
441 avail = MAX_TX_RECLAIM;
443 free_tx_desc(adapter, tq, avail, unmap);
449 * get_buf_size - return the size of an RX Free List buffer.
450 * @adapter: pointer to the associated adapter
451 * @sdesc: pointer to the software buffer descriptor
453 static inline int get_buf_size(const struct adapter *adapter,
454 const struct rx_sw_desc *sdesc)
456 const struct sge *s = &adapter->sge;
458 return (s->fl_pg_order > 0 && (sdesc->dma_addr & RX_LARGE_BUF)
459 ? (PAGE_SIZE << s->fl_pg_order) : PAGE_SIZE);
463 * free_rx_bufs - free RX buffers on an SGE Free List
464 * @adapter: the adapter
465 * @fl: the SGE Free List to free buffers from
466 * @n: how many buffers to free
468 * Release the next @n buffers on an SGE Free List RX queue. The
469 * buffers must be made inaccessible to hardware before calling this
472 static void free_rx_bufs(struct adapter *adapter, struct sge_fl *fl, int n)
475 struct rx_sw_desc *sdesc = &fl->sdesc[fl->cidx];
477 if (is_buf_mapped(sdesc))
478 dma_unmap_page(adapter->pdev_dev, get_buf_addr(sdesc),
479 get_buf_size(adapter, sdesc),
481 put_page(sdesc->page);
483 if (++fl->cidx == fl->size)
490 * unmap_rx_buf - unmap the current RX buffer on an SGE Free List
491 * @adapter: the adapter
492 * @fl: the SGE Free List
494 * Unmap the current buffer on an SGE Free List RX queue. The
495 * buffer must be made inaccessible to HW before calling this function.
497 * This is similar to @free_rx_bufs above but does not free the buffer.
498 * Do note that the FL still loses any further access to the buffer.
499 * This is used predominantly to "transfer ownership" of an FL buffer
500 * to another entity (typically an skb's fragment list).
502 static void unmap_rx_buf(struct adapter *adapter, struct sge_fl *fl)
504 struct rx_sw_desc *sdesc = &fl->sdesc[fl->cidx];
506 if (is_buf_mapped(sdesc))
507 dma_unmap_page(adapter->pdev_dev, get_buf_addr(sdesc),
508 get_buf_size(adapter, sdesc),
511 if (++fl->cidx == fl->size)
517 * ring_fl_db - righ doorbell on free list
518 * @adapter: the adapter
519 * @fl: the Free List whose doorbell should be rung ...
521 * Tell the Scatter Gather Engine that there are new free list entries
524 static inline void ring_fl_db(struct adapter *adapter, struct sge_fl *fl)
529 * The SGE keeps track of its Producer and Consumer Indices in terms
530 * of Egress Queue Units so we can only tell it about integral numbers
531 * of multiples of Free List Entries per Egress Queue Units ...
533 if (fl->pend_cred >= FL_PER_EQ_UNIT) {
534 val = PIDX(fl->pend_cred / FL_PER_EQ_UNIT);
535 if (!is_t4(adapter->params.chip))
538 t4_write_reg(adapter, T4VF_SGE_BASE_ADDR + SGE_VF_KDOORBELL,
540 QID(fl->cntxt_id) | val);
541 fl->pend_cred %= FL_PER_EQ_UNIT;
546 * set_rx_sw_desc - initialize software RX buffer descriptor
547 * @sdesc: pointer to the softwore RX buffer descriptor
548 * @page: pointer to the page data structure backing the RX buffer
549 * @dma_addr: PCI DMA address (possibly with low-bit flags)
551 static inline void set_rx_sw_desc(struct rx_sw_desc *sdesc, struct page *page,
555 sdesc->dma_addr = dma_addr;
559 * Support for poisoning RX buffers ...
561 #define POISON_BUF_VAL -1
563 static inline void poison_buf(struct page *page, size_t sz)
565 #if POISON_BUF_VAL >= 0
566 memset(page_address(page), POISON_BUF_VAL, sz);
571 * refill_fl - refill an SGE RX buffer ring
572 * @adapter: the adapter
573 * @fl: the Free List ring to refill
574 * @n: the number of new buffers to allocate
575 * @gfp: the gfp flags for the allocations
577 * (Re)populate an SGE free-buffer queue with up to @n new packet buffers,
578 * allocated with the supplied gfp flags. The caller must assure that
579 * @n does not exceed the queue's capacity -- i.e. (cidx == pidx) _IN
580 * EGRESS QUEUE UNITS_ indicates an empty Free List! Returns the number
581 * of buffers allocated. If afterwards the queue is found critically low,
582 * mark it as starving in the bitmap of starving FLs.
584 static unsigned int refill_fl(struct adapter *adapter, struct sge_fl *fl,
587 struct sge *s = &adapter->sge;
590 unsigned int cred = fl->avail;
591 __be64 *d = &fl->desc[fl->pidx];
592 struct rx_sw_desc *sdesc = &fl->sdesc[fl->pidx];
595 * Sanity: ensure that the result of adding n Free List buffers
596 * won't result in wrapping the SGE's Producer Index around to
597 * it's Consumer Index thereby indicating an empty Free List ...
599 BUG_ON(fl->avail + n > fl->size - FL_PER_EQ_UNIT);
602 * If we support large pages, prefer large buffers and fail over to
603 * small pages if we can't allocate large pages to satisfy the refill.
604 * If we don't support large pages, drop directly into the small page
607 if (s->fl_pg_order == 0)
608 goto alloc_small_pages;
611 page = alloc_pages(gfp | __GFP_COMP | __GFP_NOWARN,
613 if (unlikely(!page)) {
615 * We've failed inour attempt to allocate a "large
616 * page". Fail over to the "small page" allocation
619 fl->large_alloc_failed++;
622 poison_buf(page, PAGE_SIZE << s->fl_pg_order);
624 dma_addr = dma_map_page(adapter->pdev_dev, page, 0,
625 PAGE_SIZE << s->fl_pg_order,
627 if (unlikely(dma_mapping_error(adapter->pdev_dev, dma_addr))) {
629 * We've run out of DMA mapping space. Free up the
630 * buffer and return with what we've managed to put
631 * into the free list. We don't want to fail over to
632 * the small page allocation below in this case
633 * because DMA mapping resources are typically
634 * critical resources once they become scarse.
636 __free_pages(page, s->fl_pg_order);
639 dma_addr |= RX_LARGE_BUF;
640 *d++ = cpu_to_be64(dma_addr);
642 set_rx_sw_desc(sdesc, page, dma_addr);
646 if (++fl->pidx == fl->size) {
656 page = __skb_alloc_page(gfp | __GFP_NOWARN, NULL);
657 if (unlikely(!page)) {
661 poison_buf(page, PAGE_SIZE);
663 dma_addr = dma_map_page(adapter->pdev_dev, page, 0, PAGE_SIZE,
665 if (unlikely(dma_mapping_error(adapter->pdev_dev, dma_addr))) {
669 *d++ = cpu_to_be64(dma_addr);
671 set_rx_sw_desc(sdesc, page, dma_addr);
675 if (++fl->pidx == fl->size) {
684 * Update our accounting state to incorporate the new Free List
685 * buffers, tell the hardware about them and return the number of
686 * buffers which we were able to allocate.
688 cred = fl->avail - cred;
689 fl->pend_cred += cred;
690 ring_fl_db(adapter, fl);
692 if (unlikely(fl_starving(adapter, fl))) {
694 set_bit(fl->cntxt_id, adapter->sge.starving_fl);
701 * Refill a Free List to its capacity or the Maximum Refill Increment,
702 * whichever is smaller ...
704 static inline void __refill_fl(struct adapter *adapter, struct sge_fl *fl)
706 refill_fl(adapter, fl,
707 min((unsigned int)MAX_RX_REFILL, fl_cap(fl) - fl->avail),
712 * alloc_ring - allocate resources for an SGE descriptor ring
713 * @dev: the PCI device's core device
714 * @nelem: the number of descriptors
715 * @hwsize: the size of each hardware descriptor
716 * @swsize: the size of each software descriptor
717 * @busaddrp: the physical PCI bus address of the allocated ring
718 * @swringp: return address pointer for software ring
719 * @stat_size: extra space in hardware ring for status information
721 * Allocates resources for an SGE descriptor ring, such as TX queues,
722 * free buffer lists, response queues, etc. Each SGE ring requires
723 * space for its hardware descriptors plus, optionally, space for software
724 * state associated with each hardware entry (the metadata). The function
725 * returns three values: the virtual address for the hardware ring (the
726 * return value of the function), the PCI bus address of the hardware
727 * ring (in *busaddrp), and the address of the software ring (in swringp).
728 * Both the hardware and software rings are returned zeroed out.
730 static void *alloc_ring(struct device *dev, size_t nelem, size_t hwsize,
731 size_t swsize, dma_addr_t *busaddrp, void *swringp,
735 * Allocate the hardware ring and PCI DMA bus address space for said.
737 size_t hwlen = nelem * hwsize + stat_size;
738 void *hwring = dma_alloc_coherent(dev, hwlen, busaddrp, GFP_KERNEL);
744 * If the caller wants a software ring, allocate it and return a
745 * pointer to it in *swringp.
747 BUG_ON((swsize != 0) != (swringp != NULL));
749 void *swring = kcalloc(nelem, swsize, GFP_KERNEL);
752 dma_free_coherent(dev, hwlen, hwring, *busaddrp);
755 *(void **)swringp = swring;
759 * Zero out the hardware ring and return its address as our function
762 memset(hwring, 0, hwlen);
767 * sgl_len - calculates the size of an SGL of the given capacity
768 * @n: the number of SGL entries
770 * Calculates the number of flits (8-byte units) needed for a Direct
771 * Scatter/Gather List that can hold the given number of entries.
773 static inline unsigned int sgl_len(unsigned int n)
776 * A Direct Scatter Gather List uses 32-bit lengths and 64-bit PCI DMA
777 * addresses. The DSGL Work Request starts off with a 32-bit DSGL
778 * ULPTX header, then Length0, then Address0, then, for 1 <= i <= N,
779 * repeated sequences of { Length[i], Length[i+1], Address[i],
780 * Address[i+1] } (this ensures that all addresses are on 64-bit
781 * boundaries). If N is even, then Length[N+1] should be set to 0 and
782 * Address[N+1] is omitted.
784 * The following calculation incorporates all of the above. It's
785 * somewhat hard to follow but, briefly: the "+2" accounts for the
786 * first two flits which include the DSGL header, Length0 and
787 * Address0; the "(3*(n-1))/2" covers the main body of list entries (3
788 * flits for every pair of the remaining N) +1 if (n-1) is odd; and
789 * finally the "+((n-1)&1)" adds the one remaining flit needed if
793 return (3 * n) / 2 + (n & 1) + 2;
797 * flits_to_desc - returns the num of TX descriptors for the given flits
798 * @flits: the number of flits
800 * Returns the number of TX descriptors needed for the supplied number
803 static inline unsigned int flits_to_desc(unsigned int flits)
805 BUG_ON(flits > SGE_MAX_WR_LEN / sizeof(__be64));
806 return DIV_ROUND_UP(flits, TXD_PER_EQ_UNIT);
810 * is_eth_imm - can an Ethernet packet be sent as immediate data?
813 * Returns whether an Ethernet packet is small enough to fit completely as
816 static inline int is_eth_imm(const struct sk_buff *skb)
819 * The VF Driver uses the FW_ETH_TX_PKT_VM_WR firmware Work Request
820 * which does not accommodate immediate data. We could dike out all
821 * of the support code for immediate data but that would tie our hands
822 * too much if we ever want to enhace the firmware. It would also
823 * create more differences between the PF and VF Drivers.
829 * calc_tx_flits - calculate the number of flits for a packet TX WR
832 * Returns the number of flits needed for a TX Work Request for the
833 * given Ethernet packet, including the needed WR and CPL headers.
835 static inline unsigned int calc_tx_flits(const struct sk_buff *skb)
840 * If the skb is small enough, we can pump it out as a work request
841 * with only immediate data. In that case we just have to have the
842 * TX Packet header plus the skb data in the Work Request.
845 return DIV_ROUND_UP(skb->len + sizeof(struct cpl_tx_pkt),
849 * Otherwise, we're going to have to construct a Scatter gather list
850 * of the skb body and fragments. We also include the flits necessary
851 * for the TX Packet Work Request and CPL. We always have a firmware
852 * Write Header (incorporated as part of the cpl_tx_pkt_lso and
853 * cpl_tx_pkt structures), followed by either a TX Packet Write CPL
854 * message or, if we're doing a Large Send Offload, an LSO CPL message
855 * with an embeded TX Packet Write CPL message.
857 flits = sgl_len(skb_shinfo(skb)->nr_frags + 1);
858 if (skb_shinfo(skb)->gso_size)
859 flits += (sizeof(struct fw_eth_tx_pkt_vm_wr) +
860 sizeof(struct cpl_tx_pkt_lso_core) +
861 sizeof(struct cpl_tx_pkt_core)) / sizeof(__be64);
863 flits += (sizeof(struct fw_eth_tx_pkt_vm_wr) +
864 sizeof(struct cpl_tx_pkt_core)) / sizeof(__be64);
869 * write_sgl - populate a Scatter/Gather List for a packet
871 * @tq: the TX queue we are writing into
872 * @sgl: starting location for writing the SGL
873 * @end: points right after the end of the SGL
874 * @start: start offset into skb main-body data to include in the SGL
875 * @addr: the list of DMA bus addresses for the SGL elements
877 * Generates a Scatter/Gather List for the buffers that make up a packet.
878 * The caller must provide adequate space for the SGL that will be written.
879 * The SGL includes all of the packet's page fragments and the data in its
880 * main body except for the first @start bytes. @pos must be 16-byte
881 * aligned and within a TX descriptor with available space. @end points
882 * write after the end of the SGL but does not account for any potential
883 * wrap around, i.e., @end > @tq->stat.
885 static void write_sgl(const struct sk_buff *skb, struct sge_txq *tq,
886 struct ulptx_sgl *sgl, u64 *end, unsigned int start,
887 const dma_addr_t *addr)
890 struct ulptx_sge_pair *to;
891 const struct skb_shared_info *si = skb_shinfo(skb);
892 unsigned int nfrags = si->nr_frags;
893 struct ulptx_sge_pair buf[MAX_SKB_FRAGS / 2 + 1];
895 len = skb_headlen(skb) - start;
897 sgl->len0 = htonl(len);
898 sgl->addr0 = cpu_to_be64(addr[0] + start);
901 sgl->len0 = htonl(skb_frag_size(&si->frags[0]));
902 sgl->addr0 = cpu_to_be64(addr[1]);
905 sgl->cmd_nsge = htonl(ULPTX_CMD(ULP_TX_SC_DSGL) |
907 if (likely(--nfrags == 0))
910 * Most of the complexity below deals with the possibility we hit the
911 * end of the queue in the middle of writing the SGL. For this case
912 * only we create the SGL in a temporary buffer and then copy it.
914 to = (u8 *)end > (u8 *)tq->stat ? buf : sgl->sge;
916 for (i = (nfrags != si->nr_frags); nfrags >= 2; nfrags -= 2, to++) {
917 to->len[0] = cpu_to_be32(skb_frag_size(&si->frags[i]));
918 to->len[1] = cpu_to_be32(skb_frag_size(&si->frags[++i]));
919 to->addr[0] = cpu_to_be64(addr[i]);
920 to->addr[1] = cpu_to_be64(addr[++i]);
923 to->len[0] = cpu_to_be32(skb_frag_size(&si->frags[i]));
924 to->len[1] = cpu_to_be32(0);
925 to->addr[0] = cpu_to_be64(addr[i + 1]);
927 if (unlikely((u8 *)end > (u8 *)tq->stat)) {
928 unsigned int part0 = (u8 *)tq->stat - (u8 *)sgl->sge, part1;
931 memcpy(sgl->sge, buf, part0);
932 part1 = (u8 *)end - (u8 *)tq->stat;
933 memcpy(tq->desc, (u8 *)buf + part0, part1);
934 end = (void *)tq->desc + part1;
936 if ((uintptr_t)end & 8) /* 0-pad to multiple of 16 */
941 * check_ring_tx_db - check and potentially ring a TX queue's doorbell
942 * @adapter: the adapter
944 * @n: number of new descriptors to give to HW
946 * Ring the doorbel for a TX queue.
948 static inline void ring_tx_db(struct adapter *adapter, struct sge_txq *tq,
952 * Warn if we write doorbells with the wrong priority and write
953 * descriptors before telling HW.
955 WARN_ON((QID(tq->cntxt_id) | PIDX(n)) & DBPRIO(1));
957 t4_write_reg(adapter, T4VF_SGE_BASE_ADDR + SGE_VF_KDOORBELL,
958 QID(tq->cntxt_id) | PIDX(n));
962 * inline_tx_skb - inline a packet's data into TX descriptors
964 * @tq: the TX queue where the packet will be inlined
965 * @pos: starting position in the TX queue to inline the packet
967 * Inline a packet's contents directly into TX descriptors, starting at
968 * the given position within the TX DMA ring.
969 * Most of the complexity of this operation is dealing with wrap arounds
970 * in the middle of the packet we want to inline.
972 static void inline_tx_skb(const struct sk_buff *skb, const struct sge_txq *tq,
976 int left = (void *)tq->stat - pos;
978 if (likely(skb->len <= left)) {
979 if (likely(!skb->data_len))
980 skb_copy_from_linear_data(skb, pos, skb->len);
982 skb_copy_bits(skb, 0, pos, skb->len);
985 skb_copy_bits(skb, 0, pos, left);
986 skb_copy_bits(skb, left, tq->desc, skb->len - left);
987 pos = (void *)tq->desc + (skb->len - left);
990 /* 0-pad to multiple of 16 */
991 p = PTR_ALIGN(pos, 8);
992 if ((uintptr_t)p & 8)
997 * Figure out what HW csum a packet wants and return the appropriate control
1000 static u64 hwcsum(const struct sk_buff *skb)
1003 const struct iphdr *iph = ip_hdr(skb);
1005 if (iph->version == 4) {
1006 if (iph->protocol == IPPROTO_TCP)
1007 csum_type = TX_CSUM_TCPIP;
1008 else if (iph->protocol == IPPROTO_UDP)
1009 csum_type = TX_CSUM_UDPIP;
1013 * unknown protocol, disable HW csum
1014 * and hope a bad packet is detected
1016 return TXPKT_L4CSUM_DIS;
1020 * this doesn't work with extension headers
1022 const struct ipv6hdr *ip6h = (const struct ipv6hdr *)iph;
1024 if (ip6h->nexthdr == IPPROTO_TCP)
1025 csum_type = TX_CSUM_TCPIP6;
1026 else if (ip6h->nexthdr == IPPROTO_UDP)
1027 csum_type = TX_CSUM_UDPIP6;
1032 if (likely(csum_type >= TX_CSUM_TCPIP))
1033 return TXPKT_CSUM_TYPE(csum_type) |
1034 TXPKT_IPHDR_LEN(skb_network_header_len(skb)) |
1035 TXPKT_ETHHDR_LEN(skb_network_offset(skb) - ETH_HLEN);
1037 int start = skb_transport_offset(skb);
1039 return TXPKT_CSUM_TYPE(csum_type) |
1040 TXPKT_CSUM_START(start) |
1041 TXPKT_CSUM_LOC(start + skb->csum_offset);
1046 * Stop an Ethernet TX queue and record that state change.
1048 static void txq_stop(struct sge_eth_txq *txq)
1050 netif_tx_stop_queue(txq->txq);
1055 * Advance our software state for a TX queue by adding n in use descriptors.
1057 static inline void txq_advance(struct sge_txq *tq, unsigned int n)
1061 if (tq->pidx >= tq->size)
1062 tq->pidx -= tq->size;
1066 * t4vf_eth_xmit - add a packet to an Ethernet TX queue
1068 * @dev: the egress net device
1070 * Add a packet to an SGE Ethernet TX queue. Runs with softirqs disabled.
1072 int t4vf_eth_xmit(struct sk_buff *skb, struct net_device *dev)
1077 unsigned int flits, ndesc;
1078 struct adapter *adapter;
1079 struct sge_eth_txq *txq;
1080 const struct port_info *pi;
1081 struct fw_eth_tx_pkt_vm_wr *wr;
1082 struct cpl_tx_pkt_core *cpl;
1083 const struct skb_shared_info *ssi;
1084 dma_addr_t addr[MAX_SKB_FRAGS + 1];
1085 const size_t fw_hdr_copy_len = (sizeof(wr->ethmacdst) +
1086 sizeof(wr->ethmacsrc) +
1087 sizeof(wr->ethtype) +
1088 sizeof(wr->vlantci));
1091 * The chip minimum packet length is 10 octets but the firmware
1092 * command that we are using requires that we copy the Ethernet header
1093 * (including the VLAN tag) into the header so we reject anything
1094 * smaller than that ...
1096 if (unlikely(skb->len < fw_hdr_copy_len))
1100 * Figure out which TX Queue we're going to use.
1102 pi = netdev_priv(dev);
1103 adapter = pi->adapter;
1104 qidx = skb_get_queue_mapping(skb);
1105 BUG_ON(qidx >= pi->nqsets);
1106 txq = &adapter->sge.ethtxq[pi->first_qset + qidx];
1109 * Take this opportunity to reclaim any TX Descriptors whose DMA
1110 * transfers have completed.
1112 reclaim_completed_tx(adapter, &txq->q, true);
1115 * Calculate the number of flits and TX Descriptors we're going to
1116 * need along with how many TX Descriptors will be left over after
1117 * we inject our Work Request.
1119 flits = calc_tx_flits(skb);
1120 ndesc = flits_to_desc(flits);
1121 credits = txq_avail(&txq->q) - ndesc;
1123 if (unlikely(credits < 0)) {
1125 * Not enough room for this packet's Work Request. Stop the
1126 * TX Queue and return a "busy" condition. The queue will get
1127 * started later on when the firmware informs us that space
1131 dev_err(adapter->pdev_dev,
1132 "%s: TX ring %u full while queue awake!\n",
1134 return NETDEV_TX_BUSY;
1137 if (!is_eth_imm(skb) &&
1138 unlikely(map_skb(adapter->pdev_dev, skb, addr) < 0)) {
1140 * We need to map the skb into PCI DMA space (because it can't
1141 * be in-lined directly into the Work Request) and the mapping
1142 * operation failed. Record the error and drop the packet.
1148 wr_mid = FW_WR_LEN16(DIV_ROUND_UP(flits, 2));
1149 if (unlikely(credits < ETHTXQ_STOP_THRES)) {
1151 * After we're done injecting the Work Request for this
1152 * packet, we'll be below our "stop threshold" so stop the TX
1153 * Queue now and schedule a request for an SGE Egress Queue
1154 * Update message. The queue will get started later on when
1155 * the firmware processes this Work Request and sends us an
1156 * Egress Queue Status Update message indicating that space
1160 wr_mid |= FW_WR_EQUEQ | FW_WR_EQUIQ;
1164 * Start filling in our Work Request. Note that we do _not_ handle
1165 * the WR Header wrapping around the TX Descriptor Ring. If our
1166 * maximum header size ever exceeds one TX Descriptor, we'll need to
1167 * do something else here.
1169 BUG_ON(DIV_ROUND_UP(ETHTXQ_MAX_HDR, TXD_PER_EQ_UNIT) > 1);
1170 wr = (void *)&txq->q.desc[txq->q.pidx];
1171 wr->equiq_to_len16 = cpu_to_be32(wr_mid);
1172 wr->r3[0] = cpu_to_be64(0);
1173 wr->r3[1] = cpu_to_be64(0);
1174 skb_copy_from_linear_data(skb, (void *)wr->ethmacdst, fw_hdr_copy_len);
1175 end = (u64 *)wr + flits;
1178 * If this is a Large Send Offload packet we'll put in an LSO CPL
1179 * message with an encapsulated TX Packet CPL message. Otherwise we
1180 * just use a TX Packet CPL message.
1182 ssi = skb_shinfo(skb);
1183 if (ssi->gso_size) {
1184 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1);
1185 bool v6 = (ssi->gso_type & SKB_GSO_TCPV6) != 0;
1186 int l3hdr_len = skb_network_header_len(skb);
1187 int eth_xtra_len = skb_network_offset(skb) - ETH_HLEN;
1190 cpu_to_be32(FW_WR_OP(FW_ETH_TX_PKT_VM_WR) |
1191 FW_WR_IMMDLEN(sizeof(*lso) +
1194 * Fill in the LSO CPL message.
1197 cpu_to_be32(LSO_OPCODE(CPL_TX_PKT_LSO) |
1201 LSO_ETHHDR_LEN(eth_xtra_len/4) |
1202 LSO_IPHDR_LEN(l3hdr_len/4) |
1203 LSO_TCPHDR_LEN(tcp_hdr(skb)->doff));
1204 lso->ipid_ofst = cpu_to_be16(0);
1205 lso->mss = cpu_to_be16(ssi->gso_size);
1206 lso->seqno_offset = cpu_to_be32(0);
1207 if (is_t4(adapter->params.chip))
1208 lso->len = cpu_to_be32(skb->len);
1210 lso->len = cpu_to_be32(LSO_T5_XFER_SIZE(skb->len));
1213 * Set up TX Packet CPL pointer, control word and perform
1216 cpl = (void *)(lso + 1);
1217 cntrl = (TXPKT_CSUM_TYPE(v6 ? TX_CSUM_TCPIP6 : TX_CSUM_TCPIP) |
1218 TXPKT_IPHDR_LEN(l3hdr_len) |
1219 TXPKT_ETHHDR_LEN(eth_xtra_len));
1221 txq->tx_cso += ssi->gso_segs;
1225 len = is_eth_imm(skb) ? skb->len + sizeof(*cpl) : sizeof(*cpl);
1227 cpu_to_be32(FW_WR_OP(FW_ETH_TX_PKT_VM_WR) |
1228 FW_WR_IMMDLEN(len));
1231 * Set up TX Packet CPL pointer, control word and perform
1234 cpl = (void *)(wr + 1);
1235 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1236 cntrl = hwcsum(skb) | TXPKT_IPCSUM_DIS;
1239 cntrl = TXPKT_L4CSUM_DIS | TXPKT_IPCSUM_DIS;
1243 * If there's a VLAN tag present, add that to the list of things to
1244 * do in this Work Request.
1246 if (vlan_tx_tag_present(skb)) {
1248 cntrl |= TXPKT_VLAN_VLD | TXPKT_VLAN(vlan_tx_tag_get(skb));
1252 * Fill in the TX Packet CPL message header.
1254 cpl->ctrl0 = cpu_to_be32(TXPKT_OPCODE(CPL_TX_PKT_XT) |
1255 TXPKT_INTF(pi->port_id) |
1257 cpl->pack = cpu_to_be16(0);
1258 cpl->len = cpu_to_be16(skb->len);
1259 cpl->ctrl1 = cpu_to_be64(cntrl);
1262 T4_TRACE5(adapter->tb[txq->q.cntxt_id & 7],
1263 "eth_xmit: ndesc %u, credits %u, pidx %u, len %u, frags %u",
1264 ndesc, credits, txq->q.pidx, skb->len, ssi->nr_frags);
1268 * Fill in the body of the TX Packet CPL message with either in-lined
1269 * data or a Scatter/Gather List.
1271 if (is_eth_imm(skb)) {
1273 * In-line the packet's data and free the skb since we don't
1274 * need it any longer.
1276 inline_tx_skb(skb, &txq->q, cpl + 1);
1277 dev_consume_skb_any(skb);
1280 * Write the skb's Scatter/Gather list into the TX Packet CPL
1281 * message and retain a pointer to the skb so we can free it
1282 * later when its DMA completes. (We store the skb pointer
1283 * in the Software Descriptor corresponding to the last TX
1284 * Descriptor used by the Work Request.)
1286 * The retained skb will be freed when the corresponding TX
1287 * Descriptors are reclaimed after their DMAs complete.
1288 * However, this could take quite a while since, in general,
1289 * the hardware is set up to be lazy about sending DMA
1290 * completion notifications to us and we mostly perform TX
1291 * reclaims in the transmit routine.
1293 * This is good for performamce but means that we rely on new
1294 * TX packets arriving to run the destructors of completed
1295 * packets, which open up space in their sockets' send queues.
1296 * Sometimes we do not get such new packets causing TX to
1297 * stall. A single UDP transmitter is a good example of this
1298 * situation. We have a clean up timer that periodically
1299 * reclaims completed packets but it doesn't run often enough
1300 * (nor do we want it to) to prevent lengthy stalls. A
1301 * solution to this problem is to run the destructor early,
1302 * after the packet is queued but before it's DMAd. A con is
1303 * that we lie to socket memory accounting, but the amount of
1304 * extra memory is reasonable (limited by the number of TX
1305 * descriptors), the packets do actually get freed quickly by
1306 * new packets almost always, and for protocols like TCP that
1307 * wait for acks to really free up the data the extra memory
1308 * is even less. On the positive side we run the destructors
1309 * on the sending CPU rather than on a potentially different
1310 * completing CPU, usually a good thing.
1312 * Run the destructor before telling the DMA engine about the
1313 * packet to make sure it doesn't complete and get freed
1316 struct ulptx_sgl *sgl = (struct ulptx_sgl *)(cpl + 1);
1317 struct sge_txq *tq = &txq->q;
1321 * If the Work Request header was an exact multiple of our TX
1322 * Descriptor length, then it's possible that the starting SGL
1323 * pointer lines up exactly with the end of our TX Descriptor
1324 * ring. If that's the case, wrap around to the beginning
1327 if (unlikely((void *)sgl == (void *)tq->stat)) {
1328 sgl = (void *)tq->desc;
1329 end = ((void *)tq->desc + ((void *)end - (void *)tq->stat));
1332 write_sgl(skb, tq, sgl, end, 0, addr);
1335 last_desc = tq->pidx + ndesc - 1;
1336 if (last_desc >= tq->size)
1337 last_desc -= tq->size;
1338 tq->sdesc[last_desc].skb = skb;
1339 tq->sdesc[last_desc].sgl = sgl;
1343 * Advance our internal TX Queue state, tell the hardware about
1344 * the new TX descriptors and return success.
1346 txq_advance(&txq->q, ndesc);
1347 dev->trans_start = jiffies;
1348 ring_tx_db(adapter, &txq->q, ndesc);
1349 return NETDEV_TX_OK;
1353 * An error of some sort happened. Free the TX skb and tell the
1354 * OS that we've "dealt" with the packet ...
1356 dev_kfree_skb_any(skb);
1357 return NETDEV_TX_OK;
1361 * copy_frags - copy fragments from gather list into skb_shared_info
1362 * @skb: destination skb
1363 * @gl: source internal packet gather list
1364 * @offset: packet start offset in first page
1366 * Copy an internal packet gather list into a Linux skb_shared_info
1369 static inline void copy_frags(struct sk_buff *skb,
1370 const struct pkt_gl *gl,
1371 unsigned int offset)
1375 /* usually there's just one frag */
1376 __skb_fill_page_desc(skb, 0, gl->frags[0].page,
1377 gl->frags[0].offset + offset,
1378 gl->frags[0].size - offset);
1379 skb_shinfo(skb)->nr_frags = gl->nfrags;
1380 for (i = 1; i < gl->nfrags; i++)
1381 __skb_fill_page_desc(skb, i, gl->frags[i].page,
1382 gl->frags[i].offset,
1385 /* get a reference to the last page, we don't own it */
1386 get_page(gl->frags[gl->nfrags - 1].page);
1390 * t4vf_pktgl_to_skb - build an sk_buff from a packet gather list
1391 * @gl: the gather list
1392 * @skb_len: size of sk_buff main body if it carries fragments
1393 * @pull_len: amount of data to move to the sk_buff's main body
1395 * Builds an sk_buff from the given packet gather list. Returns the
1396 * sk_buff or %NULL if sk_buff allocation failed.
1398 static struct sk_buff *t4vf_pktgl_to_skb(const struct pkt_gl *gl,
1399 unsigned int skb_len,
1400 unsigned int pull_len)
1402 struct sk_buff *skb;
1405 * If the ingress packet is small enough, allocate an skb large enough
1406 * for all of the data and copy it inline. Otherwise, allocate an skb
1407 * with enough room to pull in the header and reference the rest of
1408 * the data via the skb fragment list.
1410 * Below we rely on RX_COPY_THRES being less than the smallest Rx
1411 * buff! size, which is expected since buffers are at least
1412 * PAGE_SIZEd. In this case packets up to RX_COPY_THRES have only one
1415 if (gl->tot_len <= RX_COPY_THRES) {
1416 /* small packets have only one fragment */
1417 skb = alloc_skb(gl->tot_len, GFP_ATOMIC);
1420 __skb_put(skb, gl->tot_len);
1421 skb_copy_to_linear_data(skb, gl->va, gl->tot_len);
1423 skb = alloc_skb(skb_len, GFP_ATOMIC);
1426 __skb_put(skb, pull_len);
1427 skb_copy_to_linear_data(skb, gl->va, pull_len);
1429 copy_frags(skb, gl, pull_len);
1430 skb->len = gl->tot_len;
1431 skb->data_len = skb->len - pull_len;
1432 skb->truesize += skb->data_len;
1440 * t4vf_pktgl_free - free a packet gather list
1441 * @gl: the gather list
1443 * Releases the pages of a packet gather list. We do not own the last
1444 * page on the list and do not free it.
1446 static void t4vf_pktgl_free(const struct pkt_gl *gl)
1450 frag = gl->nfrags - 1;
1452 put_page(gl->frags[frag].page);
1456 * do_gro - perform Generic Receive Offload ingress packet processing
1457 * @rxq: ingress RX Ethernet Queue
1458 * @gl: gather list for ingress packet
1459 * @pkt: CPL header for last packet fragment
1461 * Perform Generic Receive Offload (GRO) ingress packet processing.
1462 * We use the standard Linux GRO interfaces for this.
1464 static void do_gro(struct sge_eth_rxq *rxq, const struct pkt_gl *gl,
1465 const struct cpl_rx_pkt *pkt)
1467 struct adapter *adapter = rxq->rspq.adapter;
1468 struct sge *s = &adapter->sge;
1470 struct sk_buff *skb;
1472 skb = napi_get_frags(&rxq->rspq.napi);
1473 if (unlikely(!skb)) {
1474 t4vf_pktgl_free(gl);
1475 rxq->stats.rx_drops++;
1479 copy_frags(skb, gl, s->pktshift);
1480 skb->len = gl->tot_len - s->pktshift;
1481 skb->data_len = skb->len;
1482 skb->truesize += skb->data_len;
1483 skb->ip_summed = CHECKSUM_UNNECESSARY;
1484 skb_record_rx_queue(skb, rxq->rspq.idx);
1487 __vlan_hwaccel_put_tag(skb, cpu_to_be16(ETH_P_8021Q),
1488 be16_to_cpu(pkt->vlan));
1489 rxq->stats.vlan_ex++;
1491 ret = napi_gro_frags(&rxq->rspq.napi);
1493 if (ret == GRO_HELD)
1494 rxq->stats.lro_pkts++;
1495 else if (ret == GRO_MERGED || ret == GRO_MERGED_FREE)
1496 rxq->stats.lro_merged++;
1498 rxq->stats.rx_cso++;
1502 * t4vf_ethrx_handler - process an ingress ethernet packet
1503 * @rspq: the response queue that received the packet
1504 * @rsp: the response queue descriptor holding the RX_PKT message
1505 * @gl: the gather list of packet fragments
1507 * Process an ingress ethernet packet and deliver it to the stack.
1509 int t4vf_ethrx_handler(struct sge_rspq *rspq, const __be64 *rsp,
1510 const struct pkt_gl *gl)
1512 struct sk_buff *skb;
1513 const struct cpl_rx_pkt *pkt = (void *)rsp;
1514 bool csum_ok = pkt->csum_calc && !pkt->err_vec &&
1515 (rspq->netdev->features & NETIF_F_RXCSUM);
1516 struct sge_eth_rxq *rxq = container_of(rspq, struct sge_eth_rxq, rspq);
1517 struct adapter *adapter = rspq->adapter;
1518 struct sge *s = &adapter->sge;
1521 * If this is a good TCP packet and we have Generic Receive Offload
1522 * enabled, handle the packet in the GRO path.
1524 if ((pkt->l2info & cpu_to_be32(RXF_TCP)) &&
1525 (rspq->netdev->features & NETIF_F_GRO) && csum_ok &&
1527 do_gro(rxq, gl, pkt);
1532 * Convert the Packet Gather List into an skb.
1534 skb = t4vf_pktgl_to_skb(gl, RX_SKB_LEN, RX_PULL_LEN);
1535 if (unlikely(!skb)) {
1536 t4vf_pktgl_free(gl);
1537 rxq->stats.rx_drops++;
1540 __skb_pull(skb, s->pktshift);
1541 skb->protocol = eth_type_trans(skb, rspq->netdev);
1542 skb_record_rx_queue(skb, rspq->idx);
1545 if (csum_ok && !pkt->err_vec &&
1546 (be32_to_cpu(pkt->l2info) & (RXF_UDP|RXF_TCP))) {
1548 skb->ip_summed = CHECKSUM_UNNECESSARY;
1550 __sum16 c = (__force __sum16)pkt->csum;
1551 skb->csum = csum_unfold(c);
1552 skb->ip_summed = CHECKSUM_COMPLETE;
1554 rxq->stats.rx_cso++;
1556 skb_checksum_none_assert(skb);
1559 rxq->stats.vlan_ex++;
1560 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), be16_to_cpu(pkt->vlan));
1563 netif_receive_skb(skb);
1569 * is_new_response - check if a response is newly written
1570 * @rc: the response control descriptor
1571 * @rspq: the response queue
1573 * Returns true if a response descriptor contains a yet unprocessed
1576 static inline bool is_new_response(const struct rsp_ctrl *rc,
1577 const struct sge_rspq *rspq)
1579 return RSPD_GEN(rc->type_gen) == rspq->gen;
1583 * restore_rx_bufs - put back a packet's RX buffers
1584 * @gl: the packet gather list
1585 * @fl: the SGE Free List
1586 * @nfrags: how many fragments in @si
1588 * Called when we find out that the current packet, @si, can't be
1589 * processed right away for some reason. This is a very rare event and
1590 * there's no effort to make this suspension/resumption process
1591 * particularly efficient.
1593 * We implement the suspension by putting all of the RX buffers associated
1594 * with the current packet back on the original Free List. The buffers
1595 * have already been unmapped and are left unmapped, we mark them as
1596 * unmapped in order to prevent further unmapping attempts. (Effectively
1597 * this function undoes the series of @unmap_rx_buf calls which were done
1598 * to create the current packet's gather list.) This leaves us ready to
1599 * restart processing of the packet the next time we start processing the
1602 static void restore_rx_bufs(const struct pkt_gl *gl, struct sge_fl *fl,
1605 struct rx_sw_desc *sdesc;
1609 fl->cidx = fl->size - 1;
1612 sdesc = &fl->sdesc[fl->cidx];
1613 sdesc->page = gl->frags[frags].page;
1614 sdesc->dma_addr |= RX_UNMAPPED_BUF;
1620 * rspq_next - advance to the next entry in a response queue
1623 * Updates the state of a response queue to advance it to the next entry.
1625 static inline void rspq_next(struct sge_rspq *rspq)
1627 rspq->cur_desc = (void *)rspq->cur_desc + rspq->iqe_len;
1628 if (unlikely(++rspq->cidx == rspq->size)) {
1631 rspq->cur_desc = rspq->desc;
1636 * process_responses - process responses from an SGE response queue
1637 * @rspq: the ingress response queue to process
1638 * @budget: how many responses can be processed in this round
1640 * Process responses from a Scatter Gather Engine response queue up to
1641 * the supplied budget. Responses include received packets as well as
1642 * control messages from firmware or hardware.
1644 * Additionally choose the interrupt holdoff time for the next interrupt
1645 * on this queue. If the system is under memory shortage use a fairly
1646 * long delay to help recovery.
1648 static int process_responses(struct sge_rspq *rspq, int budget)
1650 struct sge_eth_rxq *rxq = container_of(rspq, struct sge_eth_rxq, rspq);
1651 struct adapter *adapter = rspq->adapter;
1652 struct sge *s = &adapter->sge;
1653 int budget_left = budget;
1655 while (likely(budget_left)) {
1657 const struct rsp_ctrl *rc;
1659 rc = (void *)rspq->cur_desc + (rspq->iqe_len - sizeof(*rc));
1660 if (!is_new_response(rc, rspq))
1664 * Figure out what kind of response we've received from the
1668 rsp_type = RSPD_TYPE(rc->type_gen);
1669 if (likely(rsp_type == RSP_TYPE_FLBUF)) {
1670 struct page_frag *fp;
1672 const struct rx_sw_desc *sdesc;
1674 u32 len = be32_to_cpu(rc->pldbuflen_qid);
1677 * If we get a "new buffer" message from the SGE we
1678 * need to move on to the next Free List buffer.
1680 if (len & RSPD_NEWBUF) {
1682 * We get one "new buffer" message when we
1683 * first start up a queue so we need to ignore
1684 * it when our offset into the buffer is 0.
1686 if (likely(rspq->offset > 0)) {
1687 free_rx_bufs(rspq->adapter, &rxq->fl,
1691 len = RSPD_LEN(len);
1696 * Gather packet fragments.
1698 for (frag = 0, fp = gl.frags; /**/; frag++, fp++) {
1699 BUG_ON(frag >= MAX_SKB_FRAGS);
1700 BUG_ON(rxq->fl.avail == 0);
1701 sdesc = &rxq->fl.sdesc[rxq->fl.cidx];
1702 bufsz = get_buf_size(adapter, sdesc);
1703 fp->page = sdesc->page;
1704 fp->offset = rspq->offset;
1705 fp->size = min(bufsz, len);
1709 unmap_rx_buf(rspq->adapter, &rxq->fl);
1714 * Last buffer remains mapped so explicitly make it
1715 * coherent for CPU access and start preloading first
1718 dma_sync_single_for_cpu(rspq->adapter->pdev_dev,
1719 get_buf_addr(sdesc),
1720 fp->size, DMA_FROM_DEVICE);
1721 gl.va = (page_address(gl.frags[0].page) +
1722 gl.frags[0].offset);
1726 * Hand the new ingress packet to the handler for
1727 * this Response Queue.
1729 ret = rspq->handler(rspq, rspq->cur_desc, &gl);
1730 if (likely(ret == 0))
1731 rspq->offset += ALIGN(fp->size, s->fl_align);
1733 restore_rx_bufs(&gl, &rxq->fl, frag);
1734 } else if (likely(rsp_type == RSP_TYPE_CPL)) {
1735 ret = rspq->handler(rspq, rspq->cur_desc, NULL);
1737 WARN_ON(rsp_type > RSP_TYPE_CPL);
1741 if (unlikely(ret)) {
1743 * Couldn't process descriptor, back off for recovery.
1744 * We use the SGE's last timer which has the longest
1745 * interrupt coalescing value ...
1747 const int NOMEM_TIMER_IDX = SGE_NTIMERS-1;
1748 rspq->next_intr_params =
1749 QINTR_TIMER_IDX(NOMEM_TIMER_IDX);
1758 * If this is a Response Queue with an associated Free List and
1759 * at least two Egress Queue units available in the Free List
1760 * for new buffer pointers, refill the Free List.
1762 if (rspq->offset >= 0 &&
1763 rxq->fl.size - rxq->fl.avail >= 2*FL_PER_EQ_UNIT)
1764 __refill_fl(rspq->adapter, &rxq->fl);
1765 return budget - budget_left;
1769 * napi_rx_handler - the NAPI handler for RX processing
1770 * @napi: the napi instance
1771 * @budget: how many packets we can process in this round
1773 * Handler for new data events when using NAPI. This does not need any
1774 * locking or protection from interrupts as data interrupts are off at
1775 * this point and other adapter interrupts do not interfere (the latter
1776 * in not a concern at all with MSI-X as non-data interrupts then have
1777 * a separate handler).
1779 static int napi_rx_handler(struct napi_struct *napi, int budget)
1781 unsigned int intr_params;
1782 struct sge_rspq *rspq = container_of(napi, struct sge_rspq, napi);
1783 int work_done = process_responses(rspq, budget);
1785 if (likely(work_done < budget)) {
1786 napi_complete(napi);
1787 intr_params = rspq->next_intr_params;
1788 rspq->next_intr_params = rspq->intr_params;
1790 intr_params = QINTR_TIMER_IDX(SGE_TIMER_UPD_CIDX);
1792 if (unlikely(work_done == 0))
1793 rspq->unhandled_irqs++;
1795 t4_write_reg(rspq->adapter,
1796 T4VF_SGE_BASE_ADDR + SGE_VF_GTS,
1797 CIDXINC(work_done) |
1798 INGRESSQID((u32)rspq->cntxt_id) |
1799 SEINTARM(intr_params));
1804 * The MSI-X interrupt handler for an SGE response queue for the NAPI case
1805 * (i.e., response queue serviced by NAPI polling).
1807 irqreturn_t t4vf_sge_intr_msix(int irq, void *cookie)
1809 struct sge_rspq *rspq = cookie;
1811 napi_schedule(&rspq->napi);
1816 * Process the indirect interrupt entries in the interrupt queue and kick off
1817 * NAPI for each queue that has generated an entry.
1819 static unsigned int process_intrq(struct adapter *adapter)
1821 struct sge *s = &adapter->sge;
1822 struct sge_rspq *intrq = &s->intrq;
1823 unsigned int work_done;
1825 spin_lock(&adapter->sge.intrq_lock);
1826 for (work_done = 0; ; work_done++) {
1827 const struct rsp_ctrl *rc;
1828 unsigned int qid, iq_idx;
1829 struct sge_rspq *rspq;
1832 * Grab the next response from the interrupt queue and bail
1833 * out if it's not a new response.
1835 rc = (void *)intrq->cur_desc + (intrq->iqe_len - sizeof(*rc));
1836 if (!is_new_response(rc, intrq))
1840 * If the response isn't a forwarded interrupt message issue a
1841 * error and go on to the next response message. This should
1845 if (unlikely(RSPD_TYPE(rc->type_gen) != RSP_TYPE_INTR)) {
1846 dev_err(adapter->pdev_dev,
1847 "Unexpected INTRQ response type %d\n",
1848 RSPD_TYPE(rc->type_gen));
1853 * Extract the Queue ID from the interrupt message and perform
1854 * sanity checking to make sure it really refers to one of our
1855 * Ingress Queues which is active and matches the queue's ID.
1856 * None of these error conditions should ever happen so we may
1857 * want to either make them fatal and/or conditionalized under
1860 qid = RSPD_QID(be32_to_cpu(rc->pldbuflen_qid));
1861 iq_idx = IQ_IDX(s, qid);
1862 if (unlikely(iq_idx >= MAX_INGQ)) {
1863 dev_err(adapter->pdev_dev,
1864 "Ingress QID %d out of range\n", qid);
1867 rspq = s->ingr_map[iq_idx];
1868 if (unlikely(rspq == NULL)) {
1869 dev_err(adapter->pdev_dev,
1870 "Ingress QID %d RSPQ=NULL\n", qid);
1873 if (unlikely(rspq->abs_id != qid)) {
1874 dev_err(adapter->pdev_dev,
1875 "Ingress QID %d refers to RSPQ %d\n",
1881 * Schedule NAPI processing on the indicated Response Queue
1882 * and move on to the next entry in the Forwarded Interrupt
1885 napi_schedule(&rspq->napi);
1889 t4_write_reg(adapter, T4VF_SGE_BASE_ADDR + SGE_VF_GTS,
1890 CIDXINC(work_done) |
1891 INGRESSQID(intrq->cntxt_id) |
1892 SEINTARM(intrq->intr_params));
1894 spin_unlock(&adapter->sge.intrq_lock);
1900 * The MSI interrupt handler handles data events from SGE response queues as
1901 * well as error and other async events as they all use the same MSI vector.
1903 static irqreturn_t t4vf_intr_msi(int irq, void *cookie)
1905 struct adapter *adapter = cookie;
1907 process_intrq(adapter);
1912 * t4vf_intr_handler - select the top-level interrupt handler
1913 * @adapter: the adapter
1915 * Selects the top-level interrupt handler based on the type of interrupts
1918 irq_handler_t t4vf_intr_handler(struct adapter *adapter)
1920 BUG_ON((adapter->flags & (USING_MSIX|USING_MSI)) == 0);
1921 if (adapter->flags & USING_MSIX)
1922 return t4vf_sge_intr_msix;
1924 return t4vf_intr_msi;
1928 * sge_rx_timer_cb - perform periodic maintenance of SGE RX queues
1929 * @data: the adapter
1931 * Runs periodically from a timer to perform maintenance of SGE RX queues.
1933 * a) Replenishes RX queues that have run out due to memory shortage.
1934 * Normally new RX buffers are added when existing ones are consumed but
1935 * when out of memory a queue can become empty. We schedule NAPI to do
1936 * the actual refill.
1938 static void sge_rx_timer_cb(unsigned long data)
1940 struct adapter *adapter = (struct adapter *)data;
1941 struct sge *s = &adapter->sge;
1945 * Scan the "Starving Free Lists" flag array looking for any Free
1946 * Lists in need of more free buffers. If we find one and it's not
1947 * being actively polled, then bump its "starving" counter and attempt
1948 * to refill it. If we're successful in adding enough buffers to push
1949 * the Free List over the starving threshold, then we can clear its
1950 * "starving" status.
1952 for (i = 0; i < ARRAY_SIZE(s->starving_fl); i++) {
1955 for (m = s->starving_fl[i]; m; m &= m - 1) {
1956 unsigned int id = __ffs(m) + i * BITS_PER_LONG;
1957 struct sge_fl *fl = s->egr_map[id];
1959 clear_bit(id, s->starving_fl);
1960 smp_mb__after_atomic();
1963 * Since we are accessing fl without a lock there's a
1964 * small probability of a false positive where we
1965 * schedule napi but the FL is no longer starving.
1968 if (fl_starving(adapter, fl)) {
1969 struct sge_eth_rxq *rxq;
1971 rxq = container_of(fl, struct sge_eth_rxq, fl);
1972 if (napi_reschedule(&rxq->rspq.napi))
1975 set_bit(id, s->starving_fl);
1981 * Reschedule the next scan for starving Free Lists ...
1983 mod_timer(&s->rx_timer, jiffies + RX_QCHECK_PERIOD);
1987 * sge_tx_timer_cb - perform periodic maintenance of SGE Tx queues
1988 * @data: the adapter
1990 * Runs periodically from a timer to perform maintenance of SGE TX queues.
1992 * b) Reclaims completed Tx packets for the Ethernet queues. Normally
1993 * packets are cleaned up by new Tx packets, this timer cleans up packets
1994 * when no new packets are being submitted. This is essential for pktgen,
1997 static void sge_tx_timer_cb(unsigned long data)
1999 struct adapter *adapter = (struct adapter *)data;
2000 struct sge *s = &adapter->sge;
2001 unsigned int i, budget;
2003 budget = MAX_TIMER_TX_RECLAIM;
2004 i = s->ethtxq_rover;
2006 struct sge_eth_txq *txq = &s->ethtxq[i];
2008 if (reclaimable(&txq->q) && __netif_tx_trylock(txq->txq)) {
2009 int avail = reclaimable(&txq->q);
2014 free_tx_desc(adapter, &txq->q, avail, true);
2015 txq->q.in_use -= avail;
2016 __netif_tx_unlock(txq->txq);
2024 if (i >= s->ethqsets)
2026 } while (i != s->ethtxq_rover);
2027 s->ethtxq_rover = i;
2030 * If we found too many reclaimable packets schedule a timer in the
2031 * near future to continue where we left off. Otherwise the next timer
2032 * will be at its normal interval.
2034 mod_timer(&s->tx_timer, jiffies + (budget ? TX_QCHECK_PERIOD : 2));
2038 * t4vf_sge_alloc_rxq - allocate an SGE RX Queue
2039 * @adapter: the adapter
2040 * @rspq: pointer to to the new rxq's Response Queue to be filled in
2041 * @iqasynch: if 0, a normal rspq; if 1, an asynchronous event queue
2042 * @dev: the network device associated with the new rspq
2043 * @intr_dest: MSI-X vector index (overriden in MSI mode)
2044 * @fl: pointer to the new rxq's Free List to be filled in
2045 * @hnd: the interrupt handler to invoke for the rspq
2047 int t4vf_sge_alloc_rxq(struct adapter *adapter, struct sge_rspq *rspq,
2048 bool iqasynch, struct net_device *dev,
2050 struct sge_fl *fl, rspq_handler_t hnd)
2052 struct sge *s = &adapter->sge;
2053 struct port_info *pi = netdev_priv(dev);
2054 struct fw_iq_cmd cmd, rpl;
2055 int ret, iqandst, flsz = 0;
2058 * If we're using MSI interrupts and we're not initializing the
2059 * Forwarded Interrupt Queue itself, then set up this queue for
2060 * indirect interrupts to the Forwarded Interrupt Queue. Obviously
2061 * the Forwarded Interrupt Queue must be set up before any other
2064 if ((adapter->flags & USING_MSI) && rspq != &adapter->sge.intrq) {
2065 iqandst = SGE_INTRDST_IQ;
2066 intr_dest = adapter->sge.intrq.abs_id;
2068 iqandst = SGE_INTRDST_PCI;
2071 * Allocate the hardware ring for the Response Queue. The size needs
2072 * to be a multiple of 16 which includes the mandatory status entry
2073 * (regardless of whether the Status Page capabilities are enabled or
2076 rspq->size = roundup(rspq->size, 16);
2077 rspq->desc = alloc_ring(adapter->pdev_dev, rspq->size, rspq->iqe_len,
2078 0, &rspq->phys_addr, NULL, 0);
2083 * Fill in the Ingress Queue Command. Note: Ideally this code would
2084 * be in t4vf_hw.c but there are so many parameters and dependencies
2085 * on our Linux SGE state that we would end up having to pass tons of
2086 * parameters. We'll have to think about how this might be migrated
2087 * into OS-independent common code ...
2089 memset(&cmd, 0, sizeof(cmd));
2090 cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP(FW_IQ_CMD) |
2094 cmd.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_ALLOC |
2095 FW_IQ_CMD_IQSTART(1) |
2097 cmd.type_to_iqandstindex =
2098 cpu_to_be32(FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) |
2099 FW_IQ_CMD_IQASYNCH(iqasynch) |
2100 FW_IQ_CMD_VIID(pi->viid) |
2101 FW_IQ_CMD_IQANDST(iqandst) |
2102 FW_IQ_CMD_IQANUS(1) |
2103 FW_IQ_CMD_IQANUD(SGE_UPDATEDEL_INTR) |
2104 FW_IQ_CMD_IQANDSTINDEX(intr_dest));
2105 cmd.iqdroprss_to_iqesize =
2106 cpu_to_be16(FW_IQ_CMD_IQPCIECH(pi->port_id) |
2107 FW_IQ_CMD_IQGTSMODE |
2108 FW_IQ_CMD_IQINTCNTTHRESH(rspq->pktcnt_idx) |
2109 FW_IQ_CMD_IQESIZE(ilog2(rspq->iqe_len) - 4));
2110 cmd.iqsize = cpu_to_be16(rspq->size);
2111 cmd.iqaddr = cpu_to_be64(rspq->phys_addr);
2115 * Allocate the ring for the hardware free list (with space
2116 * for its status page) along with the associated software
2117 * descriptor ring. The free list size needs to be a multiple
2118 * of the Egress Queue Unit.
2120 fl->size = roundup(fl->size, FL_PER_EQ_UNIT);
2121 fl->desc = alloc_ring(adapter->pdev_dev, fl->size,
2122 sizeof(__be64), sizeof(struct rx_sw_desc),
2123 &fl->addr, &fl->sdesc, s->stat_len);
2130 * Calculate the size of the hardware free list ring plus
2131 * Status Page (which the SGE will place after the end of the
2132 * free list ring) in Egress Queue Units.
2134 flsz = (fl->size / FL_PER_EQ_UNIT +
2135 s->stat_len / EQ_UNIT);
2138 * Fill in all the relevant firmware Ingress Queue Command
2139 * fields for the free list.
2141 cmd.iqns_to_fl0congen =
2143 FW_IQ_CMD_FL0HOSTFCMODE(SGE_HOSTFCMODE_NONE) |
2144 FW_IQ_CMD_FL0PACKEN(1) |
2145 FW_IQ_CMD_FL0PADEN(1));
2146 cmd.fl0dcaen_to_fl0cidxfthresh =
2148 FW_IQ_CMD_FL0FBMIN(SGE_FETCHBURSTMIN_64B) |
2149 FW_IQ_CMD_FL0FBMAX(SGE_FETCHBURSTMAX_512B));
2150 cmd.fl0size = cpu_to_be16(flsz);
2151 cmd.fl0addr = cpu_to_be64(fl->addr);
2155 * Issue the firmware Ingress Queue Command and extract the results if
2156 * it completes successfully.
2158 ret = t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), &rpl);
2162 netif_napi_add(dev, &rspq->napi, napi_rx_handler, 64);
2163 rspq->cur_desc = rspq->desc;
2166 rspq->next_intr_params = rspq->intr_params;
2167 rspq->cntxt_id = be16_to_cpu(rpl.iqid);
2168 rspq->abs_id = be16_to_cpu(rpl.physiqid);
2169 rspq->size--; /* subtract status entry */
2170 rspq->adapter = adapter;
2172 rspq->handler = hnd;
2174 /* set offset to -1 to distinguish ingress queues without FL */
2175 rspq->offset = fl ? 0 : -1;
2178 fl->cntxt_id = be16_to_cpu(rpl.fl0id);
2183 fl->alloc_failed = 0;
2184 fl->large_alloc_failed = 0;
2186 refill_fl(adapter, fl, fl_cap(fl), GFP_KERNEL);
2193 * An error occurred. Clean up our partial allocation state and
2197 dma_free_coherent(adapter->pdev_dev, rspq->size * rspq->iqe_len,
2198 rspq->desc, rspq->phys_addr);
2201 if (fl && fl->desc) {
2204 dma_free_coherent(adapter->pdev_dev, flsz * EQ_UNIT,
2205 fl->desc, fl->addr);
2212 * t4vf_sge_alloc_eth_txq - allocate an SGE Ethernet TX Queue
2213 * @adapter: the adapter
2214 * @txq: pointer to the new txq to be filled in
2215 * @devq: the network TX queue associated with the new txq
2216 * @iqid: the relative ingress queue ID to which events relating to
2217 * the new txq should be directed
2219 int t4vf_sge_alloc_eth_txq(struct adapter *adapter, struct sge_eth_txq *txq,
2220 struct net_device *dev, struct netdev_queue *devq,
2223 struct sge *s = &adapter->sge;
2225 struct fw_eq_eth_cmd cmd, rpl;
2226 struct port_info *pi = netdev_priv(dev);
2229 * Calculate the size of the hardware TX Queue (including the Status
2230 * Page on the end of the TX Queue) in units of TX Descriptors.
2232 nentries = txq->q.size + s->stat_len / sizeof(struct tx_desc);
2235 * Allocate the hardware ring for the TX ring (with space for its
2236 * status page) along with the associated software descriptor ring.
2238 txq->q.desc = alloc_ring(adapter->pdev_dev, txq->q.size,
2239 sizeof(struct tx_desc),
2240 sizeof(struct tx_sw_desc),
2241 &txq->q.phys_addr, &txq->q.sdesc, s->stat_len);
2246 * Fill in the Egress Queue Command. Note: As with the direct use of
2247 * the firmware Ingress Queue COmmand above in our RXQ allocation
2248 * routine, ideally, this code would be in t4vf_hw.c. Again, we'll
2249 * have to see if there's some reasonable way to parameterize it
2250 * into the common code ...
2252 memset(&cmd, 0, sizeof(cmd));
2253 cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP(FW_EQ_ETH_CMD) |
2257 cmd.alloc_to_len16 = cpu_to_be32(FW_EQ_ETH_CMD_ALLOC |
2258 FW_EQ_ETH_CMD_EQSTART |
2260 cmd.viid_pkd = cpu_to_be32(FW_EQ_ETH_CMD_AUTOEQUEQE |
2261 FW_EQ_ETH_CMD_VIID(pi->viid));
2262 cmd.fetchszm_to_iqid =
2263 cpu_to_be32(FW_EQ_ETH_CMD_HOSTFCMODE(SGE_HOSTFCMODE_STPG) |
2264 FW_EQ_ETH_CMD_PCIECHN(pi->port_id) |
2265 FW_EQ_ETH_CMD_IQID(iqid));
2266 cmd.dcaen_to_eqsize =
2267 cpu_to_be32(FW_EQ_ETH_CMD_FBMIN(SGE_FETCHBURSTMIN_64B) |
2268 FW_EQ_ETH_CMD_FBMAX(SGE_FETCHBURSTMAX_512B) |
2269 FW_EQ_ETH_CMD_CIDXFTHRESH(SGE_CIDXFLUSHTHRESH_32) |
2270 FW_EQ_ETH_CMD_EQSIZE(nentries));
2271 cmd.eqaddr = cpu_to_be64(txq->q.phys_addr);
2274 * Issue the firmware Egress Queue Command and extract the results if
2275 * it completes successfully.
2277 ret = t4vf_wr_mbox(adapter, &cmd, sizeof(cmd), &rpl);
2280 * The girmware Ingress Queue Command failed for some reason.
2281 * Free up our partial allocation state and return the error.
2283 kfree(txq->q.sdesc);
2284 txq->q.sdesc = NULL;
2285 dma_free_coherent(adapter->pdev_dev,
2286 nentries * sizeof(struct tx_desc),
2287 txq->q.desc, txq->q.phys_addr);
2295 txq->q.stat = (void *)&txq->q.desc[txq->q.size];
2296 txq->q.cntxt_id = FW_EQ_ETH_CMD_EQID_GET(be32_to_cpu(rpl.eqid_pkd));
2298 FW_EQ_ETH_CMD_PHYSEQID_GET(be32_to_cpu(rpl.physeqid_pkd));
2304 txq->q.restarts = 0;
2305 txq->mapping_err = 0;
2310 * Free the DMA map resources associated with a TX queue.
2312 static void free_txq(struct adapter *adapter, struct sge_txq *tq)
2314 struct sge *s = &adapter->sge;
2316 dma_free_coherent(adapter->pdev_dev,
2317 tq->size * sizeof(*tq->desc) + s->stat_len,
2318 tq->desc, tq->phys_addr);
2325 * Free the resources associated with a response queue (possibly including a
2328 static void free_rspq_fl(struct adapter *adapter, struct sge_rspq *rspq,
2331 struct sge *s = &adapter->sge;
2332 unsigned int flid = fl ? fl->cntxt_id : 0xffff;
2334 t4vf_iq_free(adapter, FW_IQ_TYPE_FL_INT_CAP,
2335 rspq->cntxt_id, flid, 0xffff);
2336 dma_free_coherent(adapter->pdev_dev, (rspq->size + 1) * rspq->iqe_len,
2337 rspq->desc, rspq->phys_addr);
2338 netif_napi_del(&rspq->napi);
2339 rspq->netdev = NULL;
2345 free_rx_bufs(adapter, fl, fl->avail);
2346 dma_free_coherent(adapter->pdev_dev,
2347 fl->size * sizeof(*fl->desc) + s->stat_len,
2348 fl->desc, fl->addr);
2357 * t4vf_free_sge_resources - free SGE resources
2358 * @adapter: the adapter
2360 * Frees resources used by the SGE queue sets.
2362 void t4vf_free_sge_resources(struct adapter *adapter)
2364 struct sge *s = &adapter->sge;
2365 struct sge_eth_rxq *rxq = s->ethrxq;
2366 struct sge_eth_txq *txq = s->ethtxq;
2367 struct sge_rspq *evtq = &s->fw_evtq;
2368 struct sge_rspq *intrq = &s->intrq;
2371 for (qs = 0; qs < adapter->sge.ethqsets; qs++, rxq++, txq++) {
2373 free_rspq_fl(adapter, &rxq->rspq, &rxq->fl);
2375 t4vf_eth_eq_free(adapter, txq->q.cntxt_id);
2376 free_tx_desc(adapter, &txq->q, txq->q.in_use, true);
2377 kfree(txq->q.sdesc);
2378 free_txq(adapter, &txq->q);
2382 free_rspq_fl(adapter, evtq, NULL);
2384 free_rspq_fl(adapter, intrq, NULL);
2388 * t4vf_sge_start - enable SGE operation
2389 * @adapter: the adapter
2391 * Start tasklets and timers associated with the DMA engine.
2393 void t4vf_sge_start(struct adapter *adapter)
2395 adapter->sge.ethtxq_rover = 0;
2396 mod_timer(&adapter->sge.rx_timer, jiffies + RX_QCHECK_PERIOD);
2397 mod_timer(&adapter->sge.tx_timer, jiffies + TX_QCHECK_PERIOD);
2401 * t4vf_sge_stop - disable SGE operation
2402 * @adapter: the adapter
2404 * Stop tasklets and timers associated with the DMA engine. Note that
2405 * this is effective only if measures have been taken to disable any HW
2406 * events that may restart them.
2408 void t4vf_sge_stop(struct adapter *adapter)
2410 struct sge *s = &adapter->sge;
2412 if (s->rx_timer.function)
2413 del_timer_sync(&s->rx_timer);
2414 if (s->tx_timer.function)
2415 del_timer_sync(&s->tx_timer);
2419 * t4vf_sge_init - initialize SGE
2420 * @adapter: the adapter
2422 * Performs SGE initialization needed every time after a chip reset.
2423 * We do not initialize any of the queue sets here, instead the driver
2424 * top-level must request those individually. We also do not enable DMA
2425 * here, that should be done after the queues have been set up.
2427 int t4vf_sge_init(struct adapter *adapter)
2429 struct sge_params *sge_params = &adapter->params.sge;
2430 u32 fl0 = sge_params->sge_fl_buffer_size[0];
2431 u32 fl1 = sge_params->sge_fl_buffer_size[1];
2432 struct sge *s = &adapter->sge;
2433 unsigned int ingpadboundary, ingpackboundary;
2436 * Start by vetting the basic SGE parameters which have been set up by
2437 * the Physical Function Driver. Ideally we should be able to deal
2438 * with _any_ configuration. Practice is different ...
2440 if (fl0 != PAGE_SIZE || (fl1 != 0 && fl1 <= fl0)) {
2441 dev_err(adapter->pdev_dev, "bad SGE FL buffer sizes [%d, %d]\n",
2445 if ((sge_params->sge_control & RXPKTCPLMODE_MASK) == 0) {
2446 dev_err(adapter->pdev_dev, "bad SGE CPL MODE\n");
2451 * Now translate the adapter parameters into our internal forms.
2454 s->fl_pg_order = ilog2(fl1) - PAGE_SHIFT;
2455 s->stat_len = ((sge_params->sge_control & EGRSTATUSPAGESIZE_MASK)
2457 s->pktshift = PKTSHIFT_GET(sge_params->sge_control);
2459 /* T4 uses a single control field to specify both the PCIe Padding and
2460 * Packing Boundary. T5 introduced the ability to specify these
2461 * separately. The actual Ingress Packet Data alignment boundary
2462 * within Packed Buffer Mode is the maximum of these two
2463 * specifications. (Note that it makes no real practical sense to
2464 * have the Pading Boudary be larger than the Packing Boundary but you
2465 * could set the chip up that way and, in fact, legacy T4 code would
2466 * end doing this because it would initialize the Padding Boundary and
2467 * leave the Packing Boundary initialized to 0 (16 bytes).)
2469 ingpadboundary = 1 << (INGPADBOUNDARY_GET(sge_params->sge_control) +
2470 X_INGPADBOUNDARY_SHIFT);
2471 if (is_t4(adapter->params.chip)) {
2472 s->fl_align = ingpadboundary;
2474 /* T5 has a different interpretation of one of the PCIe Packing
2477 ingpackboundary = INGPACKBOUNDARY_G(sge_params->sge_control2);
2478 if (ingpackboundary == INGPACKBOUNDARY_16B_X)
2479 ingpackboundary = 16;
2481 ingpackboundary = 1 << (ingpackboundary +
2482 INGPACKBOUNDARY_SHIFT_X);
2484 s->fl_align = max(ingpadboundary, ingpackboundary);
2487 /* A FL with <= fl_starve_thres buffers is starving and a periodic
2488 * timer will attempt to refill it. This needs to be larger than the
2489 * SGE's Egress Congestion Threshold. If it isn't, then we can get
2490 * stuck waiting for new packets while the SGE is waiting for us to
2491 * give it more Free List entries. (Note that the SGE's Egress
2492 * Congestion Threshold is in units of 2 Free List pointers.)
2495 = EGRTHRESHOLD_GET(sge_params->sge_congestion_control)*2 + 1;
2498 * Set up tasklet timers.
2500 setup_timer(&s->rx_timer, sge_rx_timer_cb, (unsigned long)adapter);
2501 setup_timer(&s->tx_timer, sge_tx_timer_cb, (unsigned long)adapter);
2504 * Initialize Forwarded Interrupt Queue lock.
2506 spin_lock_init(&s->intrq_lock);