drivers/net/ethernet/emulex/benet/be_cmds.c

   1 /*
   2  * Copyright (C) 2005 - 2014 Emulex
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License version 2
   7  * as published by the Free Software Foundation.  The full GNU General
   8  * Public License is included in this distribution in the file called COPYING.
   9  *
  10  * Contact Information:
  11  * linux-drivers@emulex.com
  12  *
  13  * Emulex
  14  * 3333 Susan Street
  15  * Costa Mesa, CA 92626
  16  */
  17
  18 #include <linux/module.h>
  19 #include "be.h"
  20 #include "be_cmds.h"
  21
  22 static char *be_port_misconfig_evt_desc[] = {
  23         "A valid SFP module detected",
  24         "Optics faulted/ incorrectly installed/ not installed.",
  25         "Optics of two types installed.",
  26         "Incompatible optics.",
  27         "Unknown port SFP status"
  28 };
  29
  30 static char *be_port_misconfig_remedy_desc[] = {
  31         "",
  32         "Reseat optics. If issue not resolved, replace",
  33         "Remove one optic or install matching pair of optics",
  34         "Replace with compatible optics for card to function",
  35         ""
  36 };
  37
  38 static struct be_cmd_priv_map cmd_priv_map[] = {
  39         {
  40                 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
  41                 CMD_SUBSYSTEM_ETH,
  42                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  43                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  44         },
  45         {
  46                 OPCODE_COMMON_GET_FLOW_CONTROL,
  47                 CMD_SUBSYSTEM_COMMON,
  48                 BE_PRIV_LNKQUERY | BE_PRIV_VHADM |
  49                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  50         },
  51         {
  52                 OPCODE_COMMON_SET_FLOW_CONTROL,
  53                 CMD_SUBSYSTEM_COMMON,
  54                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  55                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  56         },
  57         {
  58                 OPCODE_ETH_GET_PPORT_STATS,
  59                 CMD_SUBSYSTEM_ETH,
  60                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  61                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  62         },
  63         {
  64                 OPCODE_COMMON_GET_PHY_DETAILS,
  65                 CMD_SUBSYSTEM_COMMON,
  66                 BE_PRIV_LNKMGMT | BE_PRIV_VHADM |
  67                 BE_PRIV_DEVCFG | BE_PRIV_DEVSEC
  68         }
  69 };
  70
  71 static bool be_cmd_allowed(struct be_adapter *adapter, u8 opcode, u8 subsystem)
  72 {
  73         int i;
  74         int num_entries = sizeof(cmd_priv_map)/sizeof(struct be_cmd_priv_map);
  75         u32 cmd_privileges = adapter->cmd_privileges;
  76
  77         for (i = 0; i < num_entries; i++)
  78                 if (opcode == cmd_priv_map[i].opcode &&
  79                     subsystem == cmd_priv_map[i].subsystem)
  80                         if (!(cmd_privileges & cmd_priv_map[i].priv_mask))
  81                                 return false;
  82
  83         return true;
  84 }
  85
  86 static inline void *embedded_payload(struct be_mcc_wrb *wrb)
  87 {
  88         return wrb->payload.embedded_payload;
  89 }
  90
  91 static void be_mcc_notify(struct be_adapter *adapter)
  92 {
  93         struct be_queue_info *mccq = &adapter->mcc_obj.q;
  94         u32 val = 0;
  95
  96         if (be_error(adapter))
  97                 return;
  98
  99         val |= mccq->id & DB_MCCQ_RING_ID_MASK;
 100         val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
 101
 102         wmb();
 103         iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
 104 }
 105
 106 /* To check if valid bit is set, check the entire word as we don't know
 107  * the endianness of the data (old entry is host endian while a new entry is
 108  * little endian) */
 109 static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
 110 {
 111         u32 flags;
 112
 113         if (compl->flags != 0) {
 114                 flags = le32_to_cpu(compl->flags);
 115                 if (flags & CQE_FLAGS_VALID_MASK) {
 116                         compl->flags = flags;
 117                         return true;
 118                 }
 119         }
 120         return false;
 121 }
 122
 123 /* Need to reset the entire word that houses the valid bit */
 124 static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
 125 {
 126         compl->flags = 0;
 127 }
 128
 129 static struct be_cmd_resp_hdr *be_decode_resp_hdr(u32 tag0, u32 tag1)
 130 {
 131         unsigned long addr;
 132
 133         addr = tag1;
 134         addr = ((addr << 16) << 16) | tag0;
 135         return (void *)addr;
 136 }
 137
 138 static bool be_skip_err_log(u8 opcode, u16 base_status, u16 addl_status)
 139 {
 140         if (base_status == MCC_STATUS_NOT_SUPPORTED ||
 141             base_status == MCC_STATUS_ILLEGAL_REQUEST ||
 142             addl_status == MCC_ADDL_STATUS_TOO_MANY_INTERFACES ||
 143             (opcode == OPCODE_COMMON_WRITE_FLASHROM &&
 144             (base_status == MCC_STATUS_ILLEGAL_FIELD ||
 145              addl_status == MCC_ADDL_STATUS_FLASH_IMAGE_CRC_MISMATCH)))
 146                 return true;
 147         else
 148                 return false;
 149 }
 150
 151 /* Place holder for all the async MCC cmds wherein the caller is not in a busy
 152  * loop (has not issued be_mcc_notify_wait())
 153  */
 154 static void be_async_cmd_process(struct be_adapter *adapter,
 155                                  struct be_mcc_compl *compl,
 156                                  struct be_cmd_resp_hdr *resp_hdr)
 157 {
 158         enum mcc_base_status base_status = base_status(compl->status);
 159         u8 opcode = 0, subsystem = 0;
 160
 161         if (resp_hdr) {
 162                 opcode = resp_hdr->opcode;
 163                 subsystem = resp_hdr->subsystem;
 164         }
 165
 166         if (opcode == OPCODE_LOWLEVEL_LOOPBACK_TEST &&
 167             subsystem == CMD_SUBSYSTEM_LOWLEVEL) {
 168                 complete(&adapter->et_cmd_compl);
 169                 return;
 170         }
 171
 172         if ((opcode == OPCODE_COMMON_WRITE_FLASHROM ||
 173              opcode == OPCODE_COMMON_WRITE_OBJECT) &&
 174             subsystem == CMD_SUBSYSTEM_COMMON) {
 175                 adapter->flash_status = compl->status;
 176                 complete(&adapter->et_cmd_compl);
 177                 return;
 178         }
 179
 180         if ((opcode == OPCODE_ETH_GET_STATISTICS ||
 181              opcode == OPCODE_ETH_GET_PPORT_STATS) &&
 182             subsystem == CMD_SUBSYSTEM_ETH &&
 183             base_status == MCC_STATUS_SUCCESS) {
 184                 be_parse_stats(adapter);
 185                 adapter->stats_cmd_sent = false;
 186                 return;
 187         }
 188
 189         if (opcode == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES &&
 190             subsystem == CMD_SUBSYSTEM_COMMON) {
 191                 if (base_status == MCC_STATUS_SUCCESS) {
 192                         struct be_cmd_resp_get_cntl_addnl_attribs *resp =
 193                                                         (void *)resp_hdr;
 194                         adapter->drv_stats.be_on_die_temperature =
 195                                                 resp->on_die_temperature;
 196                 } else {
 197                         adapter->be_get_temp_freq = 0;
 198                 }
 199                 return;
 200         }
 201 }
 202
 203 static int be_mcc_compl_process(struct be_adapter *adapter,
 204                                 struct be_mcc_compl *compl)
 205 {
 206         enum mcc_base_status base_status;
 207         enum mcc_addl_status addl_status;
 208         struct be_cmd_resp_hdr *resp_hdr;
 209         u8 opcode = 0, subsystem = 0;
 210
 211         /* Just swap the status to host endian; mcc tag is opaquely copied
 212          * from mcc_wrb */
 213         be_dws_le_to_cpu(compl, 4);
 214
 215         base_status = base_status(compl->status);
 216         addl_status = addl_status(compl->status);
 217
 218         resp_hdr = be_decode_resp_hdr(compl->tag0, compl->tag1);
 219         if (resp_hdr) {
 220                 opcode = resp_hdr->opcode;
 221                 subsystem = resp_hdr->subsystem;
 222         }
 223
 224         be_async_cmd_process(adapter, compl, resp_hdr);
 225
 226         if (base_status != MCC_STATUS_SUCCESS &&
 227             !be_skip_err_log(opcode, base_status, addl_status)) {
 228                 if (base_status == MCC_STATUS_UNAUTHORIZED_REQUEST) {
 229                         dev_warn(&adapter->pdev->dev,
 230                                  "VF is not privileged to issue opcode %d-%d\n",
 231                                  opcode, subsystem);
 232                 } else {
 233                         dev_err(&adapter->pdev->dev,
 234                                 "opcode %d-%d failed:status %d-%d\n",
 235                                 opcode, subsystem, base_status, addl_status);
 236                 }
 237         }
 238         return compl->status;
 239 }
 240
 241 /* Link state evt is a string of bytes; no need for endian swapping */
 242 static void be_async_link_state_process(struct be_adapter *adapter,
 243                                         struct be_mcc_compl *compl)
 244 {
 245         struct be_async_event_link_state *evt =
 246                         (struct be_async_event_link_state *)compl;
 247
 248         /* When link status changes, link speed must be re-queried from FW */
 249         adapter->phy.link_speed = -1;
 250
 251         /* On BEx the FW does not send a separate link status
 252          * notification for physical and logical link.
 253          * On other chips just process the logical link
 254          * status notification
 255          */
 256         if (!BEx_chip(adapter) &&
 257             !(evt->port_link_status & LOGICAL_LINK_STATUS_MASK))
 258                 return;
 259
 260         /* For the initial link status do not rely on the ASYNC event as
 261          * it may not be received in some cases.
 262          */
 263         if (adapter->flags & BE_FLAGS_LINK_STATUS_INIT)
 264                 be_link_status_update(adapter,
 265                                       evt->port_link_status & LINK_STATUS_MASK);
 266 }
 267
 268 static void be_async_port_misconfig_event_process(struct be_adapter *adapter,
 269                                                   struct be_mcc_compl *compl)
 270 {
 271         struct be_async_event_misconfig_port *evt =
 272                         (struct be_async_event_misconfig_port *)compl;
 273         u32 sfp_mismatch_evt = le32_to_cpu(evt->event_data_word1);
 274         struct device *dev = &adapter->pdev->dev;
 275         u8 port_misconfig_evt;
 276
 277         port_misconfig_evt =
 278                 ((sfp_mismatch_evt >> (adapter->hba_port_num * 8)) & 0xff);
 279
 280         /* Log an error message that would allow a user to determine
 281          * whether the SFPs have an issue
 282          */
 283         dev_info(dev, "Port %c: %s %s", adapter->port_name,
 284                  be_port_misconfig_evt_desc[port_misconfig_evt],
 285                  be_port_misconfig_remedy_desc[port_misconfig_evt]);
 286
 287         if (port_misconfig_evt == INCOMPATIBLE_SFP)
 288                 adapter->flags |= BE_FLAGS_EVT_INCOMPATIBLE_SFP;
 289 }
 290
 291 /* Grp5 CoS Priority evt */
 292 static void be_async_grp5_cos_priority_process(struct be_adapter *adapter,
 293                                                struct be_mcc_compl *compl)
 294 {
 295         struct be_async_event_grp5_cos_priority *evt =
 296                         (struct be_async_event_grp5_cos_priority *)compl;
 297
 298         if (evt->valid) {
 299                 adapter->vlan_prio_bmap = evt->available_priority_bmap;
 300                 adapter->recommended_prio &= ~VLAN_PRIO_MASK;
 301                 adapter->recommended_prio =
 302                         evt->reco_default_priority << VLAN_PRIO_SHIFT;
 303         }
 304 }
 305
 306 /* Grp5 QOS Speed evt: qos_link_speed is in units of 10 Mbps */
 307 static void be_async_grp5_qos_speed_process(struct be_adapter *adapter,
 308                                             struct be_mcc_compl *compl)
 309 {
 310         struct be_async_event_grp5_qos_link_speed *evt =
 311                         (struct be_async_event_grp5_qos_link_speed *)compl;
 312
 313         if (adapter->phy.link_speed >= 0 &&
 314             evt->physical_port == adapter->port_num)
 315                 adapter->phy.link_speed = le16_to_cpu(evt->qos_link_speed) * 10;
 316 }
 317
 318 /*Grp5 PVID evt*/
 319 static void be_async_grp5_pvid_state_process(struct be_adapter *adapter,
 320                                              struct be_mcc_compl *compl)
 321 {
 322         struct be_async_event_grp5_pvid_state *evt =
 323                         (struct be_async_event_grp5_pvid_state *)compl;
 324
 325         if (evt->enabled) {
 326                 adapter->pvid = le16_to_cpu(evt->tag) & VLAN_VID_MASK;
 327                 dev_info(&adapter->pdev->dev, "LPVID: %d\n", adapter->pvid);
 328         } else {
 329                 adapter->pvid = 0;
 330         }
 331 }
 332
 333 static void be_async_grp5_evt_process(struct be_adapter *adapter,
 334                                       struct be_mcc_compl *compl)
 335 {
 336         u8 event_type = (compl->flags >> ASYNC_EVENT_TYPE_SHIFT) &
 337                                 ASYNC_EVENT_TYPE_MASK;
 338
 339         switch (event_type) {
 340         case ASYNC_EVENT_COS_PRIORITY:
 341                 be_async_grp5_cos_priority_process(adapter, compl);
 342                 break;
 343         case ASYNC_EVENT_QOS_SPEED:
 344                 be_async_grp5_qos_speed_process(adapter, compl);
 345                 break;
 346         case ASYNC_EVENT_PVID_STATE:
 347                 be_async_grp5_pvid_state_process(adapter, compl);
 348                 break;
 349         default:
 350                 break;
 351         }
 352 }
 353
 354 static void be_async_dbg_evt_process(struct be_adapter *adapter,
 355                                      struct be_mcc_compl *cmp)
 356 {
 357         u8 event_type = 0;
 358         struct be_async_event_qnq *evt = (struct be_async_event_qnq *)cmp;
 359
 360         event_type = (cmp->flags >> ASYNC_EVENT_TYPE_SHIFT) &
 361                         ASYNC_EVENT_TYPE_MASK;
 362
 363         switch (event_type) {
 364         case ASYNC_DEBUG_EVENT_TYPE_QNQ:
 365                 if (evt->valid)
 366                         adapter->qnq_vid = le16_to_cpu(evt->vlan_tag);
 367                 adapter->flags |= BE_FLAGS_QNQ_ASYNC_EVT_RCVD;
 368         break;
 369         default:
 370                 dev_warn(&adapter->pdev->dev, "Unknown debug event 0x%x!\n",
 371                          event_type);
 372         break;
 373         }
 374 }
 375
 376 static void be_async_sliport_evt_process(struct be_adapter *adapter,
 377                                          struct be_mcc_compl *cmp)
 378 {
 379         u8 event_type = (cmp->flags >> ASYNC_EVENT_TYPE_SHIFT) &
 380                         ASYNC_EVENT_TYPE_MASK;
 381
 382         if (event_type == ASYNC_EVENT_PORT_MISCONFIG)
 383                 be_async_port_misconfig_event_process(adapter, cmp);
 384 }
 385
 386 static inline bool is_link_state_evt(u32 flags)
 387 {
 388         return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
 389                         ASYNC_EVENT_CODE_LINK_STATE;
 390 }
 391
 392 static inline bool is_grp5_evt(u32 flags)
 393 {
 394         return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
 395                         ASYNC_EVENT_CODE_GRP_5;
 396 }
 397
 398 static inline bool is_dbg_evt(u32 flags)
 399 {
 400         return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
 401                         ASYNC_EVENT_CODE_QNQ;
 402 }
 403
 404 static inline bool is_sliport_evt(u32 flags)
 405 {
 406         return ((flags >> ASYNC_EVENT_CODE_SHIFT) & ASYNC_EVENT_CODE_MASK) ==
 407                 ASYNC_EVENT_CODE_SLIPORT;
 408 }
 409
 410 static void be_mcc_event_process(struct be_adapter *adapter,
 411                                  struct be_mcc_compl *compl)
 412 {
 413         if (is_link_state_evt(compl->flags))
 414                 be_async_link_state_process(adapter, compl);
 415         else if (is_grp5_evt(compl->flags))
 416                 be_async_grp5_evt_process(adapter, compl);
 417         else if (is_dbg_evt(compl->flags))
 418                 be_async_dbg_evt_process(adapter, compl);
 419         else if (is_sliport_evt(compl->flags))
 420                 be_async_sliport_evt_process(adapter, compl);
 421 }
 422
 423 static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
 424 {
 425         struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
 426         struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
 427
 428         if (be_mcc_compl_is_new(compl)) {
 429                 queue_tail_inc(mcc_cq);
 430                 return compl;
 431         }
 432         return NULL;
 433 }
 434
 435 void be_async_mcc_enable(struct be_adapter *adapter)
 436 {
 437         spin_lock_bh(&adapter->mcc_cq_lock);
 438
 439         be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
 440         adapter->mcc_obj.rearm_cq = true;
 441
 442         spin_unlock_bh(&adapter->mcc_cq_lock);
 443 }
 444
 445 void be_async_mcc_disable(struct be_adapter *adapter)
 446 {
 447         spin_lock_bh(&adapter->mcc_cq_lock);
 448
 449         adapter->mcc_obj.rearm_cq = false;
 450         be_cq_notify(adapter, adapter->mcc_obj.cq.id, false, 0);
 451
 452         spin_unlock_bh(&adapter->mcc_cq_lock);
 453 }
 454
 455 int be_process_mcc(struct be_adapter *adapter)
 456 {
 457         struct be_mcc_compl *compl;
 458         int num = 0, status = 0;
 459         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 460
 461         spin_lock(&adapter->mcc_cq_lock);
 462
 463         while ((compl = be_mcc_compl_get(adapter))) {
 464                 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
 465                         be_mcc_event_process(adapter, compl);
 466                 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
 467                         status = be_mcc_compl_process(adapter, compl);
 468                         atomic_dec(&mcc_obj->q.used);
 469                 }
 470                 be_mcc_compl_use(compl);
 471                 num++;
 472         }
 473
 474         if (num)
 475                 be_cq_notify(adapter, mcc_obj->cq.id, mcc_obj->rearm_cq, num);
 476
 477         spin_unlock(&adapter->mcc_cq_lock);
 478         return status;
 479 }
 480
 481 /* Wait till no more pending mcc requests are present */
 482 static int be_mcc_wait_compl(struct be_adapter *adapter)
 483 {
 484 #define mcc_timeout             120000 /* 12s timeout */
 485         int i, status = 0;
 486         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 487
 488         for (i = 0; i < mcc_timeout; i++) {
 489                 if (be_error(adapter))
 490                         return -EIO;
 491
 492                 local_bh_disable();
 493                 status = be_process_mcc(adapter);
 494                 local_bh_enable();
 495
 496                 if (atomic_read(&mcc_obj->q.used) == 0)
 497                         break;
 498                 udelay(100);
 499         }
 500         if (i == mcc_timeout) {
 501                 dev_err(&adapter->pdev->dev, "FW not responding\n");
 502                 adapter->fw_timeout = true;
 503                 return -EIO;
 504         }
 505         return status;
 506 }
 507
 508 /* Notify MCC requests and wait for completion */
 509 static int be_mcc_notify_wait(struct be_adapter *adapter)
 510 {
 511         int status;
 512         struct be_mcc_wrb *wrb;
 513         struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
 514         u16 index = mcc_obj->q.head;
 515         struct be_cmd_resp_hdr *resp;
 516
 517         index_dec(&index, mcc_obj->q.len);
 518         wrb = queue_index_node(&mcc_obj->q, index);
 519
 520         resp = be_decode_resp_hdr(wrb->tag0, wrb->tag1);
 521
 522         be_mcc_notify(adapter);
 523
 524         status = be_mcc_wait_compl(adapter);
 525         if (status == -EIO)
 526                 goto out;
 527
 528         status = (resp->base_status |
 529                   ((resp->addl_status & CQE_ADDL_STATUS_MASK) <<
 530                    CQE_ADDL_STATUS_SHIFT));
 531 out:
 532         return status;
 533 }
 534
 535 static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
 536 {
 537         int msecs = 0;
 538         u32 ready;
 539
 540         do {
 541                 if (be_error(adapter))
 542                         return -EIO;
 543
 544                 ready = ioread32(db);
 545                 if (ready == 0xffffffff)
 546                         return -1;
 547
 548                 ready &= MPU_MAILBOX_DB_RDY_MASK;
 549                 if (ready)
 550                         break;
 551
 552                 if (msecs > 4000) {
 553                         dev_err(&adapter->pdev->dev, "FW not responding\n");
 554                         adapter->fw_timeout = true;
 555                         be_detect_error(adapter);
 556                         return -1;
 557                 }
 558
 559                 msleep(1);
 560                 msecs++;
 561         } while (true);
 562
 563         return 0;
 564 }
 565
 566 /*
 567  * Insert the mailbox address into the doorbell in two steps
 568  * Polls on the mbox doorbell till a command completion (or a timeout) occurs
 569  */
 570 static int be_mbox_notify_wait(struct be_adapter *adapter)
 571 {
 572         int status;
 573         u32 val = 0;
 574         void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
 575         struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
 576         struct be_mcc_mailbox *mbox = mbox_mem->va;
 577         struct be_mcc_compl *compl = &mbox->compl;
 578
 579         /* wait for ready to be set */
 580         status = be_mbox_db_ready_wait(adapter, db);
 581         if (status != 0)
 582                 return status;
 583
 584         val |= MPU_MAILBOX_DB_HI_MASK;
 585         /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
 586         val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
 587         iowrite32(val, db);
 588
 589         /* wait for ready to be set */
 590         status = be_mbox_db_ready_wait(adapter, db);
 591         if (status != 0)
 592                 return status;
 593
 594         val = 0;
 595         /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
 596         val |= (u32)(mbox_mem->dma >> 4) << 2;
 597         iowrite32(val, db);
 598
 599         status = be_mbox_db_ready_wait(adapter, db);
 600         if (status != 0)
 601                 return status;
 602
 603         /* A cq entry has been made now */
 604         if (be_mcc_compl_is_new(compl)) {
 605                 status = be_mcc_compl_process(adapter, &mbox->compl);
 606                 be_mcc_compl_use(compl);
 607                 if (status)
 608                         return status;
 609         } else {
 610                 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
 611                 return -1;
 612         }
 613         return 0;
 614 }
 615
 616 static u16 be_POST_stage_get(struct be_adapter *adapter)
 617 {
 618         u32 sem;
 619
 620         if (BEx_chip(adapter))
 621                 sem  = ioread32(adapter->csr + SLIPORT_SEMAPHORE_OFFSET_BEx);
 622         else
 623                 pci_read_config_dword(adapter->pdev,
 624                                       SLIPORT_SEMAPHORE_OFFSET_SH, &sem);
 625
 626         return sem & POST_STAGE_MASK;
 627 }
 628
 629 static int lancer_wait_ready(struct be_adapter *adapter)
 630 {
 631 #define SLIPORT_READY_TIMEOUT 30
 632         u32 sliport_status;
 633         int i;
 634
 635         for (i = 0; i < SLIPORT_READY_TIMEOUT; i++) {
 636                 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
 637                 if (sliport_status & SLIPORT_STATUS_RDY_MASK)
 638                         break;
 639
 640                 msleep(1000);
 641         }
 642
 643         if (i == SLIPORT_READY_TIMEOUT)
 644                 return sliport_status ? : -1;
 645
 646         return 0;
 647 }
 648
 649 static bool lancer_provisioning_error(struct be_adapter *adapter)
 650 {
 651         u32 sliport_status = 0, sliport_err1 = 0, sliport_err2 = 0;
 652
 653         sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
 654         if (sliport_status & SLIPORT_STATUS_ERR_MASK) {
 655                 sliport_err1 = ioread32(adapter->db + SLIPORT_ERROR1_OFFSET);
 656                 sliport_err2 = ioread32(adapter->db + SLIPORT_ERROR2_OFFSET);
 657
 658                 if (sliport_err1 == SLIPORT_ERROR_NO_RESOURCE1 &&
 659                     sliport_err2 == SLIPORT_ERROR_NO_RESOURCE2)
 660                         return true;
 661         }
 662         return false;
 663 }
 664
 665 int lancer_test_and_set_rdy_state(struct be_adapter *adapter)
 666 {
 667         int status;
 668         u32 sliport_status, err, reset_needed;
 669         bool resource_error;
 670
 671         resource_error = lancer_provisioning_error(adapter);
 672         if (resource_error)
 673                 return -EAGAIN;
 674
 675         status = lancer_wait_ready(adapter);
 676         if (!status) {
 677                 sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
 678                 err = sliport_status & SLIPORT_STATUS_ERR_MASK;
 679                 reset_needed = sliport_status & SLIPORT_STATUS_RN_MASK;
 680                 if (err && reset_needed) {
 681                         iowrite32(SLI_PORT_CONTROL_IP_MASK,
 682                                   adapter->db + SLIPORT_CONTROL_OFFSET);
 683
 684                         /* check if adapter has corrected the error */
 685                         status = lancer_wait_ready(adapter);
 686                         sliport_status = ioread32(adapter->db +
 687                                                   SLIPORT_STATUS_OFFSET);
 688                         sliport_status &= (SLIPORT_STATUS_ERR_MASK |
 689                                                 SLIPORT_STATUS_RN_MASK);
 690                         if (status || sliport_status)
 691                                 status = -1;
 692                 } else if (err || reset_needed) {
 693                         status = -1;
 694                 }
 695         }
 696         /* Stop error recovery if error is not recoverable.
 697          * No resource error is temporary errors and will go away
 698          * when PF provisions resources.
 699          */
 700         resource_error = lancer_provisioning_error(adapter);
 701         if (resource_error)
 702                 status = -EAGAIN;
 703
 704         return status;
 705 }
 706
 707 int be_fw_wait_ready(struct be_adapter *adapter)
 708 {
 709         u16 stage;
 710         int status, timeout = 0;
 711         struct device *dev = &adapter->pdev->dev;
 712
 713         if (lancer_chip(adapter)) {
 714                 status = lancer_wait_ready(adapter);
 715                 if (status) {
 716                         stage = status;
 717                         goto err;
 718                 }
 719                 return 0;
 720         }
 721
 722         do {
 723                 stage = be_POST_stage_get(adapter);
 724                 if (stage == POST_STAGE_ARMFW_RDY)
 725                         return 0;
 726
 727                 dev_info(dev, "Waiting for POST, %ds elapsed\n", timeout);
 728                 if (msleep_interruptible(2000)) {
 729                         dev_err(dev, "Waiting for POST aborted\n");
 730                         return -EINTR;
 731                 }
 732                 timeout += 2;
 733         } while (timeout < 60);
 734
 735 err:
 736         dev_err(dev, "POST timeout; stage=%#x\n", stage);
 737         return -1;
 738 }
 739
 740 static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
 741 {
 742         return &wrb->payload.sgl[0];
 743 }
 744
 745 static inline void fill_wrb_tags(struct be_mcc_wrb *wrb, unsigned long addr)
 746 {
 747         wrb->tag0 = addr & 0xFFFFFFFF;
 748         wrb->tag1 = upper_32_bits(addr);
 749 }
 750
 751 /* Don't touch the hdr after it's prepared */
 752 /* mem will be NULL for embedded commands */
 753 static void be_wrb_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
 754                                    u8 subsystem, u8 opcode, int cmd_len,
 755                                    struct be_mcc_wrb *wrb,
 756                                    struct be_dma_mem *mem)
 757 {
 758         struct be_sge *sge;
 759
 760         req_hdr->opcode = opcode;
 761         req_hdr->subsystem = subsystem;
 762         req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
 763         req_hdr->version = 0;
 764         fill_wrb_tags(wrb, (ulong) req_hdr);
 765         wrb->payload_length = cmd_len;
 766         if (mem) {
 767                 wrb->embedded |= (1 & MCC_WRB_SGE_CNT_MASK) <<
 768                         MCC_WRB_SGE_CNT_SHIFT;
 769                 sge = nonembedded_sgl(wrb);
 770                 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
 771                 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
 772                 sge->len = cpu_to_le32(mem->size);
 773         } else
 774                 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
 775         be_dws_cpu_to_le(wrb, 8);
 776 }
 777
 778 static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
 779                                       struct be_dma_mem *mem)
 780 {
 781         int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
 782         u64 dma = (u64)mem->dma;
 783
 784         for (i = 0; i < buf_pages; i++) {
 785                 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
 786                 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
 787                 dma += PAGE_SIZE_4K;
 788         }
 789 }
 790
 791 static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
 792 {
 793         struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
 794         struct be_mcc_wrb *wrb
 795                 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
 796         memset(wrb, 0, sizeof(*wrb));
 797         return wrb;
 798 }
 799
 800 static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
 801 {
 802         struct be_queue_info *mccq = &adapter->mcc_obj.q;
 803         struct be_mcc_wrb *wrb;
 804
 805         if (!mccq->created)
 806                 return NULL;
 807
 808         if (atomic_read(&mccq->used) >= mccq->len)
 809                 return NULL;
 810
 811         wrb = queue_head_node(mccq);
 812         queue_head_inc(mccq);
 813         atomic_inc(&mccq->used);
 814         memset(wrb, 0, sizeof(*wrb));
 815         return wrb;
 816 }
 817
 818 static bool use_mcc(struct be_adapter *adapter)
 819 {
 820         return adapter->mcc_obj.q.created;
 821 }
 822
 823 /* Must be used only in process context */
 824 static int be_cmd_lock(struct be_adapter *adapter)
 825 {
 826         if (use_mcc(adapter)) {
 827                 spin_lock_bh(&adapter->mcc_lock);
 828                 return 0;
 829         } else {
 830                 return mutex_lock_interruptible(&adapter->mbox_lock);
 831         }
 832 }
 833
 834 /* Must be used only in process context */
 835 static void be_cmd_unlock(struct be_adapter *adapter)
 836 {
 837         if (use_mcc(adapter))
 838                 spin_unlock_bh(&adapter->mcc_lock);
 839         else
 840                 return mutex_unlock(&adapter->mbox_lock);
 841 }
 842
 843 static struct be_mcc_wrb *be_cmd_copy(struct be_adapter *adapter,
 844                                       struct be_mcc_wrb *wrb)
 845 {
 846         struct be_mcc_wrb *dest_wrb;
 847
 848         if (use_mcc(adapter)) {
 849                 dest_wrb = wrb_from_mccq(adapter);
 850                 if (!dest_wrb)
 851                         return NULL;
 852         } else {
 853                 dest_wrb = wrb_from_mbox(adapter);
 854         }
 855
 856         memcpy(dest_wrb, wrb, sizeof(*wrb));
 857         if (wrb->embedded & cpu_to_le32(MCC_WRB_EMBEDDED_MASK))
 858                 fill_wrb_tags(dest_wrb, (ulong) embedded_payload(wrb));
 859
 860         return dest_wrb;
 861 }
 862
 863 /* Must be used only in process context */
 864 static int be_cmd_notify_wait(struct be_adapter *adapter,
 865                               struct be_mcc_wrb *wrb)
 866 {
 867         struct be_mcc_wrb *dest_wrb;
 868         int status;
 869
 870         status = be_cmd_lock(adapter);
 871         if (status)
 872                 return status;
 873
 874         dest_wrb = be_cmd_copy(adapter, wrb);
 875         if (!dest_wrb)
 876                 return -EBUSY;
 877
 878         if (use_mcc(adapter))
 879                 status = be_mcc_notify_wait(adapter);
 880         else
 881                 status = be_mbox_notify_wait(adapter);
 882
 883         if (!status)
 884                 memcpy(wrb, dest_wrb, sizeof(*wrb));
 885
 886         be_cmd_unlock(adapter);
 887         return status;
 888 }
 889
 890 /* Tell fw we're about to start firing cmds by writing a
 891  * special pattern across the wrb hdr; uses mbox
 892  */
 893 int be_cmd_fw_init(struct be_adapter *adapter)
 894 {
 895         u8 *wrb;
 896         int status;
 897
 898         if (lancer_chip(adapter))
 899                 return 0;
 900
 901         if (mutex_lock_interruptible(&adapter->mbox_lock))
 902                 return -1;
 903
 904         wrb = (u8 *)wrb_from_mbox(adapter);
 905         *wrb++ = 0xFF;
 906         *wrb++ = 0x12;
 907         *wrb++ = 0x34;
 908         *wrb++ = 0xFF;
 909         *wrb++ = 0xFF;
 910         *wrb++ = 0x56;
 911         *wrb++ = 0x78;
 912         *wrb = 0xFF;
 913
 914         status = be_mbox_notify_wait(adapter);
 915
 916         mutex_unlock(&adapter->mbox_lock);
 917         return status;
 918 }
 919
 920 /* Tell fw we're done with firing cmds by writing a
 921  * special pattern across the wrb hdr; uses mbox
 922  */
 923 int be_cmd_fw_clean(struct be_adapter *adapter)
 924 {
 925         u8 *wrb;
 926         int status;
 927
 928         if (lancer_chip(adapter))
 929                 return 0;
 930
 931         if (mutex_lock_interruptible(&adapter->mbox_lock))
 932                 return -1;
 933
 934         wrb = (u8 *)wrb_from_mbox(adapter);
 935         *wrb++ = 0xFF;
 936         *wrb++ = 0xAA;
 937         *wrb++ = 0xBB;
 938         *wrb++ = 0xFF;
 939         *wrb++ = 0xFF;
 940         *wrb++ = 0xCC;
 941         *wrb++ = 0xDD;
 942         *wrb = 0xFF;
 943
 944         status = be_mbox_notify_wait(adapter);
 945
 946         mutex_unlock(&adapter->mbox_lock);
 947         return status;
 948 }
 949
 950 int be_cmd_eq_create(struct be_adapter *adapter, struct be_eq_obj *eqo)
 951 {
 952         struct be_mcc_wrb *wrb;
 953         struct be_cmd_req_eq_create *req;
 954         struct be_dma_mem *q_mem = &eqo->q.dma_mem;
 955         int status, ver = 0;
 956
 957         if (mutex_lock_interruptible(&adapter->mbox_lock))
 958                 return -1;
 959
 960         wrb = wrb_from_mbox(adapter);
 961         req = embedded_payload(wrb);
 962
 963         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
 964                                OPCODE_COMMON_EQ_CREATE, sizeof(*req), wrb,
 965                                NULL);
 966
 967         /* Support for EQ_CREATEv2 available only SH-R onwards */
 968         if (!(BEx_chip(adapter) || lancer_chip(adapter)))
 969                 ver = 2;
 970
 971         req->hdr.version = ver;
 972         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
 973
 974         AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
 975         /* 4byte eqe*/
 976         AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
 977         AMAP_SET_BITS(struct amap_eq_context, count, req->context,
 978                       __ilog2_u32(eqo->q.len / 256));
 979         be_dws_cpu_to_le(req->context, sizeof(req->context));
 980
 981         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
 982
 983         status = be_mbox_notify_wait(adapter);
 984         if (!status) {
 985                 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
 986
 987                 eqo->q.id = le16_to_cpu(resp->eq_id);
 988                 eqo->msix_idx =
 989                         (ver == 2) ? le16_to_cpu(resp->msix_idx) : eqo->idx;
 990                 eqo->q.created = true;
 991         }
 992
 993         mutex_unlock(&adapter->mbox_lock);
 994         return status;
 995 }
 996
 997 /* Use MCC */
 998 int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
 999                           bool permanent, u32 if_handle, u32 pmac_id)
1000 {
1001         struct be_mcc_wrb *wrb;
1002         struct be_cmd_req_mac_query *req;
1003         int status;
1004
1005         spin_lock_bh(&adapter->mcc_lock);
1006
1007         wrb = wrb_from_mccq(adapter);
1008         if (!wrb) {
1009                 status = -EBUSY;
1010                 goto err;
1011         }
1012         req = embedded_payload(wrb);
1013
1014         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1015                                OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req), wrb,
1016                                NULL);
1017         req->type = MAC_ADDRESS_TYPE_NETWORK;
1018         if (permanent) {
1019                 req->permanent = 1;
1020         } else {
1021                 req->if_id = cpu_to_le16((u16)if_handle);
1022                 req->pmac_id = cpu_to_le32(pmac_id);
1023                 req->permanent = 0;
1024         }
1025
1026         status = be_mcc_notify_wait(adapter);
1027         if (!status) {
1028                 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
1029
1030                 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
1031         }
1032
1033 err:
1034         spin_unlock_bh(&adapter->mcc_lock);
1035         return status;
1036 }
1037
1038 /* Uses synchronous MCCQ */
1039 int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
1040                     u32 if_id, u32 *pmac_id, u32 domain)
1041 {
1042         struct be_mcc_wrb *wrb;
1043         struct be_cmd_req_pmac_add *req;
1044         int status;
1045
1046         spin_lock_bh(&adapter->mcc_lock);
1047
1048         wrb = wrb_from_mccq(adapter);
1049         if (!wrb) {
1050                 status = -EBUSY;
1051                 goto err;
1052         }
1053         req = embedded_payload(wrb);
1054
1055         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1056                                OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req), wrb,
1057                                NULL);
1058
1059         req->hdr.domain = domain;
1060         req->if_id = cpu_to_le32(if_id);
1061         memcpy(req->mac_address, mac_addr, ETH_ALEN);
1062
1063         status = be_mcc_notify_wait(adapter);
1064         if (!status) {
1065                 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
1066
1067                 *pmac_id = le32_to_cpu(resp->pmac_id);
1068         }
1069
1070 err:
1071         spin_unlock_bh(&adapter->mcc_lock);
1072
1073          if (status == MCC_STATUS_UNAUTHORIZED_REQUEST)
1074                 status = -EPERM;
1075
1076         return status;
1077 }
1078
1079 /* Uses synchronous MCCQ */
1080 int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, int pmac_id, u32 dom)
1081 {
1082         struct be_mcc_wrb *wrb;
1083         struct be_cmd_req_pmac_del *req;
1084         int status;
1085
1086         if (pmac_id == -1)
1087                 return 0;
1088
1089         spin_lock_bh(&adapter->mcc_lock);
1090
1091         wrb = wrb_from_mccq(adapter);
1092         if (!wrb) {
1093                 status = -EBUSY;
1094                 goto err;
1095         }
1096         req = embedded_payload(wrb);
1097
1098         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1099                                OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req),
1100                                wrb, NULL);
1101
1102         req->hdr.domain = dom;
1103         req->if_id = cpu_to_le32(if_id);
1104         req->pmac_id = cpu_to_le32(pmac_id);
1105
1106         status = be_mcc_notify_wait(adapter);
1107
1108 err:
1109         spin_unlock_bh(&adapter->mcc_lock);
1110         return status;
1111 }
1112
1113 /* Uses Mbox */
1114 int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq,
1115                      struct be_queue_info *eq, bool no_delay, int coalesce_wm)
1116 {
1117         struct be_mcc_wrb *wrb;
1118         struct be_cmd_req_cq_create *req;
1119         struct be_dma_mem *q_mem = &cq->dma_mem;
1120         void *ctxt;
1121         int status;
1122
1123         if (mutex_lock_interruptible(&adapter->mbox_lock))
1124                 return -1;
1125
1126         wrb = wrb_from_mbox(adapter);
1127         req = embedded_payload(wrb);
1128         ctxt = &req->context;
1129
1130         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1131                                OPCODE_COMMON_CQ_CREATE, sizeof(*req), wrb,
1132                                NULL);
1133
1134         req->num_pages =  cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1135
1136         if (BEx_chip(adapter)) {
1137                 AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt,
1138                               coalesce_wm);
1139                 AMAP_SET_BITS(struct amap_cq_context_be, nodelay,
1140                               ctxt, no_delay);
1141                 AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt,
1142                               __ilog2_u32(cq->len / 256));
1143                 AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1);
1144                 AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1);
1145                 AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id);
1146         } else {
1147                 req->hdr.version = 2;
1148                 req->page_size = 1; /* 1 for 4K */
1149
1150                 /* coalesce-wm field in this cmd is not relevant to Lancer.
1151                  * Lancer uses COMMON_MODIFY_CQ to set this field
1152                  */
1153                 if (!lancer_chip(adapter))
1154                         AMAP_SET_BITS(struct amap_cq_context_v2, coalescwm,
1155                                       ctxt, coalesce_wm);
1156                 AMAP_SET_BITS(struct amap_cq_context_v2, nodelay, ctxt,
1157                               no_delay);
1158                 AMAP_SET_BITS(struct amap_cq_context_v2, count, ctxt,
1159                               __ilog2_u32(cq->len / 256));
1160                 AMAP_SET_BITS(struct amap_cq_context_v2, valid, ctxt, 1);
1161                 AMAP_SET_BITS(struct amap_cq_context_v2, eventable, ctxt, 1);
1162                 AMAP_SET_BITS(struct amap_cq_context_v2, eqid, ctxt, eq->id);
1163         }
1164
1165         be_dws_cpu_to_le(ctxt, sizeof(req->context));
1166
1167         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1168
1169         status = be_mbox_notify_wait(adapter);
1170         if (!status) {
1171                 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
1172
1173                 cq->id = le16_to_cpu(resp->cq_id);
1174                 cq->created = true;
1175         }
1176
1177         mutex_unlock(&adapter->mbox_lock);
1178
1179         return status;
1180 }
1181
1182 static u32 be_encoded_q_len(int q_len)
1183 {
1184         u32 len_encoded = fls(q_len); /* log2(len) + 1 */
1185
1186         if (len_encoded == 16)
1187                 len_encoded = 0;
1188         return len_encoded;
1189 }
1190
1191 static int be_cmd_mccq_ext_create(struct be_adapter *adapter,
1192                                   struct be_queue_info *mccq,
1193                                   struct be_queue_info *cq)
1194 {
1195         struct be_mcc_wrb *wrb;
1196         struct be_cmd_req_mcc_ext_create *req;
1197         struct be_dma_mem *q_mem = &mccq->dma_mem;
1198         void *ctxt;
1199         int status;
1200
1201         if (mutex_lock_interruptible(&adapter->mbox_lock))
1202                 return -1;
1203
1204         wrb = wrb_from_mbox(adapter);
1205         req = embedded_payload(wrb);
1206         ctxt = &req->context;
1207
1208         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1209                                OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req), wrb,
1210                                NULL);
1211
1212         req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1213         if (BEx_chip(adapter)) {
1214                 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1215                 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
1216                               be_encoded_q_len(mccq->len));
1217                 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1218         } else {
1219                 req->hdr.version = 1;
1220                 req->cq_id = cpu_to_le16(cq->id);
1221
1222                 AMAP_SET_BITS(struct amap_mcc_context_v1, ring_size, ctxt,
1223                               be_encoded_q_len(mccq->len));
1224                 AMAP_SET_BITS(struct amap_mcc_context_v1, valid, ctxt, 1);
1225                 AMAP_SET_BITS(struct amap_mcc_context_v1, async_cq_id,
1226                               ctxt, cq->id);
1227                 AMAP_SET_BITS(struct amap_mcc_context_v1, async_cq_valid,
1228                               ctxt, 1);
1229         }
1230
1231         /* Subscribe to Link State, Sliport Event and Group 5 Events
1232          * (bits 1, 5 and 17 set)
1233          */
1234         req->async_event_bitmap[0] =
1235                         cpu_to_le32(BIT(ASYNC_EVENT_CODE_LINK_STATE) |
1236                                     BIT(ASYNC_EVENT_CODE_GRP_5) |
1237                                     BIT(ASYNC_EVENT_CODE_QNQ) |
1238                                     BIT(ASYNC_EVENT_CODE_SLIPORT));
1239
1240         be_dws_cpu_to_le(ctxt, sizeof(req->context));
1241
1242         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1243
1244         status = be_mbox_notify_wait(adapter);
1245         if (!status) {
1246                 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
1247
1248                 mccq->id = le16_to_cpu(resp->id);
1249                 mccq->created = true;
1250         }
1251         mutex_unlock(&adapter->mbox_lock);
1252
1253         return status;
1254 }
1255
1256 static int be_cmd_mccq_org_create(struct be_adapter *adapter,
1257                                   struct be_queue_info *mccq,
1258                                   struct be_queue_info *cq)
1259 {
1260         struct be_mcc_wrb *wrb;
1261         struct be_cmd_req_mcc_create *req;
1262         struct be_dma_mem *q_mem = &mccq->dma_mem;
1263         void *ctxt;
1264         int status;
1265
1266         if (mutex_lock_interruptible(&adapter->mbox_lock))
1267                 return -1;
1268
1269         wrb = wrb_from_mbox(adapter);
1270         req = embedded_payload(wrb);
1271         ctxt = &req->context;
1272
1273         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1274                                OPCODE_COMMON_MCC_CREATE, sizeof(*req), wrb,
1275                                NULL);
1276
1277         req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
1278
1279         AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
1280         AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
1281                       be_encoded_q_len(mccq->len));
1282         AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
1283
1284         be_dws_cpu_to_le(ctxt, sizeof(req->context));
1285
1286         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1287
1288         status = be_mbox_notify_wait(adapter);
1289         if (!status) {
1290                 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
1291
1292                 mccq->id = le16_to_cpu(resp->id);
1293                 mccq->created = true;
1294         }
1295
1296         mutex_unlock(&adapter->mbox_lock);
1297         return status;
1298 }
1299
1300 int be_cmd_mccq_create(struct be_adapter *adapter,
1301                        struct be_queue_info *mccq, struct be_queue_info *cq)
1302 {
1303         int status;
1304
1305         status = be_cmd_mccq_ext_create(adapter, mccq, cq);
1306         if (status && BEx_chip(adapter)) {
1307                 dev_warn(&adapter->pdev->dev, "Upgrade to F/W ver 2.102.235.0 "
1308                         "or newer to avoid conflicting priorities between NIC "
1309                         "and FCoE traffic");
1310                 status = be_cmd_mccq_org_create(adapter, mccq, cq);
1311         }
1312         return status;
1313 }
1314
1315 int be_cmd_txq_create(struct be_adapter *adapter, struct be_tx_obj *txo)
1316 {
1317         struct be_mcc_wrb wrb = {0};
1318         struct be_cmd_req_eth_tx_create *req;
1319         struct be_queue_info *txq = &txo->q;
1320         struct be_queue_info *cq = &txo->cq;
1321         struct be_dma_mem *q_mem = &txq->dma_mem;
1322         int status, ver = 0;
1323
1324         req = embedded_payload(&wrb);
1325         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1326                                OPCODE_ETH_TX_CREATE, sizeof(*req), &wrb, NULL);
1327
1328         if (lancer_chip(adapter)) {
1329                 req->hdr.version = 1;
1330         } else if (BEx_chip(adapter)) {
1331                 if (adapter->function_caps & BE_FUNCTION_CAPS_SUPER_NIC)
1332                         req->hdr.version = 2;
1333         } else { /* For SH */
1334                 req->hdr.version = 2;
1335         }
1336
1337         if (req->hdr.version > 0)
1338                 req->if_id = cpu_to_le16(adapter->if_handle);
1339         req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
1340         req->ulp_num = BE_ULP1_NUM;
1341         req->type = BE_ETH_TX_RING_TYPE_STANDARD;
1342         req->cq_id = cpu_to_le16(cq->id);
1343         req->queue_size = be_encoded_q_len(txq->len);
1344         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1345         ver = req->hdr.version;
1346
1347         status = be_cmd_notify_wait(adapter, &wrb);
1348         if (!status) {
1349                 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(&wrb);
1350
1351                 txq->id = le16_to_cpu(resp->cid);
1352                 if (ver == 2)
1353                         txo->db_offset = le32_to_cpu(resp->db_offset);
1354                 else
1355                         txo->db_offset = DB_TXULP1_OFFSET;
1356                 txq->created = true;
1357         }
1358
1359         return status;
1360 }
1361
1362 /* Uses MCC */
1363 int be_cmd_rxq_create(struct be_adapter *adapter,
1364                       struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
1365                       u32 if_id, u32 rss, u8 *rss_id)
1366 {
1367         struct be_mcc_wrb *wrb;
1368         struct be_cmd_req_eth_rx_create *req;
1369         struct be_dma_mem *q_mem = &rxq->dma_mem;
1370         int status;
1371
1372         spin_lock_bh(&adapter->mcc_lock);
1373
1374         wrb = wrb_from_mccq(adapter);
1375         if (!wrb) {
1376                 status = -EBUSY;
1377                 goto err;
1378         }
1379         req = embedded_payload(wrb);
1380
1381         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1382                                OPCODE_ETH_RX_CREATE, sizeof(*req), wrb, NULL);
1383
1384         req->cq_id = cpu_to_le16(cq_id);
1385         req->frag_size = fls(frag_size) - 1;
1386         req->num_pages = 2;
1387         be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1388         req->interface_id = cpu_to_le32(if_id);
1389         req->max_frame_size = cpu_to_le16(BE_MAX_JUMBO_FRAME_SIZE);
1390         req->rss_queue = cpu_to_le32(rss);
1391
1392         status = be_mcc_notify_wait(adapter);
1393         if (!status) {
1394                 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
1395
1396                 rxq->id = le16_to_cpu(resp->id);
1397                 rxq->created = true;
1398                 *rss_id = resp->rss_id;
1399         }
1400
1401 err:
1402         spin_unlock_bh(&adapter->mcc_lock);
1403         return status;
1404 }
1405
1406 /* Generic destroyer function for all types of queues
1407  * Uses Mbox
1408  */
1409 int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
1410                      int queue_type)
1411 {
1412         struct be_mcc_wrb *wrb;
1413         struct be_cmd_req_q_destroy *req;
1414         u8 subsys = 0, opcode = 0;
1415         int status;
1416
1417         if (mutex_lock_interruptible(&adapter->mbox_lock))
1418                 return -1;
1419
1420         wrb = wrb_from_mbox(adapter);
1421         req = embedded_payload(wrb);
1422
1423         switch (queue_type) {
1424         case QTYPE_EQ:
1425                 subsys = CMD_SUBSYSTEM_COMMON;
1426                 opcode = OPCODE_COMMON_EQ_DESTROY;
1427                 break;
1428         case QTYPE_CQ:
1429                 subsys = CMD_SUBSYSTEM_COMMON;
1430                 opcode = OPCODE_COMMON_CQ_DESTROY;
1431                 break;
1432         case QTYPE_TXQ:
1433                 subsys = CMD_SUBSYSTEM_ETH;
1434                 opcode = OPCODE_ETH_TX_DESTROY;
1435                 break;
1436         case QTYPE_RXQ:
1437                 subsys = CMD_SUBSYSTEM_ETH;
1438                 opcode = OPCODE_ETH_RX_DESTROY;
1439                 break;
1440         case QTYPE_MCCQ:
1441                 subsys = CMD_SUBSYSTEM_COMMON;
1442                 opcode = OPCODE_COMMON_MCC_DESTROY;
1443                 break;
1444         default:
1445                 BUG();
1446         }
1447
1448         be_wrb_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req), wrb,
1449                                NULL);
1450         req->id = cpu_to_le16(q->id);
1451
1452         status = be_mbox_notify_wait(adapter);
1453         q->created = false;
1454
1455         mutex_unlock(&adapter->mbox_lock);
1456         return status;
1457 }
1458
1459 /* Uses MCC */
1460 int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q)
1461 {
1462         struct be_mcc_wrb *wrb;
1463         struct be_cmd_req_q_destroy *req;
1464         int status;
1465
1466         spin_lock_bh(&adapter->mcc_lock);
1467
1468         wrb = wrb_from_mccq(adapter);
1469         if (!wrb) {
1470                 status = -EBUSY;
1471                 goto err;
1472         }
1473         req = embedded_payload(wrb);
1474
1475         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1476                                OPCODE_ETH_RX_DESTROY, sizeof(*req), wrb, NULL);
1477         req->id = cpu_to_le16(q->id);
1478
1479         status = be_mcc_notify_wait(adapter);
1480         q->created = false;
1481
1482 err:
1483         spin_unlock_bh(&adapter->mcc_lock);
1484         return status;
1485 }
1486
1487 /* Create an rx filtering policy configuration on an i/f
1488  * Will use MBOX only if MCCQ has not been created.
1489  */
1490 int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
1491                      u32 *if_handle, u32 domain)
1492 {
1493         struct be_mcc_wrb wrb = {0};
1494         struct be_cmd_req_if_create *req;
1495         int status;
1496
1497         req = embedded_payload(&wrb);
1498         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1499                                OPCODE_COMMON_NTWK_INTERFACE_CREATE,
1500                                sizeof(*req), &wrb, NULL);
1501         req->hdr.domain = domain;
1502         req->capability_flags = cpu_to_le32(cap_flags);
1503         req->enable_flags = cpu_to_le32(en_flags);
1504         req->pmac_invalid = true;
1505
1506         status = be_cmd_notify_wait(adapter, &wrb);
1507         if (!status) {
1508                 struct be_cmd_resp_if_create *resp = embedded_payload(&wrb);
1509
1510                 *if_handle = le32_to_cpu(resp->interface_id);
1511
1512                 /* Hack to retrieve VF's pmac-id on BE3 */
1513                 if (BE3_chip(adapter) && !be_physfn(adapter))
1514                         adapter->pmac_id[0] = le32_to_cpu(resp->pmac_id);
1515         }
1516         return status;
1517 }
1518
1519 /* Uses MCCQ */
1520 int be_cmd_if_destroy(struct be_adapter *adapter, int interface_id, u32 domain)
1521 {
1522         struct be_mcc_wrb *wrb;
1523         struct be_cmd_req_if_destroy *req;
1524         int status;
1525
1526         if (interface_id == -1)
1527                 return 0;
1528
1529         spin_lock_bh(&adapter->mcc_lock);
1530
1531         wrb = wrb_from_mccq(adapter);
1532         if (!wrb) {
1533                 status = -EBUSY;
1534                 goto err;
1535         }
1536         req = embedded_payload(wrb);
1537
1538         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1539                                OPCODE_COMMON_NTWK_INTERFACE_DESTROY,
1540                                sizeof(*req), wrb, NULL);
1541         req->hdr.domain = domain;
1542         req->interface_id = cpu_to_le32(interface_id);
1543
1544         status = be_mcc_notify_wait(adapter);
1545 err:
1546         spin_unlock_bh(&adapter->mcc_lock);
1547         return status;
1548 }
1549
1550 /* Get stats is a non embedded command: the request is not embedded inside
1551  * WRB but is a separate dma memory block
1552  * Uses asynchronous MCC
1553  */
1554 int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
1555 {
1556         struct be_mcc_wrb *wrb;
1557         struct be_cmd_req_hdr *hdr;
1558         int status = 0;
1559
1560         spin_lock_bh(&adapter->mcc_lock);
1561
1562         wrb = wrb_from_mccq(adapter);
1563         if (!wrb) {
1564                 status = -EBUSY;
1565                 goto err;
1566         }
1567         hdr = nonemb_cmd->va;
1568
1569         be_wrb_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH,
1570                                OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size, wrb,
1571                                nonemb_cmd);
1572
1573         /* version 1 of the cmd is not supported only by BE2 */
1574         if (BE2_chip(adapter))
1575                 hdr->version = 0;
1576         if (BE3_chip(adapter) || lancer_chip(adapter))
1577                 hdr->version = 1;
1578         else
1579                 hdr->version = 2;
1580
1581         be_mcc_notify(adapter);
1582         adapter->stats_cmd_sent = true;
1583
1584 err:
1585         spin_unlock_bh(&adapter->mcc_lock);
1586         return status;
1587 }
1588
1589 /* Lancer Stats */
1590 int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
1591                                struct be_dma_mem *nonemb_cmd)
1592 {
1593         struct be_mcc_wrb *wrb;
1594         struct lancer_cmd_req_pport_stats *req;
1595         int status = 0;
1596
1597         if (!be_cmd_allowed(adapter, OPCODE_ETH_GET_PPORT_STATS,
1598                             CMD_SUBSYSTEM_ETH))
1599                 return -EPERM;
1600
1601         spin_lock_bh(&adapter->mcc_lock);
1602
1603         wrb = wrb_from_mccq(adapter);
1604         if (!wrb) {
1605                 status = -EBUSY;
1606                 goto err;
1607         }
1608         req = nonemb_cmd->va;
1609
1610         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1611                                OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size,
1612                                wrb, nonemb_cmd);
1613
1614         req->cmd_params.params.pport_num = cpu_to_le16(adapter->hba_port_num);
1615         req->cmd_params.params.reset_stats = 0;
1616
1617         be_mcc_notify(adapter);
1618         adapter->stats_cmd_sent = true;
1619
1620 err:
1621         spin_unlock_bh(&adapter->mcc_lock);
1622         return status;
1623 }
1624
1625 static int be_mac_to_link_speed(int mac_speed)
1626 {
1627         switch (mac_speed) {
1628         case PHY_LINK_SPEED_ZERO:
1629                 return 0;
1630         case PHY_LINK_SPEED_10MBPS:
1631                 return 10;
1632         case PHY_LINK_SPEED_100MBPS:
1633                 return 100;
1634         case PHY_LINK_SPEED_1GBPS:
1635                 return 1000;
1636         case PHY_LINK_SPEED_10GBPS:
1637                 return 10000;
1638         case PHY_LINK_SPEED_20GBPS:
1639                 return 20000;
1640         case PHY_LINK_SPEED_25GBPS:
1641                 return 25000;
1642         case PHY_LINK_SPEED_40GBPS:
1643                 return 40000;
1644         }
1645         return 0;
1646 }
1647
1648 /* Uses synchronous mcc
1649  * Returns link_speed in Mbps
1650  */
1651 int be_cmd_link_status_query(struct be_adapter *adapter, u16 *link_speed,
1652                              u8 *link_status, u32 dom)
1653 {
1654         struct be_mcc_wrb *wrb;
1655         struct be_cmd_req_link_status *req;
1656         int status;
1657
1658         spin_lock_bh(&adapter->mcc_lock);
1659
1660         if (link_status)
1661                 *link_status = LINK_DOWN;
1662
1663         wrb = wrb_from_mccq(adapter);
1664         if (!wrb) {
1665                 status = -EBUSY;
1666                 goto err;
1667         }
1668         req = embedded_payload(wrb);
1669
1670         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1671                                OPCODE_COMMON_NTWK_LINK_STATUS_QUERY,
1672                                sizeof(*req), wrb, NULL);
1673
1674         /* version 1 of the cmd is not supported only by BE2 */
1675         if (!BE2_chip(adapter))
1676                 req->hdr.version = 1;
1677
1678         req->hdr.domain = dom;
1679
1680         status = be_mcc_notify_wait(adapter);
1681         if (!status) {
1682                 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
1683
1684                 if (link_speed) {
1685                         *link_speed = resp->link_speed ?
1686                                       le16_to_cpu(resp->link_speed) * 10 :
1687                                       be_mac_to_link_speed(resp->mac_speed);
1688
1689                         if (!resp->logical_link_status)
1690                                 *link_speed = 0;
1691                 }
1692                 if (link_status)
1693                         *link_status = resp->logical_link_status;
1694         }
1695
1696 err:
1697         spin_unlock_bh(&adapter->mcc_lock);
1698         return status;
1699 }
1700
1701 /* Uses synchronous mcc */
1702 int be_cmd_get_die_temperature(struct be_adapter *adapter)
1703 {
1704         struct be_mcc_wrb *wrb;
1705         struct be_cmd_req_get_cntl_addnl_attribs *req;
1706         int status = 0;
1707
1708         spin_lock_bh(&adapter->mcc_lock);
1709
1710         wrb = wrb_from_mccq(adapter);
1711         if (!wrb) {
1712                 status = -EBUSY;
1713                 goto err;
1714         }
1715         req = embedded_payload(wrb);
1716
1717         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1718                                OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES,
1719                                sizeof(*req), wrb, NULL);
1720
1721         be_mcc_notify(adapter);
1722
1723 err:
1724         spin_unlock_bh(&adapter->mcc_lock);
1725         return status;
1726 }
1727
1728 /* Uses synchronous mcc */
1729 int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size)
1730 {
1731         struct be_mcc_wrb *wrb;
1732         struct be_cmd_req_get_fat *req;
1733         int status;
1734
1735         spin_lock_bh(&adapter->mcc_lock);
1736
1737         wrb = wrb_from_mccq(adapter);
1738         if (!wrb) {
1739                 status = -EBUSY;
1740                 goto err;
1741         }
1742         req = embedded_payload(wrb);
1743
1744         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1745                                OPCODE_COMMON_MANAGE_FAT, sizeof(*req), wrb,
1746                                NULL);
1747         req->fat_operation = cpu_to_le32(QUERY_FAT);
1748         status = be_mcc_notify_wait(adapter);
1749         if (!status) {
1750                 struct be_cmd_resp_get_fat *resp = embedded_payload(wrb);
1751
1752                 if (log_size && resp->log_size)
1753                         *log_size = le32_to_cpu(resp->log_size) -
1754                                         sizeof(u32);
1755         }
1756 err:
1757         spin_unlock_bh(&adapter->mcc_lock);
1758         return status;
1759 }
1760
1761 int be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf)
1762 {
1763         struct be_dma_mem get_fat_cmd;
1764         struct be_mcc_wrb *wrb;
1765         struct be_cmd_req_get_fat *req;
1766         u32 offset = 0, total_size, buf_size,
1767                                 log_offset = sizeof(u32), payload_len;
1768         int status = 0;
1769
1770         if (buf_len == 0)
1771                 return -EIO;
1772
1773         total_size = buf_len;
1774
1775         get_fat_cmd.size = sizeof(struct be_cmd_req_get_fat) + 60*1024;
1776         get_fat_cmd.va = pci_alloc_consistent(adapter->pdev,
1777                                               get_fat_cmd.size,
1778                                               &get_fat_cmd.dma);
1779         if (!get_fat_cmd.va) {
1780                 dev_err(&adapter->pdev->dev,
1781                         "Memory allocation failure while reading FAT data\n");
1782                 return -ENOMEM;
1783         }
1784
1785         spin_lock_bh(&adapter->mcc_lock);
1786
1787         while (total_size) {
1788                 buf_size = min(total_size, (u32)60*1024);
1789                 total_size -= buf_size;
1790
1791                 wrb = wrb_from_mccq(adapter);
1792                 if (!wrb) {
1793                         status = -EBUSY;
1794                         goto err;
1795                 }
1796                 req = get_fat_cmd.va;
1797
1798                 payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size;
1799                 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1800                                        OPCODE_COMMON_MANAGE_FAT, payload_len,
1801                                        wrb, &get_fat_cmd);
1802
1803                 req->fat_operation = cpu_to_le32(RETRIEVE_FAT);
1804                 req->read_log_offset = cpu_to_le32(log_offset);
1805                 req->read_log_length = cpu_to_le32(buf_size);
1806                 req->data_buffer_size = cpu_to_le32(buf_size);
1807
1808                 status = be_mcc_notify_wait(adapter);
1809                 if (!status) {
1810                         struct be_cmd_resp_get_fat *resp = get_fat_cmd.va;
1811
1812                         memcpy(buf + offset,
1813                                resp->data_buffer,
1814                                le32_to_cpu(resp->read_log_length));
1815                 } else {
1816                         dev_err(&adapter->pdev->dev, "FAT Table Retrieve error\n");
1817                         goto err;
1818                 }
1819                 offset += buf_size;
1820                 log_offset += buf_size;
1821         }
1822 err:
1823         pci_free_consistent(adapter->pdev, get_fat_cmd.size,
1824                             get_fat_cmd.va, get_fat_cmd.dma);
1825         spin_unlock_bh(&adapter->mcc_lock);
1826         return status;
1827 }
1828
1829 /* Uses synchronous mcc */
1830 int be_cmd_get_fw_ver(struct be_adapter *adapter)
1831 {
1832         struct be_mcc_wrb *wrb;
1833         struct be_cmd_req_get_fw_version *req;
1834         int status;
1835
1836         spin_lock_bh(&adapter->mcc_lock);
1837
1838         wrb = wrb_from_mccq(adapter);
1839         if (!wrb) {
1840                 status = -EBUSY;
1841                 goto err;
1842         }
1843
1844         req = embedded_payload(wrb);
1845
1846         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1847                                OPCODE_COMMON_GET_FW_VERSION, sizeof(*req), wrb,
1848                                NULL);
1849         status = be_mcc_notify_wait(adapter);
1850         if (!status) {
1851                 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
1852
1853                 strlcpy(adapter->fw_ver, resp->firmware_version_string,
1854                         sizeof(adapter->fw_ver));
1855                 strlcpy(adapter->fw_on_flash, resp->fw_on_flash_version_string,
1856                         sizeof(adapter->fw_on_flash));
1857         }
1858 err:
1859         spin_unlock_bh(&adapter->mcc_lock);
1860         return status;
1861 }
1862
1863 /* set the EQ delay interval of an EQ to specified value
1864  * Uses async mcc
1865  */
1866 static int __be_cmd_modify_eqd(struct be_adapter *adapter,
1867                                struct be_set_eqd *set_eqd, int num)
1868 {
1869         struct be_mcc_wrb *wrb;
1870         struct be_cmd_req_modify_eq_delay *req;
1871         int status = 0, i;
1872
1873         spin_lock_bh(&adapter->mcc_lock);
1874
1875         wrb = wrb_from_mccq(adapter);
1876         if (!wrb) {
1877                 status = -EBUSY;
1878                 goto err;
1879         }
1880         req = embedded_payload(wrb);
1881
1882         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1883                                OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req), wrb,
1884                                NULL);
1885
1886         req->num_eq = cpu_to_le32(num);
1887         for (i = 0; i < num; i++) {
1888                 req->set_eqd[i].eq_id = cpu_to_le32(set_eqd[i].eq_id);
1889                 req->set_eqd[i].phase = 0;
1890                 req->set_eqd[i].delay_multiplier =
1891                                 cpu_to_le32(set_eqd[i].delay_multiplier);
1892         }
1893
1894         be_mcc_notify(adapter);
1895 err:
1896         spin_unlock_bh(&adapter->mcc_lock);
1897         return status;
1898 }
1899
1900 int be_cmd_modify_eqd(struct be_adapter *adapter, struct be_set_eqd *set_eqd,
1901                       int num)
1902 {
1903         int num_eqs, i = 0;
1904
1905         if (lancer_chip(adapter) && num > 8) {
1906                 while (num) {
1907                         num_eqs = min(num, 8);
1908                         __be_cmd_modify_eqd(adapter, &set_eqd[i], num_eqs);
1909                         i += num_eqs;
1910                         num -= num_eqs;
1911                 }
1912         } else {
1913                 __be_cmd_modify_eqd(adapter, set_eqd, num);
1914         }
1915
1916         return 0;
1917 }
1918
1919 /* Uses sycnhronous mcc */
1920 int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
1921                        u32 num, u32 domain)
1922 {
1923         struct be_mcc_wrb *wrb;
1924         struct be_cmd_req_vlan_config *req;
1925         int status;
1926
1927         spin_lock_bh(&adapter->mcc_lock);
1928
1929         wrb = wrb_from_mccq(adapter);
1930         if (!wrb) {
1931                 status = -EBUSY;
1932                 goto err;
1933         }
1934         req = embedded_payload(wrb);
1935
1936         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1937                                OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req),
1938                                wrb, NULL);
1939         req->hdr.domain = domain;
1940
1941         req->interface_id = if_id;
1942         req->untagged = BE_IF_FLAGS_UNTAGGED & be_if_cap_flags(adapter) ? 1 : 0;
1943         req->num_vlan = num;
1944         memcpy(req->normal_vlan, vtag_array,
1945                req->num_vlan * sizeof(vtag_array[0]));
1946
1947         status = be_mcc_notify_wait(adapter);
1948 err:
1949         spin_unlock_bh(&adapter->mcc_lock);
1950         return status;
1951 }
1952
1953 static int __be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
1954 {
1955         struct be_mcc_wrb *wrb;
1956         struct be_dma_mem *mem = &adapter->rx_filter;
1957         struct be_cmd_req_rx_filter *req = mem->va;
1958         int status;
1959
1960         spin_lock_bh(&adapter->mcc_lock);
1961
1962         wrb = wrb_from_mccq(adapter);
1963         if (!wrb) {
1964                 status = -EBUSY;
1965                 goto err;
1966         }
1967         memset(req, 0, sizeof(*req));
1968         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1969                                OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req),
1970                                wrb, mem);
1971
1972         req->if_id = cpu_to_le32(adapter->if_handle);
1973         req->if_flags_mask = cpu_to_le32(flags);
1974         req->if_flags = (value == ON) ? req->if_flags_mask : 0;
1975
1976         if (flags & BE_IF_FLAGS_MULTICAST) {
1977                 struct netdev_hw_addr *ha;
1978                 int i = 0;
1979
1980                 /* Reset mcast promisc mode if already set by setting mask
1981                  * and not setting flags field
1982                  */
1983                 req->if_flags_mask |=
1984                         cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS &
1985                                     be_if_cap_flags(adapter));
1986                 req->mcast_num = cpu_to_le32(netdev_mc_count(adapter->netdev));
1987                 netdev_for_each_mc_addr(ha, adapter->netdev)
1988                         memcpy(req->mcast_mac[i++].byte, ha->addr, ETH_ALEN);
1989         }
1990
1991         status = be_mcc_notify_wait(adapter);
1992 err:
1993         spin_unlock_bh(&adapter->mcc_lock);
1994         return status;
1995 }
1996
1997 int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
1998 {
1999         struct device *dev = &adapter->pdev->dev;
2000
2001         if ((flags & be_if_cap_flags(adapter)) != flags) {
2002                 dev_warn(dev, "Cannot set rx filter flags 0x%x\n", flags);
2003                 dev_warn(dev, "Interface is capable of 0x%x flags only\n",
2004                          be_if_cap_flags(adapter));
2005         }
2006         flags &= be_if_cap_flags(adapter);
2007
2008         return __be_cmd_rx_filter(adapter, flags, value);
2009 }
2010
2011 /* Uses synchrounous mcc */
2012 int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
2013 {
2014         struct be_mcc_wrb *wrb;
2015         struct be_cmd_req_set_flow_control *req;
2016         int status;
2017
2018         if (!be_cmd_allowed(adapter, OPCODE_COMMON_SET_FLOW_CONTROL,
2019                             CMD_SUBSYSTEM_COMMON))
2020                 return -EPERM;
2021
2022         spin_lock_bh(&adapter->mcc_lock);
2023
2024         wrb = wrb_from_mccq(adapter);
2025         if (!wrb) {
2026                 status = -EBUSY;
2027                 goto err;
2028         }
2029         req = embedded_payload(wrb);
2030
2031         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2032                                OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req),
2033                                wrb, NULL);
2034
2035         req->hdr.version = 1;
2036         req->tx_flow_control = cpu_to_le16((u16)tx_fc);
2037         req->rx_flow_control = cpu_to_le16((u16)rx_fc);
2038
2039         status = be_mcc_notify_wait(adapter);
2040
2041 err:
2042         spin_unlock_bh(&adapter->mcc_lock);
2043
2044         if (base_status(status) == MCC_STATUS_FEATURE_NOT_SUPPORTED)
2045                 return  -EOPNOTSUPP;
2046
2047         return status;
2048 }
2049
2050 /* Uses sycn mcc */
2051 int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
2052 {
2053         struct be_mcc_wrb *wrb;
2054         struct be_cmd_req_get_flow_control *req;
2055         int status;
2056
2057         if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_FLOW_CONTROL,
2058                             CMD_SUBSYSTEM_COMMON))
2059                 return -EPERM;
2060
2061         spin_lock_bh(&adapter->mcc_lock);
2062
2063         wrb = wrb_from_mccq(adapter);
2064         if (!wrb) {
2065                 status = -EBUSY;
2066                 goto err;
2067         }
2068         req = embedded_payload(wrb);
2069
2070         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2071                                OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req),
2072                                wrb, NULL);
2073
2074         status = be_mcc_notify_wait(adapter);
2075         if (!status) {
2076                 struct be_cmd_resp_get_flow_control *resp =
2077                                                 embedded_payload(wrb);
2078
2079                 *tx_fc = le16_to_cpu(resp->tx_flow_control);
2080                 *rx_fc = le16_to_cpu(resp->rx_flow_control);
2081         }
2082
2083 err:
2084         spin_unlock_bh(&adapter->mcc_lock);
2085         return status;
2086 }
2087
2088 /* Uses mbox */
2089 int be_cmd_query_fw_cfg(struct be_adapter *adapter)
2090 {
2091         struct be_mcc_wrb *wrb;
2092         struct be_cmd_req_query_fw_cfg *req;
2093         int status;
2094
2095         if (mutex_lock_interruptible(&adapter->mbox_lock))
2096                 return -1;
2097
2098         wrb = wrb_from_mbox(adapter);
2099         req = embedded_payload(wrb);
2100
2101         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2102                                OPCODE_COMMON_QUERY_FIRMWARE_CONFIG,
2103                                sizeof(*req), wrb, NULL);
2104
2105         status = be_mbox_notify_wait(adapter);
2106         if (!status) {
2107                 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
2108
2109                 adapter->port_num = le32_to_cpu(resp->phys_port);
2110                 adapter->function_mode = le32_to_cpu(resp->function_mode);
2111                 adapter->function_caps = le32_to_cpu(resp->function_caps);
2112                 adapter->asic_rev = le32_to_cpu(resp->asic_revision) & 0xFF;
2113                 dev_info(&adapter->pdev->dev,
2114                          "FW config: function_mode=0x%x, function_caps=0x%x\n",
2115                          adapter->function_mode, adapter->function_caps);
2116         }
2117
2118         mutex_unlock(&adapter->mbox_lock);
2119         return status;
2120 }
2121
2122 /* Uses mbox */
2123 int be_cmd_reset_function(struct be_adapter *adapter)
2124 {
2125         struct be_mcc_wrb *wrb;
2126         struct be_cmd_req_hdr *req;
2127         int status;
2128
2129         if (lancer_chip(adapter)) {
2130                 status = lancer_wait_ready(adapter);
2131                 if (!status) {
2132                         iowrite32(SLI_PORT_CONTROL_IP_MASK,
2133                                   adapter->db + SLIPORT_CONTROL_OFFSET);
2134                         status = lancer_test_and_set_rdy_state(adapter);
2135                 }
2136                 if (status) {
2137                         dev_err(&adapter->pdev->dev,
2138                                 "Adapter in non recoverable error\n");
2139                 }
2140                 return status;
2141         }
2142
2143         if (mutex_lock_interruptible(&adapter->mbox_lock))
2144                 return -1;
2145
2146         wrb = wrb_from_mbox(adapter);
2147         req = embedded_payload(wrb);
2148
2149         be_wrb_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
2150                                OPCODE_COMMON_FUNCTION_RESET, sizeof(*req), wrb,
2151                                NULL);
2152
2153         status = be_mbox_notify_wait(adapter);
2154
2155         mutex_unlock(&adapter->mbox_lock);
2156         return status;
2157 }
2158
2159 int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable,
2160                       u32 rss_hash_opts, u16 table_size, const u8 *rss_hkey)
2161 {
2162         struct be_mcc_wrb *wrb;
2163         struct be_cmd_req_rss_config *req;
2164         int status;
2165
2166         if (!(be_if_cap_flags(adapter) & BE_IF_FLAGS_RSS))
2167                 return 0;
2168
2169         spin_lock_bh(&adapter->mcc_lock);
2170
2171         wrb = wrb_from_mccq(adapter);
2172         if (!wrb) {
2173                 status = -EBUSY;
2174                 goto err;
2175         }
2176         req = embedded_payload(wrb);
2177
2178         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
2179                                OPCODE_ETH_RSS_CONFIG, sizeof(*req), wrb, NULL);
2180
2181         req->if_id = cpu_to_le32(adapter->if_handle);
2182         req->enable_rss = cpu_to_le16(rss_hash_opts);
2183         req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1);
2184
2185         if (!BEx_chip(adapter))
2186                 req->hdr.version = 1;
2187
2188         memcpy(req->cpu_table, rsstable, table_size);
2189         memcpy(req->hash, rss_hkey, RSS_HASH_KEY_LEN);
2190         be_dws_cpu_to_le(req->hash, sizeof(req->hash));
2191
2192         status = be_mcc_notify_wait(adapter);
2193 err:
2194         spin_unlock_bh(&adapter->mcc_lock);
2195         return status;
2196 }
2197
2198 /* Uses sync mcc */
2199 int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
2200                             u8 bcn, u8 sts, u8 state)
2201 {
2202         struct be_mcc_wrb *wrb;
2203         struct be_cmd_req_enable_disable_beacon *req;
2204         int status;
2205
2206         spin_lock_bh(&adapter->mcc_lock);
2207
2208         wrb = wrb_from_mccq(adapter);
2209         if (!wrb) {
2210                 status = -EBUSY;
2211                 goto err;
2212         }
2213         req = embedded_payload(wrb);
2214
2215         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2216                                OPCODE_COMMON_ENABLE_DISABLE_BEACON,
2217                                sizeof(*req), wrb, NULL);
2218
2219         req->port_num = port_num;
2220         req->beacon_state = state;
2221         req->beacon_duration = bcn;
2222         req->status_duration = sts;
2223
2224         status = be_mcc_notify_wait(adapter);
2225
2226 err:
2227         spin_unlock_bh(&adapter->mcc_lock);
2228         return status;
2229 }
2230
2231 /* Uses sync mcc */
2232 int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
2233 {
2234         struct be_mcc_wrb *wrb;
2235         struct be_cmd_req_get_beacon_state *req;
2236         int status;
2237
2238         spin_lock_bh(&adapter->mcc_lock);
2239
2240         wrb = wrb_from_mccq(adapter);
2241         if (!wrb) {
2242                 status = -EBUSY;
2243                 goto err;
2244         }
2245         req = embedded_payload(wrb);
2246
2247         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2248                                OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req),
2249                                wrb, NULL);
2250
2251         req->port_num = port_num;
2252
2253         status = be_mcc_notify_wait(adapter);
2254         if (!status) {
2255                 struct be_cmd_resp_get_beacon_state *resp =
2256                                                 embedded_payload(wrb);
2257
2258                 *state = resp->beacon_state;
2259         }
2260
2261 err:
2262         spin_unlock_bh(&adapter->mcc_lock);
2263         return status;
2264 }
2265
2266 /* Uses sync mcc */
2267 int be_cmd_read_port_transceiver_data(struct be_adapter *adapter,
2268                                       u8 page_num, u8 *data)
2269 {
2270         struct be_dma_mem cmd;
2271         struct be_mcc_wrb *wrb;
2272         struct be_cmd_req_port_type *req;
2273         int status;
2274
2275         if (page_num > TR_PAGE_A2)
2276                 return -EINVAL;
2277
2278         cmd.size = sizeof(struct be_cmd_resp_port_type);
2279         cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma);
2280         if (!cmd.va) {
2281                 dev_err(&adapter->pdev->dev, "Memory allocation failed\n");
2282                 return -ENOMEM;
2283         }
2284         memset(cmd.va, 0, cmd.size);
2285
2286         spin_lock_bh(&adapter->mcc_lock);
2287
2288         wrb = wrb_from_mccq(adapter);
2289         if (!wrb) {
2290                 status = -EBUSY;
2291                 goto err;
2292         }
2293         req = cmd.va;
2294
2295         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2296                                OPCODE_COMMON_READ_TRANSRECV_DATA,
2297                                cmd.size, wrb, &cmd);
2298
2299         req->port = cpu_to_le32(adapter->hba_port_num);
2300         req->page_num = cpu_to_le32(page_num);
2301         status = be_mcc_notify_wait(adapter);
2302         if (!status) {
2303                 struct be_cmd_resp_port_type *resp = cmd.va;
2304
2305                 memcpy(data, resp->page_data, PAGE_DATA_LEN);
2306         }
2307 err:
2308         spin_unlock_bh(&adapter->mcc_lock);
2309         pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
2310         return status;
2311 }
2312
2313 int lancer_cmd_write_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
2314                             u32 data_size, u32 data_offset,
2315                             const char *obj_name, u32 *data_written,
2316                             u8 *change_status, u8 *addn_status)
2317 {
2318         struct be_mcc_wrb *wrb;
2319         struct lancer_cmd_req_write_object *req;
2320         struct lancer_cmd_resp_write_object *resp;
2321         void *ctxt = NULL;
2322         int status;
2323
2324         spin_lock_bh(&adapter->mcc_lock);
2325         adapter->flash_status = 0;
2326
2327         wrb = wrb_from_mccq(adapter);
2328         if (!wrb) {
2329                 status = -EBUSY;
2330                 goto err_unlock;
2331         }
2332
2333         req = embedded_payload(wrb);
2334
2335         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2336                                OPCODE_COMMON_WRITE_OBJECT,
2337                                sizeof(struct lancer_cmd_req_write_object), wrb,
2338                                NULL);
2339
2340         ctxt = &req->context;
2341         AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2342                       write_length, ctxt, data_size);
2343
2344         if (data_size == 0)
2345                 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2346                               eof, ctxt, 1);
2347         else
2348                 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
2349                               eof, ctxt, 0);
2350
2351         be_dws_cpu_to_le(ctxt, sizeof(req->context));
2352         req->write_offset = cpu_to_le32(data_offset);
2353         strlcpy(req->object_name, obj_name, sizeof(req->object_name));
2354         req->descriptor_count = cpu_to_le32(1);
2355         req->buf_len = cpu_to_le32(data_size);
2356         req->addr_low = cpu_to_le32((cmd->dma +
2357                                      sizeof(struct lancer_cmd_req_write_object))
2358                                     & 0xFFFFFFFF);
2359         req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma +
2360                                 sizeof(struct lancer_cmd_req_write_object)));
2361
2362         be_mcc_notify(adapter);
2363         spin_unlock_bh(&adapter->mcc_lock);
2364
2365         if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
2366                                          msecs_to_jiffies(60000)))
2367                 status = -ETIMEDOUT;
2368         else
2369                 status = adapter->flash_status;
2370
2371         resp = embedded_payload(wrb);
2372         if (!status) {
2373                 *data_written = le32_to_cpu(resp->actual_write_len);
2374                 *change_status = resp->change_status;
2375         } else {
2376                 *addn_status = resp->additional_status;
2377         }
2378
2379         return status;
2380
2381 err_unlock:
2382         spin_unlock_bh(&adapter->mcc_lock);
2383         return status;
2384 }
2385
2386 int be_cmd_query_cable_type(struct be_adapter *adapter)
2387 {
2388         u8 page_data[PAGE_DATA_LEN];
2389         int status;
2390
2391         status = be_cmd_read_port_transceiver_data(adapter, TR_PAGE_A0,
2392                                                    page_data);
2393         if (!status) {
2394                 switch (adapter->phy.interface_type) {
2395                 case PHY_TYPE_QSFP:
2396                         adapter->phy.cable_type =
2397                                 page_data[QSFP_PLUS_CABLE_TYPE_OFFSET];
2398                         break;
2399                 case PHY_TYPE_SFP_PLUS_10GB:
2400                         adapter->phy.cable_type =
2401                                 page_data[SFP_PLUS_CABLE_TYPE_OFFSET];
2402                         break;
2403                 default:
2404                         adapter->phy.cable_type = 0;
2405                         break;
2406                 }
2407         }
2408         return status;
2409 }
2410
2411 int be_cmd_query_sfp_info(struct be_adapter *adapter)
2412 {
2413         u8 page_data[PAGE_DATA_LEN];
2414         int status;
2415
2416         status = be_cmd_read_port_transceiver_data(adapter, TR_PAGE_A0,
2417                                                    page_data);
2418         if (!status) {
2419                 strlcpy(adapter->phy.vendor_name, page_data +
2420                         SFP_VENDOR_NAME_OFFSET, SFP_VENDOR_NAME_LEN - 1);
2421                 strlcpy(adapter->phy.vendor_pn,
2422                         page_data + SFP_VENDOR_PN_OFFSET,
2423                         SFP_VENDOR_NAME_LEN - 1);
2424         }
2425
2426         return status;
2427 }
2428
2429 int lancer_cmd_delete_object(struct be_adapter *adapter, const char *obj_name)
2430 {
2431         struct lancer_cmd_req_delete_object *req;
2432         struct be_mcc_wrb *wrb;
2433         int status;
2434
2435         spin_lock_bh(&adapter->mcc_lock);
2436
2437         wrb = wrb_from_mccq(adapter);
2438         if (!wrb) {
2439                 status = -EBUSY;
2440                 goto err;
2441         }
2442
2443         req = embedded_payload(wrb);
2444
2445         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2446                                OPCODE_COMMON_DELETE_OBJECT,
2447                                sizeof(*req), wrb, NULL);
2448
2449         strlcpy(req->object_name, obj_name, sizeof(req->object_name));
2450
2451         status = be_mcc_notify_wait(adapter);
2452 err:
2453         spin_unlock_bh(&adapter->mcc_lock);
2454         return status;
2455 }
2456
2457 int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
2458                            u32 data_size, u32 data_offset, const char *obj_name,
2459                            u32 *data_read, u32 *eof, u8 *addn_status)
2460 {
2461         struct be_mcc_wrb *wrb;
2462         struct lancer_cmd_req_read_object *req;
2463         struct lancer_cmd_resp_read_object *resp;
2464         int status;
2465
2466         spin_lock_bh(&adapter->mcc_lock);
2467
2468         wrb = wrb_from_mccq(adapter);
2469         if (!wrb) {
2470                 status = -EBUSY;
2471                 goto err_unlock;
2472         }
2473
2474         req = embedded_payload(wrb);
2475
2476         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2477                                OPCODE_COMMON_READ_OBJECT,
2478                                sizeof(struct lancer_cmd_req_read_object), wrb,
2479                                NULL);
2480
2481         req->desired_read_len = cpu_to_le32(data_size);
2482         req->read_offset = cpu_to_le32(data_offset);
2483         strcpy(req->object_name, obj_name);
2484         req->descriptor_count = cpu_to_le32(1);
2485         req->buf_len = cpu_to_le32(data_size);
2486         req->addr_low = cpu_to_le32((cmd->dma & 0xFFFFFFFF));
2487         req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma));
2488
2489         status = be_mcc_notify_wait(adapter);
2490
2491         resp = embedded_payload(wrb);
2492         if (!status) {
2493                 *data_read = le32_to_cpu(resp->actual_read_len);
2494                 *eof = le32_to_cpu(resp->eof);
2495         } else {
2496                 *addn_status = resp->additional_status;
2497         }
2498
2499 err_unlock:
2500         spin_unlock_bh(&adapter->mcc_lock);
2501         return status;
2502 }
2503
2504 int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
2505                           u32 flash_type, u32 flash_opcode, u32 img_offset,
2506                           u32 buf_size)
2507 {
2508         struct be_mcc_wrb *wrb;
2509         struct be_cmd_write_flashrom *req;
2510         int status;
2511
2512         spin_lock_bh(&adapter->mcc_lock);
2513         adapter->flash_status = 0;
2514
2515         wrb = wrb_from_mccq(adapter);
2516         if (!wrb) {
2517                 status = -EBUSY;
2518                 goto err_unlock;
2519         }
2520         req = cmd->va;
2521
2522         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2523                                OPCODE_COMMON_WRITE_FLASHROM, cmd->size, wrb,
2524                                cmd);
2525
2526         req->params.op_type = cpu_to_le32(flash_type);
2527         if (flash_type == OPTYPE_OFFSET_SPECIFIED)
2528                 req->params.offset = cpu_to_le32(img_offset);
2529
2530         req->params.op_code = cpu_to_le32(flash_opcode);
2531         req->params.data_buf_size = cpu_to_le32(buf_size);
2532
2533         be_mcc_notify(adapter);
2534         spin_unlock_bh(&adapter->mcc_lock);
2535
2536         if (!wait_for_completion_timeout(&adapter->et_cmd_compl,
2537                                          msecs_to_jiffies(40000)))
2538                 status = -ETIMEDOUT;
2539         else
2540                 status = adapter->flash_status;
2541
2542         return status;
2543
2544 err_unlock:
2545         spin_unlock_bh(&adapter->mcc_lock);
2546         return status;
2547 }
2548
2549 int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
2550                          u16 img_optype, u32 img_offset, u32 crc_offset)
2551 {
2552         struct be_cmd_read_flash_crc *req;
2553         struct be_mcc_wrb *wrb;
2554         int status;
2555
2556         spin_lock_bh(&adapter->mcc_lock);
2557
2558         wrb = wrb_from_mccq(adapter);
2559         if (!wrb) {
2560                 status = -EBUSY;
2561                 goto err;
2562         }
2563         req = embedded_payload(wrb);
2564
2565         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2566                                OPCODE_COMMON_READ_FLASHROM, sizeof(*req),
2567                                wrb, NULL);
2568
2569         req->params.op_type = cpu_to_le32(img_optype);
2570         if (img_optype == OPTYPE_OFFSET_SPECIFIED)
2571                 req->params.offset = cpu_to_le32(img_offset + crc_offset);
2572         else
2573                 req->params.offset = cpu_to_le32(crc_offset);
2574
2575         req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
2576         req->params.data_buf_size = cpu_to_le32(0x4);
2577
2578         status = be_mcc_notify_wait(adapter);
2579         if (!status)
2580                 memcpy(flashed_crc, req->crc, 4);
2581
2582 err:
2583         spin_unlock_bh(&adapter->mcc_lock);
2584         return status;
2585 }
2586
2587 int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
2588                             struct be_dma_mem *nonemb_cmd)
2589 {
2590         struct be_mcc_wrb *wrb;
2591         struct be_cmd_req_acpi_wol_magic_config *req;
2592         int status;
2593
2594         spin_lock_bh(&adapter->mcc_lock);
2595
2596         wrb = wrb_from_mccq(adapter);
2597         if (!wrb) {
2598                 status = -EBUSY;
2599                 goto err;
2600         }
2601         req = nonemb_cmd->va;
2602
2603         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
2604                                OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req),
2605                                wrb, nonemb_cmd);
2606         memcpy(req->magic_mac, mac, ETH_ALEN);
2607
2608         status = be_mcc_notify_wait(adapter);
2609
2610 err:
2611         spin_unlock_bh(&adapter->mcc_lock);
2612         return status;
2613 }
2614
2615 int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
2616                         u8 loopback_type, u8 enable)
2617 {
2618         struct be_mcc_wrb *wrb;
2619         struct be_cmd_req_set_lmode *req;
2620         int status;
2621
2622         spin_lock_bh(&adapter->mcc_lock);
2623
2624         wrb = wrb_from_mccq(adapter);
2625         if (!wrb) {
2626                 status = -EBUSY;
2627                 goto err;
2628         }
2629
2630         req = embedded_payload(wrb);
2631
2632         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2633                                OPCODE_LOWLEVEL_SET_LOOPBACK_MODE, sizeof(*req),
2634                                wrb, NULL);
2635
2636         req->src_port = port_num;
2637         req->dest_port = port_num;
2638         req->loopback_type = loopback_type;
2639         req->loopback_state = enable;
2640
2641         status = be_mcc_notify_wait(adapter);
2642 err:
2643         spin_unlock_bh(&adapter->mcc_lock);
2644         return status;
2645 }
2646
2647 int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
2648                          u32 loopback_type, u32 pkt_size, u32 num_pkts,
2649                          u64 pattern)
2650 {
2651         struct be_mcc_wrb *wrb;
2652         struct be_cmd_req_loopback_test *req;
2653         struct be_cmd_resp_loopback_test *resp;
2654         int status;
2655
2656         spin_lock_bh(&adapter->mcc_lock);
2657
2658         wrb = wrb_from_mccq(adapter);
2659         if (!wrb) {
2660                 status = -EBUSY;
2661                 goto err;
2662         }
2663
2664         req = embedded_payload(wrb);
2665
2666         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2667                                OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req), wrb,
2668                                NULL);
2669
2670         req->hdr.timeout = cpu_to_le32(15);
2671         req->pattern = cpu_to_le64(pattern);
2672         req->src_port = cpu_to_le32(port_num);
2673         req->dest_port = cpu_to_le32(port_num);
2674         req->pkt_size = cpu_to_le32(pkt_size);
2675         req->num_pkts = cpu_to_le32(num_pkts);
2676         req->loopback_type = cpu_to_le32(loopback_type);
2677
2678         be_mcc_notify(adapter);
2679
2680         spin_unlock_bh(&adapter->mcc_lock);
2681
2682         wait_for_completion(&adapter->et_cmd_compl);
2683         resp = embedded_payload(wrb);
2684         status = le32_to_cpu(resp->status);
2685
2686         return status;
2687 err:
2688         spin_unlock_bh(&adapter->mcc_lock);
2689         return status;
2690 }
2691
2692 int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
2693                         u32 byte_cnt, struct be_dma_mem *cmd)
2694 {
2695         struct be_mcc_wrb *wrb;
2696         struct be_cmd_req_ddrdma_test *req;
2697         int status;
2698         int i, j = 0;
2699
2700         spin_lock_bh(&adapter->mcc_lock);
2701
2702         wrb = wrb_from_mccq(adapter);
2703         if (!wrb) {
2704                 status = -EBUSY;
2705                 goto err;
2706         }
2707         req = cmd->va;
2708         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2709                                OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size, wrb,
2710                                cmd);
2711
2712         req->pattern = cpu_to_le64(pattern);
2713         req->byte_count = cpu_to_le32(byte_cnt);
2714         for (i = 0; i < byte_cnt; i++) {
2715                 req->snd_buff[i] = (u8)(pattern >> (j*8));
2716                 j++;
2717                 if (j > 7)
2718                         j = 0;
2719         }
2720
2721         status = be_mcc_notify_wait(adapter);
2722
2723         if (!status) {
2724                 struct be_cmd_resp_ddrdma_test *resp;
2725
2726                 resp = cmd->va;
2727                 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
2728                     resp->snd_err) {
2729                         status = -1;
2730                 }
2731         }
2732
2733 err:
2734         spin_unlock_bh(&adapter->mcc_lock);
2735         return status;
2736 }
2737
2738 int be_cmd_get_seeprom_data(struct be_adapter *adapter,
2739                             struct be_dma_mem *nonemb_cmd)
2740 {
2741         struct be_mcc_wrb *wrb;
2742         struct be_cmd_req_seeprom_read *req;
2743         int status;
2744
2745         spin_lock_bh(&adapter->mcc_lock);
2746
2747         wrb = wrb_from_mccq(adapter);
2748         if (!wrb) {
2749                 status = -EBUSY;
2750                 goto err;
2751         }
2752         req = nonemb_cmd->va;
2753
2754         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2755                                OPCODE_COMMON_SEEPROM_READ, sizeof(*req), wrb,
2756                                nonemb_cmd);
2757
2758         status = be_mcc_notify_wait(adapter);
2759
2760 err:
2761         spin_unlock_bh(&adapter->mcc_lock);
2762         return status;
2763 }
2764
2765 int be_cmd_get_phy_info(struct be_adapter *adapter)
2766 {
2767         struct be_mcc_wrb *wrb;
2768         struct be_cmd_req_get_phy_info *req;
2769         struct be_dma_mem cmd;
2770         int status;
2771
2772         if (!be_cmd_allowed(adapter, OPCODE_COMMON_GET_PHY_DETAILS,
2773                             CMD_SUBSYSTEM_COMMON))
2774                 return -EPERM;
2775
2776         spin_lock_bh(&adapter->mcc_lock);
2777
2778         wrb = wrb_from_mccq(adapter);
2779         if (!wrb) {
2780                 status = -EBUSY;
2781                 goto err;
2782         }
2783         cmd.size = sizeof(struct be_cmd_req_get_phy_info);
2784         cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma);
2785         if (!cmd.va) {
2786                 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
2787                 status = -ENOMEM;
2788                 goto err;
2789         }
2790
2791         req = cmd.va;
2792
2793         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2794                                OPCODE_COMMON_GET_PHY_DETAILS, sizeof(*req),
2795                                wrb, &cmd);
2796
2797         status = be_mcc_notify_wait(adapter);
2798         if (!status) {
2799                 struct be_phy_info *resp_phy_info =
2800                                 cmd.va + sizeof(struct be_cmd_req_hdr);
2801
2802                 adapter->phy.phy_type = le16_to_cpu(resp_phy_info->phy_type);
2803                 adapter->phy.interface_type =
2804                         le16_to_cpu(resp_phy_info->interface_type);
2805                 adapter->phy.auto_speeds_supported =
2806                         le16_to_cpu(resp_phy_info->auto_speeds_supported);
2807                 adapter->phy.fixed_speeds_supported =
2808                         le16_to_cpu(resp_phy_info->fixed_speeds_supported);
2809                 adapter->phy.misc_params =
2810                         le32_to_cpu(resp_phy_info->misc_params);
2811
2812                 if (BE2_chip(adapter)) {
2813                         adapter->phy.fixed_speeds_supported =
2814                                 BE_SUPPORTED_SPEED_10GBPS |
2815                                 BE_SUPPORTED_SPEED_1GBPS;
2816                 }
2817         }
2818         pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
2819 err:
2820         spin_unlock_bh(&adapter->mcc_lock);
2821         return status;
2822 }
2823
2824 static int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
2825 {
2826         struct be_mcc_wrb *wrb;
2827         struct be_cmd_req_set_qos *req;
2828         int status;
2829
2830         spin_lock_bh(&adapter->mcc_lock);
2831
2832         wrb = wrb_from_mccq(adapter);
2833         if (!wrb) {
2834                 status = -EBUSY;
2835                 goto err;
2836         }
2837
2838         req = embedded_payload(wrb);
2839
2840         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2841                                OPCODE_COMMON_SET_QOS, sizeof(*req), wrb, NULL);
2842
2843         req->hdr.domain = domain;
2844         req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC);
2845         req->max_bps_nic = cpu_to_le32(bps);
2846
2847         status = be_mcc_notify_wait(adapter);
2848
2849 err:
2850         spin_unlock_bh(&adapter->mcc_lock);
2851         return status;
2852 }
2853
2854 int be_cmd_get_cntl_attributes(struct be_adapter *adapter)
2855 {
2856         struct be_mcc_wrb *wrb;
2857         struct be_cmd_req_cntl_attribs *req;
2858         struct be_cmd_resp_cntl_attribs *resp;
2859         int status;
2860         int payload_len = max(sizeof(*req), sizeof(*resp));
2861         struct mgmt_controller_attrib *attribs;
2862         struct be_dma_mem attribs_cmd;
2863
2864         if (mutex_lock_interruptible(&adapter->mbox_lock))
2865                 return -1;
2866
2867         memset(&attribs_cmd, 0, sizeof(struct be_dma_mem));
2868         attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs);
2869         attribs_cmd.va = pci_alloc_consistent(adapter->pdev, attribs_cmd.size,
2870                                               &attribs_cmd.dma);
2871         if (!attribs_cmd.va) {
2872                 dev_err(&adapter->pdev->dev, "Memory allocation failure\n");
2873                 status = -ENOMEM;
2874                 goto err;
2875         }
2876
2877         wrb = wrb_from_mbox(adapter);
2878         if (!wrb) {
2879                 status = -EBUSY;
2880                 goto err;
2881         }
2882         req = attribs_cmd.va;
2883
2884         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2885                                OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len,
2886                                wrb, &attribs_cmd);
2887
2888         status = be_mbox_notify_wait(adapter);
2889         if (!status) {
2890                 attribs = attribs_cmd.va + sizeof(struct be_cmd_resp_hdr);
2891                 adapter->hba_port_num = attribs->hba_attribs.phy_port;
2892         }
2893
2894 err:
2895         mutex_unlock(&adapter->mbox_lock);
2896         if (attribs_cmd.va)
2897                 pci_free_consistent(adapter->pdev, attribs_cmd.size,
2898                                     attribs_cmd.va, attribs_cmd.dma);
2899         return status;
2900 }
2901
2902 /* Uses mbox */
2903 int be_cmd_req_native_mode(struct be_adapter *adapter)
2904 {
2905         struct be_mcc_wrb *wrb;
2906         struct be_cmd_req_set_func_cap *req;
2907         int status;
2908
2909         if (mutex_lock_interruptible(&adapter->mbox_lock))
2910                 return -1;
2911
2912         wrb = wrb_from_mbox(adapter);
2913         if (!wrb) {
2914                 status = -EBUSY;
2915                 goto err;
2916         }
2917
2918         req = embedded_payload(wrb);
2919
2920         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2921                                OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP,
2922                                sizeof(*req), wrb, NULL);
2923
2924         req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS |
2925                                 CAPABILITY_BE3_NATIVE_ERX_API);
2926         req->cap_flags = cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API);
2927
2928         status = be_mbox_notify_wait(adapter);
2929         if (!status) {
2930                 struct be_cmd_resp_set_func_cap *resp = embedded_payload(wrb);
2931
2932                 adapter->be3_native = le32_to_cpu(resp->cap_flags) &
2933                                         CAPABILITY_BE3_NATIVE_ERX_API;
2934                 if (!adapter->be3_native)
2935                         dev_warn(&adapter->pdev->dev,
2936                                  "adapter not in advanced mode\n");
2937         }
2938 err:
2939         mutex_unlock(&adapter->mbox_lock);
2940         return status;
2941 }
2942
2943 /* Get privilege(s) for a function */
2944 int be_cmd_get_fn_privileges(struct be_adapter *adapter, u32 *privilege,
2945                              u32 domain)
2946 {
2947         struct be_mcc_wrb *wrb;
2948         struct be_cmd_req_get_fn_privileges *req;
2949         int status;
2950
2951         spin_lock_bh(&adapter->mcc_lock);
2952
2953         wrb = wrb_from_mccq(adapter);
2954         if (!wrb) {
2955                 status = -EBUSY;
2956                 goto err;
2957         }
2958
2959         req = embedded_payload(wrb);
2960
2961         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2962                                OPCODE_COMMON_GET_FN_PRIVILEGES, sizeof(*req),
2963                                wrb, NULL);
2964
2965         req->hdr.domain = domain;
2966
2967         status = be_mcc_notify_wait(adapter);
2968         if (!status) {
2969                 struct be_cmd_resp_get_fn_privileges *resp =
2970                                                 embedded_payload(wrb);
2971
2972                 *privilege = le32_to_cpu(resp->privilege_mask);
2973
2974                 /* In UMC mode FW does not return right privileges.
2975                  * Override with correct privilege equivalent to PF.
2976                  */
2977                 if (BEx_chip(adapter) && be_is_mc(adapter) &&
2978                     be_physfn(adapter))
2979                         *privilege = MAX_PRIVILEGES;
2980         }
2981
2982 err:
2983         spin_unlock_bh(&adapter->mcc_lock);
2984         return status;
2985 }
2986
2987 /* Set privilege(s) for a function */
2988 int be_cmd_set_fn_privileges(struct be_adapter *adapter, u32 privileges,
2989                              u32 domain)
2990 {
2991         struct be_mcc_wrb *wrb;
2992         struct be_cmd_req_set_fn_privileges *req;
2993         int status;
2994
2995         spin_lock_bh(&adapter->mcc_lock);
2996
2997         wrb = wrb_from_mccq(adapter);
2998         if (!wrb) {
2999                 status = -EBUSY;
3000                 goto err;
3001         }
3002
3003         req = embedded_payload(wrb);
3004         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3005                                OPCODE_COMMON_SET_FN_PRIVILEGES, sizeof(*req),
3006                                wrb, NULL);
3007         req->hdr.domain = domain;
3008         if (lancer_chip(adapter))
3009                 req->privileges_lancer = cpu_to_le32(privileges);
3010         else
3011                 req->privileges = cpu_to_le32(privileges);
3012
3013         status = be_mcc_notify_wait(adapter);
3014 err:
3015         spin_unlock_bh(&adapter->mcc_lock);
3016         return status;
3017 }
3018
3019 /* pmac_id_valid: true => pmac_id is supplied and MAC address is requested.
3020  * pmac_id_valid: false => pmac_id or MAC address is requested.
3021  *                If pmac_id is returned, pmac_id_valid is returned as true
3022  */
3023 int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac,
3024                              bool *pmac_id_valid, u32 *pmac_id, u32 if_handle,
3025                              u8 domain)
3026 {
3027         struct be_mcc_wrb *wrb;
3028         struct be_cmd_req_get_mac_list *req;
3029         int status;
3030         int mac_count;
3031         struct be_dma_mem get_mac_list_cmd;
3032         int i;
3033
3034         memset(&get_mac_list_cmd, 0, sizeof(struct be_dma_mem));
3035         get_mac_list_cmd.size = sizeof(struct be_cmd_resp_get_mac_list);
3036         get_mac_list_cmd.va = pci_alloc_consistent(adapter->pdev,
3037                                                    get_mac_list_cmd.size,
3038                                                    &get_mac_list_cmd.dma);
3039
3040         if (!get_mac_list_cmd.va) {
3041                 dev_err(&adapter->pdev->dev,
3042                         "Memory allocation failure during GET_MAC_LIST\n");
3043                 return -ENOMEM;
3044         }
3045
3046         spin_lock_bh(&adapter->mcc_lock);
3047
3048         wrb = wrb_from_mccq(adapter);
3049         if (!wrb) {
3050                 status = -EBUSY;
3051                 goto out;
3052         }
3053
3054         req = get_mac_list_cmd.va;
3055
3056         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3057                                OPCODE_COMMON_GET_MAC_LIST,
3058                                get_mac_list_cmd.size, wrb, &get_mac_list_cmd);
3059         req->hdr.domain = domain;
3060         req->mac_type = MAC_ADDRESS_TYPE_NETWORK;
3061         if (*pmac_id_valid) {
3062                 req->mac_id = cpu_to_le32(*pmac_id);
3063                 req->iface_id = cpu_to_le16(if_handle);
3064                 req->perm_override = 0;
3065         } else {
3066                 req->perm_override = 1;
3067         }
3068
3069         status = be_mcc_notify_wait(adapter);
3070         if (!status) {
3071                 struct be_cmd_resp_get_mac_list *resp =
3072                                                 get_mac_list_cmd.va;
3073
3074                 if (*pmac_id_valid) {
3075                         memcpy(mac, resp->macid_macaddr.mac_addr_id.macaddr,
3076                                ETH_ALEN);
3077                         goto out;
3078                 }
3079
3080                 mac_count = resp->true_mac_count + resp->pseudo_mac_count;
3081                 /* Mac list returned could contain one or more active mac_ids
3082                  * or one or more true or pseudo permanant mac addresses.
3083                  * If an active mac_id is present, return first active mac_id
3084                  * found.
3085                  */
3086                 for (i = 0; i < mac_count; i++) {
3087                         struct get_list_macaddr *mac_entry;
3088                         u16 mac_addr_size;
3089                         u32 mac_id;
3090
3091                         mac_entry = &resp->macaddr_list[i];
3092                         mac_addr_size = le16_to_cpu(mac_entry->mac_addr_size);
3093                         /* mac_id is a 32 bit value and mac_addr size
3094                          * is 6 bytes
3095                          */
3096                         if (mac_addr_size == sizeof(u32)) {
3097                                 *pmac_id_valid = true;
3098                                 mac_id = mac_entry->mac_addr_id.s_mac_id.mac_id;
3099                                 *pmac_id = le32_to_cpu(mac_id);
3100                                 goto out;
3101                         }
3102                 }
3103                 /* If no active mac_id found, return first mac addr */
3104                 *pmac_id_valid = false;
3105                 memcpy(mac, resp->macaddr_list[0].mac_addr_id.macaddr,
3106                        ETH_ALEN);
3107         }
3108
3109 out:
3110         spin_unlock_bh(&adapter->mcc_lock);
3111         pci_free_consistent(adapter->pdev, get_mac_list_cmd.size,
3112                             get_mac_list_cmd.va, get_mac_list_cmd.dma);
3113         return status;
3114 }
3115
3116 int be_cmd_get_active_mac(struct be_adapter *adapter, u32 curr_pmac_id,
3117                           u8 *mac, u32 if_handle, bool active, u32 domain)
3118 {
3119         if (!active)
3120                 be_cmd_get_mac_from_list(adapter, mac, &active, &curr_pmac_id,
3121                                          if_handle, domain);
3122         if (BEx_chip(adapter))
3123                 return be_cmd_mac_addr_query(adapter, mac, false,
3124                                              if_handle, curr_pmac_id);
3125         else
3126                 /* Fetch the MAC address using pmac_id */
3127                 return be_cmd_get_mac_from_list(adapter, mac, &active,
3128                                                 &curr_pmac_id,
3129                                                 if_handle, domain);
3130 }
3131
3132 int be_cmd_get_perm_mac(struct be_adapter *adapter, u8 *mac)
3133 {
3134         int status;
3135         bool pmac_valid = false;
3136
3137         memset(mac, 0, ETH_ALEN);
3138
3139         if (BEx_chip(adapter)) {
3140                 if (be_physfn(adapter))
3141                         status = be_cmd_mac_addr_query(adapter, mac, true, 0,
3142                                                        0);
3143                 else
3144                         status = be_cmd_mac_addr_query(adapter, mac, false,
3145                                                        adapter->if_handle, 0);
3146         } else {
3147                 status = be_cmd_get_mac_from_list(adapter, mac, &pmac_valid,
3148                                                   NULL, adapter->if_handle, 0);
3149         }
3150
3151         return status;
3152 }
3153
3154 /* Uses synchronous MCCQ */
3155 int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array,
3156                         u8 mac_count, u32 domain)
3157 {
3158         struct be_mcc_wrb *wrb;
3159         struct be_cmd_req_set_mac_list *req;
3160         int status;
3161         struct be_dma_mem cmd;
3162
3163         memset(&cmd, 0, sizeof(struct be_dma_mem));
3164         cmd.size = sizeof(struct be_cmd_req_set_mac_list);
3165         cmd.va = dma_alloc_coherent(&adapter->pdev->dev, cmd.size,
3166                                     &cmd.dma, GFP_KERNEL);
3167         if (!cmd.va)
3168                 return -ENOMEM;
3169
3170         spin_lock_bh(&adapter->mcc_lock);
3171
3172         wrb = wrb_from_mccq(adapter);
3173         if (!wrb) {
3174                 status = -EBUSY;
3175                 goto err;
3176         }
3177
3178         req = cmd.va;
3179         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3180                                OPCODE_COMMON_SET_MAC_LIST, sizeof(*req),
3181                                wrb, &cmd);
3182
3183         req->hdr.domain = domain;
3184         req->mac_count = mac_count;
3185         if (mac_count)
3186                 memcpy(req->mac, mac_array, ETH_ALEN*mac_count);
3187
3188         status = be_mcc_notify_wait(adapter);
3189
3190 err:
3191         dma_free_coherent(&adapter->pdev->dev, cmd.size, cmd.va, cmd.dma);
3192         spin_unlock_bh(&adapter->mcc_lock);
3193         return status;
3194 }
3195
3196 /* Wrapper to delete any active MACs and provision the new mac.
3197  * Changes to MAC_LIST are allowed iff none of the MAC addresses in the
3198  * current list are active.
3199  */
3200 int be_cmd_set_mac(struct be_adapter *adapter, u8 *mac, int if_id, u32 dom)
3201 {
3202         bool active_mac = false;
3203         u8 old_mac[ETH_ALEN];
3204         u32 pmac_id;
3205         int status;
3206
3207         status = be_cmd_get_mac_from_list(adapter, old_mac, &active_mac,
3208                                           &pmac_id, if_id, dom);
3209
3210         if (!status && active_mac)
3211                 be_cmd_pmac_del(adapter, if_id, pmac_id, dom);
3212
3213         return be_cmd_set_mac_list(adapter, mac, mac ? 1 : 0, dom);
3214 }
3215
3216 int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid,
3217                           u32 domain, u16 intf_id, u16 hsw_mode)
3218 {
3219         struct be_mcc_wrb *wrb;
3220         struct be_cmd_req_set_hsw_config *req;
3221         void *ctxt;
3222         int status;
3223
3224         spin_lock_bh(&adapter->mcc_lock);
3225
3226         wrb = wrb_from_mccq(adapter);
3227         if (!wrb) {
3228                 status = -EBUSY;
3229                 goto err;
3230         }
3231
3232         req = embedded_payload(wrb);
3233         ctxt = &req->context;
3234
3235         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3236                                OPCODE_COMMON_SET_HSW_CONFIG, sizeof(*req), wrb,
3237                                NULL);
3238
3239         req->hdr.domain = domain;
3240         AMAP_SET_BITS(struct amap_set_hsw_context, interface_id, ctxt, intf_id);
3241         if (pvid) {
3242                 AMAP_SET_BITS(struct amap_set_hsw_context, pvid_valid, ctxt, 1);
3243                 AMAP_SET_BITS(struct amap_set_hsw_context, pvid, ctxt, pvid);
3244         }
3245         if (!BEx_chip(adapter) && hsw_mode) {
3246                 AMAP_SET_BITS(struct amap_set_hsw_context, interface_id,
3247                               ctxt, adapter->hba_port_num);
3248                 AMAP_SET_BITS(struct amap_set_hsw_context, pport, ctxt, 1);
3249                 AMAP_SET_BITS(struct amap_set_hsw_context, port_fwd_type,
3250                               ctxt, hsw_mode);
3251         }
3252
3253         be_dws_cpu_to_le(req->context, sizeof(req->context));
3254         status = be_mcc_notify_wait(adapter);
3255
3256 err:
3257         spin_unlock_bh(&adapter->mcc_lock);
3258         return status;
3259 }
3260
3261 /* Get Hyper switch config */
3262 int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid,
3263                           u32 domain, u16 intf_id, u8 *mode)
3264 {
3265         struct be_mcc_wrb *wrb;
3266         struct be_cmd_req_get_hsw_config *req;
3267         void *ctxt;
3268         int status;
3269         u16 vid;
3270
3271         spin_lock_bh(&adapter->mcc_lock);
3272
3273         wrb = wrb_from_mccq(adapter);
3274         if (!wrb) {
3275                 status = -EBUSY;
3276                 goto err;
3277         }
3278
3279         req = embedded_payload(wrb);
3280         ctxt = &req->context;
3281
3282         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3283                                OPCODE_COMMON_GET_HSW_CONFIG, sizeof(*req), wrb,
3284                                NULL);
3285
3286         req->hdr.domain = domain;
3287         AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id,
3288                       ctxt, intf_id);
3289         AMAP_SET_BITS(struct amap_get_hsw_req_context, pvid_valid, ctxt, 1);
3290
3291         if (!BEx_chip(adapter) && mode) {
3292                 AMAP_SET_BITS(struct amap_get_hsw_req_context, interface_id,
3293                               ctxt, adapter->hba_port_num);
3294                 AMAP_SET_BITS(struct amap_get_hsw_req_context, pport, ctxt, 1);
3295         }
3296         be_dws_cpu_to_le(req->context, sizeof(req->context));
3297
3298         status = be_mcc_notify_wait(adapter);
3299         if (!status) {
3300                 struct be_cmd_resp_get_hsw_config *resp =
3301                                                 embedded_payload(wrb);
3302
3303                 be_dws_le_to_cpu(&resp->context, sizeof(resp->context));
3304                 vid = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
3305                                     pvid, &resp->context);
3306                 if (pvid)
3307                         *pvid = le16_to_cpu(vid);
3308                 if (mode)
3309                         *mode = AMAP_GET_BITS(struct amap_get_hsw_resp_context,
3310                                               port_fwd_type, &resp->context);
3311         }
3312
3313 err:
3314         spin_unlock_bh(&adapter->mcc_lock);
3315         return status;
3316 }
3317
3318 static bool be_is_wol_excluded(struct be_adapter *adapter)
3319 {
3320         struct pci_dev *pdev = adapter->pdev;
3321
3322         if (!be_physfn(adapter))
3323                 return true;
3324
3325         switch (pdev->subsystem_device) {
3326         case OC_SUBSYS_DEVICE_ID1:
3327         case OC_SUBSYS_DEVICE_ID2:
3328         case OC_SUBSYS_DEVICE_ID3:
3329         case OC_SUBSYS_DEVICE_ID4:
3330                 return true;
3331         default:
3332                 return false;
3333         }
3334 }
3335
3336 int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter)
3337 {
3338         struct be_mcc_wrb *wrb;
3339         struct be_cmd_req_acpi_wol_magic_config_v1 *req;
3340         int status = 0;
3341         struct be_dma_mem cmd;
3342
3343         if (!be_cmd_allowed(adapter, OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
3344                             CMD_SUBSYSTEM_ETH))
3345                 return -EPERM;
3346
3347         if (be_is_wol_excluded(adapter))
3348                 return status;
3349
3350         if (mutex_lock_interruptible(&adapter->mbox_lock))
3351                 return -1;
3352
3353         memset(&cmd, 0, sizeof(struct be_dma_mem));
3354         cmd.size = sizeof(struct be_cmd_resp_acpi_wol_magic_config_v1);
3355         cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma);
3356         if (!cmd.va) {
3357                 dev_err(&adapter->pdev->dev, "Memory allocation failure\n");
3358                 status = -ENOMEM;
3359                 goto err;
3360         }
3361
3362         wrb = wrb_from_mbox(adapter);
3363         if (!wrb) {
3364                 status = -EBUSY;
3365                 goto err;
3366         }
3367
3368         req = cmd.va;
3369
3370         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
3371                                OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG,
3372                                sizeof(*req), wrb, &cmd);
3373
3374         req->hdr.version = 1;
3375         req->query_options = BE_GET_WOL_CAP;
3376
3377         status = be_mbox_notify_wait(adapter);
3378         if (!status) {
3379                 struct be_cmd_resp_acpi_wol_magic_config_v1 *resp;
3380
3381                 resp = (struct be_cmd_resp_acpi_wol_magic_config_v1 *)cmd.va;
3382
3383                 adapter->wol_cap = resp->wol_settings;
3384                 if (adapter->wol_cap & BE_WOL_CAP)
3385                         adapter->wol_en = true;
3386         }
3387 err:
3388         mutex_unlock(&adapter->mbox_lock);
3389         if (cmd.va)
3390                 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
3391         return status;
3392
3393 }
3394
3395 int be_cmd_set_fw_log_level(struct be_adapter *adapter, u32 level)
3396 {
3397         struct be_dma_mem extfat_cmd;
3398         struct be_fat_conf_params *cfgs;
3399         int status;
3400         int i, j;
3401
3402         memset(&extfat_cmd, 0, sizeof(struct be_dma_mem));
3403         extfat_cmd.size = sizeof(struct be_cmd_resp_get_ext_fat_caps);
3404         extfat_cmd.va = pci_alloc_consistent(adapter->pdev, extfat_cmd.size,
3405                                              &extfat_cmd.dma);
3406         if (!extfat_cmd.va)
3407                 return -ENOMEM;
3408
3409         status = be_cmd_get_ext_fat_capabilites(adapter, &extfat_cmd);
3410         if (status)
3411                 goto err;
3412
3413         cfgs = (struct be_fat_conf_params *)
3414                         (extfat_cmd.va + sizeof(struct be_cmd_resp_hdr));
3415         for (i = 0; i < le32_to_cpu(cfgs->num_modules); i++) {
3416                 u32 num_modes = le32_to_cpu(cfgs->module[i].num_modes);
3417
3418                 for (j = 0; j < num_modes; j++) {
3419                         if (cfgs->module[i].trace_lvl[j].mode == MODE_UART)
3420                                 cfgs->module[i].trace_lvl[j].dbg_lvl =
3421                                                         cpu_to_le32(level);
3422                 }
3423         }
3424
3425         status = be_cmd_set_ext_fat_capabilites(adapter, &extfat_cmd, cfgs);
3426 err:
3427         pci_free_consistent(adapter->pdev, extfat_cmd.size, extfat_cmd.va,
3428                             extfat_cmd.dma);
3429         return status;
3430 }
3431
3432 int be_cmd_get_fw_log_level(struct be_adapter *adapter)
3433 {
3434         struct be_dma_mem extfat_cmd;
3435         struct be_fat_conf_params *cfgs;
3436         int status, j;
3437         int level = 0;
3438
3439         memset(&extfat_cmd, 0, sizeof(struct be_dma_mem));
3440         extfat_cmd.size = sizeof(struct be_cmd_resp_get_ext_fat_caps);
3441         extfat_cmd.va = pci_alloc_consistent(adapter->pdev, extfat_cmd.size,
3442                                              &extfat_cmd.dma);
3443
3444         if (!extfat_cmd.va) {
3445                 dev_err(&adapter->pdev->dev, "%s: Memory allocation failure\n",
3446                         __func__);
3447                 goto err;
3448         }
3449
3450         status = be_cmd_get_ext_fat_capabilites(adapter, &extfat_cmd);
3451         if (!status) {
3452                 cfgs = (struct be_fat_conf_params *)(extfat_cmd.va +
3453                                                 sizeof(struct be_cmd_resp_hdr));
3454
3455                 for (j = 0; j < le32_to_cpu(cfgs->module[0].num_modes); j++) {
3456                         if (cfgs->module[0].trace_lvl[j].mode == MODE_UART)
3457                                 level = cfgs->module[0].trace_lvl[j].dbg_lvl;
3458                 }
3459         }
3460         pci_free_consistent(adapter->pdev, extfat_cmd.size, extfat_cmd.va,
3461                             extfat_cmd.dma);
3462 err:
3463         return level;
3464 }
3465
3466 int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter,
3467                                    struct be_dma_mem *cmd)
3468 {
3469         struct be_mcc_wrb *wrb;
3470         struct be_cmd_req_get_ext_fat_caps *req;
3471         int status;
3472
3473         if (mutex_lock_interruptible(&adapter->mbox_lock))
3474                 return -1;
3475
3476         wrb = wrb_from_mbox(adapter);
3477         if (!wrb) {
3478                 status = -EBUSY;
3479                 goto err;
3480         }
3481
3482         req = cmd->va;
3483         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3484                                OPCODE_COMMON_GET_EXT_FAT_CAPABILITES,
3485                                cmd->size, wrb, cmd);
3486         req->parameter_type = cpu_to_le32(1);
3487
3488         status = be_mbox_notify_wait(adapter);
3489 err:
3490         mutex_unlock(&adapter->mbox_lock);
3491         return status;
3492 }
3493
3494 int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter,
3495                                    struct be_dma_mem *cmd,
3496                                    struct be_fat_conf_params *configs)
3497 {
3498         struct be_mcc_wrb *wrb;
3499         struct be_cmd_req_set_ext_fat_caps *req;
3500         int status;
3501
3502         spin_lock_bh(&adapter->mcc_lock);
3503
3504         wrb = wrb_from_mccq(adapter);
3505         if (!wrb) {
3506                 status = -EBUSY;
3507                 goto err;
3508         }
3509
3510         req = cmd->va;
3511         memcpy(&req->set_params, configs, sizeof(struct be_fat_conf_params));
3512         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3513                                OPCODE_COMMON_SET_EXT_FAT_CAPABILITES,
3514                                cmd->size, wrb, cmd);
3515
3516         status = be_mcc_notify_wait(adapter);
3517 err:
3518         spin_unlock_bh(&adapter->mcc_lock);
3519         return status;
3520 }
3521
3522 int be_cmd_query_port_name(struct be_adapter *adapter)
3523 {
3524         struct be_cmd_req_get_port_name *req;
3525         struct be_mcc_wrb *wrb;
3526         int status;
3527
3528         if (mutex_lock_interruptible(&adapter->mbox_lock))
3529                 return -1;
3530
3531         wrb = wrb_from_mbox(adapter);
3532         req = embedded_payload(wrb);
3533
3534         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3535                                OPCODE_COMMON_GET_PORT_NAME, sizeof(*req), wrb,
3536                                NULL);
3537         if (!BEx_chip(adapter))
3538                 req->hdr.version = 1;
3539
3540         status = be_mbox_notify_wait(adapter);
3541         if (!status) {
3542                 struct be_cmd_resp_get_port_name *resp = embedded_payload(wrb);
3543
3544                 adapter->port_name = resp->port_name[adapter->hba_port_num];
3545         } else {
3546                 adapter->port_name = adapter->hba_port_num + '0';
3547         }
3548
3549         mutex_unlock(&adapter->mbox_lock);
3550         return status;
3551 }
3552
3553 /* Descriptor type */
3554 enum {
3555         FUNC_DESC = 1,
3556         VFT_DESC = 2
3557 };
3558
3559 static struct be_nic_res_desc *be_get_nic_desc(u8 *buf, u32 desc_count,
3560                                                int desc_type)
3561 {
3562         struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
3563         struct be_nic_res_desc *nic;
3564         int i;
3565
3566         for (i = 0; i < desc_count; i++) {
3567                 if (hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V0 ||
3568                     hdr->desc_type == NIC_RESOURCE_DESC_TYPE_V1) {
3569                         nic = (struct be_nic_res_desc *)hdr;
3570                         if (desc_type == FUNC_DESC ||
3571                             (desc_type == VFT_DESC &&
3572                              nic->flags & (1 << VFT_SHIFT)))
3573                                 return nic;
3574                 }
3575
3576                 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
3577                 hdr = (void *)hdr + hdr->desc_len;
3578         }
3579         return NULL;
3580 }
3581
3582 static struct be_nic_res_desc *be_get_vft_desc(u8 *buf, u32 desc_count)
3583 {
3584         return be_get_nic_desc(buf, desc_count, VFT_DESC);
3585 }
3586
3587 static struct be_nic_res_desc *be_get_func_nic_desc(u8 *buf, u32 desc_count)
3588 {
3589         return be_get_nic_desc(buf, desc_count, FUNC_DESC);
3590 }
3591
3592 static struct be_pcie_res_desc *be_get_pcie_desc(u8 devfn, u8 *buf,
3593                                                  u32 desc_count)
3594 {
3595         struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
3596         struct be_pcie_res_desc *pcie;
3597         int i;
3598
3599         for (i = 0; i < desc_count; i++) {
3600                 if ((hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V0 ||
3601                      hdr->desc_type == PCIE_RESOURCE_DESC_TYPE_V1)) {
3602                         pcie = (struct be_pcie_res_desc *)hdr;
3603                         if (pcie->pf_num == devfn)
3604                                 return pcie;
3605                 }
3606
3607                 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
3608                 hdr = (void *)hdr + hdr->desc_len;
3609         }
3610         return NULL;
3611 }
3612
3613 static struct be_port_res_desc *be_get_port_desc(u8 *buf, u32 desc_count)
3614 {
3615         struct be_res_desc_hdr *hdr = (struct be_res_desc_hdr *)buf;
3616         int i;
3617
3618         for (i = 0; i < desc_count; i++) {
3619                 if (hdr->desc_type == PORT_RESOURCE_DESC_TYPE_V1)
3620                         return (struct be_port_res_desc *)hdr;
3621
3622                 hdr->desc_len = hdr->desc_len ? : RESOURCE_DESC_SIZE_V0;
3623                 hdr = (void *)hdr + hdr->desc_len;
3624         }
3625         return NULL;
3626 }
3627
3628 static void be_copy_nic_desc(struct be_resources *res,
3629                              struct be_nic_res_desc *desc)
3630 {
3631         res->max_uc_mac = le16_to_cpu(desc->unicast_mac_count);
3632         res->max_vlans = le16_to_cpu(desc->vlan_count);
3633         res->max_mcast_mac = le16_to_cpu(desc->mcast_mac_count);
3634         res->max_tx_qs = le16_to_cpu(desc->txq_count);
3635         res->max_rss_qs = le16_to_cpu(desc->rssq_count);
3636         res->max_rx_qs = le16_to_cpu(desc->rq_count);
3637         res->max_evt_qs = le16_to_cpu(desc->eq_count);
3638         /* Clear flags that driver is not interested in */
3639         res->if_cap_flags = le32_to_cpu(desc->cap_flags) &
3640                                 BE_IF_CAP_FLAGS_WANT;
3641         /* Need 1 RXQ as the default RXQ */
3642         if (res->max_rss_qs && res->max_rss_qs == res->max_rx_qs)
3643                 res->max_rss_qs -= 1;
3644 }
3645
3646 /* Uses Mbox */
3647 int be_cmd_get_func_config(struct be_adapter *adapter, struct be_resources *res)
3648 {
3649         struct be_mcc_wrb *wrb;
3650         struct be_cmd_req_get_func_config *req;
3651         int status;
3652         struct be_dma_mem cmd;
3653
3654         if (mutex_lock_interruptible(&adapter->mbox_lock))
3655                 return -1;
3656
3657         memset(&cmd, 0, sizeof(struct be_dma_mem));
3658         cmd.size = sizeof(struct be_cmd_resp_get_func_config);
3659         cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma);
3660         if (!cmd.va) {
3661                 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
3662                 status = -ENOMEM;
3663                 goto err;
3664         }
3665
3666         wrb = wrb_from_mbox(adapter);
3667         if (!wrb) {
3668                 status = -EBUSY;
3669                 goto err;
3670         }
3671
3672         req = cmd.va;
3673
3674         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3675                                OPCODE_COMMON_GET_FUNC_CONFIG,
3676                                cmd.size, wrb, &cmd);
3677
3678         if (skyhawk_chip(adapter))
3679                 req->hdr.version = 1;
3680
3681         status = be_mbox_notify_wait(adapter);
3682         if (!status) {
3683                 struct be_cmd_resp_get_func_config *resp = cmd.va;
3684                 u32 desc_count = le32_to_cpu(resp->desc_count);
3685                 struct be_nic_res_desc *desc;
3686
3687                 desc = be_get_func_nic_desc(resp->func_param, desc_count);
3688                 if (!desc) {
3689                         status = -EINVAL;
3690                         goto err;
3691                 }
3692
3693                 adapter->pf_number = desc->pf_num;
3694                 be_copy_nic_desc(res, desc);
3695         }
3696 err:
3697         mutex_unlock(&adapter->mbox_lock);
3698         if (cmd.va)
3699                 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
3700         return status;
3701 }
3702
3703 /* Will use MBOX only if MCCQ has not been created */
3704 int be_cmd_get_profile_config(struct be_adapter *adapter,
3705                               struct be_resources *res, u8 domain)
3706 {
3707         struct be_cmd_resp_get_profile_config *resp;
3708         struct be_cmd_req_get_profile_config *req;
3709         struct be_nic_res_desc *vf_res;
3710         struct be_pcie_res_desc *pcie;
3711         struct be_port_res_desc *port;
3712         struct be_nic_res_desc *nic;
3713         struct be_mcc_wrb wrb = {0};
3714         struct be_dma_mem cmd;
3715         u32 desc_count;
3716         int status;
3717
3718         memset(&cmd, 0, sizeof(struct be_dma_mem));
3719         cmd.size = sizeof(struct be_cmd_resp_get_profile_config);
3720         cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma);
3721         if (!cmd.va)
3722                 return -ENOMEM;
3723
3724         req = cmd.va;
3725         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3726                                OPCODE_COMMON_GET_PROFILE_CONFIG,
3727                                cmd.size, &wrb, &cmd);
3728
3729         req->hdr.domain = domain;
3730         if (!lancer_chip(adapter))
3731                 req->hdr.version = 1;
3732         req->type = ACTIVE_PROFILE_TYPE;
3733
3734         status = be_cmd_notify_wait(adapter, &wrb);
3735         if (status)
3736                 goto err;
3737
3738         resp = cmd.va;
3739         desc_count = le32_to_cpu(resp->desc_count);
3740
3741         pcie = be_get_pcie_desc(adapter->pdev->devfn, resp->func_param,
3742                                 desc_count);
3743         if (pcie)
3744                 res->max_vfs = le16_to_cpu(pcie->num_vfs);
3745
3746         port = be_get_port_desc(resp->func_param, desc_count);
3747         if (port)
3748                 adapter->mc_type = port->mc_type;
3749
3750         nic = be_get_func_nic_desc(resp->func_param, desc_count);
3751         if (nic)
3752                 be_copy_nic_desc(res, nic);
3753
3754         vf_res = be_get_vft_desc(resp->func_param, desc_count);
3755         if (vf_res)
3756                 res->vf_if_cap_flags = vf_res->cap_flags;
3757 err:
3758         if (cmd.va)
3759                 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
3760         return status;
3761 }
3762
3763 /* Will use MBOX only if MCCQ has not been created */
3764 static int be_cmd_set_profile_config(struct be_adapter *adapter, void *desc,
3765                                      int size, int count, u8 version, u8 domain)
3766 {
3767         struct be_cmd_req_set_profile_config *req;
3768         struct be_mcc_wrb wrb = {0};
3769         struct be_dma_mem cmd;
3770         int status;
3771
3772         memset(&cmd, 0, sizeof(struct be_dma_mem));
3773         cmd.size = sizeof(struct be_cmd_req_set_profile_config);
3774         cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma);
3775         if (!cmd.va)
3776                 return -ENOMEM;
3777
3778         req = cmd.va;
3779         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3780                                OPCODE_COMMON_SET_PROFILE_CONFIG, cmd.size,
3781                                &wrb, &cmd);
3782         req->hdr.version = version;
3783         req->hdr.domain = domain;
3784         req->desc_count = cpu_to_le32(count);
3785         memcpy(req->desc, desc, size);
3786
3787         status = be_cmd_notify_wait(adapter, &wrb);
3788
3789         if (cmd.va)
3790                 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
3791         return status;
3792 }
3793
3794 /* Mark all fields invalid */
3795 static void be_reset_nic_desc(struct be_nic_res_desc *nic)
3796 {
3797         memset(nic, 0, sizeof(*nic));
3798         nic->unicast_mac_count = 0xFFFF;
3799         nic->mcc_count = 0xFFFF;
3800         nic->vlan_count = 0xFFFF;
3801         nic->mcast_mac_count = 0xFFFF;
3802         nic->txq_count = 0xFFFF;
3803         nic->rq_count = 0xFFFF;
3804         nic->rssq_count = 0xFFFF;
3805         nic->lro_count = 0xFFFF;
3806         nic->cq_count = 0xFFFF;
3807         nic->toe_conn_count = 0xFFFF;
3808         nic->eq_count = 0xFFFF;
3809         nic->iface_count = 0xFFFF;
3810         nic->link_param = 0xFF;
3811         nic->channel_id_param = cpu_to_le16(0xF000);
3812         nic->acpi_params = 0xFF;
3813         nic->wol_param = 0x0F;
3814         nic->tunnel_iface_count = 0xFFFF;
3815         nic->direct_tenant_iface_count = 0xFFFF;
3816         nic->bw_min = 0xFFFFFFFF;
3817         nic->bw_max = 0xFFFFFFFF;
3818 }
3819
3820 /* Mark all fields invalid */
3821 static void be_reset_pcie_desc(struct be_pcie_res_desc *pcie)
3822 {
3823         memset(pcie, 0, sizeof(*pcie));
3824         pcie->sriov_state = 0xFF;
3825         pcie->pf_state = 0xFF;
3826         pcie->pf_type = 0xFF;
3827         pcie->num_vfs = 0xFFFF;
3828 }
3829
3830 int be_cmd_config_qos(struct be_adapter *adapter, u32 max_rate, u16 link_speed,
3831                       u8 domain)
3832 {
3833         struct be_nic_res_desc nic_desc;
3834         u32 bw_percent;
3835         u16 version = 0;
3836
3837         if (BE3_chip(adapter))
3838                 return be_cmd_set_qos(adapter, max_rate / 10, domain);
3839
3840         be_reset_nic_desc(&nic_desc);
3841         nic_desc.pf_num = adapter->pf_number;
3842         nic_desc.vf_num = domain;
3843         nic_desc.bw_min = 0;
3844         if (lancer_chip(adapter)) {
3845                 nic_desc.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V0;
3846                 nic_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V0;
3847                 nic_desc.flags = (1 << QUN_SHIFT) | (1 << IMM_SHIFT) |
3848                                         (1 << NOSV_SHIFT);
3849                 nic_desc.bw_max = cpu_to_le32(max_rate / 10);
3850         } else {
3851                 version = 1;
3852                 nic_desc.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V1;
3853                 nic_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
3854                 nic_desc.flags = (1 << IMM_SHIFT) | (1 << NOSV_SHIFT);
3855                 bw_percent = max_rate ? (max_rate * 100) / link_speed : 100;
3856                 nic_desc.bw_max = cpu_to_le32(bw_percent);
3857         }
3858
3859         return be_cmd_set_profile_config(adapter, &nic_desc,
3860                                          nic_desc.hdr.desc_len,
3861                                          1, version, domain);
3862 }
3863
3864 int be_cmd_set_sriov_config(struct be_adapter *adapter,
3865                             struct be_resources res, u16 num_vfs)
3866 {
3867         struct {
3868                 struct be_pcie_res_desc pcie;
3869                 struct be_nic_res_desc nic_vft;
3870         } __packed desc;
3871         u16 vf_q_count;
3872
3873         if (BEx_chip(adapter) || lancer_chip(adapter))
3874                 return 0;
3875
3876         /* PF PCIE descriptor */
3877         be_reset_pcie_desc(&desc.pcie);
3878         desc.pcie.hdr.desc_type = PCIE_RESOURCE_DESC_TYPE_V1;
3879         desc.pcie.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
3880         desc.pcie.flags = (1 << IMM_SHIFT) | (1 << NOSV_SHIFT);
3881         desc.pcie.pf_num = adapter->pdev->devfn;
3882         desc.pcie.sriov_state = num_vfs ? 1 : 0;
3883         desc.pcie.num_vfs = cpu_to_le16(num_vfs);
3884
3885         /* VF NIC Template descriptor */
3886         be_reset_nic_desc(&desc.nic_vft);
3887         desc.nic_vft.hdr.desc_type = NIC_RESOURCE_DESC_TYPE_V1;
3888         desc.nic_vft.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
3889         desc.nic_vft.flags = (1 << VFT_SHIFT) | (1 << IMM_SHIFT) |
3890                                 (1 << NOSV_SHIFT);
3891         desc.nic_vft.pf_num = adapter->pdev->devfn;
3892         desc.nic_vft.vf_num = 0;
3893
3894         if (num_vfs && res.vf_if_cap_flags & BE_IF_FLAGS_RSS) {
3895                 /* If number of VFs requested is 8 less than max supported,
3896                  * assign 8 queue pairs to the PF and divide the remaining
3897                  * resources evenly among the VFs
3898                  */
3899                 if (num_vfs < (be_max_vfs(adapter) - 8))
3900                         vf_q_count = (res.max_rss_qs - 8) / num_vfs;
3901                 else
3902                         vf_q_count = res.max_rss_qs / num_vfs;
3903
3904                 desc.nic_vft.rq_count = cpu_to_le16(vf_q_count);
3905                 desc.nic_vft.txq_count = cpu_to_le16(vf_q_count);
3906                 desc.nic_vft.rssq_count = cpu_to_le16(vf_q_count - 1);
3907                 desc.nic_vft.cq_count = cpu_to_le16(3 * vf_q_count);
3908         } else {
3909                 desc.nic_vft.txq_count = cpu_to_le16(1);
3910                 desc.nic_vft.rq_count = cpu_to_le16(1);
3911                 desc.nic_vft.rssq_count = cpu_to_le16(0);
3912                 /* One CQ for each TX, RX and MCCQ */
3913                 desc.nic_vft.cq_count = cpu_to_le16(3);
3914         }
3915
3916         return be_cmd_set_profile_config(adapter, &desc,
3917                                          2 * RESOURCE_DESC_SIZE_V1, 2, 1, 0);
3918 }
3919
3920 int be_cmd_manage_iface(struct be_adapter *adapter, u32 iface, u8 op)
3921 {
3922         struct be_mcc_wrb *wrb;
3923         struct be_cmd_req_manage_iface_filters *req;
3924         int status;
3925
3926         if (iface == 0xFFFFFFFF)
3927                 return -1;
3928
3929         spin_lock_bh(&adapter->mcc_lock);
3930
3931         wrb = wrb_from_mccq(adapter);
3932         if (!wrb) {
3933                 status = -EBUSY;
3934                 goto err;
3935         }
3936         req = embedded_payload(wrb);
3937
3938         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3939                                OPCODE_COMMON_MANAGE_IFACE_FILTERS, sizeof(*req),
3940                                wrb, NULL);
3941         req->op = op;
3942         req->target_iface_id = cpu_to_le32(iface);
3943
3944         status = be_mcc_notify_wait(adapter);
3945 err:
3946         spin_unlock_bh(&adapter->mcc_lock);
3947         return status;
3948 }
3949
3950 int be_cmd_set_vxlan_port(struct be_adapter *adapter, __be16 port)
3951 {
3952         struct be_port_res_desc port_desc;
3953
3954         memset(&port_desc, 0, sizeof(port_desc));
3955         port_desc.hdr.desc_type = PORT_RESOURCE_DESC_TYPE_V1;
3956         port_desc.hdr.desc_len = RESOURCE_DESC_SIZE_V1;
3957         port_desc.flags = (1 << IMM_SHIFT) | (1 << NOSV_SHIFT);
3958         port_desc.link_num = adapter->hba_port_num;
3959         if (port) {
3960                 port_desc.nv_flags = NV_TYPE_VXLAN | (1 << SOCVID_SHIFT) |
3961                                         (1 << RCVID_SHIFT);
3962                 port_desc.nv_port = swab16(port);
3963         } else {
3964                 port_desc.nv_flags = NV_TYPE_DISABLED;
3965                 port_desc.nv_port = 0;
3966         }
3967
3968         return be_cmd_set_profile_config(adapter, &port_desc,
3969                                          RESOURCE_DESC_SIZE_V1, 1, 1, 0);
3970 }
3971
3972 int be_cmd_get_if_id(struct be_adapter *adapter, struct be_vf_cfg *vf_cfg,
3973                      int vf_num)
3974 {
3975         struct be_mcc_wrb *wrb;
3976         struct be_cmd_req_get_iface_list *req;
3977         struct be_cmd_resp_get_iface_list *resp;
3978         int status;
3979
3980         spin_lock_bh(&adapter->mcc_lock);
3981
3982         wrb = wrb_from_mccq(adapter);
3983         if (!wrb) {
3984                 status = -EBUSY;
3985                 goto err;
3986         }
3987         req = embedded_payload(wrb);
3988
3989         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
3990                                OPCODE_COMMON_GET_IFACE_LIST, sizeof(*resp),
3991                                wrb, NULL);
3992         req->hdr.domain = vf_num + 1;
3993
3994         status = be_mcc_notify_wait(adapter);
3995         if (!status) {
3996                 resp = (struct be_cmd_resp_get_iface_list *)req;
3997                 vf_cfg->if_handle = le32_to_cpu(resp->if_desc.if_id);
3998         }
3999
4000 err:
4001         spin_unlock_bh(&adapter->mcc_lock);
4002         return status;
4003 }
4004
4005 static int lancer_wait_idle(struct be_adapter *adapter)
4006 {
4007 #define SLIPORT_IDLE_TIMEOUT 30
4008         u32 reg_val;
4009         int status = 0, i;
4010
4011         for (i = 0; i < SLIPORT_IDLE_TIMEOUT; i++) {
4012                 reg_val = ioread32(adapter->db + PHYSDEV_CONTROL_OFFSET);
4013                 if ((reg_val & PHYSDEV_CONTROL_INP_MASK) == 0)
4014                         break;
4015
4016                 ssleep(1);
4017         }
4018
4019         if (i == SLIPORT_IDLE_TIMEOUT)
4020                 status = -1;
4021
4022         return status;
4023 }
4024
4025 int lancer_physdev_ctrl(struct be_adapter *adapter, u32 mask)
4026 {
4027         int status = 0;
4028
4029         status = lancer_wait_idle(adapter);
4030         if (status)
4031                 return status;
4032
4033         iowrite32(mask, adapter->db + PHYSDEV_CONTROL_OFFSET);
4034
4035         return status;
4036 }
4037
4038 /* Routine to check whether dump image is present or not */
4039 bool dump_present(struct be_adapter *adapter)
4040 {
4041         u32 sliport_status = 0;
4042
4043         sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET);
4044         return !!(sliport_status & SLIPORT_STATUS_DIP_MASK);
4045 }
4046
4047 int lancer_initiate_dump(struct be_adapter *adapter)
4048 {
4049         struct device *dev = &adapter->pdev->dev;
4050         int status;
4051
4052         if (dump_present(adapter)) {
4053                 dev_info(dev, "Previous dump not cleared, not forcing dump\n");
4054                 return -EEXIST;
4055         }
4056
4057         /* give firmware reset and diagnostic dump */
4058         status = lancer_physdev_ctrl(adapter, PHYSDEV_CONTROL_FW_RESET_MASK |
4059                                      PHYSDEV_CONTROL_DD_MASK);
4060         if (status < 0) {
4061                 dev_err(dev, "FW reset failed\n");
4062                 return status;
4063         }
4064
4065         status = lancer_wait_idle(adapter);
4066         if (status)
4067                 return status;
4068
4069         if (!dump_present(adapter)) {
4070                 dev_err(dev, "FW dump not generated\n");
4071                 return -EIO;
4072         }
4073
4074         return 0;
4075 }
4076
4077 int lancer_delete_dump(struct be_adapter *adapter)
4078 {
4079         int status;
4080
4081         status = lancer_cmd_delete_object(adapter, LANCER_FW_DUMP_FILE);
4082         return be_cmd_status(status);
4083 }
4084
4085 /* Uses sync mcc */
4086 int be_cmd_enable_vf(struct be_adapter *adapter, u8 domain)
4087 {
4088         struct be_mcc_wrb *wrb;
4089         struct be_cmd_enable_disable_vf *req;
4090         int status;
4091
4092         if (BEx_chip(adapter))
4093                 return 0;
4094
4095         spin_lock_bh(&adapter->mcc_lock);
4096
4097         wrb = wrb_from_mccq(adapter);
4098         if (!wrb) {
4099                 status = -EBUSY;
4100                 goto err;
4101         }
4102
4103         req = embedded_payload(wrb);
4104
4105         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4106                                OPCODE_COMMON_ENABLE_DISABLE_VF, sizeof(*req),
4107                                wrb, NULL);
4108
4109         req->hdr.domain = domain;
4110         req->enable = 1;
4111         status = be_mcc_notify_wait(adapter);
4112 err:
4113         spin_unlock_bh(&adapter->mcc_lock);
4114         return status;
4115 }
4116
4117 int be_cmd_intr_set(struct be_adapter *adapter, bool intr_enable)
4118 {
4119         struct be_mcc_wrb *wrb;
4120         struct be_cmd_req_intr_set *req;
4121         int status;
4122
4123         if (mutex_lock_interruptible(&adapter->mbox_lock))
4124                 return -1;
4125
4126         wrb = wrb_from_mbox(adapter);
4127
4128         req = embedded_payload(wrb);
4129
4130         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4131                                OPCODE_COMMON_SET_INTERRUPT_ENABLE, sizeof(*req),
4132                                wrb, NULL);
4133
4134         req->intr_enabled = intr_enable;
4135
4136         status = be_mbox_notify_wait(adapter);
4137
4138         mutex_unlock(&adapter->mbox_lock);
4139         return status;
4140 }
4141
4142 /* Uses MBOX */
4143 int be_cmd_get_active_profile(struct be_adapter *adapter, u16 *profile_id)
4144 {
4145         struct be_cmd_req_get_active_profile *req;
4146         struct be_mcc_wrb *wrb;
4147         int status;
4148
4149         if (mutex_lock_interruptible(&adapter->mbox_lock))
4150                 return -1;
4151
4152         wrb = wrb_from_mbox(adapter);
4153         if (!wrb) {
4154                 status = -EBUSY;
4155                 goto err;
4156         }
4157
4158         req = embedded_payload(wrb);
4159
4160         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4161                                OPCODE_COMMON_GET_ACTIVE_PROFILE, sizeof(*req),
4162                                wrb, NULL);
4163
4164         status = be_mbox_notify_wait(adapter);
4165         if (!status) {
4166                 struct be_cmd_resp_get_active_profile *resp =
4167                                                         embedded_payload(wrb);
4168
4169                 *profile_id = le16_to_cpu(resp->active_profile_id);
4170         }
4171
4172 err:
4173         mutex_unlock(&adapter->mbox_lock);
4174         return status;
4175 }
4176
4177 int be_cmd_set_logical_link_config(struct be_adapter *adapter,
4178                                    int link_state, u8 domain)
4179 {
4180         struct be_mcc_wrb *wrb;
4181         struct be_cmd_req_set_ll_link *req;
4182         int status;
4183
4184         if (BEx_chip(adapter) || lancer_chip(adapter))
4185                 return -EOPNOTSUPP;
4186
4187         spin_lock_bh(&adapter->mcc_lock);
4188
4189         wrb = wrb_from_mccq(adapter);
4190         if (!wrb) {
4191                 status = -EBUSY;
4192                 goto err;
4193         }
4194
4195         req = embedded_payload(wrb);
4196
4197         be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
4198                                OPCODE_COMMON_SET_LOGICAL_LINK_CONFIG,
4199                                sizeof(*req), wrb, NULL);
4200
4201         req->hdr.version = 1;
4202         req->hdr.domain = domain;
4203
4204         if (link_state == IFLA_VF_LINK_STATE_ENABLE)
4205                 req->link_config |= 1;
4206
4207         if (link_state == IFLA_VF_LINK_STATE_AUTO)
4208                 req->link_config |= 1 << PLINK_TRACK_SHIFT;
4209
4210         status = be_mcc_notify_wait(adapter);
4211 err:
4212         spin_unlock_bh(&adapter->mcc_lock);
4213         return status;
4214 }
4215
4216 int be_roce_mcc_cmd(void *netdev_handle, void *wrb_payload,
4217                     int wrb_payload_size, u16 *cmd_status, u16 *ext_status)
4218 {
4219         struct be_adapter *adapter = netdev_priv(netdev_handle);
4220         struct be_mcc_wrb *wrb;
4221         struct be_cmd_req_hdr *hdr = (struct be_cmd_req_hdr *)wrb_payload;
4222         struct be_cmd_req_hdr *req;
4223         struct be_cmd_resp_hdr *resp;
4224         int status;
4225
4226         spin_lock_bh(&adapter->mcc_lock);
4227
4228         wrb = wrb_from_mccq(adapter);
4229         if (!wrb) {
4230                 status = -EBUSY;
4231                 goto err;
4232         }
4233         req = embedded_payload(wrb);
4234         resp = embedded_payload(wrb);
4235
4236         be_wrb_cmd_hdr_prepare(req, hdr->subsystem,
4237                                hdr->opcode, wrb_payload_size, wrb, NULL);
4238         memcpy(req, wrb_payload, wrb_payload_size);
4239         be_dws_cpu_to_le(req, wrb_payload_size);
4240
4241         status = be_mcc_notify_wait(adapter);
4242         if (cmd_status)
4243                 *cmd_status = (status & 0xffff);
4244         if (ext_status)
4245                 *ext_status = 0;
4246         memcpy(wrb_payload, resp, sizeof(*resp) + resp->response_length);
4247         be_dws_le_to_cpu(wrb_payload, sizeof(*resp) + resp->response_length);
4248 err:
4249         spin_unlock_bh(&adapter->mcc_lock);
4250         return status;
4251 }
4252 EXPORT_SYMBOL(be_roce_mcc_cmd);