2 * Copyright (C) 2005 - 2014 Emulex
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
10 * Contact Information:
11 * linux-drivers@emulex.com
15 * Costa Mesa, CA 92626
19 * The driver sends configuration and managements command requests to the
20 * firmware in the BE. These requests are communicated to the processor
21 * using Work Request Blocks (WRBs) submitted to the MCC-WRB ring or via one
22 * WRB inside a MAILBOX.
23 * The commands are serviced by the ARM processor in the BladeEngine's MPU.
32 #define MCC_WRB_EMBEDDED_MASK 1 /* bit 0 of dword 0*/
33 #define MCC_WRB_SGE_CNT_SHIFT 3 /* bits 3 - 7 of dword 0 */
34 #define MCC_WRB_SGE_CNT_MASK 0x1F /* bits 3 - 7 of dword 0 */
36 u32 embedded; /* dword 0 */
37 u32 payload_length; /* dword 1 */
38 u32 tag0; /* dword 2 */
39 u32 tag1; /* dword 3 */
40 u32 rsvd; /* dword 4 */
42 u8 embedded_payload[236]; /* used by embedded cmds */
43 struct be_sge sgl[19]; /* used by non-embedded cmds */
47 #define CQE_FLAGS_VALID_MASK (1 << 31)
48 #define CQE_FLAGS_ASYNC_MASK (1 << 30)
49 #define CQE_FLAGS_COMPLETED_MASK (1 << 28)
50 #define CQE_FLAGS_CONSUMED_MASK (1 << 27)
52 /* Completion Status */
54 MCC_STATUS_SUCCESS = 0,
55 MCC_STATUS_FAILED = 1,
56 MCC_STATUS_ILLEGAL_REQUEST = 2,
57 MCC_STATUS_ILLEGAL_FIELD = 3,
58 MCC_STATUS_INSUFFICIENT_BUFFER = 4,
59 MCC_STATUS_UNAUTHORIZED_REQUEST = 5,
60 MCC_STATUS_NOT_SUPPORTED = 66
63 #define MCC_ADDL_STS_INSUFFICIENT_RESOURCES 0x16
65 #define CQE_STATUS_COMPL_MASK 0xFFFF
66 #define CQE_STATUS_COMPL_SHIFT 0 /* bits 0 - 15 */
67 #define CQE_STATUS_EXTD_MASK 0xFFFF
68 #define CQE_STATUS_EXTD_SHIFT 16 /* bits 16 - 31 */
71 u32 status; /* dword 0 */
72 u32 tag0; /* dword 1 */
73 u32 tag1; /* dword 2 */
74 u32 flags; /* dword 3 */
77 /* When the async bit of mcc_compl is set, the last 4 bytes of
78 * mcc_compl is interpreted as follows:
80 #define ASYNC_TRAILER_EVENT_CODE_SHIFT 8 /* bits 8 - 15 */
81 #define ASYNC_TRAILER_EVENT_CODE_MASK 0xFF
82 #define ASYNC_TRAILER_EVENT_TYPE_SHIFT 16
83 #define ASYNC_TRAILER_EVENT_TYPE_MASK 0xFF
84 #define ASYNC_EVENT_CODE_LINK_STATE 0x1
85 #define ASYNC_EVENT_CODE_GRP_5 0x5
86 #define ASYNC_EVENT_QOS_SPEED 0x1
87 #define ASYNC_EVENT_COS_PRIORITY 0x2
88 #define ASYNC_EVENT_PVID_STATE 0x3
89 #define ASYNC_EVENT_CODE_QNQ 0x6
90 #define ASYNC_DEBUG_EVENT_TYPE_QNQ 1
92 struct be_async_event_trailer {
100 #define LINK_STATUS_MASK 0x1
101 #define LOGICAL_LINK_STATUS_MASK 0x2
103 /* When the event code of an async trailer is link-state, the mcc_compl
104 * must be interpreted as follows
106 struct be_async_event_link_state {
113 struct be_async_event_trailer trailer;
116 /* When the event code of an async trailer is GRP-5 and event_type is QOS_SPEED
117 * the mcc_compl must be interpreted as follows
119 struct be_async_event_grp5_qos_link_speed {
124 struct be_async_event_trailer trailer;
127 /* When the event code of an async trailer is GRP5 and event type is
128 * CoS-Priority, the mcc_compl must be interpreted as follows
130 struct be_async_event_grp5_cos_priority {
132 u8 available_priority_bmap;
133 u8 reco_default_priority;
137 struct be_async_event_trailer trailer;
140 /* When the event code of an async trailer is GRP5 and event type is
141 * PVID state, the mcc_compl must be interpreted as follows
143 struct be_async_event_grp5_pvid_state {
149 struct be_async_event_trailer trailer;
152 /* async event indicating outer VLAN tag in QnQ */
153 struct be_async_event_qnq {
154 u8 valid; /* Indicates if outer VLAN is valid */
159 struct be_async_event_trailer trailer;
162 struct be_mcc_mailbox {
163 struct be_mcc_wrb wrb;
164 struct be_mcc_compl compl;
167 #define CMD_SUBSYSTEM_COMMON 0x1
168 #define CMD_SUBSYSTEM_ETH 0x3
169 #define CMD_SUBSYSTEM_LOWLEVEL 0xb
171 #define OPCODE_COMMON_NTWK_MAC_QUERY 1
172 #define OPCODE_COMMON_NTWK_MAC_SET 2
173 #define OPCODE_COMMON_NTWK_MULTICAST_SET 3
174 #define OPCODE_COMMON_NTWK_VLAN_CONFIG 4
175 #define OPCODE_COMMON_NTWK_LINK_STATUS_QUERY 5
176 #define OPCODE_COMMON_READ_FLASHROM 6
177 #define OPCODE_COMMON_WRITE_FLASHROM 7
178 #define OPCODE_COMMON_CQ_CREATE 12
179 #define OPCODE_COMMON_EQ_CREATE 13
180 #define OPCODE_COMMON_MCC_CREATE 21
181 #define OPCODE_COMMON_SET_QOS 28
182 #define OPCODE_COMMON_MCC_CREATE_EXT 90
183 #define OPCODE_COMMON_SEEPROM_READ 30
184 #define OPCODE_COMMON_GET_CNTL_ATTRIBUTES 32
185 #define OPCODE_COMMON_NTWK_RX_FILTER 34
186 #define OPCODE_COMMON_GET_FW_VERSION 35
187 #define OPCODE_COMMON_SET_FLOW_CONTROL 36
188 #define OPCODE_COMMON_GET_FLOW_CONTROL 37
189 #define OPCODE_COMMON_SET_FRAME_SIZE 39
190 #define OPCODE_COMMON_MODIFY_EQ_DELAY 41
191 #define OPCODE_COMMON_FIRMWARE_CONFIG 42
192 #define OPCODE_COMMON_NTWK_INTERFACE_CREATE 50
193 #define OPCODE_COMMON_NTWK_INTERFACE_DESTROY 51
194 #define OPCODE_COMMON_MCC_DESTROY 53
195 #define OPCODE_COMMON_CQ_DESTROY 54
196 #define OPCODE_COMMON_EQ_DESTROY 55
197 #define OPCODE_COMMON_QUERY_FIRMWARE_CONFIG 58
198 #define OPCODE_COMMON_NTWK_PMAC_ADD 59
199 #define OPCODE_COMMON_NTWK_PMAC_DEL 60
200 #define OPCODE_COMMON_FUNCTION_RESET 61
201 #define OPCODE_COMMON_MANAGE_FAT 68
202 #define OPCODE_COMMON_ENABLE_DISABLE_BEACON 69
203 #define OPCODE_COMMON_GET_BEACON_STATE 70
204 #define OPCODE_COMMON_READ_TRANSRECV_DATA 73
205 #define OPCODE_COMMON_GET_PORT_NAME 77
206 #define OPCODE_COMMON_SET_INTERRUPT_ENABLE 89
207 #define OPCODE_COMMON_SET_FN_PRIVILEGES 100
208 #define OPCODE_COMMON_GET_PHY_DETAILS 102
209 #define OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP 103
210 #define OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES 121
211 #define OPCODE_COMMON_GET_EXT_FAT_CAPABILITES 125
212 #define OPCODE_COMMON_SET_EXT_FAT_CAPABILITES 126
213 #define OPCODE_COMMON_GET_MAC_LIST 147
214 #define OPCODE_COMMON_SET_MAC_LIST 148
215 #define OPCODE_COMMON_GET_HSW_CONFIG 152
216 #define OPCODE_COMMON_GET_FUNC_CONFIG 160
217 #define OPCODE_COMMON_GET_PROFILE_CONFIG 164
218 #define OPCODE_COMMON_SET_PROFILE_CONFIG 165
219 #define OPCODE_COMMON_GET_ACTIVE_PROFILE 167
220 #define OPCODE_COMMON_SET_HSW_CONFIG 153
221 #define OPCODE_COMMON_GET_FN_PRIVILEGES 170
222 #define OPCODE_COMMON_READ_OBJECT 171
223 #define OPCODE_COMMON_WRITE_OBJECT 172
224 #define OPCODE_COMMON_GET_IFACE_LIST 194
225 #define OPCODE_COMMON_ENABLE_DISABLE_VF 196
227 #define OPCODE_ETH_RSS_CONFIG 1
228 #define OPCODE_ETH_ACPI_CONFIG 2
229 #define OPCODE_ETH_PROMISCUOUS 3
230 #define OPCODE_ETH_GET_STATISTICS 4
231 #define OPCODE_ETH_TX_CREATE 7
232 #define OPCODE_ETH_RX_CREATE 8
233 #define OPCODE_ETH_TX_DESTROY 9
234 #define OPCODE_ETH_RX_DESTROY 10
235 #define OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG 12
236 #define OPCODE_ETH_GET_PPORT_STATS 18
238 #define OPCODE_LOWLEVEL_HOST_DDR_DMA 17
239 #define OPCODE_LOWLEVEL_LOOPBACK_TEST 18
240 #define OPCODE_LOWLEVEL_SET_LOOPBACK_MODE 19
242 struct be_cmd_req_hdr {
243 u8 opcode; /* dword 0 */
244 u8 subsystem; /* dword 0 */
245 u8 port_number; /* dword 0 */
246 u8 domain; /* dword 0 */
247 u32 timeout; /* dword 1 */
248 u32 request_length; /* dword 2 */
249 u8 version; /* dword 3 */
250 u8 rsvd[3]; /* dword 3 */
253 #define RESP_HDR_INFO_OPCODE_SHIFT 0 /* bits 0 - 7 */
254 #define RESP_HDR_INFO_SUBSYS_SHIFT 8 /* bits 8 - 15 */
255 struct be_cmd_resp_hdr {
256 u8 opcode; /* dword 0 */
257 u8 subsystem; /* dword 0 */
258 u8 rsvd[2]; /* dword 0 */
259 u8 status; /* dword 1 */
260 u8 add_status; /* dword 1 */
261 u8 rsvd1[2]; /* dword 1 */
262 u32 response_length; /* dword 2 */
263 u32 actual_resp_len; /* dword 3 */
271 /**************************
272 * BE Command definitions *
273 **************************/
275 /* Pseudo amap definition in which each bit of the actual structure is defined
276 * as a byte: used to calculate offset/shift/mask of each field */
277 struct amap_eq_context {
278 u8 cidx[13]; /* dword 0*/
279 u8 rsvd0[3]; /* dword 0*/
280 u8 epidx[13]; /* dword 0*/
281 u8 valid; /* dword 0*/
282 u8 rsvd1; /* dword 0*/
283 u8 size; /* dword 0*/
284 u8 pidx[13]; /* dword 1*/
285 u8 rsvd2[3]; /* dword 1*/
286 u8 pd[10]; /* dword 1*/
287 u8 count[3]; /* dword 1*/
288 u8 solevent; /* dword 1*/
289 u8 stalled; /* dword 1*/
290 u8 armed; /* dword 1*/
291 u8 rsvd3[4]; /* dword 2*/
292 u8 func[8]; /* dword 2*/
293 u8 rsvd4; /* dword 2*/
294 u8 delaymult[10]; /* dword 2*/
295 u8 rsvd5[2]; /* dword 2*/
296 u8 phase[2]; /* dword 2*/
297 u8 nodelay; /* dword 2*/
298 u8 rsvd6[4]; /* dword 2*/
299 u8 rsvd7[32]; /* dword 3*/
302 struct be_cmd_req_eq_create {
303 struct be_cmd_req_hdr hdr;
304 u16 num_pages; /* sword */
305 u16 rsvd0; /* sword */
306 u8 context[sizeof(struct amap_eq_context) / 8];
307 struct phys_addr pages[8];
310 struct be_cmd_resp_eq_create {
311 struct be_cmd_resp_hdr resp_hdr;
312 u16 eq_id; /* sword */
313 u16 msix_idx; /* available only in v2 */
316 /******************** Mac query ***************************/
318 MAC_ADDRESS_TYPE_STORAGE = 0x0,
319 MAC_ADDRESS_TYPE_NETWORK = 0x1,
320 MAC_ADDRESS_TYPE_PD = 0x2,
321 MAC_ADDRESS_TYPE_MANAGEMENT = 0x3
329 struct be_cmd_req_mac_query {
330 struct be_cmd_req_hdr hdr;
337 struct be_cmd_resp_mac_query {
338 struct be_cmd_resp_hdr hdr;
342 /******************** PMac Add ***************************/
343 struct be_cmd_req_pmac_add {
344 struct be_cmd_req_hdr hdr;
346 u8 mac_address[ETH_ALEN];
350 struct be_cmd_resp_pmac_add {
351 struct be_cmd_resp_hdr hdr;
355 /******************** PMac Del ***************************/
356 struct be_cmd_req_pmac_del {
357 struct be_cmd_req_hdr hdr;
362 /******************** Create CQ ***************************/
363 /* Pseudo amap definition in which each bit of the actual structure is defined
364 * as a byte: used to calculate offset/shift/mask of each field */
365 struct amap_cq_context_be {
366 u8 cidx[11]; /* dword 0*/
367 u8 rsvd0; /* dword 0*/
368 u8 coalescwm[2]; /* dword 0*/
369 u8 nodelay; /* dword 0*/
370 u8 epidx[11]; /* dword 0*/
371 u8 rsvd1; /* dword 0*/
372 u8 count[2]; /* dword 0*/
373 u8 valid; /* dword 0*/
374 u8 solevent; /* dword 0*/
375 u8 eventable; /* dword 0*/
376 u8 pidx[11]; /* dword 1*/
377 u8 rsvd2; /* dword 1*/
378 u8 pd[10]; /* dword 1*/
379 u8 eqid[8]; /* dword 1*/
380 u8 stalled; /* dword 1*/
381 u8 armed; /* dword 1*/
382 u8 rsvd3[4]; /* dword 2*/
383 u8 func[8]; /* dword 2*/
384 u8 rsvd4[20]; /* dword 2*/
385 u8 rsvd5[32]; /* dword 3*/
388 struct amap_cq_context_v2 {
389 u8 rsvd0[12]; /* dword 0*/
390 u8 coalescwm[2]; /* dword 0*/
391 u8 nodelay; /* dword 0*/
392 u8 rsvd1[12]; /* dword 0*/
393 u8 count[2]; /* dword 0*/
394 u8 valid; /* dword 0*/
395 u8 rsvd2; /* dword 0*/
396 u8 eventable; /* dword 0*/
397 u8 eqid[16]; /* dword 1*/
398 u8 rsvd3[15]; /* dword 1*/
399 u8 armed; /* dword 1*/
400 u8 rsvd4[32]; /* dword 2*/
401 u8 rsvd5[32]; /* dword 3*/
404 struct be_cmd_req_cq_create {
405 struct be_cmd_req_hdr hdr;
409 u8 context[sizeof(struct amap_cq_context_be) / 8];
410 struct phys_addr pages[8];
414 struct be_cmd_resp_cq_create {
415 struct be_cmd_resp_hdr hdr;
420 struct be_cmd_req_get_fat {
421 struct be_cmd_req_hdr hdr;
425 u32 data_buffer_size;
429 struct be_cmd_resp_get_fat {
430 struct be_cmd_resp_hdr hdr;
438 /******************** Create MCCQ ***************************/
439 /* Pseudo amap definition in which each bit of the actual structure is defined
440 * as a byte: used to calculate offset/shift/mask of each field */
441 struct amap_mcc_context_be {
456 struct amap_mcc_context_v1 {
462 u8 async_cq_valid[1];
467 struct be_cmd_req_mcc_create {
468 struct be_cmd_req_hdr hdr;
471 u8 context[sizeof(struct amap_mcc_context_be) / 8];
472 struct phys_addr pages[8];
475 struct be_cmd_req_mcc_ext_create {
476 struct be_cmd_req_hdr hdr;
479 u32 async_event_bitmap[1];
480 u8 context[sizeof(struct amap_mcc_context_v1) / 8];
481 struct phys_addr pages[8];
484 struct be_cmd_resp_mcc_create {
485 struct be_cmd_resp_hdr hdr;
490 /******************** Create TxQ ***************************/
491 #define BE_ETH_TX_RING_TYPE_STANDARD 2
492 #define BE_ULP1_NUM 1
494 struct be_cmd_req_eth_tx_create {
495 struct be_cmd_req_hdr hdr;
506 struct phys_addr pages[8];
509 struct be_cmd_resp_eth_tx_create {
510 struct be_cmd_resp_hdr hdr;
517 /******************** Create RxQ ***************************/
518 struct be_cmd_req_eth_rx_create {
519 struct be_cmd_req_hdr hdr;
523 struct phys_addr pages[2];
530 struct be_cmd_resp_eth_rx_create {
531 struct be_cmd_resp_hdr hdr;
537 /******************** Q Destroy ***************************/
538 /* Type of Queue to be destroyed */
547 struct be_cmd_req_q_destroy {
548 struct be_cmd_req_hdr hdr;
550 u16 bypass_flush; /* valid only for rx q destroy */
553 /************ I/f Create (it's actually I/f Config Create)**********/
555 /* Capability flags for the i/f */
557 BE_IF_FLAGS_RSS = 0x4,
558 BE_IF_FLAGS_PROMISCUOUS = 0x8,
559 BE_IF_FLAGS_BROADCAST = 0x10,
560 BE_IF_FLAGS_UNTAGGED = 0x20,
561 BE_IF_FLAGS_ULP = 0x40,
562 BE_IF_FLAGS_VLAN_PROMISCUOUS = 0x80,
563 BE_IF_FLAGS_VLAN = 0x100,
564 BE_IF_FLAGS_MCAST_PROMISCUOUS = 0x200,
565 BE_IF_FLAGS_PASS_L2_ERRORS = 0x400,
566 BE_IF_FLAGS_PASS_L3L4_ERRORS = 0x800,
567 BE_IF_FLAGS_MULTICAST = 0x1000
570 #define BE_IF_CAP_FLAGS_WANT (BE_IF_FLAGS_RSS | BE_IF_FLAGS_PROMISCUOUS |\
571 BE_IF_FLAGS_BROADCAST | BE_IF_FLAGS_VLAN_PROMISCUOUS |\
572 BE_IF_FLAGS_VLAN | BE_IF_FLAGS_MCAST_PROMISCUOUS |\
573 BE_IF_FLAGS_PASS_L3L4_ERRORS | BE_IF_FLAGS_MULTICAST |\
574 BE_IF_FLAGS_UNTAGGED)
576 /* An RX interface is an object with one or more MAC addresses and
577 * filtering capabilities. */
578 struct be_cmd_req_if_create {
579 struct be_cmd_req_hdr hdr;
580 u32 version; /* ignore currently */
581 u32 capability_flags;
583 u8 mac_addr[ETH_ALEN];
585 u8 pmac_invalid; /* if set, don't attach the mac addr to the i/f */
586 u32 vlan_tag; /* not used currently */
589 struct be_cmd_resp_if_create {
590 struct be_cmd_resp_hdr hdr;
595 /****** I/f Destroy(it's actually I/f Config Destroy )**********/
596 struct be_cmd_req_if_destroy {
597 struct be_cmd_req_hdr hdr;
601 /*************** HW Stats Get **********************************/
602 struct be_port_rxf_stats_v0 {
603 u32 rx_bytes_lsd; /* dword 0*/
604 u32 rx_bytes_msd; /* dword 1*/
605 u32 rx_total_frames; /* dword 2*/
606 u32 rx_unicast_frames; /* dword 3*/
607 u32 rx_multicast_frames; /* dword 4*/
608 u32 rx_broadcast_frames; /* dword 5*/
609 u32 rx_crc_errors; /* dword 6*/
610 u32 rx_alignment_symbol_errors; /* dword 7*/
611 u32 rx_pause_frames; /* dword 8*/
612 u32 rx_control_frames; /* dword 9*/
613 u32 rx_in_range_errors; /* dword 10*/
614 u32 rx_out_range_errors; /* dword 11*/
615 u32 rx_frame_too_long; /* dword 12*/
616 u32 rx_address_filtered; /* dword 13*/
617 u32 rx_vlan_filtered; /* dword 14*/
618 u32 rx_dropped_too_small; /* dword 15*/
619 u32 rx_dropped_too_short; /* dword 16*/
620 u32 rx_dropped_header_too_small; /* dword 17*/
621 u32 rx_dropped_tcp_length; /* dword 18*/
622 u32 rx_dropped_runt; /* dword 19*/
623 u32 rx_64_byte_packets; /* dword 20*/
624 u32 rx_65_127_byte_packets; /* dword 21*/
625 u32 rx_128_256_byte_packets; /* dword 22*/
626 u32 rx_256_511_byte_packets; /* dword 23*/
627 u32 rx_512_1023_byte_packets; /* dword 24*/
628 u32 rx_1024_1518_byte_packets; /* dword 25*/
629 u32 rx_1519_2047_byte_packets; /* dword 26*/
630 u32 rx_2048_4095_byte_packets; /* dword 27*/
631 u32 rx_4096_8191_byte_packets; /* dword 28*/
632 u32 rx_8192_9216_byte_packets; /* dword 29*/
633 u32 rx_ip_checksum_errs; /* dword 30*/
634 u32 rx_tcp_checksum_errs; /* dword 31*/
635 u32 rx_udp_checksum_errs; /* dword 32*/
636 u32 rx_non_rss_packets; /* dword 33*/
637 u32 rx_ipv4_packets; /* dword 34*/
638 u32 rx_ipv6_packets; /* dword 35*/
639 u32 rx_ipv4_bytes_lsd; /* dword 36*/
640 u32 rx_ipv4_bytes_msd; /* dword 37*/
641 u32 rx_ipv6_bytes_lsd; /* dword 38*/
642 u32 rx_ipv6_bytes_msd; /* dword 39*/
643 u32 rx_chute1_packets; /* dword 40*/
644 u32 rx_chute2_packets; /* dword 41*/
645 u32 rx_chute3_packets; /* dword 42*/
646 u32 rx_management_packets; /* dword 43*/
647 u32 rx_switched_unicast_packets; /* dword 44*/
648 u32 rx_switched_multicast_packets; /* dword 45*/
649 u32 rx_switched_broadcast_packets; /* dword 46*/
650 u32 tx_bytes_lsd; /* dword 47*/
651 u32 tx_bytes_msd; /* dword 48*/
652 u32 tx_unicastframes; /* dword 49*/
653 u32 tx_multicastframes; /* dword 50*/
654 u32 tx_broadcastframes; /* dword 51*/
655 u32 tx_pauseframes; /* dword 52*/
656 u32 tx_controlframes; /* dword 53*/
657 u32 tx_64_byte_packets; /* dword 54*/
658 u32 tx_65_127_byte_packets; /* dword 55*/
659 u32 tx_128_256_byte_packets; /* dword 56*/
660 u32 tx_256_511_byte_packets; /* dword 57*/
661 u32 tx_512_1023_byte_packets; /* dword 58*/
662 u32 tx_1024_1518_byte_packets; /* dword 59*/
663 u32 tx_1519_2047_byte_packets; /* dword 60*/
664 u32 tx_2048_4095_byte_packets; /* dword 61*/
665 u32 tx_4096_8191_byte_packets; /* dword 62*/
666 u32 tx_8192_9216_byte_packets; /* dword 63*/
667 u32 rx_fifo_overflow; /* dword 64*/
668 u32 rx_input_fifo_overflow; /* dword 65*/
671 struct be_rxf_stats_v0 {
672 struct be_port_rxf_stats_v0 port[2];
673 u32 rx_drops_no_pbuf; /* dword 132*/
674 u32 rx_drops_no_txpb; /* dword 133*/
675 u32 rx_drops_no_erx_descr; /* dword 134*/
676 u32 rx_drops_no_tpre_descr; /* dword 135*/
677 u32 management_rx_port_packets; /* dword 136*/
678 u32 management_rx_port_bytes; /* dword 137*/
679 u32 management_rx_port_pause_frames; /* dword 138*/
680 u32 management_rx_port_errors; /* dword 139*/
681 u32 management_tx_port_packets; /* dword 140*/
682 u32 management_tx_port_bytes; /* dword 141*/
683 u32 management_tx_port_pause; /* dword 142*/
684 u32 management_rx_port_rxfifo_overflow; /* dword 143*/
685 u32 rx_drops_too_many_frags; /* dword 144*/
686 u32 rx_drops_invalid_ring; /* dword 145*/
687 u32 forwarded_packets; /* dword 146*/
688 u32 rx_drops_mtu; /* dword 147*/
690 u32 port0_jabber_events;
691 u32 port1_jabber_events;
695 struct be_erx_stats_v0 {
696 u32 rx_drops_no_fragments[44]; /* dwordS 0 to 43*/
700 struct be_pmem_stats {
705 struct be_hw_stats_v0 {
706 struct be_rxf_stats_v0 rxf;
708 struct be_erx_stats_v0 erx;
709 struct be_pmem_stats pmem;
712 struct be_cmd_req_get_stats_v0 {
713 struct be_cmd_req_hdr hdr;
714 u8 rsvd[sizeof(struct be_hw_stats_v0)];
717 struct be_cmd_resp_get_stats_v0 {
718 struct be_cmd_resp_hdr hdr;
719 struct be_hw_stats_v0 hw_stats;
722 struct lancer_pport_stats {
725 u32 tx_unicast_packets_lo;
726 u32 tx_unicast_packets_hi;
727 u32 tx_multicast_packets_lo;
728 u32 tx_multicast_packets_hi;
729 u32 tx_broadcast_packets_lo;
730 u32 tx_broadcast_packets_hi;
733 u32 tx_unicast_bytes_lo;
734 u32 tx_unicast_bytes_hi;
735 u32 tx_multicast_bytes_lo;
736 u32 tx_multicast_bytes_hi;
737 u32 tx_broadcast_bytes_lo;
738 u32 tx_broadcast_bytes_hi;
743 u32 tx_pause_frames_lo;
744 u32 tx_pause_frames_hi;
745 u32 tx_pause_on_frames_lo;
746 u32 tx_pause_on_frames_hi;
747 u32 tx_pause_off_frames_lo;
748 u32 tx_pause_off_frames_hi;
749 u32 tx_internal_mac_errors_lo;
750 u32 tx_internal_mac_errors_hi;
751 u32 tx_control_frames_lo;
752 u32 tx_control_frames_hi;
753 u32 tx_packets_64_bytes_lo;
754 u32 tx_packets_64_bytes_hi;
755 u32 tx_packets_65_to_127_bytes_lo;
756 u32 tx_packets_65_to_127_bytes_hi;
757 u32 tx_packets_128_to_255_bytes_lo;
758 u32 tx_packets_128_to_255_bytes_hi;
759 u32 tx_packets_256_to_511_bytes_lo;
760 u32 tx_packets_256_to_511_bytes_hi;
761 u32 tx_packets_512_to_1023_bytes_lo;
762 u32 tx_packets_512_to_1023_bytes_hi;
763 u32 tx_packets_1024_to_1518_bytes_lo;
764 u32 tx_packets_1024_to_1518_bytes_hi;
765 u32 tx_packets_1519_to_2047_bytes_lo;
766 u32 tx_packets_1519_to_2047_bytes_hi;
767 u32 tx_packets_2048_to_4095_bytes_lo;
768 u32 tx_packets_2048_to_4095_bytes_hi;
769 u32 tx_packets_4096_to_8191_bytes_lo;
770 u32 tx_packets_4096_to_8191_bytes_hi;
771 u32 tx_packets_8192_to_9216_bytes_lo;
772 u32 tx_packets_8192_to_9216_bytes_hi;
773 u32 tx_lso_packets_lo;
774 u32 tx_lso_packets_hi;
777 u32 rx_unicast_packets_lo;
778 u32 rx_unicast_packets_hi;
779 u32 rx_multicast_packets_lo;
780 u32 rx_multicast_packets_hi;
781 u32 rx_broadcast_packets_lo;
782 u32 rx_broadcast_packets_hi;
785 u32 rx_unicast_bytes_lo;
786 u32 rx_unicast_bytes_hi;
787 u32 rx_multicast_bytes_lo;
788 u32 rx_multicast_bytes_hi;
789 u32 rx_broadcast_bytes_lo;
790 u32 rx_broadcast_bytes_hi;
791 u32 rx_unknown_protos;
792 u32 rsvd_69; /* Word 69 is reserved */
797 u32 rx_crc_errors_lo;
798 u32 rx_crc_errors_hi;
799 u32 rx_alignment_errors_lo;
800 u32 rx_alignment_errors_hi;
801 u32 rx_symbol_errors_lo;
802 u32 rx_symbol_errors_hi;
803 u32 rx_pause_frames_lo;
804 u32 rx_pause_frames_hi;
805 u32 rx_pause_on_frames_lo;
806 u32 rx_pause_on_frames_hi;
807 u32 rx_pause_off_frames_lo;
808 u32 rx_pause_off_frames_hi;
809 u32 rx_frames_too_long_lo;
810 u32 rx_frames_too_long_hi;
811 u32 rx_internal_mac_errors_lo;
812 u32 rx_internal_mac_errors_hi;
813 u32 rx_undersize_packets;
814 u32 rx_oversize_packets;
815 u32 rx_fragment_packets;
817 u32 rx_control_frames_lo;
818 u32 rx_control_frames_hi;
819 u32 rx_control_frames_unknown_opcode_lo;
820 u32 rx_control_frames_unknown_opcode_hi;
821 u32 rx_in_range_errors;
822 u32 rx_out_of_range_errors;
823 u32 rx_address_filtered;
824 u32 rx_vlan_filtered;
825 u32 rx_dropped_too_small;
826 u32 rx_dropped_too_short;
827 u32 rx_dropped_header_too_small;
828 u32 rx_dropped_invalid_tcp_length;
830 u32 rx_ip_checksum_errors;
831 u32 rx_tcp_checksum_errors;
832 u32 rx_udp_checksum_errors;
833 u32 rx_non_rss_packets;
835 u32 rx_ipv4_packets_lo;
836 u32 rx_ipv4_packets_hi;
837 u32 rx_ipv6_packets_lo;
838 u32 rx_ipv6_packets_hi;
839 u32 rx_ipv4_bytes_lo;
840 u32 rx_ipv4_bytes_hi;
841 u32 rx_ipv6_bytes_lo;
842 u32 rx_ipv6_bytes_hi;
843 u32 rx_nic_packets_lo;
844 u32 rx_nic_packets_hi;
845 u32 rx_tcp_packets_lo;
846 u32 rx_tcp_packets_hi;
847 u32 rx_iscsi_packets_lo;
848 u32 rx_iscsi_packets_hi;
849 u32 rx_management_packets_lo;
850 u32 rx_management_packets_hi;
851 u32 rx_switched_unicast_packets_lo;
852 u32 rx_switched_unicast_packets_hi;
853 u32 rx_switched_multicast_packets_lo;
854 u32 rx_switched_multicast_packets_hi;
855 u32 rx_switched_broadcast_packets_lo;
856 u32 rx_switched_broadcast_packets_hi;
859 u32 rx_fifo_overflow;
860 u32 rx_input_fifo_overflow;
861 u32 rx_drops_too_many_frags_lo;
862 u32 rx_drops_too_many_frags_hi;
863 u32 rx_drops_invalid_queue;
867 u32 rx_packets_64_bytes_lo;
868 u32 rx_packets_64_bytes_hi;
869 u32 rx_packets_65_to_127_bytes_lo;
870 u32 rx_packets_65_to_127_bytes_hi;
871 u32 rx_packets_128_to_255_bytes_lo;
872 u32 rx_packets_128_to_255_bytes_hi;
873 u32 rx_packets_256_to_511_bytes_lo;
874 u32 rx_packets_256_to_511_bytes_hi;
875 u32 rx_packets_512_to_1023_bytes_lo;
876 u32 rx_packets_512_to_1023_bytes_hi;
877 u32 rx_packets_1024_to_1518_bytes_lo;
878 u32 rx_packets_1024_to_1518_bytes_hi;
879 u32 rx_packets_1519_to_2047_bytes_lo;
880 u32 rx_packets_1519_to_2047_bytes_hi;
881 u32 rx_packets_2048_to_4095_bytes_lo;
882 u32 rx_packets_2048_to_4095_bytes_hi;
883 u32 rx_packets_4096_to_8191_bytes_lo;
884 u32 rx_packets_4096_to_8191_bytes_hi;
885 u32 rx_packets_8192_to_9216_bytes_lo;
886 u32 rx_packets_8192_to_9216_bytes_hi;
889 struct pport_stats_params {
895 struct lancer_cmd_req_pport_stats {
896 struct be_cmd_req_hdr hdr;
898 struct pport_stats_params params;
899 u8 rsvd[sizeof(struct lancer_pport_stats)];
903 struct lancer_cmd_resp_pport_stats {
904 struct be_cmd_resp_hdr hdr;
905 struct lancer_pport_stats pport_stats;
908 static inline struct lancer_pport_stats*
909 pport_stats_from_cmd(struct be_adapter *adapter)
911 struct lancer_cmd_resp_pport_stats *cmd = adapter->stats_cmd.va;
912 return &cmd->pport_stats;
915 struct be_cmd_req_get_cntl_addnl_attribs {
916 struct be_cmd_req_hdr hdr;
920 struct be_cmd_resp_get_cntl_addnl_attribs {
921 struct be_cmd_resp_hdr hdr;
925 u8 on_die_temperature; /* in degrees centigrade*/
929 struct be_cmd_req_vlan_config {
930 struct be_cmd_req_hdr hdr;
938 /******************* RX FILTER ******************************/
939 #define BE_MAX_MC 64 /* set mcast promisc if > 64 */
944 struct be_cmd_req_rx_filter {
945 struct be_cmd_req_hdr hdr;
946 u32 global_flags_mask;
952 struct macaddr mcast_mac[BE_MAX_MC];
955 /******************** Link Status Query *******************/
956 struct be_cmd_req_link_status {
957 struct be_cmd_req_hdr hdr;
962 PHY_LINK_DUPLEX_NONE = 0x0,
963 PHY_LINK_DUPLEX_HALF = 0x1,
964 PHY_LINK_DUPLEX_FULL = 0x2
968 PHY_LINK_SPEED_ZERO = 0x0, /* => No link */
969 PHY_LINK_SPEED_10MBPS = 0x1,
970 PHY_LINK_SPEED_100MBPS = 0x2,
971 PHY_LINK_SPEED_1GBPS = 0x3,
972 PHY_LINK_SPEED_10GBPS = 0x4,
973 PHY_LINK_SPEED_20GBPS = 0x5,
974 PHY_LINK_SPEED_25GBPS = 0x6,
975 PHY_LINK_SPEED_40GBPS = 0x7
978 struct be_cmd_resp_link_status {
979 struct be_cmd_resp_hdr hdr;
987 u8 logical_link_status;
991 /******************** Port Identification ***************************/
992 /* Identifies the type of port attached to NIC */
993 struct be_cmd_req_port_type {
994 struct be_cmd_req_hdr hdr;
1004 struct be_cmd_resp_port_type {
1005 struct be_cmd_resp_hdr hdr;
1028 /******************** Get FW Version *******************/
1029 struct be_cmd_req_get_fw_version {
1030 struct be_cmd_req_hdr hdr;
1031 u8 rsvd0[FW_VER_LEN];
1032 u8 rsvd1[FW_VER_LEN];
1035 struct be_cmd_resp_get_fw_version {
1036 struct be_cmd_resp_hdr hdr;
1037 u8 firmware_version_string[FW_VER_LEN];
1038 u8 fw_on_flash_version_string[FW_VER_LEN];
1041 /******************** Set Flow Contrl *******************/
1042 struct be_cmd_req_set_flow_control {
1043 struct be_cmd_req_hdr hdr;
1044 u16 tx_flow_control;
1045 u16 rx_flow_control;
1048 /******************** Get Flow Contrl *******************/
1049 struct be_cmd_req_get_flow_control {
1050 struct be_cmd_req_hdr hdr;
1054 struct be_cmd_resp_get_flow_control {
1055 struct be_cmd_resp_hdr hdr;
1056 u16 tx_flow_control;
1057 u16 rx_flow_control;
1060 /******************** Modify EQ Delay *******************/
1064 u32 delay_multiplier;
1067 struct be_cmd_req_modify_eq_delay {
1068 struct be_cmd_req_hdr hdr;
1070 struct be_set_eqd set_eqd[MAX_EVT_QS];
1073 struct be_cmd_resp_modify_eq_delay {
1074 struct be_cmd_resp_hdr hdr;
1078 /******************** Get FW Config *******************/
1079 /* The HW can come up in either of the following multi-channel modes
1080 * based on the skew/IPL.
1082 #define RDMA_ENABLED 0x4
1083 #define FLEX10_MODE 0x400
1084 #define VNIC_MODE 0x20000
1085 #define UMC_ENABLED 0x1000000
1086 struct be_cmd_req_query_fw_cfg {
1087 struct be_cmd_req_hdr hdr;
1091 struct be_cmd_resp_query_fw_cfg {
1092 struct be_cmd_resp_hdr hdr;
1093 u32 be_config_number;
1101 /******************** RSS Config ****************************************/
1102 /* RSS type Input parameters used to compute RX hash
1103 * RSS_ENABLE_IPV4 SRC IPv4, DST IPv4
1104 * RSS_ENABLE_TCP_IPV4 SRC IPv4, DST IPv4, TCP SRC PORT, TCP DST PORT
1105 * RSS_ENABLE_IPV6 SRC IPv6, DST IPv6
1106 * RSS_ENABLE_TCP_IPV6 SRC IPv6, DST IPv6, TCP SRC PORT, TCP DST PORT
1107 * RSS_ENABLE_UDP_IPV4 SRC IPv4, DST IPv4, UDP SRC PORT, UDP DST PORT
1108 * RSS_ENABLE_UDP_IPV6 SRC IPv6, DST IPv6, UDP SRC PORT, UDP DST PORT
1110 * When multiple RSS types are enabled, HW picks the best hash policy
1111 * based on the type of the received packet.
1113 #define RSS_ENABLE_NONE 0x0
1114 #define RSS_ENABLE_IPV4 0x1
1115 #define RSS_ENABLE_TCP_IPV4 0x2
1116 #define RSS_ENABLE_IPV6 0x4
1117 #define RSS_ENABLE_TCP_IPV6 0x8
1118 #define RSS_ENABLE_UDP_IPV4 0x10
1119 #define RSS_ENABLE_UDP_IPV6 0x20
1121 #define L3_RSS_FLAGS (RXH_IP_DST | RXH_IP_SRC)
1122 #define L4_RSS_FLAGS (RXH_L4_B_0_1 | RXH_L4_B_2_3)
1124 struct be_cmd_req_rss_config {
1125 struct be_cmd_req_hdr hdr;
1128 u16 cpu_table_size_log2;
1135 /******************** Port Beacon ***************************/
1137 #define BEACON_STATE_ENABLED 0x1
1138 #define BEACON_STATE_DISABLED 0x0
1140 struct be_cmd_req_enable_disable_beacon {
1141 struct be_cmd_req_hdr hdr;
1148 struct be_cmd_resp_enable_disable_beacon {
1149 struct be_cmd_resp_hdr resp_hdr;
1153 struct be_cmd_req_get_beacon_state {
1154 struct be_cmd_req_hdr hdr;
1160 struct be_cmd_resp_get_beacon_state {
1161 struct be_cmd_resp_hdr resp_hdr;
1166 /****************** Firmware Flash ******************/
1167 struct flashrom_params {
1174 struct be_cmd_write_flashrom {
1175 struct be_cmd_req_hdr hdr;
1176 struct flashrom_params params;
1181 /* cmd to read flash crc */
1182 struct be_cmd_read_flash_crc {
1183 struct be_cmd_req_hdr hdr;
1184 struct flashrom_params params;
1188 /**************** Lancer Firmware Flash ************/
1189 struct amap_lancer_write_obj_context {
1190 u8 write_length[24];
1195 struct lancer_cmd_req_write_object {
1196 struct be_cmd_req_hdr hdr;
1197 u8 context[sizeof(struct amap_lancer_write_obj_context) / 8];
1199 u8 object_name[104];
1200 u32 descriptor_count;
1206 #define LANCER_NO_RESET_NEEDED 0x00
1207 #define LANCER_FW_RESET_NEEDED 0x02
1208 struct lancer_cmd_resp_write_object {
1213 u8 additional_status;
1216 u32 actual_resp_len;
1217 u32 actual_write_len;
1222 /************************ Lancer Read FW info **************/
1223 #define LANCER_READ_FILE_CHUNK (32*1024)
1224 #define LANCER_READ_FILE_EOF_MASK 0x80000000
1226 #define LANCER_FW_DUMP_FILE "/dbg/dump.bin"
1227 #define LANCER_VPD_PF_FILE "/vpd/ntr_pf.vpd"
1228 #define LANCER_VPD_VF_FILE "/vpd/ntr_vf.vpd"
1230 struct lancer_cmd_req_read_object {
1231 struct be_cmd_req_hdr hdr;
1232 u32 desired_read_len;
1234 u8 object_name[104];
1235 u32 descriptor_count;
1241 struct lancer_cmd_resp_read_object {
1246 u8 additional_status;
1249 u32 actual_resp_len;
1250 u32 actual_read_len;
1254 /************************ WOL *******************************/
1255 struct be_cmd_req_acpi_wol_magic_config{
1256 struct be_cmd_req_hdr hdr;
1262 struct be_cmd_req_acpi_wol_magic_config_v1 {
1263 struct be_cmd_req_hdr hdr;
1272 struct be_cmd_resp_acpi_wol_magic_config_v1 {
1273 struct be_cmd_resp_hdr hdr;
1280 #define BE_GET_WOL_CAP 2
1282 #define BE_WOL_CAP 0x1
1283 #define BE_PME_D0_CAP 0x8
1284 #define BE_PME_D1_CAP 0x10
1285 #define BE_PME_D2_CAP 0x20
1286 #define BE_PME_D3HOT_CAP 0x40
1287 #define BE_PME_D3COLD_CAP 0x80
1289 /********************** LoopBack test *********************/
1290 struct be_cmd_req_loopback_test {
1291 struct be_cmd_req_hdr hdr;
1300 struct be_cmd_resp_loopback_test {
1301 struct be_cmd_resp_hdr resp_hdr;
1309 struct be_cmd_req_set_lmode {
1310 struct be_cmd_req_hdr hdr;
1317 struct be_cmd_resp_set_lmode {
1318 struct be_cmd_resp_hdr resp_hdr;
1322 /********************** DDR DMA test *********************/
1323 struct be_cmd_req_ddrdma_test {
1324 struct be_cmd_req_hdr hdr;
1332 struct be_cmd_resp_ddrdma_test {
1333 struct be_cmd_resp_hdr hdr;
1341 /*********************** SEEPROM Read ***********************/
1343 #define BE_READ_SEEPROM_LEN 1024
1344 struct be_cmd_req_seeprom_read {
1345 struct be_cmd_req_hdr hdr;
1346 u8 rsvd0[BE_READ_SEEPROM_LEN];
1349 struct be_cmd_resp_seeprom_read {
1350 struct be_cmd_req_hdr hdr;
1351 u8 seeprom_data[BE_READ_SEEPROM_LEN];
1355 PHY_TYPE_CX4_10GB = 0,
1358 PHY_TYPE_SFP_PLUS_10GB,
1361 PHY_TYPE_BASET_10GB,
1365 PHY_TYPE_DISABLED = 255
1368 #define BE_SUPPORTED_SPEED_NONE 0
1369 #define BE_SUPPORTED_SPEED_10MBPS 1
1370 #define BE_SUPPORTED_SPEED_100MBPS 2
1371 #define BE_SUPPORTED_SPEED_1GBPS 4
1372 #define BE_SUPPORTED_SPEED_10GBPS 8
1374 #define BE_AN_EN 0x2
1375 #define BE_PAUSE_SYM_EN 0x80
1377 /* MAC speed valid values */
1378 #define SPEED_DEFAULT 0x0
1379 #define SPEED_FORCED_10GB 0x1
1380 #define SPEED_FORCED_1GB 0x2
1381 #define SPEED_AUTONEG_10GB 0x3
1382 #define SPEED_AUTONEG_1GB 0x4
1383 #define SPEED_AUTONEG_100MB 0x5
1384 #define SPEED_AUTONEG_10GB_1GB 0x6
1385 #define SPEED_AUTONEG_10GB_1GB_100MB 0x7
1386 #define SPEED_AUTONEG_1GB_100MB 0x8
1387 #define SPEED_AUTONEG_10MB 0x9
1388 #define SPEED_AUTONEG_1GB_100MB_10MB 0xa
1389 #define SPEED_AUTONEG_100MB_10MB 0xb
1390 #define SPEED_FORCED_100MB 0xc
1391 #define SPEED_FORCED_10MB 0xd
1393 struct be_cmd_req_get_phy_info {
1394 struct be_cmd_req_hdr hdr;
1398 struct be_phy_info {
1402 u16 ext_phy_details;
1404 u16 auto_speeds_supported;
1405 u16 fixed_speeds_supported;
1409 struct be_cmd_resp_get_phy_info {
1410 struct be_cmd_req_hdr hdr;
1411 struct be_phy_info phy_info;
1414 /*********************** Set QOS ***********************/
1416 #define BE_QOS_BITS_NIC 1
1418 struct be_cmd_req_set_qos {
1419 struct be_cmd_req_hdr hdr;
1425 struct be_cmd_resp_set_qos {
1426 struct be_cmd_resp_hdr hdr;
1430 /*********************** Controller Attributes ***********************/
1431 struct be_cmd_req_cntl_attribs {
1432 struct be_cmd_req_hdr hdr;
1435 struct be_cmd_resp_cntl_attribs {
1436 struct be_cmd_resp_hdr hdr;
1437 struct mgmt_controller_attrib attribs;
1440 /*********************** Set driver function ***********************/
1441 #define CAPABILITY_SW_TIMESTAMPS 2
1442 #define CAPABILITY_BE3_NATIVE_ERX_API 4
1444 struct be_cmd_req_set_func_cap {
1445 struct be_cmd_req_hdr hdr;
1446 u32 valid_cap_flags;
1451 struct be_cmd_resp_set_func_cap {
1452 struct be_cmd_resp_hdr hdr;
1453 u32 valid_cap_flags;
1458 /*********************** Function Privileges ***********************/
1460 BE_PRIV_DEFAULT = 0x1,
1461 BE_PRIV_LNKQUERY = 0x2,
1462 BE_PRIV_LNKSTATS = 0x4,
1463 BE_PRIV_LNKMGMT = 0x8,
1464 BE_PRIV_LNKDIAG = 0x10,
1465 BE_PRIV_UTILQUERY = 0x20,
1466 BE_PRIV_FILTMGMT = 0x40,
1467 BE_PRIV_IFACEMGMT = 0x80,
1468 BE_PRIV_VHADM = 0x100,
1469 BE_PRIV_DEVCFG = 0x200,
1470 BE_PRIV_DEVSEC = 0x400
1472 #define MAX_PRIVILEGES (BE_PRIV_VHADM | BE_PRIV_DEVCFG | \
1474 #define MIN_PRIVILEGES BE_PRIV_DEFAULT
1476 struct be_cmd_priv_map {
1482 struct be_cmd_req_get_fn_privileges {
1483 struct be_cmd_req_hdr hdr;
1487 struct be_cmd_resp_get_fn_privileges {
1488 struct be_cmd_resp_hdr hdr;
1492 struct be_cmd_req_set_fn_privileges {
1493 struct be_cmd_req_hdr hdr;
1494 u32 privileges; /* Used by BE3, SH-R */
1495 u32 privileges_lancer; /* Used by Lancer */
1498 /******************** GET/SET_MACLIST **************************/
1499 #define BE_MAX_MAC 64
1500 struct be_cmd_req_get_mac_list {
1501 struct be_cmd_req_hdr hdr;
1509 struct get_list_macaddr {
1516 } __packed s_mac_id;
1517 } __packed mac_addr_id;
1520 struct be_cmd_resp_get_mac_list {
1521 struct be_cmd_resp_hdr hdr;
1522 struct get_list_macaddr fd_macaddr; /* Factory default mac */
1523 struct get_list_macaddr macid_macaddr; /* soft mac */
1525 u8 pseudo_mac_count;
1528 /* perm override mac */
1529 struct get_list_macaddr macaddr_list[BE_MAX_MAC];
1532 struct be_cmd_req_set_mac_list {
1533 struct be_cmd_req_hdr hdr;
1537 struct macaddr mac[BE_MAX_MAC];
1540 /*********************** HSW Config ***********************/
1541 #define PORT_FWD_TYPE_VEPA 0x3
1542 #define PORT_FWD_TYPE_VEB 0x2
1544 struct amap_set_hsw_context {
1545 u8 interface_id[16];
1550 u8 port_fwd_type[3];
1558 struct be_cmd_req_set_hsw_config {
1559 struct be_cmd_req_hdr hdr;
1560 u8 context[sizeof(struct amap_set_hsw_context) / 8];
1563 struct be_cmd_resp_set_hsw_config {
1564 struct be_cmd_resp_hdr hdr;
1568 struct amap_get_hsw_req_context {
1569 u8 interface_id[16];
1575 struct amap_get_hsw_resp_context {
1577 u8 port_fwd_type[3];
1585 struct be_cmd_req_get_hsw_config {
1586 struct be_cmd_req_hdr hdr;
1587 u8 context[sizeof(struct amap_get_hsw_req_context) / 8];
1590 struct be_cmd_resp_get_hsw_config {
1591 struct be_cmd_resp_hdr hdr;
1592 u8 context[sizeof(struct amap_get_hsw_resp_context) / 8];
1596 /******************* get port names ***************/
1597 struct be_cmd_req_get_port_name {
1598 struct be_cmd_req_hdr hdr;
1602 struct be_cmd_resp_get_port_name {
1603 struct be_cmd_req_hdr hdr;
1607 /*************** HW Stats Get v1 **********************************/
1608 #define BE_TXP_SW_SZ 48
1609 struct be_port_rxf_stats_v1 {
1612 u32 rx_alignment_symbol_errors;
1613 u32 rx_pause_frames;
1614 u32 rx_priority_pause_frames;
1615 u32 rx_control_frames;
1616 u32 rx_in_range_errors;
1617 u32 rx_out_range_errors;
1618 u32 rx_frame_too_long;
1619 u32 rx_address_filtered;
1620 u32 rx_dropped_too_small;
1621 u32 rx_dropped_too_short;
1622 u32 rx_dropped_header_too_small;
1623 u32 rx_dropped_tcp_length;
1624 u32 rx_dropped_runt;
1626 u32 rx_ip_checksum_errs;
1627 u32 rx_tcp_checksum_errs;
1628 u32 rx_udp_checksum_errs;
1630 u32 rx_switched_unicast_packets;
1631 u32 rx_switched_multicast_packets;
1632 u32 rx_switched_broadcast_packets;
1635 u32 tx_priority_pauseframes;
1636 u32 tx_controlframes;
1638 u32 rxpp_fifo_overflow_drop;
1639 u32 rx_input_fifo_overflow_drop;
1640 u32 pmem_fifo_overflow_drop;
1646 struct be_rxf_stats_v1 {
1647 struct be_port_rxf_stats_v1 port[4];
1649 u32 rx_drops_no_pbuf;
1650 u32 rx_drops_no_txpb;
1651 u32 rx_drops_no_erx_descr;
1652 u32 rx_drops_no_tpre_descr;
1654 u32 rx_drops_too_many_frags;
1655 u32 rx_drops_invalid_ring;
1656 u32 forwarded_packets;
1661 struct be_erx_stats_v1 {
1662 u32 rx_drops_no_fragments[68]; /* dwordS 0 to 67*/
1666 struct be_port_rxf_stats_v2 {
1668 u32 roce_bytes_received_lsd;
1669 u32 roce_bytes_received_msd;
1671 u32 roce_frames_received;
1673 u32 rx_alignment_symbol_errors;
1674 u32 rx_pause_frames;
1675 u32 rx_priority_pause_frames;
1676 u32 rx_control_frames;
1677 u32 rx_in_range_errors;
1678 u32 rx_out_range_errors;
1679 u32 rx_frame_too_long;
1680 u32 rx_address_filtered;
1681 u32 rx_dropped_too_small;
1682 u32 rx_dropped_too_short;
1683 u32 rx_dropped_header_too_small;
1684 u32 rx_dropped_tcp_length;
1685 u32 rx_dropped_runt;
1687 u32 rx_ip_checksum_errs;
1688 u32 rx_tcp_checksum_errs;
1689 u32 rx_udp_checksum_errs;
1691 u32 rx_switched_unicast_packets;
1692 u32 rx_switched_multicast_packets;
1693 u32 rx_switched_broadcast_packets;
1696 u32 tx_priority_pauseframes;
1697 u32 tx_controlframes;
1699 u32 rxpp_fifo_overflow_drop;
1700 u32 rx_input_fifo_overflow_drop;
1701 u32 pmem_fifo_overflow_drop;
1704 u32 rx_drops_payload_size;
1705 u32 rx_drops_clipped_header;
1707 u32 roce_drops_payload_len;
1712 struct be_rxf_stats_v2 {
1713 struct be_port_rxf_stats_v2 port[4];
1715 u32 rx_drops_no_pbuf;
1716 u32 rx_drops_no_txpb;
1717 u32 rx_drops_no_erx_descr;
1718 u32 rx_drops_no_tpre_descr;
1720 u32 rx_drops_too_many_frags;
1721 u32 rx_drops_invalid_ring;
1722 u32 forwarded_packets;
1727 struct be_hw_stats_v1 {
1728 struct be_rxf_stats_v1 rxf;
1729 u32 rsvd0[BE_TXP_SW_SZ];
1730 struct be_erx_stats_v1 erx;
1731 struct be_pmem_stats pmem;
1735 struct be_cmd_req_get_stats_v1 {
1736 struct be_cmd_req_hdr hdr;
1737 u8 rsvd[sizeof(struct be_hw_stats_v1)];
1740 struct be_cmd_resp_get_stats_v1 {
1741 struct be_cmd_resp_hdr hdr;
1742 struct be_hw_stats_v1 hw_stats;
1745 struct be_erx_stats_v2 {
1746 u32 rx_drops_no_fragments[136]; /* dwordS 0 to 135*/
1750 struct be_hw_stats_v2 {
1751 struct be_rxf_stats_v2 rxf;
1752 u32 rsvd0[BE_TXP_SW_SZ];
1753 struct be_erx_stats_v2 erx;
1754 struct be_pmem_stats pmem;
1758 struct be_cmd_req_get_stats_v2 {
1759 struct be_cmd_req_hdr hdr;
1760 u8 rsvd[sizeof(struct be_hw_stats_v2)];
1763 struct be_cmd_resp_get_stats_v2 {
1764 struct be_cmd_resp_hdr hdr;
1765 struct be_hw_stats_v2 hw_stats;
1768 /************** get fat capabilites *******************/
1769 #define MAX_MODULES 27
1772 #define FW_LOG_LEVEL_DEFAULT 48
1773 #define FW_LOG_LEVEL_FATAL 64
1775 struct ext_fat_mode {
1783 struct ext_fat_modules {
1787 struct ext_fat_mode trace_lvl[MAX_MODES];
1790 struct be_fat_conf_params {
1791 u32 max_log_entries;
1799 struct ext_fat_modules module[MAX_MODULES];
1802 struct be_cmd_req_get_ext_fat_caps {
1803 struct be_cmd_req_hdr hdr;
1807 struct be_cmd_resp_get_ext_fat_caps {
1808 struct be_cmd_resp_hdr hdr;
1809 struct be_fat_conf_params get_params;
1812 struct be_cmd_req_set_ext_fat_caps {
1813 struct be_cmd_req_hdr hdr;
1814 struct be_fat_conf_params set_params;
1817 #define RESOURCE_DESC_SIZE_V0 72
1818 #define RESOURCE_DESC_SIZE_V1 88
1819 #define PCIE_RESOURCE_DESC_TYPE_V0 0x40
1820 #define NIC_RESOURCE_DESC_TYPE_V0 0x41
1821 #define PCIE_RESOURCE_DESC_TYPE_V1 0x50
1822 #define NIC_RESOURCE_DESC_TYPE_V1 0x51
1823 #define PORT_RESOURCE_DESC_TYPE_V1 0x55
1824 #define MAX_RESOURCE_DESC 264
1826 /* QOS unit number */
1833 struct be_res_desc_hdr {
1838 struct be_pcie_res_desc {
1839 struct be_res_desc_hdr hdr;
1855 struct be_nic_res_desc {
1856 struct be_res_desc_hdr hdr;
1863 u16 unicast_mac_count;
1867 u16 mcast_mac_count;
1887 /************ Multi-Channel type ***********/
1898 struct be_port_res_desc {
1899 struct be_res_desc_hdr hdr;
1908 /* Is BE in a multi-channel mode */
1909 static inline bool be_is_mc(struct be_adapter *adapter)
1911 return adapter->mc_type > MC_NONE;
1914 struct be_cmd_req_get_func_config {
1915 struct be_cmd_req_hdr hdr;
1918 struct be_cmd_resp_get_func_config {
1919 struct be_cmd_resp_hdr hdr;
1921 u8 func_param[MAX_RESOURCE_DESC * RESOURCE_DESC_SIZE_V1];
1924 #define ACTIVE_PROFILE_TYPE 0x2
1925 struct be_cmd_req_get_profile_config {
1926 struct be_cmd_req_hdr hdr;
1932 struct be_cmd_resp_get_profile_config {
1933 struct be_cmd_resp_hdr hdr;
1935 u8 func_param[MAX_RESOURCE_DESC * RESOURCE_DESC_SIZE_V1];
1938 struct be_cmd_req_set_profile_config {
1939 struct be_cmd_req_hdr hdr;
1942 struct be_nic_res_desc nic_desc;
1945 struct be_cmd_resp_set_profile_config {
1946 struct be_cmd_resp_hdr hdr;
1949 struct be_cmd_req_get_active_profile {
1950 struct be_cmd_req_hdr hdr;
1954 struct be_cmd_resp_get_active_profile {
1955 struct be_cmd_resp_hdr hdr;
1956 u16 active_profile_id;
1957 u16 next_profile_id;
1960 struct be_cmd_enable_disable_vf {
1961 struct be_cmd_req_hdr hdr;
1966 struct be_cmd_req_intr_set {
1967 struct be_cmd_req_hdr hdr;
1972 static inline bool check_privilege(struct be_adapter *adapter, u32 flags)
1974 return flags & adapter->cmd_privileges ? true : false;
1977 /************** Get IFACE LIST *******************/
1984 struct be_cmd_req_get_iface_list {
1985 struct be_cmd_req_hdr hdr;
1988 struct be_cmd_resp_get_iface_list {
1989 struct be_cmd_req_hdr hdr;
1991 struct be_if_desc if_desc;
1994 int be_pci_fnum_get(struct be_adapter *adapter);
1995 int be_fw_wait_ready(struct be_adapter *adapter);
1996 int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
1997 bool permanent, u32 if_handle, u32 pmac_id);
1998 int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr, u32 if_id,
1999 u32 *pmac_id, u32 domain);
2000 int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, int pmac_id,
2002 int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
2003 u32 *if_handle, u32 domain);
2004 int be_cmd_if_destroy(struct be_adapter *adapter, int if_handle, u32 domain);
2005 int be_cmd_eq_create(struct be_adapter *adapter, struct be_eq_obj *eqo);
2006 int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq,
2007 struct be_queue_info *eq, bool no_delay,
2008 int num_cqe_dma_coalesce);
2009 int be_cmd_mccq_create(struct be_adapter *adapter, struct be_queue_info *mccq,
2010 struct be_queue_info *cq);
2011 int be_cmd_txq_create(struct be_adapter *adapter, struct be_tx_obj *txo);
2012 int be_cmd_rxq_create(struct be_adapter *adapter, struct be_queue_info *rxq,
2013 u16 cq_id, u16 frag_size, u32 if_id, u32 rss, u8 *rss_id);
2014 int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
2016 int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q);
2017 int be_cmd_link_status_query(struct be_adapter *adapter, u16 *link_speed,
2018 u8 *link_status, u32 dom);
2019 int be_cmd_reset(struct be_adapter *adapter);
2020 int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd);
2021 int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
2022 struct be_dma_mem *nonemb_cmd);
2023 int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver,
2025 int be_cmd_modify_eqd(struct be_adapter *adapter, struct be_set_eqd *, int num);
2026 int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
2027 u32 num, bool promiscuous);
2028 int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 status);
2029 int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc);
2030 int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc);
2031 int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num,
2032 u32 *function_mode, u32 *function_caps, u16 *asic_rev);
2033 int be_cmd_reset_function(struct be_adapter *adapter);
2034 int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable,
2035 u32 rss_hash_opts, u16 table_size);
2036 int be_process_mcc(struct be_adapter *adapter);
2037 int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num, u8 beacon,
2038 u8 status, u8 state);
2039 int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num,
2041 int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
2042 u32 flash_oper, u32 flash_opcode, u32 buf_size);
2043 int lancer_cmd_write_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
2044 u32 data_size, u32 data_offset,
2045 const char *obj_name, u32 *data_written,
2046 u8 *change_status, u8 *addn_status);
2047 int lancer_cmd_read_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
2048 u32 data_size, u32 data_offset, const char *obj_name,
2049 u32 *data_read, u32 *eof, u8 *addn_status);
2050 int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
2052 int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
2053 struct be_dma_mem *nonemb_cmd);
2054 int be_cmd_fw_init(struct be_adapter *adapter);
2055 int be_cmd_fw_clean(struct be_adapter *adapter);
2056 void be_async_mcc_enable(struct be_adapter *adapter);
2057 void be_async_mcc_disable(struct be_adapter *adapter);
2058 int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
2059 u32 loopback_type, u32 pkt_size, u32 num_pkts,
2061 int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern, u32 byte_cnt,
2062 struct be_dma_mem *cmd);
2063 int be_cmd_get_seeprom_data(struct be_adapter *adapter,
2064 struct be_dma_mem *nonemb_cmd);
2065 int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
2066 u8 loopback_type, u8 enable);
2067 int be_cmd_get_phy_info(struct be_adapter *adapter);
2068 int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain);
2069 void be_detect_error(struct be_adapter *adapter);
2070 int be_cmd_get_die_temperature(struct be_adapter *adapter);
2071 int be_cmd_get_cntl_attributes(struct be_adapter *adapter);
2072 int be_cmd_req_native_mode(struct be_adapter *adapter);
2073 int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size);
2074 void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf);
2075 int be_cmd_get_fn_privileges(struct be_adapter *adapter, u32 *privilege,
2077 int be_cmd_set_fn_privileges(struct be_adapter *adapter, u32 privileges,
2079 int be_cmd_get_mac_from_list(struct be_adapter *adapter, u8 *mac,
2080 bool *pmac_id_active, u32 *pmac_id,
2081 u32 if_handle, u8 domain);
2082 int be_cmd_get_active_mac(struct be_adapter *adapter, u32 pmac_id, u8 *mac,
2083 u32 if_handle, bool active, u32 domain);
2084 int be_cmd_get_perm_mac(struct be_adapter *adapter, u8 *mac);
2085 int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array, u8 mac_count,
2087 int be_cmd_set_mac(struct be_adapter *adapter, u8 *mac, int if_id, u32 dom);
2088 int be_cmd_set_hsw_config(struct be_adapter *adapter, u16 pvid, u32 domain,
2089 u16 intf_id, u16 hsw_mode);
2090 int be_cmd_get_hsw_config(struct be_adapter *adapter, u16 *pvid, u32 domain,
2091 u16 intf_id, u8 *mode);
2092 int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter);
2093 int be_cmd_set_fw_log_level(struct be_adapter *adapter, u32 level);
2094 int be_cmd_get_fw_log_level(struct be_adapter *adapter);
2095 int be_cmd_get_ext_fat_capabilites(struct be_adapter *adapter,
2096 struct be_dma_mem *cmd);
2097 int be_cmd_set_ext_fat_capabilites(struct be_adapter *adapter,
2098 struct be_dma_mem *cmd,
2099 struct be_fat_conf_params *cfgs);
2100 int lancer_physdev_ctrl(struct be_adapter *adapter, u32 mask);
2101 int lancer_initiate_dump(struct be_adapter *adapter);
2102 bool dump_present(struct be_adapter *adapter);
2103 int lancer_test_and_set_rdy_state(struct be_adapter *adapter);
2104 int be_cmd_query_port_name(struct be_adapter *adapter, u8 *port_name);
2105 int be_cmd_get_func_config(struct be_adapter *adapter,
2106 struct be_resources *res);
2107 int be_cmd_get_profile_config(struct be_adapter *adapter,
2108 struct be_resources *res, u8 domain);
2109 int be_cmd_set_profile_config(struct be_adapter *adapter, u32 bps, u8 domain);
2110 int be_cmd_get_active_profile(struct be_adapter *adapter, u16 *profile);
2111 int be_cmd_get_if_id(struct be_adapter *adapter, struct be_vf_cfg *vf_cfg,
2113 int be_cmd_enable_vf(struct be_adapter *adapter, u8 domain);
2114 int be_cmd_intr_set(struct be_adapter *adapter, bool intr_enable);