drivers/net/ethernet/faraday/ftgmac100.c

   1 /*
   2  * Faraday FTGMAC100 Gigabit Ethernet
   3  *
   4  * (C) Copyright 2009-2011 Faraday Technology
   5  * Po-Yu Chuang <ratbert@faraday-tech.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20  */
  21
  22 #define pr_fmt(fmt)     KBUILD_MODNAME ": " fmt
  23
  24 #include <linux/dma-mapping.h>
  25 #include <linux/etherdevice.h>
  26 #include <linux/ethtool.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/io.h>
  29 #include <linux/module.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/phy.h>
  32 #include <linux/platform_device.h>
  33 #include <net/ip.h>
  34
  35 #include "ftgmac100.h"
  36
  37 #define DRV_NAME        "ftgmac100"
  38 #define DRV_VERSION     "0.7"
  39
  40 #define RX_QUEUE_ENTRIES        256     /* must be power of 2 */
  41 #define TX_QUEUE_ENTRIES        512     /* must be power of 2 */
  42
  43 #define MAX_PKT_SIZE            1518
  44 #define RX_BUF_SIZE             PAGE_SIZE       /* must be smaller than 0x3fff */
  45
  46 /******************************************************************************
  47  * private data
  48  *****************************************************************************/
  49 struct ftgmac100_descs {
  50         struct ftgmac100_rxdes rxdes[RX_QUEUE_ENTRIES];
  51         struct ftgmac100_txdes txdes[TX_QUEUE_ENTRIES];
  52 };
  53
  54 struct ftgmac100 {
  55         struct resource *res;
  56         void __iomem *base;
  57         int irq;
  58
  59         struct ftgmac100_descs *descs;
  60         dma_addr_t descs_dma_addr;
  61
  62         unsigned int rx_pointer;
  63         unsigned int tx_clean_pointer;
  64         unsigned int tx_pointer;
  65         unsigned int tx_pending;
  66
  67         spinlock_t tx_lock;
  68
  69         struct net_device *netdev;
  70         struct device *dev;
  71         struct napi_struct napi;
  72
  73         struct mii_bus *mii_bus;
  74         int old_speed;
  75 };
  76
  77 static int ftgmac100_alloc_rx_page(struct ftgmac100 *priv,
  78                                    struct ftgmac100_rxdes *rxdes, gfp_t gfp);
  79
  80 /******************************************************************************
  81  * internal functions (hardware register access)
  82  *****************************************************************************/
  83 #define INT_MASK_ALL_ENABLED    (FTGMAC100_INT_RPKT_LOST        | \
  84                                  FTGMAC100_INT_XPKT_ETH         | \
  85                                  FTGMAC100_INT_XPKT_LOST        | \
  86                                  FTGMAC100_INT_AHB_ERR          | \
  87                                  FTGMAC100_INT_PHYSTS_CHG       | \
  88                                  FTGMAC100_INT_RPKT_BUF         | \
  89                                  FTGMAC100_INT_NO_RXBUF)
  90
  91 static void ftgmac100_set_rx_ring_base(struct ftgmac100 *priv, dma_addr_t addr)
  92 {
  93         iowrite32(addr, priv->base + FTGMAC100_OFFSET_RXR_BADR);
  94 }
  95
  96 static void ftgmac100_set_rx_buffer_size(struct ftgmac100 *priv,
  97                 unsigned int size)
  98 {
  99         size = FTGMAC100_RBSR_SIZE(size);
 100         iowrite32(size, priv->base + FTGMAC100_OFFSET_RBSR);
 101 }
 102
 103 static void ftgmac100_set_normal_prio_tx_ring_base(struct ftgmac100 *priv,
 104                                                    dma_addr_t addr)
 105 {
 106         iowrite32(addr, priv->base + FTGMAC100_OFFSET_NPTXR_BADR);
 107 }
 108
 109 static void ftgmac100_txdma_normal_prio_start_polling(struct ftgmac100 *priv)
 110 {
 111         iowrite32(1, priv->base + FTGMAC100_OFFSET_NPTXPD);
 112 }
 113
 114 static int ftgmac100_reset_hw(struct ftgmac100 *priv)
 115 {
 116         struct net_device *netdev = priv->netdev;
 117         int i;
 118
 119         /* NOTE: reset clears all registers */
 120         iowrite32(FTGMAC100_MACCR_SW_RST, priv->base + FTGMAC100_OFFSET_MACCR);
 121         for (i = 0; i < 5; i++) {
 122                 unsigned int maccr;
 123
 124                 maccr = ioread32(priv->base + FTGMAC100_OFFSET_MACCR);
 125                 if (!(maccr & FTGMAC100_MACCR_SW_RST))
 126                         return 0;
 127
 128                 udelay(1000);
 129         }
 130
 131         netdev_err(netdev, "software reset failed\n");
 132         return -EIO;
 133 }
 134
 135 static void ftgmac100_set_mac(struct ftgmac100 *priv, const unsigned char *mac)
 136 {
 137         unsigned int maddr = mac[0] << 8 | mac[1];
 138         unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5];
 139
 140         iowrite32(maddr, priv->base + FTGMAC100_OFFSET_MAC_MADR);
 141         iowrite32(laddr, priv->base + FTGMAC100_OFFSET_MAC_LADR);
 142 }
 143
 144 static void ftgmac100_init_hw(struct ftgmac100 *priv)
 145 {
 146         /* setup ring buffer base registers */
 147         ftgmac100_set_rx_ring_base(priv,
 148                                    priv->descs_dma_addr +
 149                                    offsetof(struct ftgmac100_descs, rxdes));
 150         ftgmac100_set_normal_prio_tx_ring_base(priv,
 151                                                priv->descs_dma_addr +
 152                                                offsetof(struct ftgmac100_descs, txdes));
 153
 154         ftgmac100_set_rx_buffer_size(priv, RX_BUF_SIZE);
 155
 156         iowrite32(FTGMAC100_APTC_RXPOLL_CNT(1), priv->base + FTGMAC100_OFFSET_APTC);
 157
 158         ftgmac100_set_mac(priv, priv->netdev->dev_addr);
 159 }
 160
 161 #define MACCR_ENABLE_ALL        (FTGMAC100_MACCR_TXDMA_EN       | \
 162                                  FTGMAC100_MACCR_RXDMA_EN       | \
 163                                  FTGMAC100_MACCR_TXMAC_EN       | \
 164                                  FTGMAC100_MACCR_RXMAC_EN       | \
 165                                  FTGMAC100_MACCR_FULLDUP        | \
 166                                  FTGMAC100_MACCR_CRC_APD        | \
 167                                  FTGMAC100_MACCR_RX_RUNT        | \
 168                                  FTGMAC100_MACCR_RX_BROADPKT)
 169
 170 static void ftgmac100_start_hw(struct ftgmac100 *priv, int speed)
 171 {
 172         int maccr = MACCR_ENABLE_ALL;
 173
 174         switch (speed) {
 175         default:
 176         case 10:
 177                 break;
 178
 179         case 100:
 180                 maccr |= FTGMAC100_MACCR_FAST_MODE;
 181                 break;
 182
 183         case 1000:
 184                 maccr |= FTGMAC100_MACCR_GIGA_MODE;
 185                 break;
 186         }
 187
 188         iowrite32(maccr, priv->base + FTGMAC100_OFFSET_MACCR);
 189 }
 190
 191 static void ftgmac100_stop_hw(struct ftgmac100 *priv)
 192 {
 193         iowrite32(0, priv->base + FTGMAC100_OFFSET_MACCR);
 194 }
 195
 196 /******************************************************************************
 197  * internal functions (receive descriptor)
 198  *****************************************************************************/
 199 static bool ftgmac100_rxdes_first_segment(struct ftgmac100_rxdes *rxdes)
 200 {
 201         return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_FRS);
 202 }
 203
 204 static bool ftgmac100_rxdes_last_segment(struct ftgmac100_rxdes *rxdes)
 205 {
 206         return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_LRS);
 207 }
 208
 209 static bool ftgmac100_rxdes_packet_ready(struct ftgmac100_rxdes *rxdes)
 210 {
 211         return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RXPKT_RDY);
 212 }
 213
 214 static void ftgmac100_rxdes_set_dma_own(struct ftgmac100_rxdes *rxdes)
 215 {
 216         /* clear status bits */
 217         rxdes->rxdes0 &= cpu_to_le32(FTGMAC100_RXDES0_EDORR);
 218 }
 219
 220 static bool ftgmac100_rxdes_rx_error(struct ftgmac100_rxdes *rxdes)
 221 {
 222         return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RX_ERR);
 223 }
 224
 225 static bool ftgmac100_rxdes_crc_error(struct ftgmac100_rxdes *rxdes)
 226 {
 227         return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_CRC_ERR);
 228 }
 229
 230 static bool ftgmac100_rxdes_frame_too_long(struct ftgmac100_rxdes *rxdes)
 231 {
 232         return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_FTL);
 233 }
 234
 235 static bool ftgmac100_rxdes_runt(struct ftgmac100_rxdes *rxdes)
 236 {
 237         return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RUNT);
 238 }
 239
 240 static bool ftgmac100_rxdes_odd_nibble(struct ftgmac100_rxdes *rxdes)
 241 {
 242         return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_RX_ODD_NB);
 243 }
 244
 245 static unsigned int ftgmac100_rxdes_data_length(struct ftgmac100_rxdes *rxdes)
 246 {
 247         return le32_to_cpu(rxdes->rxdes0) & FTGMAC100_RXDES0_VDBC;
 248 }
 249
 250 static bool ftgmac100_rxdes_multicast(struct ftgmac100_rxdes *rxdes)
 251 {
 252         return rxdes->rxdes0 & cpu_to_le32(FTGMAC100_RXDES0_MULTICAST);
 253 }
 254
 255 static void ftgmac100_rxdes_set_end_of_ring(struct ftgmac100_rxdes *rxdes)
 256 {
 257         rxdes->rxdes0 |= cpu_to_le32(FTGMAC100_RXDES0_EDORR);
 258 }
 259
 260 static void ftgmac100_rxdes_set_dma_addr(struct ftgmac100_rxdes *rxdes,
 261                                          dma_addr_t addr)
 262 {
 263         rxdes->rxdes3 = cpu_to_le32(addr);
 264 }
 265
 266 static dma_addr_t ftgmac100_rxdes_get_dma_addr(struct ftgmac100_rxdes *rxdes)
 267 {
 268         return le32_to_cpu(rxdes->rxdes3);
 269 }
 270
 271 static bool ftgmac100_rxdes_is_tcp(struct ftgmac100_rxdes *rxdes)
 272 {
 273         return (rxdes->rxdes1 & cpu_to_le32(FTGMAC100_RXDES1_PROT_MASK)) ==
 274                cpu_to_le32(FTGMAC100_RXDES1_PROT_TCPIP);
 275 }
 276
 277 static bool ftgmac100_rxdes_is_udp(struct ftgmac100_rxdes *rxdes)
 278 {
 279         return (rxdes->rxdes1 & cpu_to_le32(FTGMAC100_RXDES1_PROT_MASK)) ==
 280                cpu_to_le32(FTGMAC100_RXDES1_PROT_UDPIP);
 281 }
 282
 283 static bool ftgmac100_rxdes_tcpcs_err(struct ftgmac100_rxdes *rxdes)
 284 {
 285         return rxdes->rxdes1 & cpu_to_le32(FTGMAC100_RXDES1_TCP_CHKSUM_ERR);
 286 }
 287
 288 static bool ftgmac100_rxdes_udpcs_err(struct ftgmac100_rxdes *rxdes)
 289 {
 290         return rxdes->rxdes1 & cpu_to_le32(FTGMAC100_RXDES1_UDP_CHKSUM_ERR);
 291 }
 292
 293 static bool ftgmac100_rxdes_ipcs_err(struct ftgmac100_rxdes *rxdes)
 294 {
 295         return rxdes->rxdes1 & cpu_to_le32(FTGMAC100_RXDES1_IP_CHKSUM_ERR);
 296 }
 297
 298 /*
 299  * rxdes2 is not used by hardware. We use it to keep track of page.
 300  * Since hardware does not touch it, we can skip cpu_to_le32()/le32_to_cpu().
 301  */
 302 static void ftgmac100_rxdes_set_page(struct ftgmac100_rxdes *rxdes, struct page *page)
 303 {
 304         rxdes->rxdes2 = (unsigned int)page;
 305 }
 306
 307 static struct page *ftgmac100_rxdes_get_page(struct ftgmac100_rxdes *rxdes)
 308 {
 309         return (struct page *)rxdes->rxdes2;
 310 }
 311
 312 /******************************************************************************
 313  * internal functions (receive)
 314  *****************************************************************************/
 315 static int ftgmac100_next_rx_pointer(int pointer)
 316 {
 317         return (pointer + 1) & (RX_QUEUE_ENTRIES - 1);
 318 }
 319
 320 static void ftgmac100_rx_pointer_advance(struct ftgmac100 *priv)
 321 {
 322         priv->rx_pointer = ftgmac100_next_rx_pointer(priv->rx_pointer);
 323 }
 324
 325 static struct ftgmac100_rxdes *ftgmac100_current_rxdes(struct ftgmac100 *priv)
 326 {
 327         return &priv->descs->rxdes[priv->rx_pointer];
 328 }
 329
 330 static struct ftgmac100_rxdes *
 331 ftgmac100_rx_locate_first_segment(struct ftgmac100 *priv)
 332 {
 333         struct ftgmac100_rxdes *rxdes = ftgmac100_current_rxdes(priv);
 334
 335         while (ftgmac100_rxdes_packet_ready(rxdes)) {
 336                 if (ftgmac100_rxdes_first_segment(rxdes))
 337                         return rxdes;
 338
 339                 ftgmac100_rxdes_set_dma_own(rxdes);
 340                 ftgmac100_rx_pointer_advance(priv);
 341                 rxdes = ftgmac100_current_rxdes(priv);
 342         }
 343
 344         return NULL;
 345 }
 346
 347 static bool ftgmac100_rx_packet_error(struct ftgmac100 *priv,
 348                                       struct ftgmac100_rxdes *rxdes)
 349 {
 350         struct net_device *netdev = priv->netdev;
 351         bool error = false;
 352
 353         if (unlikely(ftgmac100_rxdes_rx_error(rxdes))) {
 354                 if (net_ratelimit())
 355                         netdev_info(netdev, "rx err\n");
 356
 357                 netdev->stats.rx_errors++;
 358                 error = true;
 359         }
 360
 361         if (unlikely(ftgmac100_rxdes_crc_error(rxdes))) {
 362                 if (net_ratelimit())
 363                         netdev_info(netdev, "rx crc err\n");
 364
 365                 netdev->stats.rx_crc_errors++;
 366                 error = true;
 367         } else if (unlikely(ftgmac100_rxdes_ipcs_err(rxdes))) {
 368                 if (net_ratelimit())
 369                         netdev_info(netdev, "rx IP checksum err\n");
 370
 371                 error = true;
 372         }
 373
 374         if (unlikely(ftgmac100_rxdes_frame_too_long(rxdes))) {
 375                 if (net_ratelimit())
 376                         netdev_info(netdev, "rx frame too long\n");
 377
 378                 netdev->stats.rx_length_errors++;
 379                 error = true;
 380         } else if (unlikely(ftgmac100_rxdes_runt(rxdes))) {
 381                 if (net_ratelimit())
 382                         netdev_info(netdev, "rx runt\n");
 383
 384                 netdev->stats.rx_length_errors++;
 385                 error = true;
 386         } else if (unlikely(ftgmac100_rxdes_odd_nibble(rxdes))) {
 387                 if (net_ratelimit())
 388                         netdev_info(netdev, "rx odd nibble\n");
 389
 390                 netdev->stats.rx_length_errors++;
 391                 error = true;
 392         }
 393
 394         return error;
 395 }
 396
 397 static void ftgmac100_rx_drop_packet(struct ftgmac100 *priv)
 398 {
 399         struct net_device *netdev = priv->netdev;
 400         struct ftgmac100_rxdes *rxdes = ftgmac100_current_rxdes(priv);
 401         bool done = false;
 402
 403         if (net_ratelimit())
 404                 netdev_dbg(netdev, "drop packet %p\n", rxdes);
 405
 406         do {
 407                 if (ftgmac100_rxdes_last_segment(rxdes))
 408                         done = true;
 409
 410                 ftgmac100_rxdes_set_dma_own(rxdes);
 411                 ftgmac100_rx_pointer_advance(priv);
 412                 rxdes = ftgmac100_current_rxdes(priv);
 413         } while (!done && ftgmac100_rxdes_packet_ready(rxdes));
 414
 415         netdev->stats.rx_dropped++;
 416 }
 417
 418 static bool ftgmac100_rx_packet(struct ftgmac100 *priv, int *processed)
 419 {
 420         struct net_device *netdev = priv->netdev;
 421         struct ftgmac100_rxdes *rxdes;
 422         struct sk_buff *skb;
 423         bool done = false;
 424
 425         rxdes = ftgmac100_rx_locate_first_segment(priv);
 426         if (!rxdes)
 427                 return false;
 428
 429         if (unlikely(ftgmac100_rx_packet_error(priv, rxdes))) {
 430                 ftgmac100_rx_drop_packet(priv);
 431                 return true;
 432         }
 433
 434         /* start processing */
 435         skb = netdev_alloc_skb_ip_align(netdev, 128);
 436         if (unlikely(!skb)) {
 437                 if (net_ratelimit())
 438                         netdev_err(netdev, "rx skb alloc failed\n");
 439
 440                 ftgmac100_rx_drop_packet(priv);
 441                 return true;
 442         }
 443
 444         if (unlikely(ftgmac100_rxdes_multicast(rxdes)))
 445                 netdev->stats.multicast++;
 446
 447         /*
 448          * It seems that HW does checksum incorrectly with fragmented packets,
 449          * so we are conservative here - if HW checksum error, let software do
 450          * the checksum again.
 451          */
 452         if ((ftgmac100_rxdes_is_tcp(rxdes) && !ftgmac100_rxdes_tcpcs_err(rxdes)) ||
 453             (ftgmac100_rxdes_is_udp(rxdes) && !ftgmac100_rxdes_udpcs_err(rxdes)))
 454                 skb->ip_summed = CHECKSUM_UNNECESSARY;
 455
 456         do {
 457                 dma_addr_t map = ftgmac100_rxdes_get_dma_addr(rxdes);
 458                 struct page *page = ftgmac100_rxdes_get_page(rxdes);
 459                 unsigned int size;
 460
 461                 dma_unmap_page(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE);
 462
 463                 size = ftgmac100_rxdes_data_length(rxdes);
 464                 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags, page, 0, size);
 465
 466                 skb->len += size;
 467                 skb->data_len += size;
 468                 skb->truesize += PAGE_SIZE;
 469
 470                 if (ftgmac100_rxdes_last_segment(rxdes))
 471                         done = true;
 472
 473                 ftgmac100_alloc_rx_page(priv, rxdes, GFP_ATOMIC);
 474
 475                 ftgmac100_rx_pointer_advance(priv);
 476                 rxdes = ftgmac100_current_rxdes(priv);
 477         } while (!done);
 478
 479         /* Small frames are copied into linear part of skb to free one page */
 480         if (skb->len <= 128) {
 481                 skb->truesize -= PAGE_SIZE;
 482                 __pskb_pull_tail(skb, skb->len);
 483         } else {
 484                 /* We pull the minimum amount into linear part */
 485                 __pskb_pull_tail(skb, ETH_HLEN);
 486         }
 487         skb->protocol = eth_type_trans(skb, netdev);
 488
 489         netdev->stats.rx_packets++;
 490         netdev->stats.rx_bytes += skb->len;
 491
 492         /* push packet to protocol stack */
 493         napi_gro_receive(&priv->napi, skb);
 494
 495         (*processed)++;
 496         return true;
 497 }
 498
 499 /******************************************************************************
 500  * internal functions (transmit descriptor)
 501  *****************************************************************************/
 502 static void ftgmac100_txdes_reset(struct ftgmac100_txdes *txdes)
 503 {
 504         /* clear all except end of ring bit */
 505         txdes->txdes0 &= cpu_to_le32(FTGMAC100_TXDES0_EDOTR);
 506         txdes->txdes1 = 0;
 507         txdes->txdes2 = 0;
 508         txdes->txdes3 = 0;
 509 }
 510
 511 static bool ftgmac100_txdes_owned_by_dma(struct ftgmac100_txdes *txdes)
 512 {
 513         return txdes->txdes0 & cpu_to_le32(FTGMAC100_TXDES0_TXDMA_OWN);
 514 }
 515
 516 static void ftgmac100_txdes_set_dma_own(struct ftgmac100_txdes *txdes)
 517 {
 518         /*
 519          * Make sure dma own bit will not be set before any other
 520          * descriptor fields.
 521          */
 522         wmb();
 523         txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_TXDMA_OWN);
 524 }
 525
 526 static void ftgmac100_txdes_set_end_of_ring(struct ftgmac100_txdes *txdes)
 527 {
 528         txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_EDOTR);
 529 }
 530
 531 static void ftgmac100_txdes_set_first_segment(struct ftgmac100_txdes *txdes)
 532 {
 533         txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_FTS);
 534 }
 535
 536 static void ftgmac100_txdes_set_last_segment(struct ftgmac100_txdes *txdes)
 537 {
 538         txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_LTS);
 539 }
 540
 541 static void ftgmac100_txdes_set_buffer_size(struct ftgmac100_txdes *txdes,
 542                                             unsigned int len)
 543 {
 544         txdes->txdes0 |= cpu_to_le32(FTGMAC100_TXDES0_TXBUF_SIZE(len));
 545 }
 546
 547 static void ftgmac100_txdes_set_txint(struct ftgmac100_txdes *txdes)
 548 {
 549         txdes->txdes1 |= cpu_to_le32(FTGMAC100_TXDES1_TXIC);
 550 }
 551
 552 static void ftgmac100_txdes_set_tcpcs(struct ftgmac100_txdes *txdes)
 553 {
 554         txdes->txdes1 |= cpu_to_le32(FTGMAC100_TXDES1_TCP_CHKSUM);
 555 }
 556
 557 static void ftgmac100_txdes_set_udpcs(struct ftgmac100_txdes *txdes)
 558 {
 559         txdes->txdes1 |= cpu_to_le32(FTGMAC100_TXDES1_UDP_CHKSUM);
 560 }
 561
 562 static void ftgmac100_txdes_set_ipcs(struct ftgmac100_txdes *txdes)
 563 {
 564         txdes->txdes1 |= cpu_to_le32(FTGMAC100_TXDES1_IP_CHKSUM);
 565 }
 566
 567 static void ftgmac100_txdes_set_dma_addr(struct ftgmac100_txdes *txdes,
 568                                          dma_addr_t addr)
 569 {
 570         txdes->txdes3 = cpu_to_le32(addr);
 571 }
 572
 573 static dma_addr_t ftgmac100_txdes_get_dma_addr(struct ftgmac100_txdes *txdes)
 574 {
 575         return le32_to_cpu(txdes->txdes3);
 576 }
 577
 578 /*
 579  * txdes2 is not used by hardware. We use it to keep track of socket buffer.
 580  * Since hardware does not touch it, we can skip cpu_to_le32()/le32_to_cpu().
 581  */
 582 static void ftgmac100_txdes_set_skb(struct ftgmac100_txdes *txdes,
 583                                     struct sk_buff *skb)
 584 {
 585         txdes->txdes2 = (unsigned int)skb;
 586 }
 587
 588 static struct sk_buff *ftgmac100_txdes_get_skb(struct ftgmac100_txdes *txdes)
 589 {
 590         return (struct sk_buff *)txdes->txdes2;
 591 }
 592
 593 /******************************************************************************
 594  * internal functions (transmit)
 595  *****************************************************************************/
 596 static int ftgmac100_next_tx_pointer(int pointer)
 597 {
 598         return (pointer + 1) & (TX_QUEUE_ENTRIES - 1);
 599 }
 600
 601 static void ftgmac100_tx_pointer_advance(struct ftgmac100 *priv)
 602 {
 603         priv->tx_pointer = ftgmac100_next_tx_pointer(priv->tx_pointer);
 604 }
 605
 606 static void ftgmac100_tx_clean_pointer_advance(struct ftgmac100 *priv)
 607 {
 608         priv->tx_clean_pointer = ftgmac100_next_tx_pointer(priv->tx_clean_pointer);
 609 }
 610
 611 static struct ftgmac100_txdes *ftgmac100_current_txdes(struct ftgmac100 *priv)
 612 {
 613         return &priv->descs->txdes[priv->tx_pointer];
 614 }
 615
 616 static struct ftgmac100_txdes *
 617 ftgmac100_current_clean_txdes(struct ftgmac100 *priv)
 618 {
 619         return &priv->descs->txdes[priv->tx_clean_pointer];
 620 }
 621
 622 static bool ftgmac100_tx_complete_packet(struct ftgmac100 *priv)
 623 {
 624         struct net_device *netdev = priv->netdev;
 625         struct ftgmac100_txdes *txdes;
 626         struct sk_buff *skb;
 627         dma_addr_t map;
 628
 629         if (priv->tx_pending == 0)
 630                 return false;
 631
 632         txdes = ftgmac100_current_clean_txdes(priv);
 633
 634         if (ftgmac100_txdes_owned_by_dma(txdes))
 635                 return false;
 636
 637         skb = ftgmac100_txdes_get_skb(txdes);
 638         map = ftgmac100_txdes_get_dma_addr(txdes);
 639
 640         netdev->stats.tx_packets++;
 641         netdev->stats.tx_bytes += skb->len;
 642
 643         dma_unmap_single(priv->dev, map, skb_headlen(skb), DMA_TO_DEVICE);
 644
 645         dev_kfree_skb(skb);
 646
 647         ftgmac100_txdes_reset(txdes);
 648
 649         ftgmac100_tx_clean_pointer_advance(priv);
 650
 651         spin_lock(&priv->tx_lock);
 652         priv->tx_pending--;
 653         spin_unlock(&priv->tx_lock);
 654         netif_wake_queue(netdev);
 655
 656         return true;
 657 }
 658
 659 static void ftgmac100_tx_complete(struct ftgmac100 *priv)
 660 {
 661         while (ftgmac100_tx_complete_packet(priv))
 662                 ;
 663 }
 664
 665 static int ftgmac100_xmit(struct ftgmac100 *priv, struct sk_buff *skb,
 666                           dma_addr_t map)
 667 {
 668         struct net_device *netdev = priv->netdev;
 669         struct ftgmac100_txdes *txdes;
 670         unsigned int len = (skb->len < ETH_ZLEN) ? ETH_ZLEN : skb->len;
 671
 672         txdes = ftgmac100_current_txdes(priv);
 673         ftgmac100_tx_pointer_advance(priv);
 674
 675         /* setup TX descriptor */
 676         ftgmac100_txdes_set_skb(txdes, skb);
 677         ftgmac100_txdes_set_dma_addr(txdes, map);
 678         ftgmac100_txdes_set_buffer_size(txdes, len);
 679
 680         ftgmac100_txdes_set_first_segment(txdes);
 681         ftgmac100_txdes_set_last_segment(txdes);
 682         ftgmac100_txdes_set_txint(txdes);
 683         if (skb->ip_summed == CHECKSUM_PARTIAL) {
 684                 __be16 protocol = skb->protocol;
 685
 686                 if (protocol == cpu_to_be16(ETH_P_IP)) {
 687                         u8 ip_proto = ip_hdr(skb)->protocol;
 688
 689                         ftgmac100_txdes_set_ipcs(txdes);
 690                         if (ip_proto == IPPROTO_TCP)
 691                                 ftgmac100_txdes_set_tcpcs(txdes);
 692                         else if (ip_proto == IPPROTO_UDP)
 693                                 ftgmac100_txdes_set_udpcs(txdes);
 694                 }
 695         }
 696
 697         spin_lock(&priv->tx_lock);
 698         priv->tx_pending++;
 699         if (priv->tx_pending == TX_QUEUE_ENTRIES)
 700                 netif_stop_queue(netdev);
 701
 702         /* start transmit */
 703         ftgmac100_txdes_set_dma_own(txdes);
 704         spin_unlock(&priv->tx_lock);
 705
 706         ftgmac100_txdma_normal_prio_start_polling(priv);
 707
 708         return NETDEV_TX_OK;
 709 }
 710
 711 /******************************************************************************
 712  * internal functions (buffer)
 713  *****************************************************************************/
 714 static int ftgmac100_alloc_rx_page(struct ftgmac100 *priv,
 715                                    struct ftgmac100_rxdes *rxdes, gfp_t gfp)
 716 {
 717         struct net_device *netdev = priv->netdev;
 718         struct page *page;
 719         dma_addr_t map;
 720
 721         page = alloc_page(gfp);
 722         if (!page) {
 723                 if (net_ratelimit())
 724                         netdev_err(netdev, "failed to allocate rx page\n");
 725                 return -ENOMEM;
 726         }
 727
 728         map = dma_map_page(priv->dev, page, 0, RX_BUF_SIZE, DMA_FROM_DEVICE);
 729         if (unlikely(dma_mapping_error(priv->dev, map))) {
 730                 if (net_ratelimit())
 731                         netdev_err(netdev, "failed to map rx page\n");
 732                 __free_page(page);
 733                 return -ENOMEM;
 734         }
 735
 736         ftgmac100_rxdes_set_page(rxdes, page);
 737         ftgmac100_rxdes_set_dma_addr(rxdes, map);
 738         ftgmac100_rxdes_set_dma_own(rxdes);
 739         return 0;
 740 }
 741
 742 static void ftgmac100_free_buffers(struct ftgmac100 *priv)
 743 {
 744         int i;
 745
 746         for (i = 0; i < RX_QUEUE_ENTRIES; i++) {
 747                 struct ftgmac100_rxdes *rxdes = &priv->descs->rxdes[i];
 748                 struct page *page = ftgmac100_rxdes_get_page(rxdes);
 749                 dma_addr_t map = ftgmac100_rxdes_get_dma_addr(rxdes);
 750
 751                 if (!page)
 752                         continue;
 753
 754                 dma_unmap_page(priv->dev, map, RX_BUF_SIZE, DMA_FROM_DEVICE);
 755                 __free_page(page);
 756         }
 757
 758         for (i = 0; i < TX_QUEUE_ENTRIES; i++) {
 759                 struct ftgmac100_txdes *txdes = &priv->descs->txdes[i];
 760                 struct sk_buff *skb = ftgmac100_txdes_get_skb(txdes);
 761                 dma_addr_t map = ftgmac100_txdes_get_dma_addr(txdes);
 762
 763                 if (!skb)
 764                         continue;
 765
 766                 dma_unmap_single(priv->dev, map, skb_headlen(skb), DMA_TO_DEVICE);
 767                 kfree_skb(skb);
 768         }
 769
 770         dma_free_coherent(priv->dev, sizeof(struct ftgmac100_descs),
 771                           priv->descs, priv->descs_dma_addr);
 772 }
 773
 774 static int ftgmac100_alloc_buffers(struct ftgmac100 *priv)
 775 {
 776         int i;
 777
 778         priv->descs = dma_zalloc_coherent(priv->dev,
 779                                           sizeof(struct ftgmac100_descs),
 780                                           &priv->descs_dma_addr, GFP_KERNEL);
 781         if (!priv->descs)
 782                 return -ENOMEM;
 783
 784         /* initialize RX ring */
 785         ftgmac100_rxdes_set_end_of_ring(&priv->descs->rxdes[RX_QUEUE_ENTRIES - 1]);
 786
 787         for (i = 0; i < RX_QUEUE_ENTRIES; i++) {
 788                 struct ftgmac100_rxdes *rxdes = &priv->descs->rxdes[i];
 789
 790                 if (ftgmac100_alloc_rx_page(priv, rxdes, GFP_KERNEL))
 791                         goto err;
 792         }
 793
 794         /* initialize TX ring */
 795         ftgmac100_txdes_set_end_of_ring(&priv->descs->txdes[TX_QUEUE_ENTRIES - 1]);
 796         return 0;
 797
 798 err:
 799         ftgmac100_free_buffers(priv);
 800         return -ENOMEM;
 801 }
 802
 803 /******************************************************************************
 804  * internal functions (mdio)
 805  *****************************************************************************/
 806 static void ftgmac100_adjust_link(struct net_device *netdev)
 807 {
 808         struct ftgmac100 *priv = netdev_priv(netdev);
 809         struct phy_device *phydev = netdev->phydev;
 810         int ier;
 811
 812         if (phydev->speed == priv->old_speed)
 813                 return;
 814
 815         priv->old_speed = phydev->speed;
 816
 817         ier = ioread32(priv->base + FTGMAC100_OFFSET_IER);
 818
 819         /* disable all interrupts */
 820         iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
 821
 822         netif_stop_queue(netdev);
 823         ftgmac100_stop_hw(priv);
 824
 825         netif_start_queue(netdev);
 826         ftgmac100_init_hw(priv);
 827         ftgmac100_start_hw(priv, phydev->speed);
 828
 829         /* re-enable interrupts */
 830         iowrite32(ier, priv->base + FTGMAC100_OFFSET_IER);
 831 }
 832
 833 static int ftgmac100_mii_probe(struct ftgmac100 *priv)
 834 {
 835         struct net_device *netdev = priv->netdev;
 836         struct phy_device *phydev;
 837
 838         phydev = phy_find_first(priv->mii_bus);
 839         if (!phydev) {
 840                 netdev_info(netdev, "%s: no PHY found\n", netdev->name);
 841                 return -ENODEV;
 842         }
 843
 844         phydev = phy_connect(netdev, phydev_name(phydev),
 845                              &ftgmac100_adjust_link, PHY_INTERFACE_MODE_GMII);
 846
 847         if (IS_ERR(phydev)) {
 848                 netdev_err(netdev, "%s: Could not attach to PHY\n", netdev->name);
 849                 return PTR_ERR(phydev);
 850         }
 851
 852         return 0;
 853 }
 854
 855 /******************************************************************************
 856  * struct mii_bus functions
 857  *****************************************************************************/
 858 static int ftgmac100_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
 859 {
 860         struct net_device *netdev = bus->priv;
 861         struct ftgmac100 *priv = netdev_priv(netdev);
 862         unsigned int phycr;
 863         int i;
 864
 865         phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
 866
 867         /* preserve MDC cycle threshold */
 868         phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK;
 869
 870         phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) |
 871                  FTGMAC100_PHYCR_REGAD(regnum) |
 872                  FTGMAC100_PHYCR_MIIRD;
 873
 874         iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR);
 875
 876         for (i = 0; i < 10; i++) {
 877                 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
 878
 879                 if ((phycr & FTGMAC100_PHYCR_MIIRD) == 0) {
 880                         int data;
 881
 882                         data = ioread32(priv->base + FTGMAC100_OFFSET_PHYDATA);
 883                         return FTGMAC100_PHYDATA_MIIRDATA(data);
 884                 }
 885
 886                 udelay(100);
 887         }
 888
 889         netdev_err(netdev, "mdio read timed out\n");
 890         return -EIO;
 891 }
 892
 893 static int ftgmac100_mdiobus_write(struct mii_bus *bus, int phy_addr,
 894                                    int regnum, u16 value)
 895 {
 896         struct net_device *netdev = bus->priv;
 897         struct ftgmac100 *priv = netdev_priv(netdev);
 898         unsigned int phycr;
 899         int data;
 900         int i;
 901
 902         phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
 903
 904         /* preserve MDC cycle threshold */
 905         phycr &= FTGMAC100_PHYCR_MDC_CYCTHR_MASK;
 906
 907         phycr |= FTGMAC100_PHYCR_PHYAD(phy_addr) |
 908                  FTGMAC100_PHYCR_REGAD(regnum) |
 909                  FTGMAC100_PHYCR_MIIWR;
 910
 911         data = FTGMAC100_PHYDATA_MIIWDATA(value);
 912
 913         iowrite32(data, priv->base + FTGMAC100_OFFSET_PHYDATA);
 914         iowrite32(phycr, priv->base + FTGMAC100_OFFSET_PHYCR);
 915
 916         for (i = 0; i < 10; i++) {
 917                 phycr = ioread32(priv->base + FTGMAC100_OFFSET_PHYCR);
 918
 919                 if ((phycr & FTGMAC100_PHYCR_MIIWR) == 0)
 920                         return 0;
 921
 922                 udelay(100);
 923         }
 924
 925         netdev_err(netdev, "mdio write timed out\n");
 926         return -EIO;
 927 }
 928
 929 /******************************************************************************
 930  * struct ethtool_ops functions
 931  *****************************************************************************/
 932 static void ftgmac100_get_drvinfo(struct net_device *netdev,
 933                                   struct ethtool_drvinfo *info)
 934 {
 935         strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
 936         strlcpy(info->version, DRV_VERSION, sizeof(info->version));
 937         strlcpy(info->bus_info, dev_name(&netdev->dev), sizeof(info->bus_info));
 938 }
 939
 940 static const struct ethtool_ops ftgmac100_ethtool_ops = {
 941         .get_drvinfo            = ftgmac100_get_drvinfo,
 942         .get_link               = ethtool_op_get_link,
 943         .get_link_ksettings     = phy_ethtool_get_link_ksettings,
 944         .set_link_ksettings     = phy_ethtool_set_link_ksettings,
 945 };
 946
 947 /******************************************************************************
 948  * interrupt handler
 949  *****************************************************************************/
 950 static irqreturn_t ftgmac100_interrupt(int irq, void *dev_id)
 951 {
 952         struct net_device *netdev = dev_id;
 953         struct ftgmac100 *priv = netdev_priv(netdev);
 954
 955         if (likely(netif_running(netdev))) {
 956                 /* Disable interrupts for polling */
 957                 iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
 958                 napi_schedule(&priv->napi);
 959         }
 960
 961         return IRQ_HANDLED;
 962 }
 963
 964 /******************************************************************************
 965  * struct napi_struct functions
 966  *****************************************************************************/
 967 static int ftgmac100_poll(struct napi_struct *napi, int budget)
 968 {
 969         struct ftgmac100 *priv = container_of(napi, struct ftgmac100, napi);
 970         struct net_device *netdev = priv->netdev;
 971         unsigned int status;
 972         bool completed = true;
 973         int rx = 0;
 974
 975         status = ioread32(priv->base + FTGMAC100_OFFSET_ISR);
 976         iowrite32(status, priv->base + FTGMAC100_OFFSET_ISR);
 977
 978         if (status & (FTGMAC100_INT_RPKT_BUF | FTGMAC100_INT_NO_RXBUF)) {
 979                 /*
 980                  * FTGMAC100_INT_RPKT_BUF:
 981                  *      RX DMA has received packets into RX buffer successfully
 982                  *
 983                  * FTGMAC100_INT_NO_RXBUF:
 984                  *      RX buffer unavailable
 985                  */
 986                 bool retry;
 987
 988                 do {
 989                         retry = ftgmac100_rx_packet(priv, &rx);
 990                 } while (retry && rx < budget);
 991
 992                 if (retry && rx == budget)
 993                         completed = false;
 994         }
 995
 996         if (status & (FTGMAC100_INT_XPKT_ETH | FTGMAC100_INT_XPKT_LOST)) {
 997                 /*
 998                  * FTGMAC100_INT_XPKT_ETH:
 999                  *      packet transmitted to ethernet successfully
1000                  *
1001                  * FTGMAC100_INT_XPKT_LOST:
1002                  *      packet transmitted to ethernet lost due to late
1003                  *      collision or excessive collision
1004                  */
1005                 ftgmac100_tx_complete(priv);
1006         }
1007
1008         if (status & (FTGMAC100_INT_NO_RXBUF | FTGMAC100_INT_RPKT_LOST |
1009                       FTGMAC100_INT_AHB_ERR | FTGMAC100_INT_PHYSTS_CHG)) {
1010                 if (net_ratelimit())
1011                         netdev_info(netdev, "[ISR] = 0x%x: %s%s%s%s\n", status,
1012                                     status & FTGMAC100_INT_NO_RXBUF ? "NO_RXBUF " : "",
1013                                     status & FTGMAC100_INT_RPKT_LOST ? "RPKT_LOST " : "",
1014                                     status & FTGMAC100_INT_AHB_ERR ? "AHB_ERR " : "",
1015                                     status & FTGMAC100_INT_PHYSTS_CHG ? "PHYSTS_CHG" : "");
1016
1017                 if (status & FTGMAC100_INT_NO_RXBUF) {
1018                         /* RX buffer unavailable */
1019                         netdev->stats.rx_over_errors++;
1020                 }
1021
1022                 if (status & FTGMAC100_INT_RPKT_LOST) {
1023                         /* received packet lost due to RX FIFO full */
1024                         netdev->stats.rx_fifo_errors++;
1025                 }
1026         }
1027
1028         if (completed) {
1029                 napi_complete(napi);
1030
1031                 /* enable all interrupts */
1032                 iowrite32(INT_MASK_ALL_ENABLED, priv->base + FTGMAC100_OFFSET_IER);
1033         }
1034
1035         return rx;
1036 }
1037
1038 /******************************************************************************
1039  * struct net_device_ops functions
1040  *****************************************************************************/
1041 static int ftgmac100_open(struct net_device *netdev)
1042 {
1043         struct ftgmac100 *priv = netdev_priv(netdev);
1044         int err;
1045
1046         err = ftgmac100_alloc_buffers(priv);
1047         if (err) {
1048                 netdev_err(netdev, "failed to allocate buffers\n");
1049                 goto err_alloc;
1050         }
1051
1052         err = request_irq(priv->irq, ftgmac100_interrupt, 0, netdev->name, netdev);
1053         if (err) {
1054                 netdev_err(netdev, "failed to request irq %d\n", priv->irq);
1055                 goto err_irq;
1056         }
1057
1058         priv->rx_pointer = 0;
1059         priv->tx_clean_pointer = 0;
1060         priv->tx_pointer = 0;
1061         priv->tx_pending = 0;
1062
1063         err = ftgmac100_reset_hw(priv);
1064         if (err)
1065                 goto err_hw;
1066
1067         ftgmac100_init_hw(priv);
1068         ftgmac100_start_hw(priv, 10);
1069
1070         phy_start(netdev->phydev);
1071
1072         napi_enable(&priv->napi);
1073         netif_start_queue(netdev);
1074
1075         /* enable all interrupts */
1076         iowrite32(INT_MASK_ALL_ENABLED, priv->base + FTGMAC100_OFFSET_IER);
1077         return 0;
1078
1079 err_hw:
1080         free_irq(priv->irq, netdev);
1081 err_irq:
1082         ftgmac100_free_buffers(priv);
1083 err_alloc:
1084         return err;
1085 }
1086
1087 static int ftgmac100_stop(struct net_device *netdev)
1088 {
1089         struct ftgmac100 *priv = netdev_priv(netdev);
1090
1091         /* disable all interrupts */
1092         iowrite32(0, priv->base + FTGMAC100_OFFSET_IER);
1093
1094         netif_stop_queue(netdev);
1095         napi_disable(&priv->napi);
1096         phy_stop(netdev->phydev);
1097
1098         ftgmac100_stop_hw(priv);
1099         free_irq(priv->irq, netdev);
1100         ftgmac100_free_buffers(priv);
1101
1102         return 0;
1103 }
1104
1105 static int ftgmac100_hard_start_xmit(struct sk_buff *skb,
1106                                      struct net_device *netdev)
1107 {
1108         struct ftgmac100 *priv = netdev_priv(netdev);
1109         dma_addr_t map;
1110
1111         if (unlikely(skb->len > MAX_PKT_SIZE)) {
1112                 if (net_ratelimit())
1113                         netdev_dbg(netdev, "tx packet too big\n");
1114
1115                 netdev->stats.tx_dropped++;
1116                 kfree_skb(skb);
1117                 return NETDEV_TX_OK;
1118         }
1119
1120         map = dma_map_single(priv->dev, skb->data, skb_headlen(skb), DMA_TO_DEVICE);
1121         if (unlikely(dma_mapping_error(priv->dev, map))) {
1122                 /* drop packet */
1123                 if (net_ratelimit())
1124                         netdev_err(netdev, "map socket buffer failed\n");
1125
1126                 netdev->stats.tx_dropped++;
1127                 kfree_skb(skb);
1128                 return NETDEV_TX_OK;
1129         }
1130
1131         return ftgmac100_xmit(priv, skb, map);
1132 }
1133
1134 /* optional */
1135 static int ftgmac100_do_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1136 {
1137         return phy_mii_ioctl(netdev->phydev, ifr, cmd);
1138 }
1139
1140 static const struct net_device_ops ftgmac100_netdev_ops = {
1141         .ndo_open               = ftgmac100_open,
1142         .ndo_stop               = ftgmac100_stop,
1143         .ndo_start_xmit         = ftgmac100_hard_start_xmit,
1144         .ndo_set_mac_address    = eth_mac_addr,
1145         .ndo_validate_addr      = eth_validate_addr,
1146         .ndo_do_ioctl           = ftgmac100_do_ioctl,
1147 };
1148
1149 /******************************************************************************
1150  * struct platform_driver functions
1151  *****************************************************************************/
1152 static int ftgmac100_probe(struct platform_device *pdev)
1153 {
1154         struct resource *res;
1155         int irq;
1156         struct net_device *netdev;
1157         struct ftgmac100 *priv;
1158         int err;
1159
1160         if (!pdev)
1161                 return -ENODEV;
1162
1163         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1164         if (!res)
1165                 return -ENXIO;
1166
1167         irq = platform_get_irq(pdev, 0);
1168         if (irq < 0)
1169                 return irq;
1170
1171         /* setup net_device */
1172         netdev = alloc_etherdev(sizeof(*priv));
1173         if (!netdev) {
1174                 err = -ENOMEM;
1175                 goto err_alloc_etherdev;
1176         }
1177
1178         SET_NETDEV_DEV(netdev, &pdev->dev);
1179
1180         netdev->ethtool_ops = &ftgmac100_ethtool_ops;
1181         netdev->netdev_ops = &ftgmac100_netdev_ops;
1182         netdev->features = NETIF_F_IP_CSUM | NETIF_F_GRO;
1183
1184         platform_set_drvdata(pdev, netdev);
1185
1186         /* setup private data */
1187         priv = netdev_priv(netdev);
1188         priv->netdev = netdev;
1189         priv->dev = &pdev->dev;
1190
1191         spin_lock_init(&priv->tx_lock);
1192
1193         /* initialize NAPI */
1194         netif_napi_add(netdev, &priv->napi, ftgmac100_poll, 64);
1195
1196         /* map io memory */
1197         priv->res = request_mem_region(res->start, resource_size(res),
1198                                        dev_name(&pdev->dev));
1199         if (!priv->res) {
1200                 dev_err(&pdev->dev, "Could not reserve memory region\n");
1201                 err = -ENOMEM;
1202                 goto err_req_mem;
1203         }
1204
1205         priv->base = ioremap(res->start, resource_size(res));
1206         if (!priv->base) {
1207                 dev_err(&pdev->dev, "Failed to ioremap ethernet registers\n");
1208                 err = -EIO;
1209                 goto err_ioremap;
1210         }
1211
1212         priv->irq = irq;
1213
1214         /* initialize mdio bus */
1215         priv->mii_bus = mdiobus_alloc();
1216         if (!priv->mii_bus) {
1217                 err = -EIO;
1218                 goto err_alloc_mdiobus;
1219         }
1220
1221         priv->mii_bus->name = "ftgmac100_mdio";
1222         snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "ftgmac100_mii");
1223
1224         priv->mii_bus->priv = netdev;
1225         priv->mii_bus->read = ftgmac100_mdiobus_read;
1226         priv->mii_bus->write = ftgmac100_mdiobus_write;
1227
1228         err = mdiobus_register(priv->mii_bus);
1229         if (err) {
1230                 dev_err(&pdev->dev, "Cannot register MDIO bus!\n");
1231                 goto err_register_mdiobus;
1232         }
1233
1234         err = ftgmac100_mii_probe(priv);
1235         if (err) {
1236                 dev_err(&pdev->dev, "MII Probe failed!\n");
1237                 goto err_mii_probe;
1238         }
1239
1240         /* register network device */
1241         err = register_netdev(netdev);
1242         if (err) {
1243                 dev_err(&pdev->dev, "Failed to register netdev\n");
1244                 goto err_register_netdev;
1245         }
1246
1247         netdev_info(netdev, "irq %d, mapped at %p\n", priv->irq, priv->base);
1248
1249         if (!is_valid_ether_addr(netdev->dev_addr)) {
1250                 eth_hw_addr_random(netdev);
1251                 netdev_info(netdev, "generated random MAC address %pM\n",
1252                             netdev->dev_addr);
1253         }
1254
1255         return 0;
1256
1257 err_register_netdev:
1258         phy_disconnect(netdev->phydev);
1259 err_mii_probe:
1260         mdiobus_unregister(priv->mii_bus);
1261 err_register_mdiobus:
1262         mdiobus_free(priv->mii_bus);
1263 err_alloc_mdiobus:
1264         iounmap(priv->base);
1265 err_ioremap:
1266         release_resource(priv->res);
1267 err_req_mem:
1268         netif_napi_del(&priv->napi);
1269         free_netdev(netdev);
1270 err_alloc_etherdev:
1271         return err;
1272 }
1273
1274 static int __exit ftgmac100_remove(struct platform_device *pdev)
1275 {
1276         struct net_device *netdev;
1277         struct ftgmac100 *priv;
1278
1279         netdev = platform_get_drvdata(pdev);
1280         priv = netdev_priv(netdev);
1281
1282         unregister_netdev(netdev);
1283
1284         phy_disconnect(netdev->phydev);
1285         mdiobus_unregister(priv->mii_bus);
1286         mdiobus_free(priv->mii_bus);
1287
1288         iounmap(priv->base);
1289         release_resource(priv->res);
1290
1291         netif_napi_del(&priv->napi);
1292         free_netdev(netdev);
1293         return 0;
1294 }
1295
1296 static struct platform_driver ftgmac100_driver = {
1297         .probe          = ftgmac100_probe,
1298         .remove         = __exit_p(ftgmac100_remove),
1299         .driver         = {
1300                 .name   = DRV_NAME,
1301         },
1302 };
1303
1304 module_platform_driver(ftgmac100_driver);
1305
1306 MODULE_AUTHOR("Po-Yu Chuang <ratbert@faraday-tech.com>");
1307 MODULE_DESCRIPTION("FTGMAC100 driver");
1308 MODULE_LICENSE("GPL");