2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/string.h>
27 #include <linux/ptrace.h>
28 #include <linux/errno.h>
29 #include <linux/ioport.h>
30 #include <linux/slab.h>
31 #include <linux/interrupt.h>
32 #include <linux/delay.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/skbuff.h>
40 #include <linux/tcp.h>
41 #include <linux/udp.h>
42 #include <linux/icmp.h>
43 #include <linux/spinlock.h>
44 #include <linux/workqueue.h>
45 #include <linux/bitops.h>
47 #include <linux/irq.h>
48 #include <linux/clk.h>
49 #include <linux/platform_device.h>
50 #include <linux/phy.h>
51 #include <linux/fec.h>
53 #include <linux/of_device.h>
54 #include <linux/of_gpio.h>
55 #include <linux/of_mdio.h>
56 #include <linux/of_net.h>
57 #include <linux/regulator/consumer.h>
58 #include <linux/if_vlan.h>
59 #include <linux/pinctrl/consumer.h>
60 #include <linux/prefetch.h>
62 #include <asm/cacheflush.h>
66 static void set_multicast_list(struct net_device *ndev);
67 static void fec_enet_itr_coal_init(struct net_device *ndev);
69 #define DRIVER_NAME "fec"
71 #define FEC_ENET_GET_QUQUE(_x) ((_x == 0) ? 1 : ((_x == 1) ? 2 : 0))
73 /* Pause frame feild and FIFO threshold */
74 #define FEC_ENET_FCE (1 << 5)
75 #define FEC_ENET_RSEM_V 0x84
76 #define FEC_ENET_RSFL_V 16
77 #define FEC_ENET_RAEM_V 0x8
78 #define FEC_ENET_RAFL_V 0x8
79 #define FEC_ENET_OPD_V 0xFFF0
81 /* Controller is ENET-MAC */
82 #define FEC_QUIRK_ENET_MAC (1 << 0)
83 /* Controller needs driver to swap frame */
84 #define FEC_QUIRK_SWAP_FRAME (1 << 1)
85 /* Controller uses gasket */
86 #define FEC_QUIRK_USE_GASKET (1 << 2)
87 /* Controller has GBIT support */
88 #define FEC_QUIRK_HAS_GBIT (1 << 3)
89 /* Controller has extend desc buffer */
90 #define FEC_QUIRK_HAS_BUFDESC_EX (1 << 4)
91 /* Controller has hardware checksum support */
92 #define FEC_QUIRK_HAS_CSUM (1 << 5)
93 /* Controller has hardware vlan support */
94 #define FEC_QUIRK_HAS_VLAN (1 << 6)
95 /* ENET IP errata ERR006358
97 * If the ready bit in the transmit buffer descriptor (TxBD[R]) is previously
98 * detected as not set during a prior frame transmission, then the
99 * ENET_TDAR[TDAR] bit is cleared at a later time, even if additional TxBDs
100 * were added to the ring and the ENET_TDAR[TDAR] bit is set. This results in
101 * frames not being transmitted until there is a 0-to-1 transition on
104 #define FEC_QUIRK_ERR006358 (1 << 7)
107 * i.MX6SX ENET IP add Audio Video Bridging (AVB) feature support.
108 * - Two class indicators on receive with configurable priority
109 * - Two class indicators and line speed timer on transmit allowing
110 * implementation class credit based shapers externally
111 * - Additional DMA registers provisioned to allow managing up to 3
114 #define FEC_QUIRK_HAS_AVB (1 << 8)
115 /* There is a TDAR race condition for mutliQ when the software sets TDAR
116 * and the UDMA clears TDAR simultaneously or in a small window (2-4 cycles).
117 * This will cause the udma_tx and udma_tx_arbiter state machines to hang.
118 * The issue exist at i.MX6SX enet IP.
120 #define FEC_QUIRK_ERR007885 (1 << 9)
122 static struct platform_device_id fec_devtype[] = {
124 /* keep it for coldfire */
129 .driver_data = FEC_QUIRK_USE_GASKET,
135 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME,
138 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
139 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
140 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_ERR006358,
142 .name = "mvf600-fec",
143 .driver_data = FEC_QUIRK_ENET_MAC,
145 .name = "imx6sx-fec",
146 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
147 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM |
148 FEC_QUIRK_HAS_VLAN | FEC_QUIRK_HAS_AVB |
154 MODULE_DEVICE_TABLE(platform, fec_devtype);
157 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
158 IMX27_FEC, /* runs on i.mx27/35/51 */
165 static const struct of_device_id fec_dt_ids[] = {
166 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
167 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
168 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
169 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
170 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], },
171 { .compatible = "fsl,imx6sx-fec", .data = &fec_devtype[IMX6SX_FEC], },
174 MODULE_DEVICE_TABLE(of, fec_dt_ids);
176 static unsigned char macaddr[ETH_ALEN];
177 module_param_array(macaddr, byte, NULL, 0);
178 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
180 #if defined(CONFIG_M5272)
182 * Some hardware gets it MAC address out of local flash memory.
183 * if this is non-zero then assume it is the address to get MAC from.
185 #if defined(CONFIG_NETtel)
186 #define FEC_FLASHMAC 0xf0006006
187 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
188 #define FEC_FLASHMAC 0xf0006000
189 #elif defined(CONFIG_CANCam)
190 #define FEC_FLASHMAC 0xf0020000
191 #elif defined (CONFIG_M5272C3)
192 #define FEC_FLASHMAC (0xffe04000 + 4)
193 #elif defined(CONFIG_MOD5272)
194 #define FEC_FLASHMAC 0xffc0406b
196 #define FEC_FLASHMAC 0
198 #endif /* CONFIG_M5272 */
200 /* The FEC stores dest/src/type/vlan, data, and checksum for receive packets.
202 #define PKT_MAXBUF_SIZE 1522
203 #define PKT_MINBUF_SIZE 64
204 #define PKT_MAXBLR_SIZE 1536
206 /* FEC receive acceleration */
207 #define FEC_RACC_IPDIS (1 << 1)
208 #define FEC_RACC_PRODIS (1 << 2)
209 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS)
212 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
213 * size bits. Other FEC hardware does not, so we need to take that into
214 * account when setting it.
216 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
217 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
218 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
220 #define OPT_FRAME_SIZE 0
223 /* FEC MII MMFR bits definition */
224 #define FEC_MMFR_ST (1 << 30)
225 #define FEC_MMFR_OP_READ (2 << 28)
226 #define FEC_MMFR_OP_WRITE (1 << 28)
227 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
228 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
229 #define FEC_MMFR_TA (2 << 16)
230 #define FEC_MMFR_DATA(v) (v & 0xffff)
232 #define FEC_MII_TIMEOUT 30000 /* us */
234 /* Transmitter timeout */
235 #define TX_TIMEOUT (2 * HZ)
237 #define FEC_PAUSE_FLAG_AUTONEG 0x1
238 #define FEC_PAUSE_FLAG_ENABLE 0x2
240 #define COPYBREAK_DEFAULT 256
242 #define TSO_HEADER_SIZE 128
243 /* Max number of allowed TCP segments for software TSO */
244 #define FEC_MAX_TSO_SEGS 100
245 #define FEC_MAX_SKB_DESCS (FEC_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
247 #define IS_TSO_HEADER(txq, addr) \
248 ((addr >= txq->tso_hdrs_dma) && \
249 (addr < txq->tso_hdrs_dma + txq->tx_ring_size * TSO_HEADER_SIZE))
254 struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp,
255 struct fec_enet_private *fep,
258 struct bufdesc *new_bd = bdp + 1;
259 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp + 1;
260 struct fec_enet_priv_tx_q *txq = fep->tx_queue[queue_id];
261 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[queue_id];
262 struct bufdesc_ex *ex_base;
263 struct bufdesc *base;
266 if (bdp >= txq->tx_bd_base) {
267 base = txq->tx_bd_base;
268 ring_size = txq->tx_ring_size;
269 ex_base = (struct bufdesc_ex *)txq->tx_bd_base;
271 base = rxq->rx_bd_base;
272 ring_size = rxq->rx_ring_size;
273 ex_base = (struct bufdesc_ex *)rxq->rx_bd_base;
277 return (struct bufdesc *)((ex_new_bd >= (ex_base + ring_size)) ?
278 ex_base : ex_new_bd);
280 return (new_bd >= (base + ring_size)) ?
285 struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp,
286 struct fec_enet_private *fep,
289 struct bufdesc *new_bd = bdp - 1;
290 struct bufdesc_ex *ex_new_bd = (struct bufdesc_ex *)bdp - 1;
291 struct fec_enet_priv_tx_q *txq = fep->tx_queue[queue_id];
292 struct fec_enet_priv_rx_q *rxq = fep->rx_queue[queue_id];
293 struct bufdesc_ex *ex_base;
294 struct bufdesc *base;
297 if (bdp >= txq->tx_bd_base) {
298 base = txq->tx_bd_base;
299 ring_size = txq->tx_ring_size;
300 ex_base = (struct bufdesc_ex *)txq->tx_bd_base;
302 base = rxq->rx_bd_base;
303 ring_size = rxq->rx_ring_size;
304 ex_base = (struct bufdesc_ex *)rxq->rx_bd_base;
308 return (struct bufdesc *)((ex_new_bd < ex_base) ?
309 (ex_new_bd + ring_size) : ex_new_bd);
311 return (new_bd < base) ? (new_bd + ring_size) : new_bd;
314 static int fec_enet_get_bd_index(struct bufdesc *base, struct bufdesc *bdp,
315 struct fec_enet_private *fep)
317 return ((const char *)bdp - (const char *)base) / fep->bufdesc_size;
320 static int fec_enet_get_free_txdesc_num(struct fec_enet_private *fep,
321 struct fec_enet_priv_tx_q *txq)
325 entries = ((const char *)txq->dirty_tx -
326 (const char *)txq->cur_tx) / fep->bufdesc_size - 1;
328 return entries > 0 ? entries : entries + txq->tx_ring_size;
331 static void *swap_buffer(void *bufaddr, int len)
334 unsigned int *buf = bufaddr;
336 for (i = 0; i < DIV_ROUND_UP(len, 4); i++, buf++)
337 *buf = cpu_to_be32(*buf);
342 static void fec_dump(struct net_device *ndev)
344 struct fec_enet_private *fep = netdev_priv(ndev);
346 struct fec_enet_priv_tx_q *txq;
349 netdev_info(ndev, "TX ring dump\n");
350 pr_info("Nr SC addr len SKB\n");
352 txq = fep->tx_queue[0];
353 bdp = txq->tx_bd_base;
356 pr_info("%3u %c%c 0x%04x 0x%08lx %4u %p\n",
358 bdp == txq->cur_tx ? 'S' : ' ',
359 bdp == txq->dirty_tx ? 'H' : ' ',
360 bdp->cbd_sc, bdp->cbd_bufaddr, bdp->cbd_datlen,
361 txq->tx_skbuff[index]);
362 bdp = fec_enet_get_nextdesc(bdp, fep, 0);
364 } while (bdp != txq->tx_bd_base);
367 static inline bool is_ipv4_pkt(struct sk_buff *skb)
369 return skb->protocol == htons(ETH_P_IP) && ip_hdr(skb)->version == 4;
373 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev)
375 /* Only run for packets requiring a checksum. */
376 if (skb->ip_summed != CHECKSUM_PARTIAL)
379 if (unlikely(skb_cow_head(skb, 0)))
382 if (is_ipv4_pkt(skb))
383 ip_hdr(skb)->check = 0;
384 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0;
390 fec_enet_txq_submit_frag_skb(struct fec_enet_priv_tx_q *txq,
392 struct net_device *ndev)
394 struct fec_enet_private *fep = netdev_priv(ndev);
395 const struct platform_device_id *id_entry =
396 platform_get_device_id(fep->pdev);
397 struct bufdesc *bdp = txq->cur_tx;
398 struct bufdesc_ex *ebdp;
399 int nr_frags = skb_shinfo(skb)->nr_frags;
400 unsigned short queue = skb_get_queue_mapping(skb);
402 unsigned short status;
403 unsigned int estatus = 0;
404 skb_frag_t *this_frag;
410 for (frag = 0; frag < nr_frags; frag++) {
411 this_frag = &skb_shinfo(skb)->frags[frag];
412 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
413 ebdp = (struct bufdesc_ex *)bdp;
415 status = bdp->cbd_sc;
416 status &= ~BD_ENET_TX_STATS;
417 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
418 frag_len = skb_shinfo(skb)->frags[frag].size;
420 /* Handle the last BD specially */
421 if (frag == nr_frags - 1) {
422 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
423 if (fep->bufdesc_ex) {
424 estatus |= BD_ENET_TX_INT;
425 if (unlikely(skb_shinfo(skb)->tx_flags &
426 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
427 estatus |= BD_ENET_TX_TS;
431 if (fep->bufdesc_ex) {
432 if (id_entry->driver_data & FEC_QUIRK_HAS_AVB)
433 estatus |= FEC_TX_BD_FTYPE(queue);
434 if (skb->ip_summed == CHECKSUM_PARTIAL)
435 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
437 ebdp->cbd_esc = estatus;
440 bufaddr = page_address(this_frag->page.p) + this_frag->page_offset;
442 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
443 if (((unsigned long) bufaddr) & fep->tx_align ||
444 id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) {
445 memcpy(txq->tx_bounce[index], bufaddr, frag_len);
446 bufaddr = txq->tx_bounce[index];
448 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
449 swap_buffer(bufaddr, frag_len);
452 addr = dma_map_single(&fep->pdev->dev, bufaddr, frag_len,
454 if (dma_mapping_error(&fep->pdev->dev, addr)) {
455 dev_kfree_skb_any(skb);
457 netdev_err(ndev, "Tx DMA memory map failed\n");
458 goto dma_mapping_error;
461 bdp->cbd_bufaddr = addr;
462 bdp->cbd_datlen = frag_len;
463 bdp->cbd_sc = status;
472 for (i = 0; i < frag; i++) {
473 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
474 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
475 bdp->cbd_datlen, DMA_TO_DEVICE);
480 static int fec_enet_txq_submit_skb(struct fec_enet_priv_tx_q *txq,
481 struct sk_buff *skb, struct net_device *ndev)
483 struct fec_enet_private *fep = netdev_priv(ndev);
484 const struct platform_device_id *id_entry =
485 platform_get_device_id(fep->pdev);
486 int nr_frags = skb_shinfo(skb)->nr_frags;
487 struct bufdesc *bdp, *last_bdp;
490 unsigned short status;
491 unsigned short buflen;
492 unsigned short queue;
493 unsigned int estatus = 0;
498 entries_free = fec_enet_get_free_txdesc_num(fep, txq);
499 if (entries_free < MAX_SKB_FRAGS + 1) {
500 dev_kfree_skb_any(skb);
502 netdev_err(ndev, "NOT enough BD for SG!\n");
506 /* Protocol checksum off-load for TCP and UDP. */
507 if (fec_enet_clear_csum(skb, ndev)) {
508 dev_kfree_skb_any(skb);
512 /* Fill in a Tx ring entry */
514 status = bdp->cbd_sc;
515 status &= ~BD_ENET_TX_STATS;
517 /* Set buffer length and buffer pointer */
519 buflen = skb_headlen(skb);
521 queue = skb_get_queue_mapping(skb);
522 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
523 if (((unsigned long) bufaddr) & fep->tx_align ||
524 id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) {
525 memcpy(txq->tx_bounce[index], skb->data, buflen);
526 bufaddr = txq->tx_bounce[index];
528 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
529 swap_buffer(bufaddr, buflen);
532 /* Push the data cache so the CPM does not get stale memory data. */
533 addr = dma_map_single(&fep->pdev->dev, bufaddr, buflen, DMA_TO_DEVICE);
534 if (dma_mapping_error(&fep->pdev->dev, addr)) {
535 dev_kfree_skb_any(skb);
537 netdev_err(ndev, "Tx DMA memory map failed\n");
542 ret = fec_enet_txq_submit_frag_skb(txq, skb, ndev);
546 status |= (BD_ENET_TX_INTR | BD_ENET_TX_LAST);
547 if (fep->bufdesc_ex) {
548 estatus = BD_ENET_TX_INT;
549 if (unlikely(skb_shinfo(skb)->tx_flags &
550 SKBTX_HW_TSTAMP && fep->hwts_tx_en))
551 estatus |= BD_ENET_TX_TS;
555 if (fep->bufdesc_ex) {
557 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
559 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
561 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
563 if (id_entry->driver_data & FEC_QUIRK_HAS_AVB)
564 estatus |= FEC_TX_BD_FTYPE(queue);
566 if (skb->ip_summed == CHECKSUM_PARTIAL)
567 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
570 ebdp->cbd_esc = estatus;
573 last_bdp = txq->cur_tx;
574 index = fec_enet_get_bd_index(txq->tx_bd_base, last_bdp, fep);
575 /* Save skb pointer */
576 txq->tx_skbuff[index] = skb;
578 bdp->cbd_datlen = buflen;
579 bdp->cbd_bufaddr = addr;
581 /* Send it on its way. Tell FEC it's ready, interrupt when done,
582 * it's the last BD of the frame, and to put the CRC on the end.
584 status |= (BD_ENET_TX_READY | BD_ENET_TX_TC);
585 bdp->cbd_sc = status;
587 /* If this was the last BD in the ring, start at the beginning again. */
588 bdp = fec_enet_get_nextdesc(last_bdp, fep, queue);
590 skb_tx_timestamp(skb);
594 /* Trigger transmission start */
595 writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue));
601 fec_enet_txq_put_data_tso(struct fec_enet_priv_tx_q *txq, struct sk_buff *skb,
602 struct net_device *ndev,
603 struct bufdesc *bdp, int index, char *data,
604 int size, bool last_tcp, bool is_last)
606 struct fec_enet_private *fep = netdev_priv(ndev);
607 const struct platform_device_id *id_entry =
608 platform_get_device_id(fep->pdev);
609 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
610 unsigned short queue = skb_get_queue_mapping(skb);
611 unsigned short status;
612 unsigned int estatus = 0;
615 status = bdp->cbd_sc;
616 status &= ~BD_ENET_TX_STATS;
618 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
620 if (((unsigned long) data) & fep->tx_align ||
621 id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) {
622 memcpy(txq->tx_bounce[index], data, size);
623 data = txq->tx_bounce[index];
625 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
626 swap_buffer(data, size);
629 addr = dma_map_single(&fep->pdev->dev, data, size, DMA_TO_DEVICE);
630 if (dma_mapping_error(&fep->pdev->dev, addr)) {
631 dev_kfree_skb_any(skb);
633 netdev_err(ndev, "Tx DMA memory map failed\n");
634 return NETDEV_TX_BUSY;
637 bdp->cbd_datlen = size;
638 bdp->cbd_bufaddr = addr;
640 if (fep->bufdesc_ex) {
641 if (id_entry->driver_data & FEC_QUIRK_HAS_AVB)
642 estatus |= FEC_TX_BD_FTYPE(queue);
643 if (skb->ip_summed == CHECKSUM_PARTIAL)
644 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
646 ebdp->cbd_esc = estatus;
649 /* Handle the last BD specially */
651 status |= (BD_ENET_TX_LAST | BD_ENET_TX_TC);
653 status |= BD_ENET_TX_INTR;
655 ebdp->cbd_esc |= BD_ENET_TX_INT;
658 bdp->cbd_sc = status;
664 fec_enet_txq_put_hdr_tso(struct fec_enet_priv_tx_q *txq,
665 struct sk_buff *skb, struct net_device *ndev,
666 struct bufdesc *bdp, int index)
668 struct fec_enet_private *fep = netdev_priv(ndev);
669 const struct platform_device_id *id_entry =
670 platform_get_device_id(fep->pdev);
671 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
672 struct bufdesc_ex *ebdp = container_of(bdp, struct bufdesc_ex, desc);
673 unsigned short queue = skb_get_queue_mapping(skb);
675 unsigned long dmabuf;
676 unsigned short status;
677 unsigned int estatus = 0;
679 status = bdp->cbd_sc;
680 status &= ~BD_ENET_TX_STATS;
681 status |= (BD_ENET_TX_TC | BD_ENET_TX_READY);
683 bufaddr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
684 dmabuf = txq->tso_hdrs_dma + index * TSO_HEADER_SIZE;
685 if (((unsigned long)bufaddr) & fep->tx_align ||
686 id_entry->driver_data & FEC_QUIRK_SWAP_FRAME) {
687 memcpy(txq->tx_bounce[index], skb->data, hdr_len);
688 bufaddr = txq->tx_bounce[index];
690 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
691 swap_buffer(bufaddr, hdr_len);
693 dmabuf = dma_map_single(&fep->pdev->dev, bufaddr,
694 hdr_len, DMA_TO_DEVICE);
695 if (dma_mapping_error(&fep->pdev->dev, dmabuf)) {
696 dev_kfree_skb_any(skb);
698 netdev_err(ndev, "Tx DMA memory map failed\n");
699 return NETDEV_TX_BUSY;
703 bdp->cbd_bufaddr = dmabuf;
704 bdp->cbd_datlen = hdr_len;
706 if (fep->bufdesc_ex) {
707 if (id_entry->driver_data & FEC_QUIRK_HAS_AVB)
708 estatus |= FEC_TX_BD_FTYPE(queue);
709 if (skb->ip_summed == CHECKSUM_PARTIAL)
710 estatus |= BD_ENET_TX_PINS | BD_ENET_TX_IINS;
712 ebdp->cbd_esc = estatus;
715 bdp->cbd_sc = status;
720 static int fec_enet_txq_submit_tso(struct fec_enet_priv_tx_q *txq,
722 struct net_device *ndev)
724 struct fec_enet_private *fep = netdev_priv(ndev);
725 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
726 int total_len, data_left;
727 struct bufdesc *bdp = txq->cur_tx;
728 unsigned short queue = skb_get_queue_mapping(skb);
730 unsigned int index = 0;
732 const struct platform_device_id *id_entry =
733 platform_get_device_id(fep->pdev);
735 if (tso_count_descs(skb) >= fec_enet_get_free_txdesc_num(fep, txq)) {
736 dev_kfree_skb_any(skb);
738 netdev_err(ndev, "NOT enough BD for TSO!\n");
742 /* Protocol checksum off-load for TCP and UDP. */
743 if (fec_enet_clear_csum(skb, ndev)) {
744 dev_kfree_skb_any(skb);
748 /* Initialize the TSO handler, and prepare the first payload */
749 tso_start(skb, &tso);
751 total_len = skb->len - hdr_len;
752 while (total_len > 0) {
755 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
756 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
757 total_len -= data_left;
759 /* prepare packet headers: MAC + IP + TCP */
760 hdr = txq->tso_hdrs + index * TSO_HEADER_SIZE;
761 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
762 ret = fec_enet_txq_put_hdr_tso(txq, skb, ndev, bdp, index);
766 while (data_left > 0) {
769 size = min_t(int, tso.size, data_left);
770 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
771 index = fec_enet_get_bd_index(txq->tx_bd_base,
773 ret = fec_enet_txq_put_data_tso(txq, skb, ndev,
782 tso_build_data(skb, &tso, size);
785 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
788 /* Save skb pointer */
789 txq->tx_skbuff[index] = skb;
791 skb_tx_timestamp(skb);
794 /* Trigger transmission start */
795 if (!(id_entry->driver_data & FEC_QUIRK_ERR007885) ||
796 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) ||
797 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) ||
798 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)) ||
799 !readl(fep->hwp + FEC_X_DES_ACTIVE(queue)))
800 writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue));
805 /* TODO: Release all used data descriptors for TSO */
810 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
812 struct fec_enet_private *fep = netdev_priv(ndev);
814 unsigned short queue;
815 struct fec_enet_priv_tx_q *txq;
816 struct netdev_queue *nq;
819 queue = skb_get_queue_mapping(skb);
820 txq = fep->tx_queue[queue];
821 nq = netdev_get_tx_queue(ndev, queue);
824 ret = fec_enet_txq_submit_tso(txq, skb, ndev);
826 ret = fec_enet_txq_submit_skb(txq, skb, ndev);
830 entries_free = fec_enet_get_free_txdesc_num(fep, txq);
831 if (entries_free <= txq->tx_stop_threshold)
832 netif_tx_stop_queue(nq);
837 /* Init RX & TX buffer descriptors
839 static void fec_enet_bd_init(struct net_device *dev)
841 struct fec_enet_private *fep = netdev_priv(dev);
842 struct fec_enet_priv_tx_q *txq;
843 struct fec_enet_priv_rx_q *rxq;
848 for (q = 0; q < fep->num_rx_queues; q++) {
849 /* Initialize the receive buffer descriptors. */
850 rxq = fep->rx_queue[q];
851 bdp = rxq->rx_bd_base;
853 for (i = 0; i < rxq->rx_ring_size; i++) {
855 /* Initialize the BD for every fragment in the page. */
856 if (bdp->cbd_bufaddr)
857 bdp->cbd_sc = BD_ENET_RX_EMPTY;
860 bdp = fec_enet_get_nextdesc(bdp, fep, q);
863 /* Set the last buffer to wrap */
864 bdp = fec_enet_get_prevdesc(bdp, fep, q);
865 bdp->cbd_sc |= BD_SC_WRAP;
867 rxq->cur_rx = rxq->rx_bd_base;
870 for (q = 0; q < fep->num_tx_queues; q++) {
871 /* ...and the same for transmit */
872 txq = fep->tx_queue[q];
873 bdp = txq->tx_bd_base;
876 for (i = 0; i < txq->tx_ring_size; i++) {
877 /* Initialize the BD for every fragment in the page. */
879 if (txq->tx_skbuff[i]) {
880 dev_kfree_skb_any(txq->tx_skbuff[i]);
881 txq->tx_skbuff[i] = NULL;
883 bdp->cbd_bufaddr = 0;
884 bdp = fec_enet_get_nextdesc(bdp, fep, q);
887 /* Set the last buffer to wrap */
888 bdp = fec_enet_get_prevdesc(bdp, fep, q);
889 bdp->cbd_sc |= BD_SC_WRAP;
894 static void fec_enet_active_rxring(struct net_device *ndev)
896 struct fec_enet_private *fep = netdev_priv(ndev);
899 for (i = 0; i < fep->num_rx_queues; i++)
900 writel(0, fep->hwp + FEC_R_DES_ACTIVE(i));
903 static void fec_enet_enable_ring(struct net_device *ndev)
905 struct fec_enet_private *fep = netdev_priv(ndev);
906 struct fec_enet_priv_tx_q *txq;
907 struct fec_enet_priv_rx_q *rxq;
910 for (i = 0; i < fep->num_rx_queues; i++) {
911 rxq = fep->rx_queue[i];
912 writel(rxq->bd_dma, fep->hwp + FEC_R_DES_START(i));
916 writel(RCMR_MATCHEN | RCMR_CMP(i),
917 fep->hwp + FEC_RCMR(i));
920 for (i = 0; i < fep->num_tx_queues; i++) {
921 txq = fep->tx_queue[i];
922 writel(txq->bd_dma, fep->hwp + FEC_X_DES_START(i));
926 writel(DMA_CLASS_EN | IDLE_SLOPE(i),
927 fep->hwp + FEC_DMA_CFG(i));
931 static void fec_enet_reset_skb(struct net_device *ndev)
933 struct fec_enet_private *fep = netdev_priv(ndev);
934 struct fec_enet_priv_tx_q *txq;
937 for (i = 0; i < fep->num_tx_queues; i++) {
938 txq = fep->tx_queue[i];
940 for (j = 0; j < txq->tx_ring_size; j++) {
941 if (txq->tx_skbuff[j]) {
942 dev_kfree_skb_any(txq->tx_skbuff[j]);
943 txq->tx_skbuff[j] = NULL;
950 * This function is called to start or restart the FEC during a link
951 * change, transmit timeout, or to reconfigure the FEC. The network
952 * packet processing for this device must be stopped before this call.
955 fec_restart(struct net_device *ndev)
957 struct fec_enet_private *fep = netdev_priv(ndev);
958 const struct platform_device_id *id_entry =
959 platform_get_device_id(fep->pdev);
962 u32 rcntl = OPT_FRAME_SIZE | 0x04;
963 u32 ecntl = 0x2; /* ETHEREN */
965 /* Whack a reset. We should wait for this.
966 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
967 * instead of reset MAC itself.
969 if (id_entry && id_entry->driver_data & FEC_QUIRK_HAS_AVB) {
970 writel(0, fep->hwp + FEC_ECNTRL);
972 writel(1, fep->hwp + FEC_ECNTRL);
977 * enet-mac reset will reset mac address registers too,
978 * so need to reconfigure it.
980 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
981 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
982 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
983 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
986 /* Clear any outstanding interrupt. */
987 writel(0xffc00000, fep->hwp + FEC_IEVENT);
989 /* Set maximum receive buffer size. */
990 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
992 fec_enet_bd_init(ndev);
994 fec_enet_enable_ring(ndev);
996 /* Reset tx SKB buffers. */
997 fec_enet_reset_skb(ndev);
999 /* Enable MII mode */
1000 if (fep->full_duplex == DUPLEX_FULL) {
1002 writel(0x04, fep->hwp + FEC_X_CNTRL);
1004 /* No Rcv on Xmit */
1006 writel(0x0, fep->hwp + FEC_X_CNTRL);
1010 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1012 #if !defined(CONFIG_M5272)
1013 /* set RX checksum */
1014 val = readl(fep->hwp + FEC_RACC);
1015 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED)
1016 val |= FEC_RACC_OPTIONS;
1018 val &= ~FEC_RACC_OPTIONS;
1019 writel(val, fep->hwp + FEC_RACC);
1023 * The phy interface and speed need to get configured
1024 * differently on enet-mac.
1026 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
1027 /* Enable flow control and length check */
1028 rcntl |= 0x40000000 | 0x00000020;
1030 /* RGMII, RMII or MII */
1031 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII)
1033 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
1038 /* 1G, 100M or 10M */
1040 if (fep->phy_dev->speed == SPEED_1000)
1042 else if (fep->phy_dev->speed == SPEED_100)
1048 #ifdef FEC_MIIGSK_ENR
1049 if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) {
1051 /* disable the gasket and wait */
1052 writel(0, fep->hwp + FEC_MIIGSK_ENR);
1053 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
1057 * configure the gasket:
1058 * RMII, 50 MHz, no loopback, no echo
1059 * MII, 25 MHz, no loopback, no echo
1061 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
1062 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
1063 if (fep->phy_dev && fep->phy_dev->speed == SPEED_10)
1064 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
1065 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
1067 /* re-enable the gasket */
1068 writel(2, fep->hwp + FEC_MIIGSK_ENR);
1073 #if !defined(CONFIG_M5272)
1074 /* enable pause frame*/
1075 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
1076 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
1077 fep->phy_dev && fep->phy_dev->pause)) {
1078 rcntl |= FEC_ENET_FCE;
1080 /* set FIFO threshold parameter to reduce overrun */
1081 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
1082 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
1083 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
1084 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
1087 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
1089 rcntl &= ~FEC_ENET_FCE;
1091 #endif /* !defined(CONFIG_M5272) */
1093 writel(rcntl, fep->hwp + FEC_R_CNTRL);
1095 /* Setup multicast filter. */
1096 set_multicast_list(ndev);
1097 #ifndef CONFIG_M5272
1098 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
1099 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
1102 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
1103 /* enable ENET endian swap */
1105 /* enable ENET store and forward mode */
1106 writel(1 << 8, fep->hwp + FEC_X_WMRK);
1109 if (fep->bufdesc_ex)
1112 #ifndef CONFIG_M5272
1113 /* Enable the MIB statistic event counters */
1114 writel(0 << 31, fep->hwp + FEC_MIB_CTRLSTAT);
1117 /* And last, enable the transmit and receive processing */
1118 writel(ecntl, fep->hwp + FEC_ECNTRL);
1119 fec_enet_active_rxring(ndev);
1121 if (fep->bufdesc_ex)
1122 fec_ptp_start_cyclecounter(ndev);
1124 /* Enable interrupts we wish to service */
1125 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1127 /* Init the interrupt coalescing */
1128 fec_enet_itr_coal_init(ndev);
1133 fec_stop(struct net_device *ndev)
1135 struct fec_enet_private *fep = netdev_priv(ndev);
1136 const struct platform_device_id *id_entry =
1137 platform_get_device_id(fep->pdev);
1138 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
1140 /* We cannot expect a graceful transmit stop without link !!! */
1142 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
1144 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
1145 netdev_err(ndev, "Graceful transmit stop did not complete!\n");
1148 /* Whack a reset. We should wait for this.
1149 * For i.MX6SX SOC, enet use AXI bus, we use disable MAC
1150 * instead of reset MAC itself.
1152 if (id_entry && id_entry->driver_data & FEC_QUIRK_HAS_AVB) {
1153 writel(0, fep->hwp + FEC_ECNTRL);
1155 writel(1, fep->hwp + FEC_ECNTRL);
1158 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1159 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1161 /* We have to keep ENET enabled to have MII interrupt stay working */
1162 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
1163 writel(2, fep->hwp + FEC_ECNTRL);
1164 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
1170 fec_timeout(struct net_device *ndev)
1172 struct fec_enet_private *fep = netdev_priv(ndev);
1176 ndev->stats.tx_errors++;
1178 schedule_work(&fep->tx_timeout_work);
1181 static void fec_enet_timeout_work(struct work_struct *work)
1183 struct fec_enet_private *fep =
1184 container_of(work, struct fec_enet_private, tx_timeout_work);
1185 struct net_device *ndev = fep->netdev;
1188 if (netif_device_present(ndev) || netif_running(ndev)) {
1189 napi_disable(&fep->napi);
1190 netif_tx_lock_bh(ndev);
1192 netif_wake_queue(ndev);
1193 netif_tx_unlock_bh(ndev);
1194 napi_enable(&fep->napi);
1200 fec_enet_hwtstamp(struct fec_enet_private *fep, unsigned ts,
1201 struct skb_shared_hwtstamps *hwtstamps)
1203 unsigned long flags;
1206 spin_lock_irqsave(&fep->tmreg_lock, flags);
1207 ns = timecounter_cyc2time(&fep->tc, ts);
1208 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
1210 memset(hwtstamps, 0, sizeof(*hwtstamps));
1211 hwtstamps->hwtstamp = ns_to_ktime(ns);
1215 fec_enet_tx_queue(struct net_device *ndev, u16 queue_id)
1217 struct fec_enet_private *fep;
1218 struct bufdesc *bdp;
1219 unsigned short status;
1220 struct sk_buff *skb;
1221 struct fec_enet_priv_tx_q *txq;
1222 struct netdev_queue *nq;
1226 fep = netdev_priv(ndev);
1228 queue_id = FEC_ENET_GET_QUQUE(queue_id);
1230 txq = fep->tx_queue[queue_id];
1231 /* get next bdp of dirty_tx */
1232 nq = netdev_get_tx_queue(ndev, queue_id);
1233 bdp = txq->dirty_tx;
1235 /* get next bdp of dirty_tx */
1236 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
1238 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
1240 /* current queue is empty */
1241 if (bdp == txq->cur_tx)
1244 index = fec_enet_get_bd_index(txq->tx_bd_base, bdp, fep);
1246 skb = txq->tx_skbuff[index];
1247 txq->tx_skbuff[index] = NULL;
1248 if (!IS_TSO_HEADER(txq, bdp->cbd_bufaddr))
1249 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
1250 bdp->cbd_datlen, DMA_TO_DEVICE);
1251 bdp->cbd_bufaddr = 0;
1253 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
1257 /* Check for errors. */
1258 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
1259 BD_ENET_TX_RL | BD_ENET_TX_UN |
1261 ndev->stats.tx_errors++;
1262 if (status & BD_ENET_TX_HB) /* No heartbeat */
1263 ndev->stats.tx_heartbeat_errors++;
1264 if (status & BD_ENET_TX_LC) /* Late collision */
1265 ndev->stats.tx_window_errors++;
1266 if (status & BD_ENET_TX_RL) /* Retrans limit */
1267 ndev->stats.tx_aborted_errors++;
1268 if (status & BD_ENET_TX_UN) /* Underrun */
1269 ndev->stats.tx_fifo_errors++;
1270 if (status & BD_ENET_TX_CSL) /* Carrier lost */
1271 ndev->stats.tx_carrier_errors++;
1273 ndev->stats.tx_packets++;
1274 ndev->stats.tx_bytes += skb->len;
1277 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
1279 struct skb_shared_hwtstamps shhwtstamps;
1280 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1282 fec_enet_hwtstamp(fep, ebdp->ts, &shhwtstamps);
1283 skb_tstamp_tx(skb, &shhwtstamps);
1286 /* Deferred means some collisions occurred during transmit,
1287 * but we eventually sent the packet OK.
1289 if (status & BD_ENET_TX_DEF)
1290 ndev->stats.collisions++;
1292 /* Free the sk buffer associated with this last transmit */
1293 dev_kfree_skb_any(skb);
1295 txq->dirty_tx = bdp;
1297 /* Update pointer to next buffer descriptor to be transmitted */
1298 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
1300 /* Since we have freed up a buffer, the ring is no longer full
1302 if (netif_queue_stopped(ndev)) {
1303 entries_free = fec_enet_get_free_txdesc_num(fep, txq);
1304 if (entries_free >= txq->tx_wake_threshold)
1305 netif_tx_wake_queue(nq);
1309 /* ERR006538: Keep the transmitter going */
1310 if (bdp != txq->cur_tx &&
1311 readl(fep->hwp + FEC_X_DES_ACTIVE(queue_id)) == 0)
1312 writel(0, fep->hwp + FEC_X_DES_ACTIVE(queue_id));
1316 fec_enet_tx(struct net_device *ndev)
1318 struct fec_enet_private *fep = netdev_priv(ndev);
1320 /* First process class A queue, then Class B and Best Effort queue */
1321 for_each_set_bit(queue_id, &fep->work_tx, FEC_ENET_MAX_TX_QS) {
1322 clear_bit(queue_id, &fep->work_tx);
1323 fec_enet_tx_queue(ndev, queue_id);
1329 fec_enet_new_rxbdp(struct net_device *ndev, struct bufdesc *bdp, struct sk_buff *skb)
1331 struct fec_enet_private *fep = netdev_priv(ndev);
1334 off = ((unsigned long)skb->data) & fep->rx_align;
1336 skb_reserve(skb, fep->rx_align + 1 - off);
1338 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data,
1339 FEC_ENET_RX_FRSIZE - fep->rx_align,
1341 if (dma_mapping_error(&fep->pdev->dev, bdp->cbd_bufaddr)) {
1342 if (net_ratelimit())
1343 netdev_err(ndev, "Rx DMA memory map failed\n");
1350 static bool fec_enet_copybreak(struct net_device *ndev, struct sk_buff **skb,
1351 struct bufdesc *bdp, u32 length)
1353 struct fec_enet_private *fep = netdev_priv(ndev);
1354 struct sk_buff *new_skb;
1356 if (length > fep->rx_copybreak)
1359 new_skb = netdev_alloc_skb(ndev, length);
1363 dma_sync_single_for_cpu(&fep->pdev->dev, bdp->cbd_bufaddr,
1364 FEC_ENET_RX_FRSIZE - fep->rx_align,
1366 memcpy(new_skb->data, (*skb)->data, length);
1372 /* During a receive, the cur_rx points to the current incoming buffer.
1373 * When we update through the ring, if the next incoming buffer has
1374 * not been given to the system, we just set the empty indicator,
1375 * effectively tossing the packet.
1378 fec_enet_rx_queue(struct net_device *ndev, int budget, u16 queue_id)
1380 struct fec_enet_private *fep = netdev_priv(ndev);
1381 const struct platform_device_id *id_entry =
1382 platform_get_device_id(fep->pdev);
1383 struct fec_enet_priv_rx_q *rxq;
1384 struct bufdesc *bdp;
1385 unsigned short status;
1386 struct sk_buff *skb_new = NULL;
1387 struct sk_buff *skb;
1390 int pkt_received = 0;
1391 struct bufdesc_ex *ebdp = NULL;
1392 bool vlan_packet_rcvd = false;
1400 queue_id = FEC_ENET_GET_QUQUE(queue_id);
1401 rxq = fep->rx_queue[queue_id];
1403 /* First, grab all of the stats for the incoming packet.
1404 * These get messed up if we get called due to a busy condition.
1408 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
1410 if (pkt_received >= budget)
1414 /* Since we have allocated space to hold a complete frame,
1415 * the last indicator should be set.
1417 if ((status & BD_ENET_RX_LAST) == 0)
1418 netdev_err(ndev, "rcv is not +last\n");
1421 /* Check for errors. */
1422 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
1423 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
1424 ndev->stats.rx_errors++;
1425 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
1426 /* Frame too long or too short. */
1427 ndev->stats.rx_length_errors++;
1429 if (status & BD_ENET_RX_NO) /* Frame alignment */
1430 ndev->stats.rx_frame_errors++;
1431 if (status & BD_ENET_RX_CR) /* CRC Error */
1432 ndev->stats.rx_crc_errors++;
1433 if (status & BD_ENET_RX_OV) /* FIFO overrun */
1434 ndev->stats.rx_fifo_errors++;
1437 /* Report late collisions as a frame error.
1438 * On this error, the BD is closed, but we don't know what we
1439 * have in the buffer. So, just drop this frame on the floor.
1441 if (status & BD_ENET_RX_CL) {
1442 ndev->stats.rx_errors++;
1443 ndev->stats.rx_frame_errors++;
1444 goto rx_processing_done;
1447 /* Process the incoming frame. */
1448 ndev->stats.rx_packets++;
1449 pkt_len = bdp->cbd_datlen;
1450 ndev->stats.rx_bytes += pkt_len;
1452 index = fec_enet_get_bd_index(rxq->rx_bd_base, bdp, fep);
1453 skb = rxq->rx_skbuff[index];
1455 /* The packet length includes FCS, but we don't want to
1456 * include that when passing upstream as it messes up
1457 * bridging applications.
1459 is_copybreak = fec_enet_copybreak(ndev, &skb, bdp, pkt_len - 4);
1460 if (!is_copybreak) {
1461 skb_new = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
1462 if (unlikely(!skb_new)) {
1463 ndev->stats.rx_dropped++;
1464 goto rx_processing_done;
1466 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
1467 FEC_ENET_RX_FRSIZE - fep->rx_align,
1471 prefetch(skb->data - NET_IP_ALIGN);
1472 skb_put(skb, pkt_len - 4);
1474 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
1475 swap_buffer(data, pkt_len);
1477 /* Extract the enhanced buffer descriptor */
1479 if (fep->bufdesc_ex)
1480 ebdp = (struct bufdesc_ex *)bdp;
1482 /* If this is a VLAN packet remove the VLAN Tag */
1483 vlan_packet_rcvd = false;
1484 if ((ndev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1485 fep->bufdesc_ex && (ebdp->cbd_esc & BD_ENET_RX_VLAN)) {
1486 /* Push and remove the vlan tag */
1487 struct vlan_hdr *vlan_header =
1488 (struct vlan_hdr *) (data + ETH_HLEN);
1489 vlan_tag = ntohs(vlan_header->h_vlan_TCI);
1491 vlan_packet_rcvd = true;
1493 skb_copy_to_linear_data_offset(skb, VLAN_HLEN,
1494 data, (2 * ETH_ALEN));
1495 skb_pull(skb, VLAN_HLEN);
1498 skb->protocol = eth_type_trans(skb, ndev);
1500 /* Get receive timestamp from the skb */
1501 if (fep->hwts_rx_en && fep->bufdesc_ex)
1502 fec_enet_hwtstamp(fep, ebdp->ts,
1503 skb_hwtstamps(skb));
1505 if (fep->bufdesc_ex &&
1506 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
1507 if (!(ebdp->cbd_esc & FLAG_RX_CSUM_ERROR)) {
1508 /* don't check it */
1509 skb->ip_summed = CHECKSUM_UNNECESSARY;
1511 skb_checksum_none_assert(skb);
1515 /* Handle received VLAN packets */
1516 if (vlan_packet_rcvd)
1517 __vlan_hwaccel_put_tag(skb,
1521 napi_gro_receive(&fep->napi, skb);
1524 dma_sync_single_for_device(&fep->pdev->dev, bdp->cbd_bufaddr,
1525 FEC_ENET_RX_FRSIZE - fep->rx_align,
1528 rxq->rx_skbuff[index] = skb_new;
1529 fec_enet_new_rxbdp(ndev, bdp, skb_new);
1533 /* Clear the status flags for this buffer */
1534 status &= ~BD_ENET_RX_STATS;
1536 /* Mark the buffer empty */
1537 status |= BD_ENET_RX_EMPTY;
1538 bdp->cbd_sc = status;
1540 if (fep->bufdesc_ex) {
1541 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1543 ebdp->cbd_esc = BD_ENET_RX_INT;
1548 /* Update BD pointer to next entry */
1549 bdp = fec_enet_get_nextdesc(bdp, fep, queue_id);
1551 /* Doing this here will keep the FEC running while we process
1552 * incoming frames. On a heavily loaded network, we should be
1553 * able to keep up at the expense of system resources.
1555 writel(0, fep->hwp + FEC_R_DES_ACTIVE(queue_id));
1558 return pkt_received;
1562 fec_enet_rx(struct net_device *ndev, int budget)
1564 int pkt_received = 0;
1566 struct fec_enet_private *fep = netdev_priv(ndev);
1568 for_each_set_bit(queue_id, &fep->work_rx, FEC_ENET_MAX_RX_QS) {
1569 clear_bit(queue_id, &fep->work_rx);
1570 pkt_received += fec_enet_rx_queue(ndev,
1571 budget - pkt_received, queue_id);
1573 return pkt_received;
1577 fec_enet_collect_events(struct fec_enet_private *fep, uint int_events)
1579 if (int_events == 0)
1582 if (int_events & FEC_ENET_RXF)
1583 fep->work_rx |= (1 << 2);
1584 if (int_events & FEC_ENET_RXF_1)
1585 fep->work_rx |= (1 << 0);
1586 if (int_events & FEC_ENET_RXF_2)
1587 fep->work_rx |= (1 << 1);
1589 if (int_events & FEC_ENET_TXF)
1590 fep->work_tx |= (1 << 2);
1591 if (int_events & FEC_ENET_TXF_1)
1592 fep->work_tx |= (1 << 0);
1593 if (int_events & FEC_ENET_TXF_2)
1594 fep->work_tx |= (1 << 1);
1600 fec_enet_interrupt(int irq, void *dev_id)
1602 struct net_device *ndev = dev_id;
1603 struct fec_enet_private *fep = netdev_priv(ndev);
1604 const unsigned napi_mask = FEC_ENET_RXF | FEC_ENET_TXF;
1606 irqreturn_t ret = IRQ_NONE;
1608 int_events = readl(fep->hwp + FEC_IEVENT);
1609 writel(int_events & ~napi_mask, fep->hwp + FEC_IEVENT);
1610 fec_enet_collect_events(fep, int_events);
1612 if (int_events & napi_mask) {
1615 /* Disable the NAPI interrupts */
1616 writel(FEC_ENET_MII, fep->hwp + FEC_IMASK);
1617 napi_schedule(&fep->napi);
1620 if (int_events & FEC_ENET_MII) {
1622 complete(&fep->mdio_done);
1625 fec_ptp_check_pps_event(fep);
1630 static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
1632 struct net_device *ndev = napi->dev;
1633 struct fec_enet_private *fep = netdev_priv(ndev);
1637 * Clear any pending transmit or receive interrupts before
1638 * processing the rings to avoid racing with the hardware.
1640 writel(FEC_ENET_RXF | FEC_ENET_TXF, fep->hwp + FEC_IEVENT);
1642 pkts = fec_enet_rx(ndev, budget);
1646 if (pkts < budget) {
1647 napi_complete(napi);
1648 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
1653 /* ------------------------------------------------------------------------- */
1654 static void fec_get_mac(struct net_device *ndev)
1656 struct fec_enet_private *fep = netdev_priv(ndev);
1657 struct fec_platform_data *pdata = dev_get_platdata(&fep->pdev->dev);
1658 unsigned char *iap, tmpaddr[ETH_ALEN];
1661 * try to get mac address in following order:
1663 * 1) module parameter via kernel command line in form
1664 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
1669 * 2) from device tree data
1671 if (!is_valid_ether_addr(iap)) {
1672 struct device_node *np = fep->pdev->dev.of_node;
1674 const char *mac = of_get_mac_address(np);
1676 iap = (unsigned char *) mac;
1681 * 3) from flash or fuse (via platform data)
1683 if (!is_valid_ether_addr(iap)) {
1686 iap = (unsigned char *)FEC_FLASHMAC;
1689 iap = (unsigned char *)&pdata->mac;
1694 * 4) FEC mac registers set by bootloader
1696 if (!is_valid_ether_addr(iap)) {
1697 *((__be32 *) &tmpaddr[0]) =
1698 cpu_to_be32(readl(fep->hwp + FEC_ADDR_LOW));
1699 *((__be16 *) &tmpaddr[4]) =
1700 cpu_to_be16(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
1705 * 5) random mac address
1707 if (!is_valid_ether_addr(iap)) {
1708 /* Report it and use a random ethernet address instead */
1709 netdev_err(ndev, "Invalid MAC address: %pM\n", iap);
1710 eth_hw_addr_random(ndev);
1711 netdev_info(ndev, "Using random MAC address: %pM\n",
1716 memcpy(ndev->dev_addr, iap, ETH_ALEN);
1718 /* Adjust MAC if using macaddr */
1720 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
1723 /* ------------------------------------------------------------------------- */
1728 static void fec_enet_adjust_link(struct net_device *ndev)
1730 struct fec_enet_private *fep = netdev_priv(ndev);
1731 struct phy_device *phy_dev = fep->phy_dev;
1732 int status_change = 0;
1734 /* Prevent a state halted on mii error */
1735 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
1736 phy_dev->state = PHY_RESUMING;
1741 * If the netdev is down, or is going down, we're not interested
1742 * in link state events, so just mark our idea of the link as down
1743 * and ignore the event.
1745 if (!netif_running(ndev) || !netif_device_present(ndev)) {
1747 } else if (phy_dev->link) {
1749 fep->link = phy_dev->link;
1753 if (fep->full_duplex != phy_dev->duplex) {
1754 fep->full_duplex = phy_dev->duplex;
1758 if (phy_dev->speed != fep->speed) {
1759 fep->speed = phy_dev->speed;
1763 /* if any of the above changed restart the FEC */
1764 if (status_change) {
1765 napi_disable(&fep->napi);
1766 netif_tx_lock_bh(ndev);
1768 netif_wake_queue(ndev);
1769 netif_tx_unlock_bh(ndev);
1770 napi_enable(&fep->napi);
1774 napi_disable(&fep->napi);
1775 netif_tx_lock_bh(ndev);
1777 netif_tx_unlock_bh(ndev);
1778 napi_enable(&fep->napi);
1779 fep->link = phy_dev->link;
1785 phy_print_status(phy_dev);
1788 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1790 struct fec_enet_private *fep = bus->priv;
1791 unsigned long time_left;
1793 fep->mii_timeout = 0;
1794 init_completion(&fep->mdio_done);
1796 /* start a read op */
1797 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
1798 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1799 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
1801 /* wait for end of transfer */
1802 time_left = wait_for_completion_timeout(&fep->mdio_done,
1803 usecs_to_jiffies(FEC_MII_TIMEOUT));
1804 if (time_left == 0) {
1805 fep->mii_timeout = 1;
1806 netdev_err(fep->netdev, "MDIO read timeout\n");
1811 return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
1814 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
1817 struct fec_enet_private *fep = bus->priv;
1818 unsigned long time_left;
1820 fep->mii_timeout = 0;
1821 init_completion(&fep->mdio_done);
1823 /* start a write op */
1824 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
1825 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1826 FEC_MMFR_TA | FEC_MMFR_DATA(value),
1827 fep->hwp + FEC_MII_DATA);
1829 /* wait for end of transfer */
1830 time_left = wait_for_completion_timeout(&fep->mdio_done,
1831 usecs_to_jiffies(FEC_MII_TIMEOUT));
1832 if (time_left == 0) {
1833 fep->mii_timeout = 1;
1834 netdev_err(fep->netdev, "MDIO write timeout\n");
1841 static int fec_enet_clk_enable(struct net_device *ndev, bool enable)
1843 struct fec_enet_private *fep = netdev_priv(ndev);
1847 ret = clk_prepare_enable(fep->clk_ahb);
1850 ret = clk_prepare_enable(fep->clk_ipg);
1852 goto failed_clk_ipg;
1853 if (fep->clk_enet_out) {
1854 ret = clk_prepare_enable(fep->clk_enet_out);
1856 goto failed_clk_enet_out;
1859 mutex_lock(&fep->ptp_clk_mutex);
1860 ret = clk_prepare_enable(fep->clk_ptp);
1862 mutex_unlock(&fep->ptp_clk_mutex);
1863 goto failed_clk_ptp;
1865 fep->ptp_clk_on = true;
1867 mutex_unlock(&fep->ptp_clk_mutex);
1870 ret = clk_prepare_enable(fep->clk_ref);
1872 goto failed_clk_ref;
1875 clk_disable_unprepare(fep->clk_ahb);
1876 clk_disable_unprepare(fep->clk_ipg);
1877 if (fep->clk_enet_out)
1878 clk_disable_unprepare(fep->clk_enet_out);
1880 mutex_lock(&fep->ptp_clk_mutex);
1881 clk_disable_unprepare(fep->clk_ptp);
1882 fep->ptp_clk_on = false;
1883 mutex_unlock(&fep->ptp_clk_mutex);
1886 clk_disable_unprepare(fep->clk_ref);
1893 clk_disable_unprepare(fep->clk_ref);
1895 if (fep->clk_enet_out)
1896 clk_disable_unprepare(fep->clk_enet_out);
1897 failed_clk_enet_out:
1898 clk_disable_unprepare(fep->clk_ipg);
1900 clk_disable_unprepare(fep->clk_ahb);
1905 static int fec_enet_mii_probe(struct net_device *ndev)
1907 struct fec_enet_private *fep = netdev_priv(ndev);
1908 const struct platform_device_id *id_entry =
1909 platform_get_device_id(fep->pdev);
1910 struct phy_device *phy_dev = NULL;
1911 char mdio_bus_id[MII_BUS_ID_SIZE];
1912 char phy_name[MII_BUS_ID_SIZE + 3];
1914 int dev_id = fep->dev_id;
1916 fep->phy_dev = NULL;
1918 if (fep->phy_node) {
1919 phy_dev = of_phy_connect(ndev, fep->phy_node,
1920 &fec_enet_adjust_link, 0,
1921 fep->phy_interface);
1923 /* check for attached phy */
1924 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
1925 if ((fep->mii_bus->phy_mask & (1 << phy_id)))
1927 if (fep->mii_bus->phy_map[phy_id] == NULL)
1929 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0)
1933 strlcpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
1937 if (phy_id >= PHY_MAX_ADDR) {
1938 netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
1939 strlcpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
1943 snprintf(phy_name, sizeof(phy_name),
1944 PHY_ID_FMT, mdio_bus_id, phy_id);
1945 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
1946 fep->phy_interface);
1949 if (IS_ERR(phy_dev)) {
1950 netdev_err(ndev, "could not attach to PHY\n");
1951 return PTR_ERR(phy_dev);
1954 /* mask with MAC supported features */
1955 if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT) {
1956 phy_dev->supported &= PHY_GBIT_FEATURES;
1957 phy_dev->supported &= ~SUPPORTED_1000baseT_Half;
1958 #if !defined(CONFIG_M5272)
1959 phy_dev->supported |= SUPPORTED_Pause;
1963 phy_dev->supported &= PHY_BASIC_FEATURES;
1965 phy_dev->advertising = phy_dev->supported;
1967 fep->phy_dev = phy_dev;
1969 fep->full_duplex = 0;
1971 netdev_info(ndev, "Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1972 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev),
1978 static int fec_enet_mii_init(struct platform_device *pdev)
1980 static struct mii_bus *fec0_mii_bus;
1981 struct net_device *ndev = platform_get_drvdata(pdev);
1982 struct fec_enet_private *fep = netdev_priv(ndev);
1983 const struct platform_device_id *id_entry =
1984 platform_get_device_id(fep->pdev);
1985 struct device_node *node;
1986 int err = -ENXIO, i;
1989 * The dual fec interfaces are not equivalent with enet-mac.
1990 * Here are the differences:
1992 * - fec0 supports MII & RMII modes while fec1 only supports RMII
1993 * - fec0 acts as the 1588 time master while fec1 is slave
1994 * - external phys can only be configured by fec0
1996 * That is to say fec1 can not work independently. It only works
1997 * when fec0 is working. The reason behind this design is that the
1998 * second interface is added primarily for Switch mode.
2000 * Because of the last point above, both phys are attached on fec0
2001 * mdio interface in board design, and need to be configured by
2004 if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) {
2005 /* fec1 uses fec0 mii_bus */
2006 if (mii_cnt && fec0_mii_bus) {
2007 fep->mii_bus = fec0_mii_bus;
2014 fep->mii_timeout = 0;
2017 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
2019 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
2020 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
2021 * Reference Manual has an error on this, and gets fixed on i.MX6Q
2024 fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ipg), 5000000);
2025 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
2027 fep->phy_speed <<= 1;
2028 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
2030 fep->mii_bus = mdiobus_alloc();
2031 if (fep->mii_bus == NULL) {
2036 fep->mii_bus->name = "fec_enet_mii_bus";
2037 fep->mii_bus->read = fec_enet_mdio_read;
2038 fep->mii_bus->write = fec_enet_mdio_write;
2039 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2040 pdev->name, fep->dev_id + 1);
2041 fep->mii_bus->priv = fep;
2042 fep->mii_bus->parent = &pdev->dev;
2044 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
2045 if (!fep->mii_bus->irq) {
2047 goto err_out_free_mdiobus;
2050 for (i = 0; i < PHY_MAX_ADDR; i++)
2051 fep->mii_bus->irq[i] = PHY_POLL;
2053 node = of_get_child_by_name(pdev->dev.of_node, "mdio");
2055 err = of_mdiobus_register(fep->mii_bus, node);
2058 err = mdiobus_register(fep->mii_bus);
2062 goto err_out_free_mdio_irq;
2066 /* save fec0 mii_bus */
2067 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
2068 fec0_mii_bus = fep->mii_bus;
2072 err_out_free_mdio_irq:
2073 kfree(fep->mii_bus->irq);
2074 err_out_free_mdiobus:
2075 mdiobus_free(fep->mii_bus);
2080 static void fec_enet_mii_remove(struct fec_enet_private *fep)
2082 if (--mii_cnt == 0) {
2083 mdiobus_unregister(fep->mii_bus);
2084 kfree(fep->mii_bus->irq);
2085 mdiobus_free(fep->mii_bus);
2089 static int fec_enet_get_settings(struct net_device *ndev,
2090 struct ethtool_cmd *cmd)
2092 struct fec_enet_private *fep = netdev_priv(ndev);
2093 struct phy_device *phydev = fep->phy_dev;
2098 return phy_ethtool_gset(phydev, cmd);
2101 static int fec_enet_set_settings(struct net_device *ndev,
2102 struct ethtool_cmd *cmd)
2104 struct fec_enet_private *fep = netdev_priv(ndev);
2105 struct phy_device *phydev = fep->phy_dev;
2110 return phy_ethtool_sset(phydev, cmd);
2113 static void fec_enet_get_drvinfo(struct net_device *ndev,
2114 struct ethtool_drvinfo *info)
2116 struct fec_enet_private *fep = netdev_priv(ndev);
2118 strlcpy(info->driver, fep->pdev->dev.driver->name,
2119 sizeof(info->driver));
2120 strlcpy(info->version, "Revision: 1.0", sizeof(info->version));
2121 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
2124 static int fec_enet_get_ts_info(struct net_device *ndev,
2125 struct ethtool_ts_info *info)
2127 struct fec_enet_private *fep = netdev_priv(ndev);
2129 if (fep->bufdesc_ex) {
2131 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
2132 SOF_TIMESTAMPING_RX_SOFTWARE |
2133 SOF_TIMESTAMPING_SOFTWARE |
2134 SOF_TIMESTAMPING_TX_HARDWARE |
2135 SOF_TIMESTAMPING_RX_HARDWARE |
2136 SOF_TIMESTAMPING_RAW_HARDWARE;
2138 info->phc_index = ptp_clock_index(fep->ptp_clock);
2140 info->phc_index = -1;
2142 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
2143 (1 << HWTSTAMP_TX_ON);
2145 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
2146 (1 << HWTSTAMP_FILTER_ALL);
2149 return ethtool_op_get_ts_info(ndev, info);
2153 #if !defined(CONFIG_M5272)
2155 static void fec_enet_get_pauseparam(struct net_device *ndev,
2156 struct ethtool_pauseparam *pause)
2158 struct fec_enet_private *fep = netdev_priv(ndev);
2160 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
2161 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
2162 pause->rx_pause = pause->tx_pause;
2165 static int fec_enet_set_pauseparam(struct net_device *ndev,
2166 struct ethtool_pauseparam *pause)
2168 struct fec_enet_private *fep = netdev_priv(ndev);
2173 if (pause->tx_pause != pause->rx_pause) {
2175 "hardware only support enable/disable both tx and rx");
2179 fep->pause_flag = 0;
2181 /* tx pause must be same as rx pause */
2182 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
2183 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
2185 if (pause->rx_pause || pause->autoneg) {
2186 fep->phy_dev->supported |= ADVERTISED_Pause;
2187 fep->phy_dev->advertising |= ADVERTISED_Pause;
2189 fep->phy_dev->supported &= ~ADVERTISED_Pause;
2190 fep->phy_dev->advertising &= ~ADVERTISED_Pause;
2193 if (pause->autoneg) {
2194 if (netif_running(ndev))
2196 phy_start_aneg(fep->phy_dev);
2198 if (netif_running(ndev)) {
2199 napi_disable(&fep->napi);
2200 netif_tx_lock_bh(ndev);
2202 netif_wake_queue(ndev);
2203 netif_tx_unlock_bh(ndev);
2204 napi_enable(&fep->napi);
2210 static const struct fec_stat {
2211 char name[ETH_GSTRING_LEN];
2215 { "tx_dropped", RMON_T_DROP },
2216 { "tx_packets", RMON_T_PACKETS },
2217 { "tx_broadcast", RMON_T_BC_PKT },
2218 { "tx_multicast", RMON_T_MC_PKT },
2219 { "tx_crc_errors", RMON_T_CRC_ALIGN },
2220 { "tx_undersize", RMON_T_UNDERSIZE },
2221 { "tx_oversize", RMON_T_OVERSIZE },
2222 { "tx_fragment", RMON_T_FRAG },
2223 { "tx_jabber", RMON_T_JAB },
2224 { "tx_collision", RMON_T_COL },
2225 { "tx_64byte", RMON_T_P64 },
2226 { "tx_65to127byte", RMON_T_P65TO127 },
2227 { "tx_128to255byte", RMON_T_P128TO255 },
2228 { "tx_256to511byte", RMON_T_P256TO511 },
2229 { "tx_512to1023byte", RMON_T_P512TO1023 },
2230 { "tx_1024to2047byte", RMON_T_P1024TO2047 },
2231 { "tx_GTE2048byte", RMON_T_P_GTE2048 },
2232 { "tx_octets", RMON_T_OCTETS },
2235 { "IEEE_tx_drop", IEEE_T_DROP },
2236 { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
2237 { "IEEE_tx_1col", IEEE_T_1COL },
2238 { "IEEE_tx_mcol", IEEE_T_MCOL },
2239 { "IEEE_tx_def", IEEE_T_DEF },
2240 { "IEEE_tx_lcol", IEEE_T_LCOL },
2241 { "IEEE_tx_excol", IEEE_T_EXCOL },
2242 { "IEEE_tx_macerr", IEEE_T_MACERR },
2243 { "IEEE_tx_cserr", IEEE_T_CSERR },
2244 { "IEEE_tx_sqe", IEEE_T_SQE },
2245 { "IEEE_tx_fdxfc", IEEE_T_FDXFC },
2246 { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
2249 { "rx_packets", RMON_R_PACKETS },
2250 { "rx_broadcast", RMON_R_BC_PKT },
2251 { "rx_multicast", RMON_R_MC_PKT },
2252 { "rx_crc_errors", RMON_R_CRC_ALIGN },
2253 { "rx_undersize", RMON_R_UNDERSIZE },
2254 { "rx_oversize", RMON_R_OVERSIZE },
2255 { "rx_fragment", RMON_R_FRAG },
2256 { "rx_jabber", RMON_R_JAB },
2257 { "rx_64byte", RMON_R_P64 },
2258 { "rx_65to127byte", RMON_R_P65TO127 },
2259 { "rx_128to255byte", RMON_R_P128TO255 },
2260 { "rx_256to511byte", RMON_R_P256TO511 },
2261 { "rx_512to1023byte", RMON_R_P512TO1023 },
2262 { "rx_1024to2047byte", RMON_R_P1024TO2047 },
2263 { "rx_GTE2048byte", RMON_R_P_GTE2048 },
2264 { "rx_octets", RMON_R_OCTETS },
2267 { "IEEE_rx_drop", IEEE_R_DROP },
2268 { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
2269 { "IEEE_rx_crc", IEEE_R_CRC },
2270 { "IEEE_rx_align", IEEE_R_ALIGN },
2271 { "IEEE_rx_macerr", IEEE_R_MACERR },
2272 { "IEEE_rx_fdxfc", IEEE_R_FDXFC },
2273 { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
2276 static void fec_enet_get_ethtool_stats(struct net_device *dev,
2277 struct ethtool_stats *stats, u64 *data)
2279 struct fec_enet_private *fep = netdev_priv(dev);
2282 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2283 data[i] = readl(fep->hwp + fec_stats[i].offset);
2286 static void fec_enet_get_strings(struct net_device *netdev,
2287 u32 stringset, u8 *data)
2290 switch (stringset) {
2292 for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
2293 memcpy(data + i * ETH_GSTRING_LEN,
2294 fec_stats[i].name, ETH_GSTRING_LEN);
2299 static int fec_enet_get_sset_count(struct net_device *dev, int sset)
2303 return ARRAY_SIZE(fec_stats);
2308 #endif /* !defined(CONFIG_M5272) */
2310 static int fec_enet_nway_reset(struct net_device *dev)
2312 struct fec_enet_private *fep = netdev_priv(dev);
2313 struct phy_device *phydev = fep->phy_dev;
2318 return genphy_restart_aneg(phydev);
2321 /* ITR clock source is enet system clock (clk_ahb).
2322 * TCTT unit is cycle_ns * 64 cycle
2323 * So, the ICTT value = X us / (cycle_ns * 64)
2325 static int fec_enet_us_to_itr_clock(struct net_device *ndev, int us)
2327 struct fec_enet_private *fep = netdev_priv(ndev);
2329 return us * (fep->itr_clk_rate / 64000) / 1000;
2332 /* Set threshold for interrupt coalescing */
2333 static void fec_enet_itr_coal_set(struct net_device *ndev)
2335 struct fec_enet_private *fep = netdev_priv(ndev);
2336 const struct platform_device_id *id_entry =
2337 platform_get_device_id(fep->pdev);
2340 if (!(id_entry->driver_data & FEC_QUIRK_HAS_AVB))
2343 /* Must be greater than zero to avoid unpredictable behavior */
2344 if (!fep->rx_time_itr || !fep->rx_pkts_itr ||
2345 !fep->tx_time_itr || !fep->tx_pkts_itr)
2348 /* Select enet system clock as Interrupt Coalescing
2349 * timer Clock Source
2351 rx_itr = FEC_ITR_CLK_SEL;
2352 tx_itr = FEC_ITR_CLK_SEL;
2354 /* set ICFT and ICTT */
2355 rx_itr |= FEC_ITR_ICFT(fep->rx_pkts_itr);
2356 rx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr));
2357 tx_itr |= FEC_ITR_ICFT(fep->tx_pkts_itr);
2358 tx_itr |= FEC_ITR_ICTT(fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr));
2360 rx_itr |= FEC_ITR_EN;
2361 tx_itr |= FEC_ITR_EN;
2363 writel(tx_itr, fep->hwp + FEC_TXIC0);
2364 writel(rx_itr, fep->hwp + FEC_RXIC0);
2365 writel(tx_itr, fep->hwp + FEC_TXIC1);
2366 writel(rx_itr, fep->hwp + FEC_RXIC1);
2367 writel(tx_itr, fep->hwp + FEC_TXIC2);
2368 writel(rx_itr, fep->hwp + FEC_RXIC2);
2372 fec_enet_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2374 struct fec_enet_private *fep = netdev_priv(ndev);
2375 const struct platform_device_id *id_entry =
2376 platform_get_device_id(fep->pdev);
2378 if (!(id_entry->driver_data & FEC_QUIRK_HAS_AVB))
2381 ec->rx_coalesce_usecs = fep->rx_time_itr;
2382 ec->rx_max_coalesced_frames = fep->rx_pkts_itr;
2384 ec->tx_coalesce_usecs = fep->tx_time_itr;
2385 ec->tx_max_coalesced_frames = fep->tx_pkts_itr;
2391 fec_enet_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *ec)
2393 struct fec_enet_private *fep = netdev_priv(ndev);
2394 const struct platform_device_id *id_entry =
2395 platform_get_device_id(fep->pdev);
2399 if (!(id_entry->driver_data & FEC_QUIRK_HAS_AVB))
2402 if (ec->rx_max_coalesced_frames > 255) {
2403 pr_err("Rx coalesced frames exceed hardware limiation");
2407 if (ec->tx_max_coalesced_frames > 255) {
2408 pr_err("Tx coalesced frame exceed hardware limiation");
2412 cycle = fec_enet_us_to_itr_clock(ndev, fep->rx_time_itr);
2413 if (cycle > 0xFFFF) {
2414 pr_err("Rx coalesed usec exceeed hardware limiation");
2418 cycle = fec_enet_us_to_itr_clock(ndev, fep->tx_time_itr);
2419 if (cycle > 0xFFFF) {
2420 pr_err("Rx coalesed usec exceeed hardware limiation");
2424 fep->rx_time_itr = ec->rx_coalesce_usecs;
2425 fep->rx_pkts_itr = ec->rx_max_coalesced_frames;
2427 fep->tx_time_itr = ec->tx_coalesce_usecs;
2428 fep->tx_pkts_itr = ec->tx_max_coalesced_frames;
2430 fec_enet_itr_coal_set(ndev);
2435 static void fec_enet_itr_coal_init(struct net_device *ndev)
2437 struct ethtool_coalesce ec;
2439 ec.rx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2440 ec.rx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2442 ec.tx_coalesce_usecs = FEC_ITR_ICTT_DEFAULT;
2443 ec.tx_max_coalesced_frames = FEC_ITR_ICFT_DEFAULT;
2445 fec_enet_set_coalesce(ndev, &ec);
2448 static int fec_enet_get_tunable(struct net_device *netdev,
2449 const struct ethtool_tunable *tuna,
2452 struct fec_enet_private *fep = netdev_priv(netdev);
2456 case ETHTOOL_RX_COPYBREAK:
2457 *(u32 *)data = fep->rx_copybreak;
2467 static int fec_enet_set_tunable(struct net_device *netdev,
2468 const struct ethtool_tunable *tuna,
2471 struct fec_enet_private *fep = netdev_priv(netdev);
2475 case ETHTOOL_RX_COPYBREAK:
2476 fep->rx_copybreak = *(u32 *)data;
2486 static const struct ethtool_ops fec_enet_ethtool_ops = {
2487 .get_settings = fec_enet_get_settings,
2488 .set_settings = fec_enet_set_settings,
2489 .get_drvinfo = fec_enet_get_drvinfo,
2490 .nway_reset = fec_enet_nway_reset,
2491 .get_link = ethtool_op_get_link,
2492 .get_coalesce = fec_enet_get_coalesce,
2493 .set_coalesce = fec_enet_set_coalesce,
2494 #ifndef CONFIG_M5272
2495 .get_pauseparam = fec_enet_get_pauseparam,
2496 .set_pauseparam = fec_enet_set_pauseparam,
2497 .get_strings = fec_enet_get_strings,
2498 .get_ethtool_stats = fec_enet_get_ethtool_stats,
2499 .get_sset_count = fec_enet_get_sset_count,
2501 .get_ts_info = fec_enet_get_ts_info,
2502 .get_tunable = fec_enet_get_tunable,
2503 .set_tunable = fec_enet_set_tunable,
2506 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2508 struct fec_enet_private *fep = netdev_priv(ndev);
2509 struct phy_device *phydev = fep->phy_dev;
2511 if (!netif_running(ndev))
2517 if (fep->bufdesc_ex) {
2518 if (cmd == SIOCSHWTSTAMP)
2519 return fec_ptp_set(ndev, rq);
2520 if (cmd == SIOCGHWTSTAMP)
2521 return fec_ptp_get(ndev, rq);
2524 return phy_mii_ioctl(phydev, rq, cmd);
2527 static void fec_enet_free_buffers(struct net_device *ndev)
2529 struct fec_enet_private *fep = netdev_priv(ndev);
2531 struct sk_buff *skb;
2532 struct bufdesc *bdp;
2533 struct fec_enet_priv_tx_q *txq;
2534 struct fec_enet_priv_rx_q *rxq;
2537 for (q = 0; q < fep->num_rx_queues; q++) {
2538 rxq = fep->rx_queue[q];
2539 bdp = rxq->rx_bd_base;
2540 for (i = 0; i < rxq->rx_ring_size; i++) {
2541 skb = rxq->rx_skbuff[i];
2542 rxq->rx_skbuff[i] = NULL;
2544 dma_unmap_single(&fep->pdev->dev,
2546 FEC_ENET_RX_FRSIZE - fep->rx_align,
2550 bdp = fec_enet_get_nextdesc(bdp, fep, q);
2554 for (q = 0; q < fep->num_tx_queues; q++) {
2555 txq = fep->tx_queue[q];
2556 bdp = txq->tx_bd_base;
2557 for (i = 0; i < txq->tx_ring_size; i++) {
2558 kfree(txq->tx_bounce[i]);
2559 txq->tx_bounce[i] = NULL;
2560 skb = txq->tx_skbuff[i];
2561 txq->tx_skbuff[i] = NULL;
2567 static void fec_enet_free_queue(struct net_device *ndev)
2569 struct fec_enet_private *fep = netdev_priv(ndev);
2571 struct fec_enet_priv_tx_q *txq;
2573 for (i = 0; i < fep->num_tx_queues; i++)
2574 if (fep->tx_queue[i] && fep->tx_queue[i]->tso_hdrs) {
2575 txq = fep->tx_queue[i];
2576 dma_free_coherent(NULL,
2577 txq->tx_ring_size * TSO_HEADER_SIZE,
2582 for (i = 0; i < fep->num_rx_queues; i++)
2583 if (fep->rx_queue[i])
2584 kfree(fep->rx_queue[i]);
2586 for (i = 0; i < fep->num_tx_queues; i++)
2587 if (fep->tx_queue[i])
2588 kfree(fep->tx_queue[i]);
2591 static int fec_enet_alloc_queue(struct net_device *ndev)
2593 struct fec_enet_private *fep = netdev_priv(ndev);
2596 struct fec_enet_priv_tx_q *txq;
2598 for (i = 0; i < fep->num_tx_queues; i++) {
2599 txq = kzalloc(sizeof(*txq), GFP_KERNEL);
2605 fep->tx_queue[i] = txq;
2606 txq->tx_ring_size = TX_RING_SIZE;
2607 fep->total_tx_ring_size += fep->tx_queue[i]->tx_ring_size;
2609 txq->tx_stop_threshold = FEC_MAX_SKB_DESCS;
2610 txq->tx_wake_threshold =
2611 (txq->tx_ring_size - txq->tx_stop_threshold) / 2;
2613 txq->tso_hdrs = dma_alloc_coherent(NULL,
2614 txq->tx_ring_size * TSO_HEADER_SIZE,
2617 if (!txq->tso_hdrs) {
2623 for (i = 0; i < fep->num_rx_queues; i++) {
2624 fep->rx_queue[i] = kzalloc(sizeof(*fep->rx_queue[i]),
2626 if (!fep->rx_queue[i]) {
2631 fep->rx_queue[i]->rx_ring_size = RX_RING_SIZE;
2632 fep->total_rx_ring_size += fep->rx_queue[i]->rx_ring_size;
2637 fec_enet_free_queue(ndev);
2642 fec_enet_alloc_rxq_buffers(struct net_device *ndev, unsigned int queue)
2644 struct fec_enet_private *fep = netdev_priv(ndev);
2646 struct sk_buff *skb;
2647 struct bufdesc *bdp;
2648 struct fec_enet_priv_rx_q *rxq;
2650 rxq = fep->rx_queue[queue];
2651 bdp = rxq->rx_bd_base;
2652 for (i = 0; i < rxq->rx_ring_size; i++) {
2653 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
2657 if (fec_enet_new_rxbdp(ndev, bdp, skb)) {
2662 rxq->rx_skbuff[i] = skb;
2663 bdp->cbd_sc = BD_ENET_RX_EMPTY;
2665 if (fep->bufdesc_ex) {
2666 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
2667 ebdp->cbd_esc = BD_ENET_RX_INT;
2670 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
2673 /* Set the last buffer to wrap. */
2674 bdp = fec_enet_get_prevdesc(bdp, fep, queue);
2675 bdp->cbd_sc |= BD_SC_WRAP;
2679 fec_enet_free_buffers(ndev);
2684 fec_enet_alloc_txq_buffers(struct net_device *ndev, unsigned int queue)
2686 struct fec_enet_private *fep = netdev_priv(ndev);
2688 struct bufdesc *bdp;
2689 struct fec_enet_priv_tx_q *txq;
2691 txq = fep->tx_queue[queue];
2692 bdp = txq->tx_bd_base;
2693 for (i = 0; i < txq->tx_ring_size; i++) {
2694 txq->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
2695 if (!txq->tx_bounce[i])
2699 bdp->cbd_bufaddr = 0;
2701 if (fep->bufdesc_ex) {
2702 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
2703 ebdp->cbd_esc = BD_ENET_TX_INT;
2706 bdp = fec_enet_get_nextdesc(bdp, fep, queue);
2709 /* Set the last buffer to wrap. */
2710 bdp = fec_enet_get_prevdesc(bdp, fep, queue);
2711 bdp->cbd_sc |= BD_SC_WRAP;
2716 fec_enet_free_buffers(ndev);
2720 static int fec_enet_alloc_buffers(struct net_device *ndev)
2722 struct fec_enet_private *fep = netdev_priv(ndev);
2725 for (i = 0; i < fep->num_rx_queues; i++)
2726 if (fec_enet_alloc_rxq_buffers(ndev, i))
2729 for (i = 0; i < fep->num_tx_queues; i++)
2730 if (fec_enet_alloc_txq_buffers(ndev, i))
2736 fec_enet_open(struct net_device *ndev)
2738 struct fec_enet_private *fep = netdev_priv(ndev);
2741 pinctrl_pm_select_default_state(&fep->pdev->dev);
2742 ret = fec_enet_clk_enable(ndev, true);
2746 /* I should reset the ring buffers here, but I don't yet know
2747 * a simple way to do that.
2750 ret = fec_enet_alloc_buffers(ndev);
2752 goto err_enet_alloc;
2754 /* Probe and connect to PHY when open the interface */
2755 ret = fec_enet_mii_probe(ndev);
2757 goto err_enet_mii_probe;
2760 napi_enable(&fep->napi);
2761 phy_start(fep->phy_dev);
2762 netif_tx_start_all_queues(ndev);
2767 fec_enet_free_buffers(ndev);
2769 fec_enet_clk_enable(ndev, false);
2770 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
2775 fec_enet_close(struct net_device *ndev)
2777 struct fec_enet_private *fep = netdev_priv(ndev);
2779 phy_stop(fep->phy_dev);
2781 if (netif_device_present(ndev)) {
2782 napi_disable(&fep->napi);
2783 netif_tx_disable(ndev);
2787 phy_disconnect(fep->phy_dev);
2788 fep->phy_dev = NULL;
2790 fec_enet_clk_enable(ndev, false);
2791 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
2792 fec_enet_free_buffers(ndev);
2797 /* Set or clear the multicast filter for this adaptor.
2798 * Skeleton taken from sunlance driver.
2799 * The CPM Ethernet implementation allows Multicast as well as individual
2800 * MAC address filtering. Some of the drivers check to make sure it is
2801 * a group multicast address, and discard those that are not. I guess I
2802 * will do the same for now, but just remove the test if you want
2803 * individual filtering as well (do the upper net layers want or support
2804 * this kind of feature?).
2807 #define HASH_BITS 6 /* #bits in hash */
2808 #define CRC32_POLY 0xEDB88320
2810 static void set_multicast_list(struct net_device *ndev)
2812 struct fec_enet_private *fep = netdev_priv(ndev);
2813 struct netdev_hw_addr *ha;
2814 unsigned int i, bit, data, crc, tmp;
2817 if (ndev->flags & IFF_PROMISC) {
2818 tmp = readl(fep->hwp + FEC_R_CNTRL);
2820 writel(tmp, fep->hwp + FEC_R_CNTRL);
2824 tmp = readl(fep->hwp + FEC_R_CNTRL);
2826 writel(tmp, fep->hwp + FEC_R_CNTRL);
2828 if (ndev->flags & IFF_ALLMULTI) {
2829 /* Catch all multicast addresses, so set the
2832 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2833 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2838 /* Clear filter and add the addresses in hash register
2840 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2841 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2843 netdev_for_each_mc_addr(ha, ndev) {
2844 /* calculate crc32 value of mac address */
2847 for (i = 0; i < ndev->addr_len; i++) {
2849 for (bit = 0; bit < 8; bit++, data >>= 1) {
2851 (((crc ^ data) & 1) ? CRC32_POLY : 0);
2855 /* only upper 6 bits (HASH_BITS) are used
2856 * which point to specific bit in he hash registers
2858 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
2861 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2862 tmp |= 1 << (hash - 32);
2863 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
2865 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2867 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
2872 /* Set a MAC change in hardware. */
2874 fec_set_mac_address(struct net_device *ndev, void *p)
2876 struct fec_enet_private *fep = netdev_priv(ndev);
2877 struct sockaddr *addr = p;
2880 if (!is_valid_ether_addr(addr->sa_data))
2881 return -EADDRNOTAVAIL;
2882 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
2885 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
2886 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
2887 fep->hwp + FEC_ADDR_LOW);
2888 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
2889 fep->hwp + FEC_ADDR_HIGH);
2893 #ifdef CONFIG_NET_POLL_CONTROLLER
2895 * fec_poll_controller - FEC Poll controller function
2896 * @dev: The FEC network adapter
2898 * Polled functionality used by netconsole and others in non interrupt mode
2901 static void fec_poll_controller(struct net_device *dev)
2904 struct fec_enet_private *fep = netdev_priv(dev);
2906 for (i = 0; i < FEC_IRQ_NUM; i++) {
2907 if (fep->irq[i] > 0) {
2908 disable_irq(fep->irq[i]);
2909 fec_enet_interrupt(fep->irq[i], dev);
2910 enable_irq(fep->irq[i]);
2916 #define FEATURES_NEED_QUIESCE NETIF_F_RXCSUM
2917 static inline void fec_enet_set_netdev_features(struct net_device *netdev,
2918 netdev_features_t features)
2920 struct fec_enet_private *fep = netdev_priv(netdev);
2921 netdev_features_t changed = features ^ netdev->features;
2923 netdev->features = features;
2925 /* Receive checksum has been changed */
2926 if (changed & NETIF_F_RXCSUM) {
2927 if (features & NETIF_F_RXCSUM)
2928 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
2930 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED;
2934 static int fec_set_features(struct net_device *netdev,
2935 netdev_features_t features)
2937 struct fec_enet_private *fep = netdev_priv(netdev);
2938 netdev_features_t changed = features ^ netdev->features;
2940 if (netif_running(netdev) && changed & FEATURES_NEED_QUIESCE) {
2941 napi_disable(&fep->napi);
2942 netif_tx_lock_bh(netdev);
2944 fec_enet_set_netdev_features(netdev, features);
2945 fec_restart(netdev);
2946 netif_tx_wake_all_queues(netdev);
2947 netif_tx_unlock_bh(netdev);
2948 napi_enable(&fep->napi);
2950 fec_enet_set_netdev_features(netdev, features);
2956 static const struct net_device_ops fec_netdev_ops = {
2957 .ndo_open = fec_enet_open,
2958 .ndo_stop = fec_enet_close,
2959 .ndo_start_xmit = fec_enet_start_xmit,
2960 .ndo_set_rx_mode = set_multicast_list,
2961 .ndo_change_mtu = eth_change_mtu,
2962 .ndo_validate_addr = eth_validate_addr,
2963 .ndo_tx_timeout = fec_timeout,
2964 .ndo_set_mac_address = fec_set_mac_address,
2965 .ndo_do_ioctl = fec_enet_ioctl,
2966 #ifdef CONFIG_NET_POLL_CONTROLLER
2967 .ndo_poll_controller = fec_poll_controller,
2969 .ndo_set_features = fec_set_features,
2973 * XXX: We need to clean up on failure exits here.
2976 static int fec_enet_init(struct net_device *ndev)
2978 struct fec_enet_private *fep = netdev_priv(ndev);
2979 const struct platform_device_id *id_entry =
2980 platform_get_device_id(fep->pdev);
2981 struct fec_enet_priv_tx_q *txq;
2982 struct fec_enet_priv_rx_q *rxq;
2983 struct bufdesc *cbd_base;
2988 #if defined(CONFIG_ARM)
2989 fep->rx_align = 0xf;
2990 fep->tx_align = 0xf;
2992 fep->rx_align = 0x3;
2993 fep->tx_align = 0x3;
2996 fec_enet_alloc_queue(ndev);
2998 if (fep->bufdesc_ex)
2999 fep->bufdesc_size = sizeof(struct bufdesc_ex);
3001 fep->bufdesc_size = sizeof(struct bufdesc);
3002 bd_size = (fep->total_tx_ring_size + fep->total_rx_ring_size) *
3005 /* Allocate memory for buffer descriptors. */
3006 cbd_base = dma_alloc_coherent(NULL, bd_size, &bd_dma,
3012 memset(cbd_base, 0, bd_size);
3014 /* Get the Ethernet address */
3016 /* make sure MAC we just acquired is programmed into the hw */
3017 fec_set_mac_address(ndev, NULL);
3019 /* Set receive and transmit descriptor base. */
3020 for (i = 0; i < fep->num_rx_queues; i++) {
3021 rxq = fep->rx_queue[i];
3023 rxq->rx_bd_base = (struct bufdesc *)cbd_base;
3024 rxq->bd_dma = bd_dma;
3025 if (fep->bufdesc_ex) {
3026 bd_dma += sizeof(struct bufdesc_ex) * rxq->rx_ring_size;
3027 cbd_base = (struct bufdesc *)
3028 (((struct bufdesc_ex *)cbd_base) + rxq->rx_ring_size);
3030 bd_dma += sizeof(struct bufdesc) * rxq->rx_ring_size;
3031 cbd_base += rxq->rx_ring_size;
3035 for (i = 0; i < fep->num_tx_queues; i++) {
3036 txq = fep->tx_queue[i];
3038 txq->tx_bd_base = (struct bufdesc *)cbd_base;
3039 txq->bd_dma = bd_dma;
3040 if (fep->bufdesc_ex) {
3041 bd_dma += sizeof(struct bufdesc_ex) * txq->tx_ring_size;
3042 cbd_base = (struct bufdesc *)
3043 (((struct bufdesc_ex *)cbd_base) + txq->tx_ring_size);
3045 bd_dma += sizeof(struct bufdesc) * txq->tx_ring_size;
3046 cbd_base += txq->tx_ring_size;
3051 /* The FEC Ethernet specific entries in the device structure */
3052 ndev->watchdog_timeo = TX_TIMEOUT;
3053 ndev->netdev_ops = &fec_netdev_ops;
3054 ndev->ethtool_ops = &fec_enet_ethtool_ops;
3056 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
3057 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, NAPI_POLL_WEIGHT);
3059 if (id_entry->driver_data & FEC_QUIRK_HAS_VLAN)
3060 /* enable hw VLAN support */
3061 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
3063 if (id_entry->driver_data & FEC_QUIRK_HAS_CSUM) {
3064 ndev->gso_max_segs = FEC_MAX_TSO_SEGS;
3066 /* enable hw accelerator */
3067 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
3068 | NETIF_F_RXCSUM | NETIF_F_SG | NETIF_F_TSO);
3069 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
3072 if (id_entry->driver_data & FEC_QUIRK_HAS_AVB) {
3074 fep->rx_align = 0x3f;
3077 ndev->hw_features = ndev->features;
3085 static void fec_reset_phy(struct platform_device *pdev)
3089 struct device_node *np = pdev->dev.of_node;
3094 of_property_read_u32(np, "phy-reset-duration", &msec);
3095 /* A sane reset duration should not be longer than 1s */
3099 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
3100 if (!gpio_is_valid(phy_reset))
3103 err = devm_gpio_request_one(&pdev->dev, phy_reset,
3104 GPIOF_OUT_INIT_LOW, "phy-reset");
3106 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
3110 gpio_set_value(phy_reset, 1);
3112 #else /* CONFIG_OF */
3113 static void fec_reset_phy(struct platform_device *pdev)
3116 * In case of platform probe, the reset has been done
3120 #endif /* CONFIG_OF */
3123 fec_enet_get_queue_num(struct platform_device *pdev, int *num_tx, int *num_rx)
3125 struct device_node *np = pdev->dev.of_node;
3128 *num_tx = *num_rx = 1;
3130 if (!np || !of_device_is_available(np))
3133 /* parse the num of tx and rx queues */
3134 err = of_property_read_u32(np, "fsl,num-tx-queues", num_tx);
3138 err = of_property_read_u32(np, "fsl,num-rx-queues", num_rx);
3142 if (*num_tx < 1 || *num_tx > FEC_ENET_MAX_TX_QS) {
3143 dev_warn(&pdev->dev, "Invalid num_tx(=%d), fall back to 1\n",
3149 if (*num_rx < 1 || *num_rx > FEC_ENET_MAX_RX_QS) {
3150 dev_warn(&pdev->dev, "Invalid num_rx(=%d), fall back to 1\n",
3159 fec_probe(struct platform_device *pdev)
3161 struct fec_enet_private *fep;
3162 struct fec_platform_data *pdata;
3163 struct net_device *ndev;
3164 int i, irq, ret = 0;
3166 const struct of_device_id *of_id;
3168 struct device_node *np = pdev->dev.of_node, *phy_node;
3172 of_id = of_match_device(fec_dt_ids, &pdev->dev);
3174 pdev->id_entry = of_id->data;
3176 fec_enet_get_queue_num(pdev, &num_tx_qs, &num_rx_qs);
3178 /* Init network device */
3179 ndev = alloc_etherdev_mqs(sizeof(struct fec_enet_private),
3180 num_tx_qs, num_rx_qs);
3184 SET_NETDEV_DEV(ndev, &pdev->dev);
3186 /* setup board info structure */
3187 fep = netdev_priv(ndev);
3189 fep->num_rx_queues = num_rx_qs;
3190 fep->num_tx_queues = num_tx_qs;
3192 #if !defined(CONFIG_M5272)
3193 /* default enable pause frame auto negotiation */
3194 if (pdev->id_entry &&
3195 (pdev->id_entry->driver_data & FEC_QUIRK_HAS_GBIT))
3196 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
3199 /* Select default pin state */
3200 pinctrl_pm_select_default_state(&pdev->dev);
3202 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3203 fep->hwp = devm_ioremap_resource(&pdev->dev, r);
3204 if (IS_ERR(fep->hwp)) {
3205 ret = PTR_ERR(fep->hwp);
3206 goto failed_ioremap;
3210 fep->dev_id = dev_id++;
3212 fep->bufdesc_ex = 0;
3214 platform_set_drvdata(pdev, ndev);
3216 phy_node = of_parse_phandle(np, "phy-handle", 0);
3217 if (!phy_node && of_phy_is_fixed_link(np)) {
3218 ret = of_phy_register_fixed_link(np);
3221 "broken fixed-link specification\n");
3224 phy_node = of_node_get(np);
3226 fep->phy_node = phy_node;
3228 ret = of_get_phy_mode(pdev->dev.of_node);
3230 pdata = dev_get_platdata(&pdev->dev);
3232 fep->phy_interface = pdata->phy;
3234 fep->phy_interface = PHY_INTERFACE_MODE_MII;
3236 fep->phy_interface = ret;
3239 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
3240 if (IS_ERR(fep->clk_ipg)) {
3241 ret = PTR_ERR(fep->clk_ipg);
3245 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
3246 if (IS_ERR(fep->clk_ahb)) {
3247 ret = PTR_ERR(fep->clk_ahb);
3251 fep->itr_clk_rate = clk_get_rate(fep->clk_ahb);
3253 /* enet_out is optional, depends on board */
3254 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out");
3255 if (IS_ERR(fep->clk_enet_out))
3256 fep->clk_enet_out = NULL;
3258 fep->ptp_clk_on = false;
3259 mutex_init(&fep->ptp_clk_mutex);
3261 /* clk_ref is optional, depends on board */
3262 fep->clk_ref = devm_clk_get(&pdev->dev, "enet_clk_ref");
3263 if (IS_ERR(fep->clk_ref))
3264 fep->clk_ref = NULL;
3266 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
3268 pdev->id_entry->driver_data & FEC_QUIRK_HAS_BUFDESC_EX;
3269 if (IS_ERR(fep->clk_ptp)) {
3270 fep->clk_ptp = NULL;
3271 fep->bufdesc_ex = 0;
3274 ret = fec_enet_clk_enable(ndev, true);
3278 fep->reg_phy = devm_regulator_get(&pdev->dev, "phy");
3279 if (!IS_ERR(fep->reg_phy)) {
3280 ret = regulator_enable(fep->reg_phy);
3283 "Failed to enable phy regulator: %d\n", ret);
3284 goto failed_regulator;
3287 fep->reg_phy = NULL;
3290 fec_reset_phy(pdev);
3292 if (fep->bufdesc_ex)
3295 ret = fec_enet_init(ndev);
3299 for (i = 0; i < FEC_IRQ_NUM; i++) {
3300 irq = platform_get_irq(pdev, i);
3307 ret = devm_request_irq(&pdev->dev, irq, fec_enet_interrupt,
3308 0, pdev->name, ndev);
3313 init_completion(&fep->mdio_done);
3314 ret = fec_enet_mii_init(pdev);
3316 goto failed_mii_init;
3318 /* Carrier starts down, phylib will bring it up */
3319 netif_carrier_off(ndev);
3320 fec_enet_clk_enable(ndev, false);
3321 pinctrl_pm_select_sleep_state(&pdev->dev);
3323 ret = register_netdev(ndev);
3325 goto failed_register;
3327 if (fep->bufdesc_ex && fep->ptp_clock)
3328 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
3330 fep->rx_copybreak = COPYBREAK_DEFAULT;
3331 INIT_WORK(&fep->tx_timeout_work, fec_enet_timeout_work);
3335 fec_enet_mii_remove(fep);
3340 regulator_disable(fep->reg_phy);
3342 fec_enet_clk_enable(ndev, false);
3345 of_node_put(phy_node);
3353 fec_drv_remove(struct platform_device *pdev)
3355 struct net_device *ndev = platform_get_drvdata(pdev);
3356 struct fec_enet_private *fep = netdev_priv(ndev);
3358 cancel_delayed_work_sync(&fep->time_keep);
3359 cancel_work_sync(&fep->tx_timeout_work);
3360 unregister_netdev(ndev);
3361 fec_enet_mii_remove(fep);
3363 regulator_disable(fep->reg_phy);
3365 ptp_clock_unregister(fep->ptp_clock);
3366 fec_enet_clk_enable(ndev, false);
3367 of_node_put(fep->phy_node);
3373 static int __maybe_unused fec_suspend(struct device *dev)
3375 struct net_device *ndev = dev_get_drvdata(dev);
3376 struct fec_enet_private *fep = netdev_priv(ndev);
3379 if (netif_running(ndev)) {
3380 phy_stop(fep->phy_dev);
3381 napi_disable(&fep->napi);
3382 netif_tx_lock_bh(ndev);
3383 netif_device_detach(ndev);
3384 netif_tx_unlock_bh(ndev);
3389 fec_enet_clk_enable(ndev, false);
3390 pinctrl_pm_select_sleep_state(&fep->pdev->dev);
3393 regulator_disable(fep->reg_phy);
3398 static int __maybe_unused fec_resume(struct device *dev)
3400 struct net_device *ndev = dev_get_drvdata(dev);
3401 struct fec_enet_private *fep = netdev_priv(ndev);
3405 ret = regulator_enable(fep->reg_phy);
3410 pinctrl_pm_select_default_state(&fep->pdev->dev);
3411 ret = fec_enet_clk_enable(ndev, true);
3416 if (netif_running(ndev)) {
3418 netif_tx_lock_bh(ndev);
3419 netif_device_attach(ndev);
3420 netif_tx_unlock_bh(ndev);
3421 napi_enable(&fep->napi);
3422 phy_start(fep->phy_dev);
3430 regulator_disable(fep->reg_phy);
3434 static SIMPLE_DEV_PM_OPS(fec_pm_ops, fec_suspend, fec_resume);
3436 static struct platform_driver fec_driver = {
3438 .name = DRIVER_NAME,
3439 .owner = THIS_MODULE,
3441 .of_match_table = fec_dt_ids,
3443 .id_table = fec_devtype,
3445 .remove = fec_drv_remove,
3448 module_platform_driver(fec_driver);
3450 MODULE_ALIAS("platform:"DRIVER_NAME);
3451 MODULE_LICENSE("GPL");