2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
21 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/string.h>
27 #include <linux/ptrace.h>
28 #include <linux/errno.h>
29 #include <linux/ioport.h>
30 #include <linux/slab.h>
31 #include <linux/interrupt.h>
32 #include <linux/init.h>
33 #include <linux/delay.h>
34 #include <linux/netdevice.h>
35 #include <linux/etherdevice.h>
36 #include <linux/skbuff.h>
40 #include <linux/tcp.h>
41 #include <linux/udp.h>
42 #include <linux/icmp.h>
43 #include <linux/spinlock.h>
44 #include <linux/workqueue.h>
45 #include <linux/bitops.h>
47 #include <linux/irq.h>
48 #include <linux/clk.h>
49 #include <linux/platform_device.h>
50 #include <linux/phy.h>
51 #include <linux/fec.h>
53 #include <linux/of_device.h>
54 #include <linux/of_gpio.h>
55 #include <linux/of_net.h>
56 #include <linux/pinctrl/consumer.h>
57 #include <linux/regulator/consumer.h>
59 #include <asm/cacheflush.h>
63 #if defined(CONFIG_ARM)
64 #define FEC_ALIGNMENT 0xf
66 #define FEC_ALIGNMENT 0x3
69 #define DRIVER_NAME "fec"
70 #define FEC_NAPI_WEIGHT 64
72 /* Pause frame feild and FIFO threshold */
73 #define FEC_ENET_FCE (1 << 5)
74 #define FEC_ENET_RSEM_V 0x84
75 #define FEC_ENET_RSFL_V 16
76 #define FEC_ENET_RAEM_V 0x8
77 #define FEC_ENET_RAFL_V 0x8
78 #define FEC_ENET_OPD_V 0xFFF0
80 /* Controller is ENET-MAC */
81 #define FEC_QUIRK_ENET_MAC (1 << 0)
82 /* Controller needs driver to swap frame */
83 #define FEC_QUIRK_SWAP_FRAME (1 << 1)
84 /* Controller uses gasket */
85 #define FEC_QUIRK_USE_GASKET (1 << 2)
86 /* Controller has GBIT support */
87 #define FEC_QUIRK_HAS_GBIT (1 << 3)
88 /* Controller has extend desc buffer */
89 #define FEC_QUIRK_HAS_BUFDESC_EX (1 << 4)
90 /* Controller has hardware checksum support */
91 #define FEC_QUIRK_HAS_CSUM (1 << 5)
93 static struct platform_device_id fec_devtype[] = {
95 /* keep it for coldfire */
100 .driver_data = FEC_QUIRK_USE_GASKET,
106 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME,
109 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT |
110 FEC_QUIRK_HAS_BUFDESC_EX | FEC_QUIRK_HAS_CSUM,
112 .name = "mvf600-fec",
113 .driver_data = FEC_QUIRK_ENET_MAC,
118 MODULE_DEVICE_TABLE(platform, fec_devtype);
121 IMX25_FEC = 1, /* runs on i.mx25/50/53 */
122 IMX27_FEC, /* runs on i.mx27/35/51 */
128 static const struct of_device_id fec_dt_ids[] = {
129 { .compatible = "fsl,imx25-fec", .data = &fec_devtype[IMX25_FEC], },
130 { .compatible = "fsl,imx27-fec", .data = &fec_devtype[IMX27_FEC], },
131 { .compatible = "fsl,imx28-fec", .data = &fec_devtype[IMX28_FEC], },
132 { .compatible = "fsl,imx6q-fec", .data = &fec_devtype[IMX6Q_FEC], },
133 { .compatible = "fsl,mvf600-fec", .data = &fec_devtype[MVF600_FEC], },
136 MODULE_DEVICE_TABLE(of, fec_dt_ids);
138 static unsigned char macaddr[ETH_ALEN];
139 module_param_array(macaddr, byte, NULL, 0);
140 MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
142 #if defined(CONFIG_M5272)
144 * Some hardware gets it MAC address out of local flash memory.
145 * if this is non-zero then assume it is the address to get MAC from.
147 #if defined(CONFIG_NETtel)
148 #define FEC_FLASHMAC 0xf0006006
149 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
150 #define FEC_FLASHMAC 0xf0006000
151 #elif defined(CONFIG_CANCam)
152 #define FEC_FLASHMAC 0xf0020000
153 #elif defined (CONFIG_M5272C3)
154 #define FEC_FLASHMAC (0xffe04000 + 4)
155 #elif defined(CONFIG_MOD5272)
156 #define FEC_FLASHMAC 0xffc0406b
158 #define FEC_FLASHMAC 0
160 #endif /* CONFIG_M5272 */
162 #if (((RX_RING_SIZE + TX_RING_SIZE) * 32) > PAGE_SIZE)
163 #error "FEC: descriptor ring size constants too large"
166 /* Interrupt events/masks. */
167 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
168 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
169 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
170 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
171 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
172 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
173 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
174 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
175 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
176 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
178 #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII)
179 #define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF))
181 /* The FEC stores dest/src/type, data, and checksum for receive packets.
183 #define PKT_MAXBUF_SIZE 1518
184 #define PKT_MINBUF_SIZE 64
185 #define PKT_MAXBLR_SIZE 1520
187 /* FEC receive acceleration */
188 #define FEC_RACC_IPDIS (1 << 1)
189 #define FEC_RACC_PRODIS (1 << 2)
190 #define FEC_RACC_OPTIONS (FEC_RACC_IPDIS | FEC_RACC_PRODIS)
193 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
194 * size bits. Other FEC hardware does not, so we need to take that into
195 * account when setting it.
197 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
198 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM)
199 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
201 #define OPT_FRAME_SIZE 0
204 /* FEC MII MMFR bits definition */
205 #define FEC_MMFR_ST (1 << 30)
206 #define FEC_MMFR_OP_READ (2 << 28)
207 #define FEC_MMFR_OP_WRITE (1 << 28)
208 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
209 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
210 #define FEC_MMFR_TA (2 << 16)
211 #define FEC_MMFR_DATA(v) (v & 0xffff)
213 #define FEC_MII_TIMEOUT 30000 /* us */
215 /* Transmitter timeout */
216 #define TX_TIMEOUT (2 * HZ)
218 #define FEC_PAUSE_FLAG_AUTONEG 0x1
219 #define FEC_PAUSE_FLAG_ENABLE 0x2
223 static struct bufdesc *fec_enet_get_nextdesc(struct bufdesc *bdp, int is_ex)
225 struct bufdesc_ex *ex = (struct bufdesc_ex *)bdp;
227 return (struct bufdesc *)(ex + 1);
232 static struct bufdesc *fec_enet_get_prevdesc(struct bufdesc *bdp, int is_ex)
234 struct bufdesc_ex *ex = (struct bufdesc_ex *)bdp;
236 return (struct bufdesc *)(ex - 1);
241 static void *swap_buffer(void *bufaddr, int len)
244 unsigned int *buf = bufaddr;
246 for (i = 0; i < (len + 3) / 4; i++, buf++)
247 *buf = cpu_to_be32(*buf);
253 fec_enet_clear_csum(struct sk_buff *skb, struct net_device *ndev)
255 /* Only run for packets requiring a checksum. */
256 if (skb->ip_summed != CHECKSUM_PARTIAL)
259 if (unlikely(skb_cow_head(skb, 0)))
262 *(__sum16 *)(skb->head + skb->csum_start + skb->csum_offset) = 0;
268 fec_enet_start_xmit(struct sk_buff *skb, struct net_device *ndev)
270 struct fec_enet_private *fep = netdev_priv(ndev);
271 const struct platform_device_id *id_entry =
272 platform_get_device_id(fep->pdev);
275 unsigned short status;
279 /* Link is down or auto-negotiation is in progress. */
280 return NETDEV_TX_BUSY;
283 /* Fill in a Tx ring entry */
286 status = bdp->cbd_sc;
288 if (status & BD_ENET_TX_READY) {
289 /* Ooops. All transmit buffers are full. Bail out.
290 * This should not happen, since ndev->tbusy should be set.
292 netdev_err(ndev, "tx queue full!\n");
293 return NETDEV_TX_BUSY;
296 /* Protocol checksum off-load for TCP and UDP. */
297 if (fec_enet_clear_csum(skb, ndev)) {
302 /* Clear all of the status flags */
303 status &= ~BD_ENET_TX_STATS;
305 /* Set buffer length and buffer pointer */
307 bdp->cbd_datlen = skb->len;
310 * On some FEC implementations data must be aligned on
311 * 4-byte boundaries. Use bounce buffers to copy data
312 * and get it aligned. Ugh.
315 index = (struct bufdesc_ex *)bdp -
316 (struct bufdesc_ex *)fep->tx_bd_base;
318 index = bdp - fep->tx_bd_base;
320 if (((unsigned long) bufaddr) & FEC_ALIGNMENT) {
321 memcpy(fep->tx_bounce[index], skb->data, skb->len);
322 bufaddr = fep->tx_bounce[index];
326 * Some design made an incorrect assumption on endian mode of
327 * the system that it's running on. As the result, driver has to
328 * swap every frame going to and coming from the controller.
330 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
331 swap_buffer(bufaddr, skb->len);
333 /* Save skb pointer */
334 fep->tx_skbuff[index] = skb;
336 /* Push the data cache so the CPM does not get stale memory
339 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, bufaddr,
340 FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
342 /* Send it on its way. Tell FEC it's ready, interrupt when done,
343 * it's the last BD of the frame, and to put the CRC on the end.
345 status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR
346 | BD_ENET_TX_LAST | BD_ENET_TX_TC);
347 bdp->cbd_sc = status;
349 if (fep->bufdesc_ex) {
351 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
353 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
355 ebdp->cbd_esc = (BD_ENET_TX_TS | BD_ENET_TX_INT);
356 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
358 ebdp->cbd_esc = BD_ENET_TX_INT;
360 /* Enable protocol checksum flags
361 * We do not bother with the IP Checksum bits as they
362 * are done by the kernel
364 if (skb->ip_summed == CHECKSUM_PARTIAL)
365 ebdp->cbd_esc |= BD_ENET_TX_PINS;
368 /* If this was the last BD in the ring, start at the beginning again. */
369 if (status & BD_ENET_TX_WRAP)
370 bdp = fep->tx_bd_base;
372 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
376 if (fep->cur_tx == fep->dirty_tx)
377 netif_stop_queue(ndev);
379 /* Trigger transmission start */
380 writel(0, fep->hwp + FEC_X_DES_ACTIVE);
382 skb_tx_timestamp(skb);
387 /* Init RX & TX buffer descriptors
389 static void fec_enet_bd_init(struct net_device *dev)
391 struct fec_enet_private *fep = netdev_priv(dev);
395 /* Initialize the receive buffer descriptors. */
396 bdp = fep->rx_bd_base;
397 for (i = 0; i < RX_RING_SIZE; i++) {
399 /* Initialize the BD for every fragment in the page. */
400 if (bdp->cbd_bufaddr)
401 bdp->cbd_sc = BD_ENET_RX_EMPTY;
404 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
407 /* Set the last buffer to wrap */
408 bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
409 bdp->cbd_sc |= BD_SC_WRAP;
411 fep->cur_rx = fep->rx_bd_base;
413 /* ...and the same for transmit */
414 bdp = fep->tx_bd_base;
416 for (i = 0; i < TX_RING_SIZE; i++) {
418 /* Initialize the BD for every fragment in the page. */
420 if (bdp->cbd_bufaddr && fep->tx_skbuff[i]) {
421 dev_kfree_skb_any(fep->tx_skbuff[i]);
422 fep->tx_skbuff[i] = NULL;
424 bdp->cbd_bufaddr = 0;
425 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
428 /* Set the last buffer to wrap */
429 bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
430 bdp->cbd_sc |= BD_SC_WRAP;
434 /* This function is called to start or restart the FEC during a link
435 * change. This only happens when switching between half and full
439 fec_restart(struct net_device *ndev, int duplex)
441 struct fec_enet_private *fep = netdev_priv(ndev);
442 const struct platform_device_id *id_entry =
443 platform_get_device_id(fep->pdev);
447 u32 rcntl = OPT_FRAME_SIZE | 0x04;
448 u32 ecntl = 0x2; /* ETHEREN */
450 if (netif_running(ndev)) {
451 netif_device_detach(ndev);
452 napi_disable(&fep->napi);
453 netif_stop_queue(ndev);
454 netif_tx_lock_bh(ndev);
457 /* Whack a reset. We should wait for this. */
458 writel(1, fep->hwp + FEC_ECNTRL);
462 * enet-mac reset will reset mac address registers too,
463 * so need to reconfigure it.
465 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
466 memcpy(&temp_mac, ndev->dev_addr, ETH_ALEN);
467 writel(cpu_to_be32(temp_mac[0]), fep->hwp + FEC_ADDR_LOW);
468 writel(cpu_to_be32(temp_mac[1]), fep->hwp + FEC_ADDR_HIGH);
471 /* Clear any outstanding interrupt. */
472 writel(0xffc00000, fep->hwp + FEC_IEVENT);
474 /* Reset all multicast. */
475 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
476 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
478 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH);
479 writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
482 /* Set maximum receive buffer size. */
483 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE);
485 fec_enet_bd_init(ndev);
487 /* Set receive and transmit descriptor base. */
488 writel(fep->bd_dma, fep->hwp + FEC_R_DES_START);
490 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc_ex)
491 * RX_RING_SIZE, fep->hwp + FEC_X_DES_START);
493 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc)
494 * RX_RING_SIZE, fep->hwp + FEC_X_DES_START);
497 for (i = 0; i <= TX_RING_MOD_MASK; i++) {
498 if (fep->tx_skbuff[i]) {
499 dev_kfree_skb_any(fep->tx_skbuff[i]);
500 fep->tx_skbuff[i] = NULL;
504 /* Enable MII mode */
507 writel(0x04, fep->hwp + FEC_X_CNTRL);
511 writel(0x0, fep->hwp + FEC_X_CNTRL);
514 fep->full_duplex = duplex;
517 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
519 #if !defined(CONFIG_M5272)
520 /* set RX checksum */
521 val = readl(fep->hwp + FEC_RACC);
522 if (fep->csum_flags & FLAG_RX_CSUM_ENABLED)
523 val |= FEC_RACC_OPTIONS;
525 val &= ~FEC_RACC_OPTIONS;
526 writel(val, fep->hwp + FEC_RACC);
530 * The phy interface and speed need to get configured
531 * differently on enet-mac.
533 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
534 /* Enable flow control and length check */
535 rcntl |= 0x40000000 | 0x00000020;
537 /* RGMII, RMII or MII */
538 if (fep->phy_interface == PHY_INTERFACE_MODE_RGMII)
540 else if (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
545 /* 1G, 100M or 10M */
547 if (fep->phy_dev->speed == SPEED_1000)
549 else if (fep->phy_dev->speed == SPEED_100)
555 #ifdef FEC_MIIGSK_ENR
556 if (id_entry->driver_data & FEC_QUIRK_USE_GASKET) {
558 /* disable the gasket and wait */
559 writel(0, fep->hwp + FEC_MIIGSK_ENR);
560 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4)
564 * configure the gasket:
565 * RMII, 50 MHz, no loopback, no echo
566 * MII, 25 MHz, no loopback, no echo
568 cfgr = (fep->phy_interface == PHY_INTERFACE_MODE_RMII)
569 ? BM_MIIGSK_CFGR_RMII : BM_MIIGSK_CFGR_MII;
570 if (fep->phy_dev && fep->phy_dev->speed == SPEED_10)
571 cfgr |= BM_MIIGSK_CFGR_FRCONT_10M;
572 writel(cfgr, fep->hwp + FEC_MIIGSK_CFGR);
574 /* re-enable the gasket */
575 writel(2, fep->hwp + FEC_MIIGSK_ENR);
580 #if !defined(CONFIG_M5272)
581 /* enable pause frame*/
582 if ((fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) ||
583 ((fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) &&
584 fep->phy_dev && fep->phy_dev->pause)) {
585 rcntl |= FEC_ENET_FCE;
587 /* set FIFO threshold parameter to reduce overrun */
588 writel(FEC_ENET_RSEM_V, fep->hwp + FEC_R_FIFO_RSEM);
589 writel(FEC_ENET_RSFL_V, fep->hwp + FEC_R_FIFO_RSFL);
590 writel(FEC_ENET_RAEM_V, fep->hwp + FEC_R_FIFO_RAEM);
591 writel(FEC_ENET_RAFL_V, fep->hwp + FEC_R_FIFO_RAFL);
594 writel(FEC_ENET_OPD_V, fep->hwp + FEC_OPD);
596 rcntl &= ~FEC_ENET_FCE;
598 #endif /* !defined(CONFIG_M5272) */
600 writel(rcntl, fep->hwp + FEC_R_CNTRL);
602 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
603 /* enable ENET endian swap */
605 /* enable ENET store and forward mode */
606 writel(1 << 8, fep->hwp + FEC_X_WMRK);
612 /* And last, enable the transmit and receive processing */
613 writel(ecntl, fep->hwp + FEC_ECNTRL);
614 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
617 fec_ptp_start_cyclecounter(ndev);
619 /* Enable interrupts we wish to service */
620 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
622 if (netif_running(ndev)) {
623 netif_tx_unlock_bh(ndev);
624 netif_wake_queue(ndev);
625 napi_enable(&fep->napi);
626 netif_device_attach(ndev);
631 fec_stop(struct net_device *ndev)
633 struct fec_enet_private *fep = netdev_priv(ndev);
634 const struct platform_device_id *id_entry =
635 platform_get_device_id(fep->pdev);
636 u32 rmii_mode = readl(fep->hwp + FEC_R_CNTRL) & (1 << 8);
638 /* We cannot expect a graceful transmit stop without link !!! */
640 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */
642 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA))
643 netdev_err(ndev, "Graceful transmit stop did not complete!\n");
646 /* Whack a reset. We should wait for this. */
647 writel(1, fep->hwp + FEC_ECNTRL);
649 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
650 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
652 /* We have to keep ENET enabled to have MII interrupt stay working */
653 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC) {
654 writel(2, fep->hwp + FEC_ECNTRL);
655 writel(rmii_mode, fep->hwp + FEC_R_CNTRL);
661 fec_timeout(struct net_device *ndev)
663 struct fec_enet_private *fep = netdev_priv(ndev);
665 ndev->stats.tx_errors++;
667 fep->delay_work.timeout = true;
668 schedule_delayed_work(&(fep->delay_work.delay_work), 0);
671 static void fec_enet_work(struct work_struct *work)
673 struct fec_enet_private *fep =
675 struct fec_enet_private,
676 delay_work.delay_work.work);
678 if (fep->delay_work.timeout) {
679 fep->delay_work.timeout = false;
680 fec_restart(fep->netdev, fep->full_duplex);
681 netif_wake_queue(fep->netdev);
686 fec_enet_tx(struct net_device *ndev)
688 struct fec_enet_private *fep;
690 unsigned short status;
694 fep = netdev_priv(ndev);
697 /* get next bdp of dirty_tx */
698 if (bdp->cbd_sc & BD_ENET_TX_WRAP)
699 bdp = fep->tx_bd_base;
701 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
703 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) {
705 /* current queue is empty */
706 if (bdp == fep->cur_tx)
710 index = (struct bufdesc_ex *)bdp -
711 (struct bufdesc_ex *)fep->tx_bd_base;
713 index = bdp - fep->tx_bd_base;
715 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
716 FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE);
717 bdp->cbd_bufaddr = 0;
719 skb = fep->tx_skbuff[index];
721 /* Check for errors. */
722 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC |
723 BD_ENET_TX_RL | BD_ENET_TX_UN |
725 ndev->stats.tx_errors++;
726 if (status & BD_ENET_TX_HB) /* No heartbeat */
727 ndev->stats.tx_heartbeat_errors++;
728 if (status & BD_ENET_TX_LC) /* Late collision */
729 ndev->stats.tx_window_errors++;
730 if (status & BD_ENET_TX_RL) /* Retrans limit */
731 ndev->stats.tx_aborted_errors++;
732 if (status & BD_ENET_TX_UN) /* Underrun */
733 ndev->stats.tx_fifo_errors++;
734 if (status & BD_ENET_TX_CSL) /* Carrier lost */
735 ndev->stats.tx_carrier_errors++;
737 ndev->stats.tx_packets++;
740 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS) &&
742 struct skb_shared_hwtstamps shhwtstamps;
744 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
746 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
747 spin_lock_irqsave(&fep->tmreg_lock, flags);
748 shhwtstamps.hwtstamp = ns_to_ktime(
749 timecounter_cyc2time(&fep->tc, ebdp->ts));
750 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
751 skb_tstamp_tx(skb, &shhwtstamps);
754 if (status & BD_ENET_TX_READY)
755 netdev_err(ndev, "HEY! Enet xmit interrupt and TX_READY\n");
757 /* Deferred means some collisions occurred during transmit,
758 * but we eventually sent the packet OK.
760 if (status & BD_ENET_TX_DEF)
761 ndev->stats.collisions++;
763 /* Free the sk buffer associated with this last transmit */
764 dev_kfree_skb_any(skb);
765 fep->tx_skbuff[index] = NULL;
769 /* Update pointer to next buffer descriptor to be transmitted */
770 if (status & BD_ENET_TX_WRAP)
771 bdp = fep->tx_bd_base;
773 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
775 /* Since we have freed up a buffer, the ring is no longer full
777 if (fep->dirty_tx != fep->cur_tx) {
778 if (netif_queue_stopped(ndev))
779 netif_wake_queue(ndev);
786 /* During a receive, the cur_rx points to the current incoming buffer.
787 * When we update through the ring, if the next incoming buffer has
788 * not been given to the system, we just set the empty indicator,
789 * effectively tossing the packet.
792 fec_enet_rx(struct net_device *ndev, int budget)
794 struct fec_enet_private *fep = netdev_priv(ndev);
795 const struct platform_device_id *id_entry =
796 platform_get_device_id(fep->pdev);
798 unsigned short status;
802 int pkt_received = 0;
808 /* First, grab all of the stats for the incoming packet.
809 * These get messed up if we get called due to a busy condition.
813 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) {
815 if (pkt_received >= budget)
819 /* Since we have allocated space to hold a complete frame,
820 * the last indicator should be set.
822 if ((status & BD_ENET_RX_LAST) == 0)
823 netdev_err(ndev, "rcv is not +last\n");
826 goto rx_processing_done;
828 /* Check for errors. */
829 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO |
830 BD_ENET_RX_CR | BD_ENET_RX_OV)) {
831 ndev->stats.rx_errors++;
832 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) {
833 /* Frame too long or too short. */
834 ndev->stats.rx_length_errors++;
836 if (status & BD_ENET_RX_NO) /* Frame alignment */
837 ndev->stats.rx_frame_errors++;
838 if (status & BD_ENET_RX_CR) /* CRC Error */
839 ndev->stats.rx_crc_errors++;
840 if (status & BD_ENET_RX_OV) /* FIFO overrun */
841 ndev->stats.rx_fifo_errors++;
844 /* Report late collisions as a frame error.
845 * On this error, the BD is closed, but we don't know what we
846 * have in the buffer. So, just drop this frame on the floor.
848 if (status & BD_ENET_RX_CL) {
849 ndev->stats.rx_errors++;
850 ndev->stats.rx_frame_errors++;
851 goto rx_processing_done;
854 /* Process the incoming frame. */
855 ndev->stats.rx_packets++;
856 pkt_len = bdp->cbd_datlen;
857 ndev->stats.rx_bytes += pkt_len;
858 data = (__u8*)__va(bdp->cbd_bufaddr);
860 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
861 FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE);
863 if (id_entry->driver_data & FEC_QUIRK_SWAP_FRAME)
864 swap_buffer(data, pkt_len);
866 /* This does 16 byte alignment, exactly what we need.
867 * The packet length includes FCS, but we don't want to
868 * include that when passing upstream as it messes up
869 * bridging applications.
871 skb = netdev_alloc_skb(ndev, pkt_len - 4 + NET_IP_ALIGN);
873 if (unlikely(!skb)) {
874 ndev->stats.rx_dropped++;
876 skb_reserve(skb, NET_IP_ALIGN);
877 skb_put(skb, pkt_len - 4); /* Make room */
878 skb_copy_to_linear_data(skb, data, pkt_len - 4);
879 skb->protocol = eth_type_trans(skb, ndev);
881 /* Get receive timestamp from the skb */
882 if (fep->hwts_rx_en && fep->bufdesc_ex) {
883 struct skb_shared_hwtstamps *shhwtstamps =
886 struct bufdesc_ex *ebdp =
887 (struct bufdesc_ex *)bdp;
889 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
891 spin_lock_irqsave(&fep->tmreg_lock, flags);
892 shhwtstamps->hwtstamp = ns_to_ktime(
893 timecounter_cyc2time(&fep->tc, ebdp->ts));
894 spin_unlock_irqrestore(&fep->tmreg_lock, flags);
897 if (fep->bufdesc_ex &&
898 (fep->csum_flags & FLAG_RX_CSUM_ENABLED)) {
899 struct bufdesc_ex *ebdp =
900 (struct bufdesc_ex *)bdp;
901 if (!(ebdp->cbd_esc & FLAG_RX_CSUM_ERROR)) {
903 skb->ip_summed = CHECKSUM_UNNECESSARY;
905 skb_checksum_none_assert(skb);
909 if (!skb_defer_rx_timestamp(skb))
910 napi_gro_receive(&fep->napi, skb);
913 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, data,
914 FEC_ENET_TX_FRSIZE, DMA_FROM_DEVICE);
916 /* Clear the status flags for this buffer */
917 status &= ~BD_ENET_RX_STATS;
919 /* Mark the buffer empty */
920 status |= BD_ENET_RX_EMPTY;
921 bdp->cbd_sc = status;
923 if (fep->bufdesc_ex) {
924 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
926 ebdp->cbd_esc = BD_ENET_RX_INT;
931 /* Update BD pointer to next entry */
932 if (status & BD_ENET_RX_WRAP)
933 bdp = fep->rx_bd_base;
935 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
936 /* Doing this here will keep the FEC running while we process
937 * incoming frames. On a heavily loaded network, we should be
938 * able to keep up at the expense of system resources.
940 writel(0, fep->hwp + FEC_R_DES_ACTIVE);
948 fec_enet_interrupt(int irq, void *dev_id)
950 struct net_device *ndev = dev_id;
951 struct fec_enet_private *fep = netdev_priv(ndev);
953 irqreturn_t ret = IRQ_NONE;
956 int_events = readl(fep->hwp + FEC_IEVENT);
957 writel(int_events, fep->hwp + FEC_IEVENT);
959 if (int_events & (FEC_ENET_RXF | FEC_ENET_TXF)) {
962 /* Disable the RX interrupt */
963 if (napi_schedule_prep(&fep->napi)) {
964 writel(FEC_RX_DISABLED_IMASK,
965 fep->hwp + FEC_IMASK);
966 __napi_schedule(&fep->napi);
970 if (int_events & FEC_ENET_MII) {
972 complete(&fep->mdio_done);
974 } while (int_events);
979 static int fec_enet_rx_napi(struct napi_struct *napi, int budget)
981 struct net_device *ndev = napi->dev;
982 int pkts = fec_enet_rx(ndev, budget);
983 struct fec_enet_private *fep = netdev_priv(ndev);
989 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK);
994 /* ------------------------------------------------------------------------- */
995 static void fec_get_mac(struct net_device *ndev)
997 struct fec_enet_private *fep = netdev_priv(ndev);
998 struct fec_platform_data *pdata = fep->pdev->dev.platform_data;
999 unsigned char *iap, tmpaddr[ETH_ALEN];
1002 * try to get mac address in following order:
1004 * 1) module parameter via kernel command line in form
1005 * fec.macaddr=0x00,0x04,0x9f,0x01,0x30,0xe0
1010 * 2) from device tree data
1012 if (!is_valid_ether_addr(iap)) {
1013 struct device_node *np = fep->pdev->dev.of_node;
1015 const char *mac = of_get_mac_address(np);
1017 iap = (unsigned char *) mac;
1022 * 3) from flash or fuse (via platform data)
1024 if (!is_valid_ether_addr(iap)) {
1027 iap = (unsigned char *)FEC_FLASHMAC;
1030 iap = (unsigned char *)&pdata->mac;
1035 * 4) FEC mac registers set by bootloader
1037 if (!is_valid_ether_addr(iap)) {
1038 *((unsigned long *) &tmpaddr[0]) =
1039 be32_to_cpu(readl(fep->hwp + FEC_ADDR_LOW));
1040 *((unsigned short *) &tmpaddr[4]) =
1041 be16_to_cpu(readl(fep->hwp + FEC_ADDR_HIGH) >> 16);
1046 * 5) random mac address
1048 if (!is_valid_ether_addr(iap)) {
1049 /* Report it and use a random ethernet address instead */
1050 netdev_err(ndev, "Invalid MAC address: %pM\n", iap);
1051 eth_hw_addr_random(ndev);
1052 netdev_info(ndev, "Using random MAC address: %pM\n",
1057 memcpy(ndev->dev_addr, iap, ETH_ALEN);
1059 /* Adjust MAC if using macaddr */
1061 ndev->dev_addr[ETH_ALEN-1] = macaddr[ETH_ALEN-1] + fep->dev_id;
1064 /* ------------------------------------------------------------------------- */
1069 static void fec_enet_adjust_link(struct net_device *ndev)
1071 struct fec_enet_private *fep = netdev_priv(ndev);
1072 struct phy_device *phy_dev = fep->phy_dev;
1073 int status_change = 0;
1075 /* Prevent a state halted on mii error */
1076 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) {
1077 phy_dev->state = PHY_RESUMING;
1081 if (phy_dev->link) {
1083 fep->link = phy_dev->link;
1087 if (fep->full_duplex != phy_dev->duplex)
1090 if (phy_dev->speed != fep->speed) {
1091 fep->speed = phy_dev->speed;
1095 /* if any of the above changed restart the FEC */
1097 fec_restart(ndev, phy_dev->duplex);
1101 fep->link = phy_dev->link;
1107 phy_print_status(phy_dev);
1110 static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
1112 struct fec_enet_private *fep = bus->priv;
1113 unsigned long time_left;
1115 fep->mii_timeout = 0;
1116 init_completion(&fep->mdio_done);
1118 /* start a read op */
1119 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
1120 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1121 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
1123 /* wait for end of transfer */
1124 time_left = wait_for_completion_timeout(&fep->mdio_done,
1125 usecs_to_jiffies(FEC_MII_TIMEOUT));
1126 if (time_left == 0) {
1127 fep->mii_timeout = 1;
1128 netdev_err(fep->netdev, "MDIO read timeout\n");
1133 return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA));
1136 static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
1139 struct fec_enet_private *fep = bus->priv;
1140 unsigned long time_left;
1142 fep->mii_timeout = 0;
1143 init_completion(&fep->mdio_done);
1145 /* start a write op */
1146 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
1147 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
1148 FEC_MMFR_TA | FEC_MMFR_DATA(value),
1149 fep->hwp + FEC_MII_DATA);
1151 /* wait for end of transfer */
1152 time_left = wait_for_completion_timeout(&fep->mdio_done,
1153 usecs_to_jiffies(FEC_MII_TIMEOUT));
1154 if (time_left == 0) {
1155 fep->mii_timeout = 1;
1156 netdev_err(fep->netdev, "MDIO write timeout\n");
1163 static int fec_enet_mdio_reset(struct mii_bus *bus)
1168 static int fec_enet_mii_probe(struct net_device *ndev)
1170 struct fec_enet_private *fep = netdev_priv(ndev);
1171 const struct platform_device_id *id_entry =
1172 platform_get_device_id(fep->pdev);
1173 struct phy_device *phy_dev = NULL;
1174 char mdio_bus_id[MII_BUS_ID_SIZE];
1175 char phy_name[MII_BUS_ID_SIZE + 3];
1177 int dev_id = fep->dev_id;
1179 fep->phy_dev = NULL;
1181 /* check for attached phy */
1182 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) {
1183 if ((fep->mii_bus->phy_mask & (1 << phy_id)))
1185 if (fep->mii_bus->phy_map[phy_id] == NULL)
1187 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0)
1191 strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE);
1195 if (phy_id >= PHY_MAX_ADDR) {
1196 netdev_info(ndev, "no PHY, assuming direct connection to switch\n");
1197 strncpy(mdio_bus_id, "fixed-0", MII_BUS_ID_SIZE);
1201 snprintf(phy_name, sizeof(phy_name), PHY_ID_FMT, mdio_bus_id, phy_id);
1202 phy_dev = phy_connect(ndev, phy_name, &fec_enet_adjust_link,
1203 fep->phy_interface);
1204 if (IS_ERR(phy_dev)) {
1205 netdev_err(ndev, "could not attach to PHY\n");
1206 return PTR_ERR(phy_dev);
1209 /* mask with MAC supported features */
1210 if (id_entry->driver_data & FEC_QUIRK_HAS_GBIT) {
1211 phy_dev->supported &= PHY_GBIT_FEATURES;
1212 #if !defined(CONFIG_M5272)
1213 phy_dev->supported |= SUPPORTED_Pause;
1217 phy_dev->supported &= PHY_BASIC_FEATURES;
1219 phy_dev->advertising = phy_dev->supported;
1221 fep->phy_dev = phy_dev;
1223 fep->full_duplex = 0;
1225 netdev_info(ndev, "Freescale FEC PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
1226 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev),
1232 static int fec_enet_mii_init(struct platform_device *pdev)
1234 static struct mii_bus *fec0_mii_bus;
1235 struct net_device *ndev = platform_get_drvdata(pdev);
1236 struct fec_enet_private *fep = netdev_priv(ndev);
1237 const struct platform_device_id *id_entry =
1238 platform_get_device_id(fep->pdev);
1239 int err = -ENXIO, i;
1242 * The dual fec interfaces are not equivalent with enet-mac.
1243 * Here are the differences:
1245 * - fec0 supports MII & RMII modes while fec1 only supports RMII
1246 * - fec0 acts as the 1588 time master while fec1 is slave
1247 * - external phys can only be configured by fec0
1249 * That is to say fec1 can not work independently. It only works
1250 * when fec0 is working. The reason behind this design is that the
1251 * second interface is added primarily for Switch mode.
1253 * Because of the last point above, both phys are attached on fec0
1254 * mdio interface in board design, and need to be configured by
1257 if ((id_entry->driver_data & FEC_QUIRK_ENET_MAC) && fep->dev_id > 0) {
1258 /* fec1 uses fec0 mii_bus */
1259 if (mii_cnt && fec0_mii_bus) {
1260 fep->mii_bus = fec0_mii_bus;
1267 fep->mii_timeout = 0;
1270 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
1272 * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
1273 * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'. The i.MX28
1274 * Reference Manual has an error on this, and gets fixed on i.MX6Q
1277 fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk_ahb), 5000000);
1278 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1280 fep->phy_speed <<= 1;
1281 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED);
1283 fep->mii_bus = mdiobus_alloc();
1284 if (fep->mii_bus == NULL) {
1289 fep->mii_bus->name = "fec_enet_mii_bus";
1290 fep->mii_bus->read = fec_enet_mdio_read;
1291 fep->mii_bus->write = fec_enet_mdio_write;
1292 fep->mii_bus->reset = fec_enet_mdio_reset;
1293 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1294 pdev->name, fep->dev_id + 1);
1295 fep->mii_bus->priv = fep;
1296 fep->mii_bus->parent = &pdev->dev;
1298 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
1299 if (!fep->mii_bus->irq) {
1301 goto err_out_free_mdiobus;
1304 for (i = 0; i < PHY_MAX_ADDR; i++)
1305 fep->mii_bus->irq[i] = PHY_POLL;
1307 if (mdiobus_register(fep->mii_bus))
1308 goto err_out_free_mdio_irq;
1312 /* save fec0 mii_bus */
1313 if (id_entry->driver_data & FEC_QUIRK_ENET_MAC)
1314 fec0_mii_bus = fep->mii_bus;
1318 err_out_free_mdio_irq:
1319 kfree(fep->mii_bus->irq);
1320 err_out_free_mdiobus:
1321 mdiobus_free(fep->mii_bus);
1326 static void fec_enet_mii_remove(struct fec_enet_private *fep)
1328 if (--mii_cnt == 0) {
1329 mdiobus_unregister(fep->mii_bus);
1330 kfree(fep->mii_bus->irq);
1331 mdiobus_free(fep->mii_bus);
1335 static int fec_enet_get_settings(struct net_device *ndev,
1336 struct ethtool_cmd *cmd)
1338 struct fec_enet_private *fep = netdev_priv(ndev);
1339 struct phy_device *phydev = fep->phy_dev;
1344 return phy_ethtool_gset(phydev, cmd);
1347 static int fec_enet_set_settings(struct net_device *ndev,
1348 struct ethtool_cmd *cmd)
1350 struct fec_enet_private *fep = netdev_priv(ndev);
1351 struct phy_device *phydev = fep->phy_dev;
1356 return phy_ethtool_sset(phydev, cmd);
1359 static void fec_enet_get_drvinfo(struct net_device *ndev,
1360 struct ethtool_drvinfo *info)
1362 struct fec_enet_private *fep = netdev_priv(ndev);
1364 strlcpy(info->driver, fep->pdev->dev.driver->name,
1365 sizeof(info->driver));
1366 strlcpy(info->version, "Revision: 1.0", sizeof(info->version));
1367 strlcpy(info->bus_info, dev_name(&ndev->dev), sizeof(info->bus_info));
1370 static int fec_enet_get_ts_info(struct net_device *ndev,
1371 struct ethtool_ts_info *info)
1373 struct fec_enet_private *fep = netdev_priv(ndev);
1375 if (fep->bufdesc_ex) {
1377 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
1378 SOF_TIMESTAMPING_RX_SOFTWARE |
1379 SOF_TIMESTAMPING_SOFTWARE |
1380 SOF_TIMESTAMPING_TX_HARDWARE |
1381 SOF_TIMESTAMPING_RX_HARDWARE |
1382 SOF_TIMESTAMPING_RAW_HARDWARE;
1384 info->phc_index = ptp_clock_index(fep->ptp_clock);
1386 info->phc_index = -1;
1388 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
1389 (1 << HWTSTAMP_TX_ON);
1391 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
1392 (1 << HWTSTAMP_FILTER_ALL);
1395 return ethtool_op_get_ts_info(ndev, info);
1399 #if !defined(CONFIG_M5272)
1401 static void fec_enet_get_pauseparam(struct net_device *ndev,
1402 struct ethtool_pauseparam *pause)
1404 struct fec_enet_private *fep = netdev_priv(ndev);
1406 pause->autoneg = (fep->pause_flag & FEC_PAUSE_FLAG_AUTONEG) != 0;
1407 pause->tx_pause = (fep->pause_flag & FEC_PAUSE_FLAG_ENABLE) != 0;
1408 pause->rx_pause = pause->tx_pause;
1411 static int fec_enet_set_pauseparam(struct net_device *ndev,
1412 struct ethtool_pauseparam *pause)
1414 struct fec_enet_private *fep = netdev_priv(ndev);
1416 if (pause->tx_pause != pause->rx_pause) {
1418 "hardware only support enable/disable both tx and rx");
1422 fep->pause_flag = 0;
1424 /* tx pause must be same as rx pause */
1425 fep->pause_flag |= pause->rx_pause ? FEC_PAUSE_FLAG_ENABLE : 0;
1426 fep->pause_flag |= pause->autoneg ? FEC_PAUSE_FLAG_AUTONEG : 0;
1428 if (pause->rx_pause || pause->autoneg) {
1429 fep->phy_dev->supported |= ADVERTISED_Pause;
1430 fep->phy_dev->advertising |= ADVERTISED_Pause;
1432 fep->phy_dev->supported &= ~ADVERTISED_Pause;
1433 fep->phy_dev->advertising &= ~ADVERTISED_Pause;
1436 if (pause->autoneg) {
1437 if (netif_running(ndev))
1439 phy_start_aneg(fep->phy_dev);
1441 if (netif_running(ndev))
1442 fec_restart(ndev, 0);
1447 #endif /* !defined(CONFIG_M5272) */
1449 static const struct ethtool_ops fec_enet_ethtool_ops = {
1450 #if !defined(CONFIG_M5272)
1451 .get_pauseparam = fec_enet_get_pauseparam,
1452 .set_pauseparam = fec_enet_set_pauseparam,
1454 .get_settings = fec_enet_get_settings,
1455 .set_settings = fec_enet_set_settings,
1456 .get_drvinfo = fec_enet_get_drvinfo,
1457 .get_link = ethtool_op_get_link,
1458 .get_ts_info = fec_enet_get_ts_info,
1461 static int fec_enet_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
1463 struct fec_enet_private *fep = netdev_priv(ndev);
1464 struct phy_device *phydev = fep->phy_dev;
1466 if (!netif_running(ndev))
1472 if (cmd == SIOCSHWTSTAMP && fep->bufdesc_ex)
1473 return fec_ptp_ioctl(ndev, rq, cmd);
1475 return phy_mii_ioctl(phydev, rq, cmd);
1478 static void fec_enet_free_buffers(struct net_device *ndev)
1480 struct fec_enet_private *fep = netdev_priv(ndev);
1482 struct sk_buff *skb;
1483 struct bufdesc *bdp;
1485 bdp = fep->rx_bd_base;
1486 for (i = 0; i < RX_RING_SIZE; i++) {
1487 skb = fep->rx_skbuff[i];
1489 if (bdp->cbd_bufaddr)
1490 dma_unmap_single(&fep->pdev->dev, bdp->cbd_bufaddr,
1491 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1494 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
1497 bdp = fep->tx_bd_base;
1498 for (i = 0; i < TX_RING_SIZE; i++)
1499 kfree(fep->tx_bounce[i]);
1502 static int fec_enet_alloc_buffers(struct net_device *ndev)
1504 struct fec_enet_private *fep = netdev_priv(ndev);
1506 struct sk_buff *skb;
1507 struct bufdesc *bdp;
1509 bdp = fep->rx_bd_base;
1510 for (i = 0; i < RX_RING_SIZE; i++) {
1511 skb = netdev_alloc_skb(ndev, FEC_ENET_RX_FRSIZE);
1513 fec_enet_free_buffers(ndev);
1516 fep->rx_skbuff[i] = skb;
1518 bdp->cbd_bufaddr = dma_map_single(&fep->pdev->dev, skb->data,
1519 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE);
1520 bdp->cbd_sc = BD_ENET_RX_EMPTY;
1522 if (fep->bufdesc_ex) {
1523 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1524 ebdp->cbd_esc = BD_ENET_RX_INT;
1527 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
1530 /* Set the last buffer to wrap. */
1531 bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
1532 bdp->cbd_sc |= BD_SC_WRAP;
1534 bdp = fep->tx_bd_base;
1535 for (i = 0; i < TX_RING_SIZE; i++) {
1536 fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL);
1539 bdp->cbd_bufaddr = 0;
1541 if (fep->bufdesc_ex) {
1542 struct bufdesc_ex *ebdp = (struct bufdesc_ex *)bdp;
1543 ebdp->cbd_esc = BD_ENET_TX_INT;
1546 bdp = fec_enet_get_nextdesc(bdp, fep->bufdesc_ex);
1549 /* Set the last buffer to wrap. */
1550 bdp = fec_enet_get_prevdesc(bdp, fep->bufdesc_ex);
1551 bdp->cbd_sc |= BD_SC_WRAP;
1557 fec_enet_open(struct net_device *ndev)
1559 struct fec_enet_private *fep = netdev_priv(ndev);
1562 napi_enable(&fep->napi);
1564 /* I should reset the ring buffers here, but I don't yet know
1565 * a simple way to do that.
1568 ret = fec_enet_alloc_buffers(ndev);
1572 /* Probe and connect to PHY when open the interface */
1573 ret = fec_enet_mii_probe(ndev);
1575 fec_enet_free_buffers(ndev);
1578 phy_start(fep->phy_dev);
1579 netif_start_queue(ndev);
1585 fec_enet_close(struct net_device *ndev)
1587 struct fec_enet_private *fep = netdev_priv(ndev);
1589 /* Don't know what to do yet. */
1590 napi_disable(&fep->napi);
1592 netif_stop_queue(ndev);
1596 phy_stop(fep->phy_dev);
1597 phy_disconnect(fep->phy_dev);
1600 fec_enet_free_buffers(ndev);
1605 /* Set or clear the multicast filter for this adaptor.
1606 * Skeleton taken from sunlance driver.
1607 * The CPM Ethernet implementation allows Multicast as well as individual
1608 * MAC address filtering. Some of the drivers check to make sure it is
1609 * a group multicast address, and discard those that are not. I guess I
1610 * will do the same for now, but just remove the test if you want
1611 * individual filtering as well (do the upper net layers want or support
1612 * this kind of feature?).
1615 #define HASH_BITS 6 /* #bits in hash */
1616 #define CRC32_POLY 0xEDB88320
1618 static void set_multicast_list(struct net_device *ndev)
1620 struct fec_enet_private *fep = netdev_priv(ndev);
1621 struct netdev_hw_addr *ha;
1622 unsigned int i, bit, data, crc, tmp;
1625 if (ndev->flags & IFF_PROMISC) {
1626 tmp = readl(fep->hwp + FEC_R_CNTRL);
1628 writel(tmp, fep->hwp + FEC_R_CNTRL);
1632 tmp = readl(fep->hwp + FEC_R_CNTRL);
1634 writel(tmp, fep->hwp + FEC_R_CNTRL);
1636 if (ndev->flags & IFF_ALLMULTI) {
1637 /* Catch all multicast addresses, so set the
1640 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1641 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1646 /* Clear filter and add the addresses in hash register
1648 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1649 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1651 netdev_for_each_mc_addr(ha, ndev) {
1652 /* calculate crc32 value of mac address */
1655 for (i = 0; i < ndev->addr_len; i++) {
1657 for (bit = 0; bit < 8; bit++, data >>= 1) {
1659 (((crc ^ data) & 1) ? CRC32_POLY : 0);
1663 /* only upper 6 bits (HASH_BITS) are used
1664 * which point to specific bit in he hash registers
1666 hash = (crc >> (32 - HASH_BITS)) & 0x3f;
1669 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1670 tmp |= 1 << (hash - 32);
1671 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH);
1673 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1675 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW);
1680 /* Set a MAC change in hardware. */
1682 fec_set_mac_address(struct net_device *ndev, void *p)
1684 struct fec_enet_private *fep = netdev_priv(ndev);
1685 struct sockaddr *addr = p;
1687 if (!is_valid_ether_addr(addr->sa_data))
1688 return -EADDRNOTAVAIL;
1690 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
1692 writel(ndev->dev_addr[3] | (ndev->dev_addr[2] << 8) |
1693 (ndev->dev_addr[1] << 16) | (ndev->dev_addr[0] << 24),
1694 fep->hwp + FEC_ADDR_LOW);
1695 writel((ndev->dev_addr[5] << 16) | (ndev->dev_addr[4] << 24),
1696 fep->hwp + FEC_ADDR_HIGH);
1700 #ifdef CONFIG_NET_POLL_CONTROLLER
1702 * fec_poll_controller - FEC Poll controller function
1703 * @dev: The FEC network adapter
1705 * Polled functionality used by netconsole and others in non interrupt mode
1708 static void fec_poll_controller(struct net_device *dev)
1711 struct fec_enet_private *fep = netdev_priv(dev);
1713 for (i = 0; i < FEC_IRQ_NUM; i++) {
1714 if (fep->irq[i] > 0) {
1715 disable_irq(fep->irq[i]);
1716 fec_enet_interrupt(fep->irq[i], dev);
1717 enable_irq(fep->irq[i]);
1723 static int fec_set_features(struct net_device *netdev,
1724 netdev_features_t features)
1726 struct fec_enet_private *fep = netdev_priv(netdev);
1727 netdev_features_t changed = features ^ netdev->features;
1729 netdev->features = features;
1731 /* Receive checksum has been changed */
1732 if (changed & NETIF_F_RXCSUM) {
1733 if (features & NETIF_F_RXCSUM)
1734 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
1736 fep->csum_flags &= ~FLAG_RX_CSUM_ENABLED;
1738 if (netif_running(netdev)) {
1740 fec_restart(netdev, fep->phy_dev->duplex);
1741 netif_wake_queue(netdev);
1743 fec_restart(netdev, fep->phy_dev->duplex);
1750 static const struct net_device_ops fec_netdev_ops = {
1751 .ndo_open = fec_enet_open,
1752 .ndo_stop = fec_enet_close,
1753 .ndo_start_xmit = fec_enet_start_xmit,
1754 .ndo_set_rx_mode = set_multicast_list,
1755 .ndo_change_mtu = eth_change_mtu,
1756 .ndo_validate_addr = eth_validate_addr,
1757 .ndo_tx_timeout = fec_timeout,
1758 .ndo_set_mac_address = fec_set_mac_address,
1759 .ndo_do_ioctl = fec_enet_ioctl,
1760 #ifdef CONFIG_NET_POLL_CONTROLLER
1761 .ndo_poll_controller = fec_poll_controller,
1763 .ndo_set_features = fec_set_features,
1767 * XXX: We need to clean up on failure exits here.
1770 static int fec_enet_init(struct net_device *ndev)
1772 struct fec_enet_private *fep = netdev_priv(ndev);
1773 const struct platform_device_id *id_entry =
1774 platform_get_device_id(fep->pdev);
1775 struct bufdesc *cbd_base;
1777 /* Allocate memory for buffer descriptors. */
1778 cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma,
1783 memset(cbd_base, 0, PAGE_SIZE);
1787 /* Get the Ethernet address */
1790 /* Set receive and transmit descriptor base. */
1791 fep->rx_bd_base = cbd_base;
1792 if (fep->bufdesc_ex)
1793 fep->tx_bd_base = (struct bufdesc *)
1794 (((struct bufdesc_ex *)cbd_base) + RX_RING_SIZE);
1796 fep->tx_bd_base = cbd_base + RX_RING_SIZE;
1798 /* The FEC Ethernet specific entries in the device structure */
1799 ndev->watchdog_timeo = TX_TIMEOUT;
1800 ndev->netdev_ops = &fec_netdev_ops;
1801 ndev->ethtool_ops = &fec_enet_ethtool_ops;
1803 writel(FEC_RX_DISABLED_IMASK, fep->hwp + FEC_IMASK);
1804 netif_napi_add(ndev, &fep->napi, fec_enet_rx_napi, FEC_NAPI_WEIGHT);
1806 if (id_entry->driver_data & FEC_QUIRK_HAS_CSUM) {
1807 /* enable hw accelerator */
1808 ndev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
1810 ndev->hw_features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM
1812 fep->csum_flags |= FLAG_RX_CSUM_ENABLED;
1815 fec_restart(ndev, 0);
1821 static void fec_reset_phy(struct platform_device *pdev)
1825 struct device_node *np = pdev->dev.of_node;
1830 of_property_read_u32(np, "phy-reset-duration", &msec);
1831 /* A sane reset duration should not be longer than 1s */
1835 phy_reset = of_get_named_gpio(np, "phy-reset-gpios", 0);
1836 if (!gpio_is_valid(phy_reset))
1839 err = devm_gpio_request_one(&pdev->dev, phy_reset,
1840 GPIOF_OUT_INIT_LOW, "phy-reset");
1842 dev_err(&pdev->dev, "failed to get phy-reset-gpios: %d\n", err);
1846 gpio_set_value(phy_reset, 1);
1848 #else /* CONFIG_OF */
1849 static void fec_reset_phy(struct platform_device *pdev)
1852 * In case of platform probe, the reset has been done
1856 #endif /* CONFIG_OF */
1859 fec_probe(struct platform_device *pdev)
1861 struct fec_enet_private *fep;
1862 struct fec_platform_data *pdata;
1863 struct net_device *ndev;
1864 int i, irq, ret = 0;
1866 const struct of_device_id *of_id;
1868 struct pinctrl *pinctrl;
1869 struct regulator *reg_phy;
1871 of_id = of_match_device(fec_dt_ids, &pdev->dev);
1873 pdev->id_entry = of_id->data;
1875 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1879 /* Init network device */
1880 ndev = alloc_etherdev(sizeof(struct fec_enet_private));
1884 SET_NETDEV_DEV(ndev, &pdev->dev);
1886 /* setup board info structure */
1887 fep = netdev_priv(ndev);
1889 #if !defined(CONFIG_M5272)
1890 /* default enable pause frame auto negotiation */
1891 if (pdev->id_entry &&
1892 (pdev->id_entry->driver_data & FEC_QUIRK_HAS_GBIT))
1893 fep->pause_flag |= FEC_PAUSE_FLAG_AUTONEG;
1896 fep->hwp = devm_request_and_ioremap(&pdev->dev, r);
1898 fep->dev_id = dev_id++;
1900 fep->bufdesc_ex = 0;
1904 goto failed_ioremap;
1907 platform_set_drvdata(pdev, ndev);
1909 ret = of_get_phy_mode(pdev->dev.of_node);
1911 pdata = pdev->dev.platform_data;
1913 fep->phy_interface = pdata->phy;
1915 fep->phy_interface = PHY_INTERFACE_MODE_MII;
1917 fep->phy_interface = ret;
1920 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
1921 if (IS_ERR(pinctrl)) {
1922 ret = PTR_ERR(pinctrl);
1926 fep->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1927 if (IS_ERR(fep->clk_ipg)) {
1928 ret = PTR_ERR(fep->clk_ipg);
1932 fep->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1933 if (IS_ERR(fep->clk_ahb)) {
1934 ret = PTR_ERR(fep->clk_ahb);
1938 /* enet_out is optional, depends on board */
1939 fep->clk_enet_out = devm_clk_get(&pdev->dev, "enet_out");
1940 if (IS_ERR(fep->clk_enet_out))
1941 fep->clk_enet_out = NULL;
1943 fep->clk_ptp = devm_clk_get(&pdev->dev, "ptp");
1945 pdev->id_entry->driver_data & FEC_QUIRK_HAS_BUFDESC_EX;
1946 if (IS_ERR(fep->clk_ptp)) {
1947 fep->clk_ptp = NULL;
1948 fep->bufdesc_ex = 0;
1951 clk_prepare_enable(fep->clk_ahb);
1952 clk_prepare_enable(fep->clk_ipg);
1953 clk_prepare_enable(fep->clk_enet_out);
1954 clk_prepare_enable(fep->clk_ptp);
1956 reg_phy = devm_regulator_get(&pdev->dev, "phy");
1957 if (!IS_ERR(reg_phy)) {
1958 ret = regulator_enable(reg_phy);
1961 "Failed to enable phy regulator: %d\n", ret);
1962 goto failed_regulator;
1966 fec_reset_phy(pdev);
1968 if (fep->bufdesc_ex)
1969 fec_ptp_init(ndev, pdev);
1971 ret = fec_enet_init(ndev);
1975 for (i = 0; i < FEC_IRQ_NUM; i++) {
1976 irq = platform_get_irq(pdev, i);
1983 ret = request_irq(irq, fec_enet_interrupt, IRQF_DISABLED, pdev->name, ndev);
1986 irq = platform_get_irq(pdev, i);
1987 free_irq(irq, ndev);
1993 ret = fec_enet_mii_init(pdev);
1995 goto failed_mii_init;
1997 /* Carrier starts down, phylib will bring it up */
1998 netif_carrier_off(ndev);
2000 ret = register_netdev(ndev);
2002 goto failed_register;
2004 if (fep->bufdesc_ex && fep->ptp_clock)
2005 netdev_info(ndev, "registered PHC device %d\n", fep->dev_id);
2007 INIT_DELAYED_WORK(&(fep->delay_work.delay_work), fec_enet_work);
2011 fec_enet_mii_remove(fep);
2014 for (i = 0; i < FEC_IRQ_NUM; i++) {
2015 irq = platform_get_irq(pdev, i);
2017 free_irq(irq, ndev);
2021 clk_disable_unprepare(fep->clk_ahb);
2022 clk_disable_unprepare(fep->clk_ipg);
2023 clk_disable_unprepare(fep->clk_enet_out);
2024 clk_disable_unprepare(fep->clk_ptp);
2034 fec_drv_remove(struct platform_device *pdev)
2036 struct net_device *ndev = platform_get_drvdata(pdev);
2037 struct fec_enet_private *fep = netdev_priv(ndev);
2040 cancel_delayed_work_sync(&(fep->delay_work.delay_work));
2041 unregister_netdev(ndev);
2042 fec_enet_mii_remove(fep);
2043 del_timer_sync(&fep->time_keep);
2044 clk_disable_unprepare(fep->clk_ptp);
2046 ptp_clock_unregister(fep->ptp_clock);
2047 clk_disable_unprepare(fep->clk_enet_out);
2048 clk_disable_unprepare(fep->clk_ahb);
2049 clk_disable_unprepare(fep->clk_ipg);
2050 for (i = 0; i < FEC_IRQ_NUM; i++) {
2051 int irq = platform_get_irq(pdev, i);
2053 free_irq(irq, ndev);
2057 platform_set_drvdata(pdev, NULL);
2062 #ifdef CONFIG_PM_SLEEP
2064 fec_suspend(struct device *dev)
2066 struct net_device *ndev = dev_get_drvdata(dev);
2067 struct fec_enet_private *fep = netdev_priv(ndev);
2069 if (netif_running(ndev)) {
2071 netif_device_detach(ndev);
2073 clk_disable_unprepare(fep->clk_enet_out);
2074 clk_disable_unprepare(fep->clk_ahb);
2075 clk_disable_unprepare(fep->clk_ipg);
2081 fec_resume(struct device *dev)
2083 struct net_device *ndev = dev_get_drvdata(dev);
2084 struct fec_enet_private *fep = netdev_priv(ndev);
2086 clk_prepare_enable(fep->clk_enet_out);
2087 clk_prepare_enable(fep->clk_ahb);
2088 clk_prepare_enable(fep->clk_ipg);
2089 if (netif_running(ndev)) {
2090 fec_restart(ndev, fep->full_duplex);
2091 netif_device_attach(ndev);
2096 #endif /* CONFIG_PM_SLEEP */
2098 static SIMPLE_DEV_PM_OPS(fec_pm_ops, fec_suspend, fec_resume);
2100 static struct platform_driver fec_driver = {
2102 .name = DRIVER_NAME,
2103 .owner = THIS_MODULE,
2105 .of_match_table = fec_dt_ids,
2107 .id_table = fec_devtype,
2109 .remove = fec_drv_remove,
2112 module_platform_driver(fec_driver);
2114 MODULE_LICENSE("GPL");