drivers/net/ethernet/freescale/gianfar.c

   1 /*
   2  * drivers/net/ethernet/freescale/gianfar.c
   3  *
   4  * Gianfar Ethernet Driver
   5  * This driver is designed for the non-CPM ethernet controllers
   6  * on the 85xx and 83xx family of integrated processors
   7  * Based on 8260_io/fcc_enet.c
   8  *
   9  * Author: Andy Fleming
  10  * Maintainer: Kumar Gala
  11  * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
  12  *
  13  * Copyright 2002-2009, 2011 Freescale Semiconductor, Inc.
  14  * Copyright 2007 MontaVista Software, Inc.
  15  *
  16  * This program is free software; you can redistribute  it and/or modify it
  17  * under  the terms of  the GNU General  Public License as published by the
  18  * Free Software Foundation;  either version 2 of the  License, or (at your
  19  * option) any later version.
  20  *
  21  *  Gianfar:  AKA Lambda Draconis, "Dragon"
  22  *  RA 11 31 24.2
  23  *  Dec +69 19 52
  24  *  V 3.84
  25  *  B-V +1.62
  26  *
  27  *  Theory of operation
  28  *
  29  *  The driver is initialized through of_device. Configuration information
  30  *  is therefore conveyed through an OF-style device tree.
  31  *
  32  *  The Gianfar Ethernet Controller uses a ring of buffer
  33  *  descriptors.  The beginning is indicated by a register
  34  *  pointing to the physical address of the start of the ring.
  35  *  The end is determined by a "wrap" bit being set in the
  36  *  last descriptor of the ring.
  37  *
  38  *  When a packet is received, the RXF bit in the
  39  *  IEVENT register is set, triggering an interrupt when the
  40  *  corresponding bit in the IMASK register is also set (if
  41  *  interrupt coalescing is active, then the interrupt may not
  42  *  happen immediately, but will wait until either a set number
  43  *  of frames or amount of time have passed).  In NAPI, the
  44  *  interrupt handler will signal there is work to be done, and
  45  *  exit. This method will start at the last known empty
  46  *  descriptor, and process every subsequent descriptor until there
  47  *  are none left with data (NAPI will stop after a set number of
  48  *  packets to give time to other tasks, but will eventually
  49  *  process all the packets).  The data arrives inside a
  50  *  pre-allocated skb, and so after the skb is passed up to the
  51  *  stack, a new skb must be allocated, and the address field in
  52  *  the buffer descriptor must be updated to indicate this new
  53  *  skb.
  54  *
  55  *  When the kernel requests that a packet be transmitted, the
  56  *  driver starts where it left off last time, and points the
  57  *  descriptor at the buffer which was passed in.  The driver
  58  *  then informs the DMA engine that there are packets ready to
  59  *  be transmitted.  Once the controller is finished transmitting
  60  *  the packet, an interrupt may be triggered (under the same
  61  *  conditions as for reception, but depending on the TXF bit).
  62  *  The driver then cleans up the buffer.
  63  */
  64
  65 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  66 #define DEBUG
  67
  68 #include <linux/kernel.h>
  69 #include <linux/string.h>
  70 #include <linux/errno.h>
  71 #include <linux/unistd.h>
  72 #include <linux/slab.h>
  73 #include <linux/interrupt.h>
  74 #include <linux/init.h>
  75 #include <linux/delay.h>
  76 #include <linux/netdevice.h>
  77 #include <linux/etherdevice.h>
  78 #include <linux/skbuff.h>
  79 #include <linux/if_vlan.h>
  80 #include <linux/spinlock.h>
  81 #include <linux/mm.h>
  82 #include <linux/of_mdio.h>
  83 #include <linux/of_platform.h>
  84 #include <linux/ip.h>
  85 #include <linux/tcp.h>
  86 #include <linux/udp.h>
  87 #include <linux/in.h>
  88 #include <linux/net_tstamp.h>
  89
  90 #include <asm/io.h>
  91 #include <asm/reg.h>
  92 #include <asm/irq.h>
  93 #include <asm/uaccess.h>
  94 #include <linux/module.h>
  95 #include <linux/dma-mapping.h>
  96 #include <linux/crc32.h>
  97 #include <linux/mii.h>
  98 #include <linux/phy.h>
  99 #include <linux/phy_fixed.h>
 100 #include <linux/of.h>
 101 #include <linux/of_net.h>
 102
 103 #include "gianfar.h"
 104 #include "fsl_pq_mdio.h"
 105
 106 #define TX_TIMEOUT      (1*HZ)
 107
 108 const char gfar_driver_version[] = "1.3";
 109
 110 static int gfar_enet_open(struct net_device *dev);
 111 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
 112 static void gfar_reset_task(struct work_struct *work);
 113 static void gfar_timeout(struct net_device *dev);
 114 static int gfar_close(struct net_device *dev);
 115 struct sk_buff *gfar_new_skb(struct net_device *dev);
 116 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
 117                 struct sk_buff *skb);
 118 static int gfar_set_mac_address(struct net_device *dev);
 119 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
 120 static irqreturn_t gfar_error(int irq, void *dev_id);
 121 static irqreturn_t gfar_transmit(int irq, void *dev_id);
 122 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
 123 static void adjust_link(struct net_device *dev);
 124 static void init_registers(struct net_device *dev);
 125 static int init_phy(struct net_device *dev);
 126 static int gfar_probe(struct platform_device *ofdev);
 127 static int gfar_remove(struct platform_device *ofdev);
 128 static void free_skb_resources(struct gfar_private *priv);
 129 static void gfar_set_multi(struct net_device *dev);
 130 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
 131 static void gfar_configure_serdes(struct net_device *dev);
 132 static int gfar_poll(struct napi_struct *napi, int budget);
 133 #ifdef CONFIG_NET_POLL_CONTROLLER
 134 static void gfar_netpoll(struct net_device *dev);
 135 #endif
 136 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit);
 137 static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue);
 138 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
 139                               int amount_pull, struct napi_struct *napi);
 140 void gfar_halt(struct net_device *dev);
 141 static void gfar_halt_nodisable(struct net_device *dev);
 142 void gfar_start(struct net_device *dev);
 143 static void gfar_clear_exact_match(struct net_device *dev);
 144 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
 145                                   const u8 *addr);
 146 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 147
 148 MODULE_AUTHOR("Freescale Semiconductor, Inc");
 149 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
 150 MODULE_LICENSE("GPL");
 151
 152 static void gfar_init_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
 153                             dma_addr_t buf)
 154 {
 155         u32 lstatus;
 156
 157         bdp->bufPtr = buf;
 158
 159         lstatus = BD_LFLAG(RXBD_EMPTY | RXBD_INTERRUPT);
 160         if (bdp == rx_queue->rx_bd_base + rx_queue->rx_ring_size - 1)
 161                 lstatus |= BD_LFLAG(RXBD_WRAP);
 162
 163         eieio();
 164
 165         bdp->lstatus = lstatus;
 166 }
 167
 168 static int gfar_init_bds(struct net_device *ndev)
 169 {
 170         struct gfar_private *priv = netdev_priv(ndev);
 171         struct gfar_priv_tx_q *tx_queue = NULL;
 172         struct gfar_priv_rx_q *rx_queue = NULL;
 173         struct txbd8 *txbdp;
 174         struct rxbd8 *rxbdp;
 175         int i, j;
 176
 177         for (i = 0; i < priv->num_tx_queues; i++) {
 178                 tx_queue = priv->tx_queue[i];
 179                 /* Initialize some variables in our dev structure */
 180                 tx_queue->num_txbdfree = tx_queue->tx_ring_size;
 181                 tx_queue->dirty_tx = tx_queue->tx_bd_base;
 182                 tx_queue->cur_tx = tx_queue->tx_bd_base;
 183                 tx_queue->skb_curtx = 0;
 184                 tx_queue->skb_dirtytx = 0;
 185
 186                 /* Initialize Transmit Descriptor Ring */
 187                 txbdp = tx_queue->tx_bd_base;
 188                 for (j = 0; j < tx_queue->tx_ring_size; j++) {
 189                         txbdp->lstatus = 0;
 190                         txbdp->bufPtr = 0;
 191                         txbdp++;
 192                 }
 193
 194                 /* Set the last descriptor in the ring to indicate wrap */
 195                 txbdp--;
 196                 txbdp->status |= TXBD_WRAP;
 197         }
 198
 199         for (i = 0; i < priv->num_rx_queues; i++) {
 200                 rx_queue = priv->rx_queue[i];
 201                 rx_queue->cur_rx = rx_queue->rx_bd_base;
 202                 rx_queue->skb_currx = 0;
 203                 rxbdp = rx_queue->rx_bd_base;
 204
 205                 for (j = 0; j < rx_queue->rx_ring_size; j++) {
 206                         struct sk_buff *skb = rx_queue->rx_skbuff[j];
 207
 208                         if (skb) {
 209                                 gfar_init_rxbdp(rx_queue, rxbdp,
 210                                                 rxbdp->bufPtr);
 211                         } else {
 212                                 skb = gfar_new_skb(ndev);
 213                                 if (!skb) {
 214                                         netdev_err(ndev, "Can't allocate RX buffers\n");
 215                                         goto err_rxalloc_fail;
 216                                 }
 217                                 rx_queue->rx_skbuff[j] = skb;
 218
 219                                 gfar_new_rxbdp(rx_queue, rxbdp, skb);
 220                         }
 221
 222                         rxbdp++;
 223                 }
 224
 225         }
 226
 227         return 0;
 228
 229 err_rxalloc_fail:
 230         free_skb_resources(priv);
 231         return -ENOMEM;
 232 }
 233
 234 static int gfar_alloc_skb_resources(struct net_device *ndev)
 235 {
 236         void *vaddr;
 237         dma_addr_t addr;
 238         int i, j, k;
 239         struct gfar_private *priv = netdev_priv(ndev);
 240         struct device *dev = &priv->ofdev->dev;
 241         struct gfar_priv_tx_q *tx_queue = NULL;
 242         struct gfar_priv_rx_q *rx_queue = NULL;
 243
 244         priv->total_tx_ring_size = 0;
 245         for (i = 0; i < priv->num_tx_queues; i++)
 246                 priv->total_tx_ring_size += priv->tx_queue[i]->tx_ring_size;
 247
 248         priv->total_rx_ring_size = 0;
 249         for (i = 0; i < priv->num_rx_queues; i++)
 250                 priv->total_rx_ring_size += priv->rx_queue[i]->rx_ring_size;
 251
 252         /* Allocate memory for the buffer descriptors */
 253         vaddr = dma_alloc_coherent(dev,
 254                         sizeof(struct txbd8) * priv->total_tx_ring_size +
 255                         sizeof(struct rxbd8) * priv->total_rx_ring_size,
 256                         &addr, GFP_KERNEL);
 257         if (!vaddr) {
 258                 netif_err(priv, ifup, ndev,
 259                           "Could not allocate buffer descriptors!\n");
 260                 return -ENOMEM;
 261         }
 262
 263         for (i = 0; i < priv->num_tx_queues; i++) {
 264                 tx_queue = priv->tx_queue[i];
 265                 tx_queue->tx_bd_base = vaddr;
 266                 tx_queue->tx_bd_dma_base = addr;
 267                 tx_queue->dev = ndev;
 268                 /* enet DMA only understands physical addresses */
 269                 addr    += sizeof(struct txbd8) *tx_queue->tx_ring_size;
 270                 vaddr   += sizeof(struct txbd8) *tx_queue->tx_ring_size;
 271         }
 272
 273         /* Start the rx descriptor ring where the tx ring leaves off */
 274         for (i = 0; i < priv->num_rx_queues; i++) {
 275                 rx_queue = priv->rx_queue[i];
 276                 rx_queue->rx_bd_base = vaddr;
 277                 rx_queue->rx_bd_dma_base = addr;
 278                 rx_queue->dev = ndev;
 279                 addr    += sizeof (struct rxbd8) * rx_queue->rx_ring_size;
 280                 vaddr   += sizeof (struct rxbd8) * rx_queue->rx_ring_size;
 281         }
 282
 283         /* Setup the skbuff rings */
 284         for (i = 0; i < priv->num_tx_queues; i++) {
 285                 tx_queue = priv->tx_queue[i];
 286                 tx_queue->tx_skbuff = kmalloc(sizeof(*tx_queue->tx_skbuff) *
 287                                   tx_queue->tx_ring_size, GFP_KERNEL);
 288                 if (!tx_queue->tx_skbuff) {
 289                         netif_err(priv, ifup, ndev,
 290                                   "Could not allocate tx_skbuff\n");
 291                         goto cleanup;
 292                 }
 293
 294                 for (k = 0; k < tx_queue->tx_ring_size; k++)
 295                         tx_queue->tx_skbuff[k] = NULL;
 296         }
 297
 298         for (i = 0; i < priv->num_rx_queues; i++) {
 299                 rx_queue = priv->rx_queue[i];
 300                 rx_queue->rx_skbuff = kmalloc(sizeof(*rx_queue->rx_skbuff) *
 301                                   rx_queue->rx_ring_size, GFP_KERNEL);
 302
 303                 if (!rx_queue->rx_skbuff) {
 304                         netif_err(priv, ifup, ndev,
 305                                   "Could not allocate rx_skbuff\n");
 306                         goto cleanup;
 307                 }
 308
 309                 for (j = 0; j < rx_queue->rx_ring_size; j++)
 310                         rx_queue->rx_skbuff[j] = NULL;
 311         }
 312
 313         if (gfar_init_bds(ndev))
 314                 goto cleanup;
 315
 316         return 0;
 317
 318 cleanup:
 319         free_skb_resources(priv);
 320         return -ENOMEM;
 321 }
 322
 323 static void gfar_init_tx_rx_base(struct gfar_private *priv)
 324 {
 325         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 326         u32 __iomem *baddr;
 327         int i;
 328
 329         baddr = &regs->tbase0;
 330         for(i = 0; i < priv->num_tx_queues; i++) {
 331                 gfar_write(baddr, priv->tx_queue[i]->tx_bd_dma_base);
 332                 baddr   += 2;
 333         }
 334
 335         baddr = &regs->rbase0;
 336         for(i = 0; i < priv->num_rx_queues; i++) {
 337                 gfar_write(baddr, priv->rx_queue[i]->rx_bd_dma_base);
 338                 baddr   += 2;
 339         }
 340 }
 341
 342 static void gfar_init_mac(struct net_device *ndev)
 343 {
 344         struct gfar_private *priv = netdev_priv(ndev);
 345         struct gfar __iomem *regs = priv->gfargrp[0].regs;
 346         u32 rctrl = 0;
 347         u32 tctrl = 0;
 348         u32 attrs = 0;
 349
 350         /* write the tx/rx base registers */
 351         gfar_init_tx_rx_base(priv);
 352
 353         /* Configure the coalescing support */
 354         gfar_configure_coalescing(priv, 0xFF, 0xFF);
 355
 356         if (priv->rx_filer_enable) {
 357                 rctrl |= RCTRL_FILREN;
 358                 /* Program the RIR0 reg with the required distribution */
 359                 gfar_write(&regs->rir0, DEFAULT_RIR0);
 360         }
 361
 362         if (ndev->features & NETIF_F_RXCSUM)
 363                 rctrl |= RCTRL_CHECKSUMMING;
 364
 365         if (priv->extended_hash) {
 366                 rctrl |= RCTRL_EXTHASH;
 367
 368                 gfar_clear_exact_match(ndev);
 369                 rctrl |= RCTRL_EMEN;
 370         }
 371
 372         if (priv->padding) {
 373                 rctrl &= ~RCTRL_PAL_MASK;
 374                 rctrl |= RCTRL_PADDING(priv->padding);
 375         }
 376
 377         /* Insert receive time stamps into padding alignment bytes */
 378         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER) {
 379                 rctrl &= ~RCTRL_PAL_MASK;
 380                 rctrl |= RCTRL_PADDING(8);
 381                 priv->padding = 8;
 382         }
 383
 384         /* Enable HW time stamping if requested from user space */
 385         if (priv->hwts_rx_en)
 386                 rctrl |= RCTRL_PRSDEP_INIT | RCTRL_TS_ENABLE;
 387
 388         if (ndev->features & NETIF_F_HW_VLAN_RX)
 389                 rctrl |= RCTRL_VLEX | RCTRL_PRSDEP_INIT;
 390
 391         /* Init rctrl based on our settings */
 392         gfar_write(&regs->rctrl, rctrl);
 393
 394         if (ndev->features & NETIF_F_IP_CSUM)
 395                 tctrl |= TCTRL_INIT_CSUM;
 396
 397         tctrl |= TCTRL_TXSCHED_PRIO;
 398
 399         gfar_write(&regs->tctrl, tctrl);
 400
 401         /* Set the extraction length and index */
 402         attrs = ATTRELI_EL(priv->rx_stash_size) |
 403                 ATTRELI_EI(priv->rx_stash_index);
 404
 405         gfar_write(&regs->attreli, attrs);
 406
 407         /* Start with defaults, and add stashing or locking
 408          * depending on the approprate variables */
 409         attrs = ATTR_INIT_SETTINGS;
 410
 411         if (priv->bd_stash_en)
 412                 attrs |= ATTR_BDSTASH;
 413
 414         if (priv->rx_stash_size != 0)
 415                 attrs |= ATTR_BUFSTASH;
 416
 417         gfar_write(&regs->attr, attrs);
 418
 419         gfar_write(&regs->fifo_tx_thr, priv->fifo_threshold);
 420         gfar_write(&regs->fifo_tx_starve, priv->fifo_starve);
 421         gfar_write(&regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
 422 }
 423
 424 static struct net_device_stats *gfar_get_stats(struct net_device *dev)
 425 {
 426         struct gfar_private *priv = netdev_priv(dev);
 427         unsigned long rx_packets = 0, rx_bytes = 0, rx_dropped = 0;
 428         unsigned long tx_packets = 0, tx_bytes = 0;
 429         int i = 0;
 430
 431         for (i = 0; i < priv->num_rx_queues; i++) {
 432                 rx_packets += priv->rx_queue[i]->stats.rx_packets;
 433                 rx_bytes += priv->rx_queue[i]->stats.rx_bytes;
 434                 rx_dropped += priv->rx_queue[i]->stats.rx_dropped;
 435         }
 436
 437         dev->stats.rx_packets = rx_packets;
 438         dev->stats.rx_bytes = rx_bytes;
 439         dev->stats.rx_dropped = rx_dropped;
 440
 441         for (i = 0; i < priv->num_tx_queues; i++) {
 442                 tx_bytes += priv->tx_queue[i]->stats.tx_bytes;
 443                 tx_packets += priv->tx_queue[i]->stats.tx_packets;
 444         }
 445
 446         dev->stats.tx_bytes = tx_bytes;
 447         dev->stats.tx_packets = tx_packets;
 448
 449         return &dev->stats;
 450 }
 451
 452 static const struct net_device_ops gfar_netdev_ops = {
 453         .ndo_open = gfar_enet_open,
 454         .ndo_start_xmit = gfar_start_xmit,
 455         .ndo_stop = gfar_close,
 456         .ndo_change_mtu = gfar_change_mtu,
 457         .ndo_set_features = gfar_set_features,
 458         .ndo_set_rx_mode = gfar_set_multi,
 459         .ndo_tx_timeout = gfar_timeout,
 460         .ndo_do_ioctl = gfar_ioctl,
 461         .ndo_get_stats = gfar_get_stats,
 462         .ndo_set_mac_address = eth_mac_addr,
 463         .ndo_validate_addr = eth_validate_addr,
 464 #ifdef CONFIG_NET_POLL_CONTROLLER
 465         .ndo_poll_controller = gfar_netpoll,
 466 #endif
 467 };
 468
 469 void lock_rx_qs(struct gfar_private *priv)
 470 {
 471         int i = 0x0;
 472
 473         for (i = 0; i < priv->num_rx_queues; i++)
 474                 spin_lock(&priv->rx_queue[i]->rxlock);
 475 }
 476
 477 void lock_tx_qs(struct gfar_private *priv)
 478 {
 479         int i = 0x0;
 480
 481         for (i = 0; i < priv->num_tx_queues; i++)
 482                 spin_lock(&priv->tx_queue[i]->txlock);
 483 }
 484
 485 void unlock_rx_qs(struct gfar_private *priv)
 486 {
 487         int i = 0x0;
 488
 489         for (i = 0; i < priv->num_rx_queues; i++)
 490                 spin_unlock(&priv->rx_queue[i]->rxlock);
 491 }
 492
 493 void unlock_tx_qs(struct gfar_private *priv)
 494 {
 495         int i = 0x0;
 496
 497         for (i = 0; i < priv->num_tx_queues; i++)
 498                 spin_unlock(&priv->tx_queue[i]->txlock);
 499 }
 500
 501 static bool gfar_is_vlan_on(struct gfar_private *priv)
 502 {
 503         return (priv->ndev->features & NETIF_F_HW_VLAN_RX) ||
 504                (priv->ndev->features & NETIF_F_HW_VLAN_TX);
 505 }
 506
 507 /* Returns 1 if incoming frames use an FCB */
 508 static inline int gfar_uses_fcb(struct gfar_private *priv)
 509 {
 510         return gfar_is_vlan_on(priv) ||
 511                 (priv->ndev->features & NETIF_F_RXCSUM) ||
 512                 (priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER);
 513 }
 514
 515 static void free_tx_pointers(struct gfar_private *priv)
 516 {
 517         int i = 0;
 518
 519         for (i = 0; i < priv->num_tx_queues; i++)
 520                 kfree(priv->tx_queue[i]);
 521 }
 522
 523 static void free_rx_pointers(struct gfar_private *priv)
 524 {
 525         int i = 0;
 526
 527         for (i = 0; i < priv->num_rx_queues; i++)
 528                 kfree(priv->rx_queue[i]);
 529 }
 530
 531 static void unmap_group_regs(struct gfar_private *priv)
 532 {
 533         int i = 0;
 534
 535         for (i = 0; i < MAXGROUPS; i++)
 536                 if (priv->gfargrp[i].regs)
 537                         iounmap(priv->gfargrp[i].regs);
 538 }
 539
 540 static void disable_napi(struct gfar_private *priv)
 541 {
 542         int i = 0;
 543
 544         for (i = 0; i < priv->num_grps; i++)
 545                 napi_disable(&priv->gfargrp[i].napi);
 546 }
 547
 548 static void enable_napi(struct gfar_private *priv)
 549 {
 550         int i = 0;
 551
 552         for (i = 0; i < priv->num_grps; i++)
 553                 napi_enable(&priv->gfargrp[i].napi);
 554 }
 555
 556 static int gfar_parse_group(struct device_node *np,
 557                 struct gfar_private *priv, const char *model)
 558 {
 559         u32 *queue_mask;
 560
 561         priv->gfargrp[priv->num_grps].regs = of_iomap(np, 0);
 562         if (!priv->gfargrp[priv->num_grps].regs)
 563                 return -ENOMEM;
 564
 565         priv->gfargrp[priv->num_grps].interruptTransmit =
 566                         irq_of_parse_and_map(np, 0);
 567
 568         /* If we aren't the FEC we have multiple interrupts */
 569         if (model && strcasecmp(model, "FEC")) {
 570                 priv->gfargrp[priv->num_grps].interruptReceive =
 571                         irq_of_parse_and_map(np, 1);
 572                 priv->gfargrp[priv->num_grps].interruptError =
 573                         irq_of_parse_and_map(np,2);
 574                 if (priv->gfargrp[priv->num_grps].interruptTransmit == NO_IRQ ||
 575                     priv->gfargrp[priv->num_grps].interruptReceive  == NO_IRQ ||
 576                     priv->gfargrp[priv->num_grps].interruptError    == NO_IRQ)
 577                         return -EINVAL;
 578         }
 579
 580         priv->gfargrp[priv->num_grps].grp_id = priv->num_grps;
 581         priv->gfargrp[priv->num_grps].priv = priv;
 582         spin_lock_init(&priv->gfargrp[priv->num_grps].grplock);
 583         if(priv->mode == MQ_MG_MODE) {
 584                 queue_mask = (u32 *)of_get_property(np,
 585                                         "fsl,rx-bit-map", NULL);
 586                 priv->gfargrp[priv->num_grps].rx_bit_map =
 587                         queue_mask ?  *queue_mask :(DEFAULT_MAPPING >> priv->num_grps);
 588                 queue_mask = (u32 *)of_get_property(np,
 589                                         "fsl,tx-bit-map", NULL);
 590                 priv->gfargrp[priv->num_grps].tx_bit_map =
 591                         queue_mask ? *queue_mask : (DEFAULT_MAPPING >> priv->num_grps);
 592         } else {
 593                 priv->gfargrp[priv->num_grps].rx_bit_map = 0xFF;
 594                 priv->gfargrp[priv->num_grps].tx_bit_map = 0xFF;
 595         }
 596         priv->num_grps++;
 597
 598         return 0;
 599 }
 600
 601 static int gfar_of_init(struct platform_device *ofdev, struct net_device **pdev)
 602 {
 603         const char *model;
 604         const char *ctype;
 605         const void *mac_addr;
 606         int err = 0, i;
 607         struct net_device *dev = NULL;
 608         struct gfar_private *priv = NULL;
 609         struct device_node *np = ofdev->dev.of_node;
 610         struct device_node *child = NULL;
 611         const u32 *stash;
 612         const u32 *stash_len;
 613         const u32 *stash_idx;
 614         unsigned int num_tx_qs, num_rx_qs;
 615         u32 *tx_queues, *rx_queues;
 616
 617         if (!np || !of_device_is_available(np))
 618                 return -ENODEV;
 619
 620         /* parse the num of tx and rx queues */
 621         tx_queues = (u32 *)of_get_property(np, "fsl,num_tx_queues", NULL);
 622         num_tx_qs = tx_queues ? *tx_queues : 1;
 623
 624         if (num_tx_qs > MAX_TX_QS) {
 625                 pr_err("num_tx_qs(=%d) greater than MAX_TX_QS(=%d)\n",
 626                        num_tx_qs, MAX_TX_QS);
 627                 pr_err("Cannot do alloc_etherdev, aborting\n");
 628                 return -EINVAL;
 629         }
 630
 631         rx_queues = (u32 *)of_get_property(np, "fsl,num_rx_queues", NULL);
 632         num_rx_qs = rx_queues ? *rx_queues : 1;
 633
 634         if (num_rx_qs > MAX_RX_QS) {
 635                 pr_err("num_rx_qs(=%d) greater than MAX_RX_QS(=%d)\n",
 636                        num_rx_qs, MAX_RX_QS);
 637                 pr_err("Cannot do alloc_etherdev, aborting\n");
 638                 return -EINVAL;
 639         }
 640
 641         *pdev = alloc_etherdev_mq(sizeof(*priv), num_tx_qs);
 642         dev = *pdev;
 643         if (NULL == dev)
 644                 return -ENOMEM;
 645
 646         priv = netdev_priv(dev);
 647         priv->node = ofdev->dev.of_node;
 648         priv->ndev = dev;
 649
 650         priv->num_tx_queues = num_tx_qs;
 651         netif_set_real_num_rx_queues(dev, num_rx_qs);
 652         priv->num_rx_queues = num_rx_qs;
 653         priv->num_grps = 0x0;
 654
 655         /* Init Rx queue filer rule set linked list*/
 656         INIT_LIST_HEAD(&priv->rx_list.list);
 657         priv->rx_list.count = 0;
 658         mutex_init(&priv->rx_queue_access);
 659
 660         model = of_get_property(np, "model", NULL);
 661
 662         for (i = 0; i < MAXGROUPS; i++)
 663                 priv->gfargrp[i].regs = NULL;
 664
 665         /* Parse and initialize group specific information */
 666         if (of_device_is_compatible(np, "fsl,etsec2")) {
 667                 priv->mode = MQ_MG_MODE;
 668                 for_each_child_of_node(np, child) {
 669                         err = gfar_parse_group(child, priv, model);
 670                         if (err)
 671                                 goto err_grp_init;
 672                 }
 673         } else {
 674                 priv->mode = SQ_SG_MODE;
 675                 err = gfar_parse_group(np, priv, model);
 676                 if(err)
 677                         goto err_grp_init;
 678         }
 679
 680         for (i = 0; i < priv->num_tx_queues; i++)
 681                priv->tx_queue[i] = NULL;
 682         for (i = 0; i < priv->num_rx_queues; i++)
 683                 priv->rx_queue[i] = NULL;
 684
 685         for (i = 0; i < priv->num_tx_queues; i++) {
 686                 priv->tx_queue[i] = kzalloc(sizeof(struct gfar_priv_tx_q),
 687                                             GFP_KERNEL);
 688                 if (!priv->tx_queue[i]) {
 689                         err = -ENOMEM;
 690                         goto tx_alloc_failed;
 691                 }
 692                 priv->tx_queue[i]->tx_skbuff = NULL;
 693                 priv->tx_queue[i]->qindex = i;
 694                 priv->tx_queue[i]->dev = dev;
 695                 spin_lock_init(&(priv->tx_queue[i]->txlock));
 696         }
 697
 698         for (i = 0; i < priv->num_rx_queues; i++) {
 699                 priv->rx_queue[i] = kzalloc(sizeof(struct gfar_priv_rx_q),
 700                                             GFP_KERNEL);
 701                 if (!priv->rx_queue[i]) {
 702                         err = -ENOMEM;
 703                         goto rx_alloc_failed;
 704                 }
 705                 priv->rx_queue[i]->rx_skbuff = NULL;
 706                 priv->rx_queue[i]->qindex = i;
 707                 priv->rx_queue[i]->dev = dev;
 708                 spin_lock_init(&(priv->rx_queue[i]->rxlock));
 709         }
 710
 711
 712         stash = of_get_property(np, "bd-stash", NULL);
 713
 714         if (stash) {
 715                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BD_STASHING;
 716                 priv->bd_stash_en = 1;
 717         }
 718
 719         stash_len = of_get_property(np, "rx-stash-len", NULL);
 720
 721         if (stash_len)
 722                 priv->rx_stash_size = *stash_len;
 723
 724         stash_idx = of_get_property(np, "rx-stash-idx", NULL);
 725
 726         if (stash_idx)
 727                 priv->rx_stash_index = *stash_idx;
 728
 729         if (stash_len || stash_idx)
 730                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_BUF_STASHING;
 731
 732         mac_addr = of_get_mac_address(np);
 733         if (mac_addr)
 734                 memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
 735
 736         if (model && !strcasecmp(model, "TSEC"))
 737                 priv->device_flags =
 738                         FSL_GIANFAR_DEV_HAS_GIGABIT |
 739                         FSL_GIANFAR_DEV_HAS_COALESCE |
 740                         FSL_GIANFAR_DEV_HAS_RMON |
 741                         FSL_GIANFAR_DEV_HAS_MULTI_INTR;
 742         if (model && !strcasecmp(model, "eTSEC"))
 743                 priv->device_flags =
 744                         FSL_GIANFAR_DEV_HAS_GIGABIT |
 745                         FSL_GIANFAR_DEV_HAS_COALESCE |
 746                         FSL_GIANFAR_DEV_HAS_RMON |
 747                         FSL_GIANFAR_DEV_HAS_MULTI_INTR |
 748                         FSL_GIANFAR_DEV_HAS_PADDING |
 749                         FSL_GIANFAR_DEV_HAS_CSUM |
 750                         FSL_GIANFAR_DEV_HAS_VLAN |
 751                         FSL_GIANFAR_DEV_HAS_MAGIC_PACKET |
 752                         FSL_GIANFAR_DEV_HAS_EXTENDED_HASH |
 753                         FSL_GIANFAR_DEV_HAS_TIMER;
 754
 755         ctype = of_get_property(np, "phy-connection-type", NULL);
 756
 757         /* We only care about rgmii-id.  The rest are autodetected */
 758         if (ctype && !strcmp(ctype, "rgmii-id"))
 759                 priv->interface = PHY_INTERFACE_MODE_RGMII_ID;
 760         else
 761                 priv->interface = PHY_INTERFACE_MODE_MII;
 762
 763         if (of_get_property(np, "fsl,magic-packet", NULL))
 764                 priv->device_flags |= FSL_GIANFAR_DEV_HAS_MAGIC_PACKET;
 765
 766         priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
 767
 768         /* Find the TBI PHY.  If it's not there, we don't support SGMII */
 769         priv->tbi_node = of_parse_phandle(np, "tbi-handle", 0);
 770
 771         return 0;
 772
 773 rx_alloc_failed:
 774         free_rx_pointers(priv);
 775 tx_alloc_failed:
 776         free_tx_pointers(priv);
 777 err_grp_init:
 778         unmap_group_regs(priv);
 779         free_netdev(dev);
 780         return err;
 781 }
 782
 783 static int gfar_hwtstamp_ioctl(struct net_device *netdev,
 784                         struct ifreq *ifr, int cmd)
 785 {
 786         struct hwtstamp_config config;
 787         struct gfar_private *priv = netdev_priv(netdev);
 788
 789         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
 790                 return -EFAULT;
 791
 792         /* reserved for future extensions */
 793         if (config.flags)
 794                 return -EINVAL;
 795
 796         switch (config.tx_type) {
 797         case HWTSTAMP_TX_OFF:
 798                 priv->hwts_tx_en = 0;
 799                 break;
 800         case HWTSTAMP_TX_ON:
 801                 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
 802                         return -ERANGE;
 803                 priv->hwts_tx_en = 1;
 804                 break;
 805         default:
 806                 return -ERANGE;
 807         }
 808
 809         switch (config.rx_filter) {
 810         case HWTSTAMP_FILTER_NONE:
 811                 if (priv->hwts_rx_en) {
 812                         stop_gfar(netdev);
 813                         priv->hwts_rx_en = 0;
 814                         startup_gfar(netdev);
 815                 }
 816                 break;
 817         default:
 818                 if (!(priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER))
 819                         return -ERANGE;
 820                 if (!priv->hwts_rx_en) {
 821                         stop_gfar(netdev);
 822                         priv->hwts_rx_en = 1;
 823                         startup_gfar(netdev);
 824                 }
 825                 config.rx_filter = HWTSTAMP_FILTER_ALL;
 826                 break;
 827         }
 828
 829         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
 830                 -EFAULT : 0;
 831 }
 832
 833 /* Ioctl MII Interface */
 834 static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 835 {
 836         struct gfar_private *priv = netdev_priv(dev);
 837
 838         if (!netif_running(dev))
 839                 return -EINVAL;
 840
 841         if (cmd == SIOCSHWTSTAMP)
 842                 return gfar_hwtstamp_ioctl(dev, rq, cmd);
 843
 844         if (!priv->phydev)
 845                 return -ENODEV;
 846
 847         return phy_mii_ioctl(priv->phydev, rq, cmd);
 848 }
 849
 850 static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs)
 851 {
 852         unsigned int new_bit_map = 0x0;
 853         int mask = 0x1 << (max_qs - 1), i;
 854         for (i = 0; i < max_qs; i++) {
 855                 if (bit_map & mask)
 856                         new_bit_map = new_bit_map + (1 << i);
 857                 mask = mask >> 0x1;
 858         }
 859         return new_bit_map;
 860 }
 861
 862 static u32 cluster_entry_per_class(struct gfar_private *priv, u32 rqfar,
 863                                    u32 class)
 864 {
 865         u32 rqfpr = FPR_FILER_MASK;
 866         u32 rqfcr = 0x0;
 867
 868         rqfar--;
 869         rqfcr = RQFCR_CLE | RQFCR_PID_MASK | RQFCR_CMP_EXACT;
 870         priv->ftp_rqfpr[rqfar] = rqfpr;
 871         priv->ftp_rqfcr[rqfar] = rqfcr;
 872         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 873
 874         rqfar--;
 875         rqfcr = RQFCR_CMP_NOMATCH;
 876         priv->ftp_rqfpr[rqfar] = rqfpr;
 877         priv->ftp_rqfcr[rqfar] = rqfcr;
 878         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 879
 880         rqfar--;
 881         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_PARSE | RQFCR_CLE | RQFCR_AND;
 882         rqfpr = class;
 883         priv->ftp_rqfcr[rqfar] = rqfcr;
 884         priv->ftp_rqfpr[rqfar] = rqfpr;
 885         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 886
 887         rqfar--;
 888         rqfcr = RQFCR_CMP_EXACT | RQFCR_PID_MASK | RQFCR_AND;
 889         rqfpr = class;
 890         priv->ftp_rqfcr[rqfar] = rqfcr;
 891         priv->ftp_rqfpr[rqfar] = rqfpr;
 892         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 893
 894         return rqfar;
 895 }
 896
 897 static void gfar_init_filer_table(struct gfar_private *priv)
 898 {
 899         int i = 0x0;
 900         u32 rqfar = MAX_FILER_IDX;
 901         u32 rqfcr = 0x0;
 902         u32 rqfpr = FPR_FILER_MASK;
 903
 904         /* Default rule */
 905         rqfcr = RQFCR_CMP_MATCH;
 906         priv->ftp_rqfcr[rqfar] = rqfcr;
 907         priv->ftp_rqfpr[rqfar] = rqfpr;
 908         gfar_write_filer(priv, rqfar, rqfcr, rqfpr);
 909
 910         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6);
 911         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_UDP);
 912         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV6 | RQFPR_TCP);
 913         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4);
 914         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_UDP);
 915         rqfar = cluster_entry_per_class(priv, rqfar, RQFPR_IPV4 | RQFPR_TCP);
 916
 917         /* cur_filer_idx indicated the first non-masked rule */
 918         priv->cur_filer_idx = rqfar;
 919
 920         /* Rest are masked rules */
 921         rqfcr = RQFCR_CMP_NOMATCH;
 922         for (i = 0; i < rqfar; i++) {
 923                 priv->ftp_rqfcr[i] = rqfcr;
 924                 priv->ftp_rqfpr[i] = rqfpr;
 925                 gfar_write_filer(priv, i, rqfcr, rqfpr);
 926         }
 927 }
 928
 929 static void gfar_detect_errata(struct gfar_private *priv)
 930 {
 931         struct device *dev = &priv->ofdev->dev;
 932         unsigned int pvr = mfspr(SPRN_PVR);
 933         unsigned int svr = mfspr(SPRN_SVR);
 934         unsigned int mod = (svr >> 16) & 0xfff6; /* w/o E suffix */
 935         unsigned int rev = svr & 0xffff;
 936
 937         /* MPC8313 Rev 2.0 and higher; All MPC837x */
 938         if ((pvr == 0x80850010 && mod == 0x80b0 && rev >= 0x0020) ||
 939                         (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
 940                 priv->errata |= GFAR_ERRATA_74;
 941
 942         /* MPC8313 and MPC837x all rev */
 943         if ((pvr == 0x80850010 && mod == 0x80b0) ||
 944                         (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
 945                 priv->errata |= GFAR_ERRATA_76;
 946
 947         /* MPC8313 and MPC837x all rev */
 948         if ((pvr == 0x80850010 && mod == 0x80b0) ||
 949                         (pvr == 0x80861010 && (mod & 0xfff9) == 0x80c0))
 950                 priv->errata |= GFAR_ERRATA_A002;
 951
 952         /* MPC8313 Rev < 2.0, MPC8548 rev 2.0 */
 953         if ((pvr == 0x80850010 && mod == 0x80b0 && rev < 0x0020) ||
 954                         (pvr == 0x80210020 && mod == 0x8030 && rev == 0x0020))
 955                 priv->errata |= GFAR_ERRATA_12;
 956
 957         if (priv->errata)
 958                 dev_info(dev, "enabled errata workarounds, flags: 0x%x\n",
 959                          priv->errata);
 960 }
 961
 962 /* Set up the ethernet device structure, private data,
 963  * and anything else we need before we start */
 964 static int gfar_probe(struct platform_device *ofdev)
 965 {
 966         u32 tempval;
 967         struct net_device *dev = NULL;
 968         struct gfar_private *priv = NULL;
 969         struct gfar __iomem *regs = NULL;
 970         int err = 0, i, grp_idx = 0;
 971         u32 rstat = 0, tstat = 0, rqueue = 0, tqueue = 0;
 972         u32 isrg = 0;
 973         u32 __iomem *baddr;
 974
 975         err = gfar_of_init(ofdev, &dev);
 976
 977         if (err)
 978                 return err;
 979
 980         priv = netdev_priv(dev);
 981         priv->ndev = dev;
 982         priv->ofdev = ofdev;
 983         priv->node = ofdev->dev.of_node;
 984         SET_NETDEV_DEV(dev, &ofdev->dev);
 985
 986         spin_lock_init(&priv->bflock);
 987         INIT_WORK(&priv->reset_task, gfar_reset_task);
 988
 989         dev_set_drvdata(&ofdev->dev, priv);
 990         regs = priv->gfargrp[0].regs;
 991
 992         gfar_detect_errata(priv);
 993
 994         /* Stop the DMA engine now, in case it was running before */
 995         /* (The firmware could have used it, and left it running). */
 996         gfar_halt(dev);
 997
 998         /* Reset MAC layer */
 999         gfar_write(&regs->maccfg1, MACCFG1_SOFT_RESET);
1000
1001         /* We need to delay at least 3 TX clocks */
1002         udelay(2);
1003
1004         tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
1005         gfar_write(&regs->maccfg1, tempval);
1006
1007         /* Initialize MACCFG2. */
1008         tempval = MACCFG2_INIT_SETTINGS;
1009         if (gfar_has_errata(priv, GFAR_ERRATA_74))
1010                 tempval |= MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK;
1011         gfar_write(&regs->maccfg2, tempval);
1012
1013         /* Initialize ECNTRL */
1014         gfar_write(&regs->ecntrl, ECNTRL_INIT_SETTINGS);
1015
1016         /* Set the dev->base_addr to the gfar reg region */
1017         dev->base_addr = (unsigned long) regs;
1018
1019         SET_NETDEV_DEV(dev, &ofdev->dev);
1020
1021         /* Fill in the dev structure */
1022         dev->watchdog_timeo = TX_TIMEOUT;
1023         dev->mtu = 1500;
1024         dev->netdev_ops = &gfar_netdev_ops;
1025         dev->ethtool_ops = &gfar_ethtool_ops;
1026
1027         /* Register for napi ...We are registering NAPI for each grp */
1028         for (i = 0; i < priv->num_grps; i++)
1029                 netif_napi_add(dev, &priv->gfargrp[i].napi, gfar_poll, GFAR_DEV_WEIGHT);
1030
1031         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
1032                 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
1033                         NETIF_F_RXCSUM;
1034                 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG |
1035                         NETIF_F_RXCSUM | NETIF_F_HIGHDMA;
1036         }
1037
1038         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
1039                 dev->hw_features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1040                 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1041         }
1042
1043         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
1044                 priv->extended_hash = 1;
1045                 priv->hash_width = 9;
1046
1047                 priv->hash_regs[0] = &regs->igaddr0;
1048                 priv->hash_regs[1] = &regs->igaddr1;
1049                 priv->hash_regs[2] = &regs->igaddr2;
1050                 priv->hash_regs[3] = &regs->igaddr3;
1051                 priv->hash_regs[4] = &regs->igaddr4;
1052                 priv->hash_regs[5] = &regs->igaddr5;
1053                 priv->hash_regs[6] = &regs->igaddr6;
1054                 priv->hash_regs[7] = &regs->igaddr7;
1055                 priv->hash_regs[8] = &regs->gaddr0;
1056                 priv->hash_regs[9] = &regs->gaddr1;
1057                 priv->hash_regs[10] = &regs->gaddr2;
1058                 priv->hash_regs[11] = &regs->gaddr3;
1059                 priv->hash_regs[12] = &regs->gaddr4;
1060                 priv->hash_regs[13] = &regs->gaddr5;
1061                 priv->hash_regs[14] = &regs->gaddr6;
1062                 priv->hash_regs[15] = &regs->gaddr7;
1063
1064         } else {
1065                 priv->extended_hash = 0;
1066                 priv->hash_width = 8;
1067
1068                 priv->hash_regs[0] = &regs->gaddr0;
1069                 priv->hash_regs[1] = &regs->gaddr1;
1070                 priv->hash_regs[2] = &regs->gaddr2;
1071                 priv->hash_regs[3] = &regs->gaddr3;
1072                 priv->hash_regs[4] = &regs->gaddr4;
1073                 priv->hash_regs[5] = &regs->gaddr5;
1074                 priv->hash_regs[6] = &regs->gaddr6;
1075                 priv->hash_regs[7] = &regs->gaddr7;
1076         }
1077
1078         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
1079                 priv->padding = DEFAULT_PADDING;
1080         else
1081                 priv->padding = 0;
1082
1083         if (dev->features & NETIF_F_IP_CSUM ||
1084                         priv->device_flags & FSL_GIANFAR_DEV_HAS_TIMER)
1085                 dev->needed_headroom = GMAC_FCB_LEN;
1086
1087         /* Program the isrg regs only if number of grps > 1 */
1088         if (priv->num_grps > 1) {
1089                 baddr = &regs->isrg0;
1090                 for (i = 0; i < priv->num_grps; i++) {
1091                         isrg |= (priv->gfargrp[i].rx_bit_map << ISRG_SHIFT_RX);
1092                         isrg |= (priv->gfargrp[i].tx_bit_map << ISRG_SHIFT_TX);
1093                         gfar_write(baddr, isrg);
1094                         baddr++;
1095                         isrg = 0x0;
1096                 }
1097         }
1098
1099         /* Need to reverse the bit maps as  bit_map's MSB is q0
1100          * but, for_each_set_bit parses from right to left, which
1101          * basically reverses the queue numbers */
1102         for (i = 0; i< priv->num_grps; i++) {
1103                 priv->gfargrp[i].tx_bit_map = reverse_bitmap(
1104                                 priv->gfargrp[i].tx_bit_map, MAX_TX_QS);
1105                 priv->gfargrp[i].rx_bit_map = reverse_bitmap(
1106                                 priv->gfargrp[i].rx_bit_map, MAX_RX_QS);
1107         }
1108
1109         /* Calculate RSTAT, TSTAT, RQUEUE and TQUEUE values,
1110          * also assign queues to groups */
1111         for (grp_idx = 0; grp_idx < priv->num_grps; grp_idx++) {
1112                 priv->gfargrp[grp_idx].num_rx_queues = 0x0;
1113                 for_each_set_bit(i, &priv->gfargrp[grp_idx].rx_bit_map,
1114                                 priv->num_rx_queues) {
1115                         priv->gfargrp[grp_idx].num_rx_queues++;
1116                         priv->rx_queue[i]->grp = &priv->gfargrp[grp_idx];
1117                         rstat = rstat | (RSTAT_CLEAR_RHALT >> i);
1118                         rqueue = rqueue | ((RQUEUE_EN0 | RQUEUE_EX0) >> i);
1119                 }
1120                 priv->gfargrp[grp_idx].num_tx_queues = 0x0;
1121                 for_each_set_bit(i, &priv->gfargrp[grp_idx].tx_bit_map,
1122                                 priv->num_tx_queues) {
1123                         priv->gfargrp[grp_idx].num_tx_queues++;
1124                         priv->tx_queue[i]->grp = &priv->gfargrp[grp_idx];
1125                         tstat = tstat | (TSTAT_CLEAR_THALT >> i);
1126                         tqueue = tqueue | (TQUEUE_EN0 >> i);
1127                 }
1128                 priv->gfargrp[grp_idx].rstat = rstat;
1129                 priv->gfargrp[grp_idx].tstat = tstat;
1130                 rstat = tstat =0;
1131         }
1132
1133         gfar_write(&regs->rqueue, rqueue);
1134         gfar_write(&regs->tqueue, tqueue);
1135
1136         priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
1137
1138         /* Initializing some of the rx/tx queue level parameters */
1139         for (i = 0; i < priv->num_tx_queues; i++) {
1140                 priv->tx_queue[i]->tx_ring_size = DEFAULT_TX_RING_SIZE;
1141                 priv->tx_queue[i]->num_txbdfree = DEFAULT_TX_RING_SIZE;
1142                 priv->tx_queue[i]->txcoalescing = DEFAULT_TX_COALESCE;
1143                 priv->tx_queue[i]->txic = DEFAULT_TXIC;
1144         }
1145
1146         for (i = 0; i < priv->num_rx_queues; i++) {
1147                 priv->rx_queue[i]->rx_ring_size = DEFAULT_RX_RING_SIZE;
1148                 priv->rx_queue[i]->rxcoalescing = DEFAULT_RX_COALESCE;
1149                 priv->rx_queue[i]->rxic = DEFAULT_RXIC;
1150         }
1151
1152         /* always enable rx filer*/
1153         priv->rx_filer_enable = 1;
1154         /* Enable most messages by default */
1155         priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1156
1157         /* Carrier starts down, phylib will bring it up */
1158         netif_carrier_off(dev);
1159
1160         err = register_netdev(dev);
1161
1162         if (err) {
1163                 pr_err("%s: Cannot register net device, aborting\n", dev->name);
1164                 goto register_fail;
1165         }
1166
1167         device_init_wakeup(&dev->dev,
1168                 priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1169
1170         /* fill out IRQ number and name fields */
1171         for (i = 0; i < priv->num_grps; i++) {
1172                 if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1173                         sprintf(priv->gfargrp[i].int_name_tx, "%s%s%c%s",
1174                                 dev->name, "_g", '0' + i, "_tx");
1175                         sprintf(priv->gfargrp[i].int_name_rx, "%s%s%c%s",
1176                                 dev->name, "_g", '0' + i, "_rx");
1177                         sprintf(priv->gfargrp[i].int_name_er, "%s%s%c%s",
1178                                 dev->name, "_g", '0' + i, "_er");
1179                 } else
1180                         strcpy(priv->gfargrp[i].int_name_tx, dev->name);
1181         }
1182
1183         /* Initialize the filer table */
1184         gfar_init_filer_table(priv);
1185
1186         /* Create all the sysfs files */
1187         gfar_init_sysfs(dev);
1188
1189         /* Print out the device info */
1190         netdev_info(dev, "mac: %pM\n", dev->dev_addr);
1191
1192         /* Even more device info helps when determining which kernel */
1193         /* provided which set of benchmarks. */
1194         netdev_info(dev, "Running with NAPI enabled\n");
1195         for (i = 0; i < priv->num_rx_queues; i++)
1196                 netdev_info(dev, "RX BD ring size for Q[%d]: %d\n",
1197                             i, priv->rx_queue[i]->rx_ring_size);
1198         for(i = 0; i < priv->num_tx_queues; i++)
1199                 netdev_info(dev, "TX BD ring size for Q[%d]: %d\n",
1200                             i, priv->tx_queue[i]->tx_ring_size);
1201
1202         return 0;
1203
1204 register_fail:
1205         unmap_group_regs(priv);
1206         free_tx_pointers(priv);
1207         free_rx_pointers(priv);
1208         if (priv->phy_node)
1209                 of_node_put(priv->phy_node);
1210         if (priv->tbi_node)
1211                 of_node_put(priv->tbi_node);
1212         free_netdev(dev);
1213         return err;
1214 }
1215
1216 static int gfar_remove(struct platform_device *ofdev)
1217 {
1218         struct gfar_private *priv = dev_get_drvdata(&ofdev->dev);
1219
1220         if (priv->phy_node)
1221                 of_node_put(priv->phy_node);
1222         if (priv->tbi_node)
1223                 of_node_put(priv->tbi_node);
1224
1225         dev_set_drvdata(&ofdev->dev, NULL);
1226
1227         unregister_netdev(priv->ndev);
1228         unmap_group_regs(priv);
1229         free_netdev(priv->ndev);
1230
1231         return 0;
1232 }
1233
1234 #ifdef CONFIG_PM
1235
1236 static int gfar_suspend(struct device *dev)
1237 {
1238         struct gfar_private *priv = dev_get_drvdata(dev);
1239         struct net_device *ndev = priv->ndev;
1240         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1241         unsigned long flags;
1242         u32 tempval;
1243
1244         int magic_packet = priv->wol_en &&
1245                 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1246
1247         netif_device_detach(ndev);
1248
1249         if (netif_running(ndev)) {
1250
1251                 local_irq_save(flags);
1252                 lock_tx_qs(priv);
1253                 lock_rx_qs(priv);
1254
1255                 gfar_halt_nodisable(ndev);
1256
1257                 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
1258                 tempval = gfar_read(&regs->maccfg1);
1259
1260                 tempval &= ~MACCFG1_TX_EN;
1261
1262                 if (!magic_packet)
1263                         tempval &= ~MACCFG1_RX_EN;
1264
1265                 gfar_write(&regs->maccfg1, tempval);
1266
1267                 unlock_rx_qs(priv);
1268                 unlock_tx_qs(priv);
1269                 local_irq_restore(flags);
1270
1271                 disable_napi(priv);
1272
1273                 if (magic_packet) {
1274                         /* Enable interrupt on Magic Packet */
1275                         gfar_write(&regs->imask, IMASK_MAG);
1276
1277                         /* Enable Magic Packet mode */
1278                         tempval = gfar_read(&regs->maccfg2);
1279                         tempval |= MACCFG2_MPEN;
1280                         gfar_write(&regs->maccfg2, tempval);
1281                 } else {
1282                         phy_stop(priv->phydev);
1283                 }
1284         }
1285
1286         return 0;
1287 }
1288
1289 static int gfar_resume(struct device *dev)
1290 {
1291         struct gfar_private *priv = dev_get_drvdata(dev);
1292         struct net_device *ndev = priv->ndev;
1293         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1294         unsigned long flags;
1295         u32 tempval;
1296         int magic_packet = priv->wol_en &&
1297                 (priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
1298
1299         if (!netif_running(ndev)) {
1300                 netif_device_attach(ndev);
1301                 return 0;
1302         }
1303
1304         if (!magic_packet && priv->phydev)
1305                 phy_start(priv->phydev);
1306
1307         /* Disable Magic Packet mode, in case something
1308          * else woke us up.
1309          */
1310         local_irq_save(flags);
1311         lock_tx_qs(priv);
1312         lock_rx_qs(priv);
1313
1314         tempval = gfar_read(&regs->maccfg2);
1315         tempval &= ~MACCFG2_MPEN;
1316         gfar_write(&regs->maccfg2, tempval);
1317
1318         gfar_start(ndev);
1319
1320         unlock_rx_qs(priv);
1321         unlock_tx_qs(priv);
1322         local_irq_restore(flags);
1323
1324         netif_device_attach(ndev);
1325
1326         enable_napi(priv);
1327
1328         return 0;
1329 }
1330
1331 static int gfar_restore(struct device *dev)
1332 {
1333         struct gfar_private *priv = dev_get_drvdata(dev);
1334         struct net_device *ndev = priv->ndev;
1335
1336         if (!netif_running(ndev))
1337                 return 0;
1338
1339         gfar_init_bds(ndev);
1340         init_registers(ndev);
1341         gfar_set_mac_address(ndev);
1342         gfar_init_mac(ndev);
1343         gfar_start(ndev);
1344
1345         priv->oldlink = 0;
1346         priv->oldspeed = 0;
1347         priv->oldduplex = -1;
1348
1349         if (priv->phydev)
1350                 phy_start(priv->phydev);
1351
1352         netif_device_attach(ndev);
1353         enable_napi(priv);
1354
1355         return 0;
1356 }
1357
1358 static struct dev_pm_ops gfar_pm_ops = {
1359         .suspend = gfar_suspend,
1360         .resume = gfar_resume,
1361         .freeze = gfar_suspend,
1362         .thaw = gfar_resume,
1363         .restore = gfar_restore,
1364 };
1365
1366 #define GFAR_PM_OPS (&gfar_pm_ops)
1367
1368 #else
1369
1370 #define GFAR_PM_OPS NULL
1371
1372 #endif
1373
1374 /* Reads the controller's registers to determine what interface
1375  * connects it to the PHY.
1376  */
1377 static phy_interface_t gfar_get_interface(struct net_device *dev)
1378 {
1379         struct gfar_private *priv = netdev_priv(dev);
1380         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1381         u32 ecntrl;
1382
1383         ecntrl = gfar_read(&regs->ecntrl);
1384
1385         if (ecntrl & ECNTRL_SGMII_MODE)
1386                 return PHY_INTERFACE_MODE_SGMII;
1387
1388         if (ecntrl & ECNTRL_TBI_MODE) {
1389                 if (ecntrl & ECNTRL_REDUCED_MODE)
1390                         return PHY_INTERFACE_MODE_RTBI;
1391                 else
1392                         return PHY_INTERFACE_MODE_TBI;
1393         }
1394
1395         if (ecntrl & ECNTRL_REDUCED_MODE) {
1396                 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
1397                         return PHY_INTERFACE_MODE_RMII;
1398                 else {
1399                         phy_interface_t interface = priv->interface;
1400
1401                         /*
1402                          * This isn't autodetected right now, so it must
1403                          * be set by the device tree or platform code.
1404                          */
1405                         if (interface == PHY_INTERFACE_MODE_RGMII_ID)
1406                                 return PHY_INTERFACE_MODE_RGMII_ID;
1407
1408                         return PHY_INTERFACE_MODE_RGMII;
1409                 }
1410         }
1411
1412         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
1413                 return PHY_INTERFACE_MODE_GMII;
1414
1415         return PHY_INTERFACE_MODE_MII;
1416 }
1417
1418
1419 /* Initializes driver's PHY state, and attaches to the PHY.
1420  * Returns 0 on success.
1421  */
1422 static int init_phy(struct net_device *dev)
1423 {
1424         struct gfar_private *priv = netdev_priv(dev);
1425         uint gigabit_support =
1426                 priv->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
1427                 SUPPORTED_1000baseT_Full : 0;
1428         phy_interface_t interface;
1429
1430         priv->oldlink = 0;
1431         priv->oldspeed = 0;
1432         priv->oldduplex = -1;
1433
1434         interface = gfar_get_interface(dev);
1435
1436         priv->phydev = of_phy_connect(dev, priv->phy_node, &adjust_link, 0,
1437                                       interface);
1438         if (!priv->phydev)
1439                 priv->phydev = of_phy_connect_fixed_link(dev, &adjust_link,
1440                                                          interface);
1441         if (!priv->phydev) {
1442                 dev_err(&dev->dev, "could not attach to PHY\n");
1443                 return -ENODEV;
1444         }
1445
1446         if (interface == PHY_INTERFACE_MODE_SGMII)
1447                 gfar_configure_serdes(dev);
1448
1449         /* Remove any features not supported by the controller */
1450         priv->phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
1451         priv->phydev->advertising = priv->phydev->supported;
1452
1453         return 0;
1454 }
1455
1456 /*
1457  * Initialize TBI PHY interface for communicating with the
1458  * SERDES lynx PHY on the chip.  We communicate with this PHY
1459  * through the MDIO bus on each controller, treating it as a
1460  * "normal" PHY at the address found in the TBIPA register.  We assume
1461  * that the TBIPA register is valid.  Either the MDIO bus code will set
1462  * it to a value that doesn't conflict with other PHYs on the bus, or the
1463  * value doesn't matter, as there are no other PHYs on the bus.
1464  */
1465 static void gfar_configure_serdes(struct net_device *dev)
1466 {
1467         struct gfar_private *priv = netdev_priv(dev);
1468         struct phy_device *tbiphy;
1469
1470         if (!priv->tbi_node) {
1471                 dev_warn(&dev->dev, "error: SGMII mode requires that the "
1472                                     "device tree specify a tbi-handle\n");
1473                 return;
1474         }
1475
1476         tbiphy = of_phy_find_device(priv->tbi_node);
1477         if (!tbiphy) {
1478                 dev_err(&dev->dev, "error: Could not get TBI device\n");
1479                 return;
1480         }
1481
1482         /*
1483          * If the link is already up, we must already be ok, and don't need to
1484          * configure and reset the TBI<->SerDes link.  Maybe U-Boot configured
1485          * everything for us?  Resetting it takes the link down and requires
1486          * several seconds for it to come back.
1487          */
1488         if (phy_read(tbiphy, MII_BMSR) & BMSR_LSTATUS)
1489                 return;
1490
1491         /* Single clk mode, mii mode off(for serdes communication) */
1492         phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT);
1493
1494         phy_write(tbiphy, MII_ADVERTISE,
1495                         ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
1496                         ADVERTISE_1000XPSE_ASYM);
1497
1498         phy_write(tbiphy, MII_BMCR, BMCR_ANENABLE |
1499                         BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
1500 }
1501
1502 static void init_registers(struct net_device *dev)
1503 {
1504         struct gfar_private *priv = netdev_priv(dev);
1505         struct gfar __iomem *regs = NULL;
1506         int i = 0;
1507
1508         for (i = 0; i < priv->num_grps; i++) {
1509                 regs = priv->gfargrp[i].regs;
1510                 /* Clear IEVENT */
1511                 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1512
1513                 /* Initialize IMASK */
1514                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1515         }
1516
1517         regs = priv->gfargrp[0].regs;
1518         /* Init hash registers to zero */
1519         gfar_write(&regs->igaddr0, 0);
1520         gfar_write(&regs->igaddr1, 0);
1521         gfar_write(&regs->igaddr2, 0);
1522         gfar_write(&regs->igaddr3, 0);
1523         gfar_write(&regs->igaddr4, 0);
1524         gfar_write(&regs->igaddr5, 0);
1525         gfar_write(&regs->igaddr6, 0);
1526         gfar_write(&regs->igaddr7, 0);
1527
1528         gfar_write(&regs->gaddr0, 0);
1529         gfar_write(&regs->gaddr1, 0);
1530         gfar_write(&regs->gaddr2, 0);
1531         gfar_write(&regs->gaddr3, 0);
1532         gfar_write(&regs->gaddr4, 0);
1533         gfar_write(&regs->gaddr5, 0);
1534         gfar_write(&regs->gaddr6, 0);
1535         gfar_write(&regs->gaddr7, 0);
1536
1537         /* Zero out the rmon mib registers if it has them */
1538         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
1539                 memset_io(&(regs->rmon), 0, sizeof (struct rmon_mib));
1540
1541                 /* Mask off the CAM interrupts */
1542                 gfar_write(&regs->rmon.cam1, 0xffffffff);
1543                 gfar_write(&regs->rmon.cam2, 0xffffffff);
1544         }
1545
1546         /* Initialize the max receive buffer length */
1547         gfar_write(&regs->mrblr, priv->rx_buffer_size);
1548
1549         /* Initialize the Minimum Frame Length Register */
1550         gfar_write(&regs->minflr, MINFLR_INIT_SETTINGS);
1551 }
1552
1553 static int __gfar_is_rx_idle(struct gfar_private *priv)
1554 {
1555         u32 res;
1556
1557         /*
1558          * Normaly TSEC should not hang on GRS commands, so we should
1559          * actually wait for IEVENT_GRSC flag.
1560          */
1561         if (likely(!gfar_has_errata(priv, GFAR_ERRATA_A002)))
1562                 return 0;
1563
1564         /*
1565          * Read the eTSEC register at offset 0xD1C. If bits 7-14 are
1566          * the same as bits 23-30, the eTSEC Rx is assumed to be idle
1567          * and the Rx can be safely reset.
1568          */
1569         res = gfar_read((void __iomem *)priv->gfargrp[0].regs + 0xd1c);
1570         res &= 0x7f807f80;
1571         if ((res & 0xffff) == (res >> 16))
1572                 return 1;
1573
1574         return 0;
1575 }
1576
1577 /* Halt the receive and transmit queues */
1578 static void gfar_halt_nodisable(struct net_device *dev)
1579 {
1580         struct gfar_private *priv = netdev_priv(dev);
1581         struct gfar __iomem *regs = NULL;
1582         u32 tempval;
1583         int i = 0;
1584
1585         for (i = 0; i < priv->num_grps; i++) {
1586                 regs = priv->gfargrp[i].regs;
1587                 /* Mask all interrupts */
1588                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1589
1590                 /* Clear all interrupts */
1591                 gfar_write(&regs->ievent, IEVENT_INIT_CLEAR);
1592         }
1593
1594         regs = priv->gfargrp[0].regs;
1595         /* Stop the DMA, and wait for it to stop */
1596         tempval = gfar_read(&regs->dmactrl);
1597         if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
1598             != (DMACTRL_GRS | DMACTRL_GTS)) {
1599                 int ret;
1600
1601                 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
1602                 gfar_write(&regs->dmactrl, tempval);
1603
1604                 do {
1605                         ret = spin_event_timeout(((gfar_read(&regs->ievent) &
1606                                  (IEVENT_GRSC | IEVENT_GTSC)) ==
1607                                  (IEVENT_GRSC | IEVENT_GTSC)), 1000000, 0);
1608                         if (!ret && !(gfar_read(&regs->ievent) & IEVENT_GRSC))
1609                                 ret = __gfar_is_rx_idle(priv);
1610                 } while (!ret);
1611         }
1612 }
1613
1614 /* Halt the receive and transmit queues */
1615 void gfar_halt(struct net_device *dev)
1616 {
1617         struct gfar_private *priv = netdev_priv(dev);
1618         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1619         u32 tempval;
1620
1621         gfar_halt_nodisable(dev);
1622
1623         /* Disable Rx and Tx */
1624         tempval = gfar_read(&regs->maccfg1);
1625         tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
1626         gfar_write(&regs->maccfg1, tempval);
1627 }
1628
1629 static void free_grp_irqs(struct gfar_priv_grp *grp)
1630 {
1631         free_irq(grp->interruptError, grp);
1632         free_irq(grp->interruptTransmit, grp);
1633         free_irq(grp->interruptReceive, grp);
1634 }
1635
1636 void stop_gfar(struct net_device *dev)
1637 {
1638         struct gfar_private *priv = netdev_priv(dev);
1639         unsigned long flags;
1640         int i;
1641
1642         phy_stop(priv->phydev);
1643
1644
1645         /* Lock it down */
1646         local_irq_save(flags);
1647         lock_tx_qs(priv);
1648         lock_rx_qs(priv);
1649
1650         gfar_halt(dev);
1651
1652         unlock_rx_qs(priv);
1653         unlock_tx_qs(priv);
1654         local_irq_restore(flags);
1655
1656         /* Free the IRQs */
1657         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1658                 for (i = 0; i < priv->num_grps; i++)
1659                         free_grp_irqs(&priv->gfargrp[i]);
1660         } else {
1661                 for (i = 0; i < priv->num_grps; i++)
1662                         free_irq(priv->gfargrp[i].interruptTransmit,
1663                                         &priv->gfargrp[i]);
1664         }
1665
1666         free_skb_resources(priv);
1667 }
1668
1669 static void free_skb_tx_queue(struct gfar_priv_tx_q *tx_queue)
1670 {
1671         struct txbd8 *txbdp;
1672         struct gfar_private *priv = netdev_priv(tx_queue->dev);
1673         int i, j;
1674
1675         txbdp = tx_queue->tx_bd_base;
1676
1677         for (i = 0; i < tx_queue->tx_ring_size; i++) {
1678                 if (!tx_queue->tx_skbuff[i])
1679                         continue;
1680
1681                 dma_unmap_single(&priv->ofdev->dev, txbdp->bufPtr,
1682                                 txbdp->length, DMA_TO_DEVICE);
1683                 txbdp->lstatus = 0;
1684                 for (j = 0; j < skb_shinfo(tx_queue->tx_skbuff[i])->nr_frags;
1685                                 j++) {
1686                         txbdp++;
1687                         dma_unmap_page(&priv->ofdev->dev, txbdp->bufPtr,
1688                                         txbdp->length, DMA_TO_DEVICE);
1689                 }
1690                 txbdp++;
1691                 dev_kfree_skb_any(tx_queue->tx_skbuff[i]);
1692                 tx_queue->tx_skbuff[i] = NULL;
1693         }
1694         kfree(tx_queue->tx_skbuff);
1695 }
1696
1697 static void free_skb_rx_queue(struct gfar_priv_rx_q *rx_queue)
1698 {
1699         struct rxbd8 *rxbdp;
1700         struct gfar_private *priv = netdev_priv(rx_queue->dev);
1701         int i;
1702
1703         rxbdp = rx_queue->rx_bd_base;
1704
1705         for (i = 0; i < rx_queue->rx_ring_size; i++) {
1706                 if (rx_queue->rx_skbuff[i]) {
1707                         dma_unmap_single(&priv->ofdev->dev,
1708                                         rxbdp->bufPtr, priv->rx_buffer_size,
1709                                         DMA_FROM_DEVICE);
1710                         dev_kfree_skb_any(rx_queue->rx_skbuff[i]);
1711                         rx_queue->rx_skbuff[i] = NULL;
1712                 }
1713                 rxbdp->lstatus = 0;
1714                 rxbdp->bufPtr = 0;
1715                 rxbdp++;
1716         }
1717         kfree(rx_queue->rx_skbuff);
1718 }
1719
1720 /* If there are any tx skbs or rx skbs still around, free them.
1721  * Then free tx_skbuff and rx_skbuff */
1722 static void free_skb_resources(struct gfar_private *priv)
1723 {
1724         struct gfar_priv_tx_q *tx_queue = NULL;
1725         struct gfar_priv_rx_q *rx_queue = NULL;
1726         int i;
1727
1728         /* Go through all the buffer descriptors and free their data buffers */
1729         for (i = 0; i < priv->num_tx_queues; i++) {
1730                 struct netdev_queue *txq;
1731                 tx_queue = priv->tx_queue[i];
1732                 txq = netdev_get_tx_queue(tx_queue->dev, tx_queue->qindex);
1733                 if(tx_queue->tx_skbuff)
1734                         free_skb_tx_queue(tx_queue);
1735                 netdev_tx_reset_queue(txq);
1736         }
1737
1738         for (i = 0; i < priv->num_rx_queues; i++) {
1739                 rx_queue = priv->rx_queue[i];
1740                 if(rx_queue->rx_skbuff)
1741                         free_skb_rx_queue(rx_queue);
1742         }
1743
1744         dma_free_coherent(&priv->ofdev->dev,
1745                         sizeof(struct txbd8) * priv->total_tx_ring_size +
1746                         sizeof(struct rxbd8) * priv->total_rx_ring_size,
1747                         priv->tx_queue[0]->tx_bd_base,
1748                         priv->tx_queue[0]->tx_bd_dma_base);
1749         skb_queue_purge(&priv->rx_recycle);
1750 }
1751
1752 void gfar_start(struct net_device *dev)
1753 {
1754         struct gfar_private *priv = netdev_priv(dev);
1755         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1756         u32 tempval;
1757         int i = 0;
1758
1759         /* Enable Rx and Tx in MACCFG1 */
1760         tempval = gfar_read(&regs->maccfg1);
1761         tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
1762         gfar_write(&regs->maccfg1, tempval);
1763
1764         /* Initialize DMACTRL to have WWR and WOP */
1765         tempval = gfar_read(&regs->dmactrl);
1766         tempval |= DMACTRL_INIT_SETTINGS;
1767         gfar_write(&regs->dmactrl, tempval);
1768
1769         /* Make sure we aren't stopped */
1770         tempval = gfar_read(&regs->dmactrl);
1771         tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
1772         gfar_write(&regs->dmactrl, tempval);
1773
1774         for (i = 0; i < priv->num_grps; i++) {
1775                 regs = priv->gfargrp[i].regs;
1776                 /* Clear THLT/RHLT, so that the DMA starts polling now */
1777                 gfar_write(&regs->tstat, priv->gfargrp[i].tstat);
1778                 gfar_write(&regs->rstat, priv->gfargrp[i].rstat);
1779                 /* Unmask the interrupts we look for */
1780                 gfar_write(&regs->imask, IMASK_DEFAULT);
1781         }
1782
1783         dev->trans_start = jiffies; /* prevent tx timeout */
1784 }
1785
1786 void gfar_configure_coalescing(struct gfar_private *priv,
1787         unsigned long tx_mask, unsigned long rx_mask)
1788 {
1789         struct gfar __iomem *regs = priv->gfargrp[0].regs;
1790         u32 __iomem *baddr;
1791         int i = 0;
1792
1793         /* Backward compatible case ---- even if we enable
1794          * multiple queues, there's only single reg to program
1795          */
1796         gfar_write(&regs->txic, 0);
1797         if(likely(priv->tx_queue[0]->txcoalescing))
1798                 gfar_write(&regs->txic, priv->tx_queue[0]->txic);
1799
1800         gfar_write(&regs->rxic, 0);
1801         if(unlikely(priv->rx_queue[0]->rxcoalescing))
1802                 gfar_write(&regs->rxic, priv->rx_queue[0]->rxic);
1803
1804         if (priv->mode == MQ_MG_MODE) {
1805                 baddr = &regs->txic0;
1806                 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) {
1807                         gfar_write(baddr + i, 0);
1808                         if (likely(priv->tx_queue[i]->txcoalescing))
1809                                 gfar_write(baddr + i, priv->tx_queue[i]->txic);
1810                 }
1811
1812                 baddr = &regs->rxic0;
1813                 for_each_set_bit(i, &rx_mask, priv->num_rx_queues) {
1814                         gfar_write(baddr + i, 0);
1815                         if (likely(priv->rx_queue[i]->rxcoalescing))
1816                                 gfar_write(baddr + i, priv->rx_queue[i]->rxic);
1817                 }
1818         }
1819 }
1820
1821 static int register_grp_irqs(struct gfar_priv_grp *grp)
1822 {
1823         struct gfar_private *priv = grp->priv;
1824         struct net_device *dev = priv->ndev;
1825         int err;
1826
1827         /* If the device has multiple interrupts, register for
1828          * them.  Otherwise, only register for the one */
1829         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1830                 /* Install our interrupt handlers for Error,
1831                  * Transmit, and Receive */
1832                 if ((err = request_irq(grp->interruptError, gfar_error, 0,
1833                                 grp->int_name_er,grp)) < 0) {
1834                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1835                                   grp->interruptError);
1836
1837                         goto err_irq_fail;
1838                 }
1839
1840                 if ((err = request_irq(grp->interruptTransmit, gfar_transmit,
1841                                 0, grp->int_name_tx, grp)) < 0) {
1842                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1843                                   grp->interruptTransmit);
1844                         goto tx_irq_fail;
1845                 }
1846
1847                 if ((err = request_irq(grp->interruptReceive, gfar_receive, 0,
1848                                 grp->int_name_rx, grp)) < 0) {
1849                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1850                                   grp->interruptReceive);
1851                         goto rx_irq_fail;
1852                 }
1853         } else {
1854                 if ((err = request_irq(grp->interruptTransmit, gfar_interrupt, 0,
1855                                 grp->int_name_tx, grp)) < 0) {
1856                         netif_err(priv, intr, dev, "Can't get IRQ %d\n",
1857                                   grp->interruptTransmit);
1858                         goto err_irq_fail;
1859                 }
1860         }
1861
1862         return 0;
1863
1864 rx_irq_fail:
1865         free_irq(grp->interruptTransmit, grp);
1866 tx_irq_fail:
1867         free_irq(grp->interruptError, grp);
1868 err_irq_fail:
1869         return err;
1870
1871 }
1872
1873 /* Bring the controller up and running */
1874 int startup_gfar(struct net_device *ndev)
1875 {
1876         struct gfar_private *priv = netdev_priv(ndev);
1877         struct gfar __iomem *regs = NULL;
1878         int err, i, j;
1879
1880         for (i = 0; i < priv->num_grps; i++) {
1881                 regs= priv->gfargrp[i].regs;
1882                 gfar_write(&regs->imask, IMASK_INIT_CLEAR);
1883         }
1884
1885         regs= priv->gfargrp[0].regs;
1886         err = gfar_alloc_skb_resources(ndev);
1887         if (err)
1888                 return err;
1889
1890         gfar_init_mac(ndev);
1891
1892         for (i = 0; i < priv->num_grps; i++) {
1893                 err = register_grp_irqs(&priv->gfargrp[i]);
1894                 if (err) {
1895                         for (j = 0; j < i; j++)
1896                                 free_grp_irqs(&priv->gfargrp[j]);
1897                         goto irq_fail;
1898                 }
1899         }
1900
1901         /* Start the controller */
1902         gfar_start(ndev);
1903
1904         phy_start(priv->phydev);
1905
1906         gfar_configure_coalescing(priv, 0xFF, 0xFF);
1907
1908         return 0;
1909
1910 irq_fail:
1911         free_skb_resources(priv);
1912         return err;
1913 }
1914
1915 /* Called when something needs to use the ethernet device */
1916 /* Returns 0 for success. */
1917 static int gfar_enet_open(struct net_device *dev)
1918 {
1919         struct gfar_private *priv = netdev_priv(dev);
1920         int err;
1921
1922         enable_napi(priv);
1923
1924         skb_queue_head_init(&priv->rx_recycle);
1925
1926         /* Initialize a bunch of registers */
1927         init_registers(dev);
1928
1929         gfar_set_mac_address(dev);
1930
1931         err = init_phy(dev);
1932
1933         if (err) {
1934                 disable_napi(priv);
1935                 return err;
1936         }
1937
1938         err = startup_gfar(dev);
1939         if (err) {
1940                 disable_napi(priv);
1941                 return err;
1942         }
1943
1944         netif_tx_start_all_queues(dev);
1945
1946         device_set_wakeup_enable(&dev->dev, priv->wol_en);
1947
1948         return err;
1949 }
1950
1951 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb)
1952 {
1953         struct txfcb *fcb = (struct txfcb *)skb_push(skb, GMAC_FCB_LEN);
1954
1955         memset(fcb, 0, GMAC_FCB_LEN);
1956
1957         return fcb;
1958 }
1959
1960 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb,
1961                 int fcb_length)
1962 {
1963         u8 flags = 0;
1964
1965         /* If we're here, it's a IP packet with a TCP or UDP
1966          * payload.  We set it to checksum, using a pseudo-header
1967          * we provide
1968          */
1969         flags = TXFCB_DEFAULT;
1970
1971         /* Tell the controller what the protocol is */
1972         /* And provide the already calculated phcs */
1973         if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
1974                 flags |= TXFCB_UDP;
1975                 fcb->phcs = udp_hdr(skb)->check;
1976         } else
1977                 fcb->phcs = tcp_hdr(skb)->check;
1978
1979         /* l3os is the distance between the start of the
1980          * frame (skb->data) and the start of the IP hdr.
1981          * l4os is the distance between the start of the
1982          * l3 hdr and the l4 hdr */
1983         fcb->l3os = (u16)(skb_network_offset(skb) - fcb_length);
1984         fcb->l4os = skb_network_header_len(skb);
1985
1986         fcb->flags = flags;
1987 }
1988
1989 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
1990 {
1991         fcb->flags |= TXFCB_VLN;
1992         fcb->vlctl = vlan_tx_tag_get(skb);
1993 }
1994
1995 static inline struct txbd8 *skip_txbd(struct txbd8 *bdp, int stride,
1996                                struct txbd8 *base, int ring_size)
1997 {
1998         struct txbd8 *new_bd = bdp + stride;
1999
2000         return (new_bd >= (base + ring_size)) ? (new_bd - ring_size) : new_bd;
2001 }
2002
2003 static inline struct txbd8 *next_txbd(struct txbd8 *bdp, struct txbd8 *base,
2004                 int ring_size)
2005 {
2006         return skip_txbd(bdp, 1, base, ring_size);
2007 }
2008
2009 /* This is called by the kernel when a frame is ready for transmission. */
2010 /* It is pointed to by the dev->hard_start_xmit function pointer */
2011 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
2012 {
2013         struct gfar_private *priv = netdev_priv(dev);
2014         struct gfar_priv_tx_q *tx_queue = NULL;
2015         struct netdev_queue *txq;
2016         struct gfar __iomem *regs = NULL;
2017         struct txfcb *fcb = NULL;
2018         struct txbd8 *txbdp, *txbdp_start, *base, *txbdp_tstamp = NULL;
2019         u32 lstatus;
2020         int i, rq = 0, do_tstamp = 0;
2021         u32 bufaddr;
2022         unsigned long flags;
2023         unsigned int nr_frags, nr_txbds, length, fcb_length = GMAC_FCB_LEN;
2024
2025         /*
2026          * TOE=1 frames larger than 2500 bytes may see excess delays
2027          * before start of transmission.
2028          */
2029         if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_76) &&
2030                         skb->ip_summed == CHECKSUM_PARTIAL &&
2031                         skb->len > 2500)) {
2032                 int ret;
2033
2034                 ret = skb_checksum_help(skb);
2035                 if (ret)
2036                         return ret;
2037         }
2038
2039         rq = skb->queue_mapping;
2040         tx_queue = priv->tx_queue[rq];
2041         txq = netdev_get_tx_queue(dev, rq);
2042         base = tx_queue->tx_bd_base;
2043         regs = tx_queue->grp->regs;
2044
2045         /* check if time stamp should be generated */
2046         if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
2047                         priv->hwts_tx_en)) {
2048                 do_tstamp = 1;
2049                 fcb_length = GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2050         }
2051
2052         /* make space for additional header when fcb is needed */
2053         if (((skb->ip_summed == CHECKSUM_PARTIAL) ||
2054                         vlan_tx_tag_present(skb) ||
2055                         unlikely(do_tstamp)) &&
2056                         (skb_headroom(skb) < fcb_length)) {
2057                 struct sk_buff *skb_new;
2058
2059                 skb_new = skb_realloc_headroom(skb, fcb_length);
2060                 if (!skb_new) {
2061                         dev->stats.tx_errors++;
2062                         kfree_skb(skb);
2063                         return NETDEV_TX_OK;
2064                 }
2065
2066                 /* Steal sock reference for processing TX time stamps */
2067                 swap(skb_new->sk, skb->sk);
2068                 swap(skb_new->destructor, skb->destructor);
2069                 kfree_skb(skb);
2070                 skb = skb_new;
2071         }
2072
2073         /* total number of fragments in the SKB */
2074         nr_frags = skb_shinfo(skb)->nr_frags;
2075
2076         /* calculate the required number of TxBDs for this skb */
2077         if (unlikely(do_tstamp))
2078                 nr_txbds = nr_frags + 2;
2079         else
2080                 nr_txbds = nr_frags + 1;
2081
2082         /* check if there is space to queue this packet */
2083         if (nr_txbds > tx_queue->num_txbdfree) {
2084                 /* no space, stop the queue */
2085                 netif_tx_stop_queue(txq);
2086                 dev->stats.tx_fifo_errors++;
2087                 return NETDEV_TX_BUSY;
2088         }
2089
2090         /* Update transmit stats */
2091         tx_queue->stats.tx_bytes += skb->len;
2092         tx_queue->stats.tx_packets++;
2093
2094         txbdp = txbdp_start = tx_queue->cur_tx;
2095         lstatus = txbdp->lstatus;
2096
2097         /* Time stamp insertion requires one additional TxBD */
2098         if (unlikely(do_tstamp))
2099                 txbdp_tstamp = txbdp = next_txbd(txbdp, base,
2100                                 tx_queue->tx_ring_size);
2101
2102         if (nr_frags == 0) {
2103                 if (unlikely(do_tstamp))
2104                         txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_LAST |
2105                                         TXBD_INTERRUPT);
2106                 else
2107                         lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2108         } else {
2109                 /* Place the fragment addresses and lengths into the TxBDs */
2110                 for (i = 0; i < nr_frags; i++) {
2111                         /* Point at the next BD, wrapping as needed */
2112                         txbdp = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2113
2114                         length = skb_shinfo(skb)->frags[i].size;
2115
2116                         lstatus = txbdp->lstatus | length |
2117                                 BD_LFLAG(TXBD_READY);
2118
2119                         /* Handle the last BD specially */
2120                         if (i == nr_frags - 1)
2121                                 lstatus |= BD_LFLAG(TXBD_LAST | TXBD_INTERRUPT);
2122
2123                         bufaddr = skb_frag_dma_map(&priv->ofdev->dev,
2124                                                    &skb_shinfo(skb)->frags[i],
2125                                                    0,
2126                                                    length,
2127                                                    DMA_TO_DEVICE);
2128
2129                         /* set the TxBD length and buffer pointer */
2130                         txbdp->bufPtr = bufaddr;
2131                         txbdp->lstatus = lstatus;
2132                 }
2133
2134                 lstatus = txbdp_start->lstatus;
2135         }
2136
2137         /* Add TxPAL between FCB and frame if required */
2138         if (unlikely(do_tstamp)) {
2139                 skb_push(skb, GMAC_TXPAL_LEN);
2140                 memset(skb->data, 0, GMAC_TXPAL_LEN);
2141         }
2142
2143         /* Set up checksumming */
2144         if (CHECKSUM_PARTIAL == skb->ip_summed) {
2145                 fcb = gfar_add_fcb(skb);
2146                 /* as specified by errata */
2147                 if (unlikely(gfar_has_errata(priv, GFAR_ERRATA_12)
2148                              && ((unsigned long)fcb % 0x20) > 0x18)) {
2149                         __skb_pull(skb, GMAC_FCB_LEN);
2150                         skb_checksum_help(skb);
2151                 } else {
2152                         lstatus |= BD_LFLAG(TXBD_TOE);
2153                         gfar_tx_checksum(skb, fcb, fcb_length);
2154                 }
2155         }
2156
2157         if (vlan_tx_tag_present(skb)) {
2158                 if (unlikely(NULL == fcb)) {
2159                         fcb = gfar_add_fcb(skb);
2160                         lstatus |= BD_LFLAG(TXBD_TOE);
2161                 }
2162
2163                 gfar_tx_vlan(skb, fcb);
2164         }
2165
2166         /* Setup tx hardware time stamping if requested */
2167         if (unlikely(do_tstamp)) {
2168                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2169                 if (fcb == NULL)
2170                         fcb = gfar_add_fcb(skb);
2171                 fcb->ptp = 1;
2172                 lstatus |= BD_LFLAG(TXBD_TOE);
2173         }
2174
2175         txbdp_start->bufPtr = dma_map_single(&priv->ofdev->dev, skb->data,
2176                         skb_headlen(skb), DMA_TO_DEVICE);
2177
2178         /*
2179          * If time stamping is requested one additional TxBD must be set up. The
2180          * first TxBD points to the FCB and must have a data length of
2181          * GMAC_FCB_LEN. The second TxBD points to the actual frame data with
2182          * the full frame length.
2183          */
2184         if (unlikely(do_tstamp)) {
2185                 txbdp_tstamp->bufPtr = txbdp_start->bufPtr + fcb_length;
2186                 txbdp_tstamp->lstatus |= BD_LFLAG(TXBD_READY) |
2187                                 (skb_headlen(skb) - fcb_length);
2188                 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | GMAC_FCB_LEN;
2189         } else {
2190                 lstatus |= BD_LFLAG(TXBD_CRC | TXBD_READY) | skb_headlen(skb);
2191         }
2192
2193         netdev_tx_sent_queue(txq, skb->len);
2194
2195         /*
2196          * We can work in parallel with gfar_clean_tx_ring(), except
2197          * when modifying num_txbdfree. Note that we didn't grab the lock
2198          * when we were reading the num_txbdfree and checking for available
2199          * space, that's because outside of this function it can only grow,
2200          * and once we've got needed space, it cannot suddenly disappear.
2201          *
2202          * The lock also protects us from gfar_error(), which can modify
2203          * regs->tstat and thus retrigger the transfers, which is why we
2204          * also must grab the lock before setting ready bit for the first
2205          * to be transmitted BD.
2206          */
2207         spin_lock_irqsave(&tx_queue->txlock, flags);
2208
2209         /*
2210          * The powerpc-specific eieio() is used, as wmb() has too strong
2211          * semantics (it requires synchronization between cacheable and
2212          * uncacheable mappings, which eieio doesn't provide and which we
2213          * don't need), thus requiring a more expensive sync instruction.  At
2214          * some point, the set of architecture-independent barrier functions
2215          * should be expanded to include weaker barriers.
2216          */
2217         eieio();
2218
2219         txbdp_start->lstatus = lstatus;
2220
2221         eieio(); /* force lstatus write before tx_skbuff */
2222
2223         tx_queue->tx_skbuff[tx_queue->skb_curtx] = skb;
2224
2225         /* Update the current skb pointer to the next entry we will use
2226          * (wrapping if necessary) */
2227         tx_queue->skb_curtx = (tx_queue->skb_curtx + 1) &
2228                 TX_RING_MOD_MASK(tx_queue->tx_ring_size);
2229
2230         tx_queue->cur_tx = next_txbd(txbdp, base, tx_queue->tx_ring_size);
2231
2232         /* reduce TxBD free count */
2233         tx_queue->num_txbdfree -= (nr_txbds);
2234
2235         /* If the next BD still needs to be cleaned up, then the bds
2236            are full.  We need to tell the kernel to stop sending us stuff. */
2237         if (!tx_queue->num_txbdfree) {
2238                 netif_tx_stop_queue(txq);
2239
2240                 dev->stats.tx_fifo_errors++;
2241         }
2242
2243         /* Tell the DMA to go go go */
2244         gfar_write(&regs->tstat, TSTAT_CLEAR_THALT >> tx_queue->qindex);
2245
2246         /* Unlock priv */
2247         spin_unlock_irqrestore(&tx_queue->txlock, flags);
2248
2249         return NETDEV_TX_OK;
2250 }
2251
2252 /* Stops the kernel queue, and halts the controller */
2253 static int gfar_close(struct net_device *dev)
2254 {
2255         struct gfar_private *priv = netdev_priv(dev);
2256
2257         disable_napi(priv);
2258
2259         cancel_work_sync(&priv->reset_task);
2260         stop_gfar(dev);
2261
2262         /* Disconnect from the PHY */
2263         phy_disconnect(priv->phydev);
2264         priv->phydev = NULL;
2265
2266         netif_tx_stop_all_queues(dev);
2267
2268         return 0;
2269 }
2270
2271 /* Changes the mac address if the controller is not running. */
2272 static int gfar_set_mac_address(struct net_device *dev)
2273 {
2274         gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
2275
2276         return 0;
2277 }
2278
2279 /* Check if rx parser should be activated */
2280 void gfar_check_rx_parser_mode(struct gfar_private *priv)
2281 {
2282         struct gfar __iomem *regs;
2283         u32 tempval;
2284
2285         regs = priv->gfargrp[0].regs;
2286
2287         tempval = gfar_read(&regs->rctrl);
2288         /* If parse is no longer required, then disable parser */
2289         if (tempval & RCTRL_REQ_PARSER)
2290                 tempval |= RCTRL_PRSDEP_INIT;
2291         else
2292                 tempval &= ~RCTRL_PRSDEP_INIT;
2293         gfar_write(&regs->rctrl, tempval);
2294 }
2295
2296 /* Enables and disables VLAN insertion/extraction */
2297 void gfar_vlan_mode(struct net_device *dev, netdev_features_t features)
2298 {
2299         struct gfar_private *priv = netdev_priv(dev);
2300         struct gfar __iomem *regs = NULL;
2301         unsigned long flags;
2302         u32 tempval;
2303
2304         regs = priv->gfargrp[0].regs;
2305         local_irq_save(flags);
2306         lock_rx_qs(priv);
2307
2308         if (features & NETIF_F_HW_VLAN_TX) {
2309                 /* Enable VLAN tag insertion */
2310                 tempval = gfar_read(&regs->tctrl);
2311                 tempval |= TCTRL_VLINS;
2312                 gfar_write(&regs->tctrl, tempval);
2313         } else {
2314                 /* Disable VLAN tag insertion */
2315                 tempval = gfar_read(&regs->tctrl);
2316                 tempval &= ~TCTRL_VLINS;
2317                 gfar_write(&regs->tctrl, tempval);
2318         }
2319
2320         if (features & NETIF_F_HW_VLAN_RX) {
2321                 /* Enable VLAN tag extraction */
2322                 tempval = gfar_read(&regs->rctrl);
2323                 tempval |= (RCTRL_VLEX | RCTRL_PRSDEP_INIT);
2324                 gfar_write(&regs->rctrl, tempval);
2325         } else {
2326                 /* Disable VLAN tag extraction */
2327                 tempval = gfar_read(&regs->rctrl);
2328                 tempval &= ~RCTRL_VLEX;
2329                 gfar_write(&regs->rctrl, tempval);
2330
2331                 gfar_check_rx_parser_mode(priv);
2332         }
2333
2334         gfar_change_mtu(dev, dev->mtu);
2335
2336         unlock_rx_qs(priv);
2337         local_irq_restore(flags);
2338 }
2339
2340 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
2341 {
2342         int tempsize, tempval;
2343         struct gfar_private *priv = netdev_priv(dev);
2344         struct gfar __iomem *regs = priv->gfargrp[0].regs;
2345         int oldsize = priv->rx_buffer_size;
2346         int frame_size = new_mtu + ETH_HLEN;
2347
2348         if (gfar_is_vlan_on(priv))
2349                 frame_size += VLAN_HLEN;
2350
2351         if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
2352                 netif_err(priv, drv, dev, "Invalid MTU setting\n");
2353                 return -EINVAL;
2354         }
2355
2356         if (gfar_uses_fcb(priv))
2357                 frame_size += GMAC_FCB_LEN;
2358
2359         frame_size += priv->padding;
2360
2361         tempsize =
2362             (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
2363             INCREMENTAL_BUFFER_SIZE;
2364
2365         /* Only stop and start the controller if it isn't already
2366          * stopped, and we changed something */
2367         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2368                 stop_gfar(dev);
2369
2370         priv->rx_buffer_size = tempsize;
2371
2372         dev->mtu = new_mtu;
2373
2374         gfar_write(&regs->mrblr, priv->rx_buffer_size);
2375         gfar_write(&regs->maxfrm, priv->rx_buffer_size);
2376
2377         /* If the mtu is larger than the max size for standard
2378          * ethernet frames (ie, a jumbo frame), then set maccfg2
2379          * to allow huge frames, and to check the length */
2380         tempval = gfar_read(&regs->maccfg2);
2381
2382         if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE ||
2383                         gfar_has_errata(priv, GFAR_ERRATA_74))
2384                 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2385         else
2386                 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
2387
2388         gfar_write(&regs->maccfg2, tempval);
2389
2390         if ((oldsize != tempsize) && (dev->flags & IFF_UP))
2391                 startup_gfar(dev);
2392
2393         return 0;
2394 }
2395
2396 /* gfar_reset_task gets scheduled when a packet has not been
2397  * transmitted after a set amount of time.
2398  * For now, assume that clearing out all the structures, and
2399  * starting over will fix the problem.
2400  */
2401 static void gfar_reset_task(struct work_struct *work)
2402 {
2403         struct gfar_private *priv = container_of(work, struct gfar_private,
2404                         reset_task);
2405         struct net_device *dev = priv->ndev;
2406
2407         if (dev->flags & IFF_UP) {
2408                 netif_tx_stop_all_queues(dev);
2409                 stop_gfar(dev);
2410                 startup_gfar(dev);
2411                 netif_tx_start_all_queues(dev);
2412         }
2413
2414         netif_tx_schedule_all(dev);
2415 }
2416
2417 static void gfar_timeout(struct net_device *dev)
2418 {
2419         struct gfar_private *priv = netdev_priv(dev);
2420
2421         dev->stats.tx_errors++;
2422         schedule_work(&priv->reset_task);
2423 }
2424
2425 static void gfar_align_skb(struct sk_buff *skb)
2426 {
2427         /* We need the data buffer to be aligned properly.  We will reserve
2428          * as many bytes as needed to align the data properly
2429          */
2430         skb_reserve(skb, RXBUF_ALIGNMENT -
2431                 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1)));
2432 }
2433
2434 /* Interrupt Handler for Transmit complete */
2435 static int gfar_clean_tx_ring(struct gfar_priv_tx_q *tx_queue)
2436 {
2437         struct net_device *dev = tx_queue->dev;
2438         struct netdev_queue *txq;
2439         struct gfar_private *priv = netdev_priv(dev);
2440         struct gfar_priv_rx_q *rx_queue = NULL;
2441         struct txbd8 *bdp, *next = NULL;
2442         struct txbd8 *lbdp = NULL;
2443         struct txbd8 *base = tx_queue->tx_bd_base;
2444         struct sk_buff *skb;
2445         int skb_dirtytx;
2446         int tx_ring_size = tx_queue->tx_ring_size;
2447         int frags = 0, nr_txbds = 0;
2448         int i;
2449         int howmany = 0;
2450         int tqi = tx_queue->qindex;
2451         unsigned int bytes_sent = 0;
2452         u32 lstatus;
2453         size_t buflen;
2454
2455         rx_queue = priv->rx_queue[tqi];
2456         txq = netdev_get_tx_queue(dev, tqi);
2457         bdp = tx_queue->dirty_tx;
2458         skb_dirtytx = tx_queue->skb_dirtytx;
2459
2460         while ((skb = tx_queue->tx_skbuff[skb_dirtytx])) {
2461                 unsigned long flags;
2462
2463                 frags = skb_shinfo(skb)->nr_frags;
2464
2465                 /*
2466                  * When time stamping, one additional TxBD must be freed.
2467                  * Also, we need to dma_unmap_single() the TxPAL.
2468                  */
2469                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))
2470                         nr_txbds = frags + 2;
2471                 else
2472                         nr_txbds = frags + 1;
2473
2474                 lbdp = skip_txbd(bdp, nr_txbds - 1, base, tx_ring_size);
2475
2476                 lstatus = lbdp->lstatus;
2477
2478                 /* Only clean completed frames */
2479                 if ((lstatus & BD_LFLAG(TXBD_READY)) &&
2480                                 (lstatus & BD_LENGTH_MASK))
2481                         break;
2482
2483                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2484                         next = next_txbd(bdp, base, tx_ring_size);
2485                         buflen = next->length + GMAC_FCB_LEN + GMAC_TXPAL_LEN;
2486                 } else
2487                         buflen = bdp->length;
2488
2489                 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
2490                                 buflen, DMA_TO_DEVICE);
2491
2492                 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)) {
2493                         struct skb_shared_hwtstamps shhwtstamps;
2494                         u64 *ns = (u64*) (((u32)skb->data + 0x10) & ~0x7);
2495                         memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2496                         shhwtstamps.hwtstamp = ns_to_ktime(*ns);
2497                         skb_pull(skb, GMAC_FCB_LEN + GMAC_TXPAL_LEN);
2498                         skb_tstamp_tx(skb, &shhwtstamps);
2499                         bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2500                         bdp = next;
2501                 }
2502
2503                 bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2504                 bdp = next_txbd(bdp, base, tx_ring_size);
2505
2506                 for (i = 0; i < frags; i++) {
2507                         dma_unmap_page(&priv->ofdev->dev,
2508                                         bdp->bufPtr,
2509                                         bdp->length,
2510                                         DMA_TO_DEVICE);
2511                         bdp->lstatus &= BD_LFLAG(TXBD_WRAP);
2512                         bdp = next_txbd(bdp, base, tx_ring_size);
2513                 }
2514
2515                 bytes_sent += skb->len;
2516
2517                 /*
2518                  * If there's room in the queue (limit it to rx_buffer_size)
2519                  * we add this skb back into the pool, if it's the right size
2520                  */
2521                 if (skb_queue_len(&priv->rx_recycle) < rx_queue->rx_ring_size &&
2522                                 skb_recycle_check(skb, priv->rx_buffer_size +
2523                                         RXBUF_ALIGNMENT)) {
2524                         gfar_align_skb(skb);
2525                         skb_queue_head(&priv->rx_recycle, skb);
2526                 } else
2527                         dev_kfree_skb_any(skb);
2528
2529                 tx_queue->tx_skbuff[skb_dirtytx] = NULL;
2530
2531                 skb_dirtytx = (skb_dirtytx + 1) &
2532                         TX_RING_MOD_MASK(tx_ring_size);
2533
2534                 howmany++;
2535                 spin_lock_irqsave(&tx_queue->txlock, flags);
2536                 tx_queue->num_txbdfree += nr_txbds;
2537                 spin_unlock_irqrestore(&tx_queue->txlock, flags);
2538         }
2539
2540         /* If we freed a buffer, we can restart transmission, if necessary */
2541         if (netif_tx_queue_stopped(txq) && tx_queue->num_txbdfree)
2542                 netif_wake_subqueue(dev, tqi);
2543
2544         /* Update dirty indicators */
2545         tx_queue->skb_dirtytx = skb_dirtytx;
2546         tx_queue->dirty_tx = bdp;
2547
2548         netdev_tx_completed_queue(txq, howmany, bytes_sent);
2549
2550         return howmany;
2551 }
2552
2553 static void gfar_schedule_cleanup(struct gfar_priv_grp *gfargrp)
2554 {
2555         unsigned long flags;
2556
2557         spin_lock_irqsave(&gfargrp->grplock, flags);
2558         if (napi_schedule_prep(&gfargrp->napi)) {
2559                 gfar_write(&gfargrp->regs->imask, IMASK_RTX_DISABLED);
2560                 __napi_schedule(&gfargrp->napi);
2561         } else {
2562                 /*
2563                  * Clear IEVENT, so interrupts aren't called again
2564                  * because of the packets that have already arrived.
2565                  */
2566                 gfar_write(&gfargrp->regs->ievent, IEVENT_RTX_MASK);
2567         }
2568         spin_unlock_irqrestore(&gfargrp->grplock, flags);
2569
2570 }
2571
2572 /* Interrupt Handler for Transmit complete */
2573 static irqreturn_t gfar_transmit(int irq, void *grp_id)
2574 {
2575         gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2576         return IRQ_HANDLED;
2577 }
2578
2579 static void gfar_new_rxbdp(struct gfar_priv_rx_q *rx_queue, struct rxbd8 *bdp,
2580                 struct sk_buff *skb)
2581 {
2582         struct net_device *dev = rx_queue->dev;
2583         struct gfar_private *priv = netdev_priv(dev);
2584         dma_addr_t buf;
2585
2586         buf = dma_map_single(&priv->ofdev->dev, skb->data,
2587                              priv->rx_buffer_size, DMA_FROM_DEVICE);
2588         gfar_init_rxbdp(rx_queue, bdp, buf);
2589 }
2590
2591 static struct sk_buff * gfar_alloc_skb(struct net_device *dev)
2592 {
2593         struct gfar_private *priv = netdev_priv(dev);
2594         struct sk_buff *skb = NULL;
2595
2596         skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
2597         if (!skb)
2598                 return NULL;
2599
2600         gfar_align_skb(skb);
2601
2602         return skb;
2603 }
2604
2605 struct sk_buff * gfar_new_skb(struct net_device *dev)
2606 {
2607         struct gfar_private *priv = netdev_priv(dev);
2608         struct sk_buff *skb = NULL;
2609
2610         skb = skb_dequeue(&priv->rx_recycle);
2611         if (!skb)
2612                 skb = gfar_alloc_skb(dev);
2613
2614         return skb;
2615 }
2616
2617 static inline void count_errors(unsigned short status, struct net_device *dev)
2618 {
2619         struct gfar_private *priv = netdev_priv(dev);
2620         struct net_device_stats *stats = &dev->stats;
2621         struct gfar_extra_stats *estats = &priv->extra_stats;
2622
2623         /* If the packet was truncated, none of the other errors
2624          * matter */
2625         if (status & RXBD_TRUNCATED) {
2626                 stats->rx_length_errors++;
2627
2628                 estats->rx_trunc++;
2629
2630                 return;
2631         }
2632         /* Count the errors, if there were any */
2633         if (status & (RXBD_LARGE | RXBD_SHORT)) {
2634                 stats->rx_length_errors++;
2635
2636                 if (status & RXBD_LARGE)
2637                         estats->rx_large++;
2638                 else
2639                         estats->rx_short++;
2640         }
2641         if (status & RXBD_NONOCTET) {
2642                 stats->rx_frame_errors++;
2643                 estats->rx_nonoctet++;
2644         }
2645         if (status & RXBD_CRCERR) {
2646                 estats->rx_crcerr++;
2647                 stats->rx_crc_errors++;
2648         }
2649         if (status & RXBD_OVERRUN) {
2650                 estats->rx_overrun++;
2651                 stats->rx_crc_errors++;
2652         }
2653 }
2654
2655 irqreturn_t gfar_receive(int irq, void *grp_id)
2656 {
2657         gfar_schedule_cleanup((struct gfar_priv_grp *)grp_id);
2658         return IRQ_HANDLED;
2659 }
2660
2661 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
2662 {
2663         /* If valid headers were found, and valid sums
2664          * were verified, then we tell the kernel that no
2665          * checksumming is necessary.  Otherwise, it is */
2666         if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
2667                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2668         else
2669                 skb_checksum_none_assert(skb);
2670 }
2671
2672
2673 /* gfar_process_frame() -- handle one incoming packet if skb
2674  * isn't NULL.  */
2675 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
2676                               int amount_pull, struct napi_struct *napi)
2677 {
2678         struct gfar_private *priv = netdev_priv(dev);
2679         struct rxfcb *fcb = NULL;
2680
2681         gro_result_t ret;
2682
2683         /* fcb is at the beginning if exists */
2684         fcb = (struct rxfcb *)skb->data;
2685
2686         /* Remove the FCB from the skb */
2687         /* Remove the padded bytes, if there are any */
2688         if (amount_pull) {
2689                 skb_record_rx_queue(skb, fcb->rq);
2690                 skb_pull(skb, amount_pull);
2691         }
2692
2693         /* Get receive timestamp from the skb */
2694         if (priv->hwts_rx_en) {
2695                 struct skb_shared_hwtstamps *shhwtstamps = skb_hwtstamps(skb);
2696                 u64 *ns = (u64 *) skb->data;
2697                 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2698                 shhwtstamps->hwtstamp = ns_to_ktime(*ns);
2699         }
2700
2701         if (priv->padding)
2702                 skb_pull(skb, priv->padding);
2703
2704         if (dev->features & NETIF_F_RXCSUM)
2705                 gfar_rx_checksum(skb, fcb);
2706
2707         /* Tell the skb what kind of packet this is */
2708         skb->protocol = eth_type_trans(skb, dev);
2709
2710         /*
2711          * There's need to check for NETIF_F_HW_VLAN_RX here.
2712          * Even if vlan rx accel is disabled, on some chips
2713          * RXFCB_VLN is pseudo randomly set.
2714          */
2715         if (dev->features & NETIF_F_HW_VLAN_RX &&
2716             fcb->flags & RXFCB_VLN)
2717                 __vlan_hwaccel_put_tag(skb, fcb->vlctl);
2718
2719         /* Send the packet up the stack */
2720         ret = napi_gro_receive(napi, skb);
2721
2722         if (GRO_DROP == ret)
2723                 priv->extra_stats.kernel_dropped++;
2724
2725         return 0;
2726 }
2727
2728 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
2729  *   until the budget/quota has been reached. Returns the number
2730  *   of frames handled
2731  */
2732 int gfar_clean_rx_ring(struct gfar_priv_rx_q *rx_queue, int rx_work_limit)
2733 {
2734         struct net_device *dev = rx_queue->dev;
2735         struct rxbd8 *bdp, *base;
2736         struct sk_buff *skb;
2737         int pkt_len;
2738         int amount_pull;
2739         int howmany = 0;
2740         struct gfar_private *priv = netdev_priv(dev);
2741
2742         /* Get the first full descriptor */
2743         bdp = rx_queue->cur_rx;
2744         base = rx_queue->rx_bd_base;
2745
2746         amount_pull = (gfar_uses_fcb(priv) ? GMAC_FCB_LEN : 0);
2747
2748         while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
2749                 struct sk_buff *newskb;
2750                 rmb();
2751
2752                 /* Add another skb for the future */
2753                 newskb = gfar_new_skb(dev);
2754
2755                 skb = rx_queue->rx_skbuff[rx_queue->skb_currx];
2756
2757                 dma_unmap_single(&priv->ofdev->dev, bdp->bufPtr,
2758                                 priv->rx_buffer_size, DMA_FROM_DEVICE);
2759
2760                 if (unlikely(!(bdp->status & RXBD_ERR) &&
2761                                 bdp->length > priv->rx_buffer_size))
2762                         bdp->status = RXBD_LARGE;
2763
2764                 /* We drop the frame if we failed to allocate a new buffer */
2765                 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
2766                                  bdp->status & RXBD_ERR)) {
2767                         count_errors(bdp->status, dev);
2768
2769                         if (unlikely(!newskb))
2770                                 newskb = skb;
2771                         else if (skb)
2772                                 skb_queue_head(&priv->rx_recycle, skb);
2773                 } else {
2774                         /* Increment the number of packets */
2775                         rx_queue->stats.rx_packets++;
2776                         howmany++;
2777
2778                         if (likely(skb)) {
2779                                 pkt_len = bdp->length - ETH_FCS_LEN;
2780                                 /* Remove the FCS from the packet length */
2781                                 skb_put(skb, pkt_len);
2782                                 rx_queue->stats.rx_bytes += pkt_len;
2783                                 skb_record_rx_queue(skb, rx_queue->qindex);
2784                                 gfar_process_frame(dev, skb, amount_pull,
2785                                                 &rx_queue->grp->napi);
2786
2787                         } else {
2788                                 netif_warn(priv, rx_err, dev, "Missing skb!\n");
2789                                 rx_queue->stats.rx_dropped++;
2790                                 priv->extra_stats.rx_skbmissing++;
2791                         }
2792
2793                 }
2794
2795                 rx_queue->rx_skbuff[rx_queue->skb_currx] = newskb;
2796
2797                 /* Setup the new bdp */
2798                 gfar_new_rxbdp(rx_queue, bdp, newskb);
2799
2800                 /* Update to the next pointer */
2801                 bdp = next_bd(bdp, base, rx_queue->rx_ring_size);
2802
2803                 /* update to point at the next skb */
2804                 rx_queue->skb_currx =
2805                     (rx_queue->skb_currx + 1) &
2806                     RX_RING_MOD_MASK(rx_queue->rx_ring_size);
2807         }
2808
2809         /* Update the current rxbd pointer to be the next one */
2810         rx_queue->cur_rx = bdp;
2811
2812         return howmany;
2813 }
2814
2815 static int gfar_poll(struct napi_struct *napi, int budget)
2816 {
2817         struct gfar_priv_grp *gfargrp = container_of(napi,
2818                         struct gfar_priv_grp, napi);
2819         struct gfar_private *priv = gfargrp->priv;
2820         struct gfar __iomem *regs = gfargrp->regs;
2821         struct gfar_priv_tx_q *tx_queue = NULL;
2822         struct gfar_priv_rx_q *rx_queue = NULL;
2823         int rx_cleaned = 0, budget_per_queue = 0, rx_cleaned_per_queue = 0;
2824         int tx_cleaned = 0, i, left_over_budget = budget;
2825         unsigned long serviced_queues = 0;
2826         int num_queues = 0;
2827
2828         num_queues = gfargrp->num_rx_queues;
2829         budget_per_queue = budget/num_queues;
2830
2831         /* Clear IEVENT, so interrupts aren't called again
2832          * because of the packets that have already arrived */
2833         gfar_write(&regs->ievent, IEVENT_RTX_MASK);
2834
2835         while (num_queues && left_over_budget) {
2836
2837                 budget_per_queue = left_over_budget/num_queues;
2838                 left_over_budget = 0;
2839
2840                 for_each_set_bit(i, &gfargrp->rx_bit_map, priv->num_rx_queues) {
2841                         if (test_bit(i, &serviced_queues))
2842                                 continue;
2843                         rx_queue = priv->rx_queue[i];
2844                         tx_queue = priv->tx_queue[rx_queue->qindex];
2845
2846                         tx_cleaned += gfar_clean_tx_ring(tx_queue);
2847                         rx_cleaned_per_queue = gfar_clean_rx_ring(rx_queue,
2848                                                         budget_per_queue);
2849                         rx_cleaned += rx_cleaned_per_queue;
2850                         if(rx_cleaned_per_queue < budget_per_queue) {
2851                                 left_over_budget = left_over_budget +
2852                                         (budget_per_queue - rx_cleaned_per_queue);
2853                                 set_bit(i, &serviced_queues);
2854                                 num_queues--;
2855                         }
2856                 }
2857         }
2858
2859         if (tx_cleaned)
2860                 return budget;
2861
2862         if (rx_cleaned < budget) {
2863                 napi_complete(napi);
2864
2865                 /* Clear the halt bit in RSTAT */
2866                 gfar_write(&regs->rstat, gfargrp->rstat);
2867
2868                 gfar_write(&regs->imask, IMASK_DEFAULT);
2869
2870                 /* If we are coalescing interrupts, update the timer */
2871                 /* Otherwise, clear it */
2872                 gfar_configure_coalescing(priv,
2873                                 gfargrp->rx_bit_map, gfargrp->tx_bit_map);
2874         }
2875
2876         return rx_cleaned;
2877 }
2878
2879 #ifdef CONFIG_NET_POLL_CONTROLLER
2880 /*
2881  * Polling 'interrupt' - used by things like netconsole to send skbs
2882  * without having to re-enable interrupts. It's not called while
2883  * the interrupt routine is executing.
2884  */
2885 static void gfar_netpoll(struct net_device *dev)
2886 {
2887         struct gfar_private *priv = netdev_priv(dev);
2888         int i = 0;
2889
2890         /* If the device has multiple interrupts, run tx/rx */
2891         if (priv->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
2892                 for (i = 0; i < priv->num_grps; i++) {
2893                         disable_irq(priv->gfargrp[i].interruptTransmit);
2894                         disable_irq(priv->gfargrp[i].interruptReceive);
2895                         disable_irq(priv->gfargrp[i].interruptError);
2896                         gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2897                                                 &priv->gfargrp[i]);
2898                         enable_irq(priv->gfargrp[i].interruptError);
2899                         enable_irq(priv->gfargrp[i].interruptReceive);
2900                         enable_irq(priv->gfargrp[i].interruptTransmit);
2901                 }
2902         } else {
2903                 for (i = 0; i < priv->num_grps; i++) {
2904                         disable_irq(priv->gfargrp[i].interruptTransmit);
2905                         gfar_interrupt(priv->gfargrp[i].interruptTransmit,
2906                                                 &priv->gfargrp[i]);
2907                         enable_irq(priv->gfargrp[i].interruptTransmit);
2908                 }
2909         }
2910 }
2911 #endif
2912
2913 /* The interrupt handler for devices with one interrupt */
2914 static irqreturn_t gfar_interrupt(int irq, void *grp_id)
2915 {
2916         struct gfar_priv_grp *gfargrp = grp_id;
2917
2918         /* Save ievent for future reference */
2919         u32 events = gfar_read(&gfargrp->regs->ievent);
2920
2921         /* Check for reception */
2922         if (events & IEVENT_RX_MASK)
2923                 gfar_receive(irq, grp_id);
2924
2925         /* Check for transmit completion */
2926         if (events & IEVENT_TX_MASK)
2927                 gfar_transmit(irq, grp_id);
2928
2929         /* Check for errors */
2930         if (events & IEVENT_ERR_MASK)
2931                 gfar_error(irq, grp_id);
2932
2933         return IRQ_HANDLED;
2934 }
2935
2936 /* Called every time the controller might need to be made
2937  * aware of new link state.  The PHY code conveys this
2938  * information through variables in the phydev structure, and this
2939  * function converts those variables into the appropriate
2940  * register values, and can bring down the device if needed.
2941  */
2942 static void adjust_link(struct net_device *dev)
2943 {
2944         struct gfar_private *priv = netdev_priv(dev);
2945         struct gfar __iomem *regs = priv->gfargrp[0].regs;
2946         unsigned long flags;
2947         struct phy_device *phydev = priv->phydev;
2948         int new_state = 0;
2949
2950         local_irq_save(flags);
2951         lock_tx_qs(priv);
2952
2953         if (phydev->link) {
2954                 u32 tempval = gfar_read(&regs->maccfg2);
2955                 u32 ecntrl = gfar_read(&regs->ecntrl);
2956
2957                 /* Now we make sure that we can be in full duplex mode.
2958                  * If not, we operate in half-duplex mode. */
2959                 if (phydev->duplex != priv->oldduplex) {
2960                         new_state = 1;
2961                         if (!(phydev->duplex))
2962                                 tempval &= ~(MACCFG2_FULL_DUPLEX);
2963                         else
2964                                 tempval |= MACCFG2_FULL_DUPLEX;
2965
2966                         priv->oldduplex = phydev->duplex;
2967                 }
2968
2969                 if (phydev->speed != priv->oldspeed) {
2970                         new_state = 1;
2971                         switch (phydev->speed) {
2972                         case 1000:
2973                                 tempval =
2974                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
2975
2976                                 ecntrl &= ~(ECNTRL_R100);
2977                                 break;
2978                         case 100:
2979                         case 10:
2980                                 tempval =
2981                                     ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
2982
2983                                 /* Reduced mode distinguishes
2984                                  * between 10 and 100 */
2985                                 if (phydev->speed == SPEED_100)
2986                                         ecntrl |= ECNTRL_R100;
2987                                 else
2988                                         ecntrl &= ~(ECNTRL_R100);
2989                                 break;
2990                         default:
2991                                 netif_warn(priv, link, dev,
2992                                            "Ack!  Speed (%d) is not 10/100/1000!\n",
2993                                            phydev->speed);
2994                                 break;
2995                         }
2996
2997                         priv->oldspeed = phydev->speed;
2998                 }
2999
3000                 gfar_write(&regs->maccfg2, tempval);
3001                 gfar_write(&regs->ecntrl, ecntrl);
3002
3003                 if (!priv->oldlink) {
3004                         new_state = 1;
3005                         priv->oldlink = 1;
3006                 }
3007         } else if (priv->oldlink) {
3008                 new_state = 1;
3009                 priv->oldlink = 0;
3010                 priv->oldspeed = 0;
3011                 priv->oldduplex = -1;
3012         }
3013
3014         if (new_state && netif_msg_link(priv))
3015                 phy_print_status(phydev);
3016         unlock_tx_qs(priv);
3017         local_irq_restore(flags);
3018 }
3019
3020 /* Update the hash table based on the current list of multicast
3021  * addresses we subscribe to.  Also, change the promiscuity of
3022  * the device based on the flags (this function is called
3023  * whenever dev->flags is changed */
3024 static void gfar_set_multi(struct net_device *dev)
3025 {
3026         struct netdev_hw_addr *ha;
3027         struct gfar_private *priv = netdev_priv(dev);
3028         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3029         u32 tempval;
3030
3031         if (dev->flags & IFF_PROMISC) {
3032                 /* Set RCTRL to PROM */
3033                 tempval = gfar_read(&regs->rctrl);
3034                 tempval |= RCTRL_PROM;
3035                 gfar_write(&regs->rctrl, tempval);
3036         } else {
3037                 /* Set RCTRL to not PROM */
3038                 tempval = gfar_read(&regs->rctrl);
3039                 tempval &= ~(RCTRL_PROM);
3040                 gfar_write(&regs->rctrl, tempval);
3041         }
3042
3043         if (dev->flags & IFF_ALLMULTI) {
3044                 /* Set the hash to rx all multicast frames */
3045                 gfar_write(&regs->igaddr0, 0xffffffff);
3046                 gfar_write(&regs->igaddr1, 0xffffffff);
3047                 gfar_write(&regs->igaddr2, 0xffffffff);
3048                 gfar_write(&regs->igaddr3, 0xffffffff);
3049                 gfar_write(&regs->igaddr4, 0xffffffff);
3050                 gfar_write(&regs->igaddr5, 0xffffffff);
3051                 gfar_write(&regs->igaddr6, 0xffffffff);
3052                 gfar_write(&regs->igaddr7, 0xffffffff);
3053                 gfar_write(&regs->gaddr0, 0xffffffff);
3054                 gfar_write(&regs->gaddr1, 0xffffffff);
3055                 gfar_write(&regs->gaddr2, 0xffffffff);
3056                 gfar_write(&regs->gaddr3, 0xffffffff);
3057                 gfar_write(&regs->gaddr4, 0xffffffff);
3058                 gfar_write(&regs->gaddr5, 0xffffffff);
3059                 gfar_write(&regs->gaddr6, 0xffffffff);
3060                 gfar_write(&regs->gaddr7, 0xffffffff);
3061         } else {
3062                 int em_num;
3063                 int idx;
3064
3065                 /* zero out the hash */
3066                 gfar_write(&regs->igaddr0, 0x0);
3067                 gfar_write(&regs->igaddr1, 0x0);
3068                 gfar_write(&regs->igaddr2, 0x0);
3069                 gfar_write(&regs->igaddr3, 0x0);
3070                 gfar_write(&regs->igaddr4, 0x0);
3071                 gfar_write(&regs->igaddr5, 0x0);
3072                 gfar_write(&regs->igaddr6, 0x0);
3073                 gfar_write(&regs->igaddr7, 0x0);
3074                 gfar_write(&regs->gaddr0, 0x0);
3075                 gfar_write(&regs->gaddr1, 0x0);
3076                 gfar_write(&regs->gaddr2, 0x0);
3077                 gfar_write(&regs->gaddr3, 0x0);
3078                 gfar_write(&regs->gaddr4, 0x0);
3079                 gfar_write(&regs->gaddr5, 0x0);
3080                 gfar_write(&regs->gaddr6, 0x0);
3081                 gfar_write(&regs->gaddr7, 0x0);
3082
3083                 /* If we have extended hash tables, we need to
3084                  * clear the exact match registers to prepare for
3085                  * setting them */
3086                 if (priv->extended_hash) {
3087                         em_num = GFAR_EM_NUM + 1;
3088                         gfar_clear_exact_match(dev);
3089                         idx = 1;
3090                 } else {
3091                         idx = 0;
3092                         em_num = 0;
3093                 }
3094
3095                 if (netdev_mc_empty(dev))
3096                         return;
3097
3098                 /* Parse the list, and set the appropriate bits */
3099                 netdev_for_each_mc_addr(ha, dev) {
3100                         if (idx < em_num) {
3101                                 gfar_set_mac_for_addr(dev, idx, ha->addr);
3102                                 idx++;
3103                         } else
3104                                 gfar_set_hash_for_addr(dev, ha->addr);
3105                 }
3106         }
3107 }
3108
3109
3110 /* Clears each of the exact match registers to zero, so they
3111  * don't interfere with normal reception */
3112 static void gfar_clear_exact_match(struct net_device *dev)
3113 {
3114         int idx;
3115         static const u8 zero_arr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
3116
3117         for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
3118                 gfar_set_mac_for_addr(dev, idx, zero_arr);
3119 }
3120
3121 /* Set the appropriate hash bit for the given addr */
3122 /* The algorithm works like so:
3123  * 1) Take the Destination Address (ie the multicast address), and
3124  * do a CRC on it (little endian), and reverse the bits of the
3125  * result.
3126  * 2) Use the 8 most significant bits as a hash into a 256-entry
3127  * table.  The table is controlled through 8 32-bit registers:
3128  * gaddr0-7.  gaddr0's MSB is entry 0, and gaddr7's LSB is
3129  * gaddr7.  This means that the 3 most significant bits in the
3130  * hash index which gaddr register to use, and the 5 other bits
3131  * indicate which bit (assuming an IBM numbering scheme, which
3132  * for PowerPC (tm) is usually the case) in the register holds
3133  * the entry. */
3134 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
3135 {
3136         u32 tempval;
3137         struct gfar_private *priv = netdev_priv(dev);
3138         u32 result = ether_crc(ETH_ALEN, addr);
3139         int width = priv->hash_width;
3140         u8 whichbit = (result >> (32 - width)) & 0x1f;
3141         u8 whichreg = result >> (32 - width + 5);
3142         u32 value = (1 << (31-whichbit));
3143
3144         tempval = gfar_read(priv->hash_regs[whichreg]);
3145         tempval |= value;
3146         gfar_write(priv->hash_regs[whichreg], tempval);
3147 }
3148
3149
3150 /* There are multiple MAC Address register pairs on some controllers
3151  * This function sets the numth pair to a given address
3152  */
3153 static void gfar_set_mac_for_addr(struct net_device *dev, int num,
3154                                   const u8 *addr)
3155 {
3156         struct gfar_private *priv = netdev_priv(dev);
3157         struct gfar __iomem *regs = priv->gfargrp[0].regs;
3158         int idx;
3159         char tmpbuf[ETH_ALEN];
3160         u32 tempval;
3161         u32 __iomem *macptr = &regs->macstnaddr1;
3162
3163         macptr += num*2;
3164
3165         /* Now copy it into the mac registers backwards, cuz */
3166         /* little endian is silly */
3167         for (idx = 0; idx < ETH_ALEN; idx++)
3168                 tmpbuf[ETH_ALEN - 1 - idx] = addr[idx];
3169
3170         gfar_write(macptr, *((u32 *) (tmpbuf)));
3171
3172         tempval = *((u32 *) (tmpbuf + 4));
3173
3174         gfar_write(macptr+1, tempval);
3175 }
3176
3177 /* GFAR error interrupt handler */
3178 static irqreturn_t gfar_error(int irq, void *grp_id)
3179 {
3180         struct gfar_priv_grp *gfargrp = grp_id;
3181         struct gfar __iomem *regs = gfargrp->regs;
3182         struct gfar_private *priv= gfargrp->priv;
3183         struct net_device *dev = priv->ndev;
3184
3185         /* Save ievent for future reference */
3186         u32 events = gfar_read(&regs->ievent);
3187
3188         /* Clear IEVENT */
3189         gfar_write(&regs->ievent, events & IEVENT_ERR_MASK);
3190
3191         /* Magic Packet is not an error. */
3192         if ((priv->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
3193             (events & IEVENT_MAG))
3194                 events &= ~IEVENT_MAG;
3195
3196         /* Hmm... */
3197         if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
3198                 netdev_dbg(dev, "error interrupt (ievent=0x%08x imask=0x%08x)\n",
3199                            events, gfar_read(&regs->imask));
3200
3201         /* Update the error counters */
3202         if (events & IEVENT_TXE) {
3203                 dev->stats.tx_errors++;
3204
3205                 if (events & IEVENT_LC)
3206                         dev->stats.tx_window_errors++;
3207                 if (events & IEVENT_CRL)
3208                         dev->stats.tx_aborted_errors++;
3209                 if (events & IEVENT_XFUN) {
3210                         unsigned long flags;
3211
3212                         netif_dbg(priv, tx_err, dev,
3213                                   "TX FIFO underrun, packet dropped\n");
3214                         dev->stats.tx_dropped++;
3215                         priv->extra_stats.tx_underrun++;
3216
3217                         local_irq_save(flags);
3218                         lock_tx_qs(priv);
3219
3220                         /* Reactivate the Tx Queues */
3221                         gfar_write(&regs->tstat, gfargrp->tstat);
3222
3223                         unlock_tx_qs(priv);
3224                         local_irq_restore(flags);
3225                 }
3226                 netif_dbg(priv, tx_err, dev, "Transmit Error\n");
3227         }
3228         if (events & IEVENT_BSY) {
3229                 dev->stats.rx_errors++;
3230                 priv->extra_stats.rx_bsy++;
3231
3232                 gfar_receive(irq, grp_id);
3233
3234                 netif_dbg(priv, rx_err, dev, "busy error (rstat: %x)\n",
3235                           gfar_read(&regs->rstat));
3236         }
3237         if (events & IEVENT_BABR) {
3238                 dev->stats.rx_errors++;
3239                 priv->extra_stats.rx_babr++;
3240
3241                 netif_dbg(priv, rx_err, dev, "babbling RX error\n");
3242         }
3243         if (events & IEVENT_EBERR) {
3244                 priv->extra_stats.eberr++;
3245                 netif_dbg(priv, rx_err, dev, "bus error\n");
3246         }
3247         if (events & IEVENT_RXC)
3248                 netif_dbg(priv, rx_status, dev, "control frame\n");
3249
3250         if (events & IEVENT_BABT) {
3251                 priv->extra_stats.tx_babt++;
3252                 netif_dbg(priv, tx_err, dev, "babbling TX error\n");
3253         }
3254         return IRQ_HANDLED;
3255 }
3256
3257 static struct of_device_id gfar_match[] =
3258 {
3259         {
3260                 .type = "network",
3261                 .compatible = "gianfar",
3262         },
3263         {
3264                 .compatible = "fsl,etsec2",
3265         },
3266         {},
3267 };
3268 MODULE_DEVICE_TABLE(of, gfar_match);
3269
3270 /* Structure for a device driver */
3271 static struct platform_driver gfar_driver = {
3272         .driver = {
3273                 .name = "fsl-gianfar",
3274                 .owner = THIS_MODULE,
3275                 .pm = GFAR_PM_OPS,
3276                 .of_match_table = gfar_match,
3277         },
3278         .probe = gfar_probe,
3279         .remove = gfar_remove,
3280 };
3281
3282 module_platform_driver(gfar_driver);