2 * Copyright (c) 2014-2015 Hisilicon Limited.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
10 #include <linux/acpi.h>
11 #include <linux/errno.h>
12 #include <linux/etherdevice.h>
13 #include <linux/init.h>
14 #include <linux/kernel.h>
15 #include <linux/mfd/syscon.h>
16 #include <linux/module.h>
17 #include <linux/mutex.h>
18 #include <linux/netdevice.h>
19 #include <linux/of_address.h>
21 #include <linux/of_mdio.h>
22 #include <linux/of_platform.h>
23 #include <linux/phy.h>
24 #include <linux/platform_device.h>
25 #include <linux/regmap.h>
26 #include <linux/spinlock_types.h>
28 #define MDIO_DRV_NAME "Hi-HNS_MDIO"
29 #define MDIO_BUS_NAME "Hisilicon MII Bus"
30 #define MDIO_DRV_VERSION "1.3.0"
31 #define MDIO_COPYRIGHT "Copyright(c) 2015 Huawei Corporation."
32 #define MDIO_DRV_STRING MDIO_BUS_NAME
33 #define MDIO_DEFAULT_DEVICE_DESCR MDIO_BUS_NAME
35 #define MDIO_CTL_DEV_ADDR(x) (x & 0x1f)
36 #define MDIO_CTL_PORT_ADDR(x) ((x & 0x1f) << 5)
38 #define MDIO_TIMEOUT 1000000
40 struct hns_mdio_sc_reg {
49 struct hns_mdio_device {
50 void *vbase; /* mdio reg base address */
51 struct regmap *subctrl_vbase;
52 struct hns_mdio_sc_reg sc_reg;
56 #define MDIO_COMMAND_REG 0x0
57 #define MDIO_ADDR_REG 0x4
58 #define MDIO_WDATA_REG 0x8
59 #define MDIO_RDATA_REG 0xc
60 #define MDIO_STA_REG 0x10
63 #define MDIO_CMD_DEVAD_M 0x1f
64 #define MDIO_CMD_DEVAD_S 0
65 #define MDIO_CMD_PRTAD_M 0x1f
66 #define MDIO_CMD_PRTAD_S 5
67 #define MDIO_CMD_OP_M 0x3
68 #define MDIO_CMD_OP_S 10
69 #define MDIO_CMD_ST_M 0x3
70 #define MDIO_CMD_ST_S 12
71 #define MDIO_CMD_START_B 14
73 #define MDIO_ADDR_DATA_M 0xffff
74 #define MDIO_ADDR_DATA_S 0
76 #define MDIO_WDATA_DATA_M 0xffff
77 #define MDIO_WDATA_DATA_S 0
79 #define MDIO_RDATA_DATA_M 0xffff
80 #define MDIO_RDATA_DATA_S 0
82 #define MDIO_STATE_STA_B 0
85 MDIO_ST_CLAUSE_45 = 0,
89 enum mdio_c22_op_seq {
94 enum mdio_c45_op_seq {
95 MDIO_C45_WRITE_ADDR = 0,
97 MDIO_C45_READ_INCREMENT,
101 /* peri subctrl reg */
102 #define MDIO_SC_CLK_EN 0x338
103 #define MDIO_SC_CLK_DIS 0x33C
104 #define MDIO_SC_RESET_REQ 0xA38
105 #define MDIO_SC_RESET_DREQ 0xA3C
106 #define MDIO_SC_CLK_ST 0x531C
107 #define MDIO_SC_RESET_ST 0x5A1C
109 static void mdio_write_reg(void *base, u32 reg, u32 value)
111 u8 __iomem *reg_addr = (u8 __iomem *)base;
113 writel_relaxed(value, reg_addr + reg);
116 #define MDIO_WRITE_REG(a, reg, value) \
117 mdio_write_reg((a)->vbase, (reg), (value))
119 static u32 mdio_read_reg(void *base, u32 reg)
121 u8 __iomem *reg_addr = (u8 __iomem *)base;
123 return readl_relaxed(reg_addr + reg);
126 #define mdio_set_field(origin, mask, shift, val) \
128 (origin) &= (~((mask) << (shift))); \
129 (origin) |= (((val) & (mask)) << (shift)); \
132 #define mdio_get_field(origin, mask, shift) (((origin) >> (shift)) & (mask))
134 static void mdio_set_reg_field(void *base, u32 reg, u32 mask, u32 shift,
137 u32 origin = mdio_read_reg(base, reg);
139 mdio_set_field(origin, mask, shift, val);
140 mdio_write_reg(base, reg, origin);
143 #define MDIO_SET_REG_FIELD(dev, reg, mask, shift, val) \
144 mdio_set_reg_field((dev)->vbase, (reg), (mask), (shift), (val))
146 static u32 mdio_get_reg_field(void *base, u32 reg, u32 mask, u32 shift)
150 origin = mdio_read_reg(base, reg);
151 return mdio_get_field(origin, mask, shift);
154 #define MDIO_GET_REG_FIELD(dev, reg, mask, shift) \
155 mdio_get_reg_field((dev)->vbase, (reg), (mask), (shift))
157 #define MDIO_GET_REG_BIT(dev, reg, bit) \
158 mdio_get_reg_field((dev)->vbase, (reg), 0x1ull, (bit))
160 #define MDIO_CHECK_SET_ST 1
161 #define MDIO_CHECK_CLR_ST 0
163 static int mdio_sc_cfg_reg_write(struct hns_mdio_device *mdio_dev,
164 u32 cfg_reg, u32 set_val,
165 u32 st_reg, u32 st_msk, u8 check_st)
170 regmap_write(mdio_dev->subctrl_vbase, cfg_reg, set_val);
172 for (time_cnt = MDIO_TIMEOUT; time_cnt; time_cnt--) {
173 regmap_read(mdio_dev->subctrl_vbase, st_reg, ®_value);
175 if ((!!check_st) == (!!reg_value))
179 if ((!!check_st) != (!!reg_value))
185 static int hns_mdio_wait_ready(struct mii_bus *bus)
187 struct hns_mdio_device *mdio_dev = bus->priv;
189 u32 cmd_reg_value = 1;
191 /* waitting for MDIO_COMMAND_REG 's mdio_start==0 */
192 /* after that can do read or write*/
193 for (i = 0; cmd_reg_value; i++) {
194 cmd_reg_value = MDIO_GET_REG_BIT(mdio_dev,
197 if (i == MDIO_TIMEOUT)
204 static void hns_mdio_cmd_write(struct hns_mdio_device *mdio_dev,
205 u8 is_c45, u8 op, u8 phy_id, u16 cmd)
208 u8 st = is_c45 ? MDIO_ST_CLAUSE_45 : MDIO_ST_CLAUSE_22;
210 cmd_reg_value = st << MDIO_CMD_ST_S;
211 cmd_reg_value |= op << MDIO_CMD_OP_S;
213 (phy_id & MDIO_CMD_PRTAD_M) << MDIO_CMD_PRTAD_S;
214 cmd_reg_value |= (cmd & MDIO_CMD_DEVAD_M) << MDIO_CMD_DEVAD_S;
215 cmd_reg_value |= 1 << MDIO_CMD_START_B;
217 MDIO_WRITE_REG(mdio_dev, MDIO_COMMAND_REG, cmd_reg_value);
221 * hns_mdio_write - access phy register
224 * @regnum: register num
225 * @value: register value
227 * Return 0 on success, negative on failure
229 static int hns_mdio_write(struct mii_bus *bus,
230 int phy_id, int regnum, u16 data)
233 struct hns_mdio_device *mdio_dev = (struct hns_mdio_device *)bus->priv;
234 u8 devad = ((regnum >> 16) & 0x1f);
235 u8 is_c45 = !!(regnum & MII_ADDR_C45);
236 u16 reg = (u16)(regnum & 0xffff);
240 dev_dbg(&bus->dev, "mdio write %s,base is %p\n",
241 bus->id, mdio_dev->vbase);
242 dev_dbg(&bus->dev, "phy id=%d, is_c45=%d, devad=%d, reg=%#x, write data=%d\n",
243 phy_id, is_c45, devad, reg, data);
246 ret = hns_mdio_wait_ready(bus);
248 dev_err(&bus->dev, "MDIO bus is busy\n");
256 /* config the cmd-reg to write addr*/
257 MDIO_SET_REG_FIELD(mdio_dev, MDIO_ADDR_REG, MDIO_ADDR_DATA_M,
258 MDIO_ADDR_DATA_S, reg);
260 hns_mdio_cmd_write(mdio_dev, is_c45,
261 MDIO_C45_WRITE_ADDR, phy_id, devad);
263 /* check for read or write opt is finished */
264 ret = hns_mdio_wait_ready(bus);
266 dev_err(&bus->dev, "MDIO bus is busy\n");
270 /* config the data needed writing */
272 op = MDIO_C45_WRITE_ADDR;
275 MDIO_SET_REG_FIELD(mdio_dev, MDIO_WDATA_REG, MDIO_WDATA_DATA_M,
276 MDIO_WDATA_DATA_S, data);
278 hns_mdio_cmd_write(mdio_dev, is_c45, op, phy_id, cmd_reg_cfg);
284 * hns_mdio_read - access phy register
287 * @regnum: register num
288 * @value: register value
290 * Return phy register value
292 static int hns_mdio_read(struct mii_bus *bus, int phy_id, int regnum)
296 u8 devad = ((regnum >> 16) & 0x1f);
297 u8 is_c45 = !!(regnum & MII_ADDR_C45);
298 u16 reg = (u16)(regnum & 0xffff);
299 struct hns_mdio_device *mdio_dev = (struct hns_mdio_device *)bus->priv;
301 dev_dbg(&bus->dev, "mdio read %s,base is %p\n",
302 bus->id, mdio_dev->vbase);
303 dev_dbg(&bus->dev, "phy id=%d, is_c45=%d, devad=%d, reg=%#x!\n",
304 phy_id, is_c45, devad, reg);
306 /* Step 1: wait for ready */
307 ret = hns_mdio_wait_ready(bus);
309 dev_err(&bus->dev, "MDIO bus is busy\n");
314 hns_mdio_cmd_write(mdio_dev, is_c45,
315 MDIO_C22_READ, phy_id, reg);
317 MDIO_SET_REG_FIELD(mdio_dev, MDIO_ADDR_REG, MDIO_ADDR_DATA_M,
318 MDIO_ADDR_DATA_S, reg);
320 /* Step 2; config the cmd-reg to write addr*/
321 hns_mdio_cmd_write(mdio_dev, is_c45,
322 MDIO_C45_WRITE_ADDR, phy_id, devad);
324 /* Step 3: check for read or write opt is finished */
325 ret = hns_mdio_wait_ready(bus);
327 dev_err(&bus->dev, "MDIO bus is busy\n");
331 hns_mdio_cmd_write(mdio_dev, is_c45,
332 MDIO_C45_WRITE_ADDR, phy_id, devad);
335 /* Step 5: waitting for MDIO_COMMAND_REG 's mdio_start==0,*/
336 /* check for read or write opt is finished */
337 ret = hns_mdio_wait_ready(bus);
339 dev_err(&bus->dev, "MDIO bus is busy\n");
343 reg_val = MDIO_GET_REG_BIT(mdio_dev, MDIO_STA_REG, MDIO_STATE_STA_B);
345 dev_err(&bus->dev, " ERROR! MDIO Read failed!\n");
349 /* Step 6; get out data*/
350 reg_val = (u16)MDIO_GET_REG_FIELD(mdio_dev, MDIO_RDATA_REG,
351 MDIO_RDATA_DATA_M, MDIO_RDATA_DATA_S);
357 * hns_mdio_reset - reset mdio bus
360 * Return 0 on success, negative on failure
362 static int hns_mdio_reset(struct mii_bus *bus)
364 struct hns_mdio_device *mdio_dev = (struct hns_mdio_device *)bus->priv;
365 const struct hns_mdio_sc_reg *sc_reg;
368 if (dev_of_node(bus->parent)) {
369 if (!mdio_dev->subctrl_vbase) {
370 dev_err(&bus->dev, "mdio sys ctl reg has not maped\n");
374 sc_reg = &mdio_dev->sc_reg;
375 /* 1. reset req, and read reset st check */
376 ret = mdio_sc_cfg_reg_write(mdio_dev, sc_reg->mdio_reset_req,
377 0x1, sc_reg->mdio_reset_st, 0x1,
380 dev_err(&bus->dev, "MDIO reset fail\n");
384 /* 2. dis clk, and read clk st check */
385 ret = mdio_sc_cfg_reg_write(mdio_dev, sc_reg->mdio_clk_dis,
386 0x1, sc_reg->mdio_clk_st, 0x1,
389 dev_err(&bus->dev, "MDIO dis clk fail\n");
393 /* 3. reset dreq, and read reset st check */
394 ret = mdio_sc_cfg_reg_write(mdio_dev, sc_reg->mdio_reset_dreq,
395 0x1, sc_reg->mdio_reset_st, 0x1,
398 dev_err(&bus->dev, "MDIO dis clk fail\n");
402 /* 4. en clk, and read clk st check */
403 ret = mdio_sc_cfg_reg_write(mdio_dev, sc_reg->mdio_clk_en,
404 0x1, sc_reg->mdio_clk_st, 0x1,
407 dev_err(&bus->dev, "MDIO en clk fail\n");
408 } else if (is_acpi_node(bus->parent->fwnode)) {
411 s = acpi_evaluate_object(ACPI_HANDLE(bus->parent),
413 if (ACPI_FAILURE(s)) {
414 dev_err(&bus->dev, "Reset failed, return:%#x\n", s);
420 dev_err(&bus->dev, "Can not get cfg data from DT or ACPI\n");
427 * hns_mdio_probe - probe mdio device
428 * @pdev: mdio platform device
430 * Return 0 on success, negative on failure
432 static int hns_mdio_probe(struct platform_device *pdev)
434 struct hns_mdio_device *mdio_dev;
435 struct mii_bus *new_bus;
436 struct resource *res;
440 dev_err(NULL, "pdev is NULL!\r\n");
444 mdio_dev = devm_kzalloc(&pdev->dev, sizeof(*mdio_dev), GFP_KERNEL);
448 new_bus = devm_mdiobus_alloc(&pdev->dev);
450 dev_err(&pdev->dev, "mdiobus_alloc fail!\n");
454 new_bus->name = MDIO_BUS_NAME;
455 new_bus->read = hns_mdio_read;
456 new_bus->write = hns_mdio_write;
457 new_bus->reset = hns_mdio_reset;
458 new_bus->priv = mdio_dev;
459 new_bus->parent = &pdev->dev;
461 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
462 mdio_dev->vbase = devm_ioremap_resource(&pdev->dev, res);
463 if (IS_ERR(mdio_dev->vbase)) {
464 ret = PTR_ERR(mdio_dev->vbase);
468 platform_set_drvdata(pdev, new_bus);
469 snprintf(new_bus->id, MII_BUS_ID_SIZE, "%s-%s", "Mii",
470 dev_name(&pdev->dev));
471 if (dev_of_node(&pdev->dev)) {
472 struct of_phandle_args reg_args;
474 ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
480 mdio_dev->subctrl_vbase =
481 syscon_node_to_regmap(reg_args.np);
482 if (IS_ERR(mdio_dev->subctrl_vbase)) {
483 dev_warn(&pdev->dev, "syscon_node_to_regmap error\n");
484 mdio_dev->subctrl_vbase = NULL;
486 if (reg_args.args_count == 4) {
487 mdio_dev->sc_reg.mdio_clk_en =
488 (u16)reg_args.args[0];
489 mdio_dev->sc_reg.mdio_clk_dis =
490 (u16)reg_args.args[0] + 4;
491 mdio_dev->sc_reg.mdio_reset_req =
492 (u16)reg_args.args[1];
493 mdio_dev->sc_reg.mdio_reset_dreq =
494 (u16)reg_args.args[1] + 4;
495 mdio_dev->sc_reg.mdio_clk_st =
496 (u16)reg_args.args[2];
497 mdio_dev->sc_reg.mdio_reset_st =
498 (u16)reg_args.args[3];
501 mdio_dev->sc_reg.mdio_clk_en =
503 mdio_dev->sc_reg.mdio_clk_dis =
505 mdio_dev->sc_reg.mdio_reset_req =
507 mdio_dev->sc_reg.mdio_reset_dreq =
509 mdio_dev->sc_reg.mdio_clk_st =
511 mdio_dev->sc_reg.mdio_reset_st =
516 dev_warn(&pdev->dev, "find syscon ret = %#x\n", ret);
517 mdio_dev->subctrl_vbase = NULL;
520 ret = of_mdiobus_register(new_bus, pdev->dev.of_node);
521 } else if (is_acpi_node(pdev->dev.fwnode)) {
522 /* Clear all the IRQ properties */
523 memset(new_bus->irq, PHY_POLL, 4 * PHY_MAX_ADDR);
525 /* Mask out all PHYs from auto probing. */
526 new_bus->phy_mask = ~0;
528 /* Register the MDIO bus */
529 ret = mdiobus_register(new_bus);
531 dev_err(&pdev->dev, "Can not get cfg data from DT or ACPI\n");
536 dev_err(&pdev->dev, "Cannot register as MDIO bus!\n");
537 platform_set_drvdata(pdev, NULL);
545 * hns_mdio_remove - remove mdio device
546 * @pdev: mdio platform device
548 * Return 0 on success, negative on failure
550 static int hns_mdio_remove(struct platform_device *pdev)
554 bus = platform_get_drvdata(pdev);
556 mdiobus_unregister(bus);
557 platform_set_drvdata(pdev, NULL);
561 static const struct of_device_id hns_mdio_match[] = {
562 {.compatible = "hisilicon,mdio"},
563 {.compatible = "hisilicon,hns-mdio"},
567 static const struct acpi_device_id hns_mdio_acpi_match[] = {
571 MODULE_DEVICE_TABLE(acpi, hns_mdio_acpi_match);
573 static struct platform_driver hns_mdio_driver = {
574 .probe = hns_mdio_probe,
575 .remove = hns_mdio_remove,
577 .name = MDIO_DRV_NAME,
578 .of_match_table = hns_mdio_match,
579 .acpi_match_table = ACPI_PTR(hns_mdio_acpi_match),
583 module_platform_driver(hns_mdio_driver);
585 MODULE_LICENSE("GPL");
586 MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
587 MODULE_DESCRIPTION("Hisilicon HNS MDIO driver");
588 MODULE_ALIAS("platform:" MDIO_DRV_NAME);