drivers/net/ethernet/intel/e1000e/80003es2lan.c

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2013 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 /* 80003ES2LAN Gigabit Ethernet Controller (Copper)
  30  * 80003ES2LAN Gigabit Ethernet Controller (Serdes)
  31  */
  32
  33 #include "e1000.h"
  34
  35 /* A table for the GG82563 cable length where the range is defined
  36  * with a lower bound at "index" and the upper bound at
  37  * "index + 5".
  38  */
  39 static const u16 e1000_gg82563_cable_length_table[] = {
  40         0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF
  41 };
  42
  43 #define GG82563_CABLE_LENGTH_TABLE_SIZE \
  44                 ARRAY_SIZE(e1000_gg82563_cable_length_table)
  45
  46 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);
  47 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
  48 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
  49 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
  50 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);
  51 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);
  52 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);
  53 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
  54                                            u16 *data);
  55 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
  56                                             u16 data);
  57 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw);
  58
  59 /**
  60  *  e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
  61  *  @hw: pointer to the HW structure
  62  **/
  63 static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)
  64 {
  65         struct e1000_phy_info *phy = &hw->phy;
  66         s32 ret_val;
  67
  68         if (hw->phy.media_type != e1000_media_type_copper) {
  69                 phy->type = e1000_phy_none;
  70                 return 0;
  71         } else {
  72                 phy->ops.power_up = e1000_power_up_phy_copper;
  73                 phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan;
  74         }
  75
  76         phy->addr = 1;
  77         phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
  78         phy->reset_delay_us = 100;
  79         phy->type = e1000_phy_gg82563;
  80
  81         /* This can only be done after all function pointers are setup. */
  82         ret_val = e1000e_get_phy_id(hw);
  83
  84         /* Verify phy id */
  85         if (phy->id != GG82563_E_PHY_ID)
  86                 return -E1000_ERR_PHY;
  87
  88         return ret_val;
  89 }
  90
  91 /**
  92  *  e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.
  93  *  @hw: pointer to the HW structure
  94  **/
  95 static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
  96 {
  97         struct e1000_nvm_info *nvm = &hw->nvm;
  98         u32 eecd = er32(EECD);
  99         u16 size;
 100
 101         nvm->opcode_bits = 8;
 102         nvm->delay_usec = 1;
 103         switch (nvm->override) {
 104         case e1000_nvm_override_spi_large:
 105                 nvm->page_size = 32;
 106                 nvm->address_bits = 16;
 107                 break;
 108         case e1000_nvm_override_spi_small:
 109                 nvm->page_size = 8;
 110                 nvm->address_bits = 8;
 111                 break;
 112         default:
 113                 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 114                 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
 115                 break;
 116         }
 117
 118         nvm->type = e1000_nvm_eeprom_spi;
 119
 120         size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
 121                      E1000_EECD_SIZE_EX_SHIFT);
 122
 123         /* Added to a constant, "size" becomes the left-shift value
 124          * for setting word_size.
 125          */
 126         size += NVM_WORD_SIZE_BASE_SHIFT;
 127
 128         /* EEPROM access above 16k is unsupported */
 129         if (size > 14)
 130                 size = 14;
 131         nvm->word_size = 1 << size;
 132
 133         return 0;
 134 }
 135
 136 /**
 137  *  e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.
 138  *  @hw: pointer to the HW structure
 139  **/
 140 static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw)
 141 {
 142         struct e1000_mac_info *mac = &hw->mac;
 143
 144         /* Set media type and media-dependent function pointers */
 145         switch (hw->adapter->pdev->device) {
 146         case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
 147                 hw->phy.media_type = e1000_media_type_internal_serdes;
 148                 mac->ops.check_for_link = e1000e_check_for_serdes_link;
 149                 mac->ops.setup_physical_interface =
 150                     e1000e_setup_fiber_serdes_link;
 151                 break;
 152         default:
 153                 hw->phy.media_type = e1000_media_type_copper;
 154                 mac->ops.check_for_link = e1000e_check_for_copper_link;
 155                 mac->ops.setup_physical_interface =
 156                     e1000_setup_copper_link_80003es2lan;
 157                 break;
 158         }
 159
 160         /* Set mta register count */
 161         mac->mta_reg_count = 128;
 162         /* Set rar entry count */
 163         mac->rar_entry_count = E1000_RAR_ENTRIES;
 164         /* FWSM register */
 165         mac->has_fwsm = true;
 166         /* ARC supported; valid only if manageability features are enabled. */
 167         mac->arc_subsystem_valid = !!(er32(FWSM) & E1000_FWSM_MODE_MASK);
 168         /* Adaptive IFS not supported */
 169         mac->adaptive_ifs = false;
 170
 171         /* set lan id for port to determine which phy lock to use */
 172         hw->mac.ops.set_lan_id(hw);
 173
 174         return 0;
 175 }
 176
 177 static s32 e1000_get_variants_80003es2lan(struct e1000_adapter *adapter)
 178 {
 179         struct e1000_hw *hw = &adapter->hw;
 180         s32 rc;
 181
 182         rc = e1000_init_mac_params_80003es2lan(hw);
 183         if (rc)
 184                 return rc;
 185
 186         rc = e1000_init_nvm_params_80003es2lan(hw);
 187         if (rc)
 188                 return rc;
 189
 190         rc = e1000_init_phy_params_80003es2lan(hw);
 191         if (rc)
 192                 return rc;
 193
 194         return 0;
 195 }
 196
 197 /**
 198  *  e1000_acquire_phy_80003es2lan - Acquire rights to access PHY
 199  *  @hw: pointer to the HW structure
 200  *
 201  *  A wrapper to acquire access rights to the correct PHY.
 202  **/
 203 static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw)
 204 {
 205         u16 mask;
 206
 207         mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
 208         return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
 209 }
 210
 211 /**
 212  *  e1000_release_phy_80003es2lan - Release rights to access PHY
 213  *  @hw: pointer to the HW structure
 214  *
 215  *  A wrapper to release access rights to the correct PHY.
 216  **/
 217 static void e1000_release_phy_80003es2lan(struct e1000_hw *hw)
 218 {
 219         u16 mask;
 220
 221         mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
 222         e1000_release_swfw_sync_80003es2lan(hw, mask);
 223 }
 224
 225 /**
 226  *  e1000_acquire_mac_csr_80003es2lan - Acquire right to access Kumeran register
 227  *  @hw: pointer to the HW structure
 228  *
 229  *  Acquire the semaphore to access the Kumeran interface.
 230  *
 231  **/
 232 static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw)
 233 {
 234         u16 mask;
 235
 236         mask = E1000_SWFW_CSR_SM;
 237
 238         return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
 239 }
 240
 241 /**
 242  *  e1000_release_mac_csr_80003es2lan - Release right to access Kumeran Register
 243  *  @hw: pointer to the HW structure
 244  *
 245  *  Release the semaphore used to access the Kumeran interface
 246  **/
 247 static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw)
 248 {
 249         u16 mask;
 250
 251         mask = E1000_SWFW_CSR_SM;
 252
 253         e1000_release_swfw_sync_80003es2lan(hw, mask);
 254 }
 255
 256 /**
 257  *  e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM
 258  *  @hw: pointer to the HW structure
 259  *
 260  *  Acquire the semaphore to access the EEPROM.
 261  **/
 262 static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw)
 263 {
 264         s32 ret_val;
 265
 266         ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
 267         if (ret_val)
 268                 return ret_val;
 269
 270         ret_val = e1000e_acquire_nvm(hw);
 271
 272         if (ret_val)
 273                 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
 274
 275         return ret_val;
 276 }
 277
 278 /**
 279  *  e1000_release_nvm_80003es2lan - Relinquish rights to access NVM
 280  *  @hw: pointer to the HW structure
 281  *
 282  *  Release the semaphore used to access the EEPROM.
 283  **/
 284 static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw)
 285 {
 286         e1000e_release_nvm(hw);
 287         e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
 288 }
 289
 290 /**
 291  *  e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore
 292  *  @hw: pointer to the HW structure
 293  *  @mask: specifies which semaphore to acquire
 294  *
 295  *  Acquire the SW/FW semaphore to access the PHY or NVM.  The mask
 296  *  will also specify which port we're acquiring the lock for.
 297  **/
 298 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
 299 {
 300         u32 swfw_sync;
 301         u32 swmask = mask;
 302         u32 fwmask = mask << 16;
 303         s32 i = 0;
 304         s32 timeout = 50;
 305
 306         while (i < timeout) {
 307                 if (e1000e_get_hw_semaphore(hw))
 308                         return -E1000_ERR_SWFW_SYNC;
 309
 310                 swfw_sync = er32(SW_FW_SYNC);
 311                 if (!(swfw_sync & (fwmask | swmask)))
 312                         break;
 313
 314                 /* Firmware currently using resource (fwmask)
 315                  * or other software thread using resource (swmask)
 316                  */
 317                 e1000e_put_hw_semaphore(hw);
 318                 mdelay(5);
 319                 i++;
 320         }
 321
 322         if (i == timeout) {
 323                 e_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
 324                 return -E1000_ERR_SWFW_SYNC;
 325         }
 326
 327         swfw_sync |= swmask;
 328         ew32(SW_FW_SYNC, swfw_sync);
 329
 330         e1000e_put_hw_semaphore(hw);
 331
 332         return 0;
 333 }
 334
 335 /**
 336  *  e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore
 337  *  @hw: pointer to the HW structure
 338  *  @mask: specifies which semaphore to acquire
 339  *
 340  *  Release the SW/FW semaphore used to access the PHY or NVM.  The mask
 341  *  will also specify which port we're releasing the lock for.
 342  **/
 343 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
 344 {
 345         u32 swfw_sync;
 346
 347         while (e1000e_get_hw_semaphore(hw) != 0)
 348                 ; /* Empty */
 349
 350         swfw_sync = er32(SW_FW_SYNC);
 351         swfw_sync &= ~mask;
 352         ew32(SW_FW_SYNC, swfw_sync);
 353
 354         e1000e_put_hw_semaphore(hw);
 355 }
 356
 357 /**
 358  *  e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register
 359  *  @hw: pointer to the HW structure
 360  *  @offset: offset of the register to read
 361  *  @data: pointer to the data returned from the operation
 362  *
 363  *  Read the GG82563 PHY register.
 364  **/
 365 static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
 366                                                   u32 offset, u16 *data)
 367 {
 368         s32 ret_val;
 369         u32 page_select;
 370         u16 temp;
 371
 372         ret_val = e1000_acquire_phy_80003es2lan(hw);
 373         if (ret_val)
 374                 return ret_val;
 375
 376         /* Select Configuration Page */
 377         if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
 378                 page_select = GG82563_PHY_PAGE_SELECT;
 379         } else {
 380                 /* Use Alternative Page Select register to access
 381                  * registers 30 and 31
 382                  */
 383                 page_select = GG82563_PHY_PAGE_SELECT_ALT;
 384         }
 385
 386         temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
 387         ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
 388         if (ret_val) {
 389                 e1000_release_phy_80003es2lan(hw);
 390                 return ret_val;
 391         }
 392
 393         if (hw->dev_spec.e80003es2lan.mdic_wa_enable) {
 394                 /* The "ready" bit in the MDIC register may be incorrectly set
 395                  * before the device has completed the "Page Select" MDI
 396                  * transaction.  So we wait 200us after each MDI command...
 397                  */
 398                 usleep_range(200, 400);
 399
 400                 /* ...and verify the command was successful. */
 401                 ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
 402
 403                 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
 404                         e1000_release_phy_80003es2lan(hw);
 405                         return -E1000_ERR_PHY;
 406                 }
 407
 408                 usleep_range(200, 400);
 409
 410                 ret_val = e1000e_read_phy_reg_mdic(hw,
 411                                                    MAX_PHY_REG_ADDRESS & offset,
 412                                                    data);
 413
 414                 usleep_range(200, 400);
 415         } else {
 416                 ret_val = e1000e_read_phy_reg_mdic(hw,
 417                                                    MAX_PHY_REG_ADDRESS & offset,
 418                                                    data);
 419         }
 420
 421         e1000_release_phy_80003es2lan(hw);
 422
 423         return ret_val;
 424 }
 425
 426 /**
 427  *  e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register
 428  *  @hw: pointer to the HW structure
 429  *  @offset: offset of the register to read
 430  *  @data: value to write to the register
 431  *
 432  *  Write to the GG82563 PHY register.
 433  **/
 434 static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
 435                                                    u32 offset, u16 data)
 436 {
 437         s32 ret_val;
 438         u32 page_select;
 439         u16 temp;
 440
 441         ret_val = e1000_acquire_phy_80003es2lan(hw);
 442         if (ret_val)
 443                 return ret_val;
 444
 445         /* Select Configuration Page */
 446         if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
 447                 page_select = GG82563_PHY_PAGE_SELECT;
 448         } else {
 449                 /* Use Alternative Page Select register to access
 450                  * registers 30 and 31
 451                  */
 452                 page_select = GG82563_PHY_PAGE_SELECT_ALT;
 453         }
 454
 455         temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
 456         ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
 457         if (ret_val) {
 458                 e1000_release_phy_80003es2lan(hw);
 459                 return ret_val;
 460         }
 461
 462         if (hw->dev_spec.e80003es2lan.mdic_wa_enable) {
 463                 /* The "ready" bit in the MDIC register may be incorrectly set
 464                  * before the device has completed the "Page Select" MDI
 465                  * transaction.  So we wait 200us after each MDI command...
 466                  */
 467                 usleep_range(200, 400);
 468
 469                 /* ...and verify the command was successful. */
 470                 ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
 471
 472                 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
 473                         e1000_release_phy_80003es2lan(hw);
 474                         return -E1000_ERR_PHY;
 475                 }
 476
 477                 usleep_range(200, 400);
 478
 479                 ret_val = e1000e_write_phy_reg_mdic(hw,
 480                                                     MAX_PHY_REG_ADDRESS &
 481                                                     offset, data);
 482
 483                 usleep_range(200, 400);
 484         } else {
 485                 ret_val = e1000e_write_phy_reg_mdic(hw,
 486                                                     MAX_PHY_REG_ADDRESS &
 487                                                     offset, data);
 488         }
 489
 490         e1000_release_phy_80003es2lan(hw);
 491
 492         return ret_val;
 493 }
 494
 495 /**
 496  *  e1000_write_nvm_80003es2lan - Write to ESB2 NVM
 497  *  @hw: pointer to the HW structure
 498  *  @offset: offset of the register to read
 499  *  @words: number of words to write
 500  *  @data: buffer of data to write to the NVM
 501  *
 502  *  Write "words" of data to the ESB2 NVM.
 503  **/
 504 static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
 505                                        u16 words, u16 *data)
 506 {
 507         return e1000e_write_nvm_spi(hw, offset, words, data);
 508 }
 509
 510 /**
 511  *  e1000_get_cfg_done_80003es2lan - Wait for configuration to complete
 512  *  @hw: pointer to the HW structure
 513  *
 514  *  Wait a specific amount of time for manageability processes to complete.
 515  *  This is a function pointer entry point called by the phy module.
 516  **/
 517 static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw)
 518 {
 519         s32 timeout = PHY_CFG_TIMEOUT;
 520         u32 mask = E1000_NVM_CFG_DONE_PORT_0;
 521
 522         if (hw->bus.func == 1)
 523                 mask = E1000_NVM_CFG_DONE_PORT_1;
 524
 525         while (timeout) {
 526                 if (er32(EEMNGCTL) & mask)
 527                         break;
 528                 usleep_range(1000, 2000);
 529                 timeout--;
 530         }
 531         if (!timeout) {
 532                 e_dbg("MNG configuration cycle has not completed.\n");
 533                 return -E1000_ERR_RESET;
 534         }
 535
 536         return 0;
 537 }
 538
 539 /**
 540  *  e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex
 541  *  @hw: pointer to the HW structure
 542  *
 543  *  Force the speed and duplex settings onto the PHY.  This is a
 544  *  function pointer entry point called by the phy module.
 545  **/
 546 static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
 547 {
 548         s32 ret_val;
 549         u16 phy_data;
 550         bool link;
 551
 552         /* Clear Auto-Crossover to force MDI manually.  M88E1000 requires MDI
 553          * forced whenever speed and duplex are forced.
 554          */
 555         ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
 556         if (ret_val)
 557                 return ret_val;
 558
 559         phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO;
 560         ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, phy_data);
 561         if (ret_val)
 562                 return ret_val;
 563
 564         e_dbg("GG82563 PSCR: %X\n", phy_data);
 565
 566         ret_val = e1e_rphy(hw, MII_BMCR, &phy_data);
 567         if (ret_val)
 568                 return ret_val;
 569
 570         e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
 571
 572         /* Reset the phy to commit changes. */
 573         phy_data |= BMCR_RESET;
 574
 575         ret_val = e1e_wphy(hw, MII_BMCR, phy_data);
 576         if (ret_val)
 577                 return ret_val;
 578
 579         udelay(1);
 580
 581         if (hw->phy.autoneg_wait_to_complete) {
 582                 e_dbg("Waiting for forced speed/duplex link on GG82563 phy.\n");
 583
 584                 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
 585                                                       100000, &link);
 586                 if (ret_val)
 587                         return ret_val;
 588
 589                 if (!link) {
 590                         /* We didn't get link.
 591                          * Reset the DSP and cross our fingers.
 592                          */
 593                         ret_val = e1000e_phy_reset_dsp(hw);
 594                         if (ret_val)
 595                                 return ret_val;
 596                 }
 597
 598                 /* Try once more */
 599                 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
 600                                                       100000, &link);
 601                 if (ret_val)
 602                         return ret_val;
 603         }
 604
 605         ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
 606         if (ret_val)
 607                 return ret_val;
 608
 609         /* Resetting the phy means we need to verify the TX_CLK corresponds
 610          * to the link speed.  10Mbps -> 2.5MHz, else 25MHz.
 611          */
 612         phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
 613         if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)
 614                 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5;
 615         else
 616                 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25;
 617
 618         /* In addition, we must re-enable CRS on Tx for both half and full
 619          * duplex.
 620          */
 621         phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
 622         ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
 623
 624         return ret_val;
 625 }
 626
 627 /**
 628  *  e1000_get_cable_length_80003es2lan - Set approximate cable length
 629  *  @hw: pointer to the HW structure
 630  *
 631  *  Find the approximate cable length as measured by the GG82563 PHY.
 632  *  This is a function pointer entry point called by the phy module.
 633  **/
 634 static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw)
 635 {
 636         struct e1000_phy_info *phy = &hw->phy;
 637         s32 ret_val;
 638         u16 phy_data, index;
 639
 640         ret_val = e1e_rphy(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);
 641         if (ret_val)
 642                 return ret_val;
 643
 644         index = phy_data & GG82563_DSPD_CABLE_LENGTH;
 645
 646         if (index >= GG82563_CABLE_LENGTH_TABLE_SIZE - 5)
 647                 return -E1000_ERR_PHY;
 648
 649         phy->min_cable_length = e1000_gg82563_cable_length_table[index];
 650         phy->max_cable_length = e1000_gg82563_cable_length_table[index + 5];
 651
 652         phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
 653
 654         return 0;
 655 }
 656
 657 /**
 658  *  e1000_get_link_up_info_80003es2lan - Report speed and duplex
 659  *  @hw: pointer to the HW structure
 660  *  @speed: pointer to speed buffer
 661  *  @duplex: pointer to duplex buffer
 662  *
 663  *  Retrieve the current speed and duplex configuration.
 664  **/
 665 static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
 666                                               u16 *duplex)
 667 {
 668         s32 ret_val;
 669
 670         if (hw->phy.media_type == e1000_media_type_copper) {
 671                 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
 672                 hw->phy.ops.cfg_on_link_up(hw);
 673         } else {
 674                 ret_val = e1000e_get_speed_and_duplex_fiber_serdes(hw,
 675                                                                    speed,
 676                                                                    duplex);
 677         }
 678
 679         return ret_val;
 680 }
 681
 682 /**
 683  *  e1000_reset_hw_80003es2lan - Reset the ESB2 controller
 684  *  @hw: pointer to the HW structure
 685  *
 686  *  Perform a global reset to the ESB2 controller.
 687  **/
 688 static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
 689 {
 690         u32 ctrl;
 691         s32 ret_val;
 692         u16 kum_reg_data;
 693
 694         /* Prevent the PCI-E bus from sticking if there is no TLP connection
 695          * on the last TLP read/write transaction when MAC is reset.
 696          */
 697         ret_val = e1000e_disable_pcie_master(hw);
 698         if (ret_val)
 699                 e_dbg("PCI-E Master disable polling has failed.\n");
 700
 701         e_dbg("Masking off all interrupts\n");
 702         ew32(IMC, 0xffffffff);
 703
 704         ew32(RCTL, 0);
 705         ew32(TCTL, E1000_TCTL_PSP);
 706         e1e_flush();
 707
 708         usleep_range(10000, 20000);
 709
 710         ctrl = er32(CTRL);
 711
 712         ret_val = e1000_acquire_phy_80003es2lan(hw);
 713         if (ret_val)
 714                 return ret_val;
 715
 716         e_dbg("Issuing a global reset to MAC\n");
 717         ew32(CTRL, ctrl | E1000_CTRL_RST);
 718         e1000_release_phy_80003es2lan(hw);
 719
 720         /* Disable IBIST slave mode (far-end loopback) */
 721         e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
 722                                         &kum_reg_data);
 723         kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;
 724         e1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
 725                                          kum_reg_data);
 726
 727         ret_val = e1000e_get_auto_rd_done(hw);
 728         if (ret_val)
 729                 /* We don't want to continue accessing MAC registers. */
 730                 return ret_val;
 731
 732         /* Clear any pending interrupt events. */
 733         ew32(IMC, 0xffffffff);
 734         er32(ICR);
 735
 736         return e1000_check_alt_mac_addr_generic(hw);
 737 }
 738
 739 /**
 740  *  e1000_init_hw_80003es2lan - Initialize the ESB2 controller
 741  *  @hw: pointer to the HW structure
 742  *
 743  *  Initialize the hw bits, LED, VFTA, MTA, link and hw counters.
 744  **/
 745 static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
 746 {
 747         struct e1000_mac_info *mac = &hw->mac;
 748         u32 reg_data;
 749         s32 ret_val;
 750         u16 kum_reg_data;
 751         u16 i;
 752
 753         e1000_initialize_hw_bits_80003es2lan(hw);
 754
 755         /* Initialize identification LED */
 756         ret_val = mac->ops.id_led_init(hw);
 757         /* An error is not fatal and we should not stop init due to this */
 758         if (ret_val)
 759                 e_dbg("Error initializing identification LED\n");
 760
 761         /* Disabling VLAN filtering */
 762         e_dbg("Initializing the IEEE VLAN\n");
 763         mac->ops.clear_vfta(hw);
 764
 765         /* Setup the receive address. */
 766         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
 767
 768         /* Zero out the Multicast HASH table */
 769         e_dbg("Zeroing the MTA\n");
 770         for (i = 0; i < mac->mta_reg_count; i++)
 771                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
 772
 773         /* Setup link and flow control */
 774         ret_val = mac->ops.setup_link(hw);
 775         if (ret_val)
 776                 return ret_val;
 777
 778         /* Disable IBIST slave mode (far-end loopback) */
 779         e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
 780                                         &kum_reg_data);
 781         kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;
 782         e1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
 783                                          kum_reg_data);
 784
 785         /* Set the transmit descriptor write-back policy */
 786         reg_data = er32(TXDCTL(0));
 787         reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
 788                     E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);
 789         ew32(TXDCTL(0), reg_data);
 790
 791         /* ...for both queues. */
 792         reg_data = er32(TXDCTL(1));
 793         reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
 794                     E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);
 795         ew32(TXDCTL(1), reg_data);
 796
 797         /* Enable retransmit on late collisions */
 798         reg_data = er32(TCTL);
 799         reg_data |= E1000_TCTL_RTLC;
 800         ew32(TCTL, reg_data);
 801
 802         /* Configure Gigabit Carry Extend Padding */
 803         reg_data = er32(TCTL_EXT);
 804         reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
 805         reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN;
 806         ew32(TCTL_EXT, reg_data);
 807
 808         /* Configure Transmit Inter-Packet Gap */
 809         reg_data = er32(TIPG);
 810         reg_data &= ~E1000_TIPG_IPGT_MASK;
 811         reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
 812         ew32(TIPG, reg_data);
 813
 814         reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);
 815         reg_data &= ~0x00100000;
 816         E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
 817
 818         /* default to true to enable the MDIC W/A */
 819         hw->dev_spec.e80003es2lan.mdic_wa_enable = true;
 820
 821         ret_val =
 822             e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_OFFSET >>
 823                                             E1000_KMRNCTRLSTA_OFFSET_SHIFT, &i);
 824         if (!ret_val) {
 825                 if ((i & E1000_KMRNCTRLSTA_OPMODE_MASK) ==
 826                     E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO)
 827                         hw->dev_spec.e80003es2lan.mdic_wa_enable = false;
 828         }
 829
 830         /* Clear all of the statistics registers (clear on read).  It is
 831          * important that we do this after we have tried to establish link
 832          * because the symbol error count will increment wildly if there
 833          * is no link.
 834          */
 835         e1000_clear_hw_cntrs_80003es2lan(hw);
 836
 837         return ret_val;
 838 }
 839
 840 /**
 841  *  e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2
 842  *  @hw: pointer to the HW structure
 843  *
 844  *  Initializes required hardware-dependent bits needed for normal operation.
 845  **/
 846 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)
 847 {
 848         u32 reg;
 849
 850         /* Transmit Descriptor Control 0 */
 851         reg = er32(TXDCTL(0));
 852         reg |= (1 << 22);
 853         ew32(TXDCTL(0), reg);
 854
 855         /* Transmit Descriptor Control 1 */
 856         reg = er32(TXDCTL(1));
 857         reg |= (1 << 22);
 858         ew32(TXDCTL(1), reg);
 859
 860         /* Transmit Arbitration Control 0 */
 861         reg = er32(TARC(0));
 862         reg &= ~(0xF << 27);    /* 30:27 */
 863         if (hw->phy.media_type != e1000_media_type_copper)
 864                 reg &= ~(1 << 20);
 865         ew32(TARC(0), reg);
 866
 867         /* Transmit Arbitration Control 1 */
 868         reg = er32(TARC(1));
 869         if (er32(TCTL) & E1000_TCTL_MULR)
 870                 reg &= ~(1 << 28);
 871         else
 872                 reg |= (1 << 28);
 873         ew32(TARC(1), reg);
 874
 875         /* Disable IPv6 extension header parsing because some malformed
 876          * IPv6 headers can hang the Rx.
 877          */
 878         reg = er32(RFCTL);
 879         reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
 880         ew32(RFCTL, reg);
 881 }
 882
 883 /**
 884  *  e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link
 885  *  @hw: pointer to the HW structure
 886  *
 887  *  Setup some GG82563 PHY registers for obtaining link
 888  **/
 889 static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
 890 {
 891         struct e1000_phy_info *phy = &hw->phy;
 892         s32 ret_val;
 893         u32 reg;
 894         u16 data;
 895
 896         ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &data);
 897         if (ret_val)
 898                 return ret_val;
 899
 900         data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
 901         /* Use 25MHz for both link down and 1000Base-T for Tx clock. */
 902         data |= GG82563_MSCR_TX_CLK_1000MBPS_25;
 903
 904         ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, data);
 905         if (ret_val)
 906                 return ret_val;
 907
 908         /* Options:
 909          *   MDI/MDI-X = 0 (default)
 910          *   0 - Auto for all speeds
 911          *   1 - MDI mode
 912          *   2 - MDI-X mode
 913          *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
 914          */
 915         ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL, &data);
 916         if (ret_val)
 917                 return ret_val;
 918
 919         data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
 920
 921         switch (phy->mdix) {
 922         case 1:
 923                 data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
 924                 break;
 925         case 2:
 926                 data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
 927                 break;
 928         case 0:
 929         default:
 930                 data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
 931                 break;
 932         }
 933
 934         /* Options:
 935          *   disable_polarity_correction = 0 (default)
 936          *       Automatic Correction for Reversed Cable Polarity
 937          *   0 - Disabled
 938          *   1 - Enabled
 939          */
 940         data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
 941         if (phy->disable_polarity_correction)
 942                 data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
 943
 944         ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, data);
 945         if (ret_val)
 946                 return ret_val;
 947
 948         /* SW Reset the PHY so all changes take effect */
 949         ret_val = hw->phy.ops.commit(hw);
 950         if (ret_val) {
 951                 e_dbg("Error Resetting the PHY\n");
 952                 return ret_val;
 953         }
 954
 955         /* Bypass Rx and Tx FIFO's */
 956         reg = E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL;
 957         data = (E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |
 958                 E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);
 959         ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data);
 960         if (ret_val)
 961                 return ret_val;
 962
 963         reg = E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE;
 964         ret_val = e1000_read_kmrn_reg_80003es2lan(hw, reg, &data);
 965         if (ret_val)
 966                 return ret_val;
 967         data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE;
 968         ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data);
 969         if (ret_val)
 970                 return ret_val;
 971
 972         ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL_2, &data);
 973         if (ret_val)
 974                 return ret_val;
 975
 976         data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
 977         ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL_2, data);
 978         if (ret_val)
 979                 return ret_val;
 980
 981         reg = er32(CTRL_EXT);
 982         reg &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
 983         ew32(CTRL_EXT, reg);
 984
 985         ret_val = e1e_rphy(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);
 986         if (ret_val)
 987                 return ret_val;
 988
 989         /* Do not init these registers when the HW is in IAMT mode, since the
 990          * firmware will have already initialized them.  We only initialize
 991          * them if the HW is not in IAMT mode.
 992          */
 993         if (!hw->mac.ops.check_mng_mode(hw)) {
 994                 /* Enable Electrical Idle on the PHY */
 995                 data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
 996                 ret_val = e1e_wphy(hw, GG82563_PHY_PWR_MGMT_CTRL, data);
 997                 if (ret_val)
 998                         return ret_val;
 999
1000                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &data);
1001                 if (ret_val)
1002                         return ret_val;
1003
1004                 data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1005                 ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, data);
1006                 if (ret_val)
1007                         return ret_val;
1008         }
1009
1010         /* Workaround: Disable padding in Kumeran interface in the MAC
1011          * and in the PHY to avoid CRC errors.
1012          */
1013         ret_val = e1e_rphy(hw, GG82563_PHY_INBAND_CTRL, &data);
1014         if (ret_val)
1015                 return ret_val;
1016
1017         data |= GG82563_ICR_DIS_PADDING;
1018         ret_val = e1e_wphy(hw, GG82563_PHY_INBAND_CTRL, data);
1019         if (ret_val)
1020                 return ret_val;
1021
1022         return 0;
1023 }
1024
1025 /**
1026  *  e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2
1027  *  @hw: pointer to the HW structure
1028  *
1029  *  Essentially a wrapper for setting up all things "copper" related.
1030  *  This is a function pointer entry point called by the mac module.
1031  **/
1032 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)
1033 {
1034         u32 ctrl;
1035         s32 ret_val;
1036         u16 reg_data;
1037
1038         ctrl = er32(CTRL);
1039         ctrl |= E1000_CTRL_SLU;
1040         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1041         ew32(CTRL, ctrl);
1042
1043         /* Set the mac to wait the maximum time between each
1044          * iteration and increase the max iterations when
1045          * polling the phy; this fixes erroneous timeouts at 10Mbps.
1046          */
1047         ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4),
1048                                                    0xFFFF);
1049         if (ret_val)
1050                 return ret_val;
1051         ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1052                                                   &reg_data);
1053         if (ret_val)
1054                 return ret_val;
1055         reg_data |= 0x3F;
1056         ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1057                                                    reg_data);
1058         if (ret_val)
1059                 return ret_val;
1060         ret_val =
1061             e1000_read_kmrn_reg_80003es2lan(hw,
1062                                             E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1063                                             &reg_data);
1064         if (ret_val)
1065                 return ret_val;
1066         reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING;
1067         ret_val =
1068             e1000_write_kmrn_reg_80003es2lan(hw,
1069                                              E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1070                                              reg_data);
1071         if (ret_val)
1072                 return ret_val;
1073
1074         ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw);
1075         if (ret_val)
1076                 return ret_val;
1077
1078         return e1000e_setup_copper_link(hw);
1079 }
1080
1081 /**
1082  *  e1000_cfg_on_link_up_80003es2lan - es2 link configuration after link-up
1083  *  @hw: pointer to the HW structure
1084  *  @duplex: current duplex setting
1085  *
1086  *  Configure the KMRN interface by applying last minute quirks for
1087  *  10/100 operation.
1088  **/
1089 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw)
1090 {
1091         s32 ret_val = 0;
1092         u16 speed;
1093         u16 duplex;
1094
1095         if (hw->phy.media_type == e1000_media_type_copper) {
1096                 ret_val = e1000e_get_speed_and_duplex_copper(hw, &speed,
1097                                                              &duplex);
1098                 if (ret_val)
1099                         return ret_val;
1100
1101                 if (speed == SPEED_1000)
1102                         ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw);
1103                 else
1104                         ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex);
1105         }
1106
1107         return ret_val;
1108 }
1109
1110 /**
1111  *  e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation
1112  *  @hw: pointer to the HW structure
1113  *  @duplex: current duplex setting
1114  *
1115  *  Configure the KMRN interface by applying last minute quirks for
1116  *  10/100 operation.
1117  **/
1118 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
1119 {
1120         s32 ret_val;
1121         u32 tipg;
1122         u32 i = 0;
1123         u16 reg_data, reg_data2;
1124
1125         reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT;
1126         ret_val =
1127             e1000_write_kmrn_reg_80003es2lan(hw,
1128                                              E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1129                                              reg_data);
1130         if (ret_val)
1131                 return ret_val;
1132
1133         /* Configure Transmit Inter-Packet Gap */
1134         tipg = er32(TIPG);
1135         tipg &= ~E1000_TIPG_IPGT_MASK;
1136         tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN;
1137         ew32(TIPG, tipg);
1138
1139         do {
1140                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
1141                 if (ret_val)
1142                         return ret_val;
1143
1144                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data2);
1145                 if (ret_val)
1146                         return ret_val;
1147                 i++;
1148         } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1149
1150         if (duplex == HALF_DUPLEX)
1151                 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1152         else
1153                 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1154
1155         return e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1156 }
1157
1158 /**
1159  *  e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation
1160  *  @hw: pointer to the HW structure
1161  *
1162  *  Configure the KMRN interface by applying last minute quirks for
1163  *  gigabit operation.
1164  **/
1165 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
1166 {
1167         s32 ret_val;
1168         u16 reg_data, reg_data2;
1169         u32 tipg;
1170         u32 i = 0;
1171
1172         reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT;
1173         ret_val =
1174             e1000_write_kmrn_reg_80003es2lan(hw,
1175                                              E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1176                                              reg_data);
1177         if (ret_val)
1178                 return ret_val;
1179
1180         /* Configure Transmit Inter-Packet Gap */
1181         tipg = er32(TIPG);
1182         tipg &= ~E1000_TIPG_IPGT_MASK;
1183         tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
1184         ew32(TIPG, tipg);
1185
1186         do {
1187                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
1188                 if (ret_val)
1189                         return ret_val;
1190
1191                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data2);
1192                 if (ret_val)
1193                         return ret_val;
1194                 i++;
1195         } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1196
1197         reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1198
1199         return e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1200 }
1201
1202 /**
1203  *  e1000_read_kmrn_reg_80003es2lan - Read kumeran register
1204  *  @hw: pointer to the HW structure
1205  *  @offset: register offset to be read
1206  *  @data: pointer to the read data
1207  *
1208  *  Acquire semaphore, then read the PHY register at offset
1209  *  using the kumeran interface.  The information retrieved is stored in data.
1210  *  Release the semaphore before exiting.
1211  **/
1212 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1213                                            u16 *data)
1214 {
1215         u32 kmrnctrlsta;
1216         s32 ret_val;
1217
1218         ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1219         if (ret_val)
1220                 return ret_val;
1221
1222         kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1223                        E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
1224         ew32(KMRNCTRLSTA, kmrnctrlsta);
1225         e1e_flush();
1226
1227         udelay(2);
1228
1229         kmrnctrlsta = er32(KMRNCTRLSTA);
1230         *data = (u16)kmrnctrlsta;
1231
1232         e1000_release_mac_csr_80003es2lan(hw);
1233
1234         return ret_val;
1235 }
1236
1237 /**
1238  *  e1000_write_kmrn_reg_80003es2lan - Write kumeran register
1239  *  @hw: pointer to the HW structure
1240  *  @offset: register offset to write to
1241  *  @data: data to write at register offset
1242  *
1243  *  Acquire semaphore, then write the data to PHY register
1244  *  at the offset using the kumeran interface.  Release semaphore
1245  *  before exiting.
1246  **/
1247 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1248                                             u16 data)
1249 {
1250         u32 kmrnctrlsta;
1251         s32 ret_val;
1252
1253         ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1254         if (ret_val)
1255                 return ret_val;
1256
1257         kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1258                        E1000_KMRNCTRLSTA_OFFSET) | data;
1259         ew32(KMRNCTRLSTA, kmrnctrlsta);
1260         e1e_flush();
1261
1262         udelay(2);
1263
1264         e1000_release_mac_csr_80003es2lan(hw);
1265
1266         return ret_val;
1267 }
1268
1269 /**
1270  *  e1000_read_mac_addr_80003es2lan - Read device MAC address
1271  *  @hw: pointer to the HW structure
1272  **/
1273 static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw)
1274 {
1275         s32 ret_val;
1276
1277         /* If there's an alternate MAC address place it in RAR0
1278          * so that it will override the Si installed default perm
1279          * address.
1280          */
1281         ret_val = e1000_check_alt_mac_addr_generic(hw);
1282         if (ret_val)
1283                 return ret_val;
1284
1285         return e1000_read_mac_addr_generic(hw);
1286 }
1287
1288 /**
1289  * e1000_power_down_phy_copper_80003es2lan - Remove link during PHY power down
1290  * @hw: pointer to the HW structure
1291  *
1292  * In the case of a PHY power down to save power, or to turn off link during a
1293  * driver unload, or wake on lan is not enabled, remove the link.
1294  **/
1295 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw)
1296 {
1297         /* If the management interface is not enabled, then power down */
1298         if (!(hw->mac.ops.check_mng_mode(hw) ||
1299               hw->phy.ops.check_reset_block(hw)))
1300                 e1000_power_down_phy_copper(hw);
1301 }
1302
1303 /**
1304  *  e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters
1305  *  @hw: pointer to the HW structure
1306  *
1307  *  Clears the hardware counters by reading the counter registers.
1308  **/
1309 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw)
1310 {
1311         e1000e_clear_hw_cntrs_base(hw);
1312
1313         er32(PRC64);
1314         er32(PRC127);
1315         er32(PRC255);
1316         er32(PRC511);
1317         er32(PRC1023);
1318         er32(PRC1522);
1319         er32(PTC64);
1320         er32(PTC127);
1321         er32(PTC255);
1322         er32(PTC511);
1323         er32(PTC1023);
1324         er32(PTC1522);
1325
1326         er32(ALGNERRC);
1327         er32(RXERRC);
1328         er32(TNCRS);
1329         er32(CEXTERR);
1330         er32(TSCTC);
1331         er32(TSCTFC);
1332
1333         er32(MGTPRC);
1334         er32(MGTPDC);
1335         er32(MGTPTC);
1336
1337         er32(IAC);
1338         er32(ICRXOC);
1339
1340         er32(ICRXPTC);
1341         er32(ICRXATC);
1342         er32(ICTXPTC);
1343         er32(ICTXATC);
1344         er32(ICTXQEC);
1345         er32(ICTXQMTC);
1346         er32(ICRXDMTC);
1347 }
1348
1349 static const struct e1000_mac_operations es2_mac_ops = {
1350         .read_mac_addr          = e1000_read_mac_addr_80003es2lan,
1351         .id_led_init            = e1000e_id_led_init_generic,
1352         .blink_led              = e1000e_blink_led_generic,
1353         .check_mng_mode         = e1000e_check_mng_mode_generic,
1354         /* check_for_link dependent on media type */
1355         .cleanup_led            = e1000e_cleanup_led_generic,
1356         .clear_hw_cntrs         = e1000_clear_hw_cntrs_80003es2lan,
1357         .get_bus_info           = e1000e_get_bus_info_pcie,
1358         .set_lan_id             = e1000_set_lan_id_multi_port_pcie,
1359         .get_link_up_info       = e1000_get_link_up_info_80003es2lan,
1360         .led_on                 = e1000e_led_on_generic,
1361         .led_off                = e1000e_led_off_generic,
1362         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
1363         .write_vfta             = e1000_write_vfta_generic,
1364         .clear_vfta             = e1000_clear_vfta_generic,
1365         .reset_hw               = e1000_reset_hw_80003es2lan,
1366         .init_hw                = e1000_init_hw_80003es2lan,
1367         .setup_link             = e1000e_setup_link_generic,
1368         /* setup_physical_interface dependent on media type */
1369         .setup_led              = e1000e_setup_led_generic,
1370         .config_collision_dist  = e1000e_config_collision_dist_generic,
1371         .rar_set                = e1000e_rar_set_generic,
1372 };
1373
1374 static const struct e1000_phy_operations es2_phy_ops = {
1375         .acquire                = e1000_acquire_phy_80003es2lan,
1376         .check_polarity         = e1000_check_polarity_m88,
1377         .check_reset_block      = e1000e_check_reset_block_generic,
1378         .commit                 = e1000e_phy_sw_reset,
1379         .force_speed_duplex     = e1000_phy_force_speed_duplex_80003es2lan,
1380         .get_cfg_done           = e1000_get_cfg_done_80003es2lan,
1381         .get_cable_length       = e1000_get_cable_length_80003es2lan,
1382         .get_info               = e1000e_get_phy_info_m88,
1383         .read_reg               = e1000_read_phy_reg_gg82563_80003es2lan,
1384         .release                = e1000_release_phy_80003es2lan,
1385         .reset                  = e1000e_phy_hw_reset_generic,
1386         .set_d0_lplu_state      = NULL,
1387         .set_d3_lplu_state      = e1000e_set_d3_lplu_state,
1388         .write_reg              = e1000_write_phy_reg_gg82563_80003es2lan,
1389         .cfg_on_link_up         = e1000_cfg_on_link_up_80003es2lan,
1390 };
1391
1392 static const struct e1000_nvm_operations es2_nvm_ops = {
1393         .acquire                = e1000_acquire_nvm_80003es2lan,
1394         .read                   = e1000e_read_nvm_eerd,
1395         .release                = e1000_release_nvm_80003es2lan,
1396         .reload                 = e1000e_reload_nvm_generic,
1397         .update                 = e1000e_update_nvm_checksum_generic,
1398         .valid_led_default      = e1000e_valid_led_default,
1399         .validate               = e1000e_validate_nvm_checksum_generic,
1400         .write                  = e1000_write_nvm_80003es2lan,
1401 };
1402
1403 const struct e1000_info e1000_es2_info = {
1404         .mac                    = e1000_80003es2lan,
1405         .flags                  = FLAG_HAS_HW_VLAN_FILTER
1406                                   | FLAG_HAS_JUMBO_FRAMES
1407                                   | FLAG_HAS_WOL
1408                                   | FLAG_APME_IN_CTRL3
1409                                   | FLAG_HAS_CTRLEXT_ON_LOAD
1410                                   | FLAG_RX_NEEDS_RESTART /* errata */
1411                                   | FLAG_TARC_SET_BIT_ZERO /* errata */
1412                                   | FLAG_APME_CHECK_PORT_B
1413                                   | FLAG_DISABLE_FC_PAUSE_TIME, /* errata */
1414         .flags2                 = FLAG2_DMA_BURST,
1415         .pba                    = 38,
1416         .max_hw_frame_size      = DEFAULT_JUMBO,
1417         .get_variants           = e1000_get_variants_80003es2lan,
1418         .mac_ops                = &es2_mac_ops,
1419         .phy_ops                = &es2_phy_ops,
1420         .nvm_ops                = &es2_nvm_ops,
1421 };