1 /*******************************************************************************
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 - 2014 Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 ******************************************************************************/
30 #include "i40e_status.h"
31 #include "i40e_osdep.h"
32 #include "i40e_register.h"
33 #include "i40e_adminq.h"
35 #include "i40e_lan_hmc.h"
38 #define I40E_DEV_ID_SFP_XL710 0x1572
39 #define I40E_DEV_ID_QEMU 0x1574
40 #define I40E_DEV_ID_KX_A 0x157F
41 #define I40E_DEV_ID_KX_B 0x1580
42 #define I40E_DEV_ID_KX_C 0x1581
43 #define I40E_DEV_ID_QSFP_A 0x1583
44 #define I40E_DEV_ID_QSFP_B 0x1584
45 #define I40E_DEV_ID_QSFP_C 0x1585
46 #define I40E_DEV_ID_10G_BASE_T 0x1586
47 #define I40E_DEV_ID_VF 0x154C
48 #define I40E_DEV_ID_VF_HV 0x1571
50 #define i40e_is_40G_device(d) ((d) == I40E_DEV_ID_QSFP_A || \
51 (d) == I40E_DEV_ID_QSFP_B || \
52 (d) == I40E_DEV_ID_QSFP_C)
54 /* I40E_MASK is a macro used on 32 bit registers */
55 #define I40E_MASK(mask, shift) (mask << shift)
57 #define I40E_MAX_VSI_QP 16
58 #define I40E_MAX_VF_VSI 3
59 #define I40E_MAX_CHAINED_RX_BUFFERS 5
60 #define I40E_MAX_PF_UDP_OFFLOAD_PORTS 16
62 /* Max default timeout in ms, */
63 #define I40E_MAX_NVM_TIMEOUT 18000
65 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
66 #define I40E_MS_TO_GTIME(time) ((time) * 1000)
68 /* forward declaration */
70 typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
72 /* Data type manipulation macros. */
74 #define I40E_DESC_UNUSED(R) \
75 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
76 (R)->next_to_clean - (R)->next_to_use - 1)
78 /* bitfields for Tx queue mapping in QTX_CTL */
79 #define I40E_QTX_CTL_VF_QUEUE 0x0
80 #define I40E_QTX_CTL_VM_QUEUE 0x1
81 #define I40E_QTX_CTL_PF_QUEUE 0x2
83 /* debug masks - set these bits in hw->debug_mask to control output */
84 enum i40e_debug_mask {
85 I40E_DEBUG_INIT = 0x00000001,
86 I40E_DEBUG_RELEASE = 0x00000002,
88 I40E_DEBUG_LINK = 0x00000010,
89 I40E_DEBUG_PHY = 0x00000020,
90 I40E_DEBUG_HMC = 0x00000040,
91 I40E_DEBUG_NVM = 0x00000080,
92 I40E_DEBUG_LAN = 0x00000100,
93 I40E_DEBUG_FLOW = 0x00000200,
94 I40E_DEBUG_DCB = 0x00000400,
95 I40E_DEBUG_DIAG = 0x00000800,
96 I40E_DEBUG_FD = 0x00001000,
98 I40E_DEBUG_AQ_MESSAGE = 0x01000000,
99 I40E_DEBUG_AQ_DESCRIPTOR = 0x02000000,
100 I40E_DEBUG_AQ_DESC_BUFFER = 0x04000000,
101 I40E_DEBUG_AQ_COMMAND = 0x06000000,
102 I40E_DEBUG_AQ = 0x0F000000,
104 I40E_DEBUG_USER = 0xF0000000,
106 I40E_DEBUG_ALL = 0xFFFFFFFF
109 /* These are structs for managing the hardware information and the operations.
110 * The structures of function pointers are filled out at init time when we
111 * know for sure exactly which hardware we're working with. This gives us the
112 * flexibility of using the same main driver code but adapting to slightly
113 * different hardware needs as new parts are developed. For this architecture,
114 * the Firmware and AdminQ are intended to insulate the driver from most of the
115 * future changes, but these structures will also do part of the job.
118 I40E_MAC_UNKNOWN = 0,
125 enum i40e_media_type {
126 I40E_MEDIA_TYPE_UNKNOWN = 0,
127 I40E_MEDIA_TYPE_FIBER,
128 I40E_MEDIA_TYPE_BASET,
129 I40E_MEDIA_TYPE_BACKPLANE,
132 I40E_MEDIA_TYPE_VIRTUAL
144 enum i40e_set_fc_aq_failures {
145 I40E_SET_FC_AQ_FAIL_NONE = 0,
146 I40E_SET_FC_AQ_FAIL_GET = 1,
147 I40E_SET_FC_AQ_FAIL_SET = 2,
148 I40E_SET_FC_AQ_FAIL_UPDATE = 4,
149 I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
161 I40E_VSI_TYPE_UNKNOWN
164 enum i40e_queue_type {
165 I40E_QUEUE_TYPE_RX = 0,
167 I40E_QUEUE_TYPE_PE_CEQ,
168 I40E_QUEUE_TYPE_UNKNOWN
171 struct i40e_link_status {
172 enum i40e_aq_phy_type phy_type;
173 enum i40e_aq_link_speed link_speed;
179 /* is Link Status Event notification to SW enabled */
186 struct i40e_phy_info {
187 struct i40e_link_status link_info;
188 struct i40e_link_status link_info_old;
189 u32 autoneg_advertised;
193 enum i40e_media_type media_type;
196 #define I40E_HW_CAP_MAX_GPIO 30
197 /* Capabilities of a PF or a VF or the whole device */
198 struct i40e_hw_capabilities {
200 #define I40E_NVM_IMAGE_TYPE_EVB 0x0
201 #define I40E_NVM_IMAGE_TYPE_CLOUD 0x2
202 #define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3
210 bool evb_802_1_qbg; /* Edge Virtual Bridging */
211 bool evb_802_1_qbh; /* Bridge Port Extension */
214 bool iscsi; /* Indicates iSCSI enabled */
220 u32 fd_filters_guaranteed;
221 u32 fd_filters_best_effort;
224 u32 rss_table_entry_width;
225 bool led[I40E_HW_CAP_MAX_GPIO];
226 bool sdp[I40E_HW_CAP_MAX_GPIO];
228 u32 num_flow_director_filters;
235 u32 num_msix_vectors;
236 u32 num_msix_vectors_vf;
246 struct i40e_mac_info {
247 enum i40e_mac_type type;
249 u8 perm_addr[ETH_ALEN];
250 u8 san_addr[ETH_ALEN];
251 u8 port_addr[ETH_ALEN];
255 enum i40e_aq_resources_ids {
256 I40E_NVM_RESOURCE_ID = 1
259 enum i40e_aq_resource_access_type {
260 I40E_RESOURCE_READ = 1,
264 struct i40e_nvm_info {
265 u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
266 u32 timeout; /* [ms] */
267 u16 sr_size; /* Shadow RAM size in words */
268 bool blank_nvm_mode; /* is NVM empty (no FW present)*/
269 u16 version; /* NVM package version */
270 u32 eetrack; /* NVM data version */
273 /* definitions used in NVM update support */
275 enum i40e_nvmupd_cmd {
277 I40E_NVMUPD_READ_CON,
278 I40E_NVMUPD_READ_SNT,
279 I40E_NVMUPD_READ_LCB,
281 I40E_NVMUPD_WRITE_ERA,
282 I40E_NVMUPD_WRITE_CON,
283 I40E_NVMUPD_WRITE_SNT,
284 I40E_NVMUPD_WRITE_LCB,
285 I40E_NVMUPD_WRITE_SA,
286 I40E_NVMUPD_CSUM_CON,
288 I40E_NVMUPD_CSUM_LCB,
291 enum i40e_nvmupd_state {
292 I40E_NVMUPD_STATE_INIT,
293 I40E_NVMUPD_STATE_READING,
294 I40E_NVMUPD_STATE_WRITING
297 /* nvm_access definition and its masks/shifts need to be accessible to
298 * application, core driver, and shared code. Where is the right file?
300 #define I40E_NVM_READ 0xB
301 #define I40E_NVM_WRITE 0xC
303 #define I40E_NVM_MOD_PNT_MASK 0xFF
305 #define I40E_NVM_TRANS_SHIFT 8
306 #define I40E_NVM_TRANS_MASK (0xf << I40E_NVM_TRANS_SHIFT)
307 #define I40E_NVM_CON 0x0
308 #define I40E_NVM_SNT 0x1
309 #define I40E_NVM_LCB 0x2
310 #define I40E_NVM_SA (I40E_NVM_SNT | I40E_NVM_LCB)
311 #define I40E_NVM_ERA 0x4
312 #define I40E_NVM_CSUM 0x8
314 #define I40E_NVM_ADAPT_SHIFT 16
315 #define I40E_NVM_ADAPT_MASK (0xffff << I40E_NVM_ADAPT_SHIFT)
317 #define I40E_NVMUPD_MAX_DATA 4096
318 #define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
320 struct i40e_nvm_access {
323 u32 offset; /* in bytes */
324 u32 data_size; /* in bytes */
330 i40e_bus_type_unknown = 0,
333 i40e_bus_type_pci_express,
334 i40e_bus_type_reserved
338 enum i40e_bus_speed {
339 i40e_bus_speed_unknown = 0,
340 i40e_bus_speed_33 = 33,
341 i40e_bus_speed_66 = 66,
342 i40e_bus_speed_100 = 100,
343 i40e_bus_speed_120 = 120,
344 i40e_bus_speed_133 = 133,
345 i40e_bus_speed_2500 = 2500,
346 i40e_bus_speed_5000 = 5000,
347 i40e_bus_speed_8000 = 8000,
348 i40e_bus_speed_reserved
352 enum i40e_bus_width {
353 i40e_bus_width_unknown = 0,
354 i40e_bus_width_pcie_x1 = 1,
355 i40e_bus_width_pcie_x2 = 2,
356 i40e_bus_width_pcie_x4 = 4,
357 i40e_bus_width_pcie_x8 = 8,
358 i40e_bus_width_32 = 32,
359 i40e_bus_width_64 = 64,
360 i40e_bus_width_reserved
364 struct i40e_bus_info {
365 enum i40e_bus_speed speed;
366 enum i40e_bus_width width;
367 enum i40e_bus_type type;
374 /* Flow control (FC) parameters */
375 struct i40e_fc_info {
376 enum i40e_fc_mode current_mode; /* FC mode in effect */
377 enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
380 #define I40E_MAX_TRAFFIC_CLASS 8
381 #define I40E_MAX_USER_PRIORITY 8
382 #define I40E_DCBX_MAX_APPS 32
383 #define I40E_LLDPDU_SIZE 1500
384 #define I40E_TLV_STATUS_OPER 0x1
385 #define I40E_TLV_STATUS_SYNC 0x2
386 #define I40E_TLV_STATUS_ERR 0x4
387 #define I40E_CEE_OPER_MAX_APPS 3
388 #define I40E_APP_PROTOID_FCOE 0x8906
389 #define I40E_APP_PROTOID_ISCSI 0x0cbc
390 #define I40E_APP_PROTOID_FIP 0x8914
391 #define I40E_APP_SEL_ETHTYPE 0x1
392 #define I40E_APP_SEL_TCPIP 0x2
394 /* CEE or IEEE 802.1Qaz ETS Configuration data */
395 struct i40e_dcb_ets_config {
399 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
400 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
401 u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
404 /* CEE or IEEE 802.1Qaz PFC Configuration data */
405 struct i40e_dcb_pfc_config {
412 /* CEE or IEEE 802.1Qaz Application Priority data */
413 struct i40e_dcb_app_priority_table {
419 struct i40e_dcbx_config {
421 #define I40E_DCBX_MODE_CEE 0x1
422 #define I40E_DCBX_MODE_IEEE 0x2
424 struct i40e_dcb_ets_config etscfg;
425 struct i40e_dcb_ets_config etsrec;
426 struct i40e_dcb_pfc_config pfc;
427 struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];
430 /* Port hardware description */
435 /* subsystem structs */
436 struct i40e_phy_info phy;
437 struct i40e_mac_info mac;
438 struct i40e_bus_info bus;
439 struct i40e_nvm_info nvm;
440 struct i40e_fc_info fc;
445 u16 subsystem_device_id;
446 u16 subsystem_vendor_id;
449 bool adapter_stopped;
451 /* capabilities for entire device and PCI func */
452 struct i40e_hw_capabilities dev_caps;
453 struct i40e_hw_capabilities func_caps;
455 /* Flow Director shared filter space */
456 u16 fdir_shared_filter_count;
458 /* device profile info */
462 /* for multi-function MACs */
467 /* Closest numa node to the device */
470 /* Admin Queue info */
471 struct i40e_adminq_info aq;
473 /* state of nvm update process */
474 enum i40e_nvmupd_state nvmupd_state;
477 struct i40e_hmc_info hmc; /* HMC info struct */
479 /* LLDP/DCBX Status */
483 struct i40e_dcbx_config local_dcbx_config;
484 struct i40e_dcbx_config remote_dcbx_config;
490 static inline bool i40e_is_vf(struct i40e_hw *hw)
492 return hw->mac.type == I40E_MAC_VF;
495 struct i40e_driver_version {
500 u8 driver_string[32];
504 union i40e_16byte_rx_desc {
506 __le64 pkt_addr; /* Packet buffer address */
507 __le64 hdr_addr; /* Header buffer address */
513 __le16 mirroring_status;
519 __le32 rss; /* RSS Hash */
520 __le32 fd_id; /* Flow director filter id */
521 __le32 fcoe_param; /* FCoE DDP Context id */
525 /* ext status/error/pktype/length */
526 __le64 status_error_len;
528 } wb; /* writeback */
531 union i40e_32byte_rx_desc {
533 __le64 pkt_addr; /* Packet buffer address */
534 __le64 hdr_addr; /* Header buffer address */
535 /* bit 0 of hdr_buffer_addr is DD bit */
543 __le16 mirroring_status;
549 __le32 rss; /* RSS Hash */
550 __le32 fcoe_param; /* FCoE DDP Context id */
551 /* Flow director filter id in case of
552 * Programming status desc WB
558 /* status/error/pktype/length */
559 __le64 status_error_len;
562 __le16 ext_status; /* extended status */
569 __le32 flex_bytes_lo;
573 __le32 flex_bytes_hi;
577 } wb; /* writeback */
580 enum i40e_rx_desc_status_bits {
581 /* Note: These are predefined bit offsets */
582 I40E_RX_DESC_STATUS_DD_SHIFT = 0,
583 I40E_RX_DESC_STATUS_EOF_SHIFT = 1,
584 I40E_RX_DESC_STATUS_L2TAG1P_SHIFT = 2,
585 I40E_RX_DESC_STATUS_L3L4P_SHIFT = 3,
586 I40E_RX_DESC_STATUS_CRCP_SHIFT = 4,
587 I40E_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 2 BITS */
588 I40E_RX_DESC_STATUS_TSYNVALID_SHIFT = 7,
589 I40E_RX_DESC_STATUS_PIF_SHIFT = 8,
590 I40E_RX_DESC_STATUS_UMBCAST_SHIFT = 9, /* 2 BITS */
591 I40E_RX_DESC_STATUS_FLM_SHIFT = 11,
592 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT = 12, /* 2 BITS */
593 I40E_RX_DESC_STATUS_LPBK_SHIFT = 14,
594 I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15,
595 I40E_RX_DESC_STATUS_RESERVED_SHIFT = 16, /* 2 BITS */
596 I40E_RX_DESC_STATUS_UDP_0_SHIFT = 18,
597 I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
600 #define I40E_RXD_QW1_STATUS_SHIFT 0
601 #define I40E_RXD_QW1_STATUS_MASK (((1 << I40E_RX_DESC_STATUS_LAST) - 1) \
602 << I40E_RXD_QW1_STATUS_SHIFT)
604 #define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
605 #define I40E_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \
606 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
608 #define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
609 #define I40E_RXD_QW1_STATUS_TSYNVALID_MASK (0x1UL << \
610 I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
612 enum i40e_rx_desc_fltstat_values {
613 I40E_RX_DESC_FLTSTAT_NO_DATA = 0,
614 I40E_RX_DESC_FLTSTAT_RSV_FD_ID = 1, /* 16byte desc? FD_ID : RSV */
615 I40E_RX_DESC_FLTSTAT_RSV = 2,
616 I40E_RX_DESC_FLTSTAT_RSS_HASH = 3,
619 #define I40E_RXD_QW1_ERROR_SHIFT 19
620 #define I40E_RXD_QW1_ERROR_MASK (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
622 enum i40e_rx_desc_error_bits {
623 /* Note: These are predefined bit offsets */
624 I40E_RX_DESC_ERROR_RXE_SHIFT = 0,
625 I40E_RX_DESC_ERROR_RECIPE_SHIFT = 1,
626 I40E_RX_DESC_ERROR_HBO_SHIFT = 2,
627 I40E_RX_DESC_ERROR_L3L4E_SHIFT = 3, /* 3 BITS */
628 I40E_RX_DESC_ERROR_IPE_SHIFT = 3,
629 I40E_RX_DESC_ERROR_L4E_SHIFT = 4,
630 I40E_RX_DESC_ERROR_EIPE_SHIFT = 5,
631 I40E_RX_DESC_ERROR_OVERSIZE_SHIFT = 6,
632 I40E_RX_DESC_ERROR_PPRS_SHIFT = 7
635 enum i40e_rx_desc_error_l3l4e_fcoe_masks {
636 I40E_RX_DESC_ERROR_L3L4E_NONE = 0,
637 I40E_RX_DESC_ERROR_L3L4E_PROT = 1,
638 I40E_RX_DESC_ERROR_L3L4E_FC = 2,
639 I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR = 3,
640 I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN = 4
643 #define I40E_RXD_QW1_PTYPE_SHIFT 30
644 #define I40E_RXD_QW1_PTYPE_MASK (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
646 /* Packet type non-ip values */
647 enum i40e_rx_l2_ptype {
648 I40E_RX_PTYPE_L2_RESERVED = 0,
649 I40E_RX_PTYPE_L2_MAC_PAY2 = 1,
650 I40E_RX_PTYPE_L2_TIMESYNC_PAY2 = 2,
651 I40E_RX_PTYPE_L2_FIP_PAY2 = 3,
652 I40E_RX_PTYPE_L2_OUI_PAY2 = 4,
653 I40E_RX_PTYPE_L2_MACCNTRL_PAY2 = 5,
654 I40E_RX_PTYPE_L2_LLDP_PAY2 = 6,
655 I40E_RX_PTYPE_L2_ECP_PAY2 = 7,
656 I40E_RX_PTYPE_L2_EVB_PAY2 = 8,
657 I40E_RX_PTYPE_L2_QCN_PAY2 = 9,
658 I40E_RX_PTYPE_L2_EAPOL_PAY2 = 10,
659 I40E_RX_PTYPE_L2_ARP = 11,
660 I40E_RX_PTYPE_L2_FCOE_PAY3 = 12,
661 I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3 = 13,
662 I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3 = 14,
663 I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3 = 15,
664 I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA = 16,
665 I40E_RX_PTYPE_L2_FCOE_VFT_PAY3 = 17,
666 I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA = 18,
667 I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY = 19,
668 I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP = 20,
669 I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER = 21,
670 I40E_RX_PTYPE_GRENAT4_MAC_PAY3 = 58,
671 I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4 = 87,
672 I40E_RX_PTYPE_GRENAT6_MAC_PAY3 = 124,
673 I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4 = 153
676 struct i40e_rx_ptype_decoded {
683 u32 tunnel_end_prot:2;
684 u32 tunnel_end_frag:1;
689 enum i40e_rx_ptype_outer_ip {
690 I40E_RX_PTYPE_OUTER_L2 = 0,
691 I40E_RX_PTYPE_OUTER_IP = 1
694 enum i40e_rx_ptype_outer_ip_ver {
695 I40E_RX_PTYPE_OUTER_NONE = 0,
696 I40E_RX_PTYPE_OUTER_IPV4 = 0,
697 I40E_RX_PTYPE_OUTER_IPV6 = 1
700 enum i40e_rx_ptype_outer_fragmented {
701 I40E_RX_PTYPE_NOT_FRAG = 0,
702 I40E_RX_PTYPE_FRAG = 1
705 enum i40e_rx_ptype_tunnel_type {
706 I40E_RX_PTYPE_TUNNEL_NONE = 0,
707 I40E_RX_PTYPE_TUNNEL_IP_IP = 1,
708 I40E_RX_PTYPE_TUNNEL_IP_GRENAT = 2,
709 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3,
710 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
713 enum i40e_rx_ptype_tunnel_end_prot {
714 I40E_RX_PTYPE_TUNNEL_END_NONE = 0,
715 I40E_RX_PTYPE_TUNNEL_END_IPV4 = 1,
716 I40E_RX_PTYPE_TUNNEL_END_IPV6 = 2,
719 enum i40e_rx_ptype_inner_prot {
720 I40E_RX_PTYPE_INNER_PROT_NONE = 0,
721 I40E_RX_PTYPE_INNER_PROT_UDP = 1,
722 I40E_RX_PTYPE_INNER_PROT_TCP = 2,
723 I40E_RX_PTYPE_INNER_PROT_SCTP = 3,
724 I40E_RX_PTYPE_INNER_PROT_ICMP = 4,
725 I40E_RX_PTYPE_INNER_PROT_TIMESYNC = 5
728 enum i40e_rx_ptype_payload_layer {
729 I40E_RX_PTYPE_PAYLOAD_LAYER_NONE = 0,
730 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1,
731 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2,
732 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3,
735 #define I40E_RXD_QW1_LENGTH_PBUF_SHIFT 38
736 #define I40E_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \
737 I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
739 #define I40E_RXD_QW1_LENGTH_HBUF_SHIFT 52
740 #define I40E_RXD_QW1_LENGTH_HBUF_MASK (0x7FFULL << \
741 I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
743 #define I40E_RXD_QW1_LENGTH_SPH_SHIFT 63
744 #define I40E_RXD_QW1_LENGTH_SPH_MASK (0x1ULL << \
745 I40E_RXD_QW1_LENGTH_SPH_SHIFT)
747 enum i40e_rx_desc_ext_status_bits {
748 /* Note: These are predefined bit offsets */
749 I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT = 0,
750 I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT = 1,
751 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT = 2, /* 2 BITS */
752 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT = 4, /* 2 BITS */
753 I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT = 9,
754 I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
755 I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT = 11,
758 enum i40e_rx_desc_pe_status_bits {
759 /* Note: These are predefined bit offsets */
760 I40E_RX_DESC_PE_STATUS_QPID_SHIFT = 0, /* 18 BITS */
761 I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT = 0, /* 16 BITS */
762 I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT = 16, /* 8 BITS */
763 I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT = 24,
764 I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT = 25,
765 I40E_RX_DESC_PE_STATUS_PORTV_SHIFT = 26,
766 I40E_RX_DESC_PE_STATUS_URG_SHIFT = 27,
767 I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT = 28,
768 I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT = 29
771 #define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT 38
772 #define I40E_RX_PROG_STATUS_DESC_LENGTH 0x2000000
774 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2
775 #define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK (0x7UL << \
776 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
778 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT 19
779 #define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK (0x3FUL << \
780 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
782 enum i40e_rx_prog_status_desc_status_bits {
783 /* Note: These are predefined bit offsets */
784 I40E_RX_PROG_STATUS_DESC_DD_SHIFT = 0,
785 I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT = 2 /* 3 BITS */
788 enum i40e_rx_prog_status_desc_prog_id_masks {
789 I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS = 1,
790 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS = 2,
791 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS = 4,
794 enum i40e_rx_prog_status_desc_error_bits {
795 /* Note: These are predefined bit offsets */
796 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT = 0,
797 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT = 1,
798 I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT = 2,
799 I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT = 3
803 struct i40e_tx_desc {
804 __le64 buffer_addr; /* Address of descriptor's data buf */
805 __le64 cmd_type_offset_bsz;
808 #define I40E_TXD_QW1_DTYPE_SHIFT 0
809 #define I40E_TXD_QW1_DTYPE_MASK (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
811 enum i40e_tx_desc_dtype_value {
812 I40E_TX_DESC_DTYPE_DATA = 0x0,
813 I40E_TX_DESC_DTYPE_NOP = 0x1, /* same as Context desc */
814 I40E_TX_DESC_DTYPE_CONTEXT = 0x1,
815 I40E_TX_DESC_DTYPE_FCOE_CTX = 0x2,
816 I40E_TX_DESC_DTYPE_FILTER_PROG = 0x8,
817 I40E_TX_DESC_DTYPE_DDP_CTX = 0x9,
818 I40E_TX_DESC_DTYPE_FLEX_DATA = 0xB,
819 I40E_TX_DESC_DTYPE_FLEX_CTX_1 = 0xC,
820 I40E_TX_DESC_DTYPE_FLEX_CTX_2 = 0xD,
821 I40E_TX_DESC_DTYPE_DESC_DONE = 0xF
824 #define I40E_TXD_QW1_CMD_SHIFT 4
825 #define I40E_TXD_QW1_CMD_MASK (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
827 enum i40e_tx_desc_cmd_bits {
828 I40E_TX_DESC_CMD_EOP = 0x0001,
829 I40E_TX_DESC_CMD_RS = 0x0002,
830 I40E_TX_DESC_CMD_ICRC = 0x0004,
831 I40E_TX_DESC_CMD_IL2TAG1 = 0x0008,
832 I40E_TX_DESC_CMD_DUMMY = 0x0010,
833 I40E_TX_DESC_CMD_IIPT_NONIP = 0x0000, /* 2 BITS */
834 I40E_TX_DESC_CMD_IIPT_IPV6 = 0x0020, /* 2 BITS */
835 I40E_TX_DESC_CMD_IIPT_IPV4 = 0x0040, /* 2 BITS */
836 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, /* 2 BITS */
837 I40E_TX_DESC_CMD_FCOET = 0x0080,
838 I40E_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000, /* 2 BITS */
839 I40E_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, /* 2 BITS */
840 I40E_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, /* 2 BITS */
841 I40E_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, /* 2 BITS */
842 I40E_TX_DESC_CMD_L4T_EOFT_EOF_N = 0x0000, /* 2 BITS */
843 I40E_TX_DESC_CMD_L4T_EOFT_EOF_T = 0x0100, /* 2 BITS */
844 I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI = 0x0200, /* 2 BITS */
845 I40E_TX_DESC_CMD_L4T_EOFT_EOF_A = 0x0300, /* 2 BITS */
848 #define I40E_TXD_QW1_OFFSET_SHIFT 16
849 #define I40E_TXD_QW1_OFFSET_MASK (0x3FFFFULL << \
850 I40E_TXD_QW1_OFFSET_SHIFT)
852 enum i40e_tx_desc_length_fields {
853 /* Note: These are predefined bit offsets */
854 I40E_TX_DESC_LENGTH_MACLEN_SHIFT = 0, /* 7 BITS */
855 I40E_TX_DESC_LENGTH_IPLEN_SHIFT = 7, /* 7 BITS */
856 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT = 14 /* 4 BITS */
859 #define I40E_TXD_QW1_TX_BUF_SZ_SHIFT 34
860 #define I40E_TXD_QW1_TX_BUF_SZ_MASK (0x3FFFULL << \
861 I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
863 #define I40E_TXD_QW1_L2TAG1_SHIFT 48
864 #define I40E_TXD_QW1_L2TAG1_MASK (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
866 /* Context descriptors */
867 struct i40e_tx_context_desc {
868 __le32 tunneling_params;
871 __le64 type_cmd_tso_mss;
874 #define I40E_TXD_CTX_QW1_DTYPE_SHIFT 0
875 #define I40E_TXD_CTX_QW1_DTYPE_MASK (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
877 #define I40E_TXD_CTX_QW1_CMD_SHIFT 4
878 #define I40E_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
880 enum i40e_tx_ctx_desc_cmd_bits {
881 I40E_TX_CTX_DESC_TSO = 0x01,
882 I40E_TX_CTX_DESC_TSYN = 0x02,
883 I40E_TX_CTX_DESC_IL2TAG2 = 0x04,
884 I40E_TX_CTX_DESC_IL2TAG2_IL2H = 0x08,
885 I40E_TX_CTX_DESC_SWTCH_NOTAG = 0x00,
886 I40E_TX_CTX_DESC_SWTCH_UPLINK = 0x10,
887 I40E_TX_CTX_DESC_SWTCH_LOCAL = 0x20,
888 I40E_TX_CTX_DESC_SWTCH_VSI = 0x30,
889 I40E_TX_CTX_DESC_SWPE = 0x40
892 #define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT 30
893 #define I40E_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \
894 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
896 #define I40E_TXD_CTX_QW1_MSS_SHIFT 50
897 #define I40E_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \
898 I40E_TXD_CTX_QW1_MSS_SHIFT)
900 #define I40E_TXD_CTX_QW1_VSI_SHIFT 50
901 #define I40E_TXD_CTX_QW1_VSI_MASK (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
903 #define I40E_TXD_CTX_QW0_EXT_IP_SHIFT 0
904 #define I40E_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \
905 I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
907 enum i40e_tx_ctx_desc_eipt_offload {
908 I40E_TX_CTX_EXT_IP_NONE = 0x0,
909 I40E_TX_CTX_EXT_IP_IPV6 = 0x1,
910 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
911 I40E_TX_CTX_EXT_IP_IPV4 = 0x3
914 #define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2
915 #define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
916 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
918 #define I40E_TXD_CTX_QW0_NATT_SHIFT 9
919 #define I40E_TXD_CTX_QW0_NATT_MASK (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
921 #define I40E_TXD_CTX_UDP_TUNNELING (0x1ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
922 #define I40E_TXD_CTX_GRE_TUNNELING (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
924 #define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT 11
925 #define I40E_TXD_CTX_QW0_EIP_NOINC_MASK (0x1ULL << \
926 I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
928 #define I40E_TXD_CTX_EIP_NOINC_IPID_CONST I40E_TXD_CTX_QW0_EIP_NOINC_MASK
930 #define I40E_TXD_CTX_QW0_NATLEN_SHIFT 12
931 #define I40E_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \
932 I40E_TXD_CTX_QW0_NATLEN_SHIFT)
934 #define I40E_TXD_CTX_QW0_DECTTL_SHIFT 19
935 #define I40E_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \
936 I40E_TXD_CTX_QW0_DECTTL_SHIFT)
938 struct i40e_filter_program_desc {
939 __le32 qindex_flex_ptype_vsi;
941 __le32 dtype_cmd_cntindex;
944 #define I40E_TXD_FLTR_QW0_QINDEX_SHIFT 0
945 #define I40E_TXD_FLTR_QW0_QINDEX_MASK (0x7FFUL << \
946 I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
947 #define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
948 #define I40E_TXD_FLTR_QW0_FLEXOFF_MASK (0x7UL << \
949 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
950 #define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT 17
951 #define I40E_TXD_FLTR_QW0_PCTYPE_MASK (0x3FUL << \
952 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
954 /* Packet Classifier Types for filters */
955 enum i40e_filter_pctype {
956 /* Note: Values 0-30 are reserved for future use */
957 I40E_FILTER_PCTYPE_NONF_IPV4_UDP = 31,
958 /* Note: Value 32 is reserved for future use */
959 I40E_FILTER_PCTYPE_NONF_IPV4_TCP = 33,
960 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP = 34,
961 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER = 35,
962 I40E_FILTER_PCTYPE_FRAG_IPV4 = 36,
963 /* Note: Values 37-40 are reserved for future use */
964 I40E_FILTER_PCTYPE_NONF_IPV6_UDP = 41,
965 I40E_FILTER_PCTYPE_NONF_IPV6_TCP = 43,
966 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP = 44,
967 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER = 45,
968 I40E_FILTER_PCTYPE_FRAG_IPV6 = 46,
969 /* Note: Value 47 is reserved for future use */
970 I40E_FILTER_PCTYPE_FCOE_OX = 48,
971 I40E_FILTER_PCTYPE_FCOE_RX = 49,
972 I40E_FILTER_PCTYPE_FCOE_OTHER = 50,
973 /* Note: Values 51-62 are reserved for future use */
974 I40E_FILTER_PCTYPE_L2_PAYLOAD = 63,
977 enum i40e_filter_program_desc_dest {
978 I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET = 0x0,
979 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX = 0x1,
980 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER = 0x2,
983 enum i40e_filter_program_desc_fd_status {
984 I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE = 0x0,
985 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID = 0x1,
986 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES = 0x2,
987 I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES = 0x3,
990 #define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23
991 #define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
992 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
994 #define I40E_TXD_FLTR_QW1_CMD_SHIFT 4
995 #define I40E_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \
996 I40E_TXD_FLTR_QW1_CMD_SHIFT)
998 #define I40E_TXD_FLTR_QW1_PCMD_SHIFT (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
999 #define I40E_TXD_FLTR_QW1_PCMD_MASK (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1001 enum i40e_filter_program_desc_pcmd {
1002 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE = 0x1,
1003 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE = 0x2,
1006 #define I40E_TXD_FLTR_QW1_DEST_SHIFT (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1007 #define I40E_TXD_FLTR_QW1_DEST_MASK (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1009 #define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1010 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK (0x1ULL << \
1011 I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1013 #define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \
1014 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1015 #define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1016 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1018 #define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1019 #define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1020 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1022 enum i40e_filter_type {
1023 I40E_FLOW_DIRECTOR_FLTR = 0,
1024 I40E_PE_QUAD_HASH_FLTR = 1,
1025 I40E_ETHERTYPE_FLTR,
1031 struct i40e_vsi_context {
1036 u16 vsis_unallocated;
1041 struct i40e_aqc_vsi_properties_data info;
1044 struct i40e_veb_context {
1049 u16 vebs_unallocated;
1051 struct i40e_aqc_get_veb_parameters_completion info;
1054 /* Statistics collected by each port, VSI, VEB, and S-channel */
1055 struct i40e_eth_stats {
1056 u64 rx_bytes; /* gorc */
1057 u64 rx_unicast; /* uprc */
1058 u64 rx_multicast; /* mprc */
1059 u64 rx_broadcast; /* bprc */
1060 u64 rx_discards; /* rdpc */
1061 u64 rx_unknown_protocol; /* rupp */
1062 u64 tx_bytes; /* gotc */
1063 u64 tx_unicast; /* uptc */
1064 u64 tx_multicast; /* mptc */
1065 u64 tx_broadcast; /* bptc */
1066 u64 tx_discards; /* tdpc */
1067 u64 tx_errors; /* tepc */
1071 /* Statistics collected per function for FCoE */
1072 struct i40e_fcoe_stats {
1073 u64 rx_fcoe_packets; /* fcoeprc */
1074 u64 rx_fcoe_dwords; /* focedwrc */
1075 u64 rx_fcoe_dropped; /* fcoerpdc */
1076 u64 tx_fcoe_packets; /* fcoeptc */
1077 u64 tx_fcoe_dwords; /* focedwtc */
1078 u64 fcoe_bad_fccrc; /* fcoecrc */
1079 u64 fcoe_last_error; /* fcoelast */
1080 u64 fcoe_ddp_count; /* fcoeddpc */
1083 /* offset to per function FCoE statistics block */
1084 #define I40E_FCOE_VF_STAT_OFFSET 0
1085 #define I40E_FCOE_PF_STAT_OFFSET 128
1086 #define I40E_FCOE_STAT_MAX (I40E_FCOE_PF_STAT_OFFSET + I40E_MAX_PF)
1089 /* Statistics collected by the MAC */
1090 struct i40e_hw_port_stats {
1091 /* eth stats collected by the port */
1092 struct i40e_eth_stats eth;
1094 /* additional port specific stats */
1095 u64 tx_dropped_link_down; /* tdold */
1096 u64 crc_errors; /* crcerrs */
1097 u64 illegal_bytes; /* illerrc */
1098 u64 error_bytes; /* errbc */
1099 u64 mac_local_faults; /* mlfc */
1100 u64 mac_remote_faults; /* mrfc */
1101 u64 rx_length_errors; /* rlec */
1102 u64 link_xon_rx; /* lxonrxc */
1103 u64 link_xoff_rx; /* lxoffrxc */
1104 u64 priority_xon_rx[8]; /* pxonrxc[8] */
1105 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
1106 u64 link_xon_tx; /* lxontxc */
1107 u64 link_xoff_tx; /* lxofftxc */
1108 u64 priority_xon_tx[8]; /* pxontxc[8] */
1109 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
1110 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
1111 u64 rx_size_64; /* prc64 */
1112 u64 rx_size_127; /* prc127 */
1113 u64 rx_size_255; /* prc255 */
1114 u64 rx_size_511; /* prc511 */
1115 u64 rx_size_1023; /* prc1023 */
1116 u64 rx_size_1522; /* prc1522 */
1117 u64 rx_size_big; /* prc9522 */
1118 u64 rx_undersize; /* ruc */
1119 u64 rx_fragments; /* rfc */
1120 u64 rx_oversize; /* roc */
1121 u64 rx_jabber; /* rjc */
1122 u64 tx_size_64; /* ptc64 */
1123 u64 tx_size_127; /* ptc127 */
1124 u64 tx_size_255; /* ptc255 */
1125 u64 tx_size_511; /* ptc511 */
1126 u64 tx_size_1023; /* ptc1023 */
1127 u64 tx_size_1522; /* ptc1522 */
1128 u64 tx_size_big; /* ptc9522 */
1129 u64 mac_short_packet_dropped; /* mspdc */
1130 u64 checksum_error; /* xec */
1131 /* flow director stats */
1137 u64 tx_lpi_count; /* etlpic */
1138 u64 rx_lpi_count; /* erlpic */
1141 /* Checksum and Shadow RAM pointers */
1142 #define I40E_SR_NVM_CONTROL_WORD 0x00
1143 #define I40E_SR_EMP_MODULE_PTR 0x0F
1144 #define I40E_SR_PBA_FLAGS 0x15
1145 #define I40E_SR_PBA_BLOCK_PTR 0x16
1146 #define I40E_SR_NVM_IMAGE_VERSION 0x18
1147 #define I40E_SR_NVM_WAKE_ON_LAN 0x19
1148 #define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27
1149 #define I40E_SR_NVM_EETRACK_LO 0x2D
1150 #define I40E_SR_NVM_EETRACK_HI 0x2E
1151 #define I40E_SR_VPD_PTR 0x2F
1152 #define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
1153 #define I40E_SR_SW_CHECKSUM_WORD 0x3F
1155 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1156 #define I40E_SR_VPD_MODULE_MAX_SIZE 1024
1157 #define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024
1158 #define I40E_SR_CONTROL_WORD_1_SHIFT 0x06
1159 #define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1161 /* Shadow RAM related */
1162 #define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800
1163 #define I40E_SR_WORDS_IN_1KB 512
1164 /* Checksum should be calculated such that after adding all the words,
1165 * including the checksum word itself, the sum should be 0xBABA.
1167 #define I40E_SR_SW_CHECKSUM_BASE 0xBABA
1169 #define I40E_SRRD_SRCTL_ATTEMPTS 100000
1172 /* FCoE Tx context descriptor - Use the i40e_tx_context_desc struct */
1174 enum i40E_fcoe_tx_ctx_desc_cmd_bits {
1175 I40E_FCOE_TX_CTX_DESC_OPCODE_SINGLE_SEND = 0x00, /* 4 BITS */
1176 I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS2 = 0x01, /* 4 BITS */
1177 I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS3 = 0x05, /* 4 BITS */
1178 I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS2 = 0x02, /* 4 BITS */
1179 I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS3 = 0x06, /* 4 BITS */
1180 I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS2 = 0x03, /* 4 BITS */
1181 I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS3 = 0x07, /* 4 BITS */
1182 I40E_FCOE_TX_CTX_DESC_OPCODE_DDP_CTX_INVL = 0x08, /* 4 BITS */
1183 I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_CTX_INVL = 0x09, /* 4 BITS */
1184 I40E_FCOE_TX_CTX_DESC_RELOFF = 0x10,
1185 I40E_FCOE_TX_CTX_DESC_CLRSEQ = 0x20,
1186 I40E_FCOE_TX_CTX_DESC_DIFENA = 0x40,
1187 I40E_FCOE_TX_CTX_DESC_IL2TAG2 = 0x80
1190 /* FCoE DDP Context descriptor */
1191 struct i40e_fcoe_ddp_context_desc {
1193 __le64 type_cmd_foff_lsize;
1196 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT 0
1197 #define I40E_FCOE_DDP_CTX_QW1_DTYPE_MASK (0xFULL << \
1198 I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT)
1200 #define I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT 4
1201 #define I40E_FCOE_DDP_CTX_QW1_CMD_MASK (0xFULL << \
1202 I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT)
1204 enum i40e_fcoe_ddp_ctx_desc_cmd_bits {
1205 I40E_FCOE_DDP_CTX_DESC_BSIZE_512B = 0x00, /* 2 BITS */
1206 I40E_FCOE_DDP_CTX_DESC_BSIZE_4K = 0x01, /* 2 BITS */
1207 I40E_FCOE_DDP_CTX_DESC_BSIZE_8K = 0x02, /* 2 BITS */
1208 I40E_FCOE_DDP_CTX_DESC_BSIZE_16K = 0x03, /* 2 BITS */
1209 I40E_FCOE_DDP_CTX_DESC_DIFENA = 0x04, /* 1 BIT */
1210 I40E_FCOE_DDP_CTX_DESC_LASTSEQH = 0x08, /* 1 BIT */
1213 #define I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT 16
1214 #define I40E_FCOE_DDP_CTX_QW1_FOFF_MASK (0x3FFFULL << \
1215 I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT)
1217 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT 32
1218 #define I40E_FCOE_DDP_CTX_QW1_LSIZE_MASK (0x3FFFULL << \
1219 I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT)
1221 /* FCoE DDP/DWO Queue Context descriptor */
1222 struct i40e_fcoe_queue_context_desc {
1223 __le64 dmaindx_fbase; /* 0:11 DMAINDX, 12:63 FBASE */
1224 __le64 flen_tph; /* 0:12 FLEN, 13:15 TPH */
1227 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT 0
1228 #define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_MASK (0xFFFULL << \
1229 I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT)
1231 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT 12
1232 #define I40E_FCOE_QUEUE_CTX_QW0_FBASE_MASK (0xFFFFFFFFFFFFFULL << \
1233 I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT)
1235 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT 0
1236 #define I40E_FCOE_QUEUE_CTX_QW1_FLEN_MASK (0x1FFFULL << \
1237 I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1239 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_SHIFT 13
1240 #define I40E_FCOE_QUEUE_CTX_QW1_TPH_MASK (0x7ULL << \
1241 I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1243 enum i40e_fcoe_queue_ctx_desc_tph_bits {
1244 I40E_FCOE_QUEUE_CTX_DESC_TPHRDESC = 0x1,
1245 I40E_FCOE_QUEUE_CTX_DESC_TPHDATA = 0x2
1248 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT 30
1249 #define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_MASK (0x3ULL << \
1250 I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT)
1252 /* FCoE DDP/DWO Filter Context descriptor */
1253 struct i40e_fcoe_filter_context_desc {
1257 /* 48:51(0:3) RSVD, 52:63(4:15) DMAINDX */
1258 __le16 rsvd_dmaindx;
1260 /* 0:7 FLAGS, 8:52 RSVD, 53:63 LANQ */
1261 __le64 flags_rsvd_lanq;
1264 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT 4
1265 #define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_MASK (0xFFF << \
1266 I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT)
1268 enum i40e_fcoe_filter_ctx_desc_flags_bits {
1269 I40E_FCOE_FILTER_CTX_DESC_CTYP_DDP = 0x00,
1270 I40E_FCOE_FILTER_CTX_DESC_CTYP_DWO = 0x01,
1271 I40E_FCOE_FILTER_CTX_DESC_ENODE_INIT = 0x00,
1272 I40E_FCOE_FILTER_CTX_DESC_ENODE_RSP = 0x02,
1273 I40E_FCOE_FILTER_CTX_DESC_FC_CLASS2 = 0x00,
1274 I40E_FCOE_FILTER_CTX_DESC_FC_CLASS3 = 0x04
1277 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT 0
1278 #define I40E_FCOE_FILTER_CTX_QW1_FLAGS_MASK (0xFFULL << \
1279 I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT)
1281 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT 8
1282 #define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_MASK (0x3FULL << \
1283 I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT)
1285 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT 53
1286 #define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_MASK (0x7FFULL << \
1287 I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT)
1289 #endif /* I40E_FCOE */
1290 enum i40e_switch_element_types {
1291 I40E_SWITCH_ELEMENT_TYPE_MAC = 1,
1292 I40E_SWITCH_ELEMENT_TYPE_PF = 2,
1293 I40E_SWITCH_ELEMENT_TYPE_VF = 3,
1294 I40E_SWITCH_ELEMENT_TYPE_EMP = 4,
1295 I40E_SWITCH_ELEMENT_TYPE_BMC = 6,
1296 I40E_SWITCH_ELEMENT_TYPE_PE = 16,
1297 I40E_SWITCH_ELEMENT_TYPE_VEB = 17,
1298 I40E_SWITCH_ELEMENT_TYPE_PA = 18,
1299 I40E_SWITCH_ELEMENT_TYPE_VSI = 19,
1302 /* Supported EtherType filters */
1303 enum i40e_ether_type_index {
1304 I40E_ETHER_TYPE_1588 = 0,
1305 I40E_ETHER_TYPE_FIP = 1,
1306 I40E_ETHER_TYPE_OUI_EXTENDED = 2,
1307 I40E_ETHER_TYPE_MAC_CONTROL = 3,
1308 I40E_ETHER_TYPE_LLDP = 4,
1309 I40E_ETHER_TYPE_EVB_PROTOCOL1 = 5,
1310 I40E_ETHER_TYPE_EVB_PROTOCOL2 = 6,
1311 I40E_ETHER_TYPE_QCN_CNM = 7,
1312 I40E_ETHER_TYPE_8021X = 8,
1313 I40E_ETHER_TYPE_ARP = 9,
1314 I40E_ETHER_TYPE_RSV1 = 10,
1315 I40E_ETHER_TYPE_RSV2 = 11,
1318 /* Filter context base size is 1K */
1319 #define I40E_HASH_FILTER_BASE_SIZE 1024
1320 /* Supported Hash filter values */
1321 enum i40e_hash_filter_size {
1322 I40E_HASH_FILTER_SIZE_1K = 0,
1323 I40E_HASH_FILTER_SIZE_2K = 1,
1324 I40E_HASH_FILTER_SIZE_4K = 2,
1325 I40E_HASH_FILTER_SIZE_8K = 3,
1326 I40E_HASH_FILTER_SIZE_16K = 4,
1327 I40E_HASH_FILTER_SIZE_32K = 5,
1328 I40E_HASH_FILTER_SIZE_64K = 6,
1329 I40E_HASH_FILTER_SIZE_128K = 7,
1330 I40E_HASH_FILTER_SIZE_256K = 8,
1331 I40E_HASH_FILTER_SIZE_512K = 9,
1332 I40E_HASH_FILTER_SIZE_1M = 10,
1335 /* DMA context base size is 0.5K */
1336 #define I40E_DMA_CNTX_BASE_SIZE 512
1337 /* Supported DMA context values */
1338 enum i40e_dma_cntx_size {
1339 I40E_DMA_CNTX_SIZE_512 = 0,
1340 I40E_DMA_CNTX_SIZE_1K = 1,
1341 I40E_DMA_CNTX_SIZE_2K = 2,
1342 I40E_DMA_CNTX_SIZE_4K = 3,
1343 I40E_DMA_CNTX_SIZE_8K = 4,
1344 I40E_DMA_CNTX_SIZE_16K = 5,
1345 I40E_DMA_CNTX_SIZE_32K = 6,
1346 I40E_DMA_CNTX_SIZE_64K = 7,
1347 I40E_DMA_CNTX_SIZE_128K = 8,
1348 I40E_DMA_CNTX_SIZE_256K = 9,
1351 /* Supported Hash look up table (LUT) sizes */
1352 enum i40e_hash_lut_size {
1353 I40E_HASH_LUT_SIZE_128 = 0,
1354 I40E_HASH_LUT_SIZE_512 = 1,
1357 /* Structure to hold a per PF filter control settings */
1358 struct i40e_filter_control_settings {
1359 /* number of PE Quad Hash filter buckets */
1360 enum i40e_hash_filter_size pe_filt_num;
1361 /* number of PE Quad Hash contexts */
1362 enum i40e_dma_cntx_size pe_cntx_num;
1363 /* number of FCoE filter buckets */
1364 enum i40e_hash_filter_size fcoe_filt_num;
1365 /* number of FCoE DDP contexts */
1366 enum i40e_dma_cntx_size fcoe_cntx_num;
1367 /* size of the Hash LUT */
1368 enum i40e_hash_lut_size hash_lut_size;
1369 /* enable FDIR filters for PF and its VFs */
1371 /* enable Ethertype filters for PF and its VFs */
1372 bool enable_ethtype;
1373 /* enable MAC/VLAN filters for PF and its VFs */
1374 bool enable_macvlan;
1377 /* Structure to hold device level control filter counts */
1378 struct i40e_control_filter_stats {
1379 u16 mac_etype_used; /* Used perfect match MAC/EtherType filters */
1380 u16 etype_used; /* Used perfect EtherType filters */
1381 u16 mac_etype_free; /* Un-used perfect match MAC/EtherType filters */
1382 u16 etype_free; /* Un-used perfect EtherType filters */
1385 enum i40e_reset_type {
1387 I40E_RESET_CORER = 1,
1388 I40E_RESET_GLOBR = 2,
1389 I40E_RESET_EMPR = 3,
1392 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1393 #define I40E_NVM_LLDP_CFG_PTR 0xD
1394 struct i40e_lldp_variables {
1404 /* RSS Hash Table Size */
1405 #define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1406 #endif /* _I40E_TYPE_H_ */