drivers/net/ethernet/intel/igb/e1000_82575.c

   1 /*******************************************************************************
   2
   3   Intel(R) Gigabit Ethernet Linux driver
   4   Copyright(c) 2007-2013 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 /* e1000_82575
  29  * e1000_82576
  30  */
  31
  32 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  33
  34 #include <linux/types.h>
  35 #include <linux/if_ether.h>
  36 #include <linux/i2c.h>
  37
  38 #include "e1000_mac.h"
  39 #include "e1000_82575.h"
  40 #include "e1000_i210.h"
  41
  42 static s32  igb_get_invariants_82575(struct e1000_hw *);
  43 static s32  igb_acquire_phy_82575(struct e1000_hw *);
  44 static void igb_release_phy_82575(struct e1000_hw *);
  45 static s32  igb_acquire_nvm_82575(struct e1000_hw *);
  46 static void igb_release_nvm_82575(struct e1000_hw *);
  47 static s32  igb_check_for_link_82575(struct e1000_hw *);
  48 static s32  igb_get_cfg_done_82575(struct e1000_hw *);
  49 static s32  igb_init_hw_82575(struct e1000_hw *);
  50 static s32  igb_phy_hw_reset_sgmii_82575(struct e1000_hw *);
  51 static s32  igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *);
  52 static s32  igb_read_phy_reg_82580(struct e1000_hw *, u32, u16 *);
  53 static s32  igb_write_phy_reg_82580(struct e1000_hw *, u32, u16);
  54 static s32  igb_reset_hw_82575(struct e1000_hw *);
  55 static s32  igb_reset_hw_82580(struct e1000_hw *);
  56 static s32  igb_set_d0_lplu_state_82575(struct e1000_hw *, bool);
  57 static s32  igb_set_d0_lplu_state_82580(struct e1000_hw *, bool);
  58 static s32  igb_set_d3_lplu_state_82580(struct e1000_hw *, bool);
  59 static s32  igb_setup_copper_link_82575(struct e1000_hw *);
  60 static s32  igb_setup_serdes_link_82575(struct e1000_hw *);
  61 static s32  igb_write_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16);
  62 static void igb_clear_hw_cntrs_82575(struct e1000_hw *);
  63 static s32  igb_acquire_swfw_sync_82575(struct e1000_hw *, u16);
  64 static s32  igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *, u16 *,
  65                                                  u16 *);
  66 static s32  igb_get_phy_id_82575(struct e1000_hw *);
  67 static void igb_release_swfw_sync_82575(struct e1000_hw *, u16);
  68 static bool igb_sgmii_active_82575(struct e1000_hw *);
  69 static s32  igb_reset_init_script_82575(struct e1000_hw *);
  70 static s32  igb_read_mac_addr_82575(struct e1000_hw *);
  71 static s32  igb_set_pcie_completion_timeout(struct e1000_hw *hw);
  72 static s32  igb_reset_mdicnfg_82580(struct e1000_hw *hw);
  73 static s32  igb_validate_nvm_checksum_82580(struct e1000_hw *hw);
  74 static s32  igb_update_nvm_checksum_82580(struct e1000_hw *hw);
  75 static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw);
  76 static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw);
  77 static const u16 e1000_82580_rxpbs_table[] =
  78         { 36, 72, 144, 1, 2, 4, 8, 16,
  79           35, 70, 140 };
  80 #define E1000_82580_RXPBS_TABLE_SIZE \
  81         (sizeof(e1000_82580_rxpbs_table)/sizeof(u16))
  82
  83 /**
  84  *  igb_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
  85  *  @hw: pointer to the HW structure
  86  *
  87  *  Called to determine if the I2C pins are being used for I2C or as an
  88  *  external MDIO interface since the two options are mutually exclusive.
  89  **/
  90 static bool igb_sgmii_uses_mdio_82575(struct e1000_hw *hw)
  91 {
  92         u32 reg = 0;
  93         bool ext_mdio = false;
  94
  95         switch (hw->mac.type) {
  96         case e1000_82575:
  97         case e1000_82576:
  98                 reg = rd32(E1000_MDIC);
  99                 ext_mdio = !!(reg & E1000_MDIC_DEST);
 100                 break;
 101         case e1000_82580:
 102         case e1000_i350:
 103         case e1000_i354:
 104         case e1000_i210:
 105         case e1000_i211:
 106                 reg = rd32(E1000_MDICNFG);
 107                 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
 108                 break;
 109         default:
 110                 break;
 111         }
 112         return ext_mdio;
 113 }
 114
 115 /**
 116  *  igb_init_phy_params_82575 - Init PHY func ptrs.
 117  *  @hw: pointer to the HW structure
 118  **/
 119 static s32 igb_init_phy_params_82575(struct e1000_hw *hw)
 120 {
 121         struct e1000_phy_info *phy = &hw->phy;
 122         s32 ret_val = 0;
 123         u32 ctrl_ext;
 124
 125         if (hw->phy.media_type != e1000_media_type_copper) {
 126                 phy->type = e1000_phy_none;
 127                 goto out;
 128         }
 129
 130         phy->autoneg_mask       = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 131         phy->reset_delay_us     = 100;
 132
 133         ctrl_ext = rd32(E1000_CTRL_EXT);
 134
 135         if (igb_sgmii_active_82575(hw)) {
 136                 phy->ops.reset = igb_phy_hw_reset_sgmii_82575;
 137                 ctrl_ext |= E1000_CTRL_I2C_ENA;
 138         } else {
 139                 phy->ops.reset = igb_phy_hw_reset;
 140                 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
 141         }
 142
 143         wr32(E1000_CTRL_EXT, ctrl_ext);
 144         igb_reset_mdicnfg_82580(hw);
 145
 146         if (igb_sgmii_active_82575(hw) && !igb_sgmii_uses_mdio_82575(hw)) {
 147                 phy->ops.read_reg = igb_read_phy_reg_sgmii_82575;
 148                 phy->ops.write_reg = igb_write_phy_reg_sgmii_82575;
 149         } else {
 150                 switch (hw->mac.type) {
 151                 case e1000_82580:
 152                 case e1000_i350:
 153                 case e1000_i354:
 154                         phy->ops.read_reg = igb_read_phy_reg_82580;
 155                         phy->ops.write_reg = igb_write_phy_reg_82580;
 156                         break;
 157                 case e1000_i210:
 158                 case e1000_i211:
 159                         phy->ops.read_reg = igb_read_phy_reg_gs40g;
 160                         phy->ops.write_reg = igb_write_phy_reg_gs40g;
 161                         break;
 162                 default:
 163                         phy->ops.read_reg = igb_read_phy_reg_igp;
 164                         phy->ops.write_reg = igb_write_phy_reg_igp;
 165                 }
 166         }
 167
 168         /* set lan id */
 169         hw->bus.func = (rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) >>
 170                         E1000_STATUS_FUNC_SHIFT;
 171
 172         /* Set phy->phy_addr and phy->id. */
 173         ret_val = igb_get_phy_id_82575(hw);
 174         if (ret_val)
 175                 return ret_val;
 176
 177         /* Verify phy id and set remaining function pointers */
 178         switch (phy->id) {
 179         case M88E1543_E_PHY_ID:
 180         case I347AT4_E_PHY_ID:
 181         case M88E1112_E_PHY_ID:
 182         case M88E1111_I_PHY_ID:
 183                 phy->type               = e1000_phy_m88;
 184                 phy->ops.check_polarity = igb_check_polarity_m88;
 185                 phy->ops.get_phy_info   = igb_get_phy_info_m88;
 186                 if (phy->id != M88E1111_I_PHY_ID)
 187                         phy->ops.get_cable_length =
 188                                          igb_get_cable_length_m88_gen2;
 189                 else
 190                         phy->ops.get_cable_length = igb_get_cable_length_m88;
 191                 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
 192                 break;
 193         case IGP03E1000_E_PHY_ID:
 194                 phy->type = e1000_phy_igp_3;
 195                 phy->ops.get_phy_info = igb_get_phy_info_igp;
 196                 phy->ops.get_cable_length = igb_get_cable_length_igp_2;
 197                 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp;
 198                 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575;
 199                 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state;
 200                 break;
 201         case I82580_I_PHY_ID:
 202         case I350_I_PHY_ID:
 203                 phy->type = e1000_phy_82580;
 204                 phy->ops.force_speed_duplex =
 205                                          igb_phy_force_speed_duplex_82580;
 206                 phy->ops.get_cable_length = igb_get_cable_length_82580;
 207                 phy->ops.get_phy_info = igb_get_phy_info_82580;
 208                 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;
 209                 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;
 210                 break;
 211         case I210_I_PHY_ID:
 212                 phy->type               = e1000_phy_i210;
 213                 phy->ops.check_polarity = igb_check_polarity_m88;
 214                 phy->ops.get_phy_info   = igb_get_phy_info_m88;
 215                 phy->ops.get_cable_length = igb_get_cable_length_m88_gen2;
 216                 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82580;
 217                 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state_82580;
 218                 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88;
 219                 break;
 220         default:
 221                 ret_val = -E1000_ERR_PHY;
 222                 goto out;
 223         }
 224
 225 out:
 226         return ret_val;
 227 }
 228
 229 /**
 230  *  igb_init_nvm_params_82575 - Init NVM func ptrs.
 231  *  @hw: pointer to the HW structure
 232  **/
 233 static s32 igb_init_nvm_params_82575(struct e1000_hw *hw)
 234 {
 235         struct e1000_nvm_info *nvm = &hw->nvm;
 236         u32 eecd = rd32(E1000_EECD);
 237         u16 size;
 238
 239         size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
 240                      E1000_EECD_SIZE_EX_SHIFT);
 241
 242         /* Added to a constant, "size" becomes the left-shift value
 243          * for setting word_size.
 244          */
 245         size += NVM_WORD_SIZE_BASE_SHIFT;
 246
 247         /* Just in case size is out of range, cap it to the largest
 248          * EEPROM size supported
 249          */
 250         if (size > 15)
 251                 size = 15;
 252
 253         nvm->word_size = 1 << size;
 254         nvm->opcode_bits = 8;
 255         nvm->delay_usec = 1;
 256
 257         switch (nvm->override) {
 258         case e1000_nvm_override_spi_large:
 259                 nvm->page_size = 32;
 260                 nvm->address_bits = 16;
 261                 break;
 262         case e1000_nvm_override_spi_small:
 263                 nvm->page_size = 8;
 264                 nvm->address_bits = 8;
 265                 break;
 266         default:
 267                 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 268                 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
 269                                     16 : 8;
 270                 break;
 271         }
 272         if (nvm->word_size == (1 << 15))
 273                 nvm->page_size = 128;
 274
 275         nvm->type = e1000_nvm_eeprom_spi;
 276
 277         /* NVM Function Pointers */
 278         nvm->ops.acquire = igb_acquire_nvm_82575;
 279         nvm->ops.release = igb_release_nvm_82575;
 280         nvm->ops.write = igb_write_nvm_spi;
 281         nvm->ops.validate = igb_validate_nvm_checksum;
 282         nvm->ops.update = igb_update_nvm_checksum;
 283         if (nvm->word_size < (1 << 15))
 284                 nvm->ops.read = igb_read_nvm_eerd;
 285         else
 286                 nvm->ops.read = igb_read_nvm_spi;
 287
 288         /* override generic family function pointers for specific descendants */
 289         switch (hw->mac.type) {
 290         case e1000_82580:
 291                 nvm->ops.validate = igb_validate_nvm_checksum_82580;
 292                 nvm->ops.update = igb_update_nvm_checksum_82580;
 293                 break;
 294         case e1000_i354:
 295         case e1000_i350:
 296                 nvm->ops.validate = igb_validate_nvm_checksum_i350;
 297                 nvm->ops.update = igb_update_nvm_checksum_i350;
 298                 break;
 299         default:
 300                 break;
 301         }
 302
 303         return 0;
 304 }
 305
 306 /**
 307  *  igb_init_mac_params_82575 - Init MAC func ptrs.
 308  *  @hw: pointer to the HW structure
 309  **/
 310 static s32 igb_init_mac_params_82575(struct e1000_hw *hw)
 311 {
 312         struct e1000_mac_info *mac = &hw->mac;
 313         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
 314
 315         /* Set mta register count */
 316         mac->mta_reg_count = 128;
 317         /* Set rar entry count */
 318         switch (mac->type) {
 319         case e1000_82576:
 320                 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
 321                 break;
 322         case e1000_82580:
 323                 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
 324                 break;
 325         case e1000_i350:
 326         case e1000_i354:
 327                 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
 328                 break;
 329         default:
 330                 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
 331                 break;
 332         }
 333         /* reset */
 334         if (mac->type >= e1000_82580)
 335                 mac->ops.reset_hw = igb_reset_hw_82580;
 336         else
 337                 mac->ops.reset_hw = igb_reset_hw_82575;
 338
 339         if (mac->type >= e1000_i210) {
 340                 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_i210;
 341                 mac->ops.release_swfw_sync = igb_release_swfw_sync_i210;
 342
 343         } else {
 344                 mac->ops.acquire_swfw_sync = igb_acquire_swfw_sync_82575;
 345                 mac->ops.release_swfw_sync = igb_release_swfw_sync_82575;
 346         }
 347
 348         /* Set if part includes ASF firmware */
 349         mac->asf_firmware_present = true;
 350         /* Set if manageability features are enabled. */
 351         mac->arc_subsystem_valid =
 352                 (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK)
 353                         ? true : false;
 354         /* enable EEE on i350 parts and later parts */
 355         if (mac->type >= e1000_i350)
 356                 dev_spec->eee_disable = false;
 357         else
 358                 dev_spec->eee_disable = true;
 359         /* Allow a single clear of the SW semaphore on I210 and newer */
 360         if (mac->type >= e1000_i210)
 361                 dev_spec->clear_semaphore_once = true;
 362         /* physical interface link setup */
 363         mac->ops.setup_physical_interface =
 364                 (hw->phy.media_type == e1000_media_type_copper)
 365                         ? igb_setup_copper_link_82575
 366                         : igb_setup_serdes_link_82575;
 367
 368         return 0;
 369 }
 370
 371 /**
 372  *  igb_set_sfp_media_type_82575 - derives SFP module media type.
 373  *  @hw: pointer to the HW structure
 374  *
 375  *  The media type is chosen based on SFP module.
 376  *  compatibility flags retrieved from SFP ID EEPROM.
 377  **/
 378 static s32 igb_set_sfp_media_type_82575(struct e1000_hw *hw)
 379 {
 380         s32 ret_val = E1000_ERR_CONFIG;
 381         u32 ctrl_ext = 0;
 382         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
 383         struct e1000_sfp_flags *eth_flags = &dev_spec->eth_flags;
 384         u8 tranceiver_type = 0;
 385         s32 timeout = 3;
 386
 387         /* Turn I2C interface ON and power on sfp cage */
 388         ctrl_ext = rd32(E1000_CTRL_EXT);
 389         ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
 390         wr32(E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA);
 391
 392         wrfl();
 393
 394         /* Read SFP module data */
 395         while (timeout) {
 396                 ret_val = igb_read_sfp_data_byte(hw,
 397                         E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET),
 398                         &tranceiver_type);
 399                 if (ret_val == 0)
 400                         break;
 401                 msleep(100);
 402                 timeout--;
 403         }
 404         if (ret_val != 0)
 405                 goto out;
 406
 407         ret_val = igb_read_sfp_data_byte(hw,
 408                         E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET),
 409                         (u8 *)eth_flags);
 410         if (ret_val != 0)
 411                 goto out;
 412
 413         /* Check if there is some SFP module plugged and powered */
 414         if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) ||
 415             (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) {
 416                 dev_spec->module_plugged = true;
 417                 if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) {
 418                         hw->phy.media_type = e1000_media_type_internal_serdes;
 419                 } else if (eth_flags->e100_base_fx) {
 420                         dev_spec->sgmii_active = true;
 421                         hw->phy.media_type = e1000_media_type_internal_serdes;
 422                 } else if (eth_flags->e1000_base_t) {
 423                         dev_spec->sgmii_active = true;
 424                         hw->phy.media_type = e1000_media_type_copper;
 425                 } else {
 426                         hw->phy.media_type = e1000_media_type_unknown;
 427                         hw_dbg("PHY module has not been recognized\n");
 428                         goto out;
 429                 }
 430         } else {
 431                 hw->phy.media_type = e1000_media_type_unknown;
 432         }
 433         ret_val = 0;
 434 out:
 435         /* Restore I2C interface setting */
 436         wr32(E1000_CTRL_EXT, ctrl_ext);
 437         return ret_val;
 438 }
 439
 440 static s32 igb_get_invariants_82575(struct e1000_hw *hw)
 441 {
 442         struct e1000_mac_info *mac = &hw->mac;
 443         struct e1000_dev_spec_82575 * dev_spec = &hw->dev_spec._82575;
 444         s32 ret_val;
 445         u32 ctrl_ext = 0;
 446         u32 link_mode = 0;
 447
 448         switch (hw->device_id) {
 449         case E1000_DEV_ID_82575EB_COPPER:
 450         case E1000_DEV_ID_82575EB_FIBER_SERDES:
 451         case E1000_DEV_ID_82575GB_QUAD_COPPER:
 452                 mac->type = e1000_82575;
 453                 break;
 454         case E1000_DEV_ID_82576:
 455         case E1000_DEV_ID_82576_NS:
 456         case E1000_DEV_ID_82576_NS_SERDES:
 457         case E1000_DEV_ID_82576_FIBER:
 458         case E1000_DEV_ID_82576_SERDES:
 459         case E1000_DEV_ID_82576_QUAD_COPPER:
 460         case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
 461         case E1000_DEV_ID_82576_SERDES_QUAD:
 462                 mac->type = e1000_82576;
 463                 break;
 464         case E1000_DEV_ID_82580_COPPER:
 465         case E1000_DEV_ID_82580_FIBER:
 466         case E1000_DEV_ID_82580_QUAD_FIBER:
 467         case E1000_DEV_ID_82580_SERDES:
 468         case E1000_DEV_ID_82580_SGMII:
 469         case E1000_DEV_ID_82580_COPPER_DUAL:
 470         case E1000_DEV_ID_DH89XXCC_SGMII:
 471         case E1000_DEV_ID_DH89XXCC_SERDES:
 472         case E1000_DEV_ID_DH89XXCC_BACKPLANE:
 473         case E1000_DEV_ID_DH89XXCC_SFP:
 474                 mac->type = e1000_82580;
 475                 break;
 476         case E1000_DEV_ID_I350_COPPER:
 477         case E1000_DEV_ID_I350_FIBER:
 478         case E1000_DEV_ID_I350_SERDES:
 479         case E1000_DEV_ID_I350_SGMII:
 480                 mac->type = e1000_i350;
 481                 break;
 482         case E1000_DEV_ID_I210_COPPER:
 483         case E1000_DEV_ID_I210_FIBER:
 484         case E1000_DEV_ID_I210_SERDES:
 485         case E1000_DEV_ID_I210_SGMII:
 486         case E1000_DEV_ID_I210_COPPER_FLASHLESS:
 487         case E1000_DEV_ID_I210_SERDES_FLASHLESS:
 488                 mac->type = e1000_i210;
 489                 break;
 490         case E1000_DEV_ID_I211_COPPER:
 491                 mac->type = e1000_i211;
 492                 break;
 493         case E1000_DEV_ID_I354_BACKPLANE_1GBPS:
 494         case E1000_DEV_ID_I354_SGMII:
 495         case E1000_DEV_ID_I354_BACKPLANE_2_5GBPS:
 496                 mac->type = e1000_i354;
 497                 break;
 498         default:
 499                 return -E1000_ERR_MAC_INIT;
 500                 break;
 501         }
 502
 503         /* Set media type */
 504         /* The 82575 uses bits 22:23 for link mode. The mode can be changed
 505          * based on the EEPROM. We cannot rely upon device ID. There
 506          * is no distinguishable difference between fiber and internal
 507          * SerDes mode on the 82575. There can be an external PHY attached
 508          * on the SGMII interface. For this, we'll set sgmii_active to true.
 509          */
 510         hw->phy.media_type = e1000_media_type_copper;
 511         dev_spec->sgmii_active = false;
 512         dev_spec->module_plugged = false;
 513
 514         ctrl_ext = rd32(E1000_CTRL_EXT);
 515
 516         link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK;
 517         switch (link_mode) {
 518         case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
 519                 hw->phy.media_type = e1000_media_type_internal_serdes;
 520                 break;
 521         case E1000_CTRL_EXT_LINK_MODE_SGMII:
 522                 /* Get phy control interface type set (MDIO vs. I2C)*/
 523                 if (igb_sgmii_uses_mdio_82575(hw)) {
 524                         hw->phy.media_type = e1000_media_type_copper;
 525                         dev_spec->sgmii_active = true;
 526                         break;
 527                 }
 528                 /* fall through for I2C based SGMII */
 529         case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
 530                 /* read media type from SFP EEPROM */
 531                 ret_val = igb_set_sfp_media_type_82575(hw);
 532                 if ((ret_val != 0) ||
 533                     (hw->phy.media_type == e1000_media_type_unknown)) {
 534                         /* If media type was not identified then return media
 535                          * type defined by the CTRL_EXT settings.
 536                          */
 537                         hw->phy.media_type = e1000_media_type_internal_serdes;
 538
 539                         if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) {
 540                                 hw->phy.media_type = e1000_media_type_copper;
 541                                 dev_spec->sgmii_active = true;
 542                         }
 543
 544                         break;
 545                 }
 546
 547                 /* do not change link mode for 100BaseFX */
 548                 if (dev_spec->eth_flags.e100_base_fx)
 549                         break;
 550
 551                 /* change current link mode setting */
 552                 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
 553
 554                 if (hw->phy.media_type == e1000_media_type_copper)
 555                         ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII;
 556                 else
 557                         ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
 558
 559                 wr32(E1000_CTRL_EXT, ctrl_ext);
 560
 561                 break;
 562         default:
 563                 break;
 564         }
 565
 566         /* mac initialization and operations */
 567         ret_val = igb_init_mac_params_82575(hw);
 568         if (ret_val)
 569                 goto out;
 570
 571         /* NVM initialization */
 572         ret_val = igb_init_nvm_params_82575(hw);
 573         switch (hw->mac.type) {
 574         case e1000_i210:
 575         case e1000_i211:
 576                 ret_val = igb_init_nvm_params_i210(hw);
 577                 break;
 578         default:
 579                 break;
 580         }
 581
 582         if (ret_val)
 583                 goto out;
 584
 585         /* if part supports SR-IOV then initialize mailbox parameters */
 586         switch (mac->type) {
 587         case e1000_82576:
 588         case e1000_i350:
 589                 igb_init_mbx_params_pf(hw);
 590                 break;
 591         default:
 592                 break;
 593         }
 594
 595         /* setup PHY parameters */
 596         ret_val = igb_init_phy_params_82575(hw);
 597
 598 out:
 599         return ret_val;
 600 }
 601
 602 /**
 603  *  igb_acquire_phy_82575 - Acquire rights to access PHY
 604  *  @hw: pointer to the HW structure
 605  *
 606  *  Acquire access rights to the correct PHY.  This is a
 607  *  function pointer entry point called by the api module.
 608  **/
 609 static s32 igb_acquire_phy_82575(struct e1000_hw *hw)
 610 {
 611         u16 mask = E1000_SWFW_PHY0_SM;
 612
 613         if (hw->bus.func == E1000_FUNC_1)
 614                 mask = E1000_SWFW_PHY1_SM;
 615         else if (hw->bus.func == E1000_FUNC_2)
 616                 mask = E1000_SWFW_PHY2_SM;
 617         else if (hw->bus.func == E1000_FUNC_3)
 618                 mask = E1000_SWFW_PHY3_SM;
 619
 620         return hw->mac.ops.acquire_swfw_sync(hw, mask);
 621 }
 622
 623 /**
 624  *  igb_release_phy_82575 - Release rights to access PHY
 625  *  @hw: pointer to the HW structure
 626  *
 627  *  A wrapper to release access rights to the correct PHY.  This is a
 628  *  function pointer entry point called by the api module.
 629  **/
 630 static void igb_release_phy_82575(struct e1000_hw *hw)
 631 {
 632         u16 mask = E1000_SWFW_PHY0_SM;
 633
 634         if (hw->bus.func == E1000_FUNC_1)
 635                 mask = E1000_SWFW_PHY1_SM;
 636         else if (hw->bus.func == E1000_FUNC_2)
 637                 mask = E1000_SWFW_PHY2_SM;
 638         else if (hw->bus.func == E1000_FUNC_3)
 639                 mask = E1000_SWFW_PHY3_SM;
 640
 641         hw->mac.ops.release_swfw_sync(hw, mask);
 642 }
 643
 644 /**
 645  *  igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
 646  *  @hw: pointer to the HW structure
 647  *  @offset: register offset to be read
 648  *  @data: pointer to the read data
 649  *
 650  *  Reads the PHY register at offset using the serial gigabit media independent
 651  *  interface and stores the retrieved information in data.
 652  **/
 653 static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
 654                                           u16 *data)
 655 {
 656         s32 ret_val = -E1000_ERR_PARAM;
 657
 658         if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
 659                 hw_dbg("PHY Address %u is out of range\n", offset);
 660                 goto out;
 661         }
 662
 663         ret_val = hw->phy.ops.acquire(hw);
 664         if (ret_val)
 665                 goto out;
 666
 667         ret_val = igb_read_phy_reg_i2c(hw, offset, data);
 668
 669         hw->phy.ops.release(hw);
 670
 671 out:
 672         return ret_val;
 673 }
 674
 675 /**
 676  *  igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
 677  *  @hw: pointer to the HW structure
 678  *  @offset: register offset to write to
 679  *  @data: data to write at register offset
 680  *
 681  *  Writes the data to PHY register at the offset using the serial gigabit
 682  *  media independent interface.
 683  **/
 684 static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
 685                                            u16 data)
 686 {
 687         s32 ret_val = -E1000_ERR_PARAM;
 688
 689
 690         if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
 691                 hw_dbg("PHY Address %d is out of range\n", offset);
 692                 goto out;
 693         }
 694
 695         ret_val = hw->phy.ops.acquire(hw);
 696         if (ret_val)
 697                 goto out;
 698
 699         ret_val = igb_write_phy_reg_i2c(hw, offset, data);
 700
 701         hw->phy.ops.release(hw);
 702
 703 out:
 704         return ret_val;
 705 }
 706
 707 /**
 708  *  igb_get_phy_id_82575 - Retrieve PHY addr and id
 709  *  @hw: pointer to the HW structure
 710  *
 711  *  Retrieves the PHY address and ID for both PHY's which do and do not use
 712  *  sgmi interface.
 713  **/
 714 static s32 igb_get_phy_id_82575(struct e1000_hw *hw)
 715 {
 716         struct e1000_phy_info *phy = &hw->phy;
 717         s32  ret_val = 0;
 718         u16 phy_id;
 719         u32 ctrl_ext;
 720         u32 mdic;
 721
 722         /* For SGMII PHYs, we try the list of possible addresses until
 723          * we find one that works.  For non-SGMII PHYs
 724          * (e.g. integrated copper PHYs), an address of 1 should
 725          * work.  The result of this function should mean phy->phy_addr
 726          * and phy->id are set correctly.
 727          */
 728         if (!(igb_sgmii_active_82575(hw))) {
 729                 phy->addr = 1;
 730                 ret_val = igb_get_phy_id(hw);
 731                 goto out;
 732         }
 733
 734         if (igb_sgmii_uses_mdio_82575(hw)) {
 735                 switch (hw->mac.type) {
 736                 case e1000_82575:
 737                 case e1000_82576:
 738                         mdic = rd32(E1000_MDIC);
 739                         mdic &= E1000_MDIC_PHY_MASK;
 740                         phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
 741                         break;
 742                 case e1000_82580:
 743                 case e1000_i350:
 744                 case e1000_i354:
 745                 case e1000_i210:
 746                 case e1000_i211:
 747                         mdic = rd32(E1000_MDICNFG);
 748                         mdic &= E1000_MDICNFG_PHY_MASK;
 749                         phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
 750                         break;
 751                 default:
 752                         ret_val = -E1000_ERR_PHY;
 753                         goto out;
 754                         break;
 755                 }
 756                 ret_val = igb_get_phy_id(hw);
 757                 goto out;
 758         }
 759
 760         /* Power on sgmii phy if it is disabled */
 761         ctrl_ext = rd32(E1000_CTRL_EXT);
 762         wr32(E1000_CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
 763         wrfl();
 764         msleep(300);
 765
 766         /* The address field in the I2CCMD register is 3 bits and 0 is invalid.
 767          * Therefore, we need to test 1-7
 768          */
 769         for (phy->addr = 1; phy->addr < 8; phy->addr++) {
 770                 ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
 771                 if (ret_val == 0) {
 772                         hw_dbg("Vendor ID 0x%08X read at address %u\n",
 773                                phy_id, phy->addr);
 774                         /* At the time of this writing, The M88 part is
 775                          * the only supported SGMII PHY product.
 776                          */
 777                         if (phy_id == M88_VENDOR)
 778                                 break;
 779                 } else {
 780                         hw_dbg("PHY address %u was unreadable\n", phy->addr);
 781                 }
 782         }
 783
 784         /* A valid PHY type couldn't be found. */
 785         if (phy->addr == 8) {
 786                 phy->addr = 0;
 787                 ret_val = -E1000_ERR_PHY;
 788                 goto out;
 789         } else {
 790                 ret_val = igb_get_phy_id(hw);
 791         }
 792
 793         /* restore previous sfp cage power state */
 794         wr32(E1000_CTRL_EXT, ctrl_ext);
 795
 796 out:
 797         return ret_val;
 798 }
 799
 800 /**
 801  *  igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset
 802  *  @hw: pointer to the HW structure
 803  *
 804  *  Resets the PHY using the serial gigabit media independent interface.
 805  **/
 806 static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
 807 {
 808         s32 ret_val;
 809
 810         /* This isn't a true "hard" reset, but is the only reset
 811          * available to us at this time.
 812          */
 813
 814         hw_dbg("Soft resetting SGMII attached PHY...\n");
 815
 816         /* SFP documentation requires the following to configure the SPF module
 817          * to work on SGMII.  No further documentation is given.
 818          */
 819         ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
 820         if (ret_val)
 821                 goto out;
 822
 823         ret_val = igb_phy_sw_reset(hw);
 824
 825 out:
 826         return ret_val;
 827 }
 828
 829 /**
 830  *  igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
 831  *  @hw: pointer to the HW structure
 832  *  @active: true to enable LPLU, false to disable
 833  *
 834  *  Sets the LPLU D0 state according to the active flag.  When
 835  *  activating LPLU this function also disables smart speed
 836  *  and vice versa.  LPLU will not be activated unless the
 837  *  device autonegotiation advertisement meets standards of
 838  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 839  *  This is a function pointer entry point only called by
 840  *  PHY setup routines.
 841  **/
 842 static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
 843 {
 844         struct e1000_phy_info *phy = &hw->phy;
 845         s32 ret_val;
 846         u16 data;
 847
 848         ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
 849         if (ret_val)
 850                 goto out;
 851
 852         if (active) {
 853                 data |= IGP02E1000_PM_D0_LPLU;
 854                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
 855                                                  data);
 856                 if (ret_val)
 857                         goto out;
 858
 859                 /* When LPLU is enabled, we should disable SmartSpeed */
 860                 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
 861                                                 &data);
 862                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 863                 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
 864                                                  data);
 865                 if (ret_val)
 866                         goto out;
 867         } else {
 868                 data &= ~IGP02E1000_PM_D0_LPLU;
 869                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
 870                                                  data);
 871                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 872                  * during Dx states where the power conservation is most
 873                  * important.  During driver activity we should enable
 874                  * SmartSpeed, so performance is maintained.
 875                  */
 876                 if (phy->smart_speed == e1000_smart_speed_on) {
 877                         ret_val = phy->ops.read_reg(hw,
 878                                         IGP01E1000_PHY_PORT_CONFIG, &data);
 879                         if (ret_val)
 880                                 goto out;
 881
 882                         data |= IGP01E1000_PSCFR_SMART_SPEED;
 883                         ret_val = phy->ops.write_reg(hw,
 884                                         IGP01E1000_PHY_PORT_CONFIG, data);
 885                         if (ret_val)
 886                                 goto out;
 887                 } else if (phy->smart_speed == e1000_smart_speed_off) {
 888                         ret_val = phy->ops.read_reg(hw,
 889                                         IGP01E1000_PHY_PORT_CONFIG, &data);
 890                         if (ret_val)
 891                                 goto out;
 892
 893                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 894                         ret_val = phy->ops.write_reg(hw,
 895                                         IGP01E1000_PHY_PORT_CONFIG, data);
 896                         if (ret_val)
 897                                 goto out;
 898                 }
 899         }
 900
 901 out:
 902         return ret_val;
 903 }
 904
 905 /**
 906  *  igb_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
 907  *  @hw: pointer to the HW structure
 908  *  @active: true to enable LPLU, false to disable
 909  *
 910  *  Sets the LPLU D0 state according to the active flag.  When
 911  *  activating LPLU this function also disables smart speed
 912  *  and vice versa.  LPLU will not be activated unless the
 913  *  device autonegotiation advertisement meets standards of
 914  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 915  *  This is a function pointer entry point only called by
 916  *  PHY setup routines.
 917  **/
 918 static s32 igb_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
 919 {
 920         struct e1000_phy_info *phy = &hw->phy;
 921         s32 ret_val = 0;
 922         u16 data;
 923
 924         data = rd32(E1000_82580_PHY_POWER_MGMT);
 925
 926         if (active) {
 927                 data |= E1000_82580_PM_D0_LPLU;
 928
 929                 /* When LPLU is enabled, we should disable SmartSpeed */
 930                 data &= ~E1000_82580_PM_SPD;
 931         } else {
 932                 data &= ~E1000_82580_PM_D0_LPLU;
 933
 934                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 935                  * during Dx states where the power conservation is most
 936                  * important.  During driver activity we should enable
 937                  * SmartSpeed, so performance is maintained.
 938                  */
 939                 if (phy->smart_speed == e1000_smart_speed_on)
 940                         data |= E1000_82580_PM_SPD;
 941                 else if (phy->smart_speed == e1000_smart_speed_off)
 942                         data &= ~E1000_82580_PM_SPD; }
 943
 944         wr32(E1000_82580_PHY_POWER_MGMT, data);
 945         return ret_val;
 946 }
 947
 948 /**
 949  *  igb_set_d3_lplu_state_82580 - Sets low power link up state for D3
 950  *  @hw: pointer to the HW structure
 951  *  @active: boolean used to enable/disable lplu
 952  *
 953  *  Success returns 0, Failure returns 1
 954  *
 955  *  The low power link up (lplu) state is set to the power management level D3
 956  *  and SmartSpeed is disabled when active is true, else clear lplu for D3
 957  *  and enable Smartspeed.  LPLU and Smartspeed are mutually exclusive.  LPLU
 958  *  is used during Dx states where the power conservation is most important.
 959  *  During driver activity, SmartSpeed should be enabled so performance is
 960  *  maintained.
 961  **/
 962 static s32 igb_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
 963 {
 964         struct e1000_phy_info *phy = &hw->phy;
 965         s32 ret_val = 0;
 966         u16 data;
 967
 968         data = rd32(E1000_82580_PHY_POWER_MGMT);
 969
 970         if (!active) {
 971                 data &= ~E1000_82580_PM_D3_LPLU;
 972                 /* LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 973                  * during Dx states where the power conservation is most
 974                  * important.  During driver activity we should enable
 975                  * SmartSpeed, so performance is maintained.
 976                  */
 977                 if (phy->smart_speed == e1000_smart_speed_on)
 978                         data |= E1000_82580_PM_SPD;
 979                 else if (phy->smart_speed == e1000_smart_speed_off)
 980                         data &= ~E1000_82580_PM_SPD;
 981         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
 982                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
 983                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
 984                 data |= E1000_82580_PM_D3_LPLU;
 985                 /* When LPLU is enabled, we should disable SmartSpeed */
 986                 data &= ~E1000_82580_PM_SPD;
 987         }
 988
 989         wr32(E1000_82580_PHY_POWER_MGMT, data);
 990         return ret_val;
 991 }
 992
 993 /**
 994  *  igb_acquire_nvm_82575 - Request for access to EEPROM
 995  *  @hw: pointer to the HW structure
 996  *
 997  *  Acquire the necessary semaphores for exclusive access to the EEPROM.
 998  *  Set the EEPROM access request bit and wait for EEPROM access grant bit.
 999  *  Return successful if access grant bit set, else clear the request for
1000  *  EEPROM access and return -E1000_ERR_NVM (-1).
1001  **/
1002 static s32 igb_acquire_nvm_82575(struct e1000_hw *hw)
1003 {
1004         s32 ret_val;
1005
1006         ret_val = hw->mac.ops.acquire_swfw_sync(hw, E1000_SWFW_EEP_SM);
1007         if (ret_val)
1008                 goto out;
1009
1010         ret_val = igb_acquire_nvm(hw);
1011
1012         if (ret_val)
1013                 hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM);
1014
1015 out:
1016         return ret_val;
1017 }
1018
1019 /**
1020  *  igb_release_nvm_82575 - Release exclusive access to EEPROM
1021  *  @hw: pointer to the HW structure
1022  *
1023  *  Stop any current commands to the EEPROM and clear the EEPROM request bit,
1024  *  then release the semaphores acquired.
1025  **/
1026 static void igb_release_nvm_82575(struct e1000_hw *hw)
1027 {
1028         igb_release_nvm(hw);
1029         hw->mac.ops.release_swfw_sync(hw, E1000_SWFW_EEP_SM);
1030 }
1031
1032 /**
1033  *  igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
1034  *  @hw: pointer to the HW structure
1035  *  @mask: specifies which semaphore to acquire
1036  *
1037  *  Acquire the SW/FW semaphore to access the PHY or NVM.  The mask
1038  *  will also specify which port we're acquiring the lock for.
1039  **/
1040 static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1041 {
1042         u32 swfw_sync;
1043         u32 swmask = mask;
1044         u32 fwmask = mask << 16;
1045         s32 ret_val = 0;
1046         s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
1047
1048         while (i < timeout) {
1049                 if (igb_get_hw_semaphore(hw)) {
1050                         ret_val = -E1000_ERR_SWFW_SYNC;
1051                         goto out;
1052                 }
1053
1054                 swfw_sync = rd32(E1000_SW_FW_SYNC);
1055                 if (!(swfw_sync & (fwmask | swmask)))
1056                         break;
1057
1058                 /* Firmware currently using resource (fwmask)
1059                  * or other software thread using resource (swmask)
1060                  */
1061                 igb_put_hw_semaphore(hw);
1062                 mdelay(5);
1063                 i++;
1064         }
1065
1066         if (i == timeout) {
1067                 hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
1068                 ret_val = -E1000_ERR_SWFW_SYNC;
1069                 goto out;
1070         }
1071
1072         swfw_sync |= swmask;
1073         wr32(E1000_SW_FW_SYNC, swfw_sync);
1074
1075         igb_put_hw_semaphore(hw);
1076
1077 out:
1078         return ret_val;
1079 }
1080
1081 /**
1082  *  igb_release_swfw_sync_82575 - Release SW/FW semaphore
1083  *  @hw: pointer to the HW structure
1084  *  @mask: specifies which semaphore to acquire
1085  *
1086  *  Release the SW/FW semaphore used to access the PHY or NVM.  The mask
1087  *  will also specify which port we're releasing the lock for.
1088  **/
1089 static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1090 {
1091         u32 swfw_sync;
1092
1093         while (igb_get_hw_semaphore(hw) != 0);
1094         /* Empty */
1095
1096         swfw_sync = rd32(E1000_SW_FW_SYNC);
1097         swfw_sync &= ~mask;
1098         wr32(E1000_SW_FW_SYNC, swfw_sync);
1099
1100         igb_put_hw_semaphore(hw);
1101 }
1102
1103 /**
1104  *  igb_get_cfg_done_82575 - Read config done bit
1105  *  @hw: pointer to the HW structure
1106  *
1107  *  Read the management control register for the config done bit for
1108  *  completion status.  NOTE: silicon which is EEPROM-less will fail trying
1109  *  to read the config done bit, so an error is *ONLY* logged and returns
1110  *  0.  If we were to return with error, EEPROM-less silicon
1111  *  would not be able to be reset or change link.
1112  **/
1113 static s32 igb_get_cfg_done_82575(struct e1000_hw *hw)
1114 {
1115         s32 timeout = PHY_CFG_TIMEOUT;
1116         s32 ret_val = 0;
1117         u32 mask = E1000_NVM_CFG_DONE_PORT_0;
1118
1119         if (hw->bus.func == 1)
1120                 mask = E1000_NVM_CFG_DONE_PORT_1;
1121         else if (hw->bus.func == E1000_FUNC_2)
1122                 mask = E1000_NVM_CFG_DONE_PORT_2;
1123         else if (hw->bus.func == E1000_FUNC_3)
1124                 mask = E1000_NVM_CFG_DONE_PORT_3;
1125
1126         while (timeout) {
1127                 if (rd32(E1000_EEMNGCTL) & mask)
1128                         break;
1129                 msleep(1);
1130                 timeout--;
1131         }
1132         if (!timeout)
1133                 hw_dbg("MNG configuration cycle has not completed.\n");
1134
1135         /* If EEPROM is not marked present, init the PHY manually */
1136         if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) &&
1137             (hw->phy.type == e1000_phy_igp_3))
1138                 igb_phy_init_script_igp3(hw);
1139
1140         return ret_val;
1141 }
1142
1143 /**
1144  *  igb_get_link_up_info_82575 - Get link speed/duplex info
1145  *  @hw: pointer to the HW structure
1146  *  @speed: stores the current speed
1147  *  @duplex: stores the current duplex
1148  *
1149  *  This is a wrapper function, if using the serial gigabit media independent
1150  *  interface, use PCS to retrieve the link speed and duplex information.
1151  *  Otherwise, use the generic function to get the link speed and duplex info.
1152  **/
1153 static s32 igb_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
1154                                         u16 *duplex)
1155 {
1156         s32 ret_val;
1157
1158         if (hw->phy.media_type != e1000_media_type_copper)
1159                 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, speed,
1160                                                                duplex);
1161         else
1162                 ret_val = igb_get_speed_and_duplex_copper(hw, speed,
1163                                                                     duplex);
1164
1165         return ret_val;
1166 }
1167
1168 /**
1169  *  igb_check_for_link_82575 - Check for link
1170  *  @hw: pointer to the HW structure
1171  *
1172  *  If sgmii is enabled, then use the pcs register to determine link, otherwise
1173  *  use the generic interface for determining link.
1174  **/
1175 static s32 igb_check_for_link_82575(struct e1000_hw *hw)
1176 {
1177         s32 ret_val;
1178         u16 speed, duplex;
1179
1180         if (hw->phy.media_type != e1000_media_type_copper) {
1181                 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed,
1182                                                              &duplex);
1183                 /* Use this flag to determine if link needs to be checked or
1184                  * not.  If  we have link clear the flag so that we do not
1185                  * continue to check for link.
1186                  */
1187                 hw->mac.get_link_status = !hw->mac.serdes_has_link;
1188
1189                 /* Configure Flow Control now that Auto-Neg has completed.
1190                  * First, we need to restore the desired flow control
1191                  * settings because we may have had to re-autoneg with a
1192                  * different link partner.
1193                  */
1194                 ret_val = igb_config_fc_after_link_up(hw);
1195                 if (ret_val)
1196                         hw_dbg("Error configuring flow control\n");
1197         } else {
1198                 ret_val = igb_check_for_copper_link(hw);
1199         }
1200
1201         return ret_val;
1202 }
1203
1204 /**
1205  *  igb_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1206  *  @hw: pointer to the HW structure
1207  **/
1208 void igb_power_up_serdes_link_82575(struct e1000_hw *hw)
1209 {
1210         u32 reg;
1211
1212
1213         if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1214             !igb_sgmii_active_82575(hw))
1215                 return;
1216
1217         /* Enable PCS to turn on link */
1218         reg = rd32(E1000_PCS_CFG0);
1219         reg |= E1000_PCS_CFG_PCS_EN;
1220         wr32(E1000_PCS_CFG0, reg);
1221
1222         /* Power up the laser */
1223         reg = rd32(E1000_CTRL_EXT);
1224         reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1225         wr32(E1000_CTRL_EXT, reg);
1226
1227         /* flush the write to verify completion */
1228         wrfl();
1229         msleep(1);
1230 }
1231
1232 /**
1233  *  igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
1234  *  @hw: pointer to the HW structure
1235  *  @speed: stores the current speed
1236  *  @duplex: stores the current duplex
1237  *
1238  *  Using the physical coding sub-layer (PCS), retrieve the current speed and
1239  *  duplex, then store the values in the pointers provided.
1240  **/
1241 static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed,
1242                                                 u16 *duplex)
1243 {
1244         struct e1000_mac_info *mac = &hw->mac;
1245         u32 pcs, status;
1246
1247         /* Set up defaults for the return values of this function */
1248         mac->serdes_has_link = false;
1249         *speed = 0;
1250         *duplex = 0;
1251
1252         /* Read the PCS Status register for link state. For non-copper mode,
1253          * the status register is not accurate. The PCS status register is
1254          * used instead.
1255          */
1256         pcs = rd32(E1000_PCS_LSTAT);
1257
1258         /* The link up bit determines when link is up on autoneg. The sync ok
1259          * gets set once both sides sync up and agree upon link. Stable link
1260          * can be determined by checking for both link up and link sync ok
1261          */
1262         if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) {
1263                 mac->serdes_has_link = true;
1264
1265                 /* Detect and store PCS speed */
1266                 if (pcs & E1000_PCS_LSTS_SPEED_1000)
1267                         *speed = SPEED_1000;
1268                 else if (pcs & E1000_PCS_LSTS_SPEED_100)
1269                         *speed = SPEED_100;
1270                 else
1271                         *speed = SPEED_10;
1272
1273                 /* Detect and store PCS duplex */
1274                 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL)
1275                         *duplex = FULL_DUPLEX;
1276                 else
1277                         *duplex = HALF_DUPLEX;
1278
1279         /* Check if it is an I354 2.5Gb backplane connection. */
1280                 if (mac->type == e1000_i354) {
1281                         status = rd32(E1000_STATUS);
1282                         if ((status & E1000_STATUS_2P5_SKU) &&
1283                             !(status & E1000_STATUS_2P5_SKU_OVER)) {
1284                                 *speed = SPEED_2500;
1285                                 *duplex = FULL_DUPLEX;
1286                                 hw_dbg("2500 Mbs, ");
1287                                 hw_dbg("Full Duplex\n");
1288                         }
1289                 }
1290
1291         }
1292
1293         return 0;
1294 }
1295
1296 /**
1297  *  igb_shutdown_serdes_link_82575 - Remove link during power down
1298  *  @hw: pointer to the HW structure
1299  *
1300  *  In the case of fiber serdes, shut down optics and PCS on driver unload
1301  *  when management pass thru is not enabled.
1302  **/
1303 void igb_shutdown_serdes_link_82575(struct e1000_hw *hw)
1304 {
1305         u32 reg;
1306
1307         if (hw->phy.media_type != e1000_media_type_internal_serdes &&
1308             igb_sgmii_active_82575(hw))
1309                 return;
1310
1311         if (!igb_enable_mng_pass_thru(hw)) {
1312                 /* Disable PCS to turn off link */
1313                 reg = rd32(E1000_PCS_CFG0);
1314                 reg &= ~E1000_PCS_CFG_PCS_EN;
1315                 wr32(E1000_PCS_CFG0, reg);
1316
1317                 /* shutdown the laser */
1318                 reg = rd32(E1000_CTRL_EXT);
1319                 reg |= E1000_CTRL_EXT_SDP3_DATA;
1320                 wr32(E1000_CTRL_EXT, reg);
1321
1322                 /* flush the write to verify completion */
1323                 wrfl();
1324                 msleep(1);
1325         }
1326 }
1327
1328 /**
1329  *  igb_reset_hw_82575 - Reset hardware
1330  *  @hw: pointer to the HW structure
1331  *
1332  *  This resets the hardware into a known state.  This is a
1333  *  function pointer entry point called by the api module.
1334  **/
1335 static s32 igb_reset_hw_82575(struct e1000_hw *hw)
1336 {
1337         u32 ctrl;
1338         s32 ret_val;
1339
1340         /* Prevent the PCI-E bus from sticking if there is no TLP connection
1341          * on the last TLP read/write transaction when MAC is reset.
1342          */
1343         ret_val = igb_disable_pcie_master(hw);
1344         if (ret_val)
1345                 hw_dbg("PCI-E Master disable polling has failed.\n");
1346
1347         /* set the completion timeout for interface */
1348         ret_val = igb_set_pcie_completion_timeout(hw);
1349         if (ret_val) {
1350                 hw_dbg("PCI-E Set completion timeout has failed.\n");
1351         }
1352
1353         hw_dbg("Masking off all interrupts\n");
1354         wr32(E1000_IMC, 0xffffffff);
1355
1356         wr32(E1000_RCTL, 0);
1357         wr32(E1000_TCTL, E1000_TCTL_PSP);
1358         wrfl();
1359
1360         msleep(10);
1361
1362         ctrl = rd32(E1000_CTRL);
1363
1364         hw_dbg("Issuing a global reset to MAC\n");
1365         wr32(E1000_CTRL, ctrl | E1000_CTRL_RST);
1366
1367         ret_val = igb_get_auto_rd_done(hw);
1368         if (ret_val) {
1369                 /* When auto config read does not complete, do not
1370                  * return with an error. This can happen in situations
1371                  * where there is no eeprom and prevents getting link.
1372                  */
1373                 hw_dbg("Auto Read Done did not complete\n");
1374         }
1375
1376         /* If EEPROM is not present, run manual init scripts */
1377         if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0)
1378                 igb_reset_init_script_82575(hw);
1379
1380         /* Clear any pending interrupt events. */
1381         wr32(E1000_IMC, 0xffffffff);
1382         rd32(E1000_ICR);
1383
1384         /* Install any alternate MAC address into RAR0 */
1385         ret_val = igb_check_alt_mac_addr(hw);
1386
1387         return ret_val;
1388 }
1389
1390 /**
1391  *  igb_init_hw_82575 - Initialize hardware
1392  *  @hw: pointer to the HW structure
1393  *
1394  *  This inits the hardware readying it for operation.
1395  **/
1396 static s32 igb_init_hw_82575(struct e1000_hw *hw)
1397 {
1398         struct e1000_mac_info *mac = &hw->mac;
1399         s32 ret_val;
1400         u16 i, rar_count = mac->rar_entry_count;
1401
1402         /* Initialize identification LED */
1403         ret_val = igb_id_led_init(hw);
1404         if (ret_val) {
1405                 hw_dbg("Error initializing identification LED\n");
1406                 /* This is not fatal and we should not stop init due to this */
1407         }
1408
1409         /* Disabling VLAN filtering */
1410         hw_dbg("Initializing the IEEE VLAN\n");
1411         if ((hw->mac.type == e1000_i350) || (hw->mac.type == e1000_i354))
1412                 igb_clear_vfta_i350(hw);
1413         else
1414                 igb_clear_vfta(hw);
1415
1416         /* Setup the receive address */
1417         igb_init_rx_addrs(hw, rar_count);
1418
1419         /* Zero out the Multicast HASH table */
1420         hw_dbg("Zeroing the MTA\n");
1421         for (i = 0; i < mac->mta_reg_count; i++)
1422                 array_wr32(E1000_MTA, i, 0);
1423
1424         /* Zero out the Unicast HASH table */
1425         hw_dbg("Zeroing the UTA\n");
1426         for (i = 0; i < mac->uta_reg_count; i++)
1427                 array_wr32(E1000_UTA, i, 0);
1428
1429         /* Setup link and flow control */
1430         ret_val = igb_setup_link(hw);
1431
1432         /* Clear all of the statistics registers (clear on read).  It is
1433          * important that we do this after we have tried to establish link
1434          * because the symbol error count will increment wildly if there
1435          * is no link.
1436          */
1437         igb_clear_hw_cntrs_82575(hw);
1438         return ret_val;
1439 }
1440
1441 /**
1442  *  igb_setup_copper_link_82575 - Configure copper link settings
1443  *  @hw: pointer to the HW structure
1444  *
1445  *  Configures the link for auto-neg or forced speed and duplex.  Then we check
1446  *  for link, once link is established calls to configure collision distance
1447  *  and flow control are called.
1448  **/
1449 static s32 igb_setup_copper_link_82575(struct e1000_hw *hw)
1450 {
1451         u32 ctrl;
1452         s32  ret_val;
1453         u32 phpm_reg;
1454
1455         ctrl = rd32(E1000_CTRL);
1456         ctrl |= E1000_CTRL_SLU;
1457         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1458         wr32(E1000_CTRL, ctrl);
1459
1460         /* Clear Go Link Disconnect bit on supported devices */
1461         switch (hw->mac.type) {
1462         case e1000_82580:
1463         case e1000_i350:
1464         case e1000_i210:
1465         case e1000_i211:
1466                 phpm_reg = rd32(E1000_82580_PHY_POWER_MGMT);
1467                 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1468                 wr32(E1000_82580_PHY_POWER_MGMT, phpm_reg);
1469                 break;
1470         default:
1471                 break;
1472         }
1473
1474         ret_val = igb_setup_serdes_link_82575(hw);
1475         if (ret_val)
1476                 goto out;
1477
1478         if (igb_sgmii_active_82575(hw) && !hw->phy.reset_disable) {
1479                 /* allow time for SFP cage time to power up phy */
1480                 msleep(300);
1481
1482                 ret_val = hw->phy.ops.reset(hw);
1483                 if (ret_val) {
1484                         hw_dbg("Error resetting the PHY.\n");
1485                         goto out;
1486                 }
1487         }
1488         switch (hw->phy.type) {
1489         case e1000_phy_i210:
1490         case e1000_phy_m88:
1491                 switch (hw->phy.id) {
1492                 case I347AT4_E_PHY_ID:
1493                 case M88E1112_E_PHY_ID:
1494                 case M88E1543_E_PHY_ID:
1495                 case I210_I_PHY_ID:
1496                         ret_val = igb_copper_link_setup_m88_gen2(hw);
1497                         break;
1498                 default:
1499                         ret_val = igb_copper_link_setup_m88(hw);
1500                         break;
1501                 }
1502                 break;
1503         case e1000_phy_igp_3:
1504                 ret_val = igb_copper_link_setup_igp(hw);
1505                 break;
1506         case e1000_phy_82580:
1507                 ret_val = igb_copper_link_setup_82580(hw);
1508                 break;
1509         default:
1510                 ret_val = -E1000_ERR_PHY;
1511                 break;
1512         }
1513
1514         if (ret_val)
1515                 goto out;
1516
1517         ret_val = igb_setup_copper_link(hw);
1518 out:
1519         return ret_val;
1520 }
1521
1522 /**
1523  *  igb_setup_serdes_link_82575 - Setup link for serdes
1524  *  @hw: pointer to the HW structure
1525  *
1526  *  Configure the physical coding sub-layer (PCS) link.  The PCS link is
1527  *  used on copper connections where the serialized gigabit media independent
1528  *  interface (sgmii), or serdes fiber is being used.  Configures the link
1529  *  for auto-negotiation or forces speed/duplex.
1530  **/
1531 static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw)
1532 {
1533         u32 ctrl_ext, ctrl_reg, reg, anadv_reg;
1534         bool pcs_autoneg;
1535         s32 ret_val = E1000_SUCCESS;
1536         u16 data;
1537
1538         if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1539             !igb_sgmii_active_82575(hw))
1540                 return ret_val;
1541
1542
1543         /* On the 82575, SerDes loopback mode persists until it is
1544          * explicitly turned off or a power cycle is performed.  A read to
1545          * the register does not indicate its status.  Therefore, we ensure
1546          * loopback mode is disabled during initialization.
1547          */
1548         wr32(E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1549
1550         /* power on the sfp cage if present and turn on I2C */
1551         ctrl_ext = rd32(E1000_CTRL_EXT);
1552         ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1553         ctrl_ext |= E1000_CTRL_I2C_ENA;
1554         wr32(E1000_CTRL_EXT, ctrl_ext);
1555
1556         ctrl_reg = rd32(E1000_CTRL);
1557         ctrl_reg |= E1000_CTRL_SLU;
1558
1559         if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) {
1560                 /* set both sw defined pins */
1561                 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1562
1563                 /* Set switch control to serdes energy detect */
1564                 reg = rd32(E1000_CONNSW);
1565                 reg |= E1000_CONNSW_ENRGSRC;
1566                 wr32(E1000_CONNSW, reg);
1567         }
1568
1569         reg = rd32(E1000_PCS_LCTL);
1570
1571         /* default pcs_autoneg to the same setting as mac autoneg */
1572         pcs_autoneg = hw->mac.autoneg;
1573
1574         switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1575         case E1000_CTRL_EXT_LINK_MODE_SGMII:
1576                 /* sgmii mode lets the phy handle forcing speed/duplex */
1577                 pcs_autoneg = true;
1578                 /* autoneg time out should be disabled for SGMII mode */
1579                 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1580                 break;
1581         case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1582                 /* disable PCS autoneg and support parallel detect only */
1583                 pcs_autoneg = false;
1584         default:
1585                 if (hw->mac.type == e1000_82575 ||
1586                     hw->mac.type == e1000_82576) {
1587                         ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1588                         if (ret_val) {
1589                                 printk(KERN_DEBUG "NVM Read Error\n\n");
1590                                 return ret_val;
1591                         }
1592
1593                         if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)
1594                                 pcs_autoneg = false;
1595                 }
1596
1597                 /* non-SGMII modes only supports a speed of 1000/Full for the
1598                  * link so it is best to just force the MAC and let the pcs
1599                  * link either autoneg or be forced to 1000/Full
1600                  */
1601                 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1602                             E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1603
1604                 /* set speed of 1000/Full if speed/duplex is forced */
1605                 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1606                 break;
1607         }
1608
1609         wr32(E1000_CTRL, ctrl_reg);
1610
1611         /* New SerDes mode allows for forcing speed or autonegotiating speed
1612          * at 1gb. Autoneg should be default set by most drivers. This is the
1613          * mode that will be compatible with older link partners and switches.
1614          * However, both are supported by the hardware and some drivers/tools.
1615          */
1616         reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1617                 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1618
1619         if (pcs_autoneg) {
1620                 /* Set PCS register for autoneg */
1621                 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1622                        E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1623
1624                 /* Disable force flow control for autoneg */
1625                 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL;
1626
1627                 /* Configure flow control advertisement for autoneg */
1628                 anadv_reg = rd32(E1000_PCS_ANADV);
1629                 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE);
1630                 switch (hw->fc.requested_mode) {
1631                 case e1000_fc_full:
1632                 case e1000_fc_rx_pause:
1633                         anadv_reg |= E1000_TXCW_ASM_DIR;
1634                         anadv_reg |= E1000_TXCW_PAUSE;
1635                         break;
1636                 case e1000_fc_tx_pause:
1637                         anadv_reg |= E1000_TXCW_ASM_DIR;
1638                         break;
1639                 default:
1640                         break;
1641                 }
1642                 wr32(E1000_PCS_ANADV, anadv_reg);
1643
1644                 hw_dbg("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
1645         } else {
1646                 /* Set PCS register for forced link */
1647                 reg |= E1000_PCS_LCTL_FSD;        /* Force Speed */
1648
1649                 /* Force flow control for forced link */
1650                 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1651
1652                 hw_dbg("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
1653         }
1654
1655         wr32(E1000_PCS_LCTL, reg);
1656
1657         if (!pcs_autoneg && !igb_sgmii_active_82575(hw))
1658                 igb_force_mac_fc(hw);
1659
1660         return ret_val;
1661 }
1662
1663 /**
1664  *  igb_sgmii_active_82575 - Return sgmii state
1665  *  @hw: pointer to the HW structure
1666  *
1667  *  82575 silicon has a serialized gigabit media independent interface (sgmii)
1668  *  which can be enabled for use in the embedded applications.  Simply
1669  *  return the current state of the sgmii interface.
1670  **/
1671 static bool igb_sgmii_active_82575(struct e1000_hw *hw)
1672 {
1673         struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1674         return dev_spec->sgmii_active;
1675 }
1676
1677 /**
1678  *  igb_reset_init_script_82575 - Inits HW defaults after reset
1679  *  @hw: pointer to the HW structure
1680  *
1681  *  Inits recommended HW defaults after a reset when there is no EEPROM
1682  *  detected. This is only for the 82575.
1683  **/
1684 static s32 igb_reset_init_script_82575(struct e1000_hw *hw)
1685 {
1686         if (hw->mac.type == e1000_82575) {
1687                 hw_dbg("Running reset init script for 82575\n");
1688                 /* SerDes configuration via SERDESCTRL */
1689                 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C);
1690                 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78);
1691                 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x1B, 0x23);
1692                 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x23, 0x15);
1693
1694                 /* CCM configuration via CCMCTL register */
1695                 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x14, 0x00);
1696                 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x10, 0x00);
1697
1698                 /* PCIe lanes configuration */
1699                 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x00, 0xEC);
1700                 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x61, 0xDF);
1701                 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x34, 0x05);
1702                 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x2F, 0x81);
1703
1704                 /* PCIe PLL Configuration */
1705                 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x02, 0x47);
1706                 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x14, 0x00);
1707                 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x10, 0x00);
1708         }
1709
1710         return 0;
1711 }
1712
1713 /**
1714  *  igb_read_mac_addr_82575 - Read device MAC address
1715  *  @hw: pointer to the HW structure
1716  **/
1717 static s32 igb_read_mac_addr_82575(struct e1000_hw *hw)
1718 {
1719         s32 ret_val = 0;
1720
1721         /* If there's an alternate MAC address place it in RAR0
1722          * so that it will override the Si installed default perm
1723          * address.
1724          */
1725         ret_val = igb_check_alt_mac_addr(hw);
1726         if (ret_val)
1727                 goto out;
1728
1729         ret_val = igb_read_mac_addr(hw);
1730
1731 out:
1732         return ret_val;
1733 }
1734
1735 /**
1736  * igb_power_down_phy_copper_82575 - Remove link during PHY power down
1737  * @hw: pointer to the HW structure
1738  *
1739  * In the case of a PHY power down to save power, or to turn off link during a
1740  * driver unload, or wake on lan is not enabled, remove the link.
1741  **/
1742 void igb_power_down_phy_copper_82575(struct e1000_hw *hw)
1743 {
1744         /* If the management interface is not enabled, then power down */
1745         if (!(igb_enable_mng_pass_thru(hw) || igb_check_reset_block(hw)))
1746                 igb_power_down_phy_copper(hw);
1747 }
1748
1749 /**
1750  *  igb_clear_hw_cntrs_82575 - Clear device specific hardware counters
1751  *  @hw: pointer to the HW structure
1752  *
1753  *  Clears the hardware counters by reading the counter registers.
1754  **/
1755 static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw)
1756 {
1757         igb_clear_hw_cntrs_base(hw);
1758
1759         rd32(E1000_PRC64);
1760         rd32(E1000_PRC127);
1761         rd32(E1000_PRC255);
1762         rd32(E1000_PRC511);
1763         rd32(E1000_PRC1023);
1764         rd32(E1000_PRC1522);
1765         rd32(E1000_PTC64);
1766         rd32(E1000_PTC127);
1767         rd32(E1000_PTC255);
1768         rd32(E1000_PTC511);
1769         rd32(E1000_PTC1023);
1770         rd32(E1000_PTC1522);
1771
1772         rd32(E1000_ALGNERRC);
1773         rd32(E1000_RXERRC);
1774         rd32(E1000_TNCRS);
1775         rd32(E1000_CEXTERR);
1776         rd32(E1000_TSCTC);
1777         rd32(E1000_TSCTFC);
1778
1779         rd32(E1000_MGTPRC);
1780         rd32(E1000_MGTPDC);
1781         rd32(E1000_MGTPTC);
1782
1783         rd32(E1000_IAC);
1784         rd32(E1000_ICRXOC);
1785
1786         rd32(E1000_ICRXPTC);
1787         rd32(E1000_ICRXATC);
1788         rd32(E1000_ICTXPTC);
1789         rd32(E1000_ICTXATC);
1790         rd32(E1000_ICTXQEC);
1791         rd32(E1000_ICTXQMTC);
1792         rd32(E1000_ICRXDMTC);
1793
1794         rd32(E1000_CBTMPC);
1795         rd32(E1000_HTDPMC);
1796         rd32(E1000_CBRMPC);
1797         rd32(E1000_RPTHC);
1798         rd32(E1000_HGPTC);
1799         rd32(E1000_HTCBDPC);
1800         rd32(E1000_HGORCL);
1801         rd32(E1000_HGORCH);
1802         rd32(E1000_HGOTCL);
1803         rd32(E1000_HGOTCH);
1804         rd32(E1000_LENERRS);
1805
1806         /* This register should not be read in copper configurations */
1807         if (hw->phy.media_type == e1000_media_type_internal_serdes ||
1808             igb_sgmii_active_82575(hw))
1809                 rd32(E1000_SCVPC);
1810 }
1811
1812 /**
1813  *  igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable
1814  *  @hw: pointer to the HW structure
1815  *
1816  *  After rx enable if managability is enabled then there is likely some
1817  *  bad data at the start of the fifo and possibly in the DMA fifo.  This
1818  *  function clears the fifos and flushes any packets that came in as rx was
1819  *  being enabled.
1820  **/
1821 void igb_rx_fifo_flush_82575(struct e1000_hw *hw)
1822 {
1823         u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
1824         int i, ms_wait;
1825
1826         if (hw->mac.type != e1000_82575 ||
1827             !(rd32(E1000_MANC) & E1000_MANC_RCV_TCO_EN))
1828                 return;
1829
1830         /* Disable all RX queues */
1831         for (i = 0; i < 4; i++) {
1832                 rxdctl[i] = rd32(E1000_RXDCTL(i));
1833                 wr32(E1000_RXDCTL(i),
1834                      rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
1835         }
1836         /* Poll all queues to verify they have shut down */
1837         for (ms_wait = 0; ms_wait < 10; ms_wait++) {
1838                 msleep(1);
1839                 rx_enabled = 0;
1840                 for (i = 0; i < 4; i++)
1841                         rx_enabled |= rd32(E1000_RXDCTL(i));
1842                 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
1843                         break;
1844         }
1845
1846         if (ms_wait == 10)
1847                 hw_dbg("Queue disable timed out after 10ms\n");
1848
1849         /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
1850          * incoming packets are rejected.  Set enable and wait 2ms so that
1851          * any packet that was coming in as RCTL.EN was set is flushed
1852          */
1853         rfctl = rd32(E1000_RFCTL);
1854         wr32(E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
1855
1856         rlpml = rd32(E1000_RLPML);
1857         wr32(E1000_RLPML, 0);
1858
1859         rctl = rd32(E1000_RCTL);
1860         temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
1861         temp_rctl |= E1000_RCTL_LPE;
1862
1863         wr32(E1000_RCTL, temp_rctl);
1864         wr32(E1000_RCTL, temp_rctl | E1000_RCTL_EN);
1865         wrfl();
1866         msleep(2);
1867
1868         /* Enable RX queues that were previously enabled and restore our
1869          * previous state
1870          */
1871         for (i = 0; i < 4; i++)
1872                 wr32(E1000_RXDCTL(i), rxdctl[i]);
1873         wr32(E1000_RCTL, rctl);
1874         wrfl();
1875
1876         wr32(E1000_RLPML, rlpml);
1877         wr32(E1000_RFCTL, rfctl);
1878
1879         /* Flush receive errors generated by workaround */
1880         rd32(E1000_ROC);
1881         rd32(E1000_RNBC);
1882         rd32(E1000_MPC);
1883 }
1884
1885 /**
1886  *  igb_set_pcie_completion_timeout - set pci-e completion timeout
1887  *  @hw: pointer to the HW structure
1888  *
1889  *  The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
1890  *  however the hardware default for these parts is 500us to 1ms which is less
1891  *  than the 10ms recommended by the pci-e spec.  To address this we need to
1892  *  increase the value to either 10ms to 200ms for capability version 1 config,
1893  *  or 16ms to 55ms for version 2.
1894  **/
1895 static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw)
1896 {
1897         u32 gcr = rd32(E1000_GCR);
1898         s32 ret_val = 0;
1899         u16 pcie_devctl2;
1900
1901         /* only take action if timeout value is defaulted to 0 */
1902         if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
1903                 goto out;
1904
1905         /* if capabilities version is type 1 we can write the
1906          * timeout of 10ms to 200ms through the GCR register
1907          */
1908         if (!(gcr & E1000_GCR_CAP_VER2)) {
1909                 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
1910                 goto out;
1911         }
1912
1913         /* for version 2 capabilities we need to write the config space
1914          * directly in order to set the completion timeout value for
1915          * 16ms to 55ms
1916          */
1917         ret_val = igb_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
1918                                         &pcie_devctl2);
1919         if (ret_val)
1920                 goto out;
1921
1922         pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
1923
1924         ret_val = igb_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
1925                                          &pcie_devctl2);
1926 out:
1927         /* disable completion timeout resend */
1928         gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
1929
1930         wr32(E1000_GCR, gcr);
1931         return ret_val;
1932 }
1933
1934 /**
1935  *  igb_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
1936  *  @hw: pointer to the hardware struct
1937  *  @enable: state to enter, either enabled or disabled
1938  *  @pf: Physical Function pool - do not set anti-spoofing for the PF
1939  *
1940  *  enables/disables L2 switch anti-spoofing functionality.
1941  **/
1942 void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
1943 {
1944         u32 reg_val, reg_offset;
1945
1946         switch (hw->mac.type) {
1947         case e1000_82576:
1948                 reg_offset = E1000_DTXSWC;
1949                 break;
1950         case e1000_i350:
1951         case e1000_i354:
1952                 reg_offset = E1000_TXSWC;
1953                 break;
1954         default:
1955                 return;
1956         }
1957
1958         reg_val = rd32(reg_offset);
1959         if (enable) {
1960                 reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK |
1961                              E1000_DTXSWC_VLAN_SPOOF_MASK);
1962                 /* The PF can spoof - it has to in order to
1963                  * support emulation mode NICs
1964                  */
1965                 reg_val ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
1966         } else {
1967                 reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
1968                              E1000_DTXSWC_VLAN_SPOOF_MASK);
1969         }
1970         wr32(reg_offset, reg_val);
1971 }
1972
1973 /**
1974  *  igb_vmdq_set_loopback_pf - enable or disable vmdq loopback
1975  *  @hw: pointer to the hardware struct
1976  *  @enable: state to enter, either enabled or disabled
1977  *
1978  *  enables/disables L2 switch loopback functionality.
1979  **/
1980 void igb_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
1981 {
1982         u32 dtxswc;
1983
1984         switch (hw->mac.type) {
1985         case e1000_82576:
1986                 dtxswc = rd32(E1000_DTXSWC);
1987                 if (enable)
1988                         dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1989                 else
1990                         dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1991                 wr32(E1000_DTXSWC, dtxswc);
1992                 break;
1993         case e1000_i354:
1994         case e1000_i350:
1995                 dtxswc = rd32(E1000_TXSWC);
1996                 if (enable)
1997                         dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1998                 else
1999                         dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2000                 wr32(E1000_TXSWC, dtxswc);
2001                 break;
2002         default:
2003                 /* Currently no other hardware supports loopback */
2004                 break;
2005         }
2006
2007 }
2008
2009 /**
2010  *  igb_vmdq_set_replication_pf - enable or disable vmdq replication
2011  *  @hw: pointer to the hardware struct
2012  *  @enable: state to enter, either enabled or disabled
2013  *
2014  *  enables/disables replication of packets across multiple pools.
2015  **/
2016 void igb_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
2017 {
2018         u32 vt_ctl = rd32(E1000_VT_CTL);
2019
2020         if (enable)
2021                 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
2022         else
2023                 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
2024
2025         wr32(E1000_VT_CTL, vt_ctl);
2026 }
2027
2028 /**
2029  *  igb_read_phy_reg_82580 - Read 82580 MDI control register
2030  *  @hw: pointer to the HW structure
2031  *  @offset: register offset to be read
2032  *  @data: pointer to the read data
2033  *
2034  *  Reads the MDI control register in the PHY at offset and stores the
2035  *  information read to data.
2036  **/
2037 static s32 igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
2038 {
2039         s32 ret_val;
2040
2041         ret_val = hw->phy.ops.acquire(hw);
2042         if (ret_val)
2043                 goto out;
2044
2045         ret_val = igb_read_phy_reg_mdic(hw, offset, data);
2046
2047         hw->phy.ops.release(hw);
2048
2049 out:
2050         return ret_val;
2051 }
2052
2053 /**
2054  *  igb_write_phy_reg_82580 - Write 82580 MDI control register
2055  *  @hw: pointer to the HW structure
2056  *  @offset: register offset to write to
2057  *  @data: data to write to register at offset
2058  *
2059  *  Writes data to MDI control register in the PHY at offset.
2060  **/
2061 static s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
2062 {
2063         s32 ret_val;
2064
2065
2066         ret_val = hw->phy.ops.acquire(hw);
2067         if (ret_val)
2068                 goto out;
2069
2070         ret_val = igb_write_phy_reg_mdic(hw, offset, data);
2071
2072         hw->phy.ops.release(hw);
2073
2074 out:
2075         return ret_val;
2076 }
2077
2078 /**
2079  *  igb_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
2080  *  @hw: pointer to the HW structure
2081  *
2082  *  This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
2083  *  the values found in the EEPROM.  This addresses an issue in which these
2084  *  bits are not restored from EEPROM after reset.
2085  **/
2086 static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw)
2087 {
2088         s32 ret_val = 0;
2089         u32 mdicnfg;
2090         u16 nvm_data = 0;
2091
2092         if (hw->mac.type != e1000_82580)
2093                 goto out;
2094         if (!igb_sgmii_active_82575(hw))
2095                 goto out;
2096
2097         ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2098                                    NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2099                                    &nvm_data);
2100         if (ret_val) {
2101                 hw_dbg("NVM Read Error\n");
2102                 goto out;
2103         }
2104
2105         mdicnfg = rd32(E1000_MDICNFG);
2106         if (nvm_data & NVM_WORD24_EXT_MDIO)
2107                 mdicnfg |= E1000_MDICNFG_EXT_MDIO;
2108         if (nvm_data & NVM_WORD24_COM_MDIO)
2109                 mdicnfg |= E1000_MDICNFG_COM_MDIO;
2110         wr32(E1000_MDICNFG, mdicnfg);
2111 out:
2112         return ret_val;
2113 }
2114
2115 /**
2116  *  igb_reset_hw_82580 - Reset hardware
2117  *  @hw: pointer to the HW structure
2118  *
2119  *  This resets function or entire device (all ports, etc.)
2120  *  to a known state.
2121  **/
2122 static s32 igb_reset_hw_82580(struct e1000_hw *hw)
2123 {
2124         s32 ret_val = 0;
2125         /* BH SW mailbox bit in SW_FW_SYNC */
2126         u16 swmbsw_mask = E1000_SW_SYNCH_MB;
2127         u32 ctrl;
2128         bool global_device_reset = hw->dev_spec._82575.global_device_reset;
2129
2130         hw->dev_spec._82575.global_device_reset = false;
2131
2132         /* due to hw errata, global device reset doesn't always
2133          * work on 82580
2134          */
2135         if (hw->mac.type == e1000_82580)
2136                 global_device_reset = false;
2137
2138         /* Get current control state. */
2139         ctrl = rd32(E1000_CTRL);
2140
2141         /* Prevent the PCI-E bus from sticking if there is no TLP connection
2142          * on the last TLP read/write transaction when MAC is reset.
2143          */
2144         ret_val = igb_disable_pcie_master(hw);
2145         if (ret_val)
2146                 hw_dbg("PCI-E Master disable polling has failed.\n");
2147
2148         hw_dbg("Masking off all interrupts\n");
2149         wr32(E1000_IMC, 0xffffffff);
2150         wr32(E1000_RCTL, 0);
2151         wr32(E1000_TCTL, E1000_TCTL_PSP);
2152         wrfl();
2153
2154         msleep(10);
2155
2156         /* Determine whether or not a global dev reset is requested */
2157         if (global_device_reset &&
2158                 hw->mac.ops.acquire_swfw_sync(hw, swmbsw_mask))
2159                         global_device_reset = false;
2160
2161         if (global_device_reset &&
2162                 !(rd32(E1000_STATUS) & E1000_STAT_DEV_RST_SET))
2163                 ctrl |= E1000_CTRL_DEV_RST;
2164         else
2165                 ctrl |= E1000_CTRL_RST;
2166
2167         wr32(E1000_CTRL, ctrl);
2168         wrfl();
2169
2170         /* Add delay to insure DEV_RST has time to complete */
2171         if (global_device_reset)
2172                 msleep(5);
2173
2174         ret_val = igb_get_auto_rd_done(hw);
2175         if (ret_val) {
2176                 /* When auto config read does not complete, do not
2177                  * return with an error. This can happen in situations
2178                  * where there is no eeprom and prevents getting link.
2179                  */
2180                 hw_dbg("Auto Read Done did not complete\n");
2181         }
2182
2183         /* clear global device reset status bit */
2184         wr32(E1000_STATUS, E1000_STAT_DEV_RST_SET);
2185
2186         /* Clear any pending interrupt events. */
2187         wr32(E1000_IMC, 0xffffffff);
2188         rd32(E1000_ICR);
2189
2190         ret_val = igb_reset_mdicnfg_82580(hw);
2191         if (ret_val)
2192                 hw_dbg("Could not reset MDICNFG based on EEPROM\n");
2193
2194         /* Install any alternate MAC address into RAR0 */
2195         ret_val = igb_check_alt_mac_addr(hw);
2196
2197         /* Release semaphore */
2198         if (global_device_reset)
2199                 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
2200
2201         return ret_val;
2202 }
2203
2204 /**
2205  *  igb_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size
2206  *  @data: data received by reading RXPBS register
2207  *
2208  *  The 82580 uses a table based approach for packet buffer allocation sizes.
2209  *  This function converts the retrieved value into the correct table value
2210  *     0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
2211  *  0x0 36  72 144   1   2   4   8  16
2212  *  0x8 35  70 140 rsv rsv rsv rsv rsv
2213  */
2214 u16 igb_rxpbs_adjust_82580(u32 data)
2215 {
2216         u16 ret_val = 0;
2217
2218         if (data < E1000_82580_RXPBS_TABLE_SIZE)
2219                 ret_val = e1000_82580_rxpbs_table[data];
2220
2221         return ret_val;
2222 }
2223
2224 /**
2225  *  igb_validate_nvm_checksum_with_offset - Validate EEPROM
2226  *  checksum
2227  *  @hw: pointer to the HW structure
2228  *  @offset: offset in words of the checksum protected region
2229  *
2230  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2231  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
2232  **/
2233 static s32 igb_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
2234                                                  u16 offset)
2235 {
2236         s32 ret_val = 0;
2237         u16 checksum = 0;
2238         u16 i, nvm_data;
2239
2240         for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
2241                 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2242                 if (ret_val) {
2243                         hw_dbg("NVM Read Error\n");
2244                         goto out;
2245                 }
2246                 checksum += nvm_data;
2247         }
2248
2249         if (checksum != (u16) NVM_SUM) {
2250                 hw_dbg("NVM Checksum Invalid\n");
2251                 ret_val = -E1000_ERR_NVM;
2252                 goto out;
2253         }
2254
2255 out:
2256         return ret_val;
2257 }
2258
2259 /**
2260  *  igb_update_nvm_checksum_with_offset - Update EEPROM
2261  *  checksum
2262  *  @hw: pointer to the HW structure
2263  *  @offset: offset in words of the checksum protected region
2264  *
2265  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
2266  *  up to the checksum.  Then calculates the EEPROM checksum and writes the
2267  *  value to the EEPROM.
2268  **/
2269 static s32 igb_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2270 {
2271         s32 ret_val;
2272         u16 checksum = 0;
2273         u16 i, nvm_data;
2274
2275         for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
2276                 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2277                 if (ret_val) {
2278                         hw_dbg("NVM Read Error while updating checksum.\n");
2279                         goto out;
2280                 }
2281                 checksum += nvm_data;
2282         }
2283         checksum = (u16) NVM_SUM - checksum;
2284         ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2285                                 &checksum);
2286         if (ret_val)
2287                 hw_dbg("NVM Write Error while updating checksum.\n");
2288
2289 out:
2290         return ret_val;
2291 }
2292
2293 /**
2294  *  igb_validate_nvm_checksum_82580 - Validate EEPROM checksum
2295  *  @hw: pointer to the HW structure
2296  *
2297  *  Calculates the EEPROM section checksum by reading/adding each word of
2298  *  the EEPROM and then verifies that the sum of the EEPROM is
2299  *  equal to 0xBABA.
2300  **/
2301 static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw)
2302 {
2303         s32 ret_val = 0;
2304         u16 eeprom_regions_count = 1;
2305         u16 j, nvm_data;
2306         u16 nvm_offset;
2307
2308         ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2309         if (ret_val) {
2310                 hw_dbg("NVM Read Error\n");
2311                 goto out;
2312         }
2313
2314         if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
2315                 /* if checksums compatibility bit is set validate checksums
2316                  * for all 4 ports.
2317                  */
2318                 eeprom_regions_count = 4;
2319         }
2320
2321         for (j = 0; j < eeprom_regions_count; j++) {
2322                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2323                 ret_val = igb_validate_nvm_checksum_with_offset(hw,
2324                                                                 nvm_offset);
2325                 if (ret_val != 0)
2326                         goto out;
2327         }
2328
2329 out:
2330         return ret_val;
2331 }
2332
2333 /**
2334  *  igb_update_nvm_checksum_82580 - Update EEPROM checksum
2335  *  @hw: pointer to the HW structure
2336  *
2337  *  Updates the EEPROM section checksums for all 4 ports by reading/adding
2338  *  each word of the EEPROM up to the checksum.  Then calculates the EEPROM
2339  *  checksum and writes the value to the EEPROM.
2340  **/
2341 static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw)
2342 {
2343         s32 ret_val;
2344         u16 j, nvm_data;
2345         u16 nvm_offset;
2346
2347         ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2348         if (ret_val) {
2349                 hw_dbg("NVM Read Error while updating checksum"
2350                         " compatibility bit.\n");
2351                 goto out;
2352         }
2353
2354         if ((nvm_data & NVM_COMPATIBILITY_BIT_MASK) == 0) {
2355                 /* set compatibility bit to validate checksums appropriately */
2356                 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2357                 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2358                                         &nvm_data);
2359                 if (ret_val) {
2360                         hw_dbg("NVM Write Error while updating checksum"
2361                                 " compatibility bit.\n");
2362                         goto out;
2363                 }
2364         }
2365
2366         for (j = 0; j < 4; j++) {
2367                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2368                 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
2369                 if (ret_val)
2370                         goto out;
2371         }
2372
2373 out:
2374         return ret_val;
2375 }
2376
2377 /**
2378  *  igb_validate_nvm_checksum_i350 - Validate EEPROM checksum
2379  *  @hw: pointer to the HW structure
2380  *
2381  *  Calculates the EEPROM section checksum by reading/adding each word of
2382  *  the EEPROM and then verifies that the sum of the EEPROM is
2383  *  equal to 0xBABA.
2384  **/
2385 static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw)
2386 {
2387         s32 ret_val = 0;
2388         u16 j;
2389         u16 nvm_offset;
2390
2391         for (j = 0; j < 4; j++) {
2392                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2393                 ret_val = igb_validate_nvm_checksum_with_offset(hw,
2394                                                                 nvm_offset);
2395                 if (ret_val != 0)
2396                         goto out;
2397         }
2398
2399 out:
2400         return ret_val;
2401 }
2402
2403 /**
2404  *  igb_update_nvm_checksum_i350 - Update EEPROM checksum
2405  *  @hw: pointer to the HW structure
2406  *
2407  *  Updates the EEPROM section checksums for all 4 ports by reading/adding
2408  *  each word of the EEPROM up to the checksum.  Then calculates the EEPROM
2409  *  checksum and writes the value to the EEPROM.
2410  **/
2411 static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw)
2412 {
2413         s32 ret_val = 0;
2414         u16 j;
2415         u16 nvm_offset;
2416
2417         for (j = 0; j < 4; j++) {
2418                 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2419                 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset);
2420                 if (ret_val != 0)
2421                         goto out;
2422         }
2423
2424 out:
2425         return ret_val;
2426 }
2427
2428 /**
2429  *  __igb_access_emi_reg - Read/write EMI register
2430  *  @hw: pointer to the HW structure
2431  *  @addr: EMI address to program
2432  *  @data: pointer to value to read/write from/to the EMI address
2433  *  @read: boolean flag to indicate read or write
2434  **/
2435 static s32 __igb_access_emi_reg(struct e1000_hw *hw, u16 address,
2436                                   u16 *data, bool read)
2437 {
2438         s32 ret_val = E1000_SUCCESS;
2439
2440         ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address);
2441         if (ret_val)
2442                 return ret_val;
2443
2444         if (read)
2445                 ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data);
2446         else
2447                 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data);
2448
2449         return ret_val;
2450 }
2451
2452 /**
2453  *  igb_read_emi_reg - Read Extended Management Interface register
2454  *  @hw: pointer to the HW structure
2455  *  @addr: EMI address to program
2456  *  @data: value to be read from the EMI address
2457  **/
2458 s32 igb_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data)
2459 {
2460         return __igb_access_emi_reg(hw, addr, data, true);
2461 }
2462
2463 /**
2464  *  igb_set_eee_i350 - Enable/disable EEE support
2465  *  @hw: pointer to the HW structure
2466  *
2467  *  Enable/disable EEE based on setting in dev_spec structure.
2468  *
2469  **/
2470 s32 igb_set_eee_i350(struct e1000_hw *hw)
2471 {
2472         s32 ret_val = 0;
2473         u32 ipcnfg, eeer;
2474
2475         if ((hw->mac.type < e1000_i350) ||
2476             (hw->phy.media_type != e1000_media_type_copper))
2477                 goto out;
2478         ipcnfg = rd32(E1000_IPCNFG);
2479         eeer = rd32(E1000_EEER);
2480
2481         /* enable or disable per user setting */
2482         if (!(hw->dev_spec._82575.eee_disable)) {
2483                 u32 eee_su = rd32(E1000_EEE_SU);
2484
2485                 ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2486                 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2487                         E1000_EEER_LPI_FC);
2488
2489                 /* This bit should not be set in normal operation. */
2490                 if (eee_su & E1000_EEE_SU_LPI_CLK_STP)
2491                         hw_dbg("LPI Clock Stop Bit should not be set!\n");
2492
2493         } else {
2494                 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN |
2495                         E1000_IPCNFG_EEE_100M_AN);
2496                 eeer &= ~(E1000_EEER_TX_LPI_EN |
2497                         E1000_EEER_RX_LPI_EN |
2498                         E1000_EEER_LPI_FC);
2499         }
2500         wr32(E1000_IPCNFG, ipcnfg);
2501         wr32(E1000_EEER, eeer);
2502         rd32(E1000_IPCNFG);
2503         rd32(E1000_EEER);
2504 out:
2505
2506         return ret_val;
2507 }
2508
2509 /**
2510  *  igb_set_eee_i354 - Enable/disable EEE support
2511  *  @hw: pointer to the HW structure
2512  *
2513  *  Enable/disable EEE legacy mode based on setting in dev_spec structure.
2514  *
2515  **/
2516 s32 igb_set_eee_i354(struct e1000_hw *hw)
2517 {
2518         struct e1000_phy_info *phy = &hw->phy;
2519         s32 ret_val = 0;
2520         u16 phy_data;
2521
2522         if ((hw->phy.media_type != e1000_media_type_copper) ||
2523             (phy->id != M88E1543_E_PHY_ID))
2524                 goto out;
2525
2526         if (!hw->dev_spec._82575.eee_disable) {
2527                 /* Switch to PHY page 18. */
2528                 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18);
2529                 if (ret_val)
2530                         goto out;
2531
2532                 ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2533                                             &phy_data);
2534                 if (ret_val)
2535                         goto out;
2536
2537                 phy_data |= E1000_M88E1543_EEE_CTRL_1_MS;
2538                 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2539                                              phy_data);
2540                 if (ret_val)
2541                         goto out;
2542
2543                 /* Return the PHY to page 0. */
2544                 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2545                 if (ret_val)
2546                         goto out;
2547
2548                 /* Turn on EEE advertisement. */
2549                 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2550                                              E1000_EEE_ADV_DEV_I354,
2551                                              &phy_data);
2552                 if (ret_val)
2553                         goto out;
2554
2555                 phy_data |= E1000_EEE_ADV_100_SUPPORTED |
2556                             E1000_EEE_ADV_1000_SUPPORTED;
2557                 ret_val = igb_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2558                                                 E1000_EEE_ADV_DEV_I354,
2559                                                 phy_data);
2560         } else {
2561                 /* Turn off EEE advertisement. */
2562                 ret_val = igb_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2563                                              E1000_EEE_ADV_DEV_I354,
2564                                              &phy_data);
2565                 if (ret_val)
2566                         goto out;
2567
2568                 phy_data &= ~(E1000_EEE_ADV_100_SUPPORTED |
2569                               E1000_EEE_ADV_1000_SUPPORTED);
2570                 ret_val = igb_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2571                                               E1000_EEE_ADV_DEV_I354,
2572                                               phy_data);
2573         }
2574
2575 out:
2576         return ret_val;
2577 }
2578
2579 /**
2580  *  igb_get_eee_status_i354 - Get EEE status
2581  *  @hw: pointer to the HW structure
2582  *  @status: EEE status
2583  *
2584  *  Get EEE status by guessing based on whether Tx or Rx LPI indications have
2585  *  been received.
2586  **/
2587 s32 igb_get_eee_status_i354(struct e1000_hw *hw, bool *status)
2588 {
2589         struct e1000_phy_info *phy = &hw->phy;
2590         s32 ret_val = 0;
2591         u16 phy_data;
2592
2593         /* Check if EEE is supported on this device. */
2594         if ((hw->phy.media_type != e1000_media_type_copper) ||
2595             (phy->id != M88E1543_E_PHY_ID))
2596                 goto out;
2597
2598         ret_val = igb_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354,
2599                                      E1000_PCS_STATUS_DEV_I354,
2600                                      &phy_data);
2601         if (ret_val)
2602                 goto out;
2603
2604         *status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD |
2605                               E1000_PCS_STATUS_RX_LPI_RCVD) ? true : false;
2606
2607 out:
2608         return ret_val;
2609 }
2610
2611 static const u8 e1000_emc_temp_data[4] = {
2612         E1000_EMC_INTERNAL_DATA,
2613         E1000_EMC_DIODE1_DATA,
2614         E1000_EMC_DIODE2_DATA,
2615         E1000_EMC_DIODE3_DATA
2616 };
2617 static const u8 e1000_emc_therm_limit[4] = {
2618         E1000_EMC_INTERNAL_THERM_LIMIT,
2619         E1000_EMC_DIODE1_THERM_LIMIT,
2620         E1000_EMC_DIODE2_THERM_LIMIT,
2621         E1000_EMC_DIODE3_THERM_LIMIT
2622 };
2623
2624 /**
2625  *  igb_get_thermal_sensor_data_generic - Gathers thermal sensor data
2626  *  @hw: pointer to hardware structure
2627  *
2628  *  Updates the temperatures in mac.thermal_sensor_data
2629  **/
2630 s32 igb_get_thermal_sensor_data_generic(struct e1000_hw *hw)
2631 {
2632         s32 status = E1000_SUCCESS;
2633         u16 ets_offset;
2634         u16 ets_cfg;
2635         u16 ets_sensor;
2636         u8  num_sensors;
2637         u8  sensor_index;
2638         u8  sensor_location;
2639         u8  i;
2640         struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
2641
2642         if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0))
2643                 return E1000_NOT_IMPLEMENTED;
2644
2645         data->sensor[0].temp = (rd32(E1000_THMJT) & 0xFF);
2646
2647         /* Return the internal sensor only if ETS is unsupported */
2648         hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset);
2649         if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
2650                 return status;
2651
2652         hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg);
2653         if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT)
2654             != NVM_ETS_TYPE_EMC)
2655                 return E1000_NOT_IMPLEMENTED;
2656
2657         num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK);
2658         if (num_sensors > E1000_MAX_SENSORS)
2659                 num_sensors = E1000_MAX_SENSORS;
2660
2661         for (i = 1; i < num_sensors; i++) {
2662                 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor);
2663                 sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >>
2664                                 NVM_ETS_DATA_INDEX_SHIFT);
2665                 sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >>
2666                                    NVM_ETS_DATA_LOC_SHIFT);
2667
2668                 if (sensor_location != 0)
2669                         hw->phy.ops.read_i2c_byte(hw,
2670                                         e1000_emc_temp_data[sensor_index],
2671                                         E1000_I2C_THERMAL_SENSOR_ADDR,
2672                                         &data->sensor[i].temp);
2673         }
2674         return status;
2675 }
2676
2677 /**
2678  *  igb_init_thermal_sensor_thresh_generic - Sets thermal sensor thresholds
2679  *  @hw: pointer to hardware structure
2680  *
2681  *  Sets the thermal sensor thresholds according to the NVM map
2682  *  and save off the threshold and location values into mac.thermal_sensor_data
2683  **/
2684 s32 igb_init_thermal_sensor_thresh_generic(struct e1000_hw *hw)
2685 {
2686         s32 status = E1000_SUCCESS;
2687         u16 ets_offset;
2688         u16 ets_cfg;
2689         u16 ets_sensor;
2690         u8  low_thresh_delta;
2691         u8  num_sensors;
2692         u8  sensor_index;
2693         u8  sensor_location;
2694         u8  therm_limit;
2695         u8  i;
2696         struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
2697
2698         if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0))
2699                 return E1000_NOT_IMPLEMENTED;
2700
2701         memset(data, 0, sizeof(struct e1000_thermal_sensor_data));
2702
2703         data->sensor[0].location = 0x1;
2704         data->sensor[0].caution_thresh =
2705                 (rd32(E1000_THHIGHTC) & 0xFF);
2706         data->sensor[0].max_op_thresh =
2707                 (rd32(E1000_THLOWTC) & 0xFF);
2708
2709         /* Return the internal sensor only if ETS is unsupported */
2710         hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_offset);
2711         if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
2712                 return status;
2713
2714         hw->nvm.ops.read(hw, ets_offset, 1, &ets_cfg);
2715         if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT)
2716             != NVM_ETS_TYPE_EMC)
2717                 return E1000_NOT_IMPLEMENTED;
2718
2719         low_thresh_delta = ((ets_cfg & NVM_ETS_LTHRES_DELTA_MASK) >>
2720                             NVM_ETS_LTHRES_DELTA_SHIFT);
2721         num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK);
2722
2723         for (i = 1; i <= num_sensors; i++) {
2724                 hw->nvm.ops.read(hw, (ets_offset + i), 1, &ets_sensor);
2725                 sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >>
2726                                 NVM_ETS_DATA_INDEX_SHIFT);
2727                 sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >>
2728                                    NVM_ETS_DATA_LOC_SHIFT);
2729                 therm_limit = ets_sensor & NVM_ETS_DATA_HTHRESH_MASK;
2730
2731                 hw->phy.ops.write_i2c_byte(hw,
2732                         e1000_emc_therm_limit[sensor_index],
2733                         E1000_I2C_THERMAL_SENSOR_ADDR,
2734                         therm_limit);
2735
2736                 if ((i < E1000_MAX_SENSORS) && (sensor_location != 0)) {
2737                         data->sensor[i].location = sensor_location;
2738                         data->sensor[i].caution_thresh = therm_limit;
2739                         data->sensor[i].max_op_thresh = therm_limit -
2740                                                         low_thresh_delta;
2741                 }
2742         }
2743         return status;
2744 }
2745
2746 static struct e1000_mac_operations e1000_mac_ops_82575 = {
2747         .init_hw              = igb_init_hw_82575,
2748         .check_for_link       = igb_check_for_link_82575,
2749         .rar_set              = igb_rar_set,
2750         .read_mac_addr        = igb_read_mac_addr_82575,
2751         .get_speed_and_duplex = igb_get_link_up_info_82575,
2752 #ifdef CONFIG_IGB_HWMON
2753         .get_thermal_sensor_data = igb_get_thermal_sensor_data_generic,
2754         .init_thermal_sensor_thresh = igb_init_thermal_sensor_thresh_generic,
2755 #endif
2756 };
2757
2758 static struct e1000_phy_operations e1000_phy_ops_82575 = {
2759         .acquire              = igb_acquire_phy_82575,
2760         .get_cfg_done         = igb_get_cfg_done_82575,
2761         .release              = igb_release_phy_82575,
2762         .write_i2c_byte       = igb_write_i2c_byte,
2763         .read_i2c_byte        = igb_read_i2c_byte,
2764 };
2765
2766 static struct e1000_nvm_operations e1000_nvm_ops_82575 = {
2767         .acquire              = igb_acquire_nvm_82575,
2768         .read                 = igb_read_nvm_eerd,
2769         .release              = igb_release_nvm_82575,
2770         .write                = igb_write_nvm_spi,
2771 };
2772
2773 const struct e1000_info e1000_82575_info = {
2774         .get_invariants = igb_get_invariants_82575,
2775         .mac_ops = &e1000_mac_ops_82575,
2776         .phy_ops = &e1000_phy_ops_82575,
2777         .nvm_ops = &e1000_nvm_ops_82575,
2778 };
2779