1 /* PTP Hardware Clock (PHC) driver for the Intel 82576 and 82580
3 * Copyright (C) 2011 Richard Cochran <richardcochran@gmail.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, see <http://www.gnu.org/licenses/>.
18 #include <linux/module.h>
19 #include <linux/device.h>
20 #include <linux/pci.h>
21 #include <linux/ptp_classify.h>
25 #define INCVALUE_MASK 0x7fffffff
26 #define ISGN 0x80000000
28 /* The 82580 timesync updates the system timer every 8ns by 8ns,
29 * and this update value cannot be reprogrammed.
31 * Neither the 82576 nor the 82580 offer registers wide enough to hold
32 * nanoseconds time values for very long. For the 82580, SYSTIM always
33 * counts nanoseconds, but the upper 24 bits are not availible. The
34 * frequency is adjusted by changing the 32 bit fractional nanoseconds
37 * For the 82576, the SYSTIM register time unit is affect by the
38 * choice of the 24 bit TININCA:IV (incvalue) field. Five bits of this
39 * field are needed to provide the nominal 16 nanosecond period,
40 * leaving 19 bits for fractional nanoseconds.
42 * We scale the NIC clock cycle by a large factor so that relatively
43 * small clock corrections can be added or subtracted at each clock
44 * tick. The drawbacks of a large factor are a) that the clock
45 * register overflows more quickly (not such a big deal) and b) that
46 * the increment per tick has to fit into 24 bits. As a result we
47 * need to use a shift of 19 so we can fit a value of 16 into the
52 * +--------------+ +---+---+------+
53 * 82576 | 32 | | 8 | 5 | 19 |
54 * +--------------+ +---+---+------+
55 * \________ 45 bits _______/ fract
57 * +----------+---+ +--------------+
58 * 82580 | 24 | 8 | | 32 |
59 * +----------+---+ +--------------+
60 * reserved \______ 40 bits _____/
63 * The 45 bit 82576 SYSTIM overflows every
64 * 2^45 * 10^-9 / 3600 = 9.77 hours.
66 * The 40 bit 82580 SYSTIM overflows every
67 * 2^40 * 10^-9 / 60 = 18.3 minutes.
70 #define IGB_SYSTIM_OVERFLOW_PERIOD (HZ * 60 * 9)
71 #define IGB_PTP_TX_TIMEOUT (HZ * 15)
72 #define INCPERIOD_82576 (1 << E1000_TIMINCA_16NS_SHIFT)
73 #define INCVALUE_82576_MASK ((1 << E1000_TIMINCA_16NS_SHIFT) - 1)
74 #define INCVALUE_82576 (16 << IGB_82576_TSYNC_SHIFT)
75 #define IGB_NBITS_82580 40
77 static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter);
79 /* SYSTIM read access for the 82576 */
80 static cycle_t igb_ptp_read_82576(const struct cyclecounter *cc)
82 struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc);
83 struct e1000_hw *hw = &igb->hw;
87 lo = rd32(E1000_SYSTIML);
88 hi = rd32(E1000_SYSTIMH);
90 val = ((u64) hi) << 32;
96 /* SYSTIM read access for the 82580 */
97 static cycle_t igb_ptp_read_82580(const struct cyclecounter *cc)
99 struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc);
100 struct e1000_hw *hw = &igb->hw;
104 /* The timestamp latches on lowest register read. For the 82580
105 * the lowest register is SYSTIMR instead of SYSTIML. However we only
106 * need to provide nanosecond resolution, so we just ignore it.
109 lo = rd32(E1000_SYSTIML);
110 hi = rd32(E1000_SYSTIMH);
112 val = ((u64) hi) << 32;
118 /* SYSTIM read access for I210/I211 */
119 static void igb_ptp_read_i210(struct igb_adapter *adapter, struct timespec *ts)
121 struct e1000_hw *hw = &adapter->hw;
124 /* The timestamp latches on lowest register read. For I210/I211, the
125 * lowest register is SYSTIMR. Since we only need to provide nanosecond
126 * resolution, we can ignore it.
129 nsec = rd32(E1000_SYSTIML);
130 sec = rd32(E1000_SYSTIMH);
136 static void igb_ptp_write_i210(struct igb_adapter *adapter,
137 const struct timespec *ts)
139 struct e1000_hw *hw = &adapter->hw;
141 /* Writing the SYSTIMR register is not necessary as it only provides
142 * sub-nanosecond resolution.
144 wr32(E1000_SYSTIML, ts->tv_nsec);
145 wr32(E1000_SYSTIMH, ts->tv_sec);
149 * igb_ptp_systim_to_hwtstamp - convert system time value to hw timestamp
150 * @adapter: board private structure
151 * @hwtstamps: timestamp structure to update
152 * @systim: unsigned 64bit system time value.
154 * We need to convert the system time value stored in the RX/TXSTMP registers
155 * into a hwtstamp which can be used by the upper level timestamping functions.
157 * The 'tmreg_lock' spinlock is used to protect the consistency of the
158 * system time value. This is needed because reading the 64 bit time
159 * value involves reading two (or three) 32 bit registers. The first
160 * read latches the value. Ditto for writing.
162 * In addition, here have extended the system time with an overflow
163 * counter in software.
165 static void igb_ptp_systim_to_hwtstamp(struct igb_adapter *adapter,
166 struct skb_shared_hwtstamps *hwtstamps,
172 switch (adapter->hw.mac.type) {
177 spin_lock_irqsave(&adapter->tmreg_lock, flags);
179 ns = timecounter_cyc2time(&adapter->tc, systim);
181 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
183 memset(hwtstamps, 0, sizeof(*hwtstamps));
184 hwtstamps->hwtstamp = ns_to_ktime(ns);
188 memset(hwtstamps, 0, sizeof(*hwtstamps));
189 /* Upper 32 bits contain s, lower 32 bits contain ns. */
190 hwtstamps->hwtstamp = ktime_set(systim >> 32,
191 systim & 0xFFFFFFFF);
198 /* PTP clock operations */
199 static int igb_ptp_adjfreq_82576(struct ptp_clock_info *ptp, s32 ppb)
201 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
203 struct e1000_hw *hw = &igb->hw;
214 rate = div_u64(rate, 1953125);
216 incvalue = 16 << IGB_82576_TSYNC_SHIFT;
223 wr32(E1000_TIMINCA, INCPERIOD_82576 | (incvalue & INCVALUE_82576_MASK));
228 static int igb_ptp_adjfreq_82580(struct ptp_clock_info *ptp, s32 ppb)
230 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
232 struct e1000_hw *hw = &igb->hw;
243 rate = div_u64(rate, 1953125);
245 inca = rate & INCVALUE_MASK;
249 wr32(E1000_TIMINCA, inca);
254 static int igb_ptp_adjtime_82576(struct ptp_clock_info *ptp, s64 delta)
256 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
261 spin_lock_irqsave(&igb->tmreg_lock, flags);
263 now = timecounter_read(&igb->tc);
265 timecounter_init(&igb->tc, &igb->cc, now);
267 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
272 static int igb_ptp_adjtime_i210(struct ptp_clock_info *ptp, s64 delta)
274 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
277 struct timespec now, then = ns_to_timespec(delta);
279 spin_lock_irqsave(&igb->tmreg_lock, flags);
281 igb_ptp_read_i210(igb, &now);
282 now = timespec_add(now, then);
283 igb_ptp_write_i210(igb, (const struct timespec *)&now);
285 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
290 static int igb_ptp_gettime_82576(struct ptp_clock_info *ptp,
293 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
299 spin_lock_irqsave(&igb->tmreg_lock, flags);
301 ns = timecounter_read(&igb->tc);
303 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
305 ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder);
306 ts->tv_nsec = remainder;
311 static int igb_ptp_gettime_i210(struct ptp_clock_info *ptp,
314 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
318 spin_lock_irqsave(&igb->tmreg_lock, flags);
320 igb_ptp_read_i210(igb, ts);
322 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
327 static int igb_ptp_settime_82576(struct ptp_clock_info *ptp,
328 const struct timespec *ts)
330 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
335 ns = ts->tv_sec * 1000000000ULL;
338 spin_lock_irqsave(&igb->tmreg_lock, flags);
340 timecounter_init(&igb->tc, &igb->cc, ns);
342 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
347 static int igb_ptp_settime_i210(struct ptp_clock_info *ptp,
348 const struct timespec *ts)
350 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
354 spin_lock_irqsave(&igb->tmreg_lock, flags);
356 igb_ptp_write_i210(igb, ts);
358 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
363 static int igb_ptp_enable(struct ptp_clock_info *ptp,
364 struct ptp_clock_request *rq, int on)
371 * @work: pointer to work struct
373 * This work function polls the TSYNCTXCTL valid bit to determine when a
374 * timestamp has been taken for the current stored skb.
376 static void igb_ptp_tx_work(struct work_struct *work)
378 struct igb_adapter *adapter = container_of(work, struct igb_adapter,
380 struct e1000_hw *hw = &adapter->hw;
383 if (!adapter->ptp_tx_skb)
386 if (time_is_before_jiffies(adapter->ptp_tx_start +
387 IGB_PTP_TX_TIMEOUT)) {
388 dev_kfree_skb_any(adapter->ptp_tx_skb);
389 adapter->ptp_tx_skb = NULL;
390 adapter->tx_hwtstamp_timeouts++;
391 dev_warn(&adapter->pdev->dev, "clearing Tx timestamp hang");
395 tsynctxctl = rd32(E1000_TSYNCTXCTL);
396 if (tsynctxctl & E1000_TSYNCTXCTL_VALID)
397 igb_ptp_tx_hwtstamp(adapter);
399 /* reschedule to check later */
400 schedule_work(&adapter->ptp_tx_work);
403 static void igb_ptp_overflow_check(struct work_struct *work)
405 struct igb_adapter *igb =
406 container_of(work, struct igb_adapter, ptp_overflow_work.work);
409 igb->ptp_caps.gettime(&igb->ptp_caps, &ts);
411 pr_debug("igb overflow check at %ld.%09lu\n", ts.tv_sec, ts.tv_nsec);
413 schedule_delayed_work(&igb->ptp_overflow_work,
414 IGB_SYSTIM_OVERFLOW_PERIOD);
418 * igb_ptp_rx_hang - detect error case when Rx timestamp registers latched
419 * @adapter: private network adapter structure
421 * This watchdog task is scheduled to detect error case where hardware has
422 * dropped an Rx packet that was timestamped when the ring is full. The
423 * particular error is rare but leaves the device in a state unable to timestamp
424 * any future packets.
426 void igb_ptp_rx_hang(struct igb_adapter *adapter)
428 struct e1000_hw *hw = &adapter->hw;
429 struct igb_ring *rx_ring;
430 u32 tsyncrxctl = rd32(E1000_TSYNCRXCTL);
431 unsigned long rx_event;
434 if (hw->mac.type != e1000_82576)
437 /* If we don't have a valid timestamp in the registers, just update the
438 * timeout counter and exit
440 if (!(tsyncrxctl & E1000_TSYNCRXCTL_VALID)) {
441 adapter->last_rx_ptp_check = jiffies;
445 /* Determine the most recent watchdog or rx_timestamp event */
446 rx_event = adapter->last_rx_ptp_check;
447 for (n = 0; n < adapter->num_rx_queues; n++) {
448 rx_ring = adapter->rx_ring[n];
449 if (time_after(rx_ring->last_rx_timestamp, rx_event))
450 rx_event = rx_ring->last_rx_timestamp;
453 /* Only need to read the high RXSTMP register to clear the lock */
454 if (time_is_before_jiffies(rx_event + 5 * HZ)) {
456 adapter->last_rx_ptp_check = jiffies;
457 adapter->rx_hwtstamp_cleared++;
458 dev_warn(&adapter->pdev->dev, "clearing Rx timestamp hang");
463 * igb_ptp_tx_hwtstamp - utility function which checks for TX time stamp
464 * @adapter: Board private structure.
466 * If we were asked to do hardware stamping and such a time stamp is
467 * available, then it must have been for this skb here because we only
468 * allow only one such packet into the queue.
470 static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter)
472 struct e1000_hw *hw = &adapter->hw;
473 struct skb_shared_hwtstamps shhwtstamps;
476 regval = rd32(E1000_TXSTMPL);
477 regval |= (u64)rd32(E1000_TXSTMPH) << 32;
479 igb_ptp_systim_to_hwtstamp(adapter, &shhwtstamps, regval);
480 skb_tstamp_tx(adapter->ptp_tx_skb, &shhwtstamps);
481 dev_kfree_skb_any(adapter->ptp_tx_skb);
482 adapter->ptp_tx_skb = NULL;
486 * igb_ptp_rx_pktstamp - retrieve Rx per packet timestamp
487 * @q_vector: Pointer to interrupt specific structure
488 * @va: Pointer to address containing Rx buffer
489 * @skb: Buffer containing timestamp and packet
491 * This function is meant to retrieve a timestamp from the first buffer of an
492 * incoming frame. The value is stored in little endian format starting on
495 void igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector,
499 __le64 *regval = (__le64 *)va;
501 /* The timestamp is recorded in little endian format.
503 * Field: Reserved Reserved SYSTIML SYSTIMH
505 igb_ptp_systim_to_hwtstamp(q_vector->adapter, skb_hwtstamps(skb),
506 le64_to_cpu(regval[1]));
510 * igb_ptp_rx_rgtstamp - retrieve Rx timestamp stored in register
511 * @q_vector: Pointer to interrupt specific structure
512 * @skb: Buffer containing timestamp and packet
514 * This function is meant to retrieve a timestamp from the internal registers
515 * of the adapter and store it in the skb.
517 void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector,
520 struct igb_adapter *adapter = q_vector->adapter;
521 struct e1000_hw *hw = &adapter->hw;
524 /* If this bit is set, then the RX registers contain the time stamp. No
525 * other packet will be time stamped until we read these registers, so
526 * read the registers to make them available again. Because only one
527 * packet can be time stamped at a time, we know that the register
528 * values must belong to this one here and therefore we don't need to
529 * compare any of the additional attributes stored for it.
531 * If nothing went wrong, then it should have a shared tx_flags that we
532 * can turn into a skb_shared_hwtstamps.
534 if (!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
537 regval = rd32(E1000_RXSTMPL);
538 regval |= (u64)rd32(E1000_RXSTMPH) << 32;
540 igb_ptp_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), regval);
544 * igb_ptp_hwtstamp_ioctl - control hardware time stamping
549 * Outgoing time stamping can be enabled and disabled. Play nice and
550 * disable it when requested, although it shouldn't case any overhead
551 * when no packet needs it. At most one packet in the queue may be
552 * marked for time stamping, otherwise it would be impossible to tell
553 * for sure to which packet the hardware time stamp belongs.
555 * Incoming time stamping has to be configured via the hardware
556 * filters. Not all combinations are supported, in particular event
557 * type has to be specified. Matching the kind of event packet is
558 * not supported, with the exception of "all V2 events regardless of
561 int igb_ptp_hwtstamp_ioctl(struct net_device *netdev,
562 struct ifreq *ifr, int cmd)
564 struct igb_adapter *adapter = netdev_priv(netdev);
565 struct e1000_hw *hw = &adapter->hw;
566 struct hwtstamp_config config;
567 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
568 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
569 u32 tsync_rx_cfg = 0;
574 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
577 /* reserved for future extensions */
581 switch (config.tx_type) {
582 case HWTSTAMP_TX_OFF:
590 switch (config.rx_filter) {
591 case HWTSTAMP_FILTER_NONE:
594 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
595 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
596 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
599 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
600 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
601 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
604 case HWTSTAMP_FILTER_PTP_V2_EVENT:
605 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
606 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
607 case HWTSTAMP_FILTER_PTP_V2_SYNC:
608 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
609 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
610 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
611 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
612 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
613 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;
614 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
618 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
619 case HWTSTAMP_FILTER_ALL:
620 /* 82576 cannot timestamp all packets, which it needs to do to
621 * support both V1 Sync and Delay_Req messages
623 if (hw->mac.type != e1000_82576) {
624 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
625 config.rx_filter = HWTSTAMP_FILTER_ALL;
630 config.rx_filter = HWTSTAMP_FILTER_NONE;
634 if (hw->mac.type == e1000_82575) {
635 if (tsync_rx_ctl | tsync_tx_ctl)
640 /* Per-packet timestamping only works if all packets are
641 * timestamped, so enable timestamping in all packets as
642 * long as one Rx filter was configured.
644 if ((hw->mac.type >= e1000_82580) && tsync_rx_ctl) {
645 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
646 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
647 config.rx_filter = HWTSTAMP_FILTER_ALL;
651 if ((hw->mac.type == e1000_i210) ||
652 (hw->mac.type == e1000_i211)) {
653 regval = rd32(E1000_RXPBS);
654 regval |= E1000_RXPBS_CFG_TS_EN;
655 wr32(E1000_RXPBS, regval);
659 /* enable/disable TX */
660 regval = rd32(E1000_TSYNCTXCTL);
661 regval &= ~E1000_TSYNCTXCTL_ENABLED;
662 regval |= tsync_tx_ctl;
663 wr32(E1000_TSYNCTXCTL, regval);
665 /* enable/disable RX */
666 regval = rd32(E1000_TSYNCRXCTL);
667 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
668 regval |= tsync_rx_ctl;
669 wr32(E1000_TSYNCRXCTL, regval);
671 /* define which PTP packets are time stamped */
672 wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
674 /* define ethertype filter for timestamped packets */
677 (E1000_ETQF_FILTER_ENABLE | /* enable filter */
678 E1000_ETQF_1588 | /* enable timestamping */
679 ETH_P_1588)); /* 1588 eth protocol type */
681 wr32(E1000_ETQF(3), 0);
683 /* L4 Queue Filter[3]: filter by destination port and protocol */
685 u32 ftqf = (IPPROTO_UDP /* UDP */
686 | E1000_FTQF_VF_BP /* VF not compared */
687 | E1000_FTQF_1588_TIME_STAMP /* Enable Timestamping */
688 | E1000_FTQF_MASK); /* mask all inputs */
689 ftqf &= ~E1000_FTQF_MASK_PROTO_BP; /* enable protocol check */
691 wr32(E1000_IMIR(3), htons(PTP_EV_PORT));
692 wr32(E1000_IMIREXT(3),
693 (E1000_IMIREXT_SIZE_BP | E1000_IMIREXT_CTRL_BP));
694 if (hw->mac.type == e1000_82576) {
695 /* enable source port check */
696 wr32(E1000_SPQF(3), htons(PTP_EV_PORT));
697 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
699 wr32(E1000_FTQF(3), ftqf);
701 wr32(E1000_FTQF(3), E1000_FTQF_MASK);
705 /* clear TX/RX time stamp registers, just to be sure */
706 regval = rd32(E1000_TXSTMPL);
707 regval = rd32(E1000_TXSTMPH);
708 regval = rd32(E1000_RXSTMPL);
709 regval = rd32(E1000_RXSTMPH);
711 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
715 void igb_ptp_init(struct igb_adapter *adapter)
717 struct e1000_hw *hw = &adapter->hw;
718 struct net_device *netdev = adapter->netdev;
720 switch (hw->mac.type) {
722 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
723 adapter->ptp_caps.owner = THIS_MODULE;
724 adapter->ptp_caps.max_adj = 999999881;
725 adapter->ptp_caps.n_ext_ts = 0;
726 adapter->ptp_caps.pps = 0;
727 adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82576;
728 adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576;
729 adapter->ptp_caps.gettime = igb_ptp_gettime_82576;
730 adapter->ptp_caps.settime = igb_ptp_settime_82576;
731 adapter->ptp_caps.enable = igb_ptp_enable;
732 adapter->cc.read = igb_ptp_read_82576;
733 adapter->cc.mask = CLOCKSOURCE_MASK(64);
734 adapter->cc.mult = 1;
735 adapter->cc.shift = IGB_82576_TSYNC_SHIFT;
736 /* Dial the nominal frequency. */
737 wr32(E1000_TIMINCA, INCPERIOD_82576 | INCVALUE_82576);
742 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
743 adapter->ptp_caps.owner = THIS_MODULE;
744 adapter->ptp_caps.max_adj = 62499999;
745 adapter->ptp_caps.n_ext_ts = 0;
746 adapter->ptp_caps.pps = 0;
747 adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82580;
748 adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576;
749 adapter->ptp_caps.gettime = igb_ptp_gettime_82576;
750 adapter->ptp_caps.settime = igb_ptp_settime_82576;
751 adapter->ptp_caps.enable = igb_ptp_enable;
752 adapter->cc.read = igb_ptp_read_82580;
753 adapter->cc.mask = CLOCKSOURCE_MASK(IGB_NBITS_82580);
754 adapter->cc.mult = 1;
755 adapter->cc.shift = 0;
756 /* Enable the timer functions by clearing bit 31. */
757 wr32(E1000_TSAUXC, 0x0);
761 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
762 adapter->ptp_caps.owner = THIS_MODULE;
763 adapter->ptp_caps.max_adj = 62499999;
764 adapter->ptp_caps.n_ext_ts = 0;
765 adapter->ptp_caps.pps = 0;
766 adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82580;
767 adapter->ptp_caps.adjtime = igb_ptp_adjtime_i210;
768 adapter->ptp_caps.gettime = igb_ptp_gettime_i210;
769 adapter->ptp_caps.settime = igb_ptp_settime_i210;
770 adapter->ptp_caps.enable = igb_ptp_enable;
771 /* Enable the timer functions by clearing bit 31. */
772 wr32(E1000_TSAUXC, 0x0);
775 adapter->ptp_clock = NULL;
781 spin_lock_init(&adapter->tmreg_lock);
782 INIT_WORK(&adapter->ptp_tx_work, igb_ptp_tx_work);
784 /* Initialize the clock and overflow work for devices that need it. */
785 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) {
786 struct timespec ts = ktime_to_timespec(ktime_get_real());
788 igb_ptp_settime_i210(&adapter->ptp_caps, &ts);
790 timecounter_init(&adapter->tc, &adapter->cc,
791 ktime_to_ns(ktime_get_real()));
793 INIT_DELAYED_WORK(&adapter->ptp_overflow_work,
794 igb_ptp_overflow_check);
796 schedule_delayed_work(&adapter->ptp_overflow_work,
797 IGB_SYSTIM_OVERFLOW_PERIOD);
800 /* Initialize the time sync interrupts for devices that support it. */
801 if (hw->mac.type >= e1000_82580) {
802 wr32(E1000_TSIM, E1000_TSIM_TXTS);
803 wr32(E1000_IMS, E1000_IMS_TS);
806 adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps,
807 &adapter->pdev->dev);
808 if (IS_ERR(adapter->ptp_clock)) {
809 adapter->ptp_clock = NULL;
810 dev_err(&adapter->pdev->dev, "ptp_clock_register failed\n");
812 dev_info(&adapter->pdev->dev, "added PHC on %s\n",
813 adapter->netdev->name);
814 adapter->flags |= IGB_FLAG_PTP;
819 * igb_ptp_stop - Disable PTP device and stop the overflow check.
820 * @adapter: Board private structure.
822 * This function stops the PTP support and cancels the delayed work.
824 void igb_ptp_stop(struct igb_adapter *adapter)
826 switch (adapter->hw.mac.type) {
831 cancel_delayed_work_sync(&adapter->ptp_overflow_work);
835 /* No delayed work to cancel. */
841 cancel_work_sync(&adapter->ptp_tx_work);
842 if (adapter->ptp_tx_skb) {
843 dev_kfree_skb_any(adapter->ptp_tx_skb);
844 adapter->ptp_tx_skb = NULL;
847 if (adapter->ptp_clock) {
848 ptp_clock_unregister(adapter->ptp_clock);
849 dev_info(&adapter->pdev->dev, "removed PHC on %s\n",
850 adapter->netdev->name);
851 adapter->flags &= ~IGB_FLAG_PTP;
856 * igb_ptp_reset - Re-enable the adapter for PTP following a reset.
857 * @adapter: Board private structure.
859 * This function handles the reset work required to re-enable the PTP device.
861 void igb_ptp_reset(struct igb_adapter *adapter)
863 struct e1000_hw *hw = &adapter->hw;
865 if (!(adapter->flags & IGB_FLAG_PTP))
868 switch (adapter->hw.mac.type) {
870 /* Dial the nominal frequency. */
871 wr32(E1000_TIMINCA, INCPERIOD_82576 | INCVALUE_82576);
878 /* Enable the timer functions and interrupts. */
879 wr32(E1000_TSAUXC, 0x0);
880 wr32(E1000_TSIM, E1000_TSIM_TXTS);
881 wr32(E1000_IMS, E1000_IMS_TS);
888 /* Re-initialize the timer. */
889 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) {
890 struct timespec ts = ktime_to_timespec(ktime_get_real());
892 igb_ptp_settime_i210(&adapter->ptp_caps, &ts);
894 timecounter_init(&adapter->tc, &adapter->cc,
895 ktime_to_ns(ktime_get_real()));