drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2014 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 /* ethtool support for ixgbe */
  30
  31 #include <linux/interrupt.h>
  32 #include <linux/types.h>
  33 #include <linux/module.h>
  34 #include <linux/slab.h>
  35 #include <linux/pci.h>
  36 #include <linux/netdevice.h>
  37 #include <linux/ethtool.h>
  38 #include <linux/vmalloc.h>
  39 #include <linux/highmem.h>
  40 #include <linux/uaccess.h>
  41
  42 #include "ixgbe.h"
  43 #include "ixgbe_phy.h"
  44
  45
  46 #define IXGBE_ALL_RAR_ENTRIES 16
  47
  48 enum {NETDEV_STATS, IXGBE_STATS};
  49
  50 struct ixgbe_stats {
  51         char stat_string[ETH_GSTRING_LEN];
  52         int type;
  53         int sizeof_stat;
  54         int stat_offset;
  55 };
  56
  57 #define IXGBE_STAT(m)           IXGBE_STATS, \
  58                                 sizeof(((struct ixgbe_adapter *)0)->m), \
  59                                 offsetof(struct ixgbe_adapter, m)
  60 #define IXGBE_NETDEV_STAT(m)    NETDEV_STATS, \
  61                                 sizeof(((struct rtnl_link_stats64 *)0)->m), \
  62                                 offsetof(struct rtnl_link_stats64, m)
  63
  64 static const struct ixgbe_stats ixgbe_gstrings_stats[] = {
  65         {"rx_packets", IXGBE_NETDEV_STAT(rx_packets)},
  66         {"tx_packets", IXGBE_NETDEV_STAT(tx_packets)},
  67         {"rx_bytes", IXGBE_NETDEV_STAT(rx_bytes)},
  68         {"tx_bytes", IXGBE_NETDEV_STAT(tx_bytes)},
  69         {"rx_pkts_nic", IXGBE_STAT(stats.gprc)},
  70         {"tx_pkts_nic", IXGBE_STAT(stats.gptc)},
  71         {"rx_bytes_nic", IXGBE_STAT(stats.gorc)},
  72         {"tx_bytes_nic", IXGBE_STAT(stats.gotc)},
  73         {"lsc_int", IXGBE_STAT(lsc_int)},
  74         {"tx_busy", IXGBE_STAT(tx_busy)},
  75         {"non_eop_descs", IXGBE_STAT(non_eop_descs)},
  76         {"rx_errors", IXGBE_NETDEV_STAT(rx_errors)},
  77         {"tx_errors", IXGBE_NETDEV_STAT(tx_errors)},
  78         {"rx_dropped", IXGBE_NETDEV_STAT(rx_dropped)},
  79         {"tx_dropped", IXGBE_NETDEV_STAT(tx_dropped)},
  80         {"multicast", IXGBE_NETDEV_STAT(multicast)},
  81         {"broadcast", IXGBE_STAT(stats.bprc)},
  82         {"rx_no_buffer_count", IXGBE_STAT(stats.rnbc[0]) },
  83         {"collisions", IXGBE_NETDEV_STAT(collisions)},
  84         {"rx_over_errors", IXGBE_NETDEV_STAT(rx_over_errors)},
  85         {"rx_crc_errors", IXGBE_NETDEV_STAT(rx_crc_errors)},
  86         {"rx_frame_errors", IXGBE_NETDEV_STAT(rx_frame_errors)},
  87         {"hw_rsc_aggregated", IXGBE_STAT(rsc_total_count)},
  88         {"hw_rsc_flushed", IXGBE_STAT(rsc_total_flush)},
  89         {"fdir_match", IXGBE_STAT(stats.fdirmatch)},
  90         {"fdir_miss", IXGBE_STAT(stats.fdirmiss)},
  91         {"fdir_overflow", IXGBE_STAT(fdir_overflow)},
  92         {"rx_fifo_errors", IXGBE_NETDEV_STAT(rx_fifo_errors)},
  93         {"rx_missed_errors", IXGBE_NETDEV_STAT(rx_missed_errors)},
  94         {"tx_aborted_errors", IXGBE_NETDEV_STAT(tx_aborted_errors)},
  95         {"tx_carrier_errors", IXGBE_NETDEV_STAT(tx_carrier_errors)},
  96         {"tx_fifo_errors", IXGBE_NETDEV_STAT(tx_fifo_errors)},
  97         {"tx_heartbeat_errors", IXGBE_NETDEV_STAT(tx_heartbeat_errors)},
  98         {"tx_timeout_count", IXGBE_STAT(tx_timeout_count)},
  99         {"tx_restart_queue", IXGBE_STAT(restart_queue)},
 100         {"rx_long_length_errors", IXGBE_STAT(stats.roc)},
 101         {"rx_short_length_errors", IXGBE_STAT(stats.ruc)},
 102         {"tx_flow_control_xon", IXGBE_STAT(stats.lxontxc)},
 103         {"rx_flow_control_xon", IXGBE_STAT(stats.lxonrxc)},
 104         {"tx_flow_control_xoff", IXGBE_STAT(stats.lxofftxc)},
 105         {"rx_flow_control_xoff", IXGBE_STAT(stats.lxoffrxc)},
 106         {"rx_csum_offload_errors", IXGBE_STAT(hw_csum_rx_error)},
 107         {"alloc_rx_page_failed", IXGBE_STAT(alloc_rx_page_failed)},
 108         {"alloc_rx_buff_failed", IXGBE_STAT(alloc_rx_buff_failed)},
 109         {"rx_no_dma_resources", IXGBE_STAT(hw_rx_no_dma_resources)},
 110         {"os2bmc_rx_by_bmc", IXGBE_STAT(stats.o2bgptc)},
 111         {"os2bmc_tx_by_bmc", IXGBE_STAT(stats.b2ospc)},
 112         {"os2bmc_tx_by_host", IXGBE_STAT(stats.o2bspc)},
 113         {"os2bmc_rx_by_host", IXGBE_STAT(stats.b2ogprc)},
 114 #ifdef IXGBE_FCOE
 115         {"fcoe_bad_fccrc", IXGBE_STAT(stats.fccrc)},
 116         {"rx_fcoe_dropped", IXGBE_STAT(stats.fcoerpdc)},
 117         {"rx_fcoe_packets", IXGBE_STAT(stats.fcoeprc)},
 118         {"rx_fcoe_dwords", IXGBE_STAT(stats.fcoedwrc)},
 119         {"fcoe_noddp", IXGBE_STAT(stats.fcoe_noddp)},
 120         {"fcoe_noddp_ext_buff", IXGBE_STAT(stats.fcoe_noddp_ext_buff)},
 121         {"tx_fcoe_packets", IXGBE_STAT(stats.fcoeptc)},
 122         {"tx_fcoe_dwords", IXGBE_STAT(stats.fcoedwtc)},
 123 #endif /* IXGBE_FCOE */
 124 };
 125
 126 /* ixgbe allocates num_tx_queues and num_rx_queues symmetrically so
 127  * we set the num_rx_queues to evaluate to num_tx_queues. This is
 128  * used because we do not have a good way to get the max number of
 129  * rx queues with CONFIG_RPS disabled.
 130  */
 131 #define IXGBE_NUM_RX_QUEUES netdev->num_tx_queues
 132
 133 #define IXGBE_QUEUE_STATS_LEN ( \
 134         (netdev->num_tx_queues + IXGBE_NUM_RX_QUEUES) * \
 135         (sizeof(struct ixgbe_queue_stats) / sizeof(u64)))
 136 #define IXGBE_GLOBAL_STATS_LEN ARRAY_SIZE(ixgbe_gstrings_stats)
 137 #define IXGBE_PB_STATS_LEN ( \
 138                         (sizeof(((struct ixgbe_adapter *)0)->stats.pxonrxc) + \
 139                          sizeof(((struct ixgbe_adapter *)0)->stats.pxontxc) + \
 140                          sizeof(((struct ixgbe_adapter *)0)->stats.pxoffrxc) + \
 141                          sizeof(((struct ixgbe_adapter *)0)->stats.pxofftxc)) \
 142                         / sizeof(u64))
 143 #define IXGBE_STATS_LEN (IXGBE_GLOBAL_STATS_LEN + \
 144                          IXGBE_PB_STATS_LEN + \
 145                          IXGBE_QUEUE_STATS_LEN)
 146
 147 static const char ixgbe_gstrings_test[][ETH_GSTRING_LEN] = {
 148         "Register test  (offline)", "Eeprom test    (offline)",
 149         "Interrupt test (offline)", "Loopback test  (offline)",
 150         "Link test   (on/offline)"
 151 };
 152 #define IXGBE_TEST_LEN sizeof(ixgbe_gstrings_test) / ETH_GSTRING_LEN
 153
 154 static int ixgbe_get_settings(struct net_device *netdev,
 155                               struct ethtool_cmd *ecmd)
 156 {
 157         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 158         struct ixgbe_hw *hw = &adapter->hw;
 159         ixgbe_link_speed supported_link;
 160         u32 link_speed = 0;
 161         bool autoneg = false;
 162         bool link_up;
 163
 164         /* SFP type is needed for get_link_capabilities */
 165         if (hw->phy.media_type & (ixgbe_media_type_fiber |
 166                                   ixgbe_media_type_fiber_qsfp)) {
 167                 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
 168                                 hw->phy.ops.identify_sfp(hw);
 169         }
 170
 171         hw->mac.ops.get_link_capabilities(hw, &supported_link, &autoneg);
 172
 173         /* set the supported link speeds */
 174         if (supported_link & IXGBE_LINK_SPEED_10GB_FULL)
 175                 ecmd->supported |= SUPPORTED_10000baseT_Full;
 176         if (supported_link & IXGBE_LINK_SPEED_1GB_FULL)
 177                 ecmd->supported |= SUPPORTED_1000baseT_Full;
 178         if (supported_link & IXGBE_LINK_SPEED_100_FULL)
 179                 ecmd->supported |= SUPPORTED_100baseT_Full;
 180
 181         /* set the advertised speeds */
 182         if (hw->phy.autoneg_advertised) {
 183                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
 184                         ecmd->advertising |= ADVERTISED_100baseT_Full;
 185                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
 186                         ecmd->advertising |= ADVERTISED_10000baseT_Full;
 187                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
 188                         ecmd->advertising |= ADVERTISED_1000baseT_Full;
 189         } else {
 190                 /* default modes in case phy.autoneg_advertised isn't set */
 191                 if (supported_link & IXGBE_LINK_SPEED_10GB_FULL)
 192                         ecmd->advertising |= ADVERTISED_10000baseT_Full;
 193                 if (supported_link & IXGBE_LINK_SPEED_1GB_FULL)
 194                         ecmd->advertising |= ADVERTISED_1000baseT_Full;
 195                 if (supported_link & IXGBE_LINK_SPEED_100_FULL)
 196                         ecmd->advertising |= ADVERTISED_100baseT_Full;
 197
 198                 if (hw->phy.multispeed_fiber && !autoneg) {
 199                         if (supported_link & IXGBE_LINK_SPEED_10GB_FULL)
 200                                 ecmd->advertising = ADVERTISED_10000baseT_Full;
 201                 }
 202         }
 203
 204         if (autoneg) {
 205                 ecmd->supported |= SUPPORTED_Autoneg;
 206                 ecmd->advertising |= ADVERTISED_Autoneg;
 207                 ecmd->autoneg = AUTONEG_ENABLE;
 208         } else
 209                 ecmd->autoneg = AUTONEG_DISABLE;
 210
 211         ecmd->transceiver = XCVR_EXTERNAL;
 212
 213         /* Determine the remaining settings based on the PHY type. */
 214         switch (adapter->hw.phy.type) {
 215         case ixgbe_phy_tn:
 216         case ixgbe_phy_aq:
 217         case ixgbe_phy_cu_unknown:
 218                 ecmd->supported |= SUPPORTED_TP;
 219                 ecmd->advertising |= ADVERTISED_TP;
 220                 ecmd->port = PORT_TP;
 221                 break;
 222         case ixgbe_phy_qt:
 223                 ecmd->supported |= SUPPORTED_FIBRE;
 224                 ecmd->advertising |= ADVERTISED_FIBRE;
 225                 ecmd->port = PORT_FIBRE;
 226                 break;
 227         case ixgbe_phy_nl:
 228         case ixgbe_phy_sfp_passive_tyco:
 229         case ixgbe_phy_sfp_passive_unknown:
 230         case ixgbe_phy_sfp_ftl:
 231         case ixgbe_phy_sfp_avago:
 232         case ixgbe_phy_sfp_intel:
 233         case ixgbe_phy_sfp_unknown:
 234                 /* SFP+ devices, further checking needed */
 235                 switch (adapter->hw.phy.sfp_type) {
 236                 case ixgbe_sfp_type_da_cu:
 237                 case ixgbe_sfp_type_da_cu_core0:
 238                 case ixgbe_sfp_type_da_cu_core1:
 239                         ecmd->supported |= SUPPORTED_FIBRE;
 240                         ecmd->advertising |= ADVERTISED_FIBRE;
 241                         ecmd->port = PORT_DA;
 242                         break;
 243                 case ixgbe_sfp_type_sr:
 244                 case ixgbe_sfp_type_lr:
 245                 case ixgbe_sfp_type_srlr_core0:
 246                 case ixgbe_sfp_type_srlr_core1:
 247                 case ixgbe_sfp_type_1g_sx_core0:
 248                 case ixgbe_sfp_type_1g_sx_core1:
 249                 case ixgbe_sfp_type_1g_lx_core0:
 250                 case ixgbe_sfp_type_1g_lx_core1:
 251                         ecmd->supported |= SUPPORTED_FIBRE;
 252                         ecmd->advertising |= ADVERTISED_FIBRE;
 253                         ecmd->port = PORT_FIBRE;
 254                         break;
 255                 case ixgbe_sfp_type_not_present:
 256                         ecmd->supported |= SUPPORTED_FIBRE;
 257                         ecmd->advertising |= ADVERTISED_FIBRE;
 258                         ecmd->port = PORT_NONE;
 259                         break;
 260                 case ixgbe_sfp_type_1g_cu_core0:
 261                 case ixgbe_sfp_type_1g_cu_core1:
 262                         ecmd->supported |= SUPPORTED_TP;
 263                         ecmd->advertising |= ADVERTISED_TP;
 264                         ecmd->port = PORT_TP;
 265                         break;
 266                 case ixgbe_sfp_type_unknown:
 267                 default:
 268                         ecmd->supported |= SUPPORTED_FIBRE;
 269                         ecmd->advertising |= ADVERTISED_FIBRE;
 270                         ecmd->port = PORT_OTHER;
 271                         break;
 272                 }
 273                 break;
 274         case ixgbe_phy_xaui:
 275                 ecmd->supported |= SUPPORTED_FIBRE;
 276                 ecmd->advertising |= ADVERTISED_FIBRE;
 277                 ecmd->port = PORT_NONE;
 278                 break;
 279         case ixgbe_phy_unknown:
 280         case ixgbe_phy_generic:
 281         case ixgbe_phy_sfp_unsupported:
 282         default:
 283                 ecmd->supported |= SUPPORTED_FIBRE;
 284                 ecmd->advertising |= ADVERTISED_FIBRE;
 285                 ecmd->port = PORT_OTHER;
 286                 break;
 287         }
 288
 289         hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
 290         if (link_up) {
 291                 switch (link_speed) {
 292                 case IXGBE_LINK_SPEED_10GB_FULL:
 293                         ethtool_cmd_speed_set(ecmd, SPEED_10000);
 294                         break;
 295                 case IXGBE_LINK_SPEED_1GB_FULL:
 296                         ethtool_cmd_speed_set(ecmd, SPEED_1000);
 297                         break;
 298                 case IXGBE_LINK_SPEED_100_FULL:
 299                         ethtool_cmd_speed_set(ecmd, SPEED_100);
 300                         break;
 301                 default:
 302                         break;
 303                 }
 304                 ecmd->duplex = DUPLEX_FULL;
 305         } else {
 306                 ethtool_cmd_speed_set(ecmd, -1);
 307                 ecmd->duplex = -1;
 308         }
 309
 310         return 0;
 311 }
 312
 313 static int ixgbe_set_settings(struct net_device *netdev,
 314                               struct ethtool_cmd *ecmd)
 315 {
 316         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 317         struct ixgbe_hw *hw = &adapter->hw;
 318         u32 advertised, old;
 319         s32 err = 0;
 320
 321         if ((hw->phy.media_type == ixgbe_media_type_copper) ||
 322             (hw->phy.multispeed_fiber)) {
 323                 /*
 324                  * this function does not support duplex forcing, but can
 325                  * limit the advertising of the adapter to the specified speed
 326                  */
 327                 if (ecmd->advertising & ~ecmd->supported)
 328                         return -EINVAL;
 329
 330                 /* only allow one speed at a time if no autoneg */
 331                 if (!ecmd->autoneg && hw->phy.multispeed_fiber) {
 332                         if (ecmd->advertising ==
 333                             (ADVERTISED_10000baseT_Full |
 334                              ADVERTISED_1000baseT_Full))
 335                                 return -EINVAL;
 336                 }
 337
 338                 old = hw->phy.autoneg_advertised;
 339                 advertised = 0;
 340                 if (ecmd->advertising & ADVERTISED_10000baseT_Full)
 341                         advertised |= IXGBE_LINK_SPEED_10GB_FULL;
 342
 343                 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
 344                         advertised |= IXGBE_LINK_SPEED_1GB_FULL;
 345
 346                 if (ecmd->advertising & ADVERTISED_100baseT_Full)
 347                         advertised |= IXGBE_LINK_SPEED_100_FULL;
 348
 349                 if (old == advertised)
 350                         return err;
 351                 /* this sets the link speed and restarts auto-neg */
 352                 hw->mac.autotry_restart = true;
 353                 err = hw->mac.ops.setup_link(hw, advertised, true);
 354                 if (err) {
 355                         e_info(probe, "setup link failed with code %d\n", err);
 356                         hw->mac.ops.setup_link(hw, old, true);
 357                 }
 358         } else {
 359                 /* in this case we currently only support 10Gb/FULL */
 360                 u32 speed = ethtool_cmd_speed(ecmd);
 361                 if ((ecmd->autoneg == AUTONEG_ENABLE) ||
 362                     (ecmd->advertising != ADVERTISED_10000baseT_Full) ||
 363                     (speed + ecmd->duplex != SPEED_10000 + DUPLEX_FULL))
 364                         return -EINVAL;
 365         }
 366
 367         return err;
 368 }
 369
 370 static void ixgbe_get_pauseparam(struct net_device *netdev,
 371                                  struct ethtool_pauseparam *pause)
 372 {
 373         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 374         struct ixgbe_hw *hw = &adapter->hw;
 375
 376         if (ixgbe_device_supports_autoneg_fc(hw) &&
 377             !hw->fc.disable_fc_autoneg)
 378                 pause->autoneg = 1;
 379         else
 380                 pause->autoneg = 0;
 381
 382         if (hw->fc.current_mode == ixgbe_fc_rx_pause) {
 383                 pause->rx_pause = 1;
 384         } else if (hw->fc.current_mode == ixgbe_fc_tx_pause) {
 385                 pause->tx_pause = 1;
 386         } else if (hw->fc.current_mode == ixgbe_fc_full) {
 387                 pause->rx_pause = 1;
 388                 pause->tx_pause = 1;
 389         }
 390 }
 391
 392 static int ixgbe_set_pauseparam(struct net_device *netdev,
 393                                 struct ethtool_pauseparam *pause)
 394 {
 395         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 396         struct ixgbe_hw *hw = &adapter->hw;
 397         struct ixgbe_fc_info fc = hw->fc;
 398
 399         /* 82598 does no support link flow control with DCB enabled */
 400         if ((hw->mac.type == ixgbe_mac_82598EB) &&
 401             (adapter->flags & IXGBE_FLAG_DCB_ENABLED))
 402                 return -EINVAL;
 403
 404         /* some devices do not support autoneg of link flow control */
 405         if ((pause->autoneg == AUTONEG_ENABLE) &&
 406             !ixgbe_device_supports_autoneg_fc(hw))
 407                 return -EINVAL;
 408
 409         fc.disable_fc_autoneg = (pause->autoneg != AUTONEG_ENABLE);
 410
 411         if ((pause->rx_pause && pause->tx_pause) || pause->autoneg)
 412                 fc.requested_mode = ixgbe_fc_full;
 413         else if (pause->rx_pause && !pause->tx_pause)
 414                 fc.requested_mode = ixgbe_fc_rx_pause;
 415         else if (!pause->rx_pause && pause->tx_pause)
 416                 fc.requested_mode = ixgbe_fc_tx_pause;
 417         else
 418                 fc.requested_mode = ixgbe_fc_none;
 419
 420         /* if the thing changed then we'll update and use new autoneg */
 421         if (memcmp(&fc, &hw->fc, sizeof(struct ixgbe_fc_info))) {
 422                 hw->fc = fc;
 423                 if (netif_running(netdev))
 424                         ixgbe_reinit_locked(adapter);
 425                 else
 426                         ixgbe_reset(adapter);
 427         }
 428
 429         return 0;
 430 }
 431
 432 static u32 ixgbe_get_msglevel(struct net_device *netdev)
 433 {
 434         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 435         return adapter->msg_enable;
 436 }
 437
 438 static void ixgbe_set_msglevel(struct net_device *netdev, u32 data)
 439 {
 440         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 441         adapter->msg_enable = data;
 442 }
 443
 444 static int ixgbe_get_regs_len(struct net_device *netdev)
 445 {
 446 #define IXGBE_REGS_LEN  1139
 447         return IXGBE_REGS_LEN * sizeof(u32);
 448 }
 449
 450 #define IXGBE_GET_STAT(_A_, _R_) _A_->stats._R_
 451
 452 static void ixgbe_get_regs(struct net_device *netdev,
 453                            struct ethtool_regs *regs, void *p)
 454 {
 455         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 456         struct ixgbe_hw *hw = &adapter->hw;
 457         u32 *regs_buff = p;
 458         u8 i;
 459
 460         memset(p, 0, IXGBE_REGS_LEN * sizeof(u32));
 461
 462         regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
 463                         hw->device_id;
 464
 465         /* General Registers */
 466         regs_buff[0] = IXGBE_READ_REG(hw, IXGBE_CTRL);
 467         regs_buff[1] = IXGBE_READ_REG(hw, IXGBE_STATUS);
 468         regs_buff[2] = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 469         regs_buff[3] = IXGBE_READ_REG(hw, IXGBE_ESDP);
 470         regs_buff[4] = IXGBE_READ_REG(hw, IXGBE_EODSDP);
 471         regs_buff[5] = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
 472         regs_buff[6] = IXGBE_READ_REG(hw, IXGBE_FRTIMER);
 473         regs_buff[7] = IXGBE_READ_REG(hw, IXGBE_TCPTIMER);
 474
 475         /* NVM Register */
 476         regs_buff[8] = IXGBE_READ_REG(hw, IXGBE_EEC);
 477         regs_buff[9] = IXGBE_READ_REG(hw, IXGBE_EERD);
 478         regs_buff[10] = IXGBE_READ_REG(hw, IXGBE_FLA);
 479         regs_buff[11] = IXGBE_READ_REG(hw, IXGBE_EEMNGCTL);
 480         regs_buff[12] = IXGBE_READ_REG(hw, IXGBE_EEMNGDATA);
 481         regs_buff[13] = IXGBE_READ_REG(hw, IXGBE_FLMNGCTL);
 482         regs_buff[14] = IXGBE_READ_REG(hw, IXGBE_FLMNGDATA);
 483         regs_buff[15] = IXGBE_READ_REG(hw, IXGBE_FLMNGCNT);
 484         regs_buff[16] = IXGBE_READ_REG(hw, IXGBE_FLOP);
 485         regs_buff[17] = IXGBE_READ_REG(hw, IXGBE_GRC);
 486
 487         /* Interrupt */
 488         /* don't read EICR because it can clear interrupt causes, instead
 489          * read EICS which is a shadow but doesn't clear EICR */
 490         regs_buff[18] = IXGBE_READ_REG(hw, IXGBE_EICS);
 491         regs_buff[19] = IXGBE_READ_REG(hw, IXGBE_EICS);
 492         regs_buff[20] = IXGBE_READ_REG(hw, IXGBE_EIMS);
 493         regs_buff[21] = IXGBE_READ_REG(hw, IXGBE_EIMC);
 494         regs_buff[22] = IXGBE_READ_REG(hw, IXGBE_EIAC);
 495         regs_buff[23] = IXGBE_READ_REG(hw, IXGBE_EIAM);
 496         regs_buff[24] = IXGBE_READ_REG(hw, IXGBE_EITR(0));
 497         regs_buff[25] = IXGBE_READ_REG(hw, IXGBE_IVAR(0));
 498         regs_buff[26] = IXGBE_READ_REG(hw, IXGBE_MSIXT);
 499         regs_buff[27] = IXGBE_READ_REG(hw, IXGBE_MSIXPBA);
 500         regs_buff[28] = IXGBE_READ_REG(hw, IXGBE_PBACL(0));
 501         regs_buff[29] = IXGBE_READ_REG(hw, IXGBE_GPIE);
 502
 503         /* Flow Control */
 504         regs_buff[30] = IXGBE_READ_REG(hw, IXGBE_PFCTOP);
 505         regs_buff[31] = IXGBE_READ_REG(hw, IXGBE_FCTTV(0));
 506         regs_buff[32] = IXGBE_READ_REG(hw, IXGBE_FCTTV(1));
 507         regs_buff[33] = IXGBE_READ_REG(hw, IXGBE_FCTTV(2));
 508         regs_buff[34] = IXGBE_READ_REG(hw, IXGBE_FCTTV(3));
 509         for (i = 0; i < 8; i++) {
 510                 switch (hw->mac.type) {
 511                 case ixgbe_mac_82598EB:
 512                         regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL(i));
 513                         regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH(i));
 514                         break;
 515                 case ixgbe_mac_82599EB:
 516                 case ixgbe_mac_X540:
 517                         regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL_82599(i));
 518                         regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
 519                         break;
 520                 default:
 521                         break;
 522                 }
 523         }
 524         regs_buff[51] = IXGBE_READ_REG(hw, IXGBE_FCRTV);
 525         regs_buff[52] = IXGBE_READ_REG(hw, IXGBE_TFCS);
 526
 527         /* Receive DMA */
 528         for (i = 0; i < 64; i++)
 529                 regs_buff[53 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
 530         for (i = 0; i < 64; i++)
 531                 regs_buff[117 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
 532         for (i = 0; i < 64; i++)
 533                 regs_buff[181 + i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
 534         for (i = 0; i < 64; i++)
 535                 regs_buff[245 + i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
 536         for (i = 0; i < 64; i++)
 537                 regs_buff[309 + i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
 538         for (i = 0; i < 64; i++)
 539                 regs_buff[373 + i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
 540         for (i = 0; i < 16; i++)
 541                 regs_buff[437 + i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
 542         for (i = 0; i < 16; i++)
 543                 regs_buff[453 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
 544         regs_buff[469] = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 545         for (i = 0; i < 8; i++)
 546                 regs_buff[470 + i] = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
 547         regs_buff[478] = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
 548         regs_buff[479] = IXGBE_READ_REG(hw, IXGBE_DROPEN);
 549
 550         /* Receive */
 551         regs_buff[480] = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
 552         regs_buff[481] = IXGBE_READ_REG(hw, IXGBE_RFCTL);
 553         for (i = 0; i < 16; i++)
 554                 regs_buff[482 + i] = IXGBE_READ_REG(hw, IXGBE_RAL(i));
 555         for (i = 0; i < 16; i++)
 556                 regs_buff[498 + i] = IXGBE_READ_REG(hw, IXGBE_RAH(i));
 557         regs_buff[514] = IXGBE_READ_REG(hw, IXGBE_PSRTYPE(0));
 558         regs_buff[515] = IXGBE_READ_REG(hw, IXGBE_FCTRL);
 559         regs_buff[516] = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
 560         regs_buff[517] = IXGBE_READ_REG(hw, IXGBE_MCSTCTRL);
 561         regs_buff[518] = IXGBE_READ_REG(hw, IXGBE_MRQC);
 562         regs_buff[519] = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
 563         for (i = 0; i < 8; i++)
 564                 regs_buff[520 + i] = IXGBE_READ_REG(hw, IXGBE_IMIR(i));
 565         for (i = 0; i < 8; i++)
 566                 regs_buff[528 + i] = IXGBE_READ_REG(hw, IXGBE_IMIREXT(i));
 567         regs_buff[536] = IXGBE_READ_REG(hw, IXGBE_IMIRVP);
 568
 569         /* Transmit */
 570         for (i = 0; i < 32; i++)
 571                 regs_buff[537 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
 572         for (i = 0; i < 32; i++)
 573                 regs_buff[569 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
 574         for (i = 0; i < 32; i++)
 575                 regs_buff[601 + i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
 576         for (i = 0; i < 32; i++)
 577                 regs_buff[633 + i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
 578         for (i = 0; i < 32; i++)
 579                 regs_buff[665 + i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
 580         for (i = 0; i < 32; i++)
 581                 regs_buff[697 + i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
 582         for (i = 0; i < 32; i++)
 583                 regs_buff[729 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAL(i));
 584         for (i = 0; i < 32; i++)
 585                 regs_buff[761 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAH(i));
 586         regs_buff[793] = IXGBE_READ_REG(hw, IXGBE_DTXCTL);
 587         for (i = 0; i < 16; i++)
 588                 regs_buff[794 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
 589         regs_buff[810] = IXGBE_READ_REG(hw, IXGBE_TIPG);
 590         for (i = 0; i < 8; i++)
 591                 regs_buff[811 + i] = IXGBE_READ_REG(hw, IXGBE_TXPBSIZE(i));
 592         regs_buff[819] = IXGBE_READ_REG(hw, IXGBE_MNGTXMAP);
 593
 594         /* Wake Up */
 595         regs_buff[820] = IXGBE_READ_REG(hw, IXGBE_WUC);
 596         regs_buff[821] = IXGBE_READ_REG(hw, IXGBE_WUFC);
 597         regs_buff[822] = IXGBE_READ_REG(hw, IXGBE_WUS);
 598         regs_buff[823] = IXGBE_READ_REG(hw, IXGBE_IPAV);
 599         regs_buff[824] = IXGBE_READ_REG(hw, IXGBE_IP4AT);
 600         regs_buff[825] = IXGBE_READ_REG(hw, IXGBE_IP6AT);
 601         regs_buff[826] = IXGBE_READ_REG(hw, IXGBE_WUPL);
 602         regs_buff[827] = IXGBE_READ_REG(hw, IXGBE_WUPM);
 603         regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT(0));
 604
 605         /* DCB */
 606         regs_buff[829] = IXGBE_READ_REG(hw, IXGBE_RMCS);   /* same as FCCFG  */
 607         regs_buff[831] = IXGBE_READ_REG(hw, IXGBE_PDPMCS); /* same as RTTPCS */
 608
 609         switch (hw->mac.type) {
 610         case ixgbe_mac_82598EB:
 611                 regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_DPMCS);
 612                 regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RUPPBMR);
 613                 for (i = 0; i < 8; i++)
 614                         regs_buff[833 + i] =
 615                                 IXGBE_READ_REG(hw, IXGBE_RT2CR(i));
 616                 for (i = 0; i < 8; i++)
 617                         regs_buff[841 + i] =
 618                                 IXGBE_READ_REG(hw, IXGBE_RT2SR(i));
 619                 for (i = 0; i < 8; i++)
 620                         regs_buff[849 + i] =
 621                                 IXGBE_READ_REG(hw, IXGBE_TDTQ2TCCR(i));
 622                 for (i = 0; i < 8; i++)
 623                         regs_buff[857 + i] =
 624                                 IXGBE_READ_REG(hw, IXGBE_TDTQ2TCSR(i));
 625                 break;
 626         case ixgbe_mac_82599EB:
 627         case ixgbe_mac_X540:
 628                 regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
 629                 regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RTRPCS);
 630                 for (i = 0; i < 8; i++)
 631                         regs_buff[833 + i] =
 632                                 IXGBE_READ_REG(hw, IXGBE_RTRPT4C(i));
 633                 for (i = 0; i < 8; i++)
 634                         regs_buff[841 + i] =
 635                                 IXGBE_READ_REG(hw, IXGBE_RTRPT4S(i));
 636                 for (i = 0; i < 8; i++)
 637                         regs_buff[849 + i] =
 638                                 IXGBE_READ_REG(hw, IXGBE_RTTDT2C(i));
 639                 for (i = 0; i < 8; i++)
 640                         regs_buff[857 + i] =
 641                                 IXGBE_READ_REG(hw, IXGBE_RTTDT2S(i));
 642                 break;
 643         default:
 644                 break;
 645         }
 646
 647         for (i = 0; i < 8; i++)
 648                 regs_buff[865 + i] =
 649                 IXGBE_READ_REG(hw, IXGBE_TDPT2TCCR(i)); /* same as RTTPT2C */
 650         for (i = 0; i < 8; i++)
 651                 regs_buff[873 + i] =
 652                 IXGBE_READ_REG(hw, IXGBE_TDPT2TCSR(i)); /* same as RTTPT2S */
 653
 654         /* Statistics */
 655         regs_buff[881] = IXGBE_GET_STAT(adapter, crcerrs);
 656         regs_buff[882] = IXGBE_GET_STAT(adapter, illerrc);
 657         regs_buff[883] = IXGBE_GET_STAT(adapter, errbc);
 658         regs_buff[884] = IXGBE_GET_STAT(adapter, mspdc);
 659         for (i = 0; i < 8; i++)
 660                 regs_buff[885 + i] = IXGBE_GET_STAT(adapter, mpc[i]);
 661         regs_buff[893] = IXGBE_GET_STAT(adapter, mlfc);
 662         regs_buff[894] = IXGBE_GET_STAT(adapter, mrfc);
 663         regs_buff[895] = IXGBE_GET_STAT(adapter, rlec);
 664         regs_buff[896] = IXGBE_GET_STAT(adapter, lxontxc);
 665         regs_buff[897] = IXGBE_GET_STAT(adapter, lxonrxc);
 666         regs_buff[898] = IXGBE_GET_STAT(adapter, lxofftxc);
 667         regs_buff[899] = IXGBE_GET_STAT(adapter, lxoffrxc);
 668         for (i = 0; i < 8; i++)
 669                 regs_buff[900 + i] = IXGBE_GET_STAT(adapter, pxontxc[i]);
 670         for (i = 0; i < 8; i++)
 671                 regs_buff[908 + i] = IXGBE_GET_STAT(adapter, pxonrxc[i]);
 672         for (i = 0; i < 8; i++)
 673                 regs_buff[916 + i] = IXGBE_GET_STAT(adapter, pxofftxc[i]);
 674         for (i = 0; i < 8; i++)
 675                 regs_buff[924 + i] = IXGBE_GET_STAT(adapter, pxoffrxc[i]);
 676         regs_buff[932] = IXGBE_GET_STAT(adapter, prc64);
 677         regs_buff[933] = IXGBE_GET_STAT(adapter, prc127);
 678         regs_buff[934] = IXGBE_GET_STAT(adapter, prc255);
 679         regs_buff[935] = IXGBE_GET_STAT(adapter, prc511);
 680         regs_buff[936] = IXGBE_GET_STAT(adapter, prc1023);
 681         regs_buff[937] = IXGBE_GET_STAT(adapter, prc1522);
 682         regs_buff[938] = IXGBE_GET_STAT(adapter, gprc);
 683         regs_buff[939] = IXGBE_GET_STAT(adapter, bprc);
 684         regs_buff[940] = IXGBE_GET_STAT(adapter, mprc);
 685         regs_buff[941] = IXGBE_GET_STAT(adapter, gptc);
 686         regs_buff[942] = IXGBE_GET_STAT(adapter, gorc);
 687         regs_buff[944] = IXGBE_GET_STAT(adapter, gotc);
 688         for (i = 0; i < 8; i++)
 689                 regs_buff[946 + i] = IXGBE_GET_STAT(adapter, rnbc[i]);
 690         regs_buff[954] = IXGBE_GET_STAT(adapter, ruc);
 691         regs_buff[955] = IXGBE_GET_STAT(adapter, rfc);
 692         regs_buff[956] = IXGBE_GET_STAT(adapter, roc);
 693         regs_buff[957] = IXGBE_GET_STAT(adapter, rjc);
 694         regs_buff[958] = IXGBE_GET_STAT(adapter, mngprc);
 695         regs_buff[959] = IXGBE_GET_STAT(adapter, mngpdc);
 696         regs_buff[960] = IXGBE_GET_STAT(adapter, mngptc);
 697         regs_buff[961] = IXGBE_GET_STAT(adapter, tor);
 698         regs_buff[963] = IXGBE_GET_STAT(adapter, tpr);
 699         regs_buff[964] = IXGBE_GET_STAT(adapter, tpt);
 700         regs_buff[965] = IXGBE_GET_STAT(adapter, ptc64);
 701         regs_buff[966] = IXGBE_GET_STAT(adapter, ptc127);
 702         regs_buff[967] = IXGBE_GET_STAT(adapter, ptc255);
 703         regs_buff[968] = IXGBE_GET_STAT(adapter, ptc511);
 704         regs_buff[969] = IXGBE_GET_STAT(adapter, ptc1023);
 705         regs_buff[970] = IXGBE_GET_STAT(adapter, ptc1522);
 706         regs_buff[971] = IXGBE_GET_STAT(adapter, mptc);
 707         regs_buff[972] = IXGBE_GET_STAT(adapter, bptc);
 708         regs_buff[973] = IXGBE_GET_STAT(adapter, xec);
 709         for (i = 0; i < 16; i++)
 710                 regs_buff[974 + i] = IXGBE_GET_STAT(adapter, qprc[i]);
 711         for (i = 0; i < 16; i++)
 712                 regs_buff[990 + i] = IXGBE_GET_STAT(adapter, qptc[i]);
 713         for (i = 0; i < 16; i++)
 714                 regs_buff[1006 + i] = IXGBE_GET_STAT(adapter, qbrc[i]);
 715         for (i = 0; i < 16; i++)
 716                 regs_buff[1022 + i] = IXGBE_GET_STAT(adapter, qbtc[i]);
 717
 718         /* MAC */
 719         regs_buff[1038] = IXGBE_READ_REG(hw, IXGBE_PCS1GCFIG);
 720         regs_buff[1039] = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
 721         regs_buff[1040] = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
 722         regs_buff[1041] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG0);
 723         regs_buff[1042] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG1);
 724         regs_buff[1043] = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
 725         regs_buff[1044] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
 726         regs_buff[1045] = IXGBE_READ_REG(hw, IXGBE_PCS1GANNP);
 727         regs_buff[1046] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLPNP);
 728         regs_buff[1047] = IXGBE_READ_REG(hw, IXGBE_HLREG0);
 729         regs_buff[1048] = IXGBE_READ_REG(hw, IXGBE_HLREG1);
 730         regs_buff[1049] = IXGBE_READ_REG(hw, IXGBE_PAP);
 731         regs_buff[1050] = IXGBE_READ_REG(hw, IXGBE_MACA);
 732         regs_buff[1051] = IXGBE_READ_REG(hw, IXGBE_APAE);
 733         regs_buff[1052] = IXGBE_READ_REG(hw, IXGBE_ARD);
 734         regs_buff[1053] = IXGBE_READ_REG(hw, IXGBE_AIS);
 735         regs_buff[1054] = IXGBE_READ_REG(hw, IXGBE_MSCA);
 736         regs_buff[1055] = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 737         regs_buff[1056] = IXGBE_READ_REG(hw, IXGBE_MLADD);
 738         regs_buff[1057] = IXGBE_READ_REG(hw, IXGBE_MHADD);
 739         regs_buff[1058] = IXGBE_READ_REG(hw, IXGBE_TREG);
 740         regs_buff[1059] = IXGBE_READ_REG(hw, IXGBE_PCSS1);
 741         regs_buff[1060] = IXGBE_READ_REG(hw, IXGBE_PCSS2);
 742         regs_buff[1061] = IXGBE_READ_REG(hw, IXGBE_XPCSS);
 743         regs_buff[1062] = IXGBE_READ_REG(hw, IXGBE_SERDESC);
 744         regs_buff[1063] = IXGBE_READ_REG(hw, IXGBE_MACS);
 745         regs_buff[1064] = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 746         regs_buff[1065] = IXGBE_READ_REG(hw, IXGBE_LINKS);
 747         regs_buff[1066] = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
 748         regs_buff[1067] = IXGBE_READ_REG(hw, IXGBE_AUTOC3);
 749         regs_buff[1068] = IXGBE_READ_REG(hw, IXGBE_ANLP1);
 750         regs_buff[1069] = IXGBE_READ_REG(hw, IXGBE_ANLP2);
 751         regs_buff[1070] = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
 752
 753         /* Diagnostic */
 754         regs_buff[1071] = IXGBE_READ_REG(hw, IXGBE_RDSTATCTL);
 755         for (i = 0; i < 8; i++)
 756                 regs_buff[1072 + i] = IXGBE_READ_REG(hw, IXGBE_RDSTAT(i));
 757         regs_buff[1080] = IXGBE_READ_REG(hw, IXGBE_RDHMPN);
 758         for (i = 0; i < 4; i++)
 759                 regs_buff[1081 + i] = IXGBE_READ_REG(hw, IXGBE_RIC_DW(i));
 760         regs_buff[1085] = IXGBE_READ_REG(hw, IXGBE_RDPROBE);
 761         regs_buff[1086] = IXGBE_READ_REG(hw, IXGBE_TDSTATCTL);
 762         for (i = 0; i < 8; i++)
 763                 regs_buff[1087 + i] = IXGBE_READ_REG(hw, IXGBE_TDSTAT(i));
 764         regs_buff[1095] = IXGBE_READ_REG(hw, IXGBE_TDHMPN);
 765         for (i = 0; i < 4; i++)
 766                 regs_buff[1096 + i] = IXGBE_READ_REG(hw, IXGBE_TIC_DW(i));
 767         regs_buff[1100] = IXGBE_READ_REG(hw, IXGBE_TDPROBE);
 768         regs_buff[1101] = IXGBE_READ_REG(hw, IXGBE_TXBUFCTRL);
 769         regs_buff[1102] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA0);
 770         regs_buff[1103] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA1);
 771         regs_buff[1104] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA2);
 772         regs_buff[1105] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA3);
 773         regs_buff[1106] = IXGBE_READ_REG(hw, IXGBE_RXBUFCTRL);
 774         regs_buff[1107] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA0);
 775         regs_buff[1108] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA1);
 776         regs_buff[1109] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA2);
 777         regs_buff[1110] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA3);
 778         for (i = 0; i < 8; i++)
 779                 regs_buff[1111 + i] = IXGBE_READ_REG(hw, IXGBE_PCIE_DIAG(i));
 780         regs_buff[1119] = IXGBE_READ_REG(hw, IXGBE_RFVAL);
 781         regs_buff[1120] = IXGBE_READ_REG(hw, IXGBE_MDFTC1);
 782         regs_buff[1121] = IXGBE_READ_REG(hw, IXGBE_MDFTC2);
 783         regs_buff[1122] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO1);
 784         regs_buff[1123] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO2);
 785         regs_buff[1124] = IXGBE_READ_REG(hw, IXGBE_MDFTS);
 786         regs_buff[1125] = IXGBE_READ_REG(hw, IXGBE_PCIEECCCTL);
 787         regs_buff[1126] = IXGBE_READ_REG(hw, IXGBE_PBTXECC);
 788         regs_buff[1127] = IXGBE_READ_REG(hw, IXGBE_PBRXECC);
 789
 790         /* 82599 X540 specific registers  */
 791         regs_buff[1128] = IXGBE_READ_REG(hw, IXGBE_MFLCN);
 792
 793         /* 82599 X540 specific DCB registers  */
 794         regs_buff[1129] = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
 795         regs_buff[1130] = IXGBE_READ_REG(hw, IXGBE_RTTUP2TC);
 796         for (i = 0; i < 4; i++)
 797                 regs_buff[1131 + i] = IXGBE_READ_REG(hw, IXGBE_TXLLQ(i));
 798         regs_buff[1135] = IXGBE_READ_REG(hw, IXGBE_RTTBCNRM);
 799                                         /* same as RTTQCNRM */
 800         regs_buff[1136] = IXGBE_READ_REG(hw, IXGBE_RTTBCNRD);
 801                                         /* same as RTTQCNRR */
 802
 803         /* X540 specific DCB registers  */
 804         regs_buff[1137] = IXGBE_READ_REG(hw, IXGBE_RTTQCNCR);
 805         regs_buff[1138] = IXGBE_READ_REG(hw, IXGBE_RTTQCNTG);
 806 }
 807
 808 static int ixgbe_get_eeprom_len(struct net_device *netdev)
 809 {
 810         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 811         return adapter->hw.eeprom.word_size * 2;
 812 }
 813
 814 static int ixgbe_get_eeprom(struct net_device *netdev,
 815                             struct ethtool_eeprom *eeprom, u8 *bytes)
 816 {
 817         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 818         struct ixgbe_hw *hw = &adapter->hw;
 819         u16 *eeprom_buff;
 820         int first_word, last_word, eeprom_len;
 821         int ret_val = 0;
 822         u16 i;
 823
 824         if (eeprom->len == 0)
 825                 return -EINVAL;
 826
 827         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
 828
 829         first_word = eeprom->offset >> 1;
 830         last_word = (eeprom->offset + eeprom->len - 1) >> 1;
 831         eeprom_len = last_word - first_word + 1;
 832
 833         eeprom_buff = kmalloc(sizeof(u16) * eeprom_len, GFP_KERNEL);
 834         if (!eeprom_buff)
 835                 return -ENOMEM;
 836
 837         ret_val = hw->eeprom.ops.read_buffer(hw, first_word, eeprom_len,
 838                                              eeprom_buff);
 839
 840         /* Device's eeprom is always little-endian, word addressable */
 841         for (i = 0; i < eeprom_len; i++)
 842                 le16_to_cpus(&eeprom_buff[i]);
 843
 844         memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len);
 845         kfree(eeprom_buff);
 846
 847         return ret_val;
 848 }
 849
 850 static int ixgbe_set_eeprom(struct net_device *netdev,
 851                             struct ethtool_eeprom *eeprom, u8 *bytes)
 852 {
 853         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 854         struct ixgbe_hw *hw = &adapter->hw;
 855         u16 *eeprom_buff;
 856         void *ptr;
 857         int max_len, first_word, last_word, ret_val = 0;
 858         u16 i;
 859
 860         if (eeprom->len == 0)
 861                 return -EINVAL;
 862
 863         if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
 864                 return -EINVAL;
 865
 866         max_len = hw->eeprom.word_size * 2;
 867
 868         first_word = eeprom->offset >> 1;
 869         last_word = (eeprom->offset + eeprom->len - 1) >> 1;
 870         eeprom_buff = kmalloc(max_len, GFP_KERNEL);
 871         if (!eeprom_buff)
 872                 return -ENOMEM;
 873
 874         ptr = eeprom_buff;
 875
 876         if (eeprom->offset & 1) {
 877                 /*
 878                  * need read/modify/write of first changed EEPROM word
 879                  * only the second byte of the word is being modified
 880                  */
 881                 ret_val = hw->eeprom.ops.read(hw, first_word, &eeprom_buff[0]);
 882                 if (ret_val)
 883                         goto err;
 884
 885                 ptr++;
 886         }
 887         if ((eeprom->offset + eeprom->len) & 1) {
 888                 /*
 889                  * need read/modify/write of last changed EEPROM word
 890                  * only the first byte of the word is being modified
 891                  */
 892                 ret_val = hw->eeprom.ops.read(hw, last_word,
 893                                           &eeprom_buff[last_word - first_word]);
 894                 if (ret_val)
 895                         goto err;
 896         }
 897
 898         /* Device's eeprom is always little-endian, word addressable */
 899         for (i = 0; i < last_word - first_word + 1; i++)
 900                 le16_to_cpus(&eeprom_buff[i]);
 901
 902         memcpy(ptr, bytes, eeprom->len);
 903
 904         for (i = 0; i < last_word - first_word + 1; i++)
 905                 cpu_to_le16s(&eeprom_buff[i]);
 906
 907         ret_val = hw->eeprom.ops.write_buffer(hw, first_word,
 908                                               last_word - first_word + 1,
 909                                               eeprom_buff);
 910
 911         /* Update the checksum */
 912         if (ret_val == 0)
 913                 hw->eeprom.ops.update_checksum(hw);
 914
 915 err:
 916         kfree(eeprom_buff);
 917         return ret_val;
 918 }
 919
 920 static void ixgbe_get_drvinfo(struct net_device *netdev,
 921                               struct ethtool_drvinfo *drvinfo)
 922 {
 923         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 924         u32 nvm_track_id;
 925
 926         strlcpy(drvinfo->driver, ixgbe_driver_name, sizeof(drvinfo->driver));
 927         strlcpy(drvinfo->version, ixgbe_driver_version,
 928                 sizeof(drvinfo->version));
 929
 930         nvm_track_id = (adapter->eeprom_verh << 16) |
 931                         adapter->eeprom_verl;
 932         snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version), "0x%08x",
 933                  nvm_track_id);
 934
 935         strlcpy(drvinfo->bus_info, pci_name(adapter->pdev),
 936                 sizeof(drvinfo->bus_info));
 937         drvinfo->n_stats = IXGBE_STATS_LEN;
 938         drvinfo->testinfo_len = IXGBE_TEST_LEN;
 939         drvinfo->regdump_len = ixgbe_get_regs_len(netdev);
 940 }
 941
 942 static void ixgbe_get_ringparam(struct net_device *netdev,
 943                                 struct ethtool_ringparam *ring)
 944 {
 945         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 946         struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
 947         struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
 948
 949         ring->rx_max_pending = IXGBE_MAX_RXD;
 950         ring->tx_max_pending = IXGBE_MAX_TXD;
 951         ring->rx_pending = rx_ring->count;
 952         ring->tx_pending = tx_ring->count;
 953 }
 954
 955 static int ixgbe_set_ringparam(struct net_device *netdev,
 956                                struct ethtool_ringparam *ring)
 957 {
 958         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 959         struct ixgbe_ring *temp_ring;
 960         int i, err = 0;
 961         u32 new_rx_count, new_tx_count;
 962
 963         if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
 964                 return -EINVAL;
 965
 966         new_tx_count = clamp_t(u32, ring->tx_pending,
 967                                IXGBE_MIN_TXD, IXGBE_MAX_TXD);
 968         new_tx_count = ALIGN(new_tx_count, IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE);
 969
 970         new_rx_count = clamp_t(u32, ring->rx_pending,
 971                                IXGBE_MIN_RXD, IXGBE_MAX_RXD);
 972         new_rx_count = ALIGN(new_rx_count, IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE);
 973
 974         if ((new_tx_count == adapter->tx_ring_count) &&
 975             (new_rx_count == adapter->rx_ring_count)) {
 976                 /* nothing to do */
 977                 return 0;
 978         }
 979
 980         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
 981                 usleep_range(1000, 2000);
 982
 983         if (!netif_running(adapter->netdev)) {
 984                 for (i = 0; i < adapter->num_tx_queues; i++)
 985                         adapter->tx_ring[i]->count = new_tx_count;
 986                 for (i = 0; i < adapter->num_rx_queues; i++)
 987                         adapter->rx_ring[i]->count = new_rx_count;
 988                 adapter->tx_ring_count = new_tx_count;
 989                 adapter->rx_ring_count = new_rx_count;
 990                 goto clear_reset;
 991         }
 992
 993         /* allocate temporary buffer to store rings in */
 994         i = max_t(int, adapter->num_tx_queues, adapter->num_rx_queues);
 995         temp_ring = vmalloc(i * sizeof(struct ixgbe_ring));
 996
 997         if (!temp_ring) {
 998                 err = -ENOMEM;
 999                 goto clear_reset;
1000         }
1001
1002         ixgbe_down(adapter);
1003
1004         /*
1005          * Setup new Tx resources and free the old Tx resources in that order.
1006          * We can then assign the new resources to the rings via a memcpy.
1007          * The advantage to this approach is that we are guaranteed to still
1008          * have resources even in the case of an allocation failure.
1009          */
1010         if (new_tx_count != adapter->tx_ring_count) {
1011                 for (i = 0; i < adapter->num_tx_queues; i++) {
1012                         memcpy(&temp_ring[i], adapter->tx_ring[i],
1013                                sizeof(struct ixgbe_ring));
1014
1015                         temp_ring[i].count = new_tx_count;
1016                         err = ixgbe_setup_tx_resources(&temp_ring[i]);
1017                         if (err) {
1018                                 while (i) {
1019                                         i--;
1020                                         ixgbe_free_tx_resources(&temp_ring[i]);
1021                                 }
1022                                 goto err_setup;
1023                         }
1024                 }
1025
1026                 for (i = 0; i < adapter->num_tx_queues; i++) {
1027                         ixgbe_free_tx_resources(adapter->tx_ring[i]);
1028
1029                         memcpy(adapter->tx_ring[i], &temp_ring[i],
1030                                sizeof(struct ixgbe_ring));
1031                 }
1032
1033                 adapter->tx_ring_count = new_tx_count;
1034         }
1035
1036         /* Repeat the process for the Rx rings if needed */
1037         if (new_rx_count != adapter->rx_ring_count) {
1038                 for (i = 0; i < adapter->num_rx_queues; i++) {
1039                         memcpy(&temp_ring[i], adapter->rx_ring[i],
1040                                sizeof(struct ixgbe_ring));
1041
1042                         temp_ring[i].count = new_rx_count;
1043                         err = ixgbe_setup_rx_resources(&temp_ring[i]);
1044                         if (err) {
1045                                 while (i) {
1046                                         i--;
1047                                         ixgbe_free_rx_resources(&temp_ring[i]);
1048                                 }
1049                                 goto err_setup;
1050                         }
1051
1052                 }
1053
1054                 for (i = 0; i < adapter->num_rx_queues; i++) {
1055                         ixgbe_free_rx_resources(adapter->rx_ring[i]);
1056
1057                         memcpy(adapter->rx_ring[i], &temp_ring[i],
1058                                sizeof(struct ixgbe_ring));
1059                 }
1060
1061                 adapter->rx_ring_count = new_rx_count;
1062         }
1063
1064 err_setup:
1065         ixgbe_up(adapter);
1066         vfree(temp_ring);
1067 clear_reset:
1068         clear_bit(__IXGBE_RESETTING, &adapter->state);
1069         return err;
1070 }
1071
1072 static int ixgbe_get_sset_count(struct net_device *netdev, int sset)
1073 {
1074         switch (sset) {
1075         case ETH_SS_TEST:
1076                 return IXGBE_TEST_LEN;
1077         case ETH_SS_STATS:
1078                 return IXGBE_STATS_LEN;
1079         default:
1080                 return -EOPNOTSUPP;
1081         }
1082 }
1083
1084 static void ixgbe_get_ethtool_stats(struct net_device *netdev,
1085                                     struct ethtool_stats *stats, u64 *data)
1086 {
1087         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1088         struct rtnl_link_stats64 temp;
1089         const struct rtnl_link_stats64 *net_stats;
1090         unsigned int start;
1091         struct ixgbe_ring *ring;
1092         int i, j;
1093         char *p = NULL;
1094
1095         ixgbe_update_stats(adapter);
1096         net_stats = dev_get_stats(netdev, &temp);
1097         for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
1098                 switch (ixgbe_gstrings_stats[i].type) {
1099                 case NETDEV_STATS:
1100                         p = (char *) net_stats +
1101                                         ixgbe_gstrings_stats[i].stat_offset;
1102                         break;
1103                 case IXGBE_STATS:
1104                         p = (char *) adapter +
1105                                         ixgbe_gstrings_stats[i].stat_offset;
1106                         break;
1107                 default:
1108                         data[i] = 0;
1109                         continue;
1110                 }
1111
1112                 data[i] = (ixgbe_gstrings_stats[i].sizeof_stat ==
1113                            sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
1114         }
1115         for (j = 0; j < netdev->num_tx_queues; j++) {
1116                 ring = adapter->tx_ring[j];
1117                 if (!ring) {
1118                         data[i] = 0;
1119                         data[i+1] = 0;
1120                         i += 2;
1121 #ifdef BP_EXTENDED_STATS
1122                         data[i] = 0;
1123                         data[i+1] = 0;
1124                         data[i+2] = 0;
1125                         i += 3;
1126 #endif
1127                         continue;
1128                 }
1129
1130                 do {
1131                         start = u64_stats_fetch_begin_irq(&ring->syncp);
1132                         data[i]   = ring->stats.packets;
1133                         data[i+1] = ring->stats.bytes;
1134                 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1135                 i += 2;
1136 #ifdef BP_EXTENDED_STATS
1137                 data[i] = ring->stats.yields;
1138                 data[i+1] = ring->stats.misses;
1139                 data[i+2] = ring->stats.cleaned;
1140                 i += 3;
1141 #endif
1142         }
1143         for (j = 0; j < IXGBE_NUM_RX_QUEUES; j++) {
1144                 ring = adapter->rx_ring[j];
1145                 if (!ring) {
1146                         data[i] = 0;
1147                         data[i+1] = 0;
1148                         i += 2;
1149 #ifdef BP_EXTENDED_STATS
1150                         data[i] = 0;
1151                         data[i+1] = 0;
1152                         data[i+2] = 0;
1153                         i += 3;
1154 #endif
1155                         continue;
1156                 }
1157
1158                 do {
1159                         start = u64_stats_fetch_begin_irq(&ring->syncp);
1160                         data[i]   = ring->stats.packets;
1161                         data[i+1] = ring->stats.bytes;
1162                 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1163                 i += 2;
1164 #ifdef BP_EXTENDED_STATS
1165                 data[i] = ring->stats.yields;
1166                 data[i+1] = ring->stats.misses;
1167                 data[i+2] = ring->stats.cleaned;
1168                 i += 3;
1169 #endif
1170         }
1171
1172         for (j = 0; j < IXGBE_MAX_PACKET_BUFFERS; j++) {
1173                 data[i++] = adapter->stats.pxontxc[j];
1174                 data[i++] = adapter->stats.pxofftxc[j];
1175         }
1176         for (j = 0; j < IXGBE_MAX_PACKET_BUFFERS; j++) {
1177                 data[i++] = adapter->stats.pxonrxc[j];
1178                 data[i++] = adapter->stats.pxoffrxc[j];
1179         }
1180 }
1181
1182 static void ixgbe_get_strings(struct net_device *netdev, u32 stringset,
1183                               u8 *data)
1184 {
1185         char *p = (char *)data;
1186         int i;
1187
1188         switch (stringset) {
1189         case ETH_SS_TEST:
1190                 for (i = 0; i < IXGBE_TEST_LEN; i++) {
1191                         memcpy(data, ixgbe_gstrings_test[i], ETH_GSTRING_LEN);
1192                         data += ETH_GSTRING_LEN;
1193                 }
1194                 break;
1195         case ETH_SS_STATS:
1196                 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
1197                         memcpy(p, ixgbe_gstrings_stats[i].stat_string,
1198                                ETH_GSTRING_LEN);
1199                         p += ETH_GSTRING_LEN;
1200                 }
1201                 for (i = 0; i < netdev->num_tx_queues; i++) {
1202                         sprintf(p, "tx_queue_%u_packets", i);
1203                         p += ETH_GSTRING_LEN;
1204                         sprintf(p, "tx_queue_%u_bytes", i);
1205                         p += ETH_GSTRING_LEN;
1206 #ifdef BP_EXTENDED_STATS
1207                         sprintf(p, "tx_queue_%u_bp_napi_yield", i);
1208                         p += ETH_GSTRING_LEN;
1209                         sprintf(p, "tx_queue_%u_bp_misses", i);
1210                         p += ETH_GSTRING_LEN;
1211                         sprintf(p, "tx_queue_%u_bp_cleaned", i);
1212                         p += ETH_GSTRING_LEN;
1213 #endif /* BP_EXTENDED_STATS */
1214                 }
1215                 for (i = 0; i < IXGBE_NUM_RX_QUEUES; i++) {
1216                         sprintf(p, "rx_queue_%u_packets", i);
1217                         p += ETH_GSTRING_LEN;
1218                         sprintf(p, "rx_queue_%u_bytes", i);
1219                         p += ETH_GSTRING_LEN;
1220 #ifdef BP_EXTENDED_STATS
1221                         sprintf(p, "rx_queue_%u_bp_poll_yield", i);
1222                         p += ETH_GSTRING_LEN;
1223                         sprintf(p, "rx_queue_%u_bp_misses", i);
1224                         p += ETH_GSTRING_LEN;
1225                         sprintf(p, "rx_queue_%u_bp_cleaned", i);
1226                         p += ETH_GSTRING_LEN;
1227 #endif /* BP_EXTENDED_STATS */
1228                 }
1229                 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) {
1230                         sprintf(p, "tx_pb_%u_pxon", i);
1231                         p += ETH_GSTRING_LEN;
1232                         sprintf(p, "tx_pb_%u_pxoff", i);
1233                         p += ETH_GSTRING_LEN;
1234                 }
1235                 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++) {
1236                         sprintf(p, "rx_pb_%u_pxon", i);
1237                         p += ETH_GSTRING_LEN;
1238                         sprintf(p, "rx_pb_%u_pxoff", i);
1239                         p += ETH_GSTRING_LEN;
1240                 }
1241                 /* BUG_ON(p - data != IXGBE_STATS_LEN * ETH_GSTRING_LEN); */
1242                 break;
1243         }
1244 }
1245
1246 static int ixgbe_link_test(struct ixgbe_adapter *adapter, u64 *data)
1247 {
1248         struct ixgbe_hw *hw = &adapter->hw;
1249         bool link_up;
1250         u32 link_speed = 0;
1251
1252         if (ixgbe_removed(hw->hw_addr)) {
1253                 *data = 1;
1254                 return 1;
1255         }
1256         *data = 0;
1257
1258         hw->mac.ops.check_link(hw, &link_speed, &link_up, true);
1259         if (link_up)
1260                 return *data;
1261         else
1262                 *data = 1;
1263         return *data;
1264 }
1265
1266 /* ethtool register test data */
1267 struct ixgbe_reg_test {
1268         u16 reg;
1269         u8  array_len;
1270         u8  test_type;
1271         u32 mask;
1272         u32 write;
1273 };
1274
1275 /* In the hardware, registers are laid out either singly, in arrays
1276  * spaced 0x40 bytes apart, or in contiguous tables.  We assume
1277  * most tests take place on arrays or single registers (handled
1278  * as a single-element array) and special-case the tables.
1279  * Table tests are always pattern tests.
1280  *
1281  * We also make provision for some required setup steps by specifying
1282  * registers to be written without any read-back testing.
1283  */
1284
1285 #define PATTERN_TEST    1
1286 #define SET_READ_TEST   2
1287 #define WRITE_NO_TEST   3
1288 #define TABLE32_TEST    4
1289 #define TABLE64_TEST_LO 5
1290 #define TABLE64_TEST_HI 6
1291
1292 /* default 82599 register test */
1293 static const struct ixgbe_reg_test reg_test_82599[] = {
1294         { IXGBE_FCRTL_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1295         { IXGBE_FCRTH_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1296         { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1297         { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1298         { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 },
1299         { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1300         { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1301         { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1302         { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1303         { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1304         { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1305         { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1306         { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1307         { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1308         { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFF80 },
1309         { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000001, 0x00000001 },
1310         { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1311         { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x8001FFFF, 0x800CFFFF },
1312         { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1313         { 0, 0, 0, 0 }
1314 };
1315
1316 /* default 82598 register test */
1317 static const struct ixgbe_reg_test reg_test_82598[] = {
1318         { IXGBE_FCRTL(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1319         { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1320         { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1321         { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1322         { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1323         { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1324         { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1325         /* Enable all four RX queues before testing. */
1326         { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1327         /* RDH is read-only for 82598, only test RDT. */
1328         { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1329         { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1330         { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1331         { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1332         { IXGBE_TIPG, 1, PATTERN_TEST, 0x000000FF, 0x000000FF },
1333         { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1334         { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1335         { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1336         { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000003, 0x00000003 },
1337         { IXGBE_DTXCTL, 1, SET_READ_TEST, 0x00000005, 0x00000005 },
1338         { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1339         { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x800CFFFF, 0x800CFFFF },
1340         { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1341         { 0, 0, 0, 0 }
1342 };
1343
1344 static bool reg_pattern_test(struct ixgbe_adapter *adapter, u64 *data, int reg,
1345                              u32 mask, u32 write)
1346 {
1347         u32 pat, val, before;
1348         static const u32 test_pattern[] = {
1349                 0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
1350
1351         if (ixgbe_removed(adapter->hw.hw_addr)) {
1352                 *data = 1;
1353                 return 1;
1354         }
1355         for (pat = 0; pat < ARRAY_SIZE(test_pattern); pat++) {
1356                 before = ixgbe_read_reg(&adapter->hw, reg);
1357                 ixgbe_write_reg(&adapter->hw, reg, test_pattern[pat] & write);
1358                 val = ixgbe_read_reg(&adapter->hw, reg);
1359                 if (val != (test_pattern[pat] & write & mask)) {
1360                         e_err(drv, "pattern test reg %04X failed: got 0x%08X expected 0x%08X\n",
1361                               reg, val, (test_pattern[pat] & write & mask));
1362                         *data = reg;
1363                         ixgbe_write_reg(&adapter->hw, reg, before);
1364                         return true;
1365                 }
1366                 ixgbe_write_reg(&adapter->hw, reg, before);
1367         }
1368         return false;
1369 }
1370
1371 static bool reg_set_and_check(struct ixgbe_adapter *adapter, u64 *data, int reg,
1372                               u32 mask, u32 write)
1373 {
1374         u32 val, before;
1375
1376         if (ixgbe_removed(adapter->hw.hw_addr)) {
1377                 *data = 1;
1378                 return 1;
1379         }
1380         before = ixgbe_read_reg(&adapter->hw, reg);
1381         ixgbe_write_reg(&adapter->hw, reg, write & mask);
1382         val = ixgbe_read_reg(&adapter->hw, reg);
1383         if ((write & mask) != (val & mask)) {
1384                 e_err(drv, "set/check reg %04X test failed: got 0x%08X expected 0x%08X\n",
1385                       reg, (val & mask), (write & mask));
1386                 *data = reg;
1387                 ixgbe_write_reg(&adapter->hw, reg, before);
1388                 return true;
1389         }
1390         ixgbe_write_reg(&adapter->hw, reg, before);
1391         return false;
1392 }
1393
1394 static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data)
1395 {
1396         const struct ixgbe_reg_test *test;
1397         u32 value, before, after;
1398         u32 i, toggle;
1399
1400         if (ixgbe_removed(adapter->hw.hw_addr)) {
1401                 e_err(drv, "Adapter removed - register test blocked\n");
1402                 *data = 1;
1403                 return 1;
1404         }
1405         switch (adapter->hw.mac.type) {
1406         case ixgbe_mac_82598EB:
1407                 toggle = 0x7FFFF3FF;
1408                 test = reg_test_82598;
1409                 break;
1410         case ixgbe_mac_82599EB:
1411         case ixgbe_mac_X540:
1412                 toggle = 0x7FFFF30F;
1413                 test = reg_test_82599;
1414                 break;
1415         default:
1416                 *data = 1;
1417                 return 1;
1418                 break;
1419         }
1420
1421         /*
1422          * Because the status register is such a special case,
1423          * we handle it separately from the rest of the register
1424          * tests.  Some bits are read-only, some toggle, and some
1425          * are writeable on newer MACs.
1426          */
1427         before = ixgbe_read_reg(&adapter->hw, IXGBE_STATUS);
1428         value = (ixgbe_read_reg(&adapter->hw, IXGBE_STATUS) & toggle);
1429         ixgbe_write_reg(&adapter->hw, IXGBE_STATUS, toggle);
1430         after = ixgbe_read_reg(&adapter->hw, IXGBE_STATUS) & toggle;
1431         if (value != after) {
1432                 e_err(drv, "failed STATUS register test got: 0x%08X expected: 0x%08X\n",
1433                       after, value);
1434                 *data = 1;
1435                 return 1;
1436         }
1437         /* restore previous status */
1438         ixgbe_write_reg(&adapter->hw, IXGBE_STATUS, before);
1439
1440         /*
1441          * Perform the remainder of the register test, looping through
1442          * the test table until we either fail or reach the null entry.
1443          */
1444         while (test->reg) {
1445                 for (i = 0; i < test->array_len; i++) {
1446                         bool b = false;
1447
1448                         switch (test->test_type) {
1449                         case PATTERN_TEST:
1450                                 b = reg_pattern_test(adapter, data,
1451                                                      test->reg + (i * 0x40),
1452                                                      test->mask,
1453                                                      test->write);
1454                                 break;
1455                         case SET_READ_TEST:
1456                                 b = reg_set_and_check(adapter, data,
1457                                                       test->reg + (i * 0x40),
1458                                                       test->mask,
1459                                                       test->write);
1460                                 break;
1461                         case WRITE_NO_TEST:
1462                                 ixgbe_write_reg(&adapter->hw,
1463                                                 test->reg + (i * 0x40),
1464                                                 test->write);
1465                                 break;
1466                         case TABLE32_TEST:
1467                                 b = reg_pattern_test(adapter, data,
1468                                                      test->reg + (i * 4),
1469                                                      test->mask,
1470                                                      test->write);
1471                                 break;
1472                         case TABLE64_TEST_LO:
1473                                 b = reg_pattern_test(adapter, data,
1474                                                      test->reg + (i * 8),
1475                                                      test->mask,
1476                                                      test->write);
1477                                 break;
1478                         case TABLE64_TEST_HI:
1479                                 b = reg_pattern_test(adapter, data,
1480                                                      (test->reg + 4) + (i * 8),
1481                                                      test->mask,
1482                                                      test->write);
1483                                 break;
1484                         }
1485                         if (b)
1486                                 return 1;
1487                 }
1488                 test++;
1489         }
1490
1491         *data = 0;
1492         return 0;
1493 }
1494
1495 static int ixgbe_eeprom_test(struct ixgbe_adapter *adapter, u64 *data)
1496 {
1497         struct ixgbe_hw *hw = &adapter->hw;
1498         if (hw->eeprom.ops.validate_checksum(hw, NULL))
1499                 *data = 1;
1500         else
1501                 *data = 0;
1502         return *data;
1503 }
1504
1505 static irqreturn_t ixgbe_test_intr(int irq, void *data)
1506 {
1507         struct net_device *netdev = (struct net_device *) data;
1508         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1509
1510         adapter->test_icr |= IXGBE_READ_REG(&adapter->hw, IXGBE_EICR);
1511
1512         return IRQ_HANDLED;
1513 }
1514
1515 static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data)
1516 {
1517         struct net_device *netdev = adapter->netdev;
1518         u32 mask, i = 0, shared_int = true;
1519         u32 irq = adapter->pdev->irq;
1520
1521         *data = 0;
1522
1523         /* Hook up test interrupt handler just for this test */
1524         if (adapter->msix_entries) {
1525                 /* NOTE: we don't test MSI-X interrupts here, yet */
1526                 return 0;
1527         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1528                 shared_int = false;
1529                 if (request_irq(irq, ixgbe_test_intr, 0, netdev->name,
1530                                 netdev)) {
1531                         *data = 1;
1532                         return -1;
1533                 }
1534         } else if (!request_irq(irq, ixgbe_test_intr, IRQF_PROBE_SHARED,
1535                                 netdev->name, netdev)) {
1536                 shared_int = false;
1537         } else if (request_irq(irq, ixgbe_test_intr, IRQF_SHARED,
1538                                netdev->name, netdev)) {
1539                 *data = 1;
1540                 return -1;
1541         }
1542         e_info(hw, "testing %s interrupt\n", shared_int ?
1543                "shared" : "unshared");
1544
1545         /* Disable all the interrupts */
1546         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
1547         IXGBE_WRITE_FLUSH(&adapter->hw);
1548         usleep_range(10000, 20000);
1549
1550         /* Test each interrupt */
1551         for (; i < 10; i++) {
1552                 /* Interrupt to test */
1553                 mask = 1 << i;
1554
1555                 if (!shared_int) {
1556                         /*
1557                          * Disable the interrupts to be reported in
1558                          * the cause register and then force the same
1559                          * interrupt and see if one gets posted.  If
1560                          * an interrupt was posted to the bus, the
1561                          * test failed.
1562                          */
1563                         adapter->test_icr = 0;
1564                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1565                                         ~mask & 0x00007FFF);
1566                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1567                                         ~mask & 0x00007FFF);
1568                         IXGBE_WRITE_FLUSH(&adapter->hw);
1569                         usleep_range(10000, 20000);
1570
1571                         if (adapter->test_icr & mask) {
1572                                 *data = 3;
1573                                 break;
1574                         }
1575                 }
1576
1577                 /*
1578                  * Enable the interrupt to be reported in the cause
1579                  * register and then force the same interrupt and see
1580                  * if one gets posted.  If an interrupt was not posted
1581                  * to the bus, the test failed.
1582                  */
1583                 adapter->test_icr = 0;
1584                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1585                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
1586                 IXGBE_WRITE_FLUSH(&adapter->hw);
1587                 usleep_range(10000, 20000);
1588
1589                 if (!(adapter->test_icr & mask)) {
1590                         *data = 4;
1591                         break;
1592                 }
1593
1594                 if (!shared_int) {
1595                         /*
1596                          * Disable the other interrupts to be reported in
1597                          * the cause register and then force the other
1598                          * interrupts and see if any get posted.  If
1599                          * an interrupt was posted to the bus, the
1600                          * test failed.
1601                          */
1602                         adapter->test_icr = 0;
1603                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1604                                         ~mask & 0x00007FFF);
1605                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1606                                         ~mask & 0x00007FFF);
1607                         IXGBE_WRITE_FLUSH(&adapter->hw);
1608                         usleep_range(10000, 20000);
1609
1610                         if (adapter->test_icr) {
1611                                 *data = 5;
1612                                 break;
1613                         }
1614                 }
1615         }
1616
1617         /* Disable all the interrupts */
1618         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
1619         IXGBE_WRITE_FLUSH(&adapter->hw);
1620         usleep_range(10000, 20000);
1621
1622         /* Unhook test interrupt handler */
1623         free_irq(irq, netdev);
1624
1625         return *data;
1626 }
1627
1628 static void ixgbe_free_desc_rings(struct ixgbe_adapter *adapter)
1629 {
1630         struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1631         struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1632         struct ixgbe_hw *hw = &adapter->hw;
1633         u32 reg_ctl;
1634
1635         /* shut down the DMA engines now so they can be reinitialized later */
1636
1637         /* first Rx */
1638         reg_ctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1639         reg_ctl &= ~IXGBE_RXCTRL_RXEN;
1640         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_ctl);
1641         ixgbe_disable_rx_queue(adapter, rx_ring);
1642
1643         /* now Tx */
1644         reg_ctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(tx_ring->reg_idx));
1645         reg_ctl &= ~IXGBE_TXDCTL_ENABLE;
1646         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(tx_ring->reg_idx), reg_ctl);
1647
1648         switch (hw->mac.type) {
1649         case ixgbe_mac_82599EB:
1650         case ixgbe_mac_X540:
1651                 reg_ctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1652                 reg_ctl &= ~IXGBE_DMATXCTL_TE;
1653                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg_ctl);
1654                 break;
1655         default:
1656                 break;
1657         }
1658
1659         ixgbe_reset(adapter);
1660
1661         ixgbe_free_tx_resources(&adapter->test_tx_ring);
1662         ixgbe_free_rx_resources(&adapter->test_rx_ring);
1663 }
1664
1665 static int ixgbe_setup_desc_rings(struct ixgbe_adapter *adapter)
1666 {
1667         struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1668         struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1669         u32 rctl, reg_data;
1670         int ret_val;
1671         int err;
1672
1673         /* Setup Tx descriptor ring and Tx buffers */
1674         tx_ring->count = IXGBE_DEFAULT_TXD;
1675         tx_ring->queue_index = 0;
1676         tx_ring->dev = &adapter->pdev->dev;
1677         tx_ring->netdev = adapter->netdev;
1678         tx_ring->reg_idx = adapter->tx_ring[0]->reg_idx;
1679
1680         err = ixgbe_setup_tx_resources(tx_ring);
1681         if (err)
1682                 return 1;
1683
1684         switch (adapter->hw.mac.type) {
1685         case ixgbe_mac_82599EB:
1686         case ixgbe_mac_X540:
1687                 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_DMATXCTL);
1688                 reg_data |= IXGBE_DMATXCTL_TE;
1689                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DMATXCTL, reg_data);
1690                 break;
1691         default:
1692                 break;
1693         }
1694
1695         ixgbe_configure_tx_ring(adapter, tx_ring);
1696
1697         /* Setup Rx Descriptor ring and Rx buffers */
1698         rx_ring->count = IXGBE_DEFAULT_RXD;
1699         rx_ring->queue_index = 0;
1700         rx_ring->dev = &adapter->pdev->dev;
1701         rx_ring->netdev = adapter->netdev;
1702         rx_ring->reg_idx = adapter->rx_ring[0]->reg_idx;
1703
1704         err = ixgbe_setup_rx_resources(rx_ring);
1705         if (err) {
1706                 ret_val = 4;
1707                 goto err_nomem;
1708         }
1709
1710         rctl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXCTRL);
1711         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl & ~IXGBE_RXCTRL_RXEN);
1712
1713         ixgbe_configure_rx_ring(adapter, rx_ring);
1714
1715         rctl |= IXGBE_RXCTRL_RXEN | IXGBE_RXCTRL_DMBYPS;
1716         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl);
1717
1718         return 0;
1719
1720 err_nomem:
1721         ixgbe_free_desc_rings(adapter);
1722         return ret_val;
1723 }
1724
1725 static int ixgbe_setup_loopback_test(struct ixgbe_adapter *adapter)
1726 {
1727         struct ixgbe_hw *hw = &adapter->hw;
1728         u32 reg_data;
1729
1730
1731         /* Setup MAC loopback */
1732         reg_data = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1733         reg_data |= IXGBE_HLREG0_LPBK;
1734         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, reg_data);
1735
1736         reg_data = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1737         reg_data |= IXGBE_FCTRL_BAM | IXGBE_FCTRL_SBP | IXGBE_FCTRL_MPE;
1738         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg_data);
1739
1740         /* X540 needs to set the MACC.FLU bit to force link up */
1741         if (adapter->hw.mac.type == ixgbe_mac_X540) {
1742                 reg_data = IXGBE_READ_REG(hw, IXGBE_MACC);
1743                 reg_data |= IXGBE_MACC_FLU;
1744                 IXGBE_WRITE_REG(hw, IXGBE_MACC, reg_data);
1745         } else {
1746                 if (hw->mac.orig_autoc) {
1747                         reg_data = hw->mac.orig_autoc | IXGBE_AUTOC_FLU;
1748                         IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_data);
1749                 } else {
1750                         return 10;
1751                 }
1752         }
1753         IXGBE_WRITE_FLUSH(hw);
1754         usleep_range(10000, 20000);
1755
1756         /* Disable Atlas Tx lanes; re-enabled in reset path */
1757         if (hw->mac.type == ixgbe_mac_82598EB) {
1758                 u8 atlas;
1759
1760                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &atlas);
1761                 atlas |= IXGBE_ATLAS_PDN_TX_REG_EN;
1762                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, atlas);
1763
1764                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, &atlas);
1765                 atlas |= IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
1766                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, atlas);
1767
1768                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, &atlas);
1769                 atlas |= IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
1770                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, atlas);
1771
1772                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, &atlas);
1773                 atlas |= IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
1774                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, atlas);
1775         }
1776
1777         return 0;
1778 }
1779
1780 static void ixgbe_loopback_cleanup(struct ixgbe_adapter *adapter)
1781 {
1782         u32 reg_data;
1783
1784         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1785         reg_data &= ~IXGBE_HLREG0_LPBK;
1786         IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1787 }
1788
1789 static void ixgbe_create_lbtest_frame(struct sk_buff *skb,
1790                                       unsigned int frame_size)
1791 {
1792         memset(skb->data, 0xFF, frame_size);
1793         frame_size >>= 1;
1794         memset(&skb->data[frame_size], 0xAA, frame_size / 2 - 1);
1795         memset(&skb->data[frame_size + 10], 0xBE, 1);
1796         memset(&skb->data[frame_size + 12], 0xAF, 1);
1797 }
1798
1799 static bool ixgbe_check_lbtest_frame(struct ixgbe_rx_buffer *rx_buffer,
1800                                      unsigned int frame_size)
1801 {
1802         unsigned char *data;
1803         bool match = true;
1804
1805         frame_size >>= 1;
1806
1807         data = kmap(rx_buffer->page) + rx_buffer->page_offset;
1808
1809         if (data[3] != 0xFF ||
1810             data[frame_size + 10] != 0xBE ||
1811             data[frame_size + 12] != 0xAF)
1812                 match = false;
1813
1814         kunmap(rx_buffer->page);
1815
1816         return match;
1817 }
1818
1819 static u16 ixgbe_clean_test_rings(struct ixgbe_ring *rx_ring,
1820                                   struct ixgbe_ring *tx_ring,
1821                                   unsigned int size)
1822 {
1823         union ixgbe_adv_rx_desc *rx_desc;
1824         struct ixgbe_rx_buffer *rx_buffer;
1825         struct ixgbe_tx_buffer *tx_buffer;
1826         u16 rx_ntc, tx_ntc, count = 0;
1827
1828         /* initialize next to clean and descriptor values */
1829         rx_ntc = rx_ring->next_to_clean;
1830         tx_ntc = tx_ring->next_to_clean;
1831         rx_desc = IXGBE_RX_DESC(rx_ring, rx_ntc);
1832
1833         while (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD)) {
1834                 /* check Rx buffer */
1835                 rx_buffer = &rx_ring->rx_buffer_info[rx_ntc];
1836
1837                 /* sync Rx buffer for CPU read */
1838                 dma_sync_single_for_cpu(rx_ring->dev,
1839                                         rx_buffer->dma,
1840                                         ixgbe_rx_bufsz(rx_ring),
1841                                         DMA_FROM_DEVICE);
1842
1843                 /* verify contents of skb */
1844                 if (ixgbe_check_lbtest_frame(rx_buffer, size))
1845                         count++;
1846
1847                 /* sync Rx buffer for device write */
1848                 dma_sync_single_for_device(rx_ring->dev,
1849                                            rx_buffer->dma,
1850                                            ixgbe_rx_bufsz(rx_ring),
1851                                            DMA_FROM_DEVICE);
1852
1853                 /* unmap buffer on Tx side */
1854                 tx_buffer = &tx_ring->tx_buffer_info[tx_ntc];
1855                 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
1856
1857                 /* increment Rx/Tx next to clean counters */
1858                 rx_ntc++;
1859                 if (rx_ntc == rx_ring->count)
1860                         rx_ntc = 0;
1861                 tx_ntc++;
1862                 if (tx_ntc == tx_ring->count)
1863                         tx_ntc = 0;
1864
1865                 /* fetch next descriptor */
1866                 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ntc);
1867         }
1868
1869         netdev_tx_reset_queue(txring_txq(tx_ring));
1870
1871         /* re-map buffers to ring, store next to clean values */
1872         ixgbe_alloc_rx_buffers(rx_ring, count);
1873         rx_ring->next_to_clean = rx_ntc;
1874         tx_ring->next_to_clean = tx_ntc;
1875
1876         return count;
1877 }
1878
1879 static int ixgbe_run_loopback_test(struct ixgbe_adapter *adapter)
1880 {
1881         struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1882         struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1883         int i, j, lc, good_cnt, ret_val = 0;
1884         unsigned int size = 1024;
1885         netdev_tx_t tx_ret_val;
1886         struct sk_buff *skb;
1887         u32 flags_orig = adapter->flags;
1888
1889         /* DCB can modify the frames on Tx */
1890         adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
1891
1892         /* allocate test skb */
1893         skb = alloc_skb(size, GFP_KERNEL);
1894         if (!skb)
1895                 return 11;
1896
1897         /* place data into test skb */
1898         ixgbe_create_lbtest_frame(skb, size);
1899         skb_put(skb, size);
1900
1901         /*
1902          * Calculate the loop count based on the largest descriptor ring
1903          * The idea is to wrap the largest ring a number of times using 64
1904          * send/receive pairs during each loop
1905          */
1906
1907         if (rx_ring->count <= tx_ring->count)
1908                 lc = ((tx_ring->count / 64) * 2) + 1;
1909         else
1910                 lc = ((rx_ring->count / 64) * 2) + 1;
1911
1912         for (j = 0; j <= lc; j++) {
1913                 /* reset count of good packets */
1914                 good_cnt = 0;
1915
1916                 /* place 64 packets on the transmit queue*/
1917                 for (i = 0; i < 64; i++) {
1918                         skb_get(skb);
1919                         tx_ret_val = ixgbe_xmit_frame_ring(skb,
1920                                                            adapter,
1921                                                            tx_ring);
1922                         if (tx_ret_val == NETDEV_TX_OK)
1923                                 good_cnt++;
1924                 }
1925
1926                 if (good_cnt != 64) {
1927                         ret_val = 12;
1928                         break;
1929                 }
1930
1931                 /* allow 200 milliseconds for packets to go from Tx to Rx */
1932                 msleep(200);
1933
1934                 good_cnt = ixgbe_clean_test_rings(rx_ring, tx_ring, size);
1935                 if (good_cnt != 64) {
1936                         ret_val = 13;
1937                         break;
1938                 }
1939         }
1940
1941         /* free the original skb */
1942         kfree_skb(skb);
1943         adapter->flags = flags_orig;
1944
1945         return ret_val;
1946 }
1947
1948 static int ixgbe_loopback_test(struct ixgbe_adapter *adapter, u64 *data)
1949 {
1950         *data = ixgbe_setup_desc_rings(adapter);
1951         if (*data)
1952                 goto out;
1953         *data = ixgbe_setup_loopback_test(adapter);
1954         if (*data)
1955                 goto err_loopback;
1956         *data = ixgbe_run_loopback_test(adapter);
1957         ixgbe_loopback_cleanup(adapter);
1958
1959 err_loopback:
1960         ixgbe_free_desc_rings(adapter);
1961 out:
1962         return *data;
1963 }
1964
1965 static void ixgbe_diag_test(struct net_device *netdev,
1966                             struct ethtool_test *eth_test, u64 *data)
1967 {
1968         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1969         bool if_running = netif_running(netdev);
1970
1971         if (ixgbe_removed(adapter->hw.hw_addr)) {
1972                 e_err(hw, "Adapter removed - test blocked\n");
1973                 data[0] = 1;
1974                 data[1] = 1;
1975                 data[2] = 1;
1976                 data[3] = 1;
1977                 data[4] = 1;
1978                 eth_test->flags |= ETH_TEST_FL_FAILED;
1979                 return;
1980         }
1981         set_bit(__IXGBE_TESTING, &adapter->state);
1982         if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
1983                 struct ixgbe_hw *hw = &adapter->hw;
1984
1985                 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
1986                         int i;
1987                         for (i = 0; i < adapter->num_vfs; i++) {
1988                                 if (adapter->vfinfo[i].clear_to_send) {
1989                                         netdev_warn(netdev, "offline diagnostic is not supported when VFs are present\n");
1990                                         data[0] = 1;
1991                                         data[1] = 1;
1992                                         data[2] = 1;
1993                                         data[3] = 1;
1994                                         data[4] = 1;
1995                                         eth_test->flags |= ETH_TEST_FL_FAILED;
1996                                         clear_bit(__IXGBE_TESTING,
1997                                                   &adapter->state);
1998                                         goto skip_ol_tests;
1999                                 }
2000                         }
2001                 }
2002
2003                 /* Offline tests */
2004                 e_info(hw, "offline testing starting\n");
2005
2006                 /* Link test performed before hardware reset so autoneg doesn't
2007                  * interfere with test result
2008                  */
2009                 if (ixgbe_link_test(adapter, &data[4]))
2010                         eth_test->flags |= ETH_TEST_FL_FAILED;
2011
2012                 if (if_running)
2013                         /* indicate we're in test mode */
2014                         dev_close(netdev);
2015                 else
2016                         ixgbe_reset(adapter);
2017
2018                 e_info(hw, "register testing starting\n");
2019                 if (ixgbe_reg_test(adapter, &data[0]))
2020                         eth_test->flags |= ETH_TEST_FL_FAILED;
2021
2022                 ixgbe_reset(adapter);
2023                 e_info(hw, "eeprom testing starting\n");
2024                 if (ixgbe_eeprom_test(adapter, &data[1]))
2025                         eth_test->flags |= ETH_TEST_FL_FAILED;
2026
2027                 ixgbe_reset(adapter);
2028                 e_info(hw, "interrupt testing starting\n");
2029                 if (ixgbe_intr_test(adapter, &data[2]))
2030                         eth_test->flags |= ETH_TEST_FL_FAILED;
2031
2032                 /* If SRIOV or VMDq is enabled then skip MAC
2033                  * loopback diagnostic. */
2034                 if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED |
2035                                       IXGBE_FLAG_VMDQ_ENABLED)) {
2036                         e_info(hw, "Skip MAC loopback diagnostic in VT mode\n");
2037                         data[3] = 0;
2038                         goto skip_loopback;
2039                 }
2040
2041                 ixgbe_reset(adapter);
2042                 e_info(hw, "loopback testing starting\n");
2043                 if (ixgbe_loopback_test(adapter, &data[3]))
2044                         eth_test->flags |= ETH_TEST_FL_FAILED;
2045
2046 skip_loopback:
2047                 ixgbe_reset(adapter);
2048
2049                 /* clear testing bit and return adapter to previous state */
2050                 clear_bit(__IXGBE_TESTING, &adapter->state);
2051                 if (if_running)
2052                         dev_open(netdev);
2053                 else if (hw->mac.ops.disable_tx_laser)
2054                         hw->mac.ops.disable_tx_laser(hw);
2055         } else {
2056                 e_info(hw, "online testing starting\n");
2057
2058                 /* Online tests */
2059                 if (ixgbe_link_test(adapter, &data[4]))
2060                         eth_test->flags |= ETH_TEST_FL_FAILED;
2061
2062                 /* Offline tests aren't run; pass by default */
2063                 data[0] = 0;
2064                 data[1] = 0;
2065                 data[2] = 0;
2066                 data[3] = 0;
2067
2068                 clear_bit(__IXGBE_TESTING, &adapter->state);
2069         }
2070
2071 skip_ol_tests:
2072         msleep_interruptible(4 * 1000);
2073 }
2074
2075 static int ixgbe_wol_exclusion(struct ixgbe_adapter *adapter,
2076                                struct ethtool_wolinfo *wol)
2077 {
2078         struct ixgbe_hw *hw = &adapter->hw;
2079         int retval = 0;
2080
2081         /* WOL not supported for all devices */
2082         if (!ixgbe_wol_supported(adapter, hw->device_id,
2083                                  hw->subsystem_device_id)) {
2084                 retval = 1;
2085                 wol->supported = 0;
2086         }
2087
2088         return retval;
2089 }
2090
2091 static void ixgbe_get_wol(struct net_device *netdev,
2092                           struct ethtool_wolinfo *wol)
2093 {
2094         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2095
2096         wol->supported = WAKE_UCAST | WAKE_MCAST |
2097                          WAKE_BCAST | WAKE_MAGIC;
2098         wol->wolopts = 0;
2099
2100         if (ixgbe_wol_exclusion(adapter, wol) ||
2101             !device_can_wakeup(&adapter->pdev->dev))
2102                 return;
2103
2104         if (adapter->wol & IXGBE_WUFC_EX)
2105                 wol->wolopts |= WAKE_UCAST;
2106         if (adapter->wol & IXGBE_WUFC_MC)
2107                 wol->wolopts |= WAKE_MCAST;
2108         if (adapter->wol & IXGBE_WUFC_BC)
2109                 wol->wolopts |= WAKE_BCAST;
2110         if (adapter->wol & IXGBE_WUFC_MAG)
2111                 wol->wolopts |= WAKE_MAGIC;
2112 }
2113
2114 static int ixgbe_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2115 {
2116         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2117
2118         if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
2119                 return -EOPNOTSUPP;
2120
2121         if (ixgbe_wol_exclusion(adapter, wol))
2122                 return wol->wolopts ? -EOPNOTSUPP : 0;
2123
2124         adapter->wol = 0;
2125
2126         if (wol->wolopts & WAKE_UCAST)
2127                 adapter->wol |= IXGBE_WUFC_EX;
2128         if (wol->wolopts & WAKE_MCAST)
2129                 adapter->wol |= IXGBE_WUFC_MC;
2130         if (wol->wolopts & WAKE_BCAST)
2131                 adapter->wol |= IXGBE_WUFC_BC;
2132         if (wol->wolopts & WAKE_MAGIC)
2133                 adapter->wol |= IXGBE_WUFC_MAG;
2134
2135         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
2136
2137         return 0;
2138 }
2139
2140 static int ixgbe_nway_reset(struct net_device *netdev)
2141 {
2142         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2143
2144         if (netif_running(netdev))
2145                 ixgbe_reinit_locked(adapter);
2146
2147         return 0;
2148 }
2149
2150 static int ixgbe_set_phys_id(struct net_device *netdev,
2151                              enum ethtool_phys_id_state state)
2152 {
2153         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2154         struct ixgbe_hw *hw = &adapter->hw;
2155
2156         switch (state) {
2157         case ETHTOOL_ID_ACTIVE:
2158                 adapter->led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2159                 return 2;
2160
2161         case ETHTOOL_ID_ON:
2162                 hw->mac.ops.led_on(hw, IXGBE_LED_ON);
2163                 break;
2164
2165         case ETHTOOL_ID_OFF:
2166                 hw->mac.ops.led_off(hw, IXGBE_LED_ON);
2167                 break;
2168
2169         case ETHTOOL_ID_INACTIVE:
2170                 /* Restore LED settings */
2171                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_LEDCTL, adapter->led_reg);
2172                 break;
2173         }
2174
2175         return 0;
2176 }
2177
2178 static int ixgbe_get_coalesce(struct net_device *netdev,
2179                               struct ethtool_coalesce *ec)
2180 {
2181         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2182
2183         /* only valid if in constant ITR mode */
2184         if (adapter->rx_itr_setting <= 1)
2185                 ec->rx_coalesce_usecs = adapter->rx_itr_setting;
2186         else
2187                 ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2;
2188
2189         /* if in mixed tx/rx queues per vector mode, report only rx settings */
2190         if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count)
2191                 return 0;
2192
2193         /* only valid if in constant ITR mode */
2194         if (adapter->tx_itr_setting <= 1)
2195                 ec->tx_coalesce_usecs = adapter->tx_itr_setting;
2196         else
2197                 ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2;
2198
2199         return 0;
2200 }
2201
2202 /*
2203  * this function must be called before setting the new value of
2204  * rx_itr_setting
2205  */
2206 static bool ixgbe_update_rsc(struct ixgbe_adapter *adapter)
2207 {
2208         struct net_device *netdev = adapter->netdev;
2209
2210         /* nothing to do if LRO or RSC are not enabled */
2211         if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) ||
2212             !(netdev->features & NETIF_F_LRO))
2213                 return false;
2214
2215         /* check the feature flag value and enable RSC if necessary */
2216         if (adapter->rx_itr_setting == 1 ||
2217             adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
2218                 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
2219                         adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
2220                         e_info(probe, "rx-usecs value high enough to re-enable RSC\n");
2221                         return true;
2222                 }
2223         /* if interrupt rate is too high then disable RSC */
2224         } else if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
2225                 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
2226                 e_info(probe, "rx-usecs set too low, disabling RSC\n");
2227                 return true;
2228         }
2229         return false;
2230 }
2231
2232 static int ixgbe_set_coalesce(struct net_device *netdev,
2233                               struct ethtool_coalesce *ec)
2234 {
2235         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2236         struct ixgbe_q_vector *q_vector;
2237         int i;
2238         u16 tx_itr_param, rx_itr_param, tx_itr_prev;
2239         bool need_reset = false;
2240
2241         if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count) {
2242                 /* reject Tx specific changes in case of mixed RxTx vectors */
2243                 if (ec->tx_coalesce_usecs)
2244                         return -EINVAL;
2245                 tx_itr_prev = adapter->rx_itr_setting;
2246         } else {
2247                 tx_itr_prev = adapter->tx_itr_setting;
2248         }
2249
2250         if ((ec->rx_coalesce_usecs > (IXGBE_MAX_EITR >> 2)) ||
2251             (ec->tx_coalesce_usecs > (IXGBE_MAX_EITR >> 2)))
2252                 return -EINVAL;
2253
2254         if (ec->rx_coalesce_usecs > 1)
2255                 adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2;
2256         else
2257                 adapter->rx_itr_setting = ec->rx_coalesce_usecs;
2258
2259         if (adapter->rx_itr_setting == 1)
2260                 rx_itr_param = IXGBE_20K_ITR;
2261         else
2262                 rx_itr_param = adapter->rx_itr_setting;
2263
2264         if (ec->tx_coalesce_usecs > 1)
2265                 adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2;
2266         else
2267                 adapter->tx_itr_setting = ec->tx_coalesce_usecs;
2268
2269         if (adapter->tx_itr_setting == 1)
2270                 tx_itr_param = IXGBE_10K_ITR;
2271         else
2272                 tx_itr_param = adapter->tx_itr_setting;
2273
2274         /* mixed Rx/Tx */
2275         if (adapter->q_vector[0]->tx.count && adapter->q_vector[0]->rx.count)
2276                 adapter->tx_itr_setting = adapter->rx_itr_setting;
2277
2278 #if IS_ENABLED(CONFIG_BQL)
2279         /* detect ITR changes that require update of TXDCTL.WTHRESH */
2280         if ((adapter->tx_itr_setting != 1) &&
2281             (adapter->tx_itr_setting < IXGBE_100K_ITR)) {
2282                 if ((tx_itr_prev == 1) ||
2283                     (tx_itr_prev >= IXGBE_100K_ITR))
2284                         need_reset = true;
2285         } else {
2286                 if ((tx_itr_prev != 1) &&
2287                     (tx_itr_prev < IXGBE_100K_ITR))
2288                         need_reset = true;
2289         }
2290 #endif
2291         /* check the old value and enable RSC if necessary */
2292         need_reset |= ixgbe_update_rsc(adapter);
2293
2294         for (i = 0; i < adapter->num_q_vectors; i++) {
2295                 q_vector = adapter->q_vector[i];
2296                 if (q_vector->tx.count && !q_vector->rx.count)
2297                         /* tx only */
2298                         q_vector->itr = tx_itr_param;
2299                 else
2300                         /* rx only or mixed */
2301                         q_vector->itr = rx_itr_param;
2302                 ixgbe_write_eitr(q_vector);
2303         }
2304
2305         /*
2306          * do reset here at the end to make sure EITR==0 case is handled
2307          * correctly w.r.t stopping tx, and changing TXDCTL.WTHRESH settings
2308          * also locks in RSC enable/disable which requires reset
2309          */
2310         if (need_reset)
2311                 ixgbe_do_reset(netdev);
2312
2313         return 0;
2314 }
2315
2316 static int ixgbe_get_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2317                                         struct ethtool_rxnfc *cmd)
2318 {
2319         union ixgbe_atr_input *mask = &adapter->fdir_mask;
2320         struct ethtool_rx_flow_spec *fsp =
2321                 (struct ethtool_rx_flow_spec *)&cmd->fs;
2322         struct hlist_node *node2;
2323         struct ixgbe_fdir_filter *rule = NULL;
2324
2325         /* report total rule count */
2326         cmd->data = (1024 << adapter->fdir_pballoc) - 2;
2327
2328         hlist_for_each_entry_safe(rule, node2,
2329                                   &adapter->fdir_filter_list, fdir_node) {
2330                 if (fsp->location <= rule->sw_idx)
2331                         break;
2332         }
2333
2334         if (!rule || fsp->location != rule->sw_idx)
2335                 return -EINVAL;
2336
2337         /* fill out the flow spec entry */
2338
2339         /* set flow type field */
2340         switch (rule->filter.formatted.flow_type) {
2341         case IXGBE_ATR_FLOW_TYPE_TCPV4:
2342                 fsp->flow_type = TCP_V4_FLOW;
2343                 break;
2344         case IXGBE_ATR_FLOW_TYPE_UDPV4:
2345                 fsp->flow_type = UDP_V4_FLOW;
2346                 break;
2347         case IXGBE_ATR_FLOW_TYPE_SCTPV4:
2348                 fsp->flow_type = SCTP_V4_FLOW;
2349                 break;
2350         case IXGBE_ATR_FLOW_TYPE_IPV4:
2351                 fsp->flow_type = IP_USER_FLOW;
2352                 fsp->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4;
2353                 fsp->h_u.usr_ip4_spec.proto = 0;
2354                 fsp->m_u.usr_ip4_spec.proto = 0;
2355                 break;
2356         default:
2357                 return -EINVAL;
2358         }
2359
2360         fsp->h_u.tcp_ip4_spec.psrc = rule->filter.formatted.src_port;
2361         fsp->m_u.tcp_ip4_spec.psrc = mask->formatted.src_port;
2362         fsp->h_u.tcp_ip4_spec.pdst = rule->filter.formatted.dst_port;
2363         fsp->m_u.tcp_ip4_spec.pdst = mask->formatted.dst_port;
2364         fsp->h_u.tcp_ip4_spec.ip4src = rule->filter.formatted.src_ip[0];
2365         fsp->m_u.tcp_ip4_spec.ip4src = mask->formatted.src_ip[0];
2366         fsp->h_u.tcp_ip4_spec.ip4dst = rule->filter.formatted.dst_ip[0];
2367         fsp->m_u.tcp_ip4_spec.ip4dst = mask->formatted.dst_ip[0];
2368         fsp->h_ext.vlan_tci = rule->filter.formatted.vlan_id;
2369         fsp->m_ext.vlan_tci = mask->formatted.vlan_id;
2370         fsp->h_ext.vlan_etype = rule->filter.formatted.flex_bytes;
2371         fsp->m_ext.vlan_etype = mask->formatted.flex_bytes;
2372         fsp->h_ext.data[1] = htonl(rule->filter.formatted.vm_pool);
2373         fsp->m_ext.data[1] = htonl(mask->formatted.vm_pool);
2374         fsp->flow_type |= FLOW_EXT;
2375
2376         /* record action */
2377         if (rule->action == IXGBE_FDIR_DROP_QUEUE)
2378                 fsp->ring_cookie = RX_CLS_FLOW_DISC;
2379         else
2380                 fsp->ring_cookie = rule->action;
2381
2382         return 0;
2383 }
2384
2385 static int ixgbe_get_ethtool_fdir_all(struct ixgbe_adapter *adapter,
2386                                       struct ethtool_rxnfc *cmd,
2387                                       u32 *rule_locs)
2388 {
2389         struct hlist_node *node2;
2390         struct ixgbe_fdir_filter *rule;
2391         int cnt = 0;
2392
2393         /* report total rule count */
2394         cmd->data = (1024 << adapter->fdir_pballoc) - 2;
2395
2396         hlist_for_each_entry_safe(rule, node2,
2397                                   &adapter->fdir_filter_list, fdir_node) {
2398                 if (cnt == cmd->rule_cnt)
2399                         return -EMSGSIZE;
2400                 rule_locs[cnt] = rule->sw_idx;
2401                 cnt++;
2402         }
2403
2404         cmd->rule_cnt = cnt;
2405
2406         return 0;
2407 }
2408
2409 static int ixgbe_get_rss_hash_opts(struct ixgbe_adapter *adapter,
2410                                    struct ethtool_rxnfc *cmd)
2411 {
2412         cmd->data = 0;
2413
2414         /* Report default options for RSS on ixgbe */
2415         switch (cmd->flow_type) {
2416         case TCP_V4_FLOW:
2417                 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2418         case UDP_V4_FLOW:
2419                 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
2420                         cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2421         case SCTP_V4_FLOW:
2422         case AH_ESP_V4_FLOW:
2423         case AH_V4_FLOW:
2424         case ESP_V4_FLOW:
2425         case IPV4_FLOW:
2426                 cmd->data |= RXH_IP_SRC | RXH_IP_DST;
2427                 break;
2428         case TCP_V6_FLOW:
2429                 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2430         case UDP_V6_FLOW:
2431                 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
2432                         cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2433         case SCTP_V6_FLOW:
2434         case AH_ESP_V6_FLOW:
2435         case AH_V6_FLOW:
2436         case ESP_V6_FLOW:
2437         case IPV6_FLOW:
2438                 cmd->data |= RXH_IP_SRC | RXH_IP_DST;
2439                 break;
2440         default:
2441                 return -EINVAL;
2442         }
2443
2444         return 0;
2445 }
2446
2447 static int ixgbe_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
2448                            u32 *rule_locs)
2449 {
2450         struct ixgbe_adapter *adapter = netdev_priv(dev);
2451         int ret = -EOPNOTSUPP;
2452
2453         switch (cmd->cmd) {
2454         case ETHTOOL_GRXRINGS:
2455                 cmd->data = adapter->num_rx_queues;
2456                 ret = 0;
2457                 break;
2458         case ETHTOOL_GRXCLSRLCNT:
2459                 cmd->rule_cnt = adapter->fdir_filter_count;
2460                 ret = 0;
2461                 break;
2462         case ETHTOOL_GRXCLSRULE:
2463                 ret = ixgbe_get_ethtool_fdir_entry(adapter, cmd);
2464                 break;
2465         case ETHTOOL_GRXCLSRLALL:
2466                 ret = ixgbe_get_ethtool_fdir_all(adapter, cmd, rule_locs);
2467                 break;
2468         case ETHTOOL_GRXFH:
2469                 ret = ixgbe_get_rss_hash_opts(adapter, cmd);
2470                 break;
2471         default:
2472                 break;
2473         }
2474
2475         return ret;
2476 }
2477
2478 static int ixgbe_update_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2479                                            struct ixgbe_fdir_filter *input,
2480                                            u16 sw_idx)
2481 {
2482         struct ixgbe_hw *hw = &adapter->hw;
2483         struct hlist_node *node2;
2484         struct ixgbe_fdir_filter *rule, *parent;
2485         int err = -EINVAL;
2486
2487         parent = NULL;
2488         rule = NULL;
2489
2490         hlist_for_each_entry_safe(rule, node2,
2491                                   &adapter->fdir_filter_list, fdir_node) {
2492                 /* hash found, or no matching entry */
2493                 if (rule->sw_idx >= sw_idx)
2494                         break;
2495                 parent = rule;
2496         }
2497
2498         /* if there is an old rule occupying our place remove it */
2499         if (rule && (rule->sw_idx == sw_idx)) {
2500                 if (!input || (rule->filter.formatted.bkt_hash !=
2501                                input->filter.formatted.bkt_hash)) {
2502                         err = ixgbe_fdir_erase_perfect_filter_82599(hw,
2503                                                                 &rule->filter,
2504                                                                 sw_idx);
2505                 }
2506
2507                 hlist_del(&rule->fdir_node);
2508                 kfree(rule);
2509                 adapter->fdir_filter_count--;
2510         }
2511
2512         /*
2513          * If no input this was a delete, err should be 0 if a rule was
2514          * successfully found and removed from the list else -EINVAL
2515          */
2516         if (!input)
2517                 return err;
2518
2519         /* initialize node and set software index */
2520         INIT_HLIST_NODE(&input->fdir_node);
2521
2522         /* add filter to the list */
2523         if (parent)
2524                 hlist_add_after(&parent->fdir_node, &input->fdir_node);
2525         else
2526                 hlist_add_head(&input->fdir_node,
2527                                &adapter->fdir_filter_list);
2528
2529         /* update counts */
2530         adapter->fdir_filter_count++;
2531
2532         return 0;
2533 }
2534
2535 static int ixgbe_flowspec_to_flow_type(struct ethtool_rx_flow_spec *fsp,
2536                                        u8 *flow_type)
2537 {
2538         switch (fsp->flow_type & ~FLOW_EXT) {
2539         case TCP_V4_FLOW:
2540                 *flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
2541                 break;
2542         case UDP_V4_FLOW:
2543                 *flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4;
2544                 break;
2545         case SCTP_V4_FLOW:
2546                 *flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4;
2547                 break;
2548         case IP_USER_FLOW:
2549                 switch (fsp->h_u.usr_ip4_spec.proto) {
2550                 case IPPROTO_TCP:
2551                         *flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
2552                         break;
2553                 case IPPROTO_UDP:
2554                         *flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4;
2555                         break;
2556                 case IPPROTO_SCTP:
2557                         *flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4;
2558                         break;
2559                 case 0:
2560                         if (!fsp->m_u.usr_ip4_spec.proto) {
2561                                 *flow_type = IXGBE_ATR_FLOW_TYPE_IPV4;
2562                                 break;
2563                         }
2564                 default:
2565                         return 0;
2566                 }
2567                 break;
2568         default:
2569                 return 0;
2570         }
2571
2572         return 1;
2573 }
2574
2575 static int ixgbe_add_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2576                                         struct ethtool_rxnfc *cmd)
2577 {
2578         struct ethtool_rx_flow_spec *fsp =
2579                 (struct ethtool_rx_flow_spec *)&cmd->fs;
2580         struct ixgbe_hw *hw = &adapter->hw;
2581         struct ixgbe_fdir_filter *input;
2582         union ixgbe_atr_input mask;
2583         int err;
2584
2585         if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
2586                 return -EOPNOTSUPP;
2587
2588         /*
2589          * Don't allow programming if the action is a queue greater than
2590          * the number of online Rx queues.
2591          */
2592         if ((fsp->ring_cookie != RX_CLS_FLOW_DISC) &&
2593             (fsp->ring_cookie >= adapter->num_rx_queues))
2594                 return -EINVAL;
2595
2596         /* Don't allow indexes to exist outside of available space */
2597         if (fsp->location >= ((1024 << adapter->fdir_pballoc) - 2)) {
2598                 e_err(drv, "Location out of range\n");
2599                 return -EINVAL;
2600         }
2601
2602         input = kzalloc(sizeof(*input), GFP_ATOMIC);
2603         if (!input)
2604                 return -ENOMEM;
2605
2606         memset(&mask, 0, sizeof(union ixgbe_atr_input));
2607
2608         /* set SW index */
2609         input->sw_idx = fsp->location;
2610
2611         /* record flow type */
2612         if (!ixgbe_flowspec_to_flow_type(fsp,
2613                                          &input->filter.formatted.flow_type)) {
2614                 e_err(drv, "Unrecognized flow type\n");
2615                 goto err_out;
2616         }
2617
2618         mask.formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
2619                                    IXGBE_ATR_L4TYPE_MASK;
2620
2621         if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4)
2622                 mask.formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK;
2623
2624         /* Copy input into formatted structures */
2625         input->filter.formatted.src_ip[0] = fsp->h_u.tcp_ip4_spec.ip4src;
2626         mask.formatted.src_ip[0] = fsp->m_u.tcp_ip4_spec.ip4src;
2627         input->filter.formatted.dst_ip[0] = fsp->h_u.tcp_ip4_spec.ip4dst;
2628         mask.formatted.dst_ip[0] = fsp->m_u.tcp_ip4_spec.ip4dst;
2629         input->filter.formatted.src_port = fsp->h_u.tcp_ip4_spec.psrc;
2630         mask.formatted.src_port = fsp->m_u.tcp_ip4_spec.psrc;
2631         input->filter.formatted.dst_port = fsp->h_u.tcp_ip4_spec.pdst;
2632         mask.formatted.dst_port = fsp->m_u.tcp_ip4_spec.pdst;
2633
2634         if (fsp->flow_type & FLOW_EXT) {
2635                 input->filter.formatted.vm_pool =
2636                                 (unsigned char)ntohl(fsp->h_ext.data[1]);
2637                 mask.formatted.vm_pool =
2638                                 (unsigned char)ntohl(fsp->m_ext.data[1]);
2639                 input->filter.formatted.vlan_id = fsp->h_ext.vlan_tci;
2640                 mask.formatted.vlan_id = fsp->m_ext.vlan_tci;
2641                 input->filter.formatted.flex_bytes =
2642                                                 fsp->h_ext.vlan_etype;
2643                 mask.formatted.flex_bytes = fsp->m_ext.vlan_etype;
2644         }
2645
2646         /* determine if we need to drop or route the packet */
2647         if (fsp->ring_cookie == RX_CLS_FLOW_DISC)
2648                 input->action = IXGBE_FDIR_DROP_QUEUE;
2649         else
2650                 input->action = fsp->ring_cookie;
2651
2652         spin_lock(&adapter->fdir_perfect_lock);
2653
2654         if (hlist_empty(&adapter->fdir_filter_list)) {
2655                 /* save mask and program input mask into HW */
2656                 memcpy(&adapter->fdir_mask, &mask, sizeof(mask));
2657                 err = ixgbe_fdir_set_input_mask_82599(hw, &mask);
2658                 if (err) {
2659                         e_err(drv, "Error writing mask\n");
2660                         goto err_out_w_lock;
2661                 }
2662         } else if (memcmp(&adapter->fdir_mask, &mask, sizeof(mask))) {
2663                 e_err(drv, "Only one mask supported per port\n");
2664                 goto err_out_w_lock;
2665         }
2666
2667         /* apply mask and compute/store hash */
2668         ixgbe_atr_compute_perfect_hash_82599(&input->filter, &mask);
2669
2670         /* program filters to filter memory */
2671         err = ixgbe_fdir_write_perfect_filter_82599(hw,
2672                                 &input->filter, input->sw_idx,
2673                                 (input->action == IXGBE_FDIR_DROP_QUEUE) ?
2674                                 IXGBE_FDIR_DROP_QUEUE :
2675                                 adapter->rx_ring[input->action]->reg_idx);
2676         if (err)
2677                 goto err_out_w_lock;
2678
2679         ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx);
2680
2681         spin_unlock(&adapter->fdir_perfect_lock);
2682
2683         return err;
2684 err_out_w_lock:
2685         spin_unlock(&adapter->fdir_perfect_lock);
2686 err_out:
2687         kfree(input);
2688         return -EINVAL;
2689 }
2690
2691 static int ixgbe_del_ethtool_fdir_entry(struct ixgbe_adapter *adapter,
2692                                         struct ethtool_rxnfc *cmd)
2693 {
2694         struct ethtool_rx_flow_spec *fsp =
2695                 (struct ethtool_rx_flow_spec *)&cmd->fs;
2696         int err;
2697
2698         spin_lock(&adapter->fdir_perfect_lock);
2699         err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, fsp->location);
2700         spin_unlock(&adapter->fdir_perfect_lock);
2701
2702         return err;
2703 }
2704
2705 #define UDP_RSS_FLAGS (IXGBE_FLAG2_RSS_FIELD_IPV4_UDP | \
2706                        IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
2707 static int ixgbe_set_rss_hash_opt(struct ixgbe_adapter *adapter,
2708                                   struct ethtool_rxnfc *nfc)
2709 {
2710         u32 flags2 = adapter->flags2;
2711
2712         /*
2713          * RSS does not support anything other than hashing
2714          * to queues on src and dst IPs and ports
2715          */
2716         if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
2717                           RXH_L4_B_0_1 | RXH_L4_B_2_3))
2718                 return -EINVAL;
2719
2720         switch (nfc->flow_type) {
2721         case TCP_V4_FLOW:
2722         case TCP_V6_FLOW:
2723                 if (!(nfc->data & RXH_IP_SRC) ||
2724                     !(nfc->data & RXH_IP_DST) ||
2725                     !(nfc->data & RXH_L4_B_0_1) ||
2726                     !(nfc->data & RXH_L4_B_2_3))
2727                         return -EINVAL;
2728                 break;
2729         case UDP_V4_FLOW:
2730                 if (!(nfc->data & RXH_IP_SRC) ||
2731                     !(nfc->data & RXH_IP_DST))
2732                         return -EINVAL;
2733                 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2734                 case 0:
2735                         flags2 &= ~IXGBE_FLAG2_RSS_FIELD_IPV4_UDP;
2736                         break;
2737                 case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
2738                         flags2 |= IXGBE_FLAG2_RSS_FIELD_IPV4_UDP;
2739                         break;
2740                 default:
2741                         return -EINVAL;
2742                 }
2743                 break;
2744         case UDP_V6_FLOW:
2745                 if (!(nfc->data & RXH_IP_SRC) ||
2746                     !(nfc->data & RXH_IP_DST))
2747                         return -EINVAL;
2748                 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2749                 case 0:
2750                         flags2 &= ~IXGBE_FLAG2_RSS_FIELD_IPV6_UDP;
2751                         break;
2752                 case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
2753                         flags2 |= IXGBE_FLAG2_RSS_FIELD_IPV6_UDP;
2754                         break;
2755                 default:
2756                         return -EINVAL;
2757                 }
2758                 break;
2759         case AH_ESP_V4_FLOW:
2760         case AH_V4_FLOW:
2761         case ESP_V4_FLOW:
2762         case SCTP_V4_FLOW:
2763         case AH_ESP_V6_FLOW:
2764         case AH_V6_FLOW:
2765         case ESP_V6_FLOW:
2766         case SCTP_V6_FLOW:
2767                 if (!(nfc->data & RXH_IP_SRC) ||
2768                     !(nfc->data & RXH_IP_DST) ||
2769                     (nfc->data & RXH_L4_B_0_1) ||
2770                     (nfc->data & RXH_L4_B_2_3))
2771                         return -EINVAL;
2772                 break;
2773         default:
2774                 return -EINVAL;
2775         }
2776
2777         /* if we changed something we need to update flags */
2778         if (flags2 != adapter->flags2) {
2779                 struct ixgbe_hw *hw = &adapter->hw;
2780                 u32 mrqc = IXGBE_READ_REG(hw, IXGBE_MRQC);
2781
2782                 if ((flags2 & UDP_RSS_FLAGS) &&
2783                     !(adapter->flags2 & UDP_RSS_FLAGS))
2784                         e_warn(drv, "enabling UDP RSS: fragmented packets may arrive out of order to the stack above\n");
2785
2786                 adapter->flags2 = flags2;
2787
2788                 /* Perform hash on these packet types */
2789                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2790                       | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2791                       | IXGBE_MRQC_RSS_FIELD_IPV6
2792                       | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2793
2794                 mrqc &= ~(IXGBE_MRQC_RSS_FIELD_IPV4_UDP |
2795                           IXGBE_MRQC_RSS_FIELD_IPV6_UDP);
2796
2797                 if (flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
2798                         mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
2799
2800                 if (flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
2801                         mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2802
2803                 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2804         }
2805
2806         return 0;
2807 }
2808
2809 static int ixgbe_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
2810 {
2811         struct ixgbe_adapter *adapter = netdev_priv(dev);
2812         int ret = -EOPNOTSUPP;
2813
2814         switch (cmd->cmd) {
2815         case ETHTOOL_SRXCLSRLINS:
2816                 ret = ixgbe_add_ethtool_fdir_entry(adapter, cmd);
2817                 break;
2818         case ETHTOOL_SRXCLSRLDEL:
2819                 ret = ixgbe_del_ethtool_fdir_entry(adapter, cmd);
2820                 break;
2821         case ETHTOOL_SRXFH:
2822                 ret = ixgbe_set_rss_hash_opt(adapter, cmd);
2823                 break;
2824         default:
2825                 break;
2826         }
2827
2828         return ret;
2829 }
2830
2831 static int ixgbe_get_ts_info(struct net_device *dev,
2832                              struct ethtool_ts_info *info)
2833 {
2834         struct ixgbe_adapter *adapter = netdev_priv(dev);
2835
2836         switch (adapter->hw.mac.type) {
2837         case ixgbe_mac_X540:
2838         case ixgbe_mac_82599EB:
2839                 info->so_timestamping =
2840                         SOF_TIMESTAMPING_TX_SOFTWARE |
2841                         SOF_TIMESTAMPING_RX_SOFTWARE |
2842                         SOF_TIMESTAMPING_SOFTWARE |
2843                         SOF_TIMESTAMPING_TX_HARDWARE |
2844                         SOF_TIMESTAMPING_RX_HARDWARE |
2845                         SOF_TIMESTAMPING_RAW_HARDWARE;
2846
2847                 if (adapter->ptp_clock)
2848                         info->phc_index = ptp_clock_index(adapter->ptp_clock);
2849                 else
2850                         info->phc_index = -1;
2851
2852                 info->tx_types =
2853                         (1 << HWTSTAMP_TX_OFF) |
2854                         (1 << HWTSTAMP_TX_ON);
2855
2856                 info->rx_filters =
2857                         (1 << HWTSTAMP_FILTER_NONE) |
2858                         (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
2859                         (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
2860                         (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
2861                         (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
2862                         (1 << HWTSTAMP_FILTER_PTP_V2_SYNC) |
2863                         (1 << HWTSTAMP_FILTER_PTP_V2_L2_SYNC) |
2864                         (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) |
2865                         (1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ) |
2866                         (1 << HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) |
2867                         (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) |
2868                         (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
2869                 break;
2870         default:
2871                 return ethtool_op_get_ts_info(dev, info);
2872                 break;
2873         }
2874         return 0;
2875 }
2876
2877 static unsigned int ixgbe_max_channels(struct ixgbe_adapter *adapter)
2878 {
2879         unsigned int max_combined;
2880         u8 tcs = netdev_get_num_tc(adapter->netdev);
2881
2882         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2883                 /* We only support one q_vector without MSI-X */
2884                 max_combined = 1;
2885         } else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2886                 /* SR-IOV currently only allows one queue on the PF */
2887                 max_combined = 1;
2888         } else if (tcs > 1) {
2889                 /* For DCB report channels per traffic class */
2890                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2891                         /* 8 TC w/ 4 queues per TC */
2892                         max_combined = 4;
2893                 } else if (tcs > 4) {
2894                         /* 8 TC w/ 8 queues per TC */
2895                         max_combined = 8;
2896                 } else {
2897                         /* 4 TC w/ 16 queues per TC */
2898                         max_combined = 16;
2899                 }
2900         } else if (adapter->atr_sample_rate) {
2901                 /* support up to 64 queues with ATR */
2902                 max_combined = IXGBE_MAX_FDIR_INDICES;
2903         } else {
2904                 /* support up to 16 queues with RSS */
2905                 max_combined = IXGBE_MAX_RSS_INDICES;
2906         }
2907
2908         return max_combined;
2909 }
2910
2911 static void ixgbe_get_channels(struct net_device *dev,
2912                                struct ethtool_channels *ch)
2913 {
2914         struct ixgbe_adapter *adapter = netdev_priv(dev);
2915
2916         /* report maximum channels */
2917         ch->max_combined = ixgbe_max_channels(adapter);
2918
2919         /* report info for other vector */
2920         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2921                 ch->max_other = NON_Q_VECTORS;
2922                 ch->other_count = NON_Q_VECTORS;
2923         }
2924
2925         /* record RSS queues */
2926         ch->combined_count = adapter->ring_feature[RING_F_RSS].indices;
2927
2928         /* nothing else to report if RSS is disabled */
2929         if (ch->combined_count == 1)
2930                 return;
2931
2932         /* we do not support ATR queueing if SR-IOV is enabled */
2933         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
2934                 return;
2935
2936         /* same thing goes for being DCB enabled */
2937         if (netdev_get_num_tc(dev) > 1)
2938                 return;
2939
2940         /* if ATR is disabled we can exit */
2941         if (!adapter->atr_sample_rate)
2942                 return;
2943
2944         /* report flow director queues as maximum channels */
2945         ch->combined_count = adapter->ring_feature[RING_F_FDIR].indices;
2946 }
2947
2948 static int ixgbe_set_channels(struct net_device *dev,
2949                               struct ethtool_channels *ch)
2950 {
2951         struct ixgbe_adapter *adapter = netdev_priv(dev);
2952         unsigned int count = ch->combined_count;
2953
2954         /* verify they are not requesting separate vectors */
2955         if (!count || ch->rx_count || ch->tx_count)
2956                 return -EINVAL;
2957
2958         /* verify other_count has not changed */
2959         if (ch->other_count != NON_Q_VECTORS)
2960                 return -EINVAL;
2961
2962         /* verify the number of channels does not exceed hardware limits */
2963         if (count > ixgbe_max_channels(adapter))
2964                 return -EINVAL;
2965
2966         /* update feature limits from largest to smallest supported values */
2967         adapter->ring_feature[RING_F_FDIR].limit = count;
2968
2969         /* cap RSS limit at 16 */
2970         if (count > IXGBE_MAX_RSS_INDICES)
2971                 count = IXGBE_MAX_RSS_INDICES;
2972         adapter->ring_feature[RING_F_RSS].limit = count;
2973
2974 #ifdef IXGBE_FCOE
2975         /* cap FCoE limit at 8 */
2976         if (count > IXGBE_FCRETA_SIZE)
2977                 count = IXGBE_FCRETA_SIZE;
2978         adapter->ring_feature[RING_F_FCOE].limit = count;
2979
2980 #endif
2981         /* use setup TC to update any traffic class queue mapping */
2982         return ixgbe_setup_tc(dev, netdev_get_num_tc(dev));
2983 }
2984
2985 static int ixgbe_get_module_info(struct net_device *dev,
2986                                        struct ethtool_modinfo *modinfo)
2987 {
2988         struct ixgbe_adapter *adapter = netdev_priv(dev);
2989         struct ixgbe_hw *hw = &adapter->hw;
2990         u32 status;
2991         u8 sff8472_rev, addr_mode;
2992         bool page_swap = false;
2993
2994         /* Check whether we support SFF-8472 or not */
2995         status = hw->phy.ops.read_i2c_eeprom(hw,
2996                                              IXGBE_SFF_SFF_8472_COMP,
2997                                              &sff8472_rev);
2998         if (status != 0)
2999                 return -EIO;
3000
3001         /* addressing mode is not supported */
3002         status = hw->phy.ops.read_i2c_eeprom(hw,
3003                                              IXGBE_SFF_SFF_8472_SWAP,
3004                                              &addr_mode);
3005         if (status != 0)
3006                 return -EIO;
3007
3008         if (addr_mode & IXGBE_SFF_ADDRESSING_MODE) {
3009                 e_err(drv, "Address change required to access page 0xA2, but not supported. Please report the module type to the driver maintainers.\n");
3010                 page_swap = true;
3011         }
3012
3013         if (sff8472_rev == IXGBE_SFF_SFF_8472_UNSUP || page_swap) {
3014                 /* We have a SFP, but it does not support SFF-8472 */
3015                 modinfo->type = ETH_MODULE_SFF_8079;
3016                 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
3017         } else {
3018                 /* We have a SFP which supports a revision of SFF-8472. */
3019                 modinfo->type = ETH_MODULE_SFF_8472;
3020                 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
3021         }
3022
3023         return 0;
3024 }
3025
3026 static int ixgbe_get_module_eeprom(struct net_device *dev,
3027                                          struct ethtool_eeprom *ee,
3028                                          u8 *data)
3029 {
3030         struct ixgbe_adapter *adapter = netdev_priv(dev);
3031         struct ixgbe_hw *hw = &adapter->hw;
3032         u32 status = IXGBE_ERR_PHY_ADDR_INVALID;
3033         u8 databyte = 0xFF;
3034         int i = 0;
3035
3036         if (ee->len == 0)
3037                 return -EINVAL;
3038
3039         for (i = ee->offset; i < ee->offset + ee->len; i++) {
3040                 /* I2C reads can take long time */
3041                 if (test_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
3042                         return -EBUSY;
3043
3044                 if (i < ETH_MODULE_SFF_8079_LEN)
3045                         status = hw->phy.ops.read_i2c_eeprom(hw, i, &databyte);
3046                 else
3047                         status = hw->phy.ops.read_i2c_sff8472(hw, i, &databyte);
3048
3049                 if (status != 0)
3050                         return -EIO;
3051
3052                 data[i - ee->offset] = databyte;
3053         }
3054
3055         return 0;
3056 }
3057
3058 static const struct ethtool_ops ixgbe_ethtool_ops = {
3059         .get_settings           = ixgbe_get_settings,
3060         .set_settings           = ixgbe_set_settings,
3061         .get_drvinfo            = ixgbe_get_drvinfo,
3062         .get_regs_len           = ixgbe_get_regs_len,
3063         .get_regs               = ixgbe_get_regs,
3064         .get_wol                = ixgbe_get_wol,
3065         .set_wol                = ixgbe_set_wol,
3066         .nway_reset             = ixgbe_nway_reset,
3067         .get_link               = ethtool_op_get_link,
3068         .get_eeprom_len         = ixgbe_get_eeprom_len,
3069         .get_eeprom             = ixgbe_get_eeprom,
3070         .set_eeprom             = ixgbe_set_eeprom,
3071         .get_ringparam          = ixgbe_get_ringparam,
3072         .set_ringparam          = ixgbe_set_ringparam,
3073         .get_pauseparam         = ixgbe_get_pauseparam,
3074         .set_pauseparam         = ixgbe_set_pauseparam,
3075         .get_msglevel           = ixgbe_get_msglevel,
3076         .set_msglevel           = ixgbe_set_msglevel,
3077         .self_test              = ixgbe_diag_test,
3078         .get_strings            = ixgbe_get_strings,
3079         .set_phys_id            = ixgbe_set_phys_id,
3080         .get_sset_count         = ixgbe_get_sset_count,
3081         .get_ethtool_stats      = ixgbe_get_ethtool_stats,
3082         .get_coalesce           = ixgbe_get_coalesce,
3083         .set_coalesce           = ixgbe_set_coalesce,
3084         .get_rxnfc              = ixgbe_get_rxnfc,
3085         .set_rxnfc              = ixgbe_set_rxnfc,
3086         .get_channels           = ixgbe_get_channels,
3087         .set_channels           = ixgbe_set_channels,
3088         .get_ts_info            = ixgbe_get_ts_info,
3089         .get_module_info        = ixgbe_get_module_info,
3090         .get_module_eeprom      = ixgbe_get_module_eeprom,
3091 };
3092
3093 void ixgbe_set_ethtool_ops(struct net_device *netdev)
3094 {
3095         netdev->ethtool_ops = &ixgbe_ethtool_ops;
3096 }