drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2014 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 #include <linux/pci.h>
  30 #include <linux/delay.h>
  31 #include <linux/sched.h>
  32
  33 #include "ixgbe.h"
  34 #include "ixgbe_phy.h"
  35
  36 static void ixgbe_i2c_start(struct ixgbe_hw *hw);
  37 static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
  38 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
  39 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
  40 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
  41 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
  42 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
  43 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  44 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  45 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
  46 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
  47 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
  48 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
  49 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
  50 static s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw);
  51
  52 /**
  53  *  ixgbe_identify_phy_generic - Get physical layer module
  54  *  @hw: pointer to hardware structure
  55  *
  56  *  Determines the physical layer module found on the current adapter.
  57  **/
  58 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
  59 {
  60         u32 phy_addr;
  61         u16 ext_ability = 0;
  62
  63         if (!hw->phy.phy_semaphore_mask) {
  64                 hw->phy.lan_id = IXGBE_READ_REG(hw, IXGBE_STATUS) &
  65                                  IXGBE_STATUS_LAN_ID_1;
  66                 if (hw->phy.lan_id)
  67                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
  68                 else
  69                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
  70         }
  71
  72         if (hw->phy.type == ixgbe_phy_unknown) {
  73                 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
  74                         hw->phy.mdio.prtad = phy_addr;
  75                         if (mdio45_probe(&hw->phy.mdio, phy_addr) == 0) {
  76                                 ixgbe_get_phy_id(hw);
  77                                 hw->phy.type =
  78                                         ixgbe_get_phy_type_from_id(hw->phy.id);
  79
  80                                 if (hw->phy.type == ixgbe_phy_unknown) {
  81                                         hw->phy.ops.read_reg(hw,
  82                                                              MDIO_PMA_EXTABLE,
  83                                                              MDIO_MMD_PMAPMD,
  84                                                              &ext_ability);
  85                                         if (ext_ability &
  86                                             (MDIO_PMA_EXTABLE_10GBT |
  87                                              MDIO_PMA_EXTABLE_1000BT))
  88                                                 hw->phy.type =
  89                                                          ixgbe_phy_cu_unknown;
  90                                         else
  91                                                 hw->phy.type =
  92                                                          ixgbe_phy_generic;
  93                                 }
  94
  95                                 return 0;
  96                         }
  97                 }
  98                 /* clear value if nothing found */
  99                 hw->phy.mdio.prtad = 0;
 100                 return IXGBE_ERR_PHY_ADDR_INVALID;
 101         }
 102         return 0;
 103 }
 104
 105 /**
 106  * ixgbe_check_reset_blocked - check status of MNG FW veto bit
 107  * @hw: pointer to the hardware structure
 108  *
 109  * This function checks the MMNGC.MNG_VETO bit to see if there are
 110  * any constraints on link from manageability.  For MAC's that don't
 111  * have this bit just return false since the link can not be blocked
 112  * via this method.
 113  **/
 114 bool ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
 115 {
 116         u32 mmngc;
 117
 118         /* If we don't have this bit, it can't be blocking */
 119         if (hw->mac.type == ixgbe_mac_82598EB)
 120                 return false;
 121
 122         mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
 123         if (mmngc & IXGBE_MMNGC_MNG_VETO) {
 124                 hw_dbg(hw, "MNG_VETO bit detected.\n");
 125                 return true;
 126         }
 127
 128         return false;
 129 }
 130
 131 /**
 132  *  ixgbe_get_phy_id - Get the phy type
 133  *  @hw: pointer to hardware structure
 134  *
 135  **/
 136 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
 137 {
 138         u32 status;
 139         u16 phy_id_high = 0;
 140         u16 phy_id_low = 0;
 141
 142         status = hw->phy.ops.read_reg(hw, MDIO_DEVID1, MDIO_MMD_PMAPMD,
 143                                       &phy_id_high);
 144
 145         if (status == 0) {
 146                 hw->phy.id = (u32)(phy_id_high << 16);
 147                 status = hw->phy.ops.read_reg(hw, MDIO_DEVID2, MDIO_MMD_PMAPMD,
 148                                               &phy_id_low);
 149                 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
 150                 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
 151         }
 152         return status;
 153 }
 154
 155 /**
 156  *  ixgbe_get_phy_type_from_id - Get the phy type
 157  *  @hw: pointer to hardware structure
 158  *
 159  **/
 160 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
 161 {
 162         enum ixgbe_phy_type phy_type;
 163
 164         switch (phy_id) {
 165         case TN1010_PHY_ID:
 166                 phy_type = ixgbe_phy_tn;
 167                 break;
 168         case X540_PHY_ID:
 169                 phy_type = ixgbe_phy_aq;
 170                 break;
 171         case QT2022_PHY_ID:
 172                 phy_type = ixgbe_phy_qt;
 173                 break;
 174         case ATH_PHY_ID:
 175                 phy_type = ixgbe_phy_nl;
 176                 break;
 177         default:
 178                 phy_type = ixgbe_phy_unknown;
 179                 break;
 180         }
 181
 182         return phy_type;
 183 }
 184
 185 /**
 186  *  ixgbe_reset_phy_generic - Performs a PHY reset
 187  *  @hw: pointer to hardware structure
 188  **/
 189 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
 190 {
 191         u32 i;
 192         u16 ctrl = 0;
 193         s32 status = 0;
 194
 195         if (hw->phy.type == ixgbe_phy_unknown)
 196                 status = ixgbe_identify_phy_generic(hw);
 197
 198         if (status != 0 || hw->phy.type == ixgbe_phy_none)
 199                 return status;
 200
 201         /* Don't reset PHY if it's shut down due to overtemp. */
 202         if (!hw->phy.reset_if_overtemp &&
 203             (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
 204                 return 0;
 205
 206         /* Blocked by MNG FW so bail */
 207         if (ixgbe_check_reset_blocked(hw))
 208                 return 0;
 209
 210         /*
 211          * Perform soft PHY reset to the PHY_XS.
 212          * This will cause a soft reset to the PHY
 213          */
 214         hw->phy.ops.write_reg(hw, MDIO_CTRL1,
 215                               MDIO_MMD_PHYXS,
 216                               MDIO_CTRL1_RESET);
 217
 218         /*
 219          * Poll for reset bit to self-clear indicating reset is complete.
 220          * Some PHYs could take up to 3 seconds to complete and need about
 221          * 1.7 usec delay after the reset is complete.
 222          */
 223         for (i = 0; i < 30; i++) {
 224                 msleep(100);
 225                 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
 226                                      MDIO_MMD_PHYXS, &ctrl);
 227                 if (!(ctrl & MDIO_CTRL1_RESET)) {
 228                         udelay(2);
 229                         break;
 230                 }
 231         }
 232
 233         if (ctrl & MDIO_CTRL1_RESET) {
 234                 hw_dbg(hw, "PHY reset polling failed to complete.\n");
 235                 return IXGBE_ERR_RESET_FAILED;
 236         }
 237
 238         return 0;
 239 }
 240
 241 /**
 242  *  ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
 243  *  the SWFW lock
 244  *  @hw: pointer to hardware structure
 245  *  @reg_addr: 32 bit address of PHY register to read
 246  *  @phy_data: Pointer to read data from PHY register
 247  **/
 248 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
 249                        u16 *phy_data)
 250 {
 251         u32 i, data, command;
 252
 253         /* Setup and write the address cycle command */
 254         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 255                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 256                    (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 257                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 258
 259         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 260
 261         /* Check every 10 usec to see if the address cycle completed.
 262          * The MDI Command bit will clear when the operation is
 263          * complete
 264          */
 265         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 266                 udelay(10);
 267
 268                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 269                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 270                                 break;
 271         }
 272
 273
 274         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 275                 hw_dbg(hw, "PHY address command did not complete.\n");
 276                 return IXGBE_ERR_PHY;
 277         }
 278
 279         /* Address cycle complete, setup and write the read
 280          * command
 281          */
 282         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 283                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 284                    (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 285                    (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
 286
 287         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 288
 289         /* Check every 10 usec to see if the address cycle
 290          * completed. The MDI Command bit will clear when the
 291          * operation is complete
 292          */
 293         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 294                 udelay(10);
 295
 296                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 297                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 298                         break;
 299         }
 300
 301         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 302                 hw_dbg(hw, "PHY read command didn't complete\n");
 303                 return IXGBE_ERR_PHY;
 304         }
 305
 306         /* Read operation is complete.  Get the data
 307          * from MSRWD
 308          */
 309         data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 310         data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 311         *phy_data = (u16)(data);
 312
 313         return 0;
 314 }
 315
 316 /**
 317  *  ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
 318  *  using the SWFW lock - this function is needed in most cases
 319  *  @hw: pointer to hardware structure
 320  *  @reg_addr: 32 bit address of PHY register to read
 321  *  @phy_data: Pointer to read data from PHY register
 322  **/
 323 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 324                                u32 device_type, u16 *phy_data)
 325 {
 326         s32 status;
 327         u32 gssr = hw->phy.phy_semaphore_mask;
 328
 329         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) {
 330                 status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type,
 331                                                 phy_data);
 332                 hw->mac.ops.release_swfw_sync(hw, gssr);
 333         } else {
 334                 return IXGBE_ERR_SWFW_SYNC;
 335         }
 336
 337         return status;
 338 }
 339
 340 /**
 341  *  ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
 342  *  without SWFW lock
 343  *  @hw: pointer to hardware structure
 344  *  @reg_addr: 32 bit PHY register to write
 345  *  @device_type: 5 bit device type
 346  *  @phy_data: Data to write to the PHY register
 347  **/
 348 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
 349                                 u32 device_type, u16 phy_data)
 350 {
 351         u32 i, command;
 352
 353         /* Put the data in the MDI single read and write data register*/
 354         IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 355
 356         /* Setup and write the address cycle command */
 357         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 358                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 359                    (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 360                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 361
 362         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 363
 364         /*
 365          * Check every 10 usec to see if the address cycle completed.
 366          * The MDI Command bit will clear when the operation is
 367          * complete
 368          */
 369         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 370                 udelay(10);
 371
 372                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 373                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 374                         break;
 375         }
 376
 377         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 378                 hw_dbg(hw, "PHY address cmd didn't complete\n");
 379                 return IXGBE_ERR_PHY;
 380         }
 381
 382         /*
 383          * Address cycle complete, setup and write the write
 384          * command
 385          */
 386         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 387                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 388                    (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 389                    (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
 390
 391         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 392
 393         /* Check every 10 usec to see if the address cycle
 394          * completed. The MDI Command bit will clear when the
 395          * operation is complete
 396          */
 397         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 398                 udelay(10);
 399
 400                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 401                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 402                         break;
 403         }
 404
 405         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 406                 hw_dbg(hw, "PHY write cmd didn't complete\n");
 407                 return IXGBE_ERR_PHY;
 408         }
 409
 410         return 0;
 411 }
 412
 413 /**
 414  *  ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
 415  *  using SWFW lock- this function is needed in most cases
 416  *  @hw: pointer to hardware structure
 417  *  @reg_addr: 32 bit PHY register to write
 418  *  @device_type: 5 bit device type
 419  *  @phy_data: Data to write to the PHY register
 420  **/
 421 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 422                                 u32 device_type, u16 phy_data)
 423 {
 424         s32 status;
 425         u32 gssr;
 426
 427         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
 428                 gssr = IXGBE_GSSR_PHY1_SM;
 429         else
 430                 gssr = IXGBE_GSSR_PHY0_SM;
 431
 432         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) {
 433                 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
 434                                                  phy_data);
 435                 hw->mac.ops.release_swfw_sync(hw, gssr);
 436         } else {
 437                 return IXGBE_ERR_SWFW_SYNC;
 438         }
 439
 440         return status;
 441 }
 442
 443 /**
 444  *  ixgbe_setup_phy_link_generic - Set and restart autoneg
 445  *  @hw: pointer to hardware structure
 446  *
 447  *  Restart autonegotiation and PHY and waits for completion.
 448  **/
 449 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
 450 {
 451         s32 status = 0;
 452         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 453         bool autoneg = false;
 454         ixgbe_link_speed speed;
 455
 456         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
 457
 458         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
 459                 /* Set or unset auto-negotiation 10G advertisement */
 460                 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
 461                                      MDIO_MMD_AN,
 462                                      &autoneg_reg);
 463
 464                 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
 465                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
 466                         autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
 467
 468                 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL,
 469                                       MDIO_MMD_AN,
 470                                       autoneg_reg);
 471         }
 472
 473         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
 474                 /* Set or unset auto-negotiation 1G advertisement */
 475                 hw->phy.ops.read_reg(hw,
 476                                      IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 477                                      MDIO_MMD_AN,
 478                                      &autoneg_reg);
 479
 480                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
 481                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
 482                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
 483
 484                 hw->phy.ops.write_reg(hw,
 485                                       IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 486                                       MDIO_MMD_AN,
 487                                       autoneg_reg);
 488         }
 489
 490         if (speed & IXGBE_LINK_SPEED_100_FULL) {
 491                 /* Set or unset auto-negotiation 100M advertisement */
 492                 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
 493                                      MDIO_MMD_AN,
 494                                      &autoneg_reg);
 495
 496                 autoneg_reg &= ~(ADVERTISE_100FULL |
 497                                  ADVERTISE_100HALF);
 498                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
 499                         autoneg_reg |= ADVERTISE_100FULL;
 500
 501                 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
 502                                       MDIO_MMD_AN,
 503                                       autoneg_reg);
 504         }
 505
 506         /* Blocked by MNG FW so don't reset PHY */
 507         if (ixgbe_check_reset_blocked(hw))
 508                 return 0;
 509
 510         /* Restart PHY autonegotiation and wait for completion */
 511         hw->phy.ops.read_reg(hw, MDIO_CTRL1,
 512                              MDIO_MMD_AN, &autoneg_reg);
 513
 514         autoneg_reg |= MDIO_AN_CTRL1_RESTART;
 515
 516         hw->phy.ops.write_reg(hw, MDIO_CTRL1,
 517                               MDIO_MMD_AN, autoneg_reg);
 518
 519         return status;
 520 }
 521
 522 /**
 523  *  ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
 524  *  @hw: pointer to hardware structure
 525  *  @speed: new link speed
 526  **/
 527 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
 528                                        ixgbe_link_speed speed,
 529                                        bool autoneg_wait_to_complete)
 530 {
 531
 532         /*
 533          * Clear autoneg_advertised and set new values based on input link
 534          * speed.
 535          */
 536         hw->phy.autoneg_advertised = 0;
 537
 538         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
 539                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
 540
 541         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 542                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
 543
 544         if (speed & IXGBE_LINK_SPEED_100_FULL)
 545                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
 546
 547         /* Setup link based on the new speed settings */
 548         hw->phy.ops.setup_link(hw);
 549
 550         return 0;
 551 }
 552
 553 /**
 554  * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
 555  * @hw: pointer to hardware structure
 556  * @speed: pointer to link speed
 557  * @autoneg: boolean auto-negotiation value
 558  *
 559  * Determines the link capabilities by reading the AUTOC register.
 560  */
 561 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
 562                                                ixgbe_link_speed *speed,
 563                                                bool *autoneg)
 564 {
 565         s32 status;
 566         u16 speed_ability;
 567
 568         *speed = 0;
 569         *autoneg = true;
 570
 571         status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
 572                                       &speed_ability);
 573
 574         if (status == 0) {
 575                 if (speed_ability & MDIO_SPEED_10G)
 576                         *speed |= IXGBE_LINK_SPEED_10GB_FULL;
 577                 if (speed_ability & MDIO_PMA_SPEED_1000)
 578                         *speed |= IXGBE_LINK_SPEED_1GB_FULL;
 579                 if (speed_ability & MDIO_PMA_SPEED_100)
 580                         *speed |= IXGBE_LINK_SPEED_100_FULL;
 581         }
 582
 583         /* Internal PHY does not support 100 Mbps */
 584         if (hw->mac.type == ixgbe_mac_X550EM_x)
 585                 *speed &= ~IXGBE_LINK_SPEED_100_FULL;
 586
 587         return status;
 588 }
 589
 590 /**
 591  *  ixgbe_check_phy_link_tnx - Determine link and speed status
 592  *  @hw: pointer to hardware structure
 593  *
 594  *  Reads the VS1 register to determine if link is up and the current speed for
 595  *  the PHY.
 596  **/
 597 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
 598                              bool *link_up)
 599 {
 600         s32 status;
 601         u32 time_out;
 602         u32 max_time_out = 10;
 603         u16 phy_link = 0;
 604         u16 phy_speed = 0;
 605         u16 phy_data = 0;
 606
 607         /* Initialize speed and link to default case */
 608         *link_up = false;
 609         *speed = IXGBE_LINK_SPEED_10GB_FULL;
 610
 611         /*
 612          * Check current speed and link status of the PHY register.
 613          * This is a vendor specific register and may have to
 614          * be changed for other copper PHYs.
 615          */
 616         for (time_out = 0; time_out < max_time_out; time_out++) {
 617                 udelay(10);
 618                 status = hw->phy.ops.read_reg(hw,
 619                                               MDIO_STAT1,
 620                                               MDIO_MMD_VEND1,
 621                                               &phy_data);
 622                 phy_link = phy_data &
 623                             IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
 624                 phy_speed = phy_data &
 625                             IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
 626                 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
 627                         *link_up = true;
 628                         if (phy_speed ==
 629                             IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
 630                                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
 631                         break;
 632                 }
 633         }
 634
 635         return status;
 636 }
 637
 638 /**
 639  *      ixgbe_setup_phy_link_tnx - Set and restart autoneg
 640  *      @hw: pointer to hardware structure
 641  *
 642  *      Restart autonegotiation and PHY and waits for completion.
 643  *      This function always returns success, this is nessary since
 644  *      it is called via a function pointer that could call other
 645  *      functions that could return an error.
 646  **/
 647 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
 648 {
 649         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 650         bool autoneg = false;
 651         ixgbe_link_speed speed;
 652
 653         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
 654
 655         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
 656                 /* Set or unset auto-negotiation 10G advertisement */
 657                 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
 658                                      MDIO_MMD_AN,
 659                                      &autoneg_reg);
 660
 661                 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
 662                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
 663                         autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
 664
 665                 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL,
 666                                       MDIO_MMD_AN,
 667                                       autoneg_reg);
 668         }
 669
 670         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
 671                 /* Set or unset auto-negotiation 1G advertisement */
 672                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
 673                                      MDIO_MMD_AN,
 674                                      &autoneg_reg);
 675
 676                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
 677                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
 678                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
 679
 680                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
 681                                       MDIO_MMD_AN,
 682                                       autoneg_reg);
 683         }
 684
 685         if (speed & IXGBE_LINK_SPEED_100_FULL) {
 686                 /* Set or unset auto-negotiation 100M advertisement */
 687                 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
 688                                      MDIO_MMD_AN,
 689                                      &autoneg_reg);
 690
 691                 autoneg_reg &= ~(ADVERTISE_100FULL |
 692                                  ADVERTISE_100HALF);
 693                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
 694                         autoneg_reg |= ADVERTISE_100FULL;
 695
 696                 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
 697                                       MDIO_MMD_AN,
 698                                       autoneg_reg);
 699         }
 700
 701         /* Blocked by MNG FW so don't reset PHY */
 702         if (ixgbe_check_reset_blocked(hw))
 703                 return 0;
 704
 705         /* Restart PHY autonegotiation and wait for completion */
 706         hw->phy.ops.read_reg(hw, MDIO_CTRL1,
 707                              MDIO_MMD_AN, &autoneg_reg);
 708
 709         autoneg_reg |= MDIO_AN_CTRL1_RESTART;
 710
 711         hw->phy.ops.write_reg(hw, MDIO_CTRL1,
 712                               MDIO_MMD_AN, autoneg_reg);
 713         return 0;
 714 }
 715
 716 /**
 717  *  ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
 718  *  @hw: pointer to hardware structure
 719  *  @firmware_version: pointer to the PHY Firmware Version
 720  **/
 721 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
 722                                        u16 *firmware_version)
 723 {
 724         s32 status;
 725
 726         status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
 727                                       MDIO_MMD_VEND1,
 728                                       firmware_version);
 729
 730         return status;
 731 }
 732
 733 /**
 734  *  ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
 735  *  @hw: pointer to hardware structure
 736  *  @firmware_version: pointer to the PHY Firmware Version
 737  **/
 738 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
 739                                            u16 *firmware_version)
 740 {
 741         s32 status;
 742
 743         status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
 744                                       MDIO_MMD_VEND1,
 745                                       firmware_version);
 746
 747         return status;
 748 }
 749
 750 /**
 751  *  ixgbe_reset_phy_nl - Performs a PHY reset
 752  *  @hw: pointer to hardware structure
 753  **/
 754 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
 755 {
 756         u16 phy_offset, control, eword, edata, block_crc;
 757         bool end_data = false;
 758         u16 list_offset, data_offset;
 759         u16 phy_data = 0;
 760         s32 ret_val;
 761         u32 i;
 762
 763         /* Blocked by MNG FW so bail */
 764         if (ixgbe_check_reset_blocked(hw))
 765                 return 0;
 766
 767         hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, &phy_data);
 768
 769         /* reset the PHY and poll for completion */
 770         hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
 771                               (phy_data | MDIO_CTRL1_RESET));
 772
 773         for (i = 0; i < 100; i++) {
 774                 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
 775                                      &phy_data);
 776                 if ((phy_data & MDIO_CTRL1_RESET) == 0)
 777                         break;
 778                 usleep_range(10000, 20000);
 779         }
 780
 781         if ((phy_data & MDIO_CTRL1_RESET) != 0) {
 782                 hw_dbg(hw, "PHY reset did not complete.\n");
 783                 return IXGBE_ERR_PHY;
 784         }
 785
 786         /* Get init offsets */
 787         ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
 788                                                       &data_offset);
 789         if (ret_val)
 790                 return ret_val;
 791
 792         ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
 793         data_offset++;
 794         while (!end_data) {
 795                 /*
 796                  * Read control word from PHY init contents offset
 797                  */
 798                 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
 799                 if (ret_val)
 800                         goto err_eeprom;
 801                 control = (eword & IXGBE_CONTROL_MASK_NL) >>
 802                            IXGBE_CONTROL_SHIFT_NL;
 803                 edata = eword & IXGBE_DATA_MASK_NL;
 804                 switch (control) {
 805                 case IXGBE_DELAY_NL:
 806                         data_offset++;
 807                         hw_dbg(hw, "DELAY: %d MS\n", edata);
 808                         usleep_range(edata * 1000, edata * 2000);
 809                         break;
 810                 case IXGBE_DATA_NL:
 811                         hw_dbg(hw, "DATA:\n");
 812                         data_offset++;
 813                         ret_val = hw->eeprom.ops.read(hw, data_offset++,
 814                                                       &phy_offset);
 815                         if (ret_val)
 816                                 goto err_eeprom;
 817                         for (i = 0; i < edata; i++) {
 818                                 ret_val = hw->eeprom.ops.read(hw, data_offset,
 819                                                               &eword);
 820                                 if (ret_val)
 821                                         goto err_eeprom;
 822                                 hw->phy.ops.write_reg(hw, phy_offset,
 823                                                       MDIO_MMD_PMAPMD, eword);
 824                                 hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword,
 825                                        phy_offset);
 826                                 data_offset++;
 827                                 phy_offset++;
 828                         }
 829                         break;
 830                 case IXGBE_CONTROL_NL:
 831                         data_offset++;
 832                         hw_dbg(hw, "CONTROL:\n");
 833                         if (edata == IXGBE_CONTROL_EOL_NL) {
 834                                 hw_dbg(hw, "EOL\n");
 835                                 end_data = true;
 836                         } else if (edata == IXGBE_CONTROL_SOL_NL) {
 837                                 hw_dbg(hw, "SOL\n");
 838                         } else {
 839                                 hw_dbg(hw, "Bad control value\n");
 840                                 return IXGBE_ERR_PHY;
 841                         }
 842                         break;
 843                 default:
 844                         hw_dbg(hw, "Bad control type\n");
 845                         return IXGBE_ERR_PHY;
 846                 }
 847         }
 848
 849         return ret_val;
 850
 851 err_eeprom:
 852         hw_err(hw, "eeprom read at offset %d failed\n", data_offset);
 853         return IXGBE_ERR_PHY;
 854 }
 855
 856 /**
 857  *  ixgbe_identify_module_generic - Identifies module type
 858  *  @hw: pointer to hardware structure
 859  *
 860  *  Determines HW type and calls appropriate function.
 861  **/
 862 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
 863 {
 864         switch (hw->mac.ops.get_media_type(hw)) {
 865         case ixgbe_media_type_fiber:
 866                 return ixgbe_identify_sfp_module_generic(hw);
 867         case ixgbe_media_type_fiber_qsfp:
 868                 return ixgbe_identify_qsfp_module_generic(hw);
 869         default:
 870                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
 871                 return IXGBE_ERR_SFP_NOT_PRESENT;
 872         }
 873
 874         return IXGBE_ERR_SFP_NOT_PRESENT;
 875 }
 876
 877 /**
 878  *  ixgbe_identify_sfp_module_generic - Identifies SFP modules
 879  *  @hw: pointer to hardware structure
 880  *
 881  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
 882  **/
 883 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
 884 {
 885         struct ixgbe_adapter *adapter = hw->back;
 886         s32 status;
 887         u32 vendor_oui = 0;
 888         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
 889         u8 identifier = 0;
 890         u8 comp_codes_1g = 0;
 891         u8 comp_codes_10g = 0;
 892         u8 oui_bytes[3] = {0, 0, 0};
 893         u8 cable_tech = 0;
 894         u8 cable_spec = 0;
 895         u16 enforce_sfp = 0;
 896
 897         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
 898                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
 899                 return IXGBE_ERR_SFP_NOT_PRESENT;
 900         }
 901
 902         status = hw->phy.ops.read_i2c_eeprom(hw,
 903                                              IXGBE_SFF_IDENTIFIER,
 904                                              &identifier);
 905
 906         if (status)
 907                 goto err_read_i2c_eeprom;
 908
 909         /* LAN ID is needed for sfp_type determination */
 910         hw->mac.ops.set_lan_id(hw);
 911
 912         if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
 913                 hw->phy.type = ixgbe_phy_sfp_unsupported;
 914                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
 915         }
 916         status = hw->phy.ops.read_i2c_eeprom(hw,
 917                                              IXGBE_SFF_1GBE_COMP_CODES,
 918                                              &comp_codes_1g);
 919
 920         if (status)
 921                 goto err_read_i2c_eeprom;
 922
 923         status = hw->phy.ops.read_i2c_eeprom(hw,
 924                                              IXGBE_SFF_10GBE_COMP_CODES,
 925                                              &comp_codes_10g);
 926
 927         if (status)
 928                 goto err_read_i2c_eeprom;
 929         status = hw->phy.ops.read_i2c_eeprom(hw,
 930                                              IXGBE_SFF_CABLE_TECHNOLOGY,
 931                                              &cable_tech);
 932
 933         if (status)
 934                 goto err_read_i2c_eeprom;
 935
 936          /* ID Module
 937           * =========
 938           * 0   SFP_DA_CU
 939           * 1   SFP_SR
 940           * 2   SFP_LR
 941           * 3   SFP_DA_CORE0 - 82599-specific
 942           * 4   SFP_DA_CORE1 - 82599-specific
 943           * 5   SFP_SR/LR_CORE0 - 82599-specific
 944           * 6   SFP_SR/LR_CORE1 - 82599-specific
 945           * 7   SFP_act_lmt_DA_CORE0 - 82599-specific
 946           * 8   SFP_act_lmt_DA_CORE1 - 82599-specific
 947           * 9   SFP_1g_cu_CORE0 - 82599-specific
 948           * 10  SFP_1g_cu_CORE1 - 82599-specific
 949           * 11  SFP_1g_sx_CORE0 - 82599-specific
 950           * 12  SFP_1g_sx_CORE1 - 82599-specific
 951           */
 952         if (hw->mac.type == ixgbe_mac_82598EB) {
 953                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
 954                         hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
 955                 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
 956                         hw->phy.sfp_type = ixgbe_sfp_type_sr;
 957                 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
 958                         hw->phy.sfp_type = ixgbe_sfp_type_lr;
 959                 else
 960                         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
 961         } else if (hw->mac.type == ixgbe_mac_82599EB) {
 962                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
 963                         if (hw->bus.lan_id == 0)
 964                                 hw->phy.sfp_type =
 965                                              ixgbe_sfp_type_da_cu_core0;
 966                         else
 967                                 hw->phy.sfp_type =
 968                                              ixgbe_sfp_type_da_cu_core1;
 969                 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
 970                         hw->phy.ops.read_i2c_eeprom(
 971                                         hw, IXGBE_SFF_CABLE_SPEC_COMP,
 972                                         &cable_spec);
 973                         if (cable_spec &
 974                             IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
 975                                 if (hw->bus.lan_id == 0)
 976                                         hw->phy.sfp_type =
 977                                         ixgbe_sfp_type_da_act_lmt_core0;
 978                                 else
 979                                         hw->phy.sfp_type =
 980                                         ixgbe_sfp_type_da_act_lmt_core1;
 981                         } else {
 982                                 hw->phy.sfp_type =
 983                                                 ixgbe_sfp_type_unknown;
 984                         }
 985                 } else if (comp_codes_10g &
 986                            (IXGBE_SFF_10GBASESR_CAPABLE |
 987                             IXGBE_SFF_10GBASELR_CAPABLE)) {
 988                         if (hw->bus.lan_id == 0)
 989                                 hw->phy.sfp_type =
 990                                               ixgbe_sfp_type_srlr_core0;
 991                         else
 992                                 hw->phy.sfp_type =
 993                                               ixgbe_sfp_type_srlr_core1;
 994                 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
 995                         if (hw->bus.lan_id == 0)
 996                                 hw->phy.sfp_type =
 997                                         ixgbe_sfp_type_1g_cu_core0;
 998                         else
 999                                 hw->phy.sfp_type =
1000                                         ixgbe_sfp_type_1g_cu_core1;
1001                 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1002                         if (hw->bus.lan_id == 0)
1003                                 hw->phy.sfp_type =
1004                                         ixgbe_sfp_type_1g_sx_core0;
1005                         else
1006                                 hw->phy.sfp_type =
1007                                         ixgbe_sfp_type_1g_sx_core1;
1008                 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1009                         if (hw->bus.lan_id == 0)
1010                                 hw->phy.sfp_type =
1011                                         ixgbe_sfp_type_1g_lx_core0;
1012                         else
1013                                 hw->phy.sfp_type =
1014                                         ixgbe_sfp_type_1g_lx_core1;
1015                 } else {
1016                         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1017                 }
1018         }
1019
1020         if (hw->phy.sfp_type != stored_sfp_type)
1021                 hw->phy.sfp_setup_needed = true;
1022
1023         /* Determine if the SFP+ PHY is dual speed or not. */
1024         hw->phy.multispeed_fiber = false;
1025         if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1026              (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1027             ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1028              (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1029                 hw->phy.multispeed_fiber = true;
1030
1031         /* Determine PHY vendor */
1032         if (hw->phy.type != ixgbe_phy_nl) {
1033                 hw->phy.id = identifier;
1034                 status = hw->phy.ops.read_i2c_eeprom(hw,
1035                                             IXGBE_SFF_VENDOR_OUI_BYTE0,
1036                                             &oui_bytes[0]);
1037
1038                 if (status != 0)
1039                         goto err_read_i2c_eeprom;
1040
1041                 status = hw->phy.ops.read_i2c_eeprom(hw,
1042                                             IXGBE_SFF_VENDOR_OUI_BYTE1,
1043                                             &oui_bytes[1]);
1044
1045                 if (status != 0)
1046                         goto err_read_i2c_eeprom;
1047
1048                 status = hw->phy.ops.read_i2c_eeprom(hw,
1049                                             IXGBE_SFF_VENDOR_OUI_BYTE2,
1050                                             &oui_bytes[2]);
1051
1052                 if (status != 0)
1053                         goto err_read_i2c_eeprom;
1054
1055                 vendor_oui =
1056                   ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1057                    (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1058                    (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1059
1060                 switch (vendor_oui) {
1061                 case IXGBE_SFF_VENDOR_OUI_TYCO:
1062                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1063                                 hw->phy.type =
1064                                             ixgbe_phy_sfp_passive_tyco;
1065                         break;
1066                 case IXGBE_SFF_VENDOR_OUI_FTL:
1067                         if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1068                                 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1069                         else
1070                                 hw->phy.type = ixgbe_phy_sfp_ftl;
1071                         break;
1072                 case IXGBE_SFF_VENDOR_OUI_AVAGO:
1073                         hw->phy.type = ixgbe_phy_sfp_avago;
1074                         break;
1075                 case IXGBE_SFF_VENDOR_OUI_INTEL:
1076                         hw->phy.type = ixgbe_phy_sfp_intel;
1077                         break;
1078                 default:
1079                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1080                                 hw->phy.type =
1081                                          ixgbe_phy_sfp_passive_unknown;
1082                         else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1083                                 hw->phy.type =
1084                                         ixgbe_phy_sfp_active_unknown;
1085                         else
1086                                 hw->phy.type = ixgbe_phy_sfp_unknown;
1087                         break;
1088                 }
1089         }
1090
1091         /* Allow any DA cable vendor */
1092         if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1093             IXGBE_SFF_DA_ACTIVE_CABLE))
1094                 return 0;
1095
1096         /* Verify supported 1G SFP modules */
1097         if (comp_codes_10g == 0 &&
1098             !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1099               hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1100               hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1101               hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1102               hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1103               hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1104                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1105                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1106         }
1107
1108         /* Anything else 82598-based is supported */
1109         if (hw->mac.type == ixgbe_mac_82598EB)
1110                 return 0;
1111
1112         hw->mac.ops.get_device_caps(hw, &enforce_sfp);
1113         if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1114             !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1115               hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1116               hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1117               hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1118               hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1119               hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1120                 /* Make sure we're a supported PHY type */
1121                 if (hw->phy.type == ixgbe_phy_sfp_intel)
1122                         return 0;
1123                 if (hw->allow_unsupported_sfp) {
1124                         e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics.  Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter.  Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1125                         return 0;
1126                 }
1127                 hw_dbg(hw, "SFP+ module not supported\n");
1128                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1129                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1130         }
1131         return 0;
1132
1133 err_read_i2c_eeprom:
1134         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1135         if (hw->phy.type != ixgbe_phy_nl) {
1136                 hw->phy.id = 0;
1137                 hw->phy.type = ixgbe_phy_unknown;
1138         }
1139         return IXGBE_ERR_SFP_NOT_PRESENT;
1140 }
1141
1142 /**
1143  * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1144  * @hw: pointer to hardware structure
1145  *
1146  * Searches for and identifies the QSFP module and assigns appropriate PHY type
1147  **/
1148 static s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1149 {
1150         struct ixgbe_adapter *adapter = hw->back;
1151         s32 status;
1152         u32 vendor_oui = 0;
1153         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1154         u8 identifier = 0;
1155         u8 comp_codes_1g = 0;
1156         u8 comp_codes_10g = 0;
1157         u8 oui_bytes[3] = {0, 0, 0};
1158         u16 enforce_sfp = 0;
1159         u8 connector = 0;
1160         u8 cable_length = 0;
1161         u8 device_tech = 0;
1162         bool active_cable = false;
1163
1164         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1165                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1166                 return IXGBE_ERR_SFP_NOT_PRESENT;
1167         }
1168
1169         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1170                                              &identifier);
1171
1172         if (status != 0)
1173                 goto err_read_i2c_eeprom;
1174
1175         if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1176                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1177                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1178         }
1179
1180         hw->phy.id = identifier;
1181
1182         /* LAN ID is needed for sfp_type determination */
1183         hw->mac.ops.set_lan_id(hw);
1184
1185         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1186                                              &comp_codes_10g);
1187
1188         if (status != 0)
1189                 goto err_read_i2c_eeprom;
1190
1191         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1192                                              &comp_codes_1g);
1193
1194         if (status != 0)
1195                 goto err_read_i2c_eeprom;
1196
1197         if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1198                 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1199                 if (hw->bus.lan_id == 0)
1200                         hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1201                 else
1202                         hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1203         } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1204                                      IXGBE_SFF_10GBASELR_CAPABLE)) {
1205                 if (hw->bus.lan_id == 0)
1206                         hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1207                 else
1208                         hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1209         } else {
1210                 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1211                         active_cable = true;
1212
1213                 if (!active_cable) {
1214                         /* check for active DA cables that pre-date
1215                          * SFF-8436 v3.6
1216                          */
1217                         hw->phy.ops.read_i2c_eeprom(hw,
1218                                         IXGBE_SFF_QSFP_CONNECTOR,
1219                                         &connector);
1220
1221                         hw->phy.ops.read_i2c_eeprom(hw,
1222                                         IXGBE_SFF_QSFP_CABLE_LENGTH,
1223                                         &cable_length);
1224
1225                         hw->phy.ops.read_i2c_eeprom(hw,
1226                                         IXGBE_SFF_QSFP_DEVICE_TECH,
1227                                         &device_tech);
1228
1229                         if ((connector ==
1230                                      IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1231                             (cable_length > 0) &&
1232                             ((device_tech >> 4) ==
1233                                      IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1234                                 active_cable = true;
1235                 }
1236
1237                 if (active_cable) {
1238                         hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1239                         if (hw->bus.lan_id == 0)
1240                                 hw->phy.sfp_type =
1241                                                 ixgbe_sfp_type_da_act_lmt_core0;
1242                         else
1243                                 hw->phy.sfp_type =
1244                                                 ixgbe_sfp_type_da_act_lmt_core1;
1245                 } else {
1246                         /* unsupported module type */
1247                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1248                         return IXGBE_ERR_SFP_NOT_SUPPORTED;
1249                 }
1250         }
1251
1252         if (hw->phy.sfp_type != stored_sfp_type)
1253                 hw->phy.sfp_setup_needed = true;
1254
1255         /* Determine if the QSFP+ PHY is dual speed or not. */
1256         hw->phy.multispeed_fiber = false;
1257         if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1258              (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1259             ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1260              (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1261                 hw->phy.multispeed_fiber = true;
1262
1263         /* Determine PHY vendor for optical modules */
1264         if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1265                               IXGBE_SFF_10GBASELR_CAPABLE)) {
1266                 status = hw->phy.ops.read_i2c_eeprom(hw,
1267                                         IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1268                                         &oui_bytes[0]);
1269
1270                 if (status != 0)
1271                         goto err_read_i2c_eeprom;
1272
1273                 status = hw->phy.ops.read_i2c_eeprom(hw,
1274                                         IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1275                                         &oui_bytes[1]);
1276
1277                 if (status != 0)
1278                         goto err_read_i2c_eeprom;
1279
1280                 status = hw->phy.ops.read_i2c_eeprom(hw,
1281                                         IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1282                                         &oui_bytes[2]);
1283
1284                 if (status != 0)
1285                         goto err_read_i2c_eeprom;
1286
1287                 vendor_oui =
1288                         ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1289                          (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1290                          (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1291
1292                 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1293                         hw->phy.type = ixgbe_phy_qsfp_intel;
1294                 else
1295                         hw->phy.type = ixgbe_phy_qsfp_unknown;
1296
1297                 hw->mac.ops.get_device_caps(hw, &enforce_sfp);
1298                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1299                         /* Make sure we're a supported PHY type */
1300                         if (hw->phy.type == ixgbe_phy_qsfp_intel)
1301                                 return 0;
1302                         if (hw->allow_unsupported_sfp) {
1303                                 e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1304                                 return 0;
1305                         }
1306                         hw_dbg(hw, "QSFP module not supported\n");
1307                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1308                         return IXGBE_ERR_SFP_NOT_SUPPORTED;
1309                 }
1310                 return 0;
1311         }
1312         return 0;
1313
1314 err_read_i2c_eeprom:
1315         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1316         hw->phy.id = 0;
1317         hw->phy.type = ixgbe_phy_unknown;
1318
1319         return IXGBE_ERR_SFP_NOT_PRESENT;
1320 }
1321
1322 /**
1323  *  ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1324  *  @hw: pointer to hardware structure
1325  *  @list_offset: offset to the SFP ID list
1326  *  @data_offset: offset to the SFP data block
1327  *
1328  *  Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1329  *  so it returns the offsets to the phy init sequence block.
1330  **/
1331 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1332                                         u16 *list_offset,
1333                                         u16 *data_offset)
1334 {
1335         u16 sfp_id;
1336         u16 sfp_type = hw->phy.sfp_type;
1337
1338         if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1339                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1340
1341         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1342                 return IXGBE_ERR_SFP_NOT_PRESENT;
1343
1344         if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1345             (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1346                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1347
1348         /*
1349          * Limiting active cables and 1G Phys must be initialized as
1350          * SR modules
1351          */
1352         if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1353             sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1354             sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1355             sfp_type == ixgbe_sfp_type_1g_sx_core0)
1356                 sfp_type = ixgbe_sfp_type_srlr_core0;
1357         else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1358                  sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1359                  sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1360                  sfp_type == ixgbe_sfp_type_1g_sx_core1)
1361                 sfp_type = ixgbe_sfp_type_srlr_core1;
1362
1363         /* Read offset to PHY init contents */
1364         if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1365                 hw_err(hw, "eeprom read at %d failed\n",
1366                        IXGBE_PHY_INIT_OFFSET_NL);
1367                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1368         }
1369
1370         if ((!*list_offset) || (*list_offset == 0xFFFF))
1371                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1372
1373         /* Shift offset to first ID word */
1374         (*list_offset)++;
1375
1376         /*
1377          * Find the matching SFP ID in the EEPROM
1378          * and program the init sequence
1379          */
1380         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1381                 goto err_phy;
1382
1383         while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1384                 if (sfp_id == sfp_type) {
1385                         (*list_offset)++;
1386                         if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1387                                 goto err_phy;
1388                         if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1389                                 hw_dbg(hw, "SFP+ module not supported\n");
1390                                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1391                         } else {
1392                                 break;
1393                         }
1394                 } else {
1395                         (*list_offset) += 2;
1396                         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1397                                 goto err_phy;
1398                 }
1399         }
1400
1401         if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1402                 hw_dbg(hw, "No matching SFP+ module found\n");
1403                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1404         }
1405
1406         return 0;
1407
1408 err_phy:
1409         hw_err(hw, "eeprom read at offset %d failed\n", *list_offset);
1410         return IXGBE_ERR_PHY;
1411 }
1412
1413 /**
1414  *  ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1415  *  @hw: pointer to hardware structure
1416  *  @byte_offset: EEPROM byte offset to read
1417  *  @eeprom_data: value read
1418  *
1419  *  Performs byte read operation to SFP module's EEPROM over I2C interface.
1420  **/
1421 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1422                                   u8 *eeprom_data)
1423 {
1424         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1425                                          IXGBE_I2C_EEPROM_DEV_ADDR,
1426                                          eeprom_data);
1427 }
1428
1429 /**
1430  *  ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1431  *  @hw: pointer to hardware structure
1432  *  @byte_offset: byte offset at address 0xA2
1433  *  @eeprom_data: value read
1434  *
1435  *  Performs byte read operation to SFP module's SFF-8472 data over I2C
1436  **/
1437 s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1438                                    u8 *sff8472_data)
1439 {
1440         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1441                                          IXGBE_I2C_EEPROM_DEV_ADDR2,
1442                                          sff8472_data);
1443 }
1444
1445 /**
1446  *  ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1447  *  @hw: pointer to hardware structure
1448  *  @byte_offset: EEPROM byte offset to write
1449  *  @eeprom_data: value to write
1450  *
1451  *  Performs byte write operation to SFP module's EEPROM over I2C interface.
1452  **/
1453 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1454                                    u8 eeprom_data)
1455 {
1456         return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1457                                           IXGBE_I2C_EEPROM_DEV_ADDR,
1458                                           eeprom_data);
1459 }
1460
1461 /**
1462  *  ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
1463  *  @hw: pointer to hardware structure
1464  *  @byte_offset: byte offset to read
1465  *  @data: value read
1466  *
1467  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
1468  *  a specified device address.
1469  **/
1470 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1471                                 u8 dev_addr, u8 *data)
1472 {
1473         s32 status;
1474         u32 max_retry = 10;
1475         u32 retry = 0;
1476         u32 swfw_mask = hw->phy.phy_semaphore_mask;
1477         bool nack = true;
1478         *data = 0;
1479
1480         do {
1481                 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
1482                         return IXGBE_ERR_SWFW_SYNC;
1483
1484                 ixgbe_i2c_start(hw);
1485
1486                 /* Device Address and write indication */
1487                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1488                 if (status != 0)
1489                         goto fail;
1490
1491                 status = ixgbe_get_i2c_ack(hw);
1492                 if (status != 0)
1493                         goto fail;
1494
1495                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1496                 if (status != 0)
1497                         goto fail;
1498
1499                 status = ixgbe_get_i2c_ack(hw);
1500                 if (status != 0)
1501                         goto fail;
1502
1503                 ixgbe_i2c_start(hw);
1504
1505                 /* Device Address and read indication */
1506                 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
1507                 if (status != 0)
1508                         goto fail;
1509
1510                 status = ixgbe_get_i2c_ack(hw);
1511                 if (status != 0)
1512                         goto fail;
1513
1514                 status = ixgbe_clock_in_i2c_byte(hw, data);
1515                 if (status != 0)
1516                         goto fail;
1517
1518                 status = ixgbe_clock_out_i2c_bit(hw, nack);
1519                 if (status != 0)
1520                         goto fail;
1521
1522                 ixgbe_i2c_stop(hw);
1523                 break;
1524
1525 fail:
1526                 ixgbe_i2c_bus_clear(hw);
1527                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1528                 msleep(100);
1529                 retry++;
1530                 if (retry < max_retry)
1531                         hw_dbg(hw, "I2C byte read error - Retrying.\n");
1532                 else
1533                         hw_dbg(hw, "I2C byte read error.\n");
1534
1535         } while (retry < max_retry);
1536
1537         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1538
1539         return status;
1540 }
1541
1542 /**
1543  *  ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
1544  *  @hw: pointer to hardware structure
1545  *  @byte_offset: byte offset to write
1546  *  @data: value to write
1547  *
1548  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
1549  *  a specified device address.
1550  **/
1551 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1552                                  u8 dev_addr, u8 data)
1553 {
1554         s32 status;
1555         u32 max_retry = 1;
1556         u32 retry = 0;
1557         u32 swfw_mask = hw->phy.phy_semaphore_mask;
1558
1559         if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
1560                 return IXGBE_ERR_SWFW_SYNC;
1561
1562         do {
1563                 ixgbe_i2c_start(hw);
1564
1565                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1566                 if (status != 0)
1567                         goto fail;
1568
1569                 status = ixgbe_get_i2c_ack(hw);
1570                 if (status != 0)
1571                         goto fail;
1572
1573                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1574                 if (status != 0)
1575                         goto fail;
1576
1577                 status = ixgbe_get_i2c_ack(hw);
1578                 if (status != 0)
1579                         goto fail;
1580
1581                 status = ixgbe_clock_out_i2c_byte(hw, data);
1582                 if (status != 0)
1583                         goto fail;
1584
1585                 status = ixgbe_get_i2c_ack(hw);
1586                 if (status != 0)
1587                         goto fail;
1588
1589                 ixgbe_i2c_stop(hw);
1590                 break;
1591
1592 fail:
1593                 ixgbe_i2c_bus_clear(hw);
1594                 retry++;
1595                 if (retry < max_retry)
1596                         hw_dbg(hw, "I2C byte write error - Retrying.\n");
1597                 else
1598                         hw_dbg(hw, "I2C byte write error.\n");
1599         } while (retry < max_retry);
1600
1601         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1602
1603         return status;
1604 }
1605
1606 /**
1607  *  ixgbe_i2c_start - Sets I2C start condition
1608  *  @hw: pointer to hardware structure
1609  *
1610  *  Sets I2C start condition (High -> Low on SDA while SCL is High)
1611  **/
1612 static void ixgbe_i2c_start(struct ixgbe_hw *hw)
1613 {
1614         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
1615
1616         /* Start condition must begin with data and clock high */
1617         ixgbe_set_i2c_data(hw, &i2cctl, 1);
1618         ixgbe_raise_i2c_clk(hw, &i2cctl);
1619
1620         /* Setup time for start condition (4.7us) */
1621         udelay(IXGBE_I2C_T_SU_STA);
1622
1623         ixgbe_set_i2c_data(hw, &i2cctl, 0);
1624
1625         /* Hold time for start condition (4us) */
1626         udelay(IXGBE_I2C_T_HD_STA);
1627
1628         ixgbe_lower_i2c_clk(hw, &i2cctl);
1629
1630         /* Minimum low period of clock is 4.7 us */
1631         udelay(IXGBE_I2C_T_LOW);
1632
1633 }
1634
1635 /**
1636  *  ixgbe_i2c_stop - Sets I2C stop condition
1637  *  @hw: pointer to hardware structure
1638  *
1639  *  Sets I2C stop condition (Low -> High on SDA while SCL is High)
1640  **/
1641 static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
1642 {
1643         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
1644
1645         /* Stop condition must begin with data low and clock high */
1646         ixgbe_set_i2c_data(hw, &i2cctl, 0);
1647         ixgbe_raise_i2c_clk(hw, &i2cctl);
1648
1649         /* Setup time for stop condition (4us) */
1650         udelay(IXGBE_I2C_T_SU_STO);
1651
1652         ixgbe_set_i2c_data(hw, &i2cctl, 1);
1653
1654         /* bus free time between stop and start (4.7us)*/
1655         udelay(IXGBE_I2C_T_BUF);
1656 }
1657
1658 /**
1659  *  ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
1660  *  @hw: pointer to hardware structure
1661  *  @data: data byte to clock in
1662  *
1663  *  Clocks in one byte data via I2C data/clock
1664  **/
1665 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
1666 {
1667         s32 i;
1668         bool bit = false;
1669
1670         for (i = 7; i >= 0; i--) {
1671                 ixgbe_clock_in_i2c_bit(hw, &bit);
1672                 *data |= bit << i;
1673         }
1674
1675         return 0;
1676 }
1677
1678 /**
1679  *  ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
1680  *  @hw: pointer to hardware structure
1681  *  @data: data byte clocked out
1682  *
1683  *  Clocks out one byte data via I2C data/clock
1684  **/
1685 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
1686 {
1687         s32 status;
1688         s32 i;
1689         u32 i2cctl;
1690         bool bit = false;
1691
1692         for (i = 7; i >= 0; i--) {
1693                 bit = (data >> i) & 0x1;
1694                 status = ixgbe_clock_out_i2c_bit(hw, bit);
1695
1696                 if (status != 0)
1697                         break;
1698         }
1699
1700         /* Release SDA line (set high) */
1701         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
1702         i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
1703         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
1704         IXGBE_WRITE_FLUSH(hw);
1705
1706         return status;
1707 }
1708
1709 /**
1710  *  ixgbe_get_i2c_ack - Polls for I2C ACK
1711  *  @hw: pointer to hardware structure
1712  *
1713  *  Clocks in/out one bit via I2C data/clock
1714  **/
1715 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
1716 {
1717         s32 status = 0;
1718         u32 i = 0;
1719         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
1720         u32 timeout = 10;
1721         bool ack = true;
1722
1723         ixgbe_raise_i2c_clk(hw, &i2cctl);
1724
1725
1726         /* Minimum high period of clock is 4us */
1727         udelay(IXGBE_I2C_T_HIGH);
1728
1729         /* Poll for ACK.  Note that ACK in I2C spec is
1730          * transition from 1 to 0 */
1731         for (i = 0; i < timeout; i++) {
1732                 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
1733                 ack = ixgbe_get_i2c_data(hw, &i2cctl);
1734
1735                 udelay(1);
1736                 if (ack == 0)
1737                         break;
1738         }
1739
1740         if (ack == 1) {
1741                 hw_dbg(hw, "I2C ack was not received.\n");
1742                 status = IXGBE_ERR_I2C;
1743         }
1744
1745         ixgbe_lower_i2c_clk(hw, &i2cctl);
1746
1747         /* Minimum low period of clock is 4.7 us */
1748         udelay(IXGBE_I2C_T_LOW);
1749
1750         return status;
1751 }
1752
1753 /**
1754  *  ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
1755  *  @hw: pointer to hardware structure
1756  *  @data: read data value
1757  *
1758  *  Clocks in one bit via I2C data/clock
1759  **/
1760 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
1761 {
1762         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
1763
1764         ixgbe_raise_i2c_clk(hw, &i2cctl);
1765
1766         /* Minimum high period of clock is 4us */
1767         udelay(IXGBE_I2C_T_HIGH);
1768
1769         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
1770         *data = ixgbe_get_i2c_data(hw, &i2cctl);
1771
1772         ixgbe_lower_i2c_clk(hw, &i2cctl);
1773
1774         /* Minimum low period of clock is 4.7 us */
1775         udelay(IXGBE_I2C_T_LOW);
1776
1777         return 0;
1778 }
1779
1780 /**
1781  *  ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
1782  *  @hw: pointer to hardware structure
1783  *  @data: data value to write
1784  *
1785  *  Clocks out one bit via I2C data/clock
1786  **/
1787 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
1788 {
1789         s32 status;
1790         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
1791
1792         status = ixgbe_set_i2c_data(hw, &i2cctl, data);
1793         if (status == 0) {
1794                 ixgbe_raise_i2c_clk(hw, &i2cctl);
1795
1796                 /* Minimum high period of clock is 4us */
1797                 udelay(IXGBE_I2C_T_HIGH);
1798
1799                 ixgbe_lower_i2c_clk(hw, &i2cctl);
1800
1801                 /* Minimum low period of clock is 4.7 us.
1802                  * This also takes care of the data hold time.
1803                  */
1804                 udelay(IXGBE_I2C_T_LOW);
1805         } else {
1806                 hw_dbg(hw, "I2C data was not set to %X\n", data);
1807                 return IXGBE_ERR_I2C;
1808         }
1809
1810         return 0;
1811 }
1812 /**
1813  *  ixgbe_raise_i2c_clk - Raises the I2C SCL clock
1814  *  @hw: pointer to hardware structure
1815  *  @i2cctl: Current value of I2CCTL register
1816  *
1817  *  Raises the I2C clock line '0'->'1'
1818  **/
1819 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1820 {
1821         u32 i = 0;
1822         u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
1823         u32 i2cctl_r = 0;
1824
1825         for (i = 0; i < timeout; i++) {
1826                 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw);
1827                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
1828                 IXGBE_WRITE_FLUSH(hw);
1829                 /* SCL rise time (1000ns) */
1830                 udelay(IXGBE_I2C_T_RISE);
1831
1832                 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
1833                 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw))
1834                         break;
1835         }
1836 }
1837
1838 /**
1839  *  ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
1840  *  @hw: pointer to hardware structure
1841  *  @i2cctl: Current value of I2CCTL register
1842  *
1843  *  Lowers the I2C clock line '1'->'0'
1844  **/
1845 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1846 {
1847
1848         *i2cctl &= ~IXGBE_I2C_CLK_OUT_BY_MAC(hw);
1849
1850         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
1851         IXGBE_WRITE_FLUSH(hw);
1852
1853         /* SCL fall time (300ns) */
1854         udelay(IXGBE_I2C_T_FALL);
1855 }
1856
1857 /**
1858  *  ixgbe_set_i2c_data - Sets the I2C data bit
1859  *  @hw: pointer to hardware structure
1860  *  @i2cctl: Current value of I2CCTL register
1861  *  @data: I2C data value (0 or 1) to set
1862  *
1863  *  Sets the I2C data bit
1864  **/
1865 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
1866 {
1867         if (data)
1868                 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
1869         else
1870                 *i2cctl &= ~IXGBE_I2C_DATA_OUT_BY_MAC(hw);
1871
1872         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
1873         IXGBE_WRITE_FLUSH(hw);
1874
1875         /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
1876         udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
1877
1878         /* Verify data was set correctly */
1879         *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
1880         if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
1881                 hw_dbg(hw, "Error - I2C data was not set to %X.\n", data);
1882                 return IXGBE_ERR_I2C;
1883         }
1884
1885         return 0;
1886 }
1887
1888 /**
1889  *  ixgbe_get_i2c_data - Reads the I2C SDA data bit
1890  *  @hw: pointer to hardware structure
1891  *  @i2cctl: Current value of I2CCTL register
1892  *
1893  *  Returns the I2C data bit value
1894  **/
1895 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
1896 {
1897         if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw))
1898                 return true;
1899         return false;
1900 }
1901
1902 /**
1903  *  ixgbe_i2c_bus_clear - Clears the I2C bus
1904  *  @hw: pointer to hardware structure
1905  *
1906  *  Clears the I2C bus by sending nine clock pulses.
1907  *  Used when data line is stuck low.
1908  **/
1909 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
1910 {
1911         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
1912         u32 i;
1913
1914         ixgbe_i2c_start(hw);
1915
1916         ixgbe_set_i2c_data(hw, &i2cctl, 1);
1917
1918         for (i = 0; i < 9; i++) {
1919                 ixgbe_raise_i2c_clk(hw, &i2cctl);
1920
1921                 /* Min high period of clock is 4us */
1922                 udelay(IXGBE_I2C_T_HIGH);
1923
1924                 ixgbe_lower_i2c_clk(hw, &i2cctl);
1925
1926                 /* Min low period of clock is 4.7us*/
1927                 udelay(IXGBE_I2C_T_LOW);
1928         }
1929
1930         ixgbe_i2c_start(hw);
1931
1932         /* Put the i2c bus back to default state */
1933         ixgbe_i2c_stop(hw);
1934 }
1935
1936 /**
1937  *  ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
1938  *  @hw: pointer to hardware structure
1939  *
1940  *  Checks if the LASI temp alarm status was triggered due to overtemp
1941  **/
1942 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
1943 {
1944         u16 phy_data = 0;
1945
1946         if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
1947                 return 0;
1948
1949         /* Check that the LASI temp alarm status was triggered */
1950         hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
1951                              MDIO_MMD_PMAPMD, &phy_data);
1952
1953         if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
1954                 return 0;
1955
1956         return IXGBE_ERR_OVERTEMP;
1957 }