1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2013 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
29 #include <linux/ptp_classify.h>
32 * The 82599 and the X540 do not have true 64bit nanosecond scale
33 * counter registers. Instead, SYSTIME is defined by a fixed point
34 * system which allows the user to define the scale counter increment
35 * value at every level change of the oscillator driving the SYSTIME
36 * value. For both devices the TIMINCA:IV field defines this
37 * increment. On the X540 device, 31 bits are provided. However on the
38 * 82599 only provides 24 bits. The time unit is determined by the
39 * clock frequency of the oscillator in combination with the TIMINCA
40 * register. When these devices link at 10Gb the oscillator has a
41 * period of 6.4ns. In order to convert the scale counter into
42 * nanoseconds the cyclecounter and timecounter structures are
43 * used. The SYSTIME registers need to be converted to ns values by use
44 * of only a right shift (division by power of 2). The following math
45 * determines the largest incvalue that will fit into the available
46 * bits in the TIMINCA register.
48 * PeriodWidth: Number of bits to store the clock period
49 * MaxWidth: The maximum width value of the TIMINCA register
50 * Period: The clock period for the oscillator
51 * round(): discard the fractional portion of the calculation
53 * Period * [ 2 ^ ( MaxWidth - PeriodWidth ) ]
55 * For the X540, MaxWidth is 31 bits, and the base period is 6.4 ns
56 * For the 82599, MaxWidth is 24 bits, and the base period is 6.4 ns
58 * The period also changes based on the link speed:
59 * At 10Gb link or no link, the period remains the same.
60 * At 1Gb link, the period is multiplied by 10. (64ns)
61 * At 100Mb link, the period is multiplied by 100. (640ns)
63 * The calculated value allows us to right shift the SYSTIME register
64 * value in order to quickly convert it into a nanosecond clock,
65 * while allowing for the maximum possible adjustment value.
67 * These diagrams are only for the 10Gb link period
70 * +--------------+ +--------------+
71 * X540 | 32 | | 1 | 3 | 28 |
72 * *--------------+ +--------------+
73 * \________ 36 bits ______/ fract
75 * +--------------+ +--------------+
76 * 82599 | 32 | | 8 | 3 | 21 |
77 * *--------------+ +--------------+
78 * \________ 43 bits ______/ fract
80 * The 36 bit X540 SYSTIME overflows every
81 * 2^36 * 10^-9 / 60 = 1.14 minutes or 69 seconds
83 * The 43 bit 82599 SYSTIME overflows every
84 * 2^43 * 10^-9 / 3600 = 2.4 hours
86 #define IXGBE_INCVAL_10GB 0x66666666
87 #define IXGBE_INCVAL_1GB 0x40000000
88 #define IXGBE_INCVAL_100 0x50000000
90 #define IXGBE_INCVAL_SHIFT_10GB 28
91 #define IXGBE_INCVAL_SHIFT_1GB 24
92 #define IXGBE_INCVAL_SHIFT_100 21
94 #define IXGBE_INCVAL_SHIFT_82599 7
95 #define IXGBE_INCPER_SHIFT_82599 24
96 #define IXGBE_MAX_TIMEADJ_VALUE 0x7FFFFFFFFFFFFFFFULL
98 #define IXGBE_OVERFLOW_PERIOD (HZ * 30)
99 #define IXGBE_PTP_TX_TIMEOUT (HZ * 15)
101 /* half of a one second clock period, for use with PPS signal. We have to use
102 * this instead of something pre-defined like IXGBE_PTP_PPS_HALF_SECOND, in
103 * order to force at least 64bits of precision for shifting
105 #define IXGBE_PTP_PPS_HALF_SECOND 500000000ULL
108 * ixgbe_ptp_setup_sdp
109 * @hw: the hardware private structure
111 * this function enables or disables the clock out feature on SDP0 for
112 * the X540 device. It will create a 1second periodic output that can
113 * be used as the PPS (via an interrupt).
115 * It calculates when the systime will be on an exact second, and then
116 * aligns the start of the PPS signal to that value. The shift is
117 * necessary because it can change based on the link speed.
119 static void ixgbe_ptp_setup_sdp(struct ixgbe_adapter *adapter)
121 struct ixgbe_hw *hw = &adapter->hw;
122 int shift = adapter->cc.shift;
123 u32 esdp, tsauxc, clktiml, clktimh, trgttiml, trgttimh, rem;
124 u64 ns = 0, clock_edge = 0;
126 if ((adapter->flags2 & IXGBE_FLAG2_PTP_PPS_ENABLED) &&
127 (hw->mac.type == ixgbe_mac_X540)) {
129 /* disable the pin first */
130 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, 0x0);
131 IXGBE_WRITE_FLUSH(hw);
133 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
136 * enable the SDP0 pin as output, and connected to the
137 * native function for Timesync (ClockOut)
139 esdp |= (IXGBE_ESDP_SDP0_DIR |
140 IXGBE_ESDP_SDP0_NATIVE);
143 * enable the Clock Out feature on SDP0, and allow
144 * interrupts to occur when the pin changes
146 tsauxc = (IXGBE_TSAUXC_EN_CLK |
147 IXGBE_TSAUXC_SYNCLK |
148 IXGBE_TSAUXC_SDP0_INT);
150 /* clock period (or pulse length) */
151 clktiml = (u32)(IXGBE_PTP_PPS_HALF_SECOND << shift);
152 clktimh = (u32)((IXGBE_PTP_PPS_HALF_SECOND << shift) >> 32);
155 * Account for the cyclecounter wrap-around value by
156 * using the converted ns value of the current time to
157 * check for when the next aligned second would occur.
159 clock_edge |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
160 clock_edge |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) << 32;
161 ns = timecounter_cyc2time(&adapter->tc, clock_edge);
163 div_u64_rem(ns, IXGBE_PTP_PPS_HALF_SECOND, &rem);
164 clock_edge += ((IXGBE_PTP_PPS_HALF_SECOND - (u64)rem) << shift);
166 /* specify the initial clock start time */
167 trgttiml = (u32)clock_edge;
168 trgttimh = (u32)(clock_edge >> 32);
170 IXGBE_WRITE_REG(hw, IXGBE_CLKTIML, clktiml);
171 IXGBE_WRITE_REG(hw, IXGBE_CLKTIMH, clktimh);
172 IXGBE_WRITE_REG(hw, IXGBE_TRGTTIML0, trgttiml);
173 IXGBE_WRITE_REG(hw, IXGBE_TRGTTIMH0, trgttimh);
175 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
176 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
178 IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, 0x0);
181 IXGBE_WRITE_FLUSH(hw);
185 * ixgbe_ptp_read - read raw cycle counter (to be used by time counter)
186 * @cc: the cyclecounter structure
188 * this function reads the cyclecounter registers and is called by the
189 * cyclecounter structure used to construct a ns counter from the
190 * arbitrary fixed point registers
192 static cycle_t ixgbe_ptp_read(const struct cyclecounter *cc)
194 struct ixgbe_adapter *adapter =
195 container_of(cc, struct ixgbe_adapter, cc);
196 struct ixgbe_hw *hw = &adapter->hw;
199 stamp |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
200 stamp |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) << 32;
207 * @ptp: the ptp clock structure
208 * @ppb: parts per billion adjustment from base
210 * adjust the frequency of the ptp cycle counter by the
211 * indicated ppb from the base frequency.
213 static int ixgbe_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
215 struct ixgbe_adapter *adapter =
216 container_of(ptp, struct ixgbe_adapter, ptp_caps);
217 struct ixgbe_hw *hw = &adapter->hw;
228 incval = ACCESS_ONCE(adapter->base_incval);
232 diff = div_u64(freq, 1000000000ULL);
234 incval = neg_adj ? (incval - diff) : (incval + diff);
236 switch (hw->mac.type) {
238 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
240 case ixgbe_mac_82599EB:
241 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
242 (1 << IXGBE_INCPER_SHIFT_82599) |
254 * @ptp: the ptp clock structure
255 * @delta: offset to adjust the cycle counter by
257 * adjust the timer by resetting the timecounter structure.
259 static int ixgbe_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
261 struct ixgbe_adapter *adapter =
262 container_of(ptp, struct ixgbe_adapter, ptp_caps);
266 spin_lock_irqsave(&adapter->tmreg_lock, flags);
268 now = timecounter_read(&adapter->tc);
271 /* reset the timecounter */
272 timecounter_init(&adapter->tc,
276 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
278 ixgbe_ptp_setup_sdp(adapter);
285 * @ptp: the ptp clock structure
286 * @ts: timespec structure to hold the current time value
288 * read the timecounter and return the correct value on ns,
289 * after converting it into a struct timespec.
291 static int ixgbe_ptp_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
293 struct ixgbe_adapter *adapter =
294 container_of(ptp, struct ixgbe_adapter, ptp_caps);
299 spin_lock_irqsave(&adapter->tmreg_lock, flags);
300 ns = timecounter_read(&adapter->tc);
301 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
303 ts->tv_sec = div_u64_rem(ns, 1000000000ULL, &remainder);
304 ts->tv_nsec = remainder;
311 * @ptp: the ptp clock structure
312 * @ts: the timespec containing the new time for the cycle counter
314 * reset the timecounter to use a new base value instead of the kernel
317 static int ixgbe_ptp_settime(struct ptp_clock_info *ptp,
318 const struct timespec *ts)
320 struct ixgbe_adapter *adapter =
321 container_of(ptp, struct ixgbe_adapter, ptp_caps);
325 ns = ts->tv_sec * 1000000000ULL;
328 /* reset the timecounter */
329 spin_lock_irqsave(&adapter->tmreg_lock, flags);
330 timecounter_init(&adapter->tc, &adapter->cc, ns);
331 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
333 ixgbe_ptp_setup_sdp(adapter);
338 * ixgbe_ptp_feature_enable
339 * @ptp: the ptp clock structure
340 * @rq: the requested feature to change
341 * @on: whether to enable or disable the feature
343 * enable (or disable) ancillary features of the phc subsystem.
344 * our driver only supports the PPS feature on the X540
346 static int ixgbe_ptp_feature_enable(struct ptp_clock_info *ptp,
347 struct ptp_clock_request *rq, int on)
349 struct ixgbe_adapter *adapter =
350 container_of(ptp, struct ixgbe_adapter, ptp_caps);
353 * When PPS is enabled, unmask the interrupt for the ClockOut
354 * feature, so that the interrupt handler can send the PPS
355 * event when the clock SDP triggers. Clear mask when PPS is
358 if (rq->type == PTP_CLK_REQ_PPS) {
359 switch (adapter->hw.mac.type) {
362 adapter->flags2 |= IXGBE_FLAG2_PTP_PPS_ENABLED;
364 adapter->flags2 &= ~IXGBE_FLAG2_PTP_PPS_ENABLED;
366 ixgbe_ptp_setup_sdp(adapter);
377 * ixgbe_ptp_check_pps_event
378 * @adapter: the private adapter structure
379 * @eicr: the interrupt cause register value
381 * This function is called by the interrupt routine when checking for
382 * interrupts. It will check and handle a pps event.
384 void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter, u32 eicr)
386 struct ixgbe_hw *hw = &adapter->hw;
387 struct ptp_clock_event event;
389 event.type = PTP_CLOCK_PPS;
391 /* this check is necessary in case the interrupt was enabled via some
392 * alternative means (ex. debug_fs). Better to check here than
393 * everywhere that calls this function.
395 if (!adapter->ptp_clock)
398 switch (hw->mac.type) {
400 ptp_clock_event(adapter->ptp_clock, &event);
408 * ixgbe_ptp_overflow_check - watchdog task to detect SYSTIME overflow
409 * @adapter: private adapter struct
411 * this watchdog task periodically reads the timecounter
412 * in order to prevent missing when the system time registers wrap
413 * around. This needs to be run approximately twice a minute.
415 void ixgbe_ptp_overflow_check(struct ixgbe_adapter *adapter)
417 bool timeout = time_is_before_jiffies(adapter->last_overflow_check +
418 IXGBE_OVERFLOW_PERIOD);
422 ixgbe_ptp_gettime(&adapter->ptp_caps, &ts);
423 adapter->last_overflow_check = jiffies;
428 * ixgbe_ptp_rx_hang - detect error case when Rx timestamp registers latched
429 * @adapter: private network adapter structure
431 * this watchdog task is scheduled to detect error case where hardware has
432 * dropped an Rx packet that was timestamped when the ring is full. The
433 * particular error is rare but leaves the device in a state unable to timestamp
434 * any future packets.
436 void ixgbe_ptp_rx_hang(struct ixgbe_adapter *adapter)
438 struct ixgbe_hw *hw = &adapter->hw;
439 u32 tsyncrxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
440 unsigned long rx_event;
442 /* if we don't have a valid timestamp in the registers, just update the
443 * timeout counter and exit
445 if (!(tsyncrxctl & IXGBE_TSYNCRXCTL_VALID)) {
446 adapter->last_rx_ptp_check = jiffies;
450 /* determine the most recent watchdog or rx_timestamp event */
451 rx_event = adapter->last_rx_ptp_check;
452 if (time_after(adapter->last_rx_timestamp, rx_event))
453 rx_event = adapter->last_rx_timestamp;
455 /* only need to read the high RXSTMP register to clear the lock */
456 if (time_is_before_jiffies(rx_event + 5*HZ)) {
457 IXGBE_READ_REG(hw, IXGBE_RXSTMPH);
458 adapter->last_rx_ptp_check = jiffies;
460 e_warn(drv, "clearing RX Timestamp hang\n");
465 * ixgbe_ptp_tx_hwtstamp - utility function which checks for TX time stamp
466 * @adapter: the private adapter struct
468 * if the timestamp is valid, we convert it into the timecounter ns
469 * value, then store that result into the shhwtstamps structure which
470 * is passed up the network stack
472 static void ixgbe_ptp_tx_hwtstamp(struct ixgbe_adapter *adapter)
474 struct ixgbe_hw *hw = &adapter->hw;
475 struct skb_shared_hwtstamps shhwtstamps;
479 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
480 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_TXSTMPH) << 32;
482 spin_lock_irqsave(&adapter->tmreg_lock, flags);
483 ns = timecounter_cyc2time(&adapter->tc, regval);
484 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
486 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
487 shhwtstamps.hwtstamp = ns_to_ktime(ns);
488 skb_tstamp_tx(adapter->ptp_tx_skb, &shhwtstamps);
490 dev_kfree_skb_any(adapter->ptp_tx_skb);
491 adapter->ptp_tx_skb = NULL;
492 clear_bit_unlock(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state);
496 * ixgbe_ptp_tx_hwtstamp_work
497 * @work: pointer to the work struct
499 * This work item polls TSYNCTXCTL valid bit to determine when a Tx hardware
500 * timestamp has been taken for the current skb. It is necesary, because the
501 * descriptor's "done" bit does not correlate with the timestamp event.
503 static void ixgbe_ptp_tx_hwtstamp_work(struct work_struct *work)
505 struct ixgbe_adapter *adapter = container_of(work, struct ixgbe_adapter,
507 struct ixgbe_hw *hw = &adapter->hw;
508 bool timeout = time_is_before_jiffies(adapter->ptp_tx_start +
509 IXGBE_PTP_TX_TIMEOUT);
513 dev_kfree_skb_any(adapter->ptp_tx_skb);
514 adapter->ptp_tx_skb = NULL;
515 clear_bit_unlock(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state);
516 e_warn(drv, "clearing Tx Timestamp hang\n");
520 tsynctxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
521 if (tsynctxctl & IXGBE_TSYNCTXCTL_VALID)
522 ixgbe_ptp_tx_hwtstamp(adapter);
524 /* reschedule to keep checking if it's not available yet */
525 schedule_work(&adapter->ptp_tx_work);
529 * ixgbe_ptp_rx_hwtstamp - utility function which checks for RX time stamp
530 * @adapter: pointer to adapter struct
531 * @skb: particular skb to send timestamp with
533 * if the timestamp is valid, we convert it into the timecounter ns
534 * value, then store that result into the shhwtstamps structure which
535 * is passed up the network stack
537 void ixgbe_ptp_rx_hwtstamp(struct ixgbe_adapter *adapter, struct sk_buff *skb)
539 struct ixgbe_hw *hw = &adapter->hw;
540 struct skb_shared_hwtstamps *shhwtstamps;
545 tsyncrxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
546 if (!(tsyncrxctl & IXGBE_TSYNCRXCTL_VALID))
549 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
550 regval |= (u64)IXGBE_READ_REG(hw, IXGBE_RXSTMPH) << 32;
552 spin_lock_irqsave(&adapter->tmreg_lock, flags);
553 ns = timecounter_cyc2time(&adapter->tc, regval);
554 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
556 shhwtstamps = skb_hwtstamps(skb);
557 shhwtstamps->hwtstamp = ns_to_ktime(ns);
559 /* Update the last_rx_timestamp timer in order to enable watchdog check
560 * for error case of latched timestamp on a dropped packet.
562 adapter->last_rx_timestamp = jiffies;
565 int ixgbe_ptp_get_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr)
567 struct hwtstamp_config *config = &adapter->tstamp_config;
569 return copy_to_user(ifr->ifr_data, config,
570 sizeof(*config)) ? -EFAULT : 0;
574 * ixgbe_ptp_set_timestamp_mode - setup the hardware for the requested mode
575 * @adapter: the private ixgbe adapter structure
576 * @config: the hwtstamp configuration requested
578 * Outgoing time stamping can be enabled and disabled. Play nice and
579 * disable it when requested, although it shouldn't cause any overhead
580 * when no packet needs it. At most one packet in the queue may be
581 * marked for time stamping, otherwise it would be impossible to tell
582 * for sure to which packet the hardware time stamp belongs.
584 * Incoming time stamping has to be configured via the hardware
585 * filters. Not all combinations are supported, in particular event
586 * type has to be specified. Matching the kind of event packet is
587 * not supported, with the exception of "all V2 events regardless of
590 * Since hardware always timestamps Path delay packets when timestamping V2
591 * packets, regardless of the type specified in the register, only use V2
592 * Event mode. This more accurately tells the user what the hardware is going
595 * Note: this may modify the hwtstamp configuration towards a more general
596 * mode, if required to support the specifically requested mode.
598 static int ixgbe_ptp_set_timestamp_mode(struct ixgbe_adapter *adapter,
599 struct hwtstamp_config *config)
601 struct ixgbe_hw *hw = &adapter->hw;
602 u32 tsync_tx_ctl = IXGBE_TSYNCTXCTL_ENABLED;
603 u32 tsync_rx_ctl = IXGBE_TSYNCRXCTL_ENABLED;
604 u32 tsync_rx_mtrl = PTP_EV_PORT << 16;
608 /* reserved for future extensions */
612 switch (config->tx_type) {
613 case HWTSTAMP_TX_OFF:
621 switch (config->rx_filter) {
622 case HWTSTAMP_FILTER_NONE:
626 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
627 tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_L4_V1;
628 tsync_rx_mtrl |= IXGBE_RXMTRL_V1_SYNC_MSG;
630 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
631 tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_L4_V1;
632 tsync_rx_mtrl |= IXGBE_RXMTRL_V1_DELAY_REQ_MSG;
634 case HWTSTAMP_FILTER_PTP_V2_EVENT:
635 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
636 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
637 case HWTSTAMP_FILTER_PTP_V2_SYNC:
638 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
639 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
640 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
641 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
642 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
643 tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_EVENT_V2;
645 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
647 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
648 case HWTSTAMP_FILTER_ALL:
651 * register RXMTRL must be set in order to do V1 packets,
652 * therefore it is not possible to time stamp both V1 Sync and
653 * Delay_Req messages and hardware does not support
654 * timestamping all packets => return error
656 config->rx_filter = HWTSTAMP_FILTER_NONE;
660 if (hw->mac.type == ixgbe_mac_82598EB) {
661 if (tsync_rx_ctl | tsync_tx_ctl)
666 /* define ethertype filter for timestamping L2 packets */
668 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
669 (IXGBE_ETQF_FILTER_EN | /* enable filter */
670 IXGBE_ETQF_1588 | /* enable timestamping */
671 ETH_P_1588)); /* 1588 eth protocol type */
673 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
675 /* enable/disable TX */
676 regval = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
677 regval &= ~IXGBE_TSYNCTXCTL_ENABLED;
678 regval |= tsync_tx_ctl;
679 IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, regval);
681 /* enable/disable RX */
682 regval = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
683 regval &= ~(IXGBE_TSYNCRXCTL_ENABLED | IXGBE_TSYNCRXCTL_TYPE_MASK);
684 regval |= tsync_rx_ctl;
685 IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, regval);
687 /* define which PTP packets are time stamped */
688 IXGBE_WRITE_REG(hw, IXGBE_RXMTRL, tsync_rx_mtrl);
690 IXGBE_WRITE_FLUSH(hw);
692 /* clear TX/RX time stamp registers, just to be sure */
693 regval = IXGBE_READ_REG(hw, IXGBE_TXSTMPH);
694 regval = IXGBE_READ_REG(hw, IXGBE_RXSTMPH);
700 * ixgbe_ptp_set_ts_config - user entry point for timestamp mode
701 * @adapter: pointer to adapter struct
704 * Set hardware to requested mode. If unsupported, return an error with no
705 * changes. Otherwise, store the mode for future reference.
707 int ixgbe_ptp_set_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr)
709 struct hwtstamp_config config;
712 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
715 err = ixgbe_ptp_set_timestamp_mode(adapter, &config);
719 /* save these settings for future reference */
720 memcpy(&adapter->tstamp_config, &config,
721 sizeof(adapter->tstamp_config));
723 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
728 * ixgbe_ptp_start_cyclecounter - create the cycle counter from hw
729 * @adapter: pointer to the adapter structure
731 * This function should be called to set the proper values for the TIMINCA
732 * register and tell the cyclecounter structure what the tick rate of SYSTIME
733 * is. It does not directly modify SYSTIME registers or the timecounter
734 * structure. It should be called whenever a new TIMINCA value is necessary,
735 * such as during initialization or when the link speed changes.
737 void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter)
739 struct ixgbe_hw *hw = &adapter->hw;
745 * Scale the NIC cycle counter by a large factor so that
746 * relatively small corrections to the frequency can be added
747 * or subtracted. The drawbacks of a large factor include
748 * (a) the clock register overflows more quickly, (b) the cycle
749 * counter structure must be able to convert the systime value
750 * to nanoseconds using only a multiplier and a right-shift,
751 * and (c) the value must fit within the timinca register space
752 * => math based on internal DMA clock rate and available bits
754 * Note that when there is no link, internal DMA clock is same as when
755 * link speed is 10Gb. Set the registers correctly even when link is
756 * down to preserve the clock setting
758 switch (adapter->link_speed) {
759 case IXGBE_LINK_SPEED_100_FULL:
760 incval = IXGBE_INCVAL_100;
761 shift = IXGBE_INCVAL_SHIFT_100;
763 case IXGBE_LINK_SPEED_1GB_FULL:
764 incval = IXGBE_INCVAL_1GB;
765 shift = IXGBE_INCVAL_SHIFT_1GB;
767 case IXGBE_LINK_SPEED_10GB_FULL:
769 incval = IXGBE_INCVAL_10GB;
770 shift = IXGBE_INCVAL_SHIFT_10GB;
775 * Modify the calculated values to fit within the correct
776 * number of bits specified by the hardware. The 82599 doesn't
777 * have the same space as the X540, so bitshift the calculated
780 switch (hw->mac.type) {
782 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
784 case ixgbe_mac_82599EB:
785 incval >>= IXGBE_INCVAL_SHIFT_82599;
786 shift -= IXGBE_INCVAL_SHIFT_82599;
787 IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
788 (1 << IXGBE_INCPER_SHIFT_82599) |
792 /* other devices aren't supported */
796 /* update the base incval used to calculate frequency adjustment */
797 ACCESS_ONCE(adapter->base_incval) = incval;
800 /* need lock to prevent incorrect read while modifying cyclecounter */
801 spin_lock_irqsave(&adapter->tmreg_lock, flags);
803 memset(&adapter->cc, 0, sizeof(adapter->cc));
804 adapter->cc.read = ixgbe_ptp_read;
805 adapter->cc.mask = CLOCKSOURCE_MASK(64);
806 adapter->cc.shift = shift;
807 adapter->cc.mult = 1;
809 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
814 * @adapter: the ixgbe private board structure
816 * When the MAC resets, all the hardware bits for timesync are reset. This
817 * function is used to re-enable the device for PTP based on current settings.
818 * We do lose the current clock time, so just reset the cyclecounter to the
819 * system real clock time.
821 * This function will maintain hwtstamp_config settings, and resets the SDP
822 * output if it was enabled.
824 void ixgbe_ptp_reset(struct ixgbe_adapter *adapter)
826 struct ixgbe_hw *hw = &adapter->hw;
829 /* set SYSTIME registers to 0 just in case */
830 IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0x00000000);
831 IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0x00000000);
832 IXGBE_WRITE_FLUSH(hw);
834 /* reset the hardware timestamping mode */
835 ixgbe_ptp_set_timestamp_mode(adapter, &adapter->tstamp_config);
837 ixgbe_ptp_start_cyclecounter(adapter);
839 spin_lock_irqsave(&adapter->tmreg_lock, flags);
841 /* reset the ns time counter */
842 timecounter_init(&adapter->tc, &adapter->cc,
843 ktime_to_ns(ktime_get_real()));
845 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
848 * Now that the shift has been calculated and the systime
849 * registers reset, (re-)enable the Clock out feature
851 ixgbe_ptp_setup_sdp(adapter);
855 * ixgbe_ptp_create_clock
856 * @adapter: the ixgbe private adapter structure
858 * This function performs setup of the user entry point function table and
859 * initializes the PTP clock device, which is used to access the clock-like
860 * features of the PTP core. It will be called by ixgbe_ptp_init, only if
861 * there isn't already a clock device (such as after a suspend/resume cycle,
862 * where the clock device wasn't destroyed).
864 static int ixgbe_ptp_create_clock(struct ixgbe_adapter *adapter)
866 struct net_device *netdev = adapter->netdev;
869 /* do nothing if we already have a clock device */
870 if (!IS_ERR_OR_NULL(adapter->ptp_clock))
873 switch (adapter->hw.mac.type) {
875 snprintf(adapter->ptp_caps.name,
876 sizeof(adapter->ptp_caps.name),
878 adapter->ptp_caps.owner = THIS_MODULE;
879 adapter->ptp_caps.max_adj = 250000000;
880 adapter->ptp_caps.n_alarm = 0;
881 adapter->ptp_caps.n_ext_ts = 0;
882 adapter->ptp_caps.n_per_out = 0;
883 adapter->ptp_caps.pps = 1;
884 adapter->ptp_caps.adjfreq = ixgbe_ptp_adjfreq;
885 adapter->ptp_caps.adjtime = ixgbe_ptp_adjtime;
886 adapter->ptp_caps.gettime = ixgbe_ptp_gettime;
887 adapter->ptp_caps.settime = ixgbe_ptp_settime;
888 adapter->ptp_caps.enable = ixgbe_ptp_feature_enable;
890 case ixgbe_mac_82599EB:
891 snprintf(adapter->ptp_caps.name,
892 sizeof(adapter->ptp_caps.name),
894 adapter->ptp_caps.owner = THIS_MODULE;
895 adapter->ptp_caps.max_adj = 250000000;
896 adapter->ptp_caps.n_alarm = 0;
897 adapter->ptp_caps.n_ext_ts = 0;
898 adapter->ptp_caps.n_per_out = 0;
899 adapter->ptp_caps.pps = 0;
900 adapter->ptp_caps.adjfreq = ixgbe_ptp_adjfreq;
901 adapter->ptp_caps.adjtime = ixgbe_ptp_adjtime;
902 adapter->ptp_caps.gettime = ixgbe_ptp_gettime;
903 adapter->ptp_caps.settime = ixgbe_ptp_settime;
904 adapter->ptp_caps.enable = ixgbe_ptp_feature_enable;
907 adapter->ptp_clock = NULL;
911 adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps,
912 &adapter->pdev->dev);
913 if (IS_ERR(adapter->ptp_clock)) {
914 err = PTR_ERR(adapter->ptp_clock);
915 adapter->ptp_clock = NULL;
916 e_dev_err("ptp_clock_register failed\n");
919 e_dev_info("registered PHC device on %s\n", netdev->name);
921 /* set default timestamp mode to disabled here. We do this in
922 * create_clock instead of init, because we don't want to override the
923 * previous settings during a resume cycle.
925 adapter->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
926 adapter->tstamp_config.tx_type = HWTSTAMP_TX_OFF;
933 * @adapter: the ixgbe private adapter structure
935 * This function performs the required steps for enabling PTP
936 * support. If PTP support has already been loaded it simply calls the
937 * cyclecounter init routine and exits.
939 void ixgbe_ptp_init(struct ixgbe_adapter *adapter)
941 /* initialize the spin lock first since we can't control when a user
942 * will call the entry functions once we have initialized the clock
945 spin_lock_init(&adapter->tmreg_lock);
947 /* obtain a PTP device, or re-use an existing device */
948 if (ixgbe_ptp_create_clock(adapter))
951 /* we have a clock so we can initialize work now */
952 INIT_WORK(&adapter->ptp_tx_work, ixgbe_ptp_tx_hwtstamp_work);
954 /* reset the PTP related hardware bits */
955 ixgbe_ptp_reset(adapter);
957 /* enter the IXGBE_PTP_RUNNING state */
958 set_bit(__IXGBE_PTP_RUNNING, &adapter->state);
964 * ixgbe_ptp_suspend - stop PTP work items
965 * @ adapter: pointer to adapter struct
967 * this function suspends PTP activity, and prevents more PTP work from being
968 * generated, but does not destroy the PTP clock device.
970 void ixgbe_ptp_suspend(struct ixgbe_adapter *adapter)
972 /* Leave the IXGBE_PTP_RUNNING state. */
973 if (!test_and_clear_bit(__IXGBE_PTP_RUNNING, &adapter->state))
976 /* since this might be called in suspend, we don't clear the state,
977 * but simply reset the auxiliary PPS signal control register
979 IXGBE_WRITE_REG(&adapter->hw, IXGBE_TSAUXC, 0x0);
981 /* ensure that we cancel any pending PTP Tx work item in progress */
982 cancel_work_sync(&adapter->ptp_tx_work);
983 if (adapter->ptp_tx_skb) {
984 dev_kfree_skb_any(adapter->ptp_tx_skb);
985 adapter->ptp_tx_skb = NULL;
986 clear_bit_unlock(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state);
991 * ixgbe_ptp_stop - close the PTP device
992 * @adapter: pointer to adapter struct
994 * completely destroy the PTP device, should only be called when the device is
995 * being fully closed.
997 void ixgbe_ptp_stop(struct ixgbe_adapter *adapter)
999 /* first, suspend PTP activity */
1000 ixgbe_ptp_suspend(adapter);
1002 /* disable the PTP clock device */
1003 if (adapter->ptp_clock) {
1004 ptp_clock_unregister(adapter->ptp_clock);
1005 adapter->ptp_clock = NULL;
1006 e_dev_info("removed PHC on %s\n",
1007 adapter->netdev->name);