drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

   1 /*******************************************************************************
   2  *
   3  *  Intel 10 Gigabit PCI Express Linux driver
   4  *  Copyright(c) 1999 - 2016 Intel Corporation.
   5  *
   6  *  This program is free software; you can redistribute it and/or modify it
   7  *  under the terms and conditions of the GNU General Public License,
   8  *  version 2, as published by the Free Software Foundation.
   9  *
  10  *  This program is distributed in the hope it will be useful, but WITHOUT
  11  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  *  more details.
  14  *
  15  *  The full GNU General Public License is included in this distribution in
  16  *  the file called "COPYING".
  17  *
  18  *  Contact Information:
  19  *  Linux NICS <linux.nics@intel.com>
  20  *  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  21  *  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  22  *
  23  ******************************************************************************/
  24 #include "ixgbe_x540.h"
  25 #include "ixgbe_type.h"
  26 #include "ixgbe_common.h"
  27 #include "ixgbe_phy.h"
  28
  29 static s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *, ixgbe_link_speed);
  30 static s32 ixgbe_setup_fc_x550em(struct ixgbe_hw *);
  31
  32 static s32 ixgbe_get_invariants_X550_x(struct ixgbe_hw *hw)
  33 {
  34         struct ixgbe_mac_info *mac = &hw->mac;
  35         struct ixgbe_phy_info *phy = &hw->phy;
  36
  37         /* Start with X540 invariants, since so simular */
  38         ixgbe_get_invariants_X540(hw);
  39
  40         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
  41                 phy->ops.set_phy_power = NULL;
  42
  43         return 0;
  44 }
  45
  46 /** ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
  47  *  @hw: pointer to hardware structure
  48  **/
  49 static void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
  50 {
  51         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
  52
  53         if (hw->bus.lan_id) {
  54                 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
  55                 esdp |= IXGBE_ESDP_SDP1_DIR;
  56         }
  57         esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
  58         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
  59         IXGBE_WRITE_FLUSH(hw);
  60 }
  61
  62 /**
  63  * ixgbe_read_cs4227 - Read CS4227 register
  64  * @hw: pointer to hardware structure
  65  * @reg: register number to write
  66  * @value: pointer to receive value read
  67  *
  68  * Returns status code
  69  */
  70 static s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
  71 {
  72         return hw->phy.ops.read_i2c_combined_unlocked(hw, IXGBE_CS4227, reg,
  73                                                       value);
  74 }
  75
  76 /**
  77  * ixgbe_write_cs4227 - Write CS4227 register
  78  * @hw: pointer to hardware structure
  79  * @reg: register number to write
  80  * @value: value to write to register
  81  *
  82  * Returns status code
  83  */
  84 static s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
  85 {
  86         return hw->phy.ops.write_i2c_combined_unlocked(hw, IXGBE_CS4227, reg,
  87                                                        value);
  88 }
  89
  90 /**
  91  * ixgbe_read_pe - Read register from port expander
  92  * @hw: pointer to hardware structure
  93  * @reg: register number to read
  94  * @value: pointer to receive read value
  95  *
  96  * Returns status code
  97  */
  98 static s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
  99 {
 100         s32 status;
 101
 102         status = ixgbe_read_i2c_byte_generic_unlocked(hw, reg, IXGBE_PE, value);
 103         if (status)
 104                 hw_err(hw, "port expander access failed with %d\n", status);
 105         return status;
 106 }
 107
 108 /**
 109  * ixgbe_write_pe - Write register to port expander
 110  * @hw: pointer to hardware structure
 111  * @reg: register number to write
 112  * @value: value to write
 113  *
 114  * Returns status code
 115  */
 116 static s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
 117 {
 118         s32 status;
 119
 120         status = ixgbe_write_i2c_byte_generic_unlocked(hw, reg, IXGBE_PE,
 121                                                        value);
 122         if (status)
 123                 hw_err(hw, "port expander access failed with %d\n", status);
 124         return status;
 125 }
 126
 127 /**
 128  * ixgbe_reset_cs4227 - Reset CS4227 using port expander
 129  * @hw: pointer to hardware structure
 130  *
 131  * This function assumes that the caller has acquired the proper semaphore.
 132  * Returns error code
 133  */
 134 static s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
 135 {
 136         s32 status;
 137         u32 retry;
 138         u16 value;
 139         u8 reg;
 140
 141         /* Trigger hard reset. */
 142         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 143         if (status)
 144                 return status;
 145         reg |= IXGBE_PE_BIT1;
 146         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 147         if (status)
 148                 return status;
 149
 150         status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
 151         if (status)
 152                 return status;
 153         reg &= ~IXGBE_PE_BIT1;
 154         status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
 155         if (status)
 156                 return status;
 157
 158         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 159         if (status)
 160                 return status;
 161         reg &= ~IXGBE_PE_BIT1;
 162         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 163         if (status)
 164                 return status;
 165
 166         usleep_range(IXGBE_CS4227_RESET_HOLD, IXGBE_CS4227_RESET_HOLD + 100);
 167
 168         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 169         if (status)
 170                 return status;
 171         reg |= IXGBE_PE_BIT1;
 172         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 173         if (status)
 174                 return status;
 175
 176         /* Wait for the reset to complete. */
 177         msleep(IXGBE_CS4227_RESET_DELAY);
 178         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 179                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
 180                                            &value);
 181                 if (!status && value == IXGBE_CS4227_EEPROM_LOAD_OK)
 182                         break;
 183                 msleep(IXGBE_CS4227_CHECK_DELAY);
 184         }
 185         if (retry == IXGBE_CS4227_RETRIES) {
 186                 hw_err(hw, "CS4227 reset did not complete\n");
 187                 return IXGBE_ERR_PHY;
 188         }
 189
 190         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
 191         if (status || !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
 192                 hw_err(hw, "CS4227 EEPROM did not load successfully\n");
 193                 return IXGBE_ERR_PHY;
 194         }
 195
 196         return 0;
 197 }
 198
 199 /**
 200  * ixgbe_check_cs4227 - Check CS4227 and reset as needed
 201  * @hw: pointer to hardware structure
 202  */
 203 static void ixgbe_check_cs4227(struct ixgbe_hw *hw)
 204 {
 205         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 206         s32 status;
 207         u16 value;
 208         u8 retry;
 209
 210         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 211                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 212                 if (status) {
 213                         hw_err(hw, "semaphore failed with %d\n", status);
 214                         msleep(IXGBE_CS4227_CHECK_DELAY);
 215                         continue;
 216                 }
 217
 218                 /* Get status of reset flow. */
 219                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 220                 if (!status && value == IXGBE_CS4227_RESET_COMPLETE)
 221                         goto out;
 222
 223                 if (status || value != IXGBE_CS4227_RESET_PENDING)
 224                         break;
 225
 226                 /* Reset is pending. Wait and check again. */
 227                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 228                 msleep(IXGBE_CS4227_CHECK_DELAY);
 229         }
 230         /* If still pending, assume other instance failed. */
 231         if (retry == IXGBE_CS4227_RETRIES) {
 232                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 233                 if (status) {
 234                         hw_err(hw, "semaphore failed with %d\n", status);
 235                         return;
 236                 }
 237         }
 238
 239         /* Reset the CS4227. */
 240         status = ixgbe_reset_cs4227(hw);
 241         if (status) {
 242                 hw_err(hw, "CS4227 reset failed: %d", status);
 243                 goto out;
 244         }
 245
 246         /* Reset takes so long, temporarily release semaphore in case the
 247          * other driver instance is waiting for the reset indication.
 248          */
 249         ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 250                            IXGBE_CS4227_RESET_PENDING);
 251         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 252         usleep_range(10000, 12000);
 253         status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 254         if (status) {
 255                 hw_err(hw, "semaphore failed with %d", status);
 256                 return;
 257         }
 258
 259         /* Record completion for next time. */
 260         status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 261                                     IXGBE_CS4227_RESET_COMPLETE);
 262
 263 out:
 264         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 265         msleep(hw->eeprom.semaphore_delay);
 266 }
 267
 268 /** ixgbe_identify_phy_x550em - Get PHY type based on device id
 269  *  @hw: pointer to hardware structure
 270  *
 271  *  Returns error code
 272  */
 273 static s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
 274 {
 275         switch (hw->device_id) {
 276         case IXGBE_DEV_ID_X550EM_A_SFP:
 277                 if (hw->bus.lan_id)
 278                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
 279                 else
 280                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
 281                 return ixgbe_identify_module_generic(hw);
 282         case IXGBE_DEV_ID_X550EM_X_SFP:
 283                 /* set up for CS4227 usage */
 284                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
 285                 ixgbe_setup_mux_ctl(hw);
 286                 ixgbe_check_cs4227(hw);
 287                 /* Fallthrough */
 288         case IXGBE_DEV_ID_X550EM_A_SFP_N:
 289                 return ixgbe_identify_module_generic(hw);
 290         case IXGBE_DEV_ID_X550EM_X_KX4:
 291                 hw->phy.type = ixgbe_phy_x550em_kx4;
 292                 break;
 293         case IXGBE_DEV_ID_X550EM_X_KR:
 294         case IXGBE_DEV_ID_X550EM_A_KR:
 295         case IXGBE_DEV_ID_X550EM_A_KR_L:
 296                 hw->phy.type = ixgbe_phy_x550em_kr;
 297                 break;
 298         case IXGBE_DEV_ID_X550EM_A_10G_T:
 299                 if (hw->bus.lan_id)
 300                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
 301                 else
 302                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
 303                 /* Fallthrough */
 304         case IXGBE_DEV_ID_X550EM_X_1G_T:
 305         case IXGBE_DEV_ID_X550EM_X_10G_T:
 306                 return ixgbe_identify_phy_generic(hw);
 307         default:
 308                 break;
 309         }
 310         return 0;
 311 }
 312
 313 static s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 314                                      u32 device_type, u16 *phy_data)
 315 {
 316         return IXGBE_NOT_IMPLEMENTED;
 317 }
 318
 319 static s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 320                                       u32 device_type, u16 phy_data)
 321 {
 322         return IXGBE_NOT_IMPLEMENTED;
 323 }
 324
 325 /** ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
 326  *  @hw: pointer to hardware structure
 327  *
 328  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 329  *  ixgbe_hw struct in order to set up EEPROM access.
 330  **/
 331 static s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
 332 {
 333         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 334         u32 eec;
 335         u16 eeprom_size;
 336
 337         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 338                 eeprom->semaphore_delay = 10;
 339                 eeprom->type = ixgbe_flash;
 340
 341                 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
 342                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 343                                     IXGBE_EEC_SIZE_SHIFT);
 344                 eeprom->word_size = BIT(eeprom_size +
 345                                         IXGBE_EEPROM_WORD_SIZE_SHIFT);
 346
 347                 hw_dbg(hw, "Eeprom params: type = %d, size = %d\n",
 348                        eeprom->type, eeprom->word_size);
 349         }
 350
 351         return 0;
 352 }
 353
 354 /**
 355  * ixgbe_iosf_wait - Wait for IOSF command completion
 356  * @hw: pointer to hardware structure
 357  * @ctrl: pointer to location to receive final IOSF control value
 358  *
 359  * Return: failing status on timeout
 360  *
 361  * Note: ctrl can be NULL if the IOSF control register value is not needed
 362  */
 363 static s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
 364 {
 365         u32 i, command;
 366
 367         /* Check every 10 usec to see if the address cycle completed.
 368          * The SB IOSF BUSY bit will clear when the operation is
 369          * complete.
 370          */
 371         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 372                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 373                 if (!(command & IXGBE_SB_IOSF_CTRL_BUSY))
 374                         break;
 375                 udelay(10);
 376         }
 377         if (ctrl)
 378                 *ctrl = command;
 379         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 380                 hw_dbg(hw, "IOSF wait timed out\n");
 381                 return IXGBE_ERR_PHY;
 382         }
 383
 384         return 0;
 385 }
 386
 387 /** ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the
 388  *  IOSF device
 389  *  @hw: pointer to hardware structure
 390  *  @reg_addr: 32 bit PHY register to write
 391  *  @device_type: 3 bit device type
 392  *  @phy_data: Pointer to read data from the register
 393  **/
 394 static s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 395                                        u32 device_type, u32 *data)
 396 {
 397         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
 398         u32 command, error;
 399         s32 ret;
 400
 401         ret = hw->mac.ops.acquire_swfw_sync(hw, gssr);
 402         if (ret)
 403                 return ret;
 404
 405         ret = ixgbe_iosf_wait(hw, NULL);
 406         if (ret)
 407                 goto out;
 408
 409         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 410                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 411
 412         /* Write IOSF control register */
 413         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 414
 415         ret = ixgbe_iosf_wait(hw, &command);
 416
 417         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 418                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 419                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 420                 hw_dbg(hw, "Failed to read, error %x\n", error);
 421                 return IXGBE_ERR_PHY;
 422         }
 423
 424         if (!ret)
 425                 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
 426
 427 out:
 428         hw->mac.ops.release_swfw_sync(hw, gssr);
 429         return ret;
 430 }
 431
 432 /**
 433  * ixgbe_get_phy_token - Get the token for shared PHY access
 434  * @hw: Pointer to hardware structure
 435  */
 436 static s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)
 437 {
 438         struct ixgbe_hic_phy_token_req token_cmd;
 439         s32 status;
 440
 441         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
 442         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
 443         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
 444         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
 445         token_cmd.port_number = hw->bus.lan_id;
 446         token_cmd.command_type = FW_PHY_TOKEN_REQ;
 447         token_cmd.pad = 0;
 448         status = ixgbe_host_interface_command(hw, &token_cmd, sizeof(token_cmd),
 449                                               IXGBE_HI_COMMAND_TIMEOUT,
 450                                               true);
 451         if (status)
 452                 return status;
 453         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
 454                 return 0;
 455         if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY)
 456                 return IXGBE_ERR_FW_RESP_INVALID;
 457
 458         return IXGBE_ERR_TOKEN_RETRY;
 459 }
 460
 461 /**
 462  * ixgbe_put_phy_token - Put the token for shared PHY access
 463  * @hw: Pointer to hardware structure
 464  */
 465 static s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)
 466 {
 467         struct ixgbe_hic_phy_token_req token_cmd;
 468         s32 status;
 469
 470         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
 471         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
 472         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
 473         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
 474         token_cmd.port_number = hw->bus.lan_id;
 475         token_cmd.command_type = FW_PHY_TOKEN_REL;
 476         token_cmd.pad = 0;
 477         status = ixgbe_host_interface_command(hw, &token_cmd, sizeof(token_cmd),
 478                                               IXGBE_HI_COMMAND_TIMEOUT,
 479                                               true);
 480         if (status)
 481                 return status;
 482         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
 483                 return 0;
 484         return IXGBE_ERR_FW_RESP_INVALID;
 485 }
 486
 487 /**
 488  *  ixgbe_write_iosf_sb_reg_x550a - Write to IOSF PHY register
 489  *  @hw: pointer to hardware structure
 490  *  @reg_addr: 32 bit PHY register to write
 491  *  @device_type: 3 bit device type
 492  *  @data: Data to write to the register
 493  **/
 494 static s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
 495                                          __always_unused u32 device_type,
 496                                          u32 data)
 497 {
 498         struct ixgbe_hic_internal_phy_req write_cmd;
 499
 500         memset(&write_cmd, 0, sizeof(write_cmd));
 501         write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
 502         write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
 503         write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
 504         write_cmd.port_number = hw->bus.lan_id;
 505         write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
 506         write_cmd.address = cpu_to_be16(reg_addr);
 507         write_cmd.write_data = cpu_to_be32(data);
 508
 509         return ixgbe_host_interface_command(hw, &write_cmd, sizeof(write_cmd),
 510                                             IXGBE_HI_COMMAND_TIMEOUT, false);
 511 }
 512
 513 /**
 514  *  ixgbe_read_iosf_sb_reg_x550a - Read from IOSF PHY register
 515  *  @hw: pointer to hardware structure
 516  *  @reg_addr: 32 bit PHY register to write
 517  *  @device_type: 3 bit device type
 518  *  @data: Pointer to read data from the register
 519  **/
 520 static s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
 521                                         __always_unused u32 device_type,
 522                                         u32 *data)
 523 {
 524         union {
 525                 struct ixgbe_hic_internal_phy_req cmd;
 526                 struct ixgbe_hic_internal_phy_resp rsp;
 527         } hic;
 528         s32 status;
 529
 530         memset(&hic, 0, sizeof(hic));
 531         hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
 532         hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
 533         hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
 534         hic.cmd.port_number = hw->bus.lan_id;
 535         hic.cmd.command_type = FW_INT_PHY_REQ_READ;
 536         hic.cmd.address = cpu_to_be16(reg_addr);
 537
 538         status = ixgbe_host_interface_command(hw, &hic.cmd, sizeof(hic.cmd),
 539                                               IXGBE_HI_COMMAND_TIMEOUT, true);
 540
 541         /* Extract the register value from the response. */
 542         *data = be32_to_cpu(hic.rsp.read_data);
 543
 544         return status;
 545 }
 546
 547 /** ixgbe_read_ee_hostif_data_X550 - Read EEPROM word using a host interface
 548  *  command assuming that the semaphore is already obtained.
 549  *  @hw: pointer to hardware structure
 550  *  @offset: offset of  word in the EEPROM to read
 551  *  @data: word read from the EEPROM
 552  *
 553  *  Reads a 16 bit word from the EEPROM using the hostif.
 554  **/
 555 static s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
 556                                           u16 *data)
 557 {
 558         s32 status;
 559         struct ixgbe_hic_read_shadow_ram buffer;
 560
 561         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
 562         buffer.hdr.req.buf_lenh = 0;
 563         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
 564         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
 565
 566         /* convert offset from words to bytes */
 567         buffer.address = cpu_to_be32(offset * 2);
 568         /* one word */
 569         buffer.length = cpu_to_be16(sizeof(u16));
 570
 571         status = ixgbe_host_interface_command(hw, &buffer, sizeof(buffer),
 572                                               IXGBE_HI_COMMAND_TIMEOUT, false);
 573         if (status)
 574                 return status;
 575
 576         *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
 577                                           FW_NVM_DATA_OFFSET);
 578
 579         return 0;
 580 }
 581
 582 /** ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
 583  *  @hw: pointer to hardware structure
 584  *  @offset: offset of  word in the EEPROM to read
 585  *  @words: number of words
 586  *  @data: word(s) read from the EEPROM
 587  *
 588  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
 589  **/
 590 static s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
 591                                             u16 offset, u16 words, u16 *data)
 592 {
 593         struct ixgbe_hic_read_shadow_ram buffer;
 594         u32 current_word = 0;
 595         u16 words_to_read;
 596         s32 status;
 597         u32 i;
 598
 599         /* Take semaphore for the entire operation. */
 600         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 601         if (status) {
 602                 hw_dbg(hw, "EEPROM read buffer - semaphore failed\n");
 603                 return status;
 604         }
 605
 606         while (words) {
 607                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
 608                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
 609                 else
 610                         words_to_read = words;
 611
 612                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
 613                 buffer.hdr.req.buf_lenh = 0;
 614                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
 615                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
 616
 617                 /* convert offset from words to bytes */
 618                 buffer.address = cpu_to_be32((offset + current_word) * 2);
 619                 buffer.length = cpu_to_be16(words_to_read * 2);
 620
 621                 status = ixgbe_host_interface_command(hw, &buffer,
 622                                                       sizeof(buffer),
 623                                                       IXGBE_HI_COMMAND_TIMEOUT,
 624                                                       false);
 625                 if (status) {
 626                         hw_dbg(hw, "Host interface command failed\n");
 627                         goto out;
 628                 }
 629
 630                 for (i = 0; i < words_to_read; i++) {
 631                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
 632                                   2 * i;
 633                         u32 value = IXGBE_READ_REG(hw, reg);
 634
 635                         data[current_word] = (u16)(value & 0xffff);
 636                         current_word++;
 637                         i++;
 638                         if (i < words_to_read) {
 639                                 value >>= 16;
 640                                 data[current_word] = (u16)(value & 0xffff);
 641                                 current_word++;
 642                         }
 643                 }
 644                 words -= words_to_read;
 645         }
 646
 647 out:
 648         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 649         return status;
 650 }
 651
 652 /** ixgbe_checksum_ptr_x550 - Checksum one pointer region
 653  *  @hw: pointer to hardware structure
 654  *  @ptr: pointer offset in eeprom
 655  *  @size: size of section pointed by ptr, if 0 first word will be used as size
 656  *  @csum: address of checksum to update
 657  *
 658  *  Returns error status for any failure
 659  **/
 660 static s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
 661                                    u16 size, u16 *csum, u16 *buffer,
 662                                    u32 buffer_size)
 663 {
 664         u16 buf[256];
 665         s32 status;
 666         u16 length, bufsz, i, start;
 667         u16 *local_buffer;
 668
 669         bufsz = sizeof(buf) / sizeof(buf[0]);
 670
 671         /* Read a chunk at the pointer location */
 672         if (!buffer) {
 673                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
 674                 if (status) {
 675                         hw_dbg(hw, "Failed to read EEPROM image\n");
 676                         return status;
 677                 }
 678                 local_buffer = buf;
 679         } else {
 680                 if (buffer_size < ptr)
 681                         return  IXGBE_ERR_PARAM;
 682                 local_buffer = &buffer[ptr];
 683         }
 684
 685         if (size) {
 686                 start = 0;
 687                 length = size;
 688         } else {
 689                 start = 1;
 690                 length = local_buffer[0];
 691
 692                 /* Skip pointer section if length is invalid. */
 693                 if (length == 0xFFFF || length == 0 ||
 694                     (ptr + length) >= hw->eeprom.word_size)
 695                         return 0;
 696         }
 697
 698         if (buffer && ((u32)start + (u32)length > buffer_size))
 699                 return IXGBE_ERR_PARAM;
 700
 701         for (i = start; length; i++, length--) {
 702                 if (i == bufsz && !buffer) {
 703                         ptr += bufsz;
 704                         i = 0;
 705                         if (length < bufsz)
 706                                 bufsz = length;
 707
 708                         /* Read a chunk at the pointer location */
 709                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
 710                                                                   bufsz, buf);
 711                         if (status) {
 712                                 hw_dbg(hw, "Failed to read EEPROM image\n");
 713                                 return status;
 714                         }
 715                 }
 716                 *csum += local_buffer[i];
 717         }
 718         return 0;
 719 }
 720
 721 /** ixgbe_calc_checksum_X550 - Calculates and returns the checksum
 722  *  @hw: pointer to hardware structure
 723  *  @buffer: pointer to buffer containing calculated checksum
 724  *  @buffer_size: size of buffer
 725  *
 726  *  Returns a negative error code on error, or the 16-bit checksum
 727  **/
 728 static s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer,
 729                                     u32 buffer_size)
 730 {
 731         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
 732         u16 *local_buffer;
 733         s32 status;
 734         u16 checksum = 0;
 735         u16 pointer, i, size;
 736
 737         hw->eeprom.ops.init_params(hw);
 738
 739         if (!buffer) {
 740                 /* Read pointer area */
 741                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
 742                                                 IXGBE_EEPROM_LAST_WORD + 1,
 743                                                 eeprom_ptrs);
 744                 if (status) {
 745                         hw_dbg(hw, "Failed to read EEPROM image\n");
 746                         return status;
 747                 }
 748                 local_buffer = eeprom_ptrs;
 749         } else {
 750                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
 751                         return IXGBE_ERR_PARAM;
 752                 local_buffer = buffer;
 753         }
 754
 755         /* For X550 hardware include 0x0-0x41 in the checksum, skip the
 756          * checksum word itself
 757          */
 758         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
 759                 if (i != IXGBE_EEPROM_CHECKSUM)
 760                         checksum += local_buffer[i];
 761
 762         /* Include all data from pointers 0x3, 0x6-0xE.  This excludes the
 763          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
 764          */
 765         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
 766                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
 767                         continue;
 768
 769                 pointer = local_buffer[i];
 770
 771                 /* Skip pointer section if the pointer is invalid. */
 772                 if (pointer == 0xFFFF || pointer == 0 ||
 773                     pointer >= hw->eeprom.word_size)
 774                         continue;
 775
 776                 switch (i) {
 777                 case IXGBE_PCIE_GENERAL_PTR:
 778                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
 779                         break;
 780                 case IXGBE_PCIE_CONFIG0_PTR:
 781                 case IXGBE_PCIE_CONFIG1_PTR:
 782                         size = IXGBE_PCIE_CONFIG_SIZE;
 783                         break;
 784                 default:
 785                         size = 0;
 786                         break;
 787                 }
 788
 789                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
 790                                                  buffer, buffer_size);
 791                 if (status)
 792                         return status;
 793         }
 794
 795         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
 796
 797         return (s32)checksum;
 798 }
 799
 800 /** ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
 801  *  @hw: pointer to hardware structure
 802  *
 803  *  Returns a negative error code on error, or the 16-bit checksum
 804  **/
 805 static s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
 806 {
 807         return ixgbe_calc_checksum_X550(hw, NULL, 0);
 808 }
 809
 810 /** ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
 811  *  @hw: pointer to hardware structure
 812  *  @offset: offset of  word in the EEPROM to read
 813  *  @data: word read from the EEPROM
 814  *
 815  *   Reads a 16 bit word from the EEPROM using the hostif.
 816  **/
 817 static s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data)
 818 {
 819         s32 status = 0;
 820
 821         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) {
 822                 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
 823                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 824         } else {
 825                 status = IXGBE_ERR_SWFW_SYNC;
 826         }
 827
 828         return status;
 829 }
 830
 831 /** ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
 832  *  @hw: pointer to hardware structure
 833  *  @checksum_val: calculated checksum
 834  *
 835  *  Performs checksum calculation and validates the EEPROM checksum.  If the
 836  *  caller does not need checksum_val, the value can be NULL.
 837  **/
 838 static s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw,
 839                                                u16 *checksum_val)
 840 {
 841         s32 status;
 842         u16 checksum;
 843         u16 read_checksum = 0;
 844
 845         /* Read the first word from the EEPROM. If this times out or fails, do
 846          * not continue or we could be in for a very long wait while every
 847          * EEPROM read fails
 848          */
 849         status = hw->eeprom.ops.read(hw, 0, &checksum);
 850         if (status) {
 851                 hw_dbg(hw, "EEPROM read failed\n");
 852                 return status;
 853         }
 854
 855         status = hw->eeprom.ops.calc_checksum(hw);
 856         if (status < 0)
 857                 return status;
 858
 859         checksum = (u16)(status & 0xffff);
 860
 861         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
 862                                            &read_checksum);
 863         if (status)
 864                 return status;
 865
 866         /* Verify read checksum from EEPROM is the same as
 867          * calculated checksum
 868          */
 869         if (read_checksum != checksum) {
 870                 status = IXGBE_ERR_EEPROM_CHECKSUM;
 871                 hw_dbg(hw, "Invalid EEPROM checksum");
 872         }
 873
 874         /* If the user cares, return the calculated checksum */
 875         if (checksum_val)
 876                 *checksum_val = checksum;
 877
 878         return status;
 879 }
 880
 881 /** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
 882  *  @hw: pointer to hardware structure
 883  *  @offset: offset of  word in the EEPROM to write
 884  *  @data: word write to the EEPROM
 885  *
 886  *  Write a 16 bit word to the EEPROM using the hostif.
 887  **/
 888 static s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
 889                                            u16 data)
 890 {
 891         s32 status;
 892         struct ixgbe_hic_write_shadow_ram buffer;
 893
 894         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
 895         buffer.hdr.req.buf_lenh = 0;
 896         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
 897         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
 898
 899         /* one word */
 900         buffer.length = cpu_to_be16(sizeof(u16));
 901         buffer.data = data;
 902         buffer.address = cpu_to_be32(offset * 2);
 903
 904         status = ixgbe_host_interface_command(hw, &buffer, sizeof(buffer),
 905                                               IXGBE_HI_COMMAND_TIMEOUT, false);
 906         return status;
 907 }
 908
 909 /** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
 910  *  @hw: pointer to hardware structure
 911  *  @offset: offset of  word in the EEPROM to write
 912  *  @data: word write to the EEPROM
 913  *
 914  *  Write a 16 bit word to the EEPROM using the hostif.
 915  **/
 916 static s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 data)
 917 {
 918         s32 status = 0;
 919
 920         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) {
 921                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
 922                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 923         } else {
 924                 hw_dbg(hw, "write ee hostif failed to get semaphore");
 925                 status = IXGBE_ERR_SWFW_SYNC;
 926         }
 927
 928         return status;
 929 }
 930
 931 /** ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
 932  *  @hw: pointer to hardware structure
 933  *
 934  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
 935  **/
 936 static s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
 937 {
 938         s32 status = 0;
 939         union ixgbe_hic_hdr2 buffer;
 940
 941         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
 942         buffer.req.buf_lenh = 0;
 943         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
 944         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
 945
 946         status = ixgbe_host_interface_command(hw, &buffer, sizeof(buffer),
 947                                               IXGBE_HI_COMMAND_TIMEOUT, false);
 948         return status;
 949 }
 950
 951 /**
 952  * ixgbe_get_bus_info_X550em - Set PCI bus info
 953  * @hw: pointer to hardware structure
 954  *
 955  * Sets bus link width and speed to unknown because X550em is
 956  * not a PCI device.
 957  **/
 958 static s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
 959 {
 960         hw->bus.type  = ixgbe_bus_type_internal;
 961         hw->bus.width = ixgbe_bus_width_unknown;
 962         hw->bus.speed = ixgbe_bus_speed_unknown;
 963
 964         hw->mac.ops.set_lan_id(hw);
 965
 966         return 0;
 967 }
 968
 969 /** ixgbe_disable_rx_x550 - Disable RX unit
 970  *
 971  *  Enables the Rx DMA unit for x550
 972  **/
 973 static void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
 974 {
 975         u32 rxctrl, pfdtxgswc;
 976         s32 status;
 977         struct ixgbe_hic_disable_rxen fw_cmd;
 978
 979         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
 980         if (rxctrl & IXGBE_RXCTRL_RXEN) {
 981                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
 982                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
 983                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
 984                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
 985                         hw->mac.set_lben = true;
 986                 } else {
 987                         hw->mac.set_lben = false;
 988                 }
 989
 990                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
 991                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
 992                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
 993                 fw_cmd.port_number = hw->bus.lan_id;
 994
 995                 status = ixgbe_host_interface_command(hw, &fw_cmd,
 996                                         sizeof(struct ixgbe_hic_disable_rxen),
 997                                         IXGBE_HI_COMMAND_TIMEOUT, true);
 998
 999                 /* If we fail - disable RX using register write */
1000                 if (status) {
1001                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1002                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
1003                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
1004                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
1005                         }
1006                 }
1007         }
1008 }
1009
1010 /** ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
1011  *  @hw: pointer to hardware structure
1012  *
1013  *  After writing EEPROM to shadow RAM using EEWR register, software calculates
1014  *  checksum and updates the EEPROM and instructs the hardware to update
1015  *  the flash.
1016  **/
1017 static s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
1018 {
1019         s32 status;
1020         u16 checksum = 0;
1021
1022         /* Read the first word from the EEPROM. If this times out or fails, do
1023          * not continue or we could be in for a very long wait while every
1024          * EEPROM read fails
1025          */
1026         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
1027         if (status) {
1028                 hw_dbg(hw, "EEPROM read failed\n");
1029                 return status;
1030         }
1031
1032         status = ixgbe_calc_eeprom_checksum_X550(hw);
1033         if (status < 0)
1034                 return status;
1035
1036         checksum = (u16)(status & 0xffff);
1037
1038         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
1039                                             checksum);
1040         if (status)
1041                 return status;
1042
1043         status = ixgbe_update_flash_X550(hw);
1044
1045         return status;
1046 }
1047
1048 /** ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
1049  *  @hw: pointer to hardware structure
1050  *  @offset: offset of  word in the EEPROM to write
1051  *  @words: number of words
1052  *  @data: word(s) write to the EEPROM
1053  *
1054  *
1055  *  Write a 16 bit word(s) to the EEPROM using the hostif.
1056  **/
1057 static s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1058                                              u16 offset, u16 words,
1059                                              u16 *data)
1060 {
1061         s32 status = 0;
1062         u32 i = 0;
1063
1064         /* Take semaphore for the entire operation. */
1065         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1066         if (status) {
1067                 hw_dbg(hw, "EEPROM write buffer - semaphore failed\n");
1068                 return status;
1069         }
1070
1071         for (i = 0; i < words; i++) {
1072                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
1073                                                          data[i]);
1074                 if (status) {
1075                         hw_dbg(hw, "Eeprom buffered write failed\n");
1076                         break;
1077                 }
1078         }
1079
1080         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1081
1082         return status;
1083 }
1084
1085 /** ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the
1086  *  IOSF device
1087  *
1088  *  @hw: pointer to hardware structure
1089  *  @reg_addr: 32 bit PHY register to write
1090  *  @device_type: 3 bit device type
1091  *  @data: Data to write to the register
1092  **/
1093 static s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1094                                         u32 device_type, u32 data)
1095 {
1096         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1097         u32 command, error;
1098         s32 ret;
1099
1100         ret = hw->mac.ops.acquire_swfw_sync(hw, gssr);
1101         if (ret)
1102                 return ret;
1103
1104         ret = ixgbe_iosf_wait(hw, NULL);
1105         if (ret)
1106                 goto out;
1107
1108         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1109                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1110
1111         /* Write IOSF control register */
1112         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1113
1114         /* Write IOSF data register */
1115         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
1116
1117         ret = ixgbe_iosf_wait(hw, &command);
1118
1119         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1120                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1121                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1122                 hw_dbg(hw, "Failed to write, error %x\n", error);
1123                 return IXGBE_ERR_PHY;
1124         }
1125
1126 out:
1127         hw->mac.ops.release_swfw_sync(hw, gssr);
1128         return ret;
1129 }
1130
1131 /** ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
1132  *  @hw: pointer to hardware structure
1133  *  @speed: the link speed to force
1134  *
1135  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
1136  *  internal and external PHY at a specific speed, without autonegotiation.
1137  **/
1138 static s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1139 {
1140         s32 status;
1141         u32 reg_val;
1142
1143         /* Disable AN and force speed to 10G Serial. */
1144         status = ixgbe_read_iosf_sb_reg_x550(hw,
1145                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1146                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1147         if (status)
1148                 return status;
1149
1150         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1151         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1152
1153         /* Select forced link speed for internal PHY. */
1154         switch (*speed) {
1155         case IXGBE_LINK_SPEED_10GB_FULL:
1156                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1157                 break;
1158         case IXGBE_LINK_SPEED_1GB_FULL:
1159                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1160                 break;
1161         default:
1162                 /* Other link speeds are not supported by internal KR PHY. */
1163                 return IXGBE_ERR_LINK_SETUP;
1164         }
1165
1166         status = ixgbe_write_iosf_sb_reg_x550(hw,
1167                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1168                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1169         if (status)
1170                 return status;
1171
1172         /* Disable training protocol FSM. */
1173         status = ixgbe_read_iosf_sb_reg_x550(hw,
1174                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1175                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1176         if (status)
1177                 return status;
1178
1179         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1180         status = ixgbe_write_iosf_sb_reg_x550(hw,
1181                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1182                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1183         if (status)
1184                 return status;
1185
1186         /* Disable Flex from training TXFFE. */
1187         status = ixgbe_read_iosf_sb_reg_x550(hw,
1188                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1189                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1190         if (status)
1191                 return status;
1192
1193         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1194         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1195         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1196         status = ixgbe_write_iosf_sb_reg_x550(hw,
1197                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1198                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1199         if (status)
1200                 return status;
1201
1202         status = ixgbe_read_iosf_sb_reg_x550(hw,
1203                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1204                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1205         if (status)
1206                 return status;
1207
1208         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1209         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1210         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1211         status = ixgbe_write_iosf_sb_reg_x550(hw,
1212                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1213                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1214         if (status)
1215                 return status;
1216
1217         /* Enable override for coefficients. */
1218         status = ixgbe_read_iosf_sb_reg_x550(hw,
1219                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1220                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1221         if (status)
1222                 return status;
1223
1224         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1225         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1226         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1227         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1228         status = ixgbe_write_iosf_sb_reg_x550(hw,
1229                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1230                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1231         if (status)
1232                 return status;
1233
1234         /* Toggle port SW reset by AN reset. */
1235         status = ixgbe_read_iosf_sb_reg_x550(hw,
1236                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1237                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1238         if (status)
1239                 return status;
1240
1241         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1242         status = ixgbe_write_iosf_sb_reg_x550(hw,
1243                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1244                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1245
1246         return status;
1247 }
1248
1249 /**
1250  *  ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1251  *  @hw: pointer to hardware structure
1252  *  @linear: true if SFP module is linear
1253  */
1254 static s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1255 {
1256         switch (hw->phy.sfp_type) {
1257         case ixgbe_sfp_type_not_present:
1258                 return IXGBE_ERR_SFP_NOT_PRESENT;
1259         case ixgbe_sfp_type_da_cu_core0:
1260         case ixgbe_sfp_type_da_cu_core1:
1261                 *linear = true;
1262                 break;
1263         case ixgbe_sfp_type_srlr_core0:
1264         case ixgbe_sfp_type_srlr_core1:
1265         case ixgbe_sfp_type_da_act_lmt_core0:
1266         case ixgbe_sfp_type_da_act_lmt_core1:
1267         case ixgbe_sfp_type_1g_sx_core0:
1268         case ixgbe_sfp_type_1g_sx_core1:
1269         case ixgbe_sfp_type_1g_lx_core0:
1270         case ixgbe_sfp_type_1g_lx_core1:
1271                 *linear = false;
1272                 break;
1273         case ixgbe_sfp_type_unknown:
1274         case ixgbe_sfp_type_1g_cu_core0:
1275         case ixgbe_sfp_type_1g_cu_core1:
1276         default:
1277                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1278         }
1279
1280         return 0;
1281 }
1282
1283 /**
1284  *  ixgbe_setup_mac_link_sfp_x550em - Configure the KR PHY for SFP.
1285  *  @hw: pointer to hardware structure
1286  *
1287  *  Configures the extern PHY and the integrated KR PHY for SFP support.
1288  */
1289 static s32
1290 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
1291                                 ixgbe_link_speed speed,
1292                                 __always_unused bool autoneg_wait_to_complete)
1293 {
1294         s32 status;
1295         u16 slice, value;
1296         bool setup_linear = false;
1297
1298         /* Check if SFP module is supported and linear */
1299         status = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1300
1301         /* If no SFP module present, then return success. Return success since
1302          * there is no reason to configure CS4227 and SFP not present error is
1303          * not accepted in the setup MAC link flow.
1304          */
1305         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
1306                 return 0;
1307
1308         if (status)
1309                 return status;
1310
1311         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
1312                 /* Configure CS4227 LINE side to 10G SR. */
1313                 slice = IXGBE_CS4227_LINE_SPARE22_MSB + (hw->bus.lan_id << 12);
1314                 value = IXGBE_CS4227_SPEED_10G;
1315                 status = ixgbe_write_i2c_combined_generic(hw, IXGBE_CS4227,
1316                                                           slice, value);
1317                 if (status)
1318                         goto i2c_err;
1319
1320                 slice = IXGBE_CS4227_LINE_SPARE24_LSB + (hw->bus.lan_id << 12);
1321                 value = (IXGBE_CS4227_EDC_MODE_SR << 1) | 1;
1322                 status = ixgbe_write_i2c_combined_generic(hw, IXGBE_CS4227,
1323                                                           slice, value);
1324                 if (status)
1325                         goto i2c_err;
1326
1327                 /* Configure CS4227 for HOST connection rate then type. */
1328                 slice = IXGBE_CS4227_HOST_SPARE22_MSB + (hw->bus.lan_id << 12);
1329                 value = speed & IXGBE_LINK_SPEED_10GB_FULL ?
1330                         IXGBE_CS4227_SPEED_10G : IXGBE_CS4227_SPEED_1G;
1331                 status = ixgbe_write_i2c_combined_generic(hw, IXGBE_CS4227,
1332                                                           slice, value);
1333                 if (status)
1334                         goto i2c_err;
1335
1336                 slice = IXGBE_CS4227_HOST_SPARE24_LSB + (hw->bus.lan_id << 12);
1337                 if (setup_linear)
1338                         value = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 1;
1339                 else
1340                         value = (IXGBE_CS4227_EDC_MODE_SR << 1) | 1;
1341                 status = ixgbe_write_i2c_combined_generic(hw, IXGBE_CS4227,
1342                                                           slice, value);
1343                 if (status)
1344                         goto i2c_err;
1345
1346                 /* Setup XFI internal link. */
1347                 status = ixgbe_setup_ixfi_x550em(hw, &speed);
1348                 if (status) {
1349                         hw_dbg(hw, "setup_ixfi failed with %d\n", status);
1350                         return status;
1351                 }
1352         } else {
1353                 /* Configure internal PHY for KR/KX. */
1354                 status = ixgbe_setup_kr_speed_x550em(hw, speed);
1355                 if (status) {
1356                         hw_dbg(hw, "setup_kr_speed failed with %d\n", status);
1357                         return status;
1358                 }
1359
1360                 /* Configure CS4227 LINE side to proper mode. */
1361                 slice = IXGBE_CS4227_LINE_SPARE24_LSB + (hw->bus.lan_id << 12);
1362                 if (setup_linear)
1363                         value = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 1;
1364                 else
1365                         value = (IXGBE_CS4227_EDC_MODE_SR << 1) | 1;
1366                 status = ixgbe_write_i2c_combined_generic(hw, IXGBE_CS4227,
1367                                                           slice, value);
1368                 if (status)
1369                         goto i2c_err;
1370         }
1371
1372         return 0;
1373
1374 i2c_err:
1375         hw_dbg(hw, "combined i2c access failed with %d\n", status);
1376         return status;
1377 }
1378
1379 /**
1380  * ixgbe_setup_mac_link_sfp_n - Setup internal PHY for native SFP
1381  * @hw: pointer to hardware structure
1382  *
1383  * Configure the the integrated PHY for native SFP support.
1384  */
1385 static s32
1386 ixgbe_setup_mac_link_sfp_n(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1387                            __always_unused bool autoneg_wait_to_complete)
1388 {
1389         bool setup_linear = false;
1390         u32 reg_phy_int;
1391         s32 rc;
1392
1393         /* Check if SFP module is supported and linear */
1394         rc = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1395
1396         /* If no SFP module present, then return success. Return success since
1397          * SFP not present error is not excepted in the setup MAC link flow.
1398          */
1399         if (rc == IXGBE_ERR_SFP_NOT_PRESENT)
1400                 return 0;
1401
1402         if (!rc)
1403                 return rc;
1404
1405         /* Configure internal PHY for native SFI */
1406         rc = hw->mac.ops.read_iosf_sb_reg(hw,
1407                                           IXGBE_KRM_AN_CNTL_8(hw->bus.lan_id),
1408                                           IXGBE_SB_IOSF_TARGET_KR_PHY,
1409                                           &reg_phy_int);
1410         if (rc)
1411                 return rc;
1412
1413         if (setup_linear) {
1414                 reg_phy_int &= ~IXGBE_KRM_AN_CNTL_8_LIMITING;
1415                 reg_phy_int |= IXGBE_KRM_AN_CNTL_8_LINEAR;
1416         } else {
1417                 reg_phy_int |= IXGBE_KRM_AN_CNTL_8_LIMITING;
1418                 reg_phy_int &= ~IXGBE_KRM_AN_CNTL_8_LINEAR;
1419         }
1420
1421         rc = hw->mac.ops.write_iosf_sb_reg(hw,
1422                                            IXGBE_KRM_AN_CNTL_8(hw->bus.lan_id),
1423                                            IXGBE_SB_IOSF_TARGET_KR_PHY,
1424                                            reg_phy_int);
1425         if (rc)
1426                 return rc;
1427
1428         /* Setup XFI/SFI internal link */
1429         return ixgbe_setup_ixfi_x550em(hw, &speed);
1430 }
1431
1432 /**
1433  * ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
1434  * @hw: pointer to hardware structure
1435  *
1436  * Configure the the integrated PHY for SFP support.
1437  */
1438 static s32
1439 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1440                                __always_unused bool autoneg_wait_to_complete)
1441 {
1442         u32 reg_slice, slice_offset;
1443         bool setup_linear = false;
1444         u16 reg_phy_ext;
1445         s32 rc;
1446
1447         /* Check if SFP module is supported and linear */
1448         rc = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1449
1450         /* If no SFP module present, then return success. Return success since
1451          * SFP not present error is not excepted in the setup MAC link flow.
1452          */
1453         if (rc == IXGBE_ERR_SFP_NOT_PRESENT)
1454                 return 0;
1455
1456         if (!rc)
1457                 return rc;
1458
1459         /* Configure internal PHY for KR/KX. */
1460         ixgbe_setup_kr_speed_x550em(hw, speed);
1461
1462         if (!hw->phy.mdio.prtad || hw->phy.mdio.prtad == 0xFFFF)
1463                 return IXGBE_ERR_PHY_ADDR_INVALID;
1464
1465         /* Get external PHY device id */
1466         rc = hw->phy.ops.read_reg(hw, IXGBE_CS4227_GLOBAL_ID_MSB,
1467                                   IXGBE_MDIO_ZERO_DEV_TYPE, &reg_phy_ext);
1468         if (rc)
1469                 return rc;
1470
1471         /* When configuring quad port CS4223, the MAC instance is part
1472          * of the slice offset.
1473          */
1474         if (reg_phy_ext == IXGBE_CS4223_PHY_ID)
1475                 slice_offset = (hw->bus.lan_id +
1476                                 (hw->bus.instance_id << 1)) << 12;
1477         else
1478                 slice_offset = hw->bus.lan_id << 12;
1479
1480         /* Configure CS4227/CS4223 LINE side to proper mode. */
1481         reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset;
1482         if (setup_linear)
1483                 reg_phy_ext = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 1;
1484         else
1485                 reg_phy_ext = (IXGBE_CS4227_EDC_MODE_SR << 1) | 1;
1486         return hw->phy.ops.write_reg(hw, reg_slice, IXGBE_MDIO_ZERO_DEV_TYPE,
1487                                      reg_phy_ext);
1488 }
1489
1490 /**
1491  * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
1492  * @hw: pointer to hardware structure
1493  * @speed: new link speed
1494  * @autoneg_wait_to_complete: true when waiting for completion is needed
1495  *
1496  * Setup internal/external PHY link speed based on link speed, then set
1497  * external PHY auto advertised link speed.
1498  *
1499  * Returns error status for any failure
1500  **/
1501 static s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
1502                                          ixgbe_link_speed speed,
1503                                          bool autoneg_wait)
1504 {
1505         s32 status;
1506         ixgbe_link_speed force_speed;
1507
1508         /* Setup internal/external PHY link speed to iXFI (10G), unless
1509          * only 1G is auto advertised then setup KX link.
1510          */
1511         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1512                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
1513         else
1514                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
1515
1516         /* If internal link mode is XFI, then setup XFI internal link. */
1517         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
1518                 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
1519
1520                 if (status)
1521                         return status;
1522         }
1523
1524         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1525 }
1526
1527 /** ixgbe_check_link_t_X550em - Determine link and speed status
1528   * @hw: pointer to hardware structure
1529   * @speed: pointer to link speed
1530   * @link_up: true when link is up
1531   * @link_up_wait_to_complete: bool used to wait for link up or not
1532   *
1533   * Check that both the MAC and X557 external PHY have link.
1534   **/
1535 static s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw,
1536                                      ixgbe_link_speed *speed,
1537                                      bool *link_up,
1538                                      bool link_up_wait_to_complete)
1539 {
1540         u32 status;
1541         u16 autoneg_status;
1542
1543         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
1544                 return IXGBE_ERR_CONFIG;
1545
1546         status = ixgbe_check_mac_link_generic(hw, speed, link_up,
1547                                               link_up_wait_to_complete);
1548
1549         /* If check link fails or MAC link is not up, then return */
1550         if (status || !(*link_up))
1551                 return status;
1552
1553          /* MAC link is up, so check external PHY link.
1554           * Read this twice back to back to indicate current status.
1555           */
1556         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1557                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1558                                       &autoneg_status);
1559         if (status)
1560                 return status;
1561
1562         /* If external PHY link is not up, then indicate link not up */
1563         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
1564                 *link_up = false;
1565
1566         return 0;
1567 }
1568
1569 /**
1570  * ixgbe_setup_sgmii - Set up link for sgmii
1571  * @hw: pointer to hardware structure
1572  */
1573 static s32
1574 ixgbe_setup_sgmii(struct ixgbe_hw *hw, __always_unused ixgbe_link_speed speed,
1575                   __always_unused bool autoneg_wait_to_complete)
1576 {
1577         struct ixgbe_mac_info *mac = &hw->mac;
1578         u32 lval, sval;
1579         s32 rc;
1580
1581         rc = mac->ops.read_iosf_sb_reg(hw,
1582                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1583                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1584         if (rc)
1585                 return rc;
1586
1587         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1588         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1589         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1590         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1591         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1592         rc = mac->ops.write_iosf_sb_reg(hw,
1593                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1594                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1595         if (rc)
1596                 return rc;
1597
1598         rc = mac->ops.read_iosf_sb_reg(hw,
1599                                        IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1600                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1601         if (rc)
1602                 return rc;
1603
1604         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1605         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1606         rc = mac->ops.write_iosf_sb_reg(hw,
1607                                         IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1608                                         IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1609         if (rc)
1610                 return rc;
1611
1612         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1613         rc = mac->ops.write_iosf_sb_reg(hw,
1614                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1615                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1616
1617         return rc;
1618 }
1619
1620 /** ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1621  *  @hw: pointer to hardware structure
1622  **/
1623 static void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1624 {
1625         struct ixgbe_mac_info *mac = &hw->mac;
1626
1627         mac->ops.setup_fc = ixgbe_setup_fc_x550em;
1628
1629         switch (mac->ops.get_media_type(hw)) {
1630         case ixgbe_media_type_fiber:
1631                 /* CS4227 does not support autoneg, so disable the laser control
1632                  * functions for SFP+ fiber
1633                  */
1634                 mac->ops.disable_tx_laser = NULL;
1635                 mac->ops.enable_tx_laser = NULL;
1636                 mac->ops.flap_tx_laser = NULL;
1637                 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1638                 switch (hw->device_id) {
1639                 case IXGBE_DEV_ID_X550EM_A_SFP_N:
1640                         mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_n;
1641                         break;
1642                 case IXGBE_DEV_ID_X550EM_A_SFP:
1643                         mac->ops.setup_mac_link =
1644                                                 ixgbe_setup_mac_link_sfp_x550a;
1645                         break;
1646                 default:
1647                         mac->ops.setup_mac_link =
1648                                                 ixgbe_setup_mac_link_sfp_x550em;
1649                         break;
1650                 }
1651                 mac->ops.set_rate_select_speed =
1652                                         ixgbe_set_soft_rate_select_speed;
1653                 break;
1654         case ixgbe_media_type_copper:
1655                 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1656                 mac->ops.setup_fc = ixgbe_setup_fc_generic;
1657                 mac->ops.check_link = ixgbe_check_link_t_X550em;
1658                 return;
1659         case ixgbe_media_type_backplane:
1660                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
1661                     hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L)
1662                         mac->ops.setup_link = ixgbe_setup_sgmii;
1663                 break;
1664         default:
1665                 break;
1666         }
1667 }
1668
1669 /** ixgbe_setup_sfp_modules_X550em - Setup SFP module
1670  * @hw: pointer to hardware structure
1671  */
1672 static s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1673 {
1674         s32 status;
1675         bool linear;
1676
1677         /* Check if SFP module is supported */
1678         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1679         if (status)
1680                 return status;
1681
1682         ixgbe_init_mac_link_ops_X550em(hw);
1683         hw->phy.ops.reset = NULL;
1684
1685         return 0;
1686 }
1687
1688 /** ixgbe_get_link_capabilities_x550em - Determines link capabilities
1689  * @hw: pointer to hardware structure
1690  * @speed: pointer to link speed
1691  * @autoneg: true when autoneg or autotry is enabled
1692  **/
1693 static s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1694                                               ixgbe_link_speed *speed,
1695                                               bool *autoneg)
1696 {
1697         /* SFP */
1698         if (hw->phy.media_type == ixgbe_media_type_fiber) {
1699                 /* CS4227 SFP must not enable auto-negotiation */
1700                 *autoneg = false;
1701
1702                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1703                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) {
1704                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1705                         return 0;
1706                 }
1707
1708                 /* Link capabilities are based on SFP */
1709                 if (hw->phy.multispeed_fiber)
1710                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1711                                  IXGBE_LINK_SPEED_1GB_FULL;
1712                 else
1713                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1714         } else {
1715                 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1716                          IXGBE_LINK_SPEED_1GB_FULL;
1717                 *autoneg = true;
1718         }
1719         return 0;
1720 }
1721
1722 /**
1723  * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1724  * @hw: pointer to hardware structure
1725  * @lsc: pointer to boolean flag which indicates whether external Base T
1726  *       PHY interrupt is lsc
1727  *
1728  * Determime if external Base T PHY interrupt cause is high temperature
1729  * failure alarm or link status change.
1730  *
1731  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1732  * failure alarm, else return PHY access status.
1733  **/
1734 static s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1735 {
1736         u32 status;
1737         u16 reg;
1738
1739         *lsc = false;
1740
1741         /* Vendor alarm triggered */
1742         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1743                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1744                                       &reg);
1745
1746         if (status || !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1747                 return status;
1748
1749         /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1750         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1751                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1752                                       &reg);
1753
1754         if (status || !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1755                                 IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1756                 return status;
1757
1758         /* Global alarm triggered */
1759         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1760                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1761                                       &reg);
1762
1763         if (status)
1764                 return status;
1765
1766         /* If high temperature failure, then return over temp error and exit */
1767         if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1768                 /* power down the PHY in case the PHY FW didn't already */
1769                 ixgbe_set_copper_phy_power(hw, false);
1770                 return IXGBE_ERR_OVERTEMP;
1771         }
1772         if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
1773                 /*  device fault alarm triggered */
1774                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
1775                                           IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1776                                           &reg);
1777                 if (status)
1778                         return status;
1779
1780                 /* if device fault was due to high temp alarm handle and exit */
1781                 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
1782                         /* power down the PHY in case the PHY FW didn't */
1783                         ixgbe_set_copper_phy_power(hw, false);
1784                         return IXGBE_ERR_OVERTEMP;
1785                 }
1786         }
1787
1788         /* Vendor alarm 2 triggered */
1789         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1790                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1791
1792         if (status || !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1793                 return status;
1794
1795         /* link connect/disconnect event occurred */
1796         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1797                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1798
1799         if (status)
1800                 return status;
1801
1802         /* Indicate LSC */
1803         if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
1804                 *lsc = true;
1805
1806         return 0;
1807 }
1808
1809 /**
1810  * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1811  * @hw: pointer to hardware structure
1812  *
1813  * Enable link status change and temperature failure alarm for the external
1814  * Base T PHY
1815  *
1816  * Returns PHY access status
1817  **/
1818 static s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1819 {
1820         u32 status;
1821         u16 reg;
1822         bool lsc;
1823
1824         /* Clear interrupt flags */
1825         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1826
1827         /* Enable link status change alarm */
1828         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1829                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1830         if (status)
1831                 return status;
1832
1833         reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
1834
1835         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1836                                        IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
1837         if (status)
1838                 return status;
1839
1840         /* Enable high temperature failure and global fault alarms */
1841         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1842                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1843                                       &reg);
1844         if (status)
1845                 return status;
1846
1847         reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
1848                 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
1849
1850         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1851                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1852                                        reg);
1853         if (status)
1854                 return status;
1855
1856         /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
1857         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1858                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1859                                       &reg);
1860         if (status)
1861                 return status;
1862
1863         reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1864                 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
1865
1866         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1867                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1868                                        reg);
1869         if (status)
1870                 return status;
1871
1872         /* Enable chip-wide vendor alarm */
1873         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1874                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1875                                       &reg);
1876         if (status)
1877                 return status;
1878
1879         reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
1880
1881         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1882                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1883                                        reg);
1884
1885         return status;
1886 }
1887
1888 /**
1889  * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
1890  * @hw: pointer to hardware structure
1891  *
1892  * Handle external Base T PHY interrupt. If high temperature
1893  * failure alarm then return error, else if link status change
1894  * then setup internal/external PHY link
1895  *
1896  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1897  * failure alarm, else return PHY access status.
1898  **/
1899 static s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1900 {
1901         struct ixgbe_phy_info *phy = &hw->phy;
1902         bool lsc;
1903         u32 status;
1904
1905         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1906         if (status)
1907                 return status;
1908
1909         if (lsc && phy->ops.setup_internal_link)
1910                 return phy->ops.setup_internal_link(hw);
1911
1912         return 0;
1913 }
1914
1915 /**
1916  * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
1917  * @hw: pointer to hardware structure
1918  * @speed: link speed
1919  *
1920  * Configures the integrated KR PHY.
1921  **/
1922 static s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
1923                                        ixgbe_link_speed speed)
1924 {
1925         s32 status;
1926         u32 reg_val;
1927
1928         status = hw->mac.ops.read_iosf_sb_reg(hw,
1929                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1930                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1931         if (status)
1932                 return status;
1933
1934         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1935         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ |
1936                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC);
1937         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1938                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1939
1940         /* Advertise 10G support. */
1941         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1942                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1943
1944         /* Advertise 1G support. */
1945         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
1946                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1947
1948         /* Restart auto-negotiation. */
1949         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1950         status = hw->mac.ops.write_iosf_sb_reg(hw,
1951                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1952                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1953
1954         return status;
1955 }
1956
1957 /** ixgbe_setup_kx4_x550em - Configure the KX4 PHY.
1958  *  @hw: pointer to hardware structure
1959  *
1960  *   Configures the integrated KX4 PHY.
1961  **/
1962 static s32 ixgbe_setup_kx4_x550em(struct ixgbe_hw *hw)
1963 {
1964         s32 status;
1965         u32 reg_val;
1966
1967         status = hw->mac.ops.read_iosf_sb_reg(hw, IXGBE_KX4_LINK_CNTL_1,
1968                                               IXGBE_SB_IOSF_TARGET_KX4_PCS0 +
1969                                               hw->bus.lan_id, &reg_val);
1970         if (status)
1971                 return status;
1972
1973         reg_val &= ~(IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4 |
1974                      IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX);
1975
1976         reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_ENABLE;
1977
1978         /* Advertise 10G support. */
1979         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1980                 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4;
1981
1982         /* Advertise 1G support. */
1983         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1984                 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX;
1985
1986         /* Restart auto-negotiation. */
1987         reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART;
1988         status = hw->mac.ops.write_iosf_sb_reg(hw, IXGBE_KX4_LINK_CNTL_1,
1989                                                IXGBE_SB_IOSF_TARGET_KX4_PCS0 +
1990                                                hw->bus.lan_id, reg_val);
1991
1992         return status;
1993 }
1994
1995 /**
1996  * ixgbe_setup_kr_x550em - Configure the KR PHY
1997  * @hw: pointer to hardware structure
1998  *
1999  * Configures the integrated KR PHY for X550EM_x.
2000  **/
2001 static s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
2002 {
2003         if (hw->mac.type != ixgbe_mac_X550EM_x)
2004                 return 0;
2005
2006         return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
2007 }
2008
2009 /** ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
2010  *  @hw: address of hardware structure
2011  *  @link_up: address of boolean to indicate link status
2012  *
2013  *  Returns error code if unable to get link status.
2014  **/
2015 static s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
2016 {
2017         u32 ret;
2018         u16 autoneg_status;
2019
2020         *link_up = false;
2021
2022         /* read this twice back to back to indicate current status */
2023         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2024                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2025                                    &autoneg_status);
2026         if (ret)
2027                 return ret;
2028
2029         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2030                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2031                                    &autoneg_status);
2032         if (ret)
2033                 return ret;
2034
2035         *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
2036
2037         return 0;
2038 }
2039
2040 /** ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
2041  *  @hw: point to hardware structure
2042  *
2043  *  Configures the link between the integrated KR PHY and the external X557 PHY
2044  *  The driver will call this function when it gets a link status change
2045  *  interrupt from the X557 PHY. This function configures the link speed
2046  *  between the PHYs to match the link speed of the BASE-T link.
2047  *
2048  * A return of a non-zero value indicates an error, and the base driver should
2049  * not report link up.
2050  **/
2051 static s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
2052 {
2053         ixgbe_link_speed force_speed;
2054         bool link_up;
2055         u32 status;
2056         u16 speed;
2057
2058         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2059                 return IXGBE_ERR_CONFIG;
2060
2061         if (hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE) {
2062                 speed = IXGBE_LINK_SPEED_10GB_FULL |
2063                         IXGBE_LINK_SPEED_1GB_FULL;
2064                 return ixgbe_setup_kr_speed_x550em(hw, speed);
2065         }
2066
2067         /* If link is not up, then there is no setup necessary so return  */
2068         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2069         if (status)
2070                 return status;
2071
2072         if (!link_up)
2073                 return 0;
2074
2075         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2076                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2077                                       &speed);
2078         if (status)
2079                 return status;
2080
2081         /* If link is not still up, then no setup is necessary so return */
2082         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2083         if (status)
2084                 return status;
2085
2086         if (!link_up)
2087                 return 0;
2088
2089         /* clear everything but the speed and duplex bits */
2090         speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
2091
2092         switch (speed) {
2093         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
2094                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
2095                 break;
2096         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
2097                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
2098                 break;
2099         default:
2100                 /* Internal PHY does not support anything else */
2101                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
2102         }
2103
2104         return ixgbe_setup_ixfi_x550em(hw, &force_speed);
2105 }
2106
2107 /** ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
2108  *  @hw: pointer to hardware structure
2109  **/
2110 static s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
2111 {
2112         s32 status;
2113
2114         status = ixgbe_reset_phy_generic(hw);
2115
2116         if (status)
2117                 return status;
2118
2119         /* Configure Link Status Alarm and Temperature Threshold interrupts */
2120         return ixgbe_enable_lasi_ext_t_x550em(hw);
2121 }
2122
2123 /**
2124  *  ixgbe_led_on_t_x550em - Turns on the software controllable LEDs.
2125  *  @hw: pointer to hardware structure
2126  *  @led_idx: led number to turn on
2127  **/
2128 s32 ixgbe_led_on_t_x550em(struct ixgbe_hw *hw, u32 led_idx)
2129 {
2130         u16 phy_data;
2131
2132         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
2133                 return IXGBE_ERR_PARAM;
2134
2135         /* To turn on the LED, set mode to ON. */
2136         hw->phy.ops.read_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
2137                              IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
2138         phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
2139         hw->phy.ops.write_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
2140                               IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
2141
2142         return 0;
2143 }
2144
2145 /**
2146  *  ixgbe_led_off_t_x550em - Turns off the software controllable LEDs.
2147  *  @hw: pointer to hardware structure
2148  *  @led_idx: led number to turn off
2149  **/
2150 s32 ixgbe_led_off_t_x550em(struct ixgbe_hw *hw, u32 led_idx)
2151 {
2152         u16 phy_data;
2153
2154         if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
2155                 return IXGBE_ERR_PARAM;
2156
2157         /* To turn on the LED, set mode to ON. */
2158         hw->phy.ops.read_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
2159                              IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data);
2160         phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
2161         hw->phy.ops.write_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
2162                               IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data);
2163
2164         return 0;
2165 }
2166
2167 /** ixgbe_get_lcd_x550em - Determine lowest common denominator
2168  *  @hw: pointer to hardware structure
2169  *  @lcd_speed: pointer to lowest common link speed
2170  *
2171  *  Determine lowest common link speed with link partner.
2172  **/
2173 static s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw,
2174                                   ixgbe_link_speed *lcd_speed)
2175 {
2176         u16 an_lp_status;
2177         s32 status;
2178         u16 word = hw->eeprom.ctrl_word_3;
2179
2180         *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
2181
2182         status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
2183                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2184                                       &an_lp_status);
2185         if (status)
2186                 return status;
2187
2188         /* If link partner advertised 1G, return 1G */
2189         if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
2190                 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
2191                 return status;
2192         }
2193
2194         /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
2195         if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
2196             (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
2197                 return status;
2198
2199         /* Link partner not capable of lower speeds, return 10G */
2200         *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
2201         return status;
2202 }
2203
2204 /**
2205  * ixgbe_setup_fc_x550em - Set up flow control
2206  * @hw: pointer to hardware structure
2207  */
2208 static s32 ixgbe_setup_fc_x550em(struct ixgbe_hw *hw)
2209 {
2210         bool pause, asm_dir;
2211         u32 reg_val;
2212         s32 rc;
2213
2214         /* Validate the requested mode */
2215         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
2216                 hw_err(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
2217                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
2218         }
2219
2220         /* 10gig parts do not have a word in the EEPROM to determine the
2221          * default flow control setting, so we explicitly set it to full.
2222          */
2223         if (hw->fc.requested_mode == ixgbe_fc_default)
2224                 hw->fc.requested_mode = ixgbe_fc_full;
2225
2226         /* Determine PAUSE and ASM_DIR bits. */
2227         switch (hw->fc.requested_mode) {
2228         case ixgbe_fc_none:
2229                 pause = false;
2230                 asm_dir = false;
2231                 break;
2232         case ixgbe_fc_tx_pause:
2233                 pause = false;
2234                 asm_dir = true;
2235                 break;
2236         case ixgbe_fc_rx_pause:
2237                 /* Rx Flow control is enabled and Tx Flow control is
2238                  * disabled by software override. Since there really
2239                  * isn't a way to advertise that we are capable of RX
2240                  * Pause ONLY, we will advertise that we support both
2241                  * symmetric and asymmetric Rx PAUSE, as such we fall
2242                  * through to the fc_full statement.  Later, we will
2243                  * disable the adapter's ability to send PAUSE frames.
2244                  */
2245                 /* Fallthrough */
2246         case ixgbe_fc_full:
2247                 pause = true;
2248                 asm_dir = true;
2249                 break;
2250         default:
2251                 hw_err(hw, "Flow control param set incorrectly\n");
2252                 return IXGBE_ERR_CONFIG;
2253         }
2254
2255         if (hw->device_id != IXGBE_DEV_ID_X550EM_X_KR &&
2256             hw->device_id != IXGBE_DEV_ID_X550EM_A_KR &&
2257             hw->device_id != IXGBE_DEV_ID_X550EM_A_KR_L)
2258                 return 0;
2259
2260         rc = hw->mac.ops.read_iosf_sb_reg(hw,
2261                                           IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2262                                           IXGBE_SB_IOSF_TARGET_KR_PHY,
2263                                           &reg_val);
2264         if (rc)
2265                 return rc;
2266
2267         reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
2268                      IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
2269         if (pause)
2270                 reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
2271         if (asm_dir)
2272                 reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
2273         rc = hw->mac.ops.write_iosf_sb_reg(hw,
2274                                            IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2275                                            IXGBE_SB_IOSF_TARGET_KR_PHY,
2276                                            reg_val);
2277
2278         /* This device does not fully support AN. */
2279         hw->fc.disable_fc_autoneg = true;
2280
2281         return rc;
2282 }
2283
2284 /** ixgbe_enter_lplu_x550em - Transition to low power states
2285  *  @hw: pointer to hardware structure
2286  *
2287  *  Configures Low Power Link Up on transition to low power states
2288  *  (from D0 to non-D0). Link is required to enter LPLU so avoid resetting
2289  *  the X557 PHY immediately prior to entering LPLU.
2290  **/
2291 static s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
2292 {
2293         u16 an_10g_cntl_reg, autoneg_reg, speed;
2294         s32 status;
2295         ixgbe_link_speed lcd_speed;
2296         u32 save_autoneg;
2297         bool link_up;
2298
2299         /* If blocked by MNG FW, then don't restart AN */
2300         if (ixgbe_check_reset_blocked(hw))
2301                 return 0;
2302
2303         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2304         if (status)
2305                 return status;
2306
2307         status = hw->eeprom.ops.read(hw, NVM_INIT_CTRL_3,
2308                                      &hw->eeprom.ctrl_word_3);
2309         if (status)
2310                 return status;
2311
2312         /* If link is down, LPLU disabled in NVM, WoL disabled, or
2313          * manageability disabled, then force link down by entering
2314          * low power mode.
2315          */
2316         if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
2317             !(hw->wol_enabled || ixgbe_mng_present(hw)))
2318                 return ixgbe_set_copper_phy_power(hw, false);
2319
2320         /* Determine LCD */
2321         status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
2322         if (status)
2323                 return status;
2324
2325         /* If no valid LCD link speed, then force link down and exit. */
2326         if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
2327                 return ixgbe_set_copper_phy_power(hw, false);
2328
2329         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2330                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2331                                       &speed);
2332         if (status)
2333                 return status;
2334
2335         /* If no link now, speed is invalid so take link down */
2336         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2337         if (status)
2338                 return ixgbe_set_copper_phy_power(hw, false);
2339
2340         /* clear everything but the speed bits */
2341         speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
2342
2343         /* If current speed is already LCD, then exit. */
2344         if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
2345              (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
2346             ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
2347              (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
2348                 return status;
2349
2350         /* Clear AN completed indication */
2351         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
2352                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2353                                       &autoneg_reg);
2354         if (status)
2355                 return status;
2356
2357         status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
2358                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2359                                       &an_10g_cntl_reg);
2360         if (status)
2361                 return status;
2362
2363         status = hw->phy.ops.read_reg(hw,
2364                                       IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
2365                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2366                                       &autoneg_reg);
2367         if (status)
2368                 return status;
2369
2370         save_autoneg = hw->phy.autoneg_advertised;
2371
2372         /* Setup link at least common link speed */
2373         status = hw->mac.ops.setup_link(hw, lcd_speed, false);
2374
2375         /* restore autoneg from before setting lplu speed */
2376         hw->phy.autoneg_advertised = save_autoneg;
2377
2378         return status;
2379 }
2380
2381 /**
2382  * ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register
2383  * @hw: pointer to hardware structure
2384  *
2385  * Read NW_MNG_IF_SEL register and save field values.
2386  */
2387 static void ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw)
2388 {
2389         /* Save NW management interface connected on board. This is used
2390          * to determine internal PHY mode.
2391          */
2392         hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
2393
2394         /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set
2395          * PHY address. This register field was has only been used for X552.
2396          */
2397         if (hw->mac.type == ixgbe_mac_x550em_a &&
2398             hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) {
2399                 hw->phy.mdio.prtad = (hw->phy.nw_mng_if_sel &
2400                                       IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
2401                                      IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
2402         }
2403 }
2404
2405 /** ixgbe_init_phy_ops_X550em - PHY/SFP specific init
2406  *  @hw: pointer to hardware structure
2407  *
2408  *  Initialize any function pointers that were not able to be
2409  *  set during init_shared_code because the PHY/SFP type was
2410  *  not known.  Perform the SFP init if necessary.
2411  **/
2412 static s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
2413 {
2414         struct ixgbe_phy_info *phy = &hw->phy;
2415         s32 ret_val;
2416
2417         hw->mac.ops.set_lan_id(hw);
2418
2419         ixgbe_read_mng_if_sel_x550em(hw);
2420
2421         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
2422                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2423                 ixgbe_setup_mux_ctl(hw);
2424         }
2425
2426         /* Identify the PHY or SFP module */
2427         ret_val = phy->ops.identify(hw);
2428
2429         /* Setup function pointers based on detected hardware */
2430         ixgbe_init_mac_link_ops_X550em(hw);
2431         if (phy->sfp_type != ixgbe_sfp_type_unknown)
2432                 phy->ops.reset = NULL;
2433
2434         /* Set functions pointers based on phy type */
2435         switch (hw->phy.type) {
2436         case ixgbe_phy_x550em_kx4:
2437                 phy->ops.setup_link = ixgbe_setup_kx4_x550em;
2438                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2439                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2440                 break;
2441         case ixgbe_phy_x550em_kr:
2442                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
2443                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2444                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2445                 break;
2446         case ixgbe_phy_x550em_ext_t:
2447                 /* Save NW management interface connected on board. This is used
2448                  * to determine internal PHY mode
2449                  */
2450                 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
2451
2452                 /* If internal link mode is XFI, then setup iXFI internal link,
2453                  * else setup KR now.
2454                  */
2455                 phy->ops.setup_internal_link =
2456                                               ixgbe_setup_internal_phy_t_x550em;
2457
2458                 /* setup SW LPLU only for first revision */
2459                 if (hw->mac.type == ixgbe_mac_X550EM_x &&
2460                     !(IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0)) &
2461                       IXGBE_FUSES0_REV_MASK))
2462                         phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
2463
2464                 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
2465                 phy->ops.reset = ixgbe_reset_phy_t_X550em;
2466                 break;
2467         default:
2468                 break;
2469         }
2470
2471         return ret_val;
2472 }
2473
2474 /** ixgbe_get_media_type_X550em - Get media type
2475  *  @hw: pointer to hardware structure
2476  *
2477  *  Returns the media type (fiber, copper, backplane)
2478  *
2479  */
2480 static enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
2481 {
2482         enum ixgbe_media_type media_type;
2483
2484         /* Detect if there is a copper PHY attached. */
2485         switch (hw->device_id) {
2486         case IXGBE_DEV_ID_X550EM_A_SGMII:
2487         case IXGBE_DEV_ID_X550EM_A_SGMII_L:
2488                 hw->phy.type = ixgbe_phy_sgmii;
2489                 /* Fallthrough */
2490         case IXGBE_DEV_ID_X550EM_X_KR:
2491         case IXGBE_DEV_ID_X550EM_X_KX4:
2492         case IXGBE_DEV_ID_X550EM_A_KR:
2493         case IXGBE_DEV_ID_X550EM_A_KR_L:
2494                 media_type = ixgbe_media_type_backplane;
2495                 break;
2496         case IXGBE_DEV_ID_X550EM_X_SFP:
2497         case IXGBE_DEV_ID_X550EM_A_SFP:
2498         case IXGBE_DEV_ID_X550EM_A_SFP_N:
2499                 media_type = ixgbe_media_type_fiber;
2500                 break;
2501         case IXGBE_DEV_ID_X550EM_X_1G_T:
2502         case IXGBE_DEV_ID_X550EM_X_10G_T:
2503         case IXGBE_DEV_ID_X550EM_A_10G_T:
2504                 media_type = ixgbe_media_type_copper;
2505                 break;
2506         default:
2507                 media_type = ixgbe_media_type_unknown;
2508                 break;
2509         }
2510         return media_type;
2511 }
2512
2513 /** ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
2514  ** @hw: pointer to hardware structure
2515  **/
2516 static s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
2517 {
2518         s32 status;
2519         u16 reg;
2520
2521         status = hw->phy.ops.read_reg(hw,
2522                                       IXGBE_MDIO_TX_VENDOR_ALARMS_3,
2523                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2524                                       &reg);
2525         if (status)
2526                 return status;
2527
2528         /* If PHY FW reset completed bit is set then this is the first
2529          * SW instance after a power on so the PHY FW must be un-stalled.
2530          */
2531         if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
2532                 status = hw->phy.ops.read_reg(hw,
2533                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2534                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2535                                         &reg);
2536                 if (status)
2537                         return status;
2538
2539                 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
2540
2541                 status = hw->phy.ops.write_reg(hw,
2542                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2543                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2544                                         reg);
2545                 if (status)
2546                         return status;
2547         }
2548
2549         return status;
2550 }
2551
2552 /**
2553  * ixgbe_set_mdio_speed - Set MDIO clock speed
2554  * @hw: pointer to hardware structure
2555  */
2556 static void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
2557 {
2558         u32 hlreg0;
2559
2560         switch (hw->device_id) {
2561         case IXGBE_DEV_ID_X550EM_X_10G_T:
2562         case IXGBE_DEV_ID_X550EM_A_SGMII:
2563         case IXGBE_DEV_ID_X550EM_A_SGMII_L:
2564         case IXGBE_DEV_ID_X550EM_A_10G_T:
2565         case IXGBE_DEV_ID_X550EM_A_SFP:
2566                 /* Config MDIO clock speed before the first MDIO PHY access */
2567                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2568                 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
2569                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2570                 break;
2571         default:
2572                 break;
2573         }
2574 }
2575
2576 /**  ixgbe_reset_hw_X550em - Perform hardware reset
2577  **  @hw: pointer to hardware structure
2578  **
2579  **  Resets the hardware by resetting the transmit and receive units, masks
2580  **  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
2581  **  reset.
2582  **/
2583 static s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
2584 {
2585         ixgbe_link_speed link_speed;
2586         s32 status;
2587         u32 ctrl = 0;
2588         u32 i;
2589         bool link_up = false;
2590
2591         /* Call adapter stop to disable Tx/Rx and clear interrupts */
2592         status = hw->mac.ops.stop_adapter(hw);
2593         if (status)
2594                 return status;
2595
2596         /* flush pending Tx transactions */
2597         ixgbe_clear_tx_pending(hw);
2598
2599         /* PHY ops must be identified and initialized prior to reset */
2600
2601         /* Identify PHY and related function pointers */
2602         status = hw->phy.ops.init(hw);
2603
2604         /* start the external PHY */
2605         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
2606                 status = ixgbe_init_ext_t_x550em(hw);
2607                 if (status)
2608                         return status;
2609         }
2610
2611         /* Setup SFP module if there is one present. */
2612         if (hw->phy.sfp_setup_needed) {
2613                 status = hw->mac.ops.setup_sfp(hw);
2614                 hw->phy.sfp_setup_needed = false;
2615         }
2616
2617         /* Reset PHY */
2618         if (!hw->phy.reset_disable && hw->phy.ops.reset)
2619                 hw->phy.ops.reset(hw);
2620
2621 mac_reset_top:
2622         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
2623          * If link reset is used when link is up, it might reset the PHY when
2624          * mng is using it.  If link is down or the flag to force full link
2625          * reset is set, then perform link reset.
2626          */
2627         ctrl = IXGBE_CTRL_LNK_RST;
2628
2629         if (!hw->force_full_reset) {
2630                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
2631                 if (link_up)
2632                         ctrl = IXGBE_CTRL_RST;
2633         }
2634
2635         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
2636         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
2637         IXGBE_WRITE_FLUSH(hw);
2638         usleep_range(1000, 1200);
2639
2640         /* Poll for reset bit to self-clear meaning reset is complete */
2641         for (i = 0; i < 10; i++) {
2642                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
2643                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
2644                         break;
2645                 udelay(1);
2646         }
2647
2648         if (ctrl & IXGBE_CTRL_RST_MASK) {
2649                 status = IXGBE_ERR_RESET_FAILED;
2650                 hw_dbg(hw, "Reset polling failed to complete.\n");
2651         }
2652
2653         msleep(50);
2654
2655         /* Double resets are required for recovery from certain error
2656          * clear the multicast table.  Also reset num_rar_entries to 128,
2657          * since we modify this value when programming the SAN MAC address.
2658          */
2659         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
2660                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2661                 goto mac_reset_top;
2662         }
2663
2664         /* Store the permanent mac address */
2665         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
2666
2667         /* Store MAC address from RAR0, clear receive address registers, and
2668          * clear the multicast table.  Also reset num_rar_entries to 128,
2669          * since we modify this value when programming the SAN MAC address.
2670          */
2671         hw->mac.num_rar_entries = 128;
2672         hw->mac.ops.init_rx_addrs(hw);
2673
2674         ixgbe_set_mdio_speed(hw);
2675
2676         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2677                 ixgbe_setup_mux_ctl(hw);
2678
2679         return status;
2680 }
2681
2682 /** ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype
2683  *      anti-spoofing
2684  *  @hw:  pointer to hardware structure
2685  *  @enable: enable or disable switch for Ethertype anti-spoofing
2686  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
2687  **/
2688 static void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
2689                                                    bool enable, int vf)
2690 {
2691         int vf_target_reg = vf >> 3;
2692         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
2693         u32 pfvfspoof;
2694
2695         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
2696         if (enable)
2697                 pfvfspoof |= BIT(vf_target_shift);
2698         else
2699                 pfvfspoof &= ~BIT(vf_target_shift);
2700
2701         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
2702 }
2703
2704 /** ixgbe_set_source_address_pruning_X550 - Enable/Disbale src address pruning
2705  *  @hw: pointer to hardware structure
2706  *  @enable: enable or disable source address pruning
2707  *  @pool: Rx pool to set source address pruning for
2708  **/
2709 static void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw,
2710                                                   bool enable,
2711                                                   unsigned int pool)
2712 {
2713         u64 pfflp;
2714
2715         /* max rx pool is 63 */
2716         if (pool > 63)
2717                 return;
2718
2719         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
2720         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
2721
2722         if (enable)
2723                 pfflp |= (1ULL << pool);
2724         else
2725                 pfflp &= ~(1ULL << pool);
2726
2727         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
2728         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
2729 }
2730
2731 /**
2732  * ixgbe_set_mux - Set mux for port 1 access with CS4227
2733  * @hw: pointer to hardware structure
2734  * @state: set mux if 1, clear if 0
2735  */
2736 static void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
2737 {
2738         u32 esdp;
2739
2740         if (!hw->bus.lan_id)
2741                 return;
2742         esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2743         if (state)
2744                 esdp |= IXGBE_ESDP_SDP1;
2745         else
2746                 esdp &= ~IXGBE_ESDP_SDP1;
2747         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2748         IXGBE_WRITE_FLUSH(hw);
2749 }
2750
2751 /**
2752  * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
2753  * @hw: pointer to hardware structure
2754  * @mask: Mask to specify which semaphore to acquire
2755  *
2756  * Acquires the SWFW semaphore and sets the I2C MUX
2757  */
2758 static s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2759 {
2760         s32 status;
2761
2762         status = ixgbe_acquire_swfw_sync_X540(hw, mask);
2763         if (status)
2764                 return status;
2765
2766         if (mask & IXGBE_GSSR_I2C_MASK)
2767                 ixgbe_set_mux(hw, 1);
2768
2769         return 0;
2770 }
2771
2772 /**
2773  * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
2774  * @hw: pointer to hardware structure
2775  * @mask: Mask to specify which semaphore to release
2776  *
2777  * Releases the SWFW semaphore and sets the I2C MUX
2778  */
2779 static void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2780 {
2781         if (mask & IXGBE_GSSR_I2C_MASK)
2782                 ixgbe_set_mux(hw, 0);
2783
2784         ixgbe_release_swfw_sync_X540(hw, mask);
2785 }
2786
2787 /**
2788  * ixgbe_acquire_swfw_sync_x550em_a - Acquire SWFW semaphore
2789  * @hw: pointer to hardware structure
2790  * @mask: Mask to specify which semaphore to acquire
2791  *
2792  * Acquires the SWFW semaphore and get the shared PHY token as needed
2793  */
2794 static s32 ixgbe_acquire_swfw_sync_x550em_a(struct ixgbe_hw *hw, u32 mask)
2795 {
2796         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
2797         int retries = FW_PHY_TOKEN_RETRIES;
2798         s32 status;
2799
2800         while (--retries) {
2801                 status = 0;
2802                 if (hmask)
2803                         status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
2804                 if (status)
2805                         return status;
2806                 if (!(mask & IXGBE_GSSR_TOKEN_SM))
2807                         return 0;
2808
2809                 status = ixgbe_get_phy_token(hw);
2810                 if (!status)
2811                         return 0;
2812                 if (hmask)
2813                         ixgbe_release_swfw_sync_X540(hw, hmask);
2814                 if (status != IXGBE_ERR_TOKEN_RETRY)
2815                         return status;
2816                 msleep(FW_PHY_TOKEN_DELAY);
2817         }
2818
2819         return status;
2820 }
2821
2822 /**
2823  * ixgbe_release_swfw_sync_x550em_a - Release SWFW semaphore
2824  * @hw: pointer to hardware structure
2825  * @mask: Mask to specify which semaphore to release
2826  *
2827  * Release the SWFW semaphore and puts the shared PHY token as needed
2828  */
2829 static void ixgbe_release_swfw_sync_x550em_a(struct ixgbe_hw *hw, u32 mask)
2830 {
2831         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
2832
2833         if (mask & IXGBE_GSSR_TOKEN_SM)
2834                 ixgbe_put_phy_token(hw);
2835
2836         if (hmask)
2837                 ixgbe_release_swfw_sync_X540(hw, hmask);
2838 }
2839
2840 /**
2841  * ixgbe_read_phy_reg_x550a - Reads specified PHY register
2842  * @hw: pointer to hardware structure
2843  * @reg_addr: 32 bit address of PHY register to read
2844  * @phy_data: Pointer to read data from PHY register
2845  *
2846  * Reads a value from a specified PHY register using the SWFW lock and PHY
2847  * Token. The PHY Token is needed since the MDIO is shared between to MAC
2848  * instances.
2849  */
2850 static s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
2851                                     u32 device_type, u16 *phy_data)
2852 {
2853         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
2854         s32 status;
2855
2856         if (hw->mac.ops.acquire_swfw_sync(hw, mask))
2857                 return IXGBE_ERR_SWFW_SYNC;
2858
2859         status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
2860
2861         hw->mac.ops.release_swfw_sync(hw, mask);
2862
2863         return status;
2864 }
2865
2866 /**
2867  * ixgbe_write_phy_reg_x550a - Writes specified PHY register
2868  * @hw: pointer to hardware structure
2869  * @reg_addr: 32 bit PHY register to write
2870  * @device_type: 5 bit device type
2871  * @phy_data: Data to write to the PHY register
2872  *
2873  * Writes a value to specified PHY register using the SWFW lock and PHY Token.
2874  * The PHY Token is needed since the MDIO is shared between to MAC instances.
2875  */
2876 static s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
2877                                      u32 device_type, u16 phy_data)
2878 {
2879         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
2880         s32 status;
2881
2882         if (hw->mac.ops.acquire_swfw_sync(hw, mask))
2883                 return IXGBE_ERR_SWFW_SYNC;
2884
2885         status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type, phy_data);
2886         hw->mac.ops.release_swfw_sync(hw, mask);
2887
2888         return status;
2889 }
2890
2891 #define X550_COMMON_MAC \
2892         .init_hw                        = &ixgbe_init_hw_generic, \
2893         .start_hw                       = &ixgbe_start_hw_X540, \
2894         .clear_hw_cntrs                 = &ixgbe_clear_hw_cntrs_generic, \
2895         .enable_rx_dma                  = &ixgbe_enable_rx_dma_generic, \
2896         .get_mac_addr                   = &ixgbe_get_mac_addr_generic, \
2897         .get_device_caps                = &ixgbe_get_device_caps_generic, \
2898         .stop_adapter                   = &ixgbe_stop_adapter_generic, \
2899         .set_lan_id                     = &ixgbe_set_lan_id_multi_port_pcie, \
2900         .read_analog_reg8               = NULL, \
2901         .write_analog_reg8              = NULL, \
2902         .set_rxpba                      = &ixgbe_set_rxpba_generic, \
2903         .check_link                     = &ixgbe_check_mac_link_generic, \
2904         .blink_led_start                = &ixgbe_blink_led_start_X540, \
2905         .blink_led_stop                 = &ixgbe_blink_led_stop_X540, \
2906         .set_rar                        = &ixgbe_set_rar_generic, \
2907         .clear_rar                      = &ixgbe_clear_rar_generic, \
2908         .set_vmdq                       = &ixgbe_set_vmdq_generic, \
2909         .set_vmdq_san_mac               = &ixgbe_set_vmdq_san_mac_generic, \
2910         .clear_vmdq                     = &ixgbe_clear_vmdq_generic, \
2911         .init_rx_addrs                  = &ixgbe_init_rx_addrs_generic, \
2912         .update_mc_addr_list            = &ixgbe_update_mc_addr_list_generic, \
2913         .enable_mc                      = &ixgbe_enable_mc_generic, \
2914         .disable_mc                     = &ixgbe_disable_mc_generic, \
2915         .clear_vfta                     = &ixgbe_clear_vfta_generic, \
2916         .set_vfta                       = &ixgbe_set_vfta_generic, \
2917         .fc_enable                      = &ixgbe_fc_enable_generic, \
2918         .set_fw_drv_ver                 = &ixgbe_set_fw_drv_ver_generic, \
2919         .init_uta_tables                = &ixgbe_init_uta_tables_generic, \
2920         .set_mac_anti_spoofing          = &ixgbe_set_mac_anti_spoofing, \
2921         .set_vlan_anti_spoofing         = &ixgbe_set_vlan_anti_spoofing, \
2922         .set_source_address_pruning     = \
2923                                 &ixgbe_set_source_address_pruning_X550, \
2924         .set_ethertype_anti_spoofing    = \
2925                                 &ixgbe_set_ethertype_anti_spoofing_X550, \
2926         .disable_rx_buff                = &ixgbe_disable_rx_buff_generic, \
2927         .enable_rx_buff                 = &ixgbe_enable_rx_buff_generic, \
2928         .get_thermal_sensor_data        = NULL, \
2929         .init_thermal_sensor_thresh     = NULL, \
2930         .enable_rx                      = &ixgbe_enable_rx_generic, \
2931         .disable_rx                     = &ixgbe_disable_rx_x550, \
2932
2933 static const struct ixgbe_mac_operations mac_ops_X550 = {
2934         X550_COMMON_MAC
2935         .led_on                 = ixgbe_led_on_generic,
2936         .led_off                = ixgbe_led_off_generic,
2937         .reset_hw               = &ixgbe_reset_hw_X540,
2938         .get_media_type         = &ixgbe_get_media_type_X540,
2939         .get_san_mac_addr       = &ixgbe_get_san_mac_addr_generic,
2940         .get_wwn_prefix         = &ixgbe_get_wwn_prefix_generic,
2941         .setup_link             = &ixgbe_setup_mac_link_X540,
2942         .get_link_capabilities  = &ixgbe_get_copper_link_capabilities_generic,
2943         .get_bus_info           = &ixgbe_get_bus_info_generic,
2944         .setup_sfp              = NULL,
2945         .acquire_swfw_sync      = &ixgbe_acquire_swfw_sync_X540,
2946         .release_swfw_sync      = &ixgbe_release_swfw_sync_X540,
2947         .init_swfw_sync         = &ixgbe_init_swfw_sync_X540,
2948         .prot_autoc_read        = prot_autoc_read_generic,
2949         .prot_autoc_write       = prot_autoc_write_generic,
2950         .setup_fc               = ixgbe_setup_fc_generic,
2951 };
2952
2953 static const struct ixgbe_mac_operations mac_ops_X550EM_x = {
2954         X550_COMMON_MAC
2955         .led_on                 = ixgbe_led_on_t_x550em,
2956         .led_off                = ixgbe_led_off_t_x550em,
2957         .reset_hw               = &ixgbe_reset_hw_X550em,
2958         .get_media_type         = &ixgbe_get_media_type_X550em,
2959         .get_san_mac_addr       = NULL,
2960         .get_wwn_prefix         = NULL,
2961         .setup_link             = &ixgbe_setup_mac_link_X540,
2962         .get_link_capabilities  = &ixgbe_get_link_capabilities_X550em,
2963         .get_bus_info           = &ixgbe_get_bus_info_X550em,
2964         .setup_sfp              = ixgbe_setup_sfp_modules_X550em,
2965         .acquire_swfw_sync      = &ixgbe_acquire_swfw_sync_X550em,
2966         .release_swfw_sync      = &ixgbe_release_swfw_sync_X550em,
2967         .init_swfw_sync         = &ixgbe_init_swfw_sync_X540,
2968         .setup_fc               = NULL, /* defined later */
2969         .read_iosf_sb_reg       = ixgbe_read_iosf_sb_reg_x550,
2970         .write_iosf_sb_reg      = ixgbe_write_iosf_sb_reg_x550,
2971 };
2972
2973 static struct ixgbe_mac_operations mac_ops_x550em_a = {
2974         X550_COMMON_MAC
2975         .led_on                 = ixgbe_led_on_t_x550em,
2976         .led_off                = ixgbe_led_off_t_x550em,
2977         .reset_hw               = ixgbe_reset_hw_X550em,
2978         .get_media_type         = ixgbe_get_media_type_X550em,
2979         .get_san_mac_addr       = NULL,
2980         .get_wwn_prefix         = NULL,
2981         .setup_link             = NULL, /* defined later */
2982         .get_link_capabilities  = ixgbe_get_link_capabilities_X550em,
2983         .get_bus_info           = ixgbe_get_bus_info_X550em,
2984         .setup_sfp              = ixgbe_setup_sfp_modules_X550em,
2985         .acquire_swfw_sync      = ixgbe_acquire_swfw_sync_x550em_a,
2986         .release_swfw_sync      = ixgbe_release_swfw_sync_x550em_a,
2987         .setup_fc               = ixgbe_setup_fc_x550em,
2988         .read_iosf_sb_reg       = ixgbe_read_iosf_sb_reg_x550a,
2989         .write_iosf_sb_reg      = ixgbe_write_iosf_sb_reg_x550a,
2990 };
2991
2992 #define X550_COMMON_EEP \
2993         .read                   = &ixgbe_read_ee_hostif_X550, \
2994         .read_buffer            = &ixgbe_read_ee_hostif_buffer_X550, \
2995         .write                  = &ixgbe_write_ee_hostif_X550, \
2996         .write_buffer           = &ixgbe_write_ee_hostif_buffer_X550, \
2997         .validate_checksum      = &ixgbe_validate_eeprom_checksum_X550, \
2998         .update_checksum        = &ixgbe_update_eeprom_checksum_X550, \
2999         .calc_checksum          = &ixgbe_calc_eeprom_checksum_X550, \
3000
3001 static const struct ixgbe_eeprom_operations eeprom_ops_X550 = {
3002         X550_COMMON_EEP
3003         .init_params            = &ixgbe_init_eeprom_params_X550,
3004 };
3005
3006 static const struct ixgbe_eeprom_operations eeprom_ops_X550EM_x = {
3007         X550_COMMON_EEP
3008         .init_params            = &ixgbe_init_eeprom_params_X540,
3009 };
3010
3011 #define X550_COMMON_PHY \
3012         .identify_sfp           = &ixgbe_identify_module_generic, \
3013         .reset                  = NULL, \
3014         .setup_link_speed       = &ixgbe_setup_phy_link_speed_generic, \
3015         .read_i2c_byte          = &ixgbe_read_i2c_byte_generic, \
3016         .write_i2c_byte         = &ixgbe_write_i2c_byte_generic, \
3017         .read_i2c_sff8472       = &ixgbe_read_i2c_sff8472_generic, \
3018         .read_i2c_eeprom        = &ixgbe_read_i2c_eeprom_generic, \
3019         .write_i2c_eeprom       = &ixgbe_write_i2c_eeprom_generic, \
3020         .setup_link             = &ixgbe_setup_phy_link_generic, \
3021         .set_phy_power          = NULL, \
3022         .check_overtemp         = &ixgbe_tn_check_overtemp, \
3023         .get_firmware_version   = &ixgbe_get_phy_firmware_version_generic,
3024
3025 static const struct ixgbe_phy_operations phy_ops_X550 = {
3026         X550_COMMON_PHY
3027         .init                   = NULL,
3028         .identify               = &ixgbe_identify_phy_generic,
3029         .read_reg               = &ixgbe_read_phy_reg_generic,
3030         .write_reg              = &ixgbe_write_phy_reg_generic,
3031 };
3032
3033 static const struct ixgbe_phy_operations phy_ops_X550EM_x = {
3034         X550_COMMON_PHY
3035         .init                   = &ixgbe_init_phy_ops_X550em,
3036         .identify               = &ixgbe_identify_phy_x550em,
3037         .read_reg               = &ixgbe_read_phy_reg_generic,
3038         .write_reg              = &ixgbe_write_phy_reg_generic,
3039         .read_i2c_combined      = &ixgbe_read_i2c_combined_generic,
3040         .write_i2c_combined     = &ixgbe_write_i2c_combined_generic,
3041         .read_i2c_combined_unlocked = &ixgbe_read_i2c_combined_generic_unlocked,
3042         .write_i2c_combined_unlocked =
3043                                      &ixgbe_write_i2c_combined_generic_unlocked,
3044 };
3045
3046 static const struct ixgbe_phy_operations phy_ops_x550em_a = {
3047         X550_COMMON_PHY
3048         .init                   = &ixgbe_init_phy_ops_X550em,
3049         .identify               = &ixgbe_identify_phy_x550em,
3050         .read_reg               = &ixgbe_read_phy_reg_x550a,
3051         .write_reg              = &ixgbe_write_phy_reg_x550a,
3052 };
3053
3054 static const u32 ixgbe_mvals_X550[IXGBE_MVALS_IDX_LIMIT] = {
3055         IXGBE_MVALS_INIT(X550)
3056 };
3057
3058 static const u32 ixgbe_mvals_X550EM_x[IXGBE_MVALS_IDX_LIMIT] = {
3059         IXGBE_MVALS_INIT(X550EM_x)
3060 };
3061
3062 static const u32 ixgbe_mvals_x550em_a[IXGBE_MVALS_IDX_LIMIT] = {
3063         IXGBE_MVALS_INIT(X550EM_a)
3064 };
3065
3066 const struct ixgbe_info ixgbe_X550_info = {
3067         .mac                    = ixgbe_mac_X550,
3068         .get_invariants         = &ixgbe_get_invariants_X540,
3069         .mac_ops                = &mac_ops_X550,
3070         .eeprom_ops             = &eeprom_ops_X550,
3071         .phy_ops                = &phy_ops_X550,
3072         .mbx_ops                = &mbx_ops_generic,
3073         .mvals                  = ixgbe_mvals_X550,
3074 };
3075
3076 const struct ixgbe_info ixgbe_X550EM_x_info = {
3077         .mac                    = ixgbe_mac_X550EM_x,
3078         .get_invariants         = &ixgbe_get_invariants_X550_x,
3079         .mac_ops                = &mac_ops_X550EM_x,
3080         .eeprom_ops             = &eeprom_ops_X550EM_x,
3081         .phy_ops                = &phy_ops_X550EM_x,
3082         .mbx_ops                = &mbx_ops_generic,
3083         .mvals                  = ixgbe_mvals_X550EM_x,
3084 };
3085
3086 const struct ixgbe_info ixgbe_x550em_a_info = {
3087         .mac                    = ixgbe_mac_x550em_a,
3088         .get_invariants         = &ixgbe_get_invariants_X550_x,
3089         .mac_ops                = &mac_ops_x550em_a,
3090         .eeprom_ops             = &eeprom_ops_X550EM_x,
3091         .phy_ops                = &phy_ops_x550em_a,
3092         .mbx_ops                = &mbx_ops_generic,
3093         .mvals                  = ixgbe_mvals_x550em_a,
3094 };