drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

   1 /*******************************************************************************
   2  *
   3  *  Intel 10 Gigabit PCI Express Linux driver
   4  *  Copyright(c) 1999 - 2016 Intel Corporation.
   5  *
   6  *  This program is free software; you can redistribute it and/or modify it
   7  *  under the terms and conditions of the GNU General Public License,
   8  *  version 2, as published by the Free Software Foundation.
   9  *
  10  *  This program is distributed in the hope it will be useful, but WITHOUT
  11  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  *  more details.
  14  *
  15  *  The full GNU General Public License is included in this distribution in
  16  *  the file called "COPYING".
  17  *
  18  *  Contact Information:
  19  *  Linux NICS <linux.nics@intel.com>
  20  *  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  21  *  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  22  *
  23  ******************************************************************************/
  24 #include "ixgbe_x540.h"
  25 #include "ixgbe_type.h"
  26 #include "ixgbe_common.h"
  27 #include "ixgbe_phy.h"
  28
  29 static s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *, ixgbe_link_speed);
  30 static s32 ixgbe_setup_fc_x550em(struct ixgbe_hw *);
  31
  32 static s32 ixgbe_get_invariants_X550_x(struct ixgbe_hw *hw)
  33 {
  34         struct ixgbe_mac_info *mac = &hw->mac;
  35         struct ixgbe_phy_info *phy = &hw->phy;
  36
  37         /* Start with X540 invariants, since so simular */
  38         ixgbe_get_invariants_X540(hw);
  39
  40         if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
  41                 phy->ops.set_phy_power = NULL;
  42
  43         return 0;
  44 }
  45
  46 /** ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
  47  *  @hw: pointer to hardware structure
  48  **/
  49 static void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
  50 {
  51         u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
  52
  53         if (hw->bus.lan_id) {
  54                 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
  55                 esdp |= IXGBE_ESDP_SDP1_DIR;
  56         }
  57         esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
  58         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
  59         IXGBE_WRITE_FLUSH(hw);
  60 }
  61
  62 /**
  63  * ixgbe_read_cs4227 - Read CS4227 register
  64  * @hw: pointer to hardware structure
  65  * @reg: register number to write
  66  * @value: pointer to receive value read
  67  *
  68  * Returns status code
  69  */
  70 static s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
  71 {
  72         return hw->phy.ops.read_i2c_combined_unlocked(hw, IXGBE_CS4227, reg,
  73                                                       value);
  74 }
  75
  76 /**
  77  * ixgbe_write_cs4227 - Write CS4227 register
  78  * @hw: pointer to hardware structure
  79  * @reg: register number to write
  80  * @value: value to write to register
  81  *
  82  * Returns status code
  83  */
  84 static s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
  85 {
  86         return hw->phy.ops.write_i2c_combined_unlocked(hw, IXGBE_CS4227, reg,
  87                                                        value);
  88 }
  89
  90 /**
  91  * ixgbe_read_pe - Read register from port expander
  92  * @hw: pointer to hardware structure
  93  * @reg: register number to read
  94  * @value: pointer to receive read value
  95  *
  96  * Returns status code
  97  */
  98 static s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
  99 {
 100         s32 status;
 101
 102         status = ixgbe_read_i2c_byte_generic_unlocked(hw, reg, IXGBE_PE, value);
 103         if (status)
 104                 hw_err(hw, "port expander access failed with %d\n", status);
 105         return status;
 106 }
 107
 108 /**
 109  * ixgbe_write_pe - Write register to port expander
 110  * @hw: pointer to hardware structure
 111  * @reg: register number to write
 112  * @value: value to write
 113  *
 114  * Returns status code
 115  */
 116 static s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
 117 {
 118         s32 status;
 119
 120         status = ixgbe_write_i2c_byte_generic_unlocked(hw, reg, IXGBE_PE,
 121                                                        value);
 122         if (status)
 123                 hw_err(hw, "port expander access failed with %d\n", status);
 124         return status;
 125 }
 126
 127 /**
 128  * ixgbe_reset_cs4227 - Reset CS4227 using port expander
 129  * @hw: pointer to hardware structure
 130  *
 131  * This function assumes that the caller has acquired the proper semaphore.
 132  * Returns error code
 133  */
 134 static s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
 135 {
 136         s32 status;
 137         u32 retry;
 138         u16 value;
 139         u8 reg;
 140
 141         /* Trigger hard reset. */
 142         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 143         if (status)
 144                 return status;
 145         reg |= IXGBE_PE_BIT1;
 146         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 147         if (status)
 148                 return status;
 149
 150         status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, &reg);
 151         if (status)
 152                 return status;
 153         reg &= ~IXGBE_PE_BIT1;
 154         status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
 155         if (status)
 156                 return status;
 157
 158         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 159         if (status)
 160                 return status;
 161         reg &= ~IXGBE_PE_BIT1;
 162         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 163         if (status)
 164                 return status;
 165
 166         usleep_range(IXGBE_CS4227_RESET_HOLD, IXGBE_CS4227_RESET_HOLD + 100);
 167
 168         status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, &reg);
 169         if (status)
 170                 return status;
 171         reg |= IXGBE_PE_BIT1;
 172         status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
 173         if (status)
 174                 return status;
 175
 176         /* Wait for the reset to complete. */
 177         msleep(IXGBE_CS4227_RESET_DELAY);
 178         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 179                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
 180                                            &value);
 181                 if (!status && value == IXGBE_CS4227_EEPROM_LOAD_OK)
 182                         break;
 183                 msleep(IXGBE_CS4227_CHECK_DELAY);
 184         }
 185         if (retry == IXGBE_CS4227_RETRIES) {
 186                 hw_err(hw, "CS4227 reset did not complete\n");
 187                 return IXGBE_ERR_PHY;
 188         }
 189
 190         status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
 191         if (status || !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
 192                 hw_err(hw, "CS4227 EEPROM did not load successfully\n");
 193                 return IXGBE_ERR_PHY;
 194         }
 195
 196         return 0;
 197 }
 198
 199 /**
 200  * ixgbe_check_cs4227 - Check CS4227 and reset as needed
 201  * @hw: pointer to hardware structure
 202  */
 203 static void ixgbe_check_cs4227(struct ixgbe_hw *hw)
 204 {
 205         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 206         s32 status;
 207         u16 value;
 208         u8 retry;
 209
 210         for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
 211                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 212                 if (status) {
 213                         hw_err(hw, "semaphore failed with %d\n", status);
 214                         msleep(IXGBE_CS4227_CHECK_DELAY);
 215                         continue;
 216                 }
 217
 218                 /* Get status of reset flow. */
 219                 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
 220                 if (!status && value == IXGBE_CS4227_RESET_COMPLETE)
 221                         goto out;
 222
 223                 if (status || value != IXGBE_CS4227_RESET_PENDING)
 224                         break;
 225
 226                 /* Reset is pending. Wait and check again. */
 227                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 228                 msleep(IXGBE_CS4227_CHECK_DELAY);
 229         }
 230         /* If still pending, assume other instance failed. */
 231         if (retry == IXGBE_CS4227_RETRIES) {
 232                 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 233                 if (status) {
 234                         hw_err(hw, "semaphore failed with %d\n", status);
 235                         return;
 236                 }
 237         }
 238
 239         /* Reset the CS4227. */
 240         status = ixgbe_reset_cs4227(hw);
 241         if (status) {
 242                 hw_err(hw, "CS4227 reset failed: %d", status);
 243                 goto out;
 244         }
 245
 246         /* Reset takes so long, temporarily release semaphore in case the
 247          * other driver instance is waiting for the reset indication.
 248          */
 249         ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 250                            IXGBE_CS4227_RESET_PENDING);
 251         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 252         usleep_range(10000, 12000);
 253         status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
 254         if (status) {
 255                 hw_err(hw, "semaphore failed with %d", status);
 256                 return;
 257         }
 258
 259         /* Record completion for next time. */
 260         status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
 261                                     IXGBE_CS4227_RESET_COMPLETE);
 262
 263 out:
 264         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 265         msleep(hw->eeprom.semaphore_delay);
 266 }
 267
 268 /** ixgbe_identify_phy_x550em - Get PHY type based on device id
 269  *  @hw: pointer to hardware structure
 270  *
 271  *  Returns error code
 272  */
 273 static s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
 274 {
 275         switch (hw->device_id) {
 276         case IXGBE_DEV_ID_X550EM_A_SFP:
 277                 if (hw->bus.lan_id)
 278                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
 279                 else
 280                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
 281                 return ixgbe_identify_module_generic(hw);
 282         case IXGBE_DEV_ID_X550EM_X_SFP:
 283                 /* set up for CS4227 usage */
 284                 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
 285                 ixgbe_setup_mux_ctl(hw);
 286                 ixgbe_check_cs4227(hw);
 287                 /* Fallthrough */
 288         case IXGBE_DEV_ID_X550EM_A_SFP_N:
 289                 return ixgbe_identify_module_generic(hw);
 290         case IXGBE_DEV_ID_X550EM_X_KX4:
 291                 hw->phy.type = ixgbe_phy_x550em_kx4;
 292                 break;
 293         case IXGBE_DEV_ID_X550EM_X_KR:
 294         case IXGBE_DEV_ID_X550EM_A_KR:
 295         case IXGBE_DEV_ID_X550EM_A_KR_L:
 296                 hw->phy.type = ixgbe_phy_x550em_kr;
 297                 break;
 298         case IXGBE_DEV_ID_X550EM_X_1G_T:
 299         case IXGBE_DEV_ID_X550EM_X_10G_T:
 300                 return ixgbe_identify_phy_generic(hw);
 301         default:
 302                 break;
 303         }
 304         return 0;
 305 }
 306
 307 static s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 308                                      u32 device_type, u16 *phy_data)
 309 {
 310         return IXGBE_NOT_IMPLEMENTED;
 311 }
 312
 313 static s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
 314                                       u32 device_type, u16 phy_data)
 315 {
 316         return IXGBE_NOT_IMPLEMENTED;
 317 }
 318
 319 /** ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
 320  *  @hw: pointer to hardware structure
 321  *
 322  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
 323  *  ixgbe_hw struct in order to set up EEPROM access.
 324  **/
 325 static s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
 326 {
 327         struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 328         u32 eec;
 329         u16 eeprom_size;
 330
 331         if (eeprom->type == ixgbe_eeprom_uninitialized) {
 332                 eeprom->semaphore_delay = 10;
 333                 eeprom->type = ixgbe_flash;
 334
 335                 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
 336                 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 337                                     IXGBE_EEC_SIZE_SHIFT);
 338                 eeprom->word_size = BIT(eeprom_size +
 339                                         IXGBE_EEPROM_WORD_SIZE_SHIFT);
 340
 341                 hw_dbg(hw, "Eeprom params: type = %d, size = %d\n",
 342                        eeprom->type, eeprom->word_size);
 343         }
 344
 345         return 0;
 346 }
 347
 348 /**
 349  * ixgbe_iosf_wait - Wait for IOSF command completion
 350  * @hw: pointer to hardware structure
 351  * @ctrl: pointer to location to receive final IOSF control value
 352  *
 353  * Return: failing status on timeout
 354  *
 355  * Note: ctrl can be NULL if the IOSF control register value is not needed
 356  */
 357 static s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
 358 {
 359         u32 i, command;
 360
 361         /* Check every 10 usec to see if the address cycle completed.
 362          * The SB IOSF BUSY bit will clear when the operation is
 363          * complete.
 364          */
 365         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 366                 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
 367                 if (!(command & IXGBE_SB_IOSF_CTRL_BUSY))
 368                         break;
 369                 udelay(10);
 370         }
 371         if (ctrl)
 372                 *ctrl = command;
 373         if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
 374                 hw_dbg(hw, "IOSF wait timed out\n");
 375                 return IXGBE_ERR_PHY;
 376         }
 377
 378         return 0;
 379 }
 380
 381 /** ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the
 382  *  IOSF device
 383  *  @hw: pointer to hardware structure
 384  *  @reg_addr: 32 bit PHY register to write
 385  *  @device_type: 3 bit device type
 386  *  @phy_data: Pointer to read data from the register
 387  **/
 388 static s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
 389                                        u32 device_type, u32 *data)
 390 {
 391         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
 392         u32 command, error;
 393         s32 ret;
 394
 395         ret = hw->mac.ops.acquire_swfw_sync(hw, gssr);
 396         if (ret)
 397                 return ret;
 398
 399         ret = ixgbe_iosf_wait(hw, NULL);
 400         if (ret)
 401                 goto out;
 402
 403         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
 404                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
 405
 406         /* Write IOSF control register */
 407         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
 408
 409         ret = ixgbe_iosf_wait(hw, &command);
 410
 411         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
 412                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
 413                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
 414                 hw_dbg(hw, "Failed to read, error %x\n", error);
 415                 return IXGBE_ERR_PHY;
 416         }
 417
 418         if (!ret)
 419                 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
 420
 421 out:
 422         hw->mac.ops.release_swfw_sync(hw, gssr);
 423         return ret;
 424 }
 425
 426 /**
 427  * ixgbe_get_phy_token - Get the token for shared PHY access
 428  * @hw: Pointer to hardware structure
 429  */
 430 static s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)
 431 {
 432         struct ixgbe_hic_phy_token_req token_cmd;
 433         s32 status;
 434
 435         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
 436         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
 437         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
 438         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
 439         token_cmd.port_number = hw->bus.lan_id;
 440         token_cmd.command_type = FW_PHY_TOKEN_REQ;
 441         token_cmd.pad = 0;
 442         status = ixgbe_host_interface_command(hw, &token_cmd, sizeof(token_cmd),
 443                                               IXGBE_HI_COMMAND_TIMEOUT,
 444                                               true);
 445         if (status)
 446                 return status;
 447         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
 448                 return 0;
 449         if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY)
 450                 return IXGBE_ERR_FW_RESP_INVALID;
 451
 452         return IXGBE_ERR_TOKEN_RETRY;
 453 }
 454
 455 /**
 456  * ixgbe_put_phy_token - Put the token for shared PHY access
 457  * @hw: Pointer to hardware structure
 458  */
 459 static s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)
 460 {
 461         struct ixgbe_hic_phy_token_req token_cmd;
 462         s32 status;
 463
 464         token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
 465         token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
 466         token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
 467         token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
 468         token_cmd.port_number = hw->bus.lan_id;
 469         token_cmd.command_type = FW_PHY_TOKEN_REL;
 470         token_cmd.pad = 0;
 471         status = ixgbe_host_interface_command(hw, &token_cmd, sizeof(token_cmd),
 472                                               IXGBE_HI_COMMAND_TIMEOUT,
 473                                               true);
 474         if (status)
 475                 return status;
 476         if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
 477                 return 0;
 478         return IXGBE_ERR_FW_RESP_INVALID;
 479 }
 480
 481 /**
 482  *  ixgbe_write_iosf_sb_reg_x550a - Write to IOSF PHY register
 483  *  @hw: pointer to hardware structure
 484  *  @reg_addr: 32 bit PHY register to write
 485  *  @device_type: 3 bit device type
 486  *  @data: Data to write to the register
 487  **/
 488 static s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
 489                                          __always_unused u32 device_type,
 490                                          u32 data)
 491 {
 492         struct ixgbe_hic_internal_phy_req write_cmd;
 493
 494         memset(&write_cmd, 0, sizeof(write_cmd));
 495         write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
 496         write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
 497         write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
 498         write_cmd.port_number = hw->bus.lan_id;
 499         write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
 500         write_cmd.address = cpu_to_be16(reg_addr);
 501         write_cmd.write_data = cpu_to_be32(data);
 502
 503         return ixgbe_host_interface_command(hw, &write_cmd, sizeof(write_cmd),
 504                                             IXGBE_HI_COMMAND_TIMEOUT, false);
 505 }
 506
 507 /**
 508  *  ixgbe_read_iosf_sb_reg_x550a - Read from IOSF PHY register
 509  *  @hw: pointer to hardware structure
 510  *  @reg_addr: 32 bit PHY register to write
 511  *  @device_type: 3 bit device type
 512  *  @data: Pointer to read data from the register
 513  **/
 514 static s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
 515                                         __always_unused u32 device_type,
 516                                         u32 *data)
 517 {
 518         union {
 519                 struct ixgbe_hic_internal_phy_req cmd;
 520                 struct ixgbe_hic_internal_phy_resp rsp;
 521         } hic;
 522         s32 status;
 523
 524         memset(&hic, 0, sizeof(hic));
 525         hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
 526         hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
 527         hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
 528         hic.cmd.port_number = hw->bus.lan_id;
 529         hic.cmd.command_type = FW_INT_PHY_REQ_READ;
 530         hic.cmd.address = cpu_to_be16(reg_addr);
 531
 532         status = ixgbe_host_interface_command(hw, &hic.cmd, sizeof(hic.cmd),
 533                                               IXGBE_HI_COMMAND_TIMEOUT, true);
 534
 535         /* Extract the register value from the response. */
 536         *data = be32_to_cpu(hic.rsp.read_data);
 537
 538         return status;
 539 }
 540
 541 /** ixgbe_read_ee_hostif_data_X550 - Read EEPROM word using a host interface
 542  *  command assuming that the semaphore is already obtained.
 543  *  @hw: pointer to hardware structure
 544  *  @offset: offset of  word in the EEPROM to read
 545  *  @data: word read from the EEPROM
 546  *
 547  *  Reads a 16 bit word from the EEPROM using the hostif.
 548  **/
 549 static s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
 550                                           u16 *data)
 551 {
 552         s32 status;
 553         struct ixgbe_hic_read_shadow_ram buffer;
 554
 555         buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
 556         buffer.hdr.req.buf_lenh = 0;
 557         buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
 558         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
 559
 560         /* convert offset from words to bytes */
 561         buffer.address = cpu_to_be32(offset * 2);
 562         /* one word */
 563         buffer.length = cpu_to_be16(sizeof(u16));
 564
 565         status = ixgbe_host_interface_command(hw, &buffer, sizeof(buffer),
 566                                               IXGBE_HI_COMMAND_TIMEOUT, false);
 567         if (status)
 568                 return status;
 569
 570         *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
 571                                           FW_NVM_DATA_OFFSET);
 572
 573         return 0;
 574 }
 575
 576 /** ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
 577  *  @hw: pointer to hardware structure
 578  *  @offset: offset of  word in the EEPROM to read
 579  *  @words: number of words
 580  *  @data: word(s) read from the EEPROM
 581  *
 582  *  Reads a 16 bit word(s) from the EEPROM using the hostif.
 583  **/
 584 static s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
 585                                             u16 offset, u16 words, u16 *data)
 586 {
 587         struct ixgbe_hic_read_shadow_ram buffer;
 588         u32 current_word = 0;
 589         u16 words_to_read;
 590         s32 status;
 591         u32 i;
 592
 593         /* Take semaphore for the entire operation. */
 594         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 595         if (status) {
 596                 hw_dbg(hw, "EEPROM read buffer - semaphore failed\n");
 597                 return status;
 598         }
 599
 600         while (words) {
 601                 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
 602                         words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
 603                 else
 604                         words_to_read = words;
 605
 606                 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
 607                 buffer.hdr.req.buf_lenh = 0;
 608                 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
 609                 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
 610
 611                 /* convert offset from words to bytes */
 612                 buffer.address = cpu_to_be32((offset + current_word) * 2);
 613                 buffer.length = cpu_to_be16(words_to_read * 2);
 614
 615                 status = ixgbe_host_interface_command(hw, &buffer,
 616                                                       sizeof(buffer),
 617                                                       IXGBE_HI_COMMAND_TIMEOUT,
 618                                                       false);
 619                 if (status) {
 620                         hw_dbg(hw, "Host interface command failed\n");
 621                         goto out;
 622                 }
 623
 624                 for (i = 0; i < words_to_read; i++) {
 625                         u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
 626                                   2 * i;
 627                         u32 value = IXGBE_READ_REG(hw, reg);
 628
 629                         data[current_word] = (u16)(value & 0xffff);
 630                         current_word++;
 631                         i++;
 632                         if (i < words_to_read) {
 633                                 value >>= 16;
 634                                 data[current_word] = (u16)(value & 0xffff);
 635                                 current_word++;
 636                         }
 637                 }
 638                 words -= words_to_read;
 639         }
 640
 641 out:
 642         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 643         return status;
 644 }
 645
 646 /** ixgbe_checksum_ptr_x550 - Checksum one pointer region
 647  *  @hw: pointer to hardware structure
 648  *  @ptr: pointer offset in eeprom
 649  *  @size: size of section pointed by ptr, if 0 first word will be used as size
 650  *  @csum: address of checksum to update
 651  *
 652  *  Returns error status for any failure
 653  **/
 654 static s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
 655                                    u16 size, u16 *csum, u16 *buffer,
 656                                    u32 buffer_size)
 657 {
 658         u16 buf[256];
 659         s32 status;
 660         u16 length, bufsz, i, start;
 661         u16 *local_buffer;
 662
 663         bufsz = sizeof(buf) / sizeof(buf[0]);
 664
 665         /* Read a chunk at the pointer location */
 666         if (!buffer) {
 667                 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
 668                 if (status) {
 669                         hw_dbg(hw, "Failed to read EEPROM image\n");
 670                         return status;
 671                 }
 672                 local_buffer = buf;
 673         } else {
 674                 if (buffer_size < ptr)
 675                         return  IXGBE_ERR_PARAM;
 676                 local_buffer = &buffer[ptr];
 677         }
 678
 679         if (size) {
 680                 start = 0;
 681                 length = size;
 682         } else {
 683                 start = 1;
 684                 length = local_buffer[0];
 685
 686                 /* Skip pointer section if length is invalid. */
 687                 if (length == 0xFFFF || length == 0 ||
 688                     (ptr + length) >= hw->eeprom.word_size)
 689                         return 0;
 690         }
 691
 692         if (buffer && ((u32)start + (u32)length > buffer_size))
 693                 return IXGBE_ERR_PARAM;
 694
 695         for (i = start; length; i++, length--) {
 696                 if (i == bufsz && !buffer) {
 697                         ptr += bufsz;
 698                         i = 0;
 699                         if (length < bufsz)
 700                                 bufsz = length;
 701
 702                         /* Read a chunk at the pointer location */
 703                         status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
 704                                                                   bufsz, buf);
 705                         if (status) {
 706                                 hw_dbg(hw, "Failed to read EEPROM image\n");
 707                                 return status;
 708                         }
 709                 }
 710                 *csum += local_buffer[i];
 711         }
 712         return 0;
 713 }
 714
 715 /** ixgbe_calc_checksum_X550 - Calculates and returns the checksum
 716  *  @hw: pointer to hardware structure
 717  *  @buffer: pointer to buffer containing calculated checksum
 718  *  @buffer_size: size of buffer
 719  *
 720  *  Returns a negative error code on error, or the 16-bit checksum
 721  **/
 722 static s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer,
 723                                     u32 buffer_size)
 724 {
 725         u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
 726         u16 *local_buffer;
 727         s32 status;
 728         u16 checksum = 0;
 729         u16 pointer, i, size;
 730
 731         hw->eeprom.ops.init_params(hw);
 732
 733         if (!buffer) {
 734                 /* Read pointer area */
 735                 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
 736                                                 IXGBE_EEPROM_LAST_WORD + 1,
 737                                                 eeprom_ptrs);
 738                 if (status) {
 739                         hw_dbg(hw, "Failed to read EEPROM image\n");
 740                         return status;
 741                 }
 742                 local_buffer = eeprom_ptrs;
 743         } else {
 744                 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
 745                         return IXGBE_ERR_PARAM;
 746                 local_buffer = buffer;
 747         }
 748
 749         /* For X550 hardware include 0x0-0x41 in the checksum, skip the
 750          * checksum word itself
 751          */
 752         for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
 753                 if (i != IXGBE_EEPROM_CHECKSUM)
 754                         checksum += local_buffer[i];
 755
 756         /* Include all data from pointers 0x3, 0x6-0xE.  This excludes the
 757          * FW, PHY module, and PCIe Expansion/Option ROM pointers.
 758          */
 759         for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
 760                 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
 761                         continue;
 762
 763                 pointer = local_buffer[i];
 764
 765                 /* Skip pointer section if the pointer is invalid. */
 766                 if (pointer == 0xFFFF || pointer == 0 ||
 767                     pointer >= hw->eeprom.word_size)
 768                         continue;
 769
 770                 switch (i) {
 771                 case IXGBE_PCIE_GENERAL_PTR:
 772                         size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
 773                         break;
 774                 case IXGBE_PCIE_CONFIG0_PTR:
 775                 case IXGBE_PCIE_CONFIG1_PTR:
 776                         size = IXGBE_PCIE_CONFIG_SIZE;
 777                         break;
 778                 default:
 779                         size = 0;
 780                         break;
 781                 }
 782
 783                 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
 784                                                  buffer, buffer_size);
 785                 if (status)
 786                         return status;
 787         }
 788
 789         checksum = (u16)IXGBE_EEPROM_SUM - checksum;
 790
 791         return (s32)checksum;
 792 }
 793
 794 /** ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
 795  *  @hw: pointer to hardware structure
 796  *
 797  *  Returns a negative error code on error, or the 16-bit checksum
 798  **/
 799 static s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
 800 {
 801         return ixgbe_calc_checksum_X550(hw, NULL, 0);
 802 }
 803
 804 /** ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
 805  *  @hw: pointer to hardware structure
 806  *  @offset: offset of  word in the EEPROM to read
 807  *  @data: word read from the EEPROM
 808  *
 809  *   Reads a 16 bit word from the EEPROM using the hostif.
 810  **/
 811 static s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data)
 812 {
 813         s32 status = 0;
 814
 815         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) {
 816                 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
 817                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 818         } else {
 819                 status = IXGBE_ERR_SWFW_SYNC;
 820         }
 821
 822         return status;
 823 }
 824
 825 /** ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
 826  *  @hw: pointer to hardware structure
 827  *  @checksum_val: calculated checksum
 828  *
 829  *  Performs checksum calculation and validates the EEPROM checksum.  If the
 830  *  caller does not need checksum_val, the value can be NULL.
 831  **/
 832 static s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw,
 833                                                u16 *checksum_val)
 834 {
 835         s32 status;
 836         u16 checksum;
 837         u16 read_checksum = 0;
 838
 839         /* Read the first word from the EEPROM. If this times out or fails, do
 840          * not continue or we could be in for a very long wait while every
 841          * EEPROM read fails
 842          */
 843         status = hw->eeprom.ops.read(hw, 0, &checksum);
 844         if (status) {
 845                 hw_dbg(hw, "EEPROM read failed\n");
 846                 return status;
 847         }
 848
 849         status = hw->eeprom.ops.calc_checksum(hw);
 850         if (status < 0)
 851                 return status;
 852
 853         checksum = (u16)(status & 0xffff);
 854
 855         status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
 856                                            &read_checksum);
 857         if (status)
 858                 return status;
 859
 860         /* Verify read checksum from EEPROM is the same as
 861          * calculated checksum
 862          */
 863         if (read_checksum != checksum) {
 864                 status = IXGBE_ERR_EEPROM_CHECKSUM;
 865                 hw_dbg(hw, "Invalid EEPROM checksum");
 866         }
 867
 868         /* If the user cares, return the calculated checksum */
 869         if (checksum_val)
 870                 *checksum_val = checksum;
 871
 872         return status;
 873 }
 874
 875 /** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
 876  *  @hw: pointer to hardware structure
 877  *  @offset: offset of  word in the EEPROM to write
 878  *  @data: word write to the EEPROM
 879  *
 880  *  Write a 16 bit word to the EEPROM using the hostif.
 881  **/
 882 static s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
 883                                            u16 data)
 884 {
 885         s32 status;
 886         struct ixgbe_hic_write_shadow_ram buffer;
 887
 888         buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
 889         buffer.hdr.req.buf_lenh = 0;
 890         buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
 891         buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
 892
 893         /* one word */
 894         buffer.length = cpu_to_be16(sizeof(u16));
 895         buffer.data = data;
 896         buffer.address = cpu_to_be32(offset * 2);
 897
 898         status = ixgbe_host_interface_command(hw, &buffer, sizeof(buffer),
 899                                               IXGBE_HI_COMMAND_TIMEOUT, false);
 900         return status;
 901 }
 902
 903 /** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
 904  *  @hw: pointer to hardware structure
 905  *  @offset: offset of  word in the EEPROM to write
 906  *  @data: word write to the EEPROM
 907  *
 908  *  Write a 16 bit word to the EEPROM using the hostif.
 909  **/
 910 static s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 data)
 911 {
 912         s32 status = 0;
 913
 914         if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) {
 915                 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
 916                 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 917         } else {
 918                 hw_dbg(hw, "write ee hostif failed to get semaphore");
 919                 status = IXGBE_ERR_SWFW_SYNC;
 920         }
 921
 922         return status;
 923 }
 924
 925 /** ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
 926  *  @hw: pointer to hardware structure
 927  *
 928  *  Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
 929  **/
 930 static s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
 931 {
 932         s32 status = 0;
 933         union ixgbe_hic_hdr2 buffer;
 934
 935         buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
 936         buffer.req.buf_lenh = 0;
 937         buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
 938         buffer.req.checksum = FW_DEFAULT_CHECKSUM;
 939
 940         status = ixgbe_host_interface_command(hw, &buffer, sizeof(buffer),
 941                                               IXGBE_HI_COMMAND_TIMEOUT, false);
 942         return status;
 943 }
 944
 945 /**
 946  * ixgbe_get_bus_info_X550em - Set PCI bus info
 947  * @hw: pointer to hardware structure
 948  *
 949  * Sets bus link width and speed to unknown because X550em is
 950  * not a PCI device.
 951  **/
 952 static s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
 953 {
 954         hw->bus.type  = ixgbe_bus_type_internal;
 955         hw->bus.width = ixgbe_bus_width_unknown;
 956         hw->bus.speed = ixgbe_bus_speed_unknown;
 957
 958         hw->mac.ops.set_lan_id(hw);
 959
 960         return 0;
 961 }
 962
 963 /** ixgbe_disable_rx_x550 - Disable RX unit
 964  *
 965  *  Enables the Rx DMA unit for x550
 966  **/
 967 static void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
 968 {
 969         u32 rxctrl, pfdtxgswc;
 970         s32 status;
 971         struct ixgbe_hic_disable_rxen fw_cmd;
 972
 973         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
 974         if (rxctrl & IXGBE_RXCTRL_RXEN) {
 975                 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
 976                 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
 977                         pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
 978                         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
 979                         hw->mac.set_lben = true;
 980                 } else {
 981                         hw->mac.set_lben = false;
 982                 }
 983
 984                 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
 985                 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
 986                 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
 987                 fw_cmd.port_number = hw->bus.lan_id;
 988
 989                 status = ixgbe_host_interface_command(hw, &fw_cmd,
 990                                         sizeof(struct ixgbe_hic_disable_rxen),
 991                                         IXGBE_HI_COMMAND_TIMEOUT, true);
 992
 993                 /* If we fail - disable RX using register write */
 994                 if (status) {
 995                         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
 996                         if (rxctrl & IXGBE_RXCTRL_RXEN) {
 997                                 rxctrl &= ~IXGBE_RXCTRL_RXEN;
 998                                 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
 999                         }
1000                 }
1001         }
1002 }
1003
1004 /** ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
1005  *  @hw: pointer to hardware structure
1006  *
1007  *  After writing EEPROM to shadow RAM using EEWR register, software calculates
1008  *  checksum and updates the EEPROM and instructs the hardware to update
1009  *  the flash.
1010  **/
1011 static s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
1012 {
1013         s32 status;
1014         u16 checksum = 0;
1015
1016         /* Read the first word from the EEPROM. If this times out or fails, do
1017          * not continue or we could be in for a very long wait while every
1018          * EEPROM read fails
1019          */
1020         status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
1021         if (status) {
1022                 hw_dbg(hw, "EEPROM read failed\n");
1023                 return status;
1024         }
1025
1026         status = ixgbe_calc_eeprom_checksum_X550(hw);
1027         if (status < 0)
1028                 return status;
1029
1030         checksum = (u16)(status & 0xffff);
1031
1032         status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
1033                                             checksum);
1034         if (status)
1035                 return status;
1036
1037         status = ixgbe_update_flash_X550(hw);
1038
1039         return status;
1040 }
1041
1042 /** ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
1043  *  @hw: pointer to hardware structure
1044  *  @offset: offset of  word in the EEPROM to write
1045  *  @words: number of words
1046  *  @data: word(s) write to the EEPROM
1047  *
1048  *
1049  *  Write a 16 bit word(s) to the EEPROM using the hostif.
1050  **/
1051 static s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1052                                              u16 offset, u16 words,
1053                                              u16 *data)
1054 {
1055         s32 status = 0;
1056         u32 i = 0;
1057
1058         /* Take semaphore for the entire operation. */
1059         status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1060         if (status) {
1061                 hw_dbg(hw, "EEPROM write buffer - semaphore failed\n");
1062                 return status;
1063         }
1064
1065         for (i = 0; i < words; i++) {
1066                 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
1067                                                          data[i]);
1068                 if (status) {
1069                         hw_dbg(hw, "Eeprom buffered write failed\n");
1070                         break;
1071                 }
1072         }
1073
1074         hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1075
1076         return status;
1077 }
1078
1079 /** ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the
1080  *  IOSF device
1081  *
1082  *  @hw: pointer to hardware structure
1083  *  @reg_addr: 32 bit PHY register to write
1084  *  @device_type: 3 bit device type
1085  *  @data: Data to write to the register
1086  **/
1087 static s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1088                                         u32 device_type, u32 data)
1089 {
1090         u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1091         u32 command, error;
1092         s32 ret;
1093
1094         ret = hw->mac.ops.acquire_swfw_sync(hw, gssr);
1095         if (ret)
1096                 return ret;
1097
1098         ret = ixgbe_iosf_wait(hw, NULL);
1099         if (ret)
1100                 goto out;
1101
1102         command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1103                    (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1104
1105         /* Write IOSF control register */
1106         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1107
1108         /* Write IOSF data register */
1109         IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
1110
1111         ret = ixgbe_iosf_wait(hw, &command);
1112
1113         if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1114                 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1115                          IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1116                 hw_dbg(hw, "Failed to write, error %x\n", error);
1117                 return IXGBE_ERR_PHY;
1118         }
1119
1120 out:
1121         hw->mac.ops.release_swfw_sync(hw, gssr);
1122         return ret;
1123 }
1124
1125 /** ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
1126  *  @hw: pointer to hardware structure
1127  *  @speed: the link speed to force
1128  *
1129  *  Configures the integrated KR PHY to use iXFI mode. Used to connect an
1130  *  internal and external PHY at a specific speed, without autonegotiation.
1131  **/
1132 static s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1133 {
1134         s32 status;
1135         u32 reg_val;
1136
1137         /* Disable AN and force speed to 10G Serial. */
1138         status = ixgbe_read_iosf_sb_reg_x550(hw,
1139                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1140                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1141         if (status)
1142                 return status;
1143
1144         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1145         reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1146
1147         /* Select forced link speed for internal PHY. */
1148         switch (*speed) {
1149         case IXGBE_LINK_SPEED_10GB_FULL:
1150                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1151                 break;
1152         case IXGBE_LINK_SPEED_1GB_FULL:
1153                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1154                 break;
1155         default:
1156                 /* Other link speeds are not supported by internal KR PHY. */
1157                 return IXGBE_ERR_LINK_SETUP;
1158         }
1159
1160         status = ixgbe_write_iosf_sb_reg_x550(hw,
1161                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1162                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1163         if (status)
1164                 return status;
1165
1166         /* Disable training protocol FSM. */
1167         status = ixgbe_read_iosf_sb_reg_x550(hw,
1168                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1169                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1170         if (status)
1171                 return status;
1172
1173         reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1174         status = ixgbe_write_iosf_sb_reg_x550(hw,
1175                                 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1176                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1177         if (status)
1178                 return status;
1179
1180         /* Disable Flex from training TXFFE. */
1181         status = ixgbe_read_iosf_sb_reg_x550(hw,
1182                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1183                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1184         if (status)
1185                 return status;
1186
1187         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1188         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1189         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1190         status = ixgbe_write_iosf_sb_reg_x550(hw,
1191                                 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1192                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1193         if (status)
1194                 return status;
1195
1196         status = ixgbe_read_iosf_sb_reg_x550(hw,
1197                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1198                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1199         if (status)
1200                 return status;
1201
1202         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1203         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1204         reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1205         status = ixgbe_write_iosf_sb_reg_x550(hw,
1206                                 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1207                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1208         if (status)
1209                 return status;
1210
1211         /* Enable override for coefficients. */
1212         status = ixgbe_read_iosf_sb_reg_x550(hw,
1213                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1214                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1215         if (status)
1216                 return status;
1217
1218         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1219         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1220         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1221         reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1222         status = ixgbe_write_iosf_sb_reg_x550(hw,
1223                                 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1224                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1225         if (status)
1226                 return status;
1227
1228         /* Toggle port SW reset by AN reset. */
1229         status = ixgbe_read_iosf_sb_reg_x550(hw,
1230                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1231                                 IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1232         if (status)
1233                 return status;
1234
1235         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1236         status = ixgbe_write_iosf_sb_reg_x550(hw,
1237                                 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1238                                 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1239
1240         return status;
1241 }
1242
1243 /**
1244  *  ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1245  *  @hw: pointer to hardware structure
1246  *  @linear: true if SFP module is linear
1247  */
1248 static s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1249 {
1250         switch (hw->phy.sfp_type) {
1251         case ixgbe_sfp_type_not_present:
1252                 return IXGBE_ERR_SFP_NOT_PRESENT;
1253         case ixgbe_sfp_type_da_cu_core0:
1254         case ixgbe_sfp_type_da_cu_core1:
1255                 *linear = true;
1256                 break;
1257         case ixgbe_sfp_type_srlr_core0:
1258         case ixgbe_sfp_type_srlr_core1:
1259         case ixgbe_sfp_type_da_act_lmt_core0:
1260         case ixgbe_sfp_type_da_act_lmt_core1:
1261         case ixgbe_sfp_type_1g_sx_core0:
1262         case ixgbe_sfp_type_1g_sx_core1:
1263         case ixgbe_sfp_type_1g_lx_core0:
1264         case ixgbe_sfp_type_1g_lx_core1:
1265                 *linear = false;
1266                 break;
1267         case ixgbe_sfp_type_unknown:
1268         case ixgbe_sfp_type_1g_cu_core0:
1269         case ixgbe_sfp_type_1g_cu_core1:
1270         default:
1271                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1272         }
1273
1274         return 0;
1275 }
1276
1277 /**
1278  *  ixgbe_setup_mac_link_sfp_x550em - Configure the KR PHY for SFP.
1279  *  @hw: pointer to hardware structure
1280  *
1281  *  Configures the extern PHY and the integrated KR PHY for SFP support.
1282  */
1283 static s32
1284 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
1285                                 ixgbe_link_speed speed,
1286                                 __always_unused bool autoneg_wait_to_complete)
1287 {
1288         s32 status;
1289         u16 slice, value;
1290         bool setup_linear = false;
1291
1292         /* Check if SFP module is supported and linear */
1293         status = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1294
1295         /* If no SFP module present, then return success. Return success since
1296          * there is no reason to configure CS4227 and SFP not present error is
1297          * not accepted in the setup MAC link flow.
1298          */
1299         if (status == IXGBE_ERR_SFP_NOT_PRESENT)
1300                 return 0;
1301
1302         if (status)
1303                 return status;
1304
1305         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
1306                 /* Configure CS4227 LINE side to 10G SR. */
1307                 slice = IXGBE_CS4227_LINE_SPARE22_MSB + (hw->bus.lan_id << 12);
1308                 value = IXGBE_CS4227_SPEED_10G;
1309                 status = ixgbe_write_i2c_combined_generic(hw, IXGBE_CS4227,
1310                                                           slice, value);
1311                 if (status)
1312                         goto i2c_err;
1313
1314                 slice = IXGBE_CS4227_LINE_SPARE24_LSB + (hw->bus.lan_id << 12);
1315                 value = (IXGBE_CS4227_EDC_MODE_SR << 1) | 1;
1316                 status = ixgbe_write_i2c_combined_generic(hw, IXGBE_CS4227,
1317                                                           slice, value);
1318                 if (status)
1319                         goto i2c_err;
1320
1321                 /* Configure CS4227 for HOST connection rate then type. */
1322                 slice = IXGBE_CS4227_HOST_SPARE22_MSB + (hw->bus.lan_id << 12);
1323                 value = speed & IXGBE_LINK_SPEED_10GB_FULL ?
1324                         IXGBE_CS4227_SPEED_10G : IXGBE_CS4227_SPEED_1G;
1325                 status = ixgbe_write_i2c_combined_generic(hw, IXGBE_CS4227,
1326                                                           slice, value);
1327                 if (status)
1328                         goto i2c_err;
1329
1330                 slice = IXGBE_CS4227_HOST_SPARE24_LSB + (hw->bus.lan_id << 12);
1331                 if (setup_linear)
1332                         value = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 1;
1333                 else
1334                         value = (IXGBE_CS4227_EDC_MODE_SR << 1) | 1;
1335                 status = ixgbe_write_i2c_combined_generic(hw, IXGBE_CS4227,
1336                                                           slice, value);
1337                 if (status)
1338                         goto i2c_err;
1339
1340                 /* Setup XFI internal link. */
1341                 status = ixgbe_setup_ixfi_x550em(hw, &speed);
1342                 if (status) {
1343                         hw_dbg(hw, "setup_ixfi failed with %d\n", status);
1344                         return status;
1345                 }
1346         } else {
1347                 /* Configure internal PHY for KR/KX. */
1348                 status = ixgbe_setup_kr_speed_x550em(hw, speed);
1349                 if (status) {
1350                         hw_dbg(hw, "setup_kr_speed failed with %d\n", status);
1351                         return status;
1352                 }
1353
1354                 /* Configure CS4227 LINE side to proper mode. */
1355                 slice = IXGBE_CS4227_LINE_SPARE24_LSB + (hw->bus.lan_id << 12);
1356                 if (setup_linear)
1357                         value = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 1;
1358                 else
1359                         value = (IXGBE_CS4227_EDC_MODE_SR << 1) | 1;
1360                 status = ixgbe_write_i2c_combined_generic(hw, IXGBE_CS4227,
1361                                                           slice, value);
1362                 if (status)
1363                         goto i2c_err;
1364         }
1365
1366         return 0;
1367
1368 i2c_err:
1369         hw_dbg(hw, "combined i2c access failed with %d\n", status);
1370         return status;
1371 }
1372
1373 /**
1374  * ixgbe_setup_mac_link_sfp_n - Setup internal PHY for native SFP
1375  * @hw: pointer to hardware structure
1376  *
1377  * Configure the the integrated PHY for native SFP support.
1378  */
1379 static s32
1380 ixgbe_setup_mac_link_sfp_n(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1381                            __always_unused bool autoneg_wait_to_complete)
1382 {
1383         bool setup_linear = false;
1384         u32 reg_phy_int;
1385         s32 rc;
1386
1387         /* Check if SFP module is supported and linear */
1388         rc = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1389
1390         /* If no SFP module present, then return success. Return success since
1391          * SFP not present error is not excepted in the setup MAC link flow.
1392          */
1393         if (rc == IXGBE_ERR_SFP_NOT_PRESENT)
1394                 return 0;
1395
1396         if (!rc)
1397                 return rc;
1398
1399         /* Configure internal PHY for native SFI */
1400         rc = hw->mac.ops.read_iosf_sb_reg(hw,
1401                                           IXGBE_KRM_AN_CNTL_8(hw->bus.lan_id),
1402                                           IXGBE_SB_IOSF_TARGET_KR_PHY,
1403                                           &reg_phy_int);
1404         if (rc)
1405                 return rc;
1406
1407         if (setup_linear) {
1408                 reg_phy_int &= ~IXGBE_KRM_AN_CNTL_8_LIMITING;
1409                 reg_phy_int |= IXGBE_KRM_AN_CNTL_8_LINEAR;
1410         } else {
1411                 reg_phy_int |= IXGBE_KRM_AN_CNTL_8_LIMITING;
1412                 reg_phy_int &= ~IXGBE_KRM_AN_CNTL_8_LINEAR;
1413         }
1414
1415         rc = hw->mac.ops.write_iosf_sb_reg(hw,
1416                                            IXGBE_KRM_AN_CNTL_8(hw->bus.lan_id),
1417                                            IXGBE_SB_IOSF_TARGET_KR_PHY,
1418                                            reg_phy_int);
1419         if (rc)
1420                 return rc;
1421
1422         /* Setup XFI/SFI internal link */
1423         return ixgbe_setup_ixfi_x550em(hw, &speed);
1424 }
1425
1426 /**
1427  * ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
1428  * @hw: pointer to hardware structure
1429  *
1430  * Configure the the integrated PHY for SFP support.
1431  */
1432 static s32
1433 ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1434                                __always_unused bool autoneg_wait_to_complete)
1435 {
1436         u32 reg_slice, slice_offset;
1437         bool setup_linear = false;
1438         u16 reg_phy_ext;
1439         s32 rc;
1440
1441         /* Check if SFP module is supported and linear */
1442         rc = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1443
1444         /* If no SFP module present, then return success. Return success since
1445          * SFP not present error is not excepted in the setup MAC link flow.
1446          */
1447         if (rc == IXGBE_ERR_SFP_NOT_PRESENT)
1448                 return 0;
1449
1450         if (!rc)
1451                 return rc;
1452
1453         /* Configure internal PHY for KR/KX. */
1454         ixgbe_setup_kr_speed_x550em(hw, speed);
1455
1456         if (!hw->phy.mdio.prtad || hw->phy.mdio.prtad == 0xFFFF)
1457                 return IXGBE_ERR_PHY_ADDR_INVALID;
1458
1459         /* Get external PHY device id */
1460         rc = hw->phy.ops.read_reg(hw, IXGBE_CS4227_GLOBAL_ID_MSB,
1461                                   IXGBE_MDIO_ZERO_DEV_TYPE, &reg_phy_ext);
1462         if (rc)
1463                 return rc;
1464
1465         /* When configuring quad port CS4223, the MAC instance is part
1466          * of the slice offset.
1467          */
1468         if (reg_phy_ext == IXGBE_CS4223_PHY_ID)
1469                 slice_offset = (hw->bus.lan_id +
1470                                 (hw->bus.instance_id << 1)) << 12;
1471         else
1472                 slice_offset = hw->bus.lan_id << 12;
1473
1474         /* Configure CS4227/CS4223 LINE side to proper mode. */
1475         reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset;
1476         if (setup_linear)
1477                 reg_phy_ext = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 1;
1478         else
1479                 reg_phy_ext = (IXGBE_CS4227_EDC_MODE_SR << 1) | 1;
1480         return hw->phy.ops.write_reg(hw, reg_slice, IXGBE_MDIO_ZERO_DEV_TYPE,
1481                                      reg_phy_ext);
1482 }
1483
1484 /**
1485  * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
1486  * @hw: pointer to hardware structure
1487  * @speed: new link speed
1488  * @autoneg_wait_to_complete: true when waiting for completion is needed
1489  *
1490  * Setup internal/external PHY link speed based on link speed, then set
1491  * external PHY auto advertised link speed.
1492  *
1493  * Returns error status for any failure
1494  **/
1495 static s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
1496                                          ixgbe_link_speed speed,
1497                                          bool autoneg_wait)
1498 {
1499         s32 status;
1500         ixgbe_link_speed force_speed;
1501
1502         /* Setup internal/external PHY link speed to iXFI (10G), unless
1503          * only 1G is auto advertised then setup KX link.
1504          */
1505         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1506                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
1507         else
1508                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
1509
1510         /* If internal link mode is XFI, then setup XFI internal link. */
1511         if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
1512                 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
1513
1514                 if (status)
1515                         return status;
1516         }
1517
1518         return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1519 }
1520
1521 /** ixgbe_check_link_t_X550em - Determine link and speed status
1522   * @hw: pointer to hardware structure
1523   * @speed: pointer to link speed
1524   * @link_up: true when link is up
1525   * @link_up_wait_to_complete: bool used to wait for link up or not
1526   *
1527   * Check that both the MAC and X557 external PHY have link.
1528   **/
1529 static s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw,
1530                                      ixgbe_link_speed *speed,
1531                                      bool *link_up,
1532                                      bool link_up_wait_to_complete)
1533 {
1534         u32 status;
1535         u16 autoneg_status;
1536
1537         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
1538                 return IXGBE_ERR_CONFIG;
1539
1540         status = ixgbe_check_mac_link_generic(hw, speed, link_up,
1541                                               link_up_wait_to_complete);
1542
1543         /* If check link fails or MAC link is not up, then return */
1544         if (status || !(*link_up))
1545                 return status;
1546
1547          /* MAC link is up, so check external PHY link.
1548           * Read this twice back to back to indicate current status.
1549           */
1550         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
1551                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1552                                       &autoneg_status);
1553         if (status)
1554                 return status;
1555
1556         /* If external PHY link is not up, then indicate link not up */
1557         if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
1558                 *link_up = false;
1559
1560         return 0;
1561 }
1562
1563 /**
1564  * ixgbe_setup_sgmii - Set up link for sgmii
1565  * @hw: pointer to hardware structure
1566  */
1567 static s32
1568 ixgbe_setup_sgmii(struct ixgbe_hw *hw, __always_unused ixgbe_link_speed speed,
1569                   __always_unused bool autoneg_wait_to_complete)
1570 {
1571         struct ixgbe_mac_info *mac = &hw->mac;
1572         u32 lval, sval;
1573         s32 rc;
1574
1575         rc = mac->ops.read_iosf_sb_reg(hw,
1576                                        IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1577                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1578         if (rc)
1579                 return rc;
1580
1581         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1582         lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1583         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1584         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1585         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1586         rc = mac->ops.write_iosf_sb_reg(hw,
1587                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1588                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1589         if (rc)
1590                 return rc;
1591
1592         rc = mac->ops.read_iosf_sb_reg(hw,
1593                                        IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1594                                        IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1595         if (rc)
1596                 return rc;
1597
1598         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1599         sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1600         rc = mac->ops.write_iosf_sb_reg(hw,
1601                                         IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1602                                         IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1603         if (rc)
1604                 return rc;
1605
1606         lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1607         rc = mac->ops.write_iosf_sb_reg(hw,
1608                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1609                                         IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1610
1611         return rc;
1612 }
1613
1614 /** ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1615  *  @hw: pointer to hardware structure
1616  **/
1617 static void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1618 {
1619         struct ixgbe_mac_info *mac = &hw->mac;
1620
1621         mac->ops.setup_fc = ixgbe_setup_fc_x550em;
1622
1623         switch (mac->ops.get_media_type(hw)) {
1624         case ixgbe_media_type_fiber:
1625                 /* CS4227 does not support autoneg, so disable the laser control
1626                  * functions for SFP+ fiber
1627                  */
1628                 mac->ops.disable_tx_laser = NULL;
1629                 mac->ops.enable_tx_laser = NULL;
1630                 mac->ops.flap_tx_laser = NULL;
1631                 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1632                 switch (hw->device_id) {
1633                 case IXGBE_DEV_ID_X550EM_A_SFP_N:
1634                         mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_n;
1635                         break;
1636                 case IXGBE_DEV_ID_X550EM_A_SFP:
1637                         mac->ops.setup_mac_link =
1638                                                 ixgbe_setup_mac_link_sfp_x550a;
1639                         break;
1640                 default:
1641                         mac->ops.setup_mac_link =
1642                                                 ixgbe_setup_mac_link_sfp_x550em;
1643                         break;
1644                 }
1645                 mac->ops.set_rate_select_speed =
1646                                         ixgbe_set_soft_rate_select_speed;
1647                 break;
1648         case ixgbe_media_type_copper:
1649                 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1650                 mac->ops.setup_fc = ixgbe_setup_fc_generic;
1651                 mac->ops.check_link = ixgbe_check_link_t_X550em;
1652                 return;
1653         case ixgbe_media_type_backplane:
1654                 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
1655                     hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L)
1656                         mac->ops.setup_link = ixgbe_setup_sgmii;
1657                 break;
1658         default:
1659                 break;
1660         }
1661 }
1662
1663 /** ixgbe_setup_sfp_modules_X550em - Setup SFP module
1664  * @hw: pointer to hardware structure
1665  */
1666 static s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1667 {
1668         s32 status;
1669         bool linear;
1670
1671         /* Check if SFP module is supported */
1672         status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1673         if (status)
1674                 return status;
1675
1676         ixgbe_init_mac_link_ops_X550em(hw);
1677         hw->phy.ops.reset = NULL;
1678
1679         return 0;
1680 }
1681
1682 /** ixgbe_get_link_capabilities_x550em - Determines link capabilities
1683  * @hw: pointer to hardware structure
1684  * @speed: pointer to link speed
1685  * @autoneg: true when autoneg or autotry is enabled
1686  **/
1687 static s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1688                                               ixgbe_link_speed *speed,
1689                                               bool *autoneg)
1690 {
1691         /* SFP */
1692         if (hw->phy.media_type == ixgbe_media_type_fiber) {
1693                 /* CS4227 SFP must not enable auto-negotiation */
1694                 *autoneg = false;
1695
1696                 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1697                     hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) {
1698                         *speed = IXGBE_LINK_SPEED_1GB_FULL;
1699                         return 0;
1700                 }
1701
1702                 /* Link capabilities are based on SFP */
1703                 if (hw->phy.multispeed_fiber)
1704                         *speed = IXGBE_LINK_SPEED_10GB_FULL |
1705                                  IXGBE_LINK_SPEED_1GB_FULL;
1706                 else
1707                         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1708         } else {
1709                 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1710                          IXGBE_LINK_SPEED_1GB_FULL;
1711                 *autoneg = true;
1712         }
1713         return 0;
1714 }
1715
1716 /**
1717  * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1718  * @hw: pointer to hardware structure
1719  * @lsc: pointer to boolean flag which indicates whether external Base T
1720  *       PHY interrupt is lsc
1721  *
1722  * Determime if external Base T PHY interrupt cause is high temperature
1723  * failure alarm or link status change.
1724  *
1725  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1726  * failure alarm, else return PHY access status.
1727  **/
1728 static s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1729 {
1730         u32 status;
1731         u16 reg;
1732
1733         *lsc = false;
1734
1735         /* Vendor alarm triggered */
1736         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1737                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1738                                       &reg);
1739
1740         if (status || !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1741                 return status;
1742
1743         /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1744         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1745                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1746                                       &reg);
1747
1748         if (status || !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1749                                 IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1750                 return status;
1751
1752         /* Global alarm triggered */
1753         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1754                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1755                                       &reg);
1756
1757         if (status)
1758                 return status;
1759
1760         /* If high temperature failure, then return over temp error and exit */
1761         if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1762                 /* power down the PHY in case the PHY FW didn't already */
1763                 ixgbe_set_copper_phy_power(hw, false);
1764                 return IXGBE_ERR_OVERTEMP;
1765         }
1766         if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
1767                 /*  device fault alarm triggered */
1768                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
1769                                           IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1770                                           &reg);
1771                 if (status)
1772                         return status;
1773
1774                 /* if device fault was due to high temp alarm handle and exit */
1775                 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
1776                         /* power down the PHY in case the PHY FW didn't */
1777                         ixgbe_set_copper_phy_power(hw, false);
1778                         return IXGBE_ERR_OVERTEMP;
1779                 }
1780         }
1781
1782         /* Vendor alarm 2 triggered */
1783         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1784                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1785
1786         if (status || !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1787                 return status;
1788
1789         /* link connect/disconnect event occurred */
1790         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1791                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1792
1793         if (status)
1794                 return status;
1795
1796         /* Indicate LSC */
1797         if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
1798                 *lsc = true;
1799
1800         return 0;
1801 }
1802
1803 /**
1804  * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1805  * @hw: pointer to hardware structure
1806  *
1807  * Enable link status change and temperature failure alarm for the external
1808  * Base T PHY
1809  *
1810  * Returns PHY access status
1811  **/
1812 static s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1813 {
1814         u32 status;
1815         u16 reg;
1816         bool lsc;
1817
1818         /* Clear interrupt flags */
1819         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1820
1821         /* Enable link status change alarm */
1822         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1823                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &reg);
1824         if (status)
1825                 return status;
1826
1827         reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
1828
1829         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
1830                                        IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg);
1831         if (status)
1832                 return status;
1833
1834         /* Enable high temperature failure and global fault alarms */
1835         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1836                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1837                                       &reg);
1838         if (status)
1839                 return status;
1840
1841         reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
1842                 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
1843
1844         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
1845                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1846                                        reg);
1847         if (status)
1848                 return status;
1849
1850         /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
1851         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1852                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1853                                       &reg);
1854         if (status)
1855                 return status;
1856
1857         reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1858                 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
1859
1860         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
1861                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1862                                        reg);
1863         if (status)
1864                 return status;
1865
1866         /* Enable chip-wide vendor alarm */
1867         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1868                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1869                                       &reg);
1870         if (status)
1871                 return status;
1872
1873         reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
1874
1875         status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
1876                                        IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1877                                        reg);
1878
1879         return status;
1880 }
1881
1882 /**
1883  * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
1884  * @hw: pointer to hardware structure
1885  *
1886  * Handle external Base T PHY interrupt. If high temperature
1887  * failure alarm then return error, else if link status change
1888  * then setup internal/external PHY link
1889  *
1890  * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1891  * failure alarm, else return PHY access status.
1892  **/
1893 static s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1894 {
1895         struct ixgbe_phy_info *phy = &hw->phy;
1896         bool lsc;
1897         u32 status;
1898
1899         status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
1900         if (status)
1901                 return status;
1902
1903         if (lsc && phy->ops.setup_internal_link)
1904                 return phy->ops.setup_internal_link(hw);
1905
1906         return 0;
1907 }
1908
1909 /**
1910  * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
1911  * @hw: pointer to hardware structure
1912  * @speed: link speed
1913  *
1914  * Configures the integrated KR PHY.
1915  **/
1916 static s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
1917                                        ixgbe_link_speed speed)
1918 {
1919         s32 status;
1920         u32 reg_val;
1921
1922         status = hw->mac.ops.read_iosf_sb_reg(hw,
1923                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1924                                         IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val);
1925         if (status)
1926                 return status;
1927
1928         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1929         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ |
1930                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC);
1931         reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
1932                      IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
1933
1934         /* Advertise 10G support. */
1935         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1936                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
1937
1938         /* Advertise 1G support. */
1939         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
1940                 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
1941
1942         /* Restart auto-negotiation. */
1943         reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1944         status = hw->mac.ops.write_iosf_sb_reg(hw,
1945                                         IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1946                                         IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1947
1948         return status;
1949 }
1950
1951 /** ixgbe_setup_kx4_x550em - Configure the KX4 PHY.
1952  *  @hw: pointer to hardware structure
1953  *
1954  *   Configures the integrated KX4 PHY.
1955  **/
1956 static s32 ixgbe_setup_kx4_x550em(struct ixgbe_hw *hw)
1957 {
1958         s32 status;
1959         u32 reg_val;
1960
1961         status = hw->mac.ops.read_iosf_sb_reg(hw, IXGBE_KX4_LINK_CNTL_1,
1962                                               IXGBE_SB_IOSF_TARGET_KX4_PCS0 +
1963                                               hw->bus.lan_id, &reg_val);
1964         if (status)
1965                 return status;
1966
1967         reg_val &= ~(IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4 |
1968                      IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX);
1969
1970         reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_ENABLE;
1971
1972         /* Advertise 10G support. */
1973         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1974                 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4;
1975
1976         /* Advertise 1G support. */
1977         if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1978                 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX;
1979
1980         /* Restart auto-negotiation. */
1981         reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART;
1982         status = hw->mac.ops.write_iosf_sb_reg(hw, IXGBE_KX4_LINK_CNTL_1,
1983                                                IXGBE_SB_IOSF_TARGET_KX4_PCS0 +
1984                                                hw->bus.lan_id, reg_val);
1985
1986         return status;
1987 }
1988
1989 /**
1990  * ixgbe_setup_kr_x550em - Configure the KR PHY
1991  * @hw: pointer to hardware structure
1992  *
1993  * Configures the integrated KR PHY for X550EM_x.
1994  **/
1995 static s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
1996 {
1997         if (hw->mac.type != ixgbe_mac_X550EM_x)
1998                 return 0;
1999
2000         return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
2001 }
2002
2003 /** ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
2004  *  @hw: address of hardware structure
2005  *  @link_up: address of boolean to indicate link status
2006  *
2007  *  Returns error code if unable to get link status.
2008  **/
2009 static s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
2010 {
2011         u32 ret;
2012         u16 autoneg_status;
2013
2014         *link_up = false;
2015
2016         /* read this twice back to back to indicate current status */
2017         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2018                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2019                                    &autoneg_status);
2020         if (ret)
2021                 return ret;
2022
2023         ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
2024                                    IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2025                                    &autoneg_status);
2026         if (ret)
2027                 return ret;
2028
2029         *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
2030
2031         return 0;
2032 }
2033
2034 /** ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
2035  *  @hw: point to hardware structure
2036  *
2037  *  Configures the link between the integrated KR PHY and the external X557 PHY
2038  *  The driver will call this function when it gets a link status change
2039  *  interrupt from the X557 PHY. This function configures the link speed
2040  *  between the PHYs to match the link speed of the BASE-T link.
2041  *
2042  * A return of a non-zero value indicates an error, and the base driver should
2043  * not report link up.
2044  **/
2045 static s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
2046 {
2047         ixgbe_link_speed force_speed;
2048         bool link_up;
2049         u32 status;
2050         u16 speed;
2051
2052         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2053                 return IXGBE_ERR_CONFIG;
2054
2055         if (hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE) {
2056                 speed = IXGBE_LINK_SPEED_10GB_FULL |
2057                         IXGBE_LINK_SPEED_1GB_FULL;
2058                 return ixgbe_setup_kr_speed_x550em(hw, speed);
2059         }
2060
2061         /* If link is not up, then there is no setup necessary so return  */
2062         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2063         if (status)
2064                 return status;
2065
2066         if (!link_up)
2067                 return 0;
2068
2069         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2070                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2071                                       &speed);
2072         if (status)
2073                 return status;
2074
2075         /* If link is not still up, then no setup is necessary so return */
2076         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2077         if (status)
2078                 return status;
2079
2080         if (!link_up)
2081                 return 0;
2082
2083         /* clear everything but the speed and duplex bits */
2084         speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
2085
2086         switch (speed) {
2087         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
2088                 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
2089                 break;
2090         case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
2091                 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
2092                 break;
2093         default:
2094                 /* Internal PHY does not support anything else */
2095                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
2096         }
2097
2098         return ixgbe_setup_ixfi_x550em(hw, &force_speed);
2099 }
2100
2101 /** ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
2102  *  @hw: pointer to hardware structure
2103  **/
2104 static s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
2105 {
2106         s32 status;
2107
2108         status = ixgbe_reset_phy_generic(hw);
2109
2110         if (status)
2111                 return status;
2112
2113         /* Configure Link Status Alarm and Temperature Threshold interrupts */
2114         return ixgbe_enable_lasi_ext_t_x550em(hw);
2115 }
2116
2117 /** ixgbe_get_lcd_x550em - Determine lowest common denominator
2118  *  @hw: pointer to hardware structure
2119  *  @lcd_speed: pointer to lowest common link speed
2120  *
2121  *  Determine lowest common link speed with link partner.
2122  **/
2123 static s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw,
2124                                   ixgbe_link_speed *lcd_speed)
2125 {
2126         u16 an_lp_status;
2127         s32 status;
2128         u16 word = hw->eeprom.ctrl_word_3;
2129
2130         *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
2131
2132         status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
2133                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2134                                       &an_lp_status);
2135         if (status)
2136                 return status;
2137
2138         /* If link partner advertised 1G, return 1G */
2139         if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
2140                 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
2141                 return status;
2142         }
2143
2144         /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
2145         if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
2146             (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
2147                 return status;
2148
2149         /* Link partner not capable of lower speeds, return 10G */
2150         *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
2151         return status;
2152 }
2153
2154 /**
2155  * ixgbe_setup_fc_x550em - Set up flow control
2156  * @hw: pointer to hardware structure
2157  */
2158 static s32 ixgbe_setup_fc_x550em(struct ixgbe_hw *hw)
2159 {
2160         bool pause, asm_dir;
2161         u32 reg_val;
2162         s32 rc;
2163
2164         /* Validate the requested mode */
2165         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
2166                 hw_err(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
2167                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
2168         }
2169
2170         /* 10gig parts do not have a word in the EEPROM to determine the
2171          * default flow control setting, so we explicitly set it to full.
2172          */
2173         if (hw->fc.requested_mode == ixgbe_fc_default)
2174                 hw->fc.requested_mode = ixgbe_fc_full;
2175
2176         /* Determine PAUSE and ASM_DIR bits. */
2177         switch (hw->fc.requested_mode) {
2178         case ixgbe_fc_none:
2179                 pause = false;
2180                 asm_dir = false;
2181                 break;
2182         case ixgbe_fc_tx_pause:
2183                 pause = false;
2184                 asm_dir = true;
2185                 break;
2186         case ixgbe_fc_rx_pause:
2187                 /* Rx Flow control is enabled and Tx Flow control is
2188                  * disabled by software override. Since there really
2189                  * isn't a way to advertise that we are capable of RX
2190                  * Pause ONLY, we will advertise that we support both
2191                  * symmetric and asymmetric Rx PAUSE, as such we fall
2192                  * through to the fc_full statement.  Later, we will
2193                  * disable the adapter's ability to send PAUSE frames.
2194                  */
2195                 /* Fallthrough */
2196         case ixgbe_fc_full:
2197                 pause = true;
2198                 asm_dir = true;
2199                 break;
2200         default:
2201                 hw_err(hw, "Flow control param set incorrectly\n");
2202                 return IXGBE_ERR_CONFIG;
2203         }
2204
2205         if (hw->device_id != IXGBE_DEV_ID_X550EM_X_KR &&
2206             hw->device_id != IXGBE_DEV_ID_X550EM_A_KR &&
2207             hw->device_id != IXGBE_DEV_ID_X550EM_A_KR_L)
2208                 return 0;
2209
2210         rc = hw->mac.ops.read_iosf_sb_reg(hw,
2211                                           IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2212                                           IXGBE_SB_IOSF_TARGET_KR_PHY,
2213                                           &reg_val);
2214         if (rc)
2215                 return rc;
2216
2217         reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
2218                      IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
2219         if (pause)
2220                 reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
2221         if (asm_dir)
2222                 reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
2223         rc = hw->mac.ops.write_iosf_sb_reg(hw,
2224                                            IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2225                                            IXGBE_SB_IOSF_TARGET_KR_PHY,
2226                                            reg_val);
2227
2228         /* This device does not fully support AN. */
2229         hw->fc.disable_fc_autoneg = true;
2230
2231         return rc;
2232 }
2233
2234 /** ixgbe_enter_lplu_x550em - Transition to low power states
2235  *  @hw: pointer to hardware structure
2236  *
2237  *  Configures Low Power Link Up on transition to low power states
2238  *  (from D0 to non-D0). Link is required to enter LPLU so avoid resetting
2239  *  the X557 PHY immediately prior to entering LPLU.
2240  **/
2241 static s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
2242 {
2243         u16 an_10g_cntl_reg, autoneg_reg, speed;
2244         s32 status;
2245         ixgbe_link_speed lcd_speed;
2246         u32 save_autoneg;
2247         bool link_up;
2248
2249         /* If blocked by MNG FW, then don't restart AN */
2250         if (ixgbe_check_reset_blocked(hw))
2251                 return 0;
2252
2253         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2254         if (status)
2255                 return status;
2256
2257         status = hw->eeprom.ops.read(hw, NVM_INIT_CTRL_3,
2258                                      &hw->eeprom.ctrl_word_3);
2259         if (status)
2260                 return status;
2261
2262         /* If link is down, LPLU disabled in NVM, WoL disabled, or
2263          * manageability disabled, then force link down by entering
2264          * low power mode.
2265          */
2266         if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
2267             !(hw->wol_enabled || ixgbe_mng_present(hw)))
2268                 return ixgbe_set_copper_phy_power(hw, false);
2269
2270         /* Determine LCD */
2271         status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
2272         if (status)
2273                 return status;
2274
2275         /* If no valid LCD link speed, then force link down and exit. */
2276         if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
2277                 return ixgbe_set_copper_phy_power(hw, false);
2278
2279         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2280                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2281                                       &speed);
2282         if (status)
2283                 return status;
2284
2285         /* If no link now, speed is invalid so take link down */
2286         status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2287         if (status)
2288                 return ixgbe_set_copper_phy_power(hw, false);
2289
2290         /* clear everything but the speed bits */
2291         speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
2292
2293         /* If current speed is already LCD, then exit. */
2294         if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
2295              (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
2296             ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
2297              (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
2298                 return status;
2299
2300         /* Clear AN completed indication */
2301         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
2302                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2303                                       &autoneg_reg);
2304         if (status)
2305                 return status;
2306
2307         status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
2308                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2309                                       &an_10g_cntl_reg);
2310         if (status)
2311                 return status;
2312
2313         status = hw->phy.ops.read_reg(hw,
2314                                       IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
2315                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2316                                       &autoneg_reg);
2317         if (status)
2318                 return status;
2319
2320         save_autoneg = hw->phy.autoneg_advertised;
2321
2322         /* Setup link at least common link speed */
2323         status = hw->mac.ops.setup_link(hw, lcd_speed, false);
2324
2325         /* restore autoneg from before setting lplu speed */
2326         hw->phy.autoneg_advertised = save_autoneg;
2327
2328         return status;
2329 }
2330
2331 /**
2332  * ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register
2333  * @hw: pointer to hardware structure
2334  *
2335  * Read NW_MNG_IF_SEL register and save field values.
2336  */
2337 static void ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw)
2338 {
2339         /* Save NW management interface connected on board. This is used
2340          * to determine internal PHY mode.
2341          */
2342         hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
2343
2344         /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set
2345          * PHY address. This register field was has only been used for X552.
2346          */
2347         if (!hw->phy.nw_mng_if_sel) {
2348                 if (hw->mac.type == ixgbe_mac_x550em_a) {
2349                         struct ixgbe_adapter *adapter = hw->back;
2350
2351                         e_warn(drv, "nw_mng_if_sel not set\n");
2352                 }
2353                 return;
2354         }
2355
2356         hw->phy.mdio.prtad = (hw->phy.nw_mng_if_sel &
2357                               IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
2358                              IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
2359 }
2360
2361 /** ixgbe_init_phy_ops_X550em - PHY/SFP specific init
2362  *  @hw: pointer to hardware structure
2363  *
2364  *  Initialize any function pointers that were not able to be
2365  *  set during init_shared_code because the PHY/SFP type was
2366  *  not known.  Perform the SFP init if necessary.
2367  **/
2368 static s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
2369 {
2370         struct ixgbe_phy_info *phy = &hw->phy;
2371         s32 ret_val;
2372
2373         hw->mac.ops.set_lan_id(hw);
2374
2375         ixgbe_read_mng_if_sel_x550em(hw);
2376
2377         if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
2378                 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2379                 ixgbe_setup_mux_ctl(hw);
2380         }
2381
2382         /* Identify the PHY or SFP module */
2383         ret_val = phy->ops.identify(hw);
2384
2385         /* Setup function pointers based on detected hardware */
2386         ixgbe_init_mac_link_ops_X550em(hw);
2387         if (phy->sfp_type != ixgbe_sfp_type_unknown)
2388                 phy->ops.reset = NULL;
2389
2390         /* Set functions pointers based on phy type */
2391         switch (hw->phy.type) {
2392         case ixgbe_phy_x550em_kx4:
2393                 phy->ops.setup_link = ixgbe_setup_kx4_x550em;
2394                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2395                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2396                 break;
2397         case ixgbe_phy_x550em_kr:
2398                 phy->ops.setup_link = ixgbe_setup_kr_x550em;
2399                 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2400                 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2401                 break;
2402         case ixgbe_phy_x550em_ext_t:
2403                 /* Save NW management interface connected on board. This is used
2404                  * to determine internal PHY mode
2405                  */
2406                 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
2407
2408                 /* If internal link mode is XFI, then setup iXFI internal link,
2409                  * else setup KR now.
2410                  */
2411                 phy->ops.setup_internal_link =
2412                                               ixgbe_setup_internal_phy_t_x550em;
2413
2414                 /* setup SW LPLU only for first revision */
2415                 if (hw->mac.type == ixgbe_mac_X550EM_x &&
2416                     !(IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0)) &
2417                       IXGBE_FUSES0_REV_MASK))
2418                         phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
2419
2420                 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
2421                 phy->ops.reset = ixgbe_reset_phy_t_X550em;
2422                 break;
2423         default:
2424                 break;
2425         }
2426
2427         return ret_val;
2428 }
2429
2430 /** ixgbe_get_media_type_X550em - Get media type
2431  *  @hw: pointer to hardware structure
2432  *
2433  *  Returns the media type (fiber, copper, backplane)
2434  *
2435  */
2436 static enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
2437 {
2438         enum ixgbe_media_type media_type;
2439
2440         /* Detect if there is a copper PHY attached. */
2441         switch (hw->device_id) {
2442         case IXGBE_DEV_ID_X550EM_A_SGMII:
2443         case IXGBE_DEV_ID_X550EM_A_SGMII_L:
2444                 hw->phy.type = ixgbe_phy_sgmii;
2445                 /* Fallthrough */
2446         case IXGBE_DEV_ID_X550EM_X_KR:
2447         case IXGBE_DEV_ID_X550EM_X_KX4:
2448         case IXGBE_DEV_ID_X550EM_A_KR:
2449         case IXGBE_DEV_ID_X550EM_A_KR_L:
2450                 media_type = ixgbe_media_type_backplane;
2451                 break;
2452         case IXGBE_DEV_ID_X550EM_X_SFP:
2453         case IXGBE_DEV_ID_X550EM_A_SFP:
2454         case IXGBE_DEV_ID_X550EM_A_SFP_N:
2455                 media_type = ixgbe_media_type_fiber;
2456                 break;
2457         case IXGBE_DEV_ID_X550EM_X_1G_T:
2458         case IXGBE_DEV_ID_X550EM_X_10G_T:
2459                 media_type = ixgbe_media_type_copper;
2460                 break;
2461         default:
2462                 media_type = ixgbe_media_type_unknown;
2463                 break;
2464         }
2465         return media_type;
2466 }
2467
2468 /** ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
2469  ** @hw: pointer to hardware structure
2470  **/
2471 static s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
2472 {
2473         s32 status;
2474         u16 reg;
2475
2476         status = hw->phy.ops.read_reg(hw,
2477                                       IXGBE_MDIO_TX_VENDOR_ALARMS_3,
2478                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
2479                                       &reg);
2480         if (status)
2481                 return status;
2482
2483         /* If PHY FW reset completed bit is set then this is the first
2484          * SW instance after a power on so the PHY FW must be un-stalled.
2485          */
2486         if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
2487                 status = hw->phy.ops.read_reg(hw,
2488                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2489                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2490                                         &reg);
2491                 if (status)
2492                         return status;
2493
2494                 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
2495
2496                 status = hw->phy.ops.write_reg(hw,
2497                                         IXGBE_MDIO_GLOBAL_RES_PR_10,
2498                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2499                                         reg);
2500                 if (status)
2501                         return status;
2502         }
2503
2504         return status;
2505 }
2506
2507 /**
2508  * ixgbe_set_mdio_speed - Set MDIO clock speed
2509  * @hw: pointer to hardware structure
2510  */
2511 static void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
2512 {
2513         u32 hlreg0;
2514
2515         switch (hw->device_id) {
2516         case IXGBE_DEV_ID_X550EM_X_10G_T:
2517         case IXGBE_DEV_ID_X550EM_A_SFP:
2518                 /* Config MDIO clock speed before the first MDIO PHY access */
2519                 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2520                 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
2521                 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2522                 break;
2523         default:
2524                 break;
2525         }
2526 }
2527
2528 /**  ixgbe_reset_hw_X550em - Perform hardware reset
2529  **  @hw: pointer to hardware structure
2530  **
2531  **  Resets the hardware by resetting the transmit and receive units, masks
2532  **  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
2533  **  reset.
2534  **/
2535 static s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
2536 {
2537         ixgbe_link_speed link_speed;
2538         s32 status;
2539         u32 ctrl = 0;
2540         u32 i;
2541         bool link_up = false;
2542
2543         /* Call adapter stop to disable Tx/Rx and clear interrupts */
2544         status = hw->mac.ops.stop_adapter(hw);
2545         if (status)
2546                 return status;
2547
2548         /* flush pending Tx transactions */
2549         ixgbe_clear_tx_pending(hw);
2550
2551         /* PHY ops must be identified and initialized prior to reset */
2552
2553         /* Identify PHY and related function pointers */
2554         status = hw->phy.ops.init(hw);
2555
2556         /* start the external PHY */
2557         if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
2558                 status = ixgbe_init_ext_t_x550em(hw);
2559                 if (status)
2560                         return status;
2561         }
2562
2563         /* Setup SFP module if there is one present. */
2564         if (hw->phy.sfp_setup_needed) {
2565                 status = hw->mac.ops.setup_sfp(hw);
2566                 hw->phy.sfp_setup_needed = false;
2567         }
2568
2569         /* Reset PHY */
2570         if (!hw->phy.reset_disable && hw->phy.ops.reset)
2571                 hw->phy.ops.reset(hw);
2572
2573 mac_reset_top:
2574         /* Issue global reset to the MAC.  Needs to be SW reset if link is up.
2575          * If link reset is used when link is up, it might reset the PHY when
2576          * mng is using it.  If link is down or the flag to force full link
2577          * reset is set, then perform link reset.
2578          */
2579         ctrl = IXGBE_CTRL_LNK_RST;
2580
2581         if (!hw->force_full_reset) {
2582                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
2583                 if (link_up)
2584                         ctrl = IXGBE_CTRL_RST;
2585         }
2586
2587         ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
2588         IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
2589         IXGBE_WRITE_FLUSH(hw);
2590         usleep_range(1000, 1200);
2591
2592         /* Poll for reset bit to self-clear meaning reset is complete */
2593         for (i = 0; i < 10; i++) {
2594                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
2595                 if (!(ctrl & IXGBE_CTRL_RST_MASK))
2596                         break;
2597                 udelay(1);
2598         }
2599
2600         if (ctrl & IXGBE_CTRL_RST_MASK) {
2601                 status = IXGBE_ERR_RESET_FAILED;
2602                 hw_dbg(hw, "Reset polling failed to complete.\n");
2603         }
2604
2605         msleep(50);
2606
2607         /* Double resets are required for recovery from certain error
2608          * clear the multicast table.  Also reset num_rar_entries to 128,
2609          * since we modify this value when programming the SAN MAC address.
2610          */
2611         if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
2612                 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2613                 goto mac_reset_top;
2614         }
2615
2616         /* Store the permanent mac address */
2617         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
2618
2619         /* Store MAC address from RAR0, clear receive address registers, and
2620          * clear the multicast table.  Also reset num_rar_entries to 128,
2621          * since we modify this value when programming the SAN MAC address.
2622          */
2623         hw->mac.num_rar_entries = 128;
2624         hw->mac.ops.init_rx_addrs(hw);
2625
2626         ixgbe_set_mdio_speed(hw);
2627
2628         if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2629                 ixgbe_setup_mux_ctl(hw);
2630
2631         return status;
2632 }
2633
2634 /** ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype
2635  *      anti-spoofing
2636  *  @hw:  pointer to hardware structure
2637  *  @enable: enable or disable switch for Ethertype anti-spoofing
2638  *  @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
2639  **/
2640 static void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
2641                                                    bool enable, int vf)
2642 {
2643         int vf_target_reg = vf >> 3;
2644         int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
2645         u32 pfvfspoof;
2646
2647         pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
2648         if (enable)
2649                 pfvfspoof |= BIT(vf_target_shift);
2650         else
2651                 pfvfspoof &= ~BIT(vf_target_shift);
2652
2653         IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
2654 }
2655
2656 /** ixgbe_set_source_address_pruning_X550 - Enable/Disbale src address pruning
2657  *  @hw: pointer to hardware structure
2658  *  @enable: enable or disable source address pruning
2659  *  @pool: Rx pool to set source address pruning for
2660  **/
2661 static void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw,
2662                                                   bool enable,
2663                                                   unsigned int pool)
2664 {
2665         u64 pfflp;
2666
2667         /* max rx pool is 63 */
2668         if (pool > 63)
2669                 return;
2670
2671         pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
2672         pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
2673
2674         if (enable)
2675                 pfflp |= (1ULL << pool);
2676         else
2677                 pfflp &= ~(1ULL << pool);
2678
2679         IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
2680         IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
2681 }
2682
2683 /**
2684  * ixgbe_set_mux - Set mux for port 1 access with CS4227
2685  * @hw: pointer to hardware structure
2686  * @state: set mux if 1, clear if 0
2687  */
2688 static void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
2689 {
2690         u32 esdp;
2691
2692         if (!hw->bus.lan_id)
2693                 return;
2694         esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2695         if (state)
2696                 esdp |= IXGBE_ESDP_SDP1;
2697         else
2698                 esdp &= ~IXGBE_ESDP_SDP1;
2699         IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2700         IXGBE_WRITE_FLUSH(hw);
2701 }
2702
2703 /**
2704  * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
2705  * @hw: pointer to hardware structure
2706  * @mask: Mask to specify which semaphore to acquire
2707  *
2708  * Acquires the SWFW semaphore and sets the I2C MUX
2709  */
2710 static s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2711 {
2712         s32 status;
2713
2714         status = ixgbe_acquire_swfw_sync_X540(hw, mask);
2715         if (status)
2716                 return status;
2717
2718         if (mask & IXGBE_GSSR_I2C_MASK)
2719                 ixgbe_set_mux(hw, 1);
2720
2721         return 0;
2722 }
2723
2724 /**
2725  * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
2726  * @hw: pointer to hardware structure
2727  * @mask: Mask to specify which semaphore to release
2728  *
2729  * Releases the SWFW semaphore and sets the I2C MUX
2730  */
2731 static void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
2732 {
2733         if (mask & IXGBE_GSSR_I2C_MASK)
2734                 ixgbe_set_mux(hw, 0);
2735
2736         ixgbe_release_swfw_sync_X540(hw, mask);
2737 }
2738
2739 /**
2740  * ixgbe_acquire_swfw_sync_x550em_a - Acquire SWFW semaphore
2741  * @hw: pointer to hardware structure
2742  * @mask: Mask to specify which semaphore to acquire
2743  *
2744  * Acquires the SWFW semaphore and get the shared PHY token as needed
2745  */
2746 static s32 ixgbe_acquire_swfw_sync_x550em_a(struct ixgbe_hw *hw, u32 mask)
2747 {
2748         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
2749         int retries = FW_PHY_TOKEN_RETRIES;
2750         s32 status;
2751
2752         while (--retries) {
2753                 status = 0;
2754                 if (hmask)
2755                         status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
2756                 if (status)
2757                         return status;
2758                 if (!(mask & IXGBE_GSSR_TOKEN_SM))
2759                         return 0;
2760
2761                 status = ixgbe_get_phy_token(hw);
2762                 if (!status)
2763                         return 0;
2764                 if (hmask)
2765                         ixgbe_release_swfw_sync_X540(hw, hmask);
2766                 if (status != IXGBE_ERR_TOKEN_RETRY)
2767                         return status;
2768                 msleep(FW_PHY_TOKEN_DELAY);
2769         }
2770
2771         return status;
2772 }
2773
2774 /**
2775  * ixgbe_release_swfw_sync_x550em_a - Release SWFW semaphore
2776  * @hw: pointer to hardware structure
2777  * @mask: Mask to specify which semaphore to release
2778  *
2779  * Release the SWFW semaphore and puts the shared PHY token as needed
2780  */
2781 static void ixgbe_release_swfw_sync_x550em_a(struct ixgbe_hw *hw, u32 mask)
2782 {
2783         u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
2784
2785         if (mask & IXGBE_GSSR_TOKEN_SM)
2786                 ixgbe_put_phy_token(hw);
2787
2788         if (hmask)
2789                 ixgbe_release_swfw_sync_X540(hw, hmask);
2790 }
2791
2792 /**
2793  * ixgbe_read_phy_reg_x550a - Reads specified PHY register
2794  * @hw: pointer to hardware structure
2795  * @reg_addr: 32 bit address of PHY register to read
2796  * @phy_data: Pointer to read data from PHY register
2797  *
2798  * Reads a value from a specified PHY register using the SWFW lock and PHY
2799  * Token. The PHY Token is needed since the MDIO is shared between to MAC
2800  * instances.
2801  */
2802 static s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
2803                                     u32 device_type, u16 *phy_data)
2804 {
2805         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
2806         s32 status;
2807
2808         if (hw->mac.ops.acquire_swfw_sync(hw, mask))
2809                 return IXGBE_ERR_SWFW_SYNC;
2810
2811         status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
2812
2813         hw->mac.ops.release_swfw_sync(hw, mask);
2814
2815         return status;
2816 }
2817
2818 /**
2819  * ixgbe_write_phy_reg_x550a - Writes specified PHY register
2820  * @hw: pointer to hardware structure
2821  * @reg_addr: 32 bit PHY register to write
2822  * @device_type: 5 bit device type
2823  * @phy_data: Data to write to the PHY register
2824  *
2825  * Writes a value to specified PHY register using the SWFW lock and PHY Token.
2826  * The PHY Token is needed since the MDIO is shared between to MAC instances.
2827  */
2828 static s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
2829                                      u32 device_type, u16 phy_data)
2830 {
2831         u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
2832         s32 status;
2833
2834         if (hw->mac.ops.acquire_swfw_sync(hw, mask))
2835                 return IXGBE_ERR_SWFW_SYNC;
2836
2837         status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type, phy_data);
2838         hw->mac.ops.release_swfw_sync(hw, mask);
2839
2840         return status;
2841 }
2842
2843 #define X550_COMMON_MAC \
2844         .init_hw                        = &ixgbe_init_hw_generic, \
2845         .start_hw                       = &ixgbe_start_hw_X540, \
2846         .clear_hw_cntrs                 = &ixgbe_clear_hw_cntrs_generic, \
2847         .enable_rx_dma                  = &ixgbe_enable_rx_dma_generic, \
2848         .get_mac_addr                   = &ixgbe_get_mac_addr_generic, \
2849         .get_device_caps                = &ixgbe_get_device_caps_generic, \
2850         .stop_adapter                   = &ixgbe_stop_adapter_generic, \
2851         .set_lan_id                     = &ixgbe_set_lan_id_multi_port_pcie, \
2852         .read_analog_reg8               = NULL, \
2853         .write_analog_reg8              = NULL, \
2854         .set_rxpba                      = &ixgbe_set_rxpba_generic, \
2855         .check_link                     = &ixgbe_check_mac_link_generic, \
2856         .led_on                         = &ixgbe_led_on_generic, \
2857         .led_off                        = &ixgbe_led_off_generic, \
2858         .blink_led_start                = &ixgbe_blink_led_start_X540, \
2859         .blink_led_stop                 = &ixgbe_blink_led_stop_X540, \
2860         .set_rar                        = &ixgbe_set_rar_generic, \
2861         .clear_rar                      = &ixgbe_clear_rar_generic, \
2862         .set_vmdq                       = &ixgbe_set_vmdq_generic, \
2863         .set_vmdq_san_mac               = &ixgbe_set_vmdq_san_mac_generic, \
2864         .clear_vmdq                     = &ixgbe_clear_vmdq_generic, \
2865         .init_rx_addrs                  = &ixgbe_init_rx_addrs_generic, \
2866         .update_mc_addr_list            = &ixgbe_update_mc_addr_list_generic, \
2867         .enable_mc                      = &ixgbe_enable_mc_generic, \
2868         .disable_mc                     = &ixgbe_disable_mc_generic, \
2869         .clear_vfta                     = &ixgbe_clear_vfta_generic, \
2870         .set_vfta                       = &ixgbe_set_vfta_generic, \
2871         .fc_enable                      = &ixgbe_fc_enable_generic, \
2872         .set_fw_drv_ver                 = &ixgbe_set_fw_drv_ver_generic, \
2873         .init_uta_tables                = &ixgbe_init_uta_tables_generic, \
2874         .set_mac_anti_spoofing          = &ixgbe_set_mac_anti_spoofing, \
2875         .set_vlan_anti_spoofing         = &ixgbe_set_vlan_anti_spoofing, \
2876         .set_source_address_pruning     = \
2877                                 &ixgbe_set_source_address_pruning_X550, \
2878         .set_ethertype_anti_spoofing    = \
2879                                 &ixgbe_set_ethertype_anti_spoofing_X550, \
2880         .disable_rx_buff                = &ixgbe_disable_rx_buff_generic, \
2881         .enable_rx_buff                 = &ixgbe_enable_rx_buff_generic, \
2882         .get_thermal_sensor_data        = NULL, \
2883         .init_thermal_sensor_thresh     = NULL, \
2884         .enable_rx                      = &ixgbe_enable_rx_generic, \
2885         .disable_rx                     = &ixgbe_disable_rx_x550, \
2886
2887 static const struct ixgbe_mac_operations mac_ops_X550 = {
2888         X550_COMMON_MAC
2889         .reset_hw               = &ixgbe_reset_hw_X540,
2890         .get_media_type         = &ixgbe_get_media_type_X540,
2891         .get_san_mac_addr       = &ixgbe_get_san_mac_addr_generic,
2892         .get_wwn_prefix         = &ixgbe_get_wwn_prefix_generic,
2893         .setup_link             = &ixgbe_setup_mac_link_X540,
2894         .get_link_capabilities  = &ixgbe_get_copper_link_capabilities_generic,
2895         .get_bus_info           = &ixgbe_get_bus_info_generic,
2896         .setup_sfp              = NULL,
2897         .acquire_swfw_sync      = &ixgbe_acquire_swfw_sync_X540,
2898         .release_swfw_sync      = &ixgbe_release_swfw_sync_X540,
2899         .init_swfw_sync         = &ixgbe_init_swfw_sync_X540,
2900         .prot_autoc_read        = prot_autoc_read_generic,
2901         .prot_autoc_write       = prot_autoc_write_generic,
2902         .setup_fc               = ixgbe_setup_fc_generic,
2903 };
2904
2905 static const struct ixgbe_mac_operations mac_ops_X550EM_x = {
2906         X550_COMMON_MAC
2907         .reset_hw               = &ixgbe_reset_hw_X550em,
2908         .get_media_type         = &ixgbe_get_media_type_X550em,
2909         .get_san_mac_addr       = NULL,
2910         .get_wwn_prefix         = NULL,
2911         .setup_link             = &ixgbe_setup_mac_link_X540,
2912         .get_link_capabilities  = &ixgbe_get_link_capabilities_X550em,
2913         .get_bus_info           = &ixgbe_get_bus_info_X550em,
2914         .setup_sfp              = ixgbe_setup_sfp_modules_X550em,
2915         .acquire_swfw_sync      = &ixgbe_acquire_swfw_sync_X550em,
2916         .release_swfw_sync      = &ixgbe_release_swfw_sync_X550em,
2917         .init_swfw_sync         = &ixgbe_init_swfw_sync_X540,
2918         .setup_fc               = NULL, /* defined later */
2919         .read_iosf_sb_reg       = ixgbe_read_iosf_sb_reg_x550,
2920         .write_iosf_sb_reg      = ixgbe_write_iosf_sb_reg_x550,
2921 };
2922
2923 static struct ixgbe_mac_operations mac_ops_x550em_a = {
2924         X550_COMMON_MAC
2925         .reset_hw               = ixgbe_reset_hw_X550em,
2926         .get_media_type         = ixgbe_get_media_type_X550em,
2927         .get_san_mac_addr       = NULL,
2928         .get_wwn_prefix         = NULL,
2929         .setup_link             = NULL, /* defined later */
2930         .get_link_capabilities  = ixgbe_get_link_capabilities_X550em,
2931         .get_bus_info           = ixgbe_get_bus_info_X550em,
2932         .setup_sfp              = ixgbe_setup_sfp_modules_X550em,
2933         .acquire_swfw_sync      = ixgbe_acquire_swfw_sync_x550em_a,
2934         .release_swfw_sync      = ixgbe_release_swfw_sync_x550em_a,
2935         .setup_fc               = ixgbe_setup_fc_x550em,
2936         .read_iosf_sb_reg       = ixgbe_read_iosf_sb_reg_x550a,
2937         .write_iosf_sb_reg      = ixgbe_write_iosf_sb_reg_x550a,
2938 };
2939
2940 #define X550_COMMON_EEP \
2941         .read                   = &ixgbe_read_ee_hostif_X550, \
2942         .read_buffer            = &ixgbe_read_ee_hostif_buffer_X550, \
2943         .write                  = &ixgbe_write_ee_hostif_X550, \
2944         .write_buffer           = &ixgbe_write_ee_hostif_buffer_X550, \
2945         .validate_checksum      = &ixgbe_validate_eeprom_checksum_X550, \
2946         .update_checksum        = &ixgbe_update_eeprom_checksum_X550, \
2947         .calc_checksum          = &ixgbe_calc_eeprom_checksum_X550, \
2948
2949 static const struct ixgbe_eeprom_operations eeprom_ops_X550 = {
2950         X550_COMMON_EEP
2951         .init_params            = &ixgbe_init_eeprom_params_X550,
2952 };
2953
2954 static const struct ixgbe_eeprom_operations eeprom_ops_X550EM_x = {
2955         X550_COMMON_EEP
2956         .init_params            = &ixgbe_init_eeprom_params_X540,
2957 };
2958
2959 #define X550_COMMON_PHY \
2960         .identify_sfp           = &ixgbe_identify_module_generic, \
2961         .reset                  = NULL, \
2962         .setup_link_speed       = &ixgbe_setup_phy_link_speed_generic, \
2963         .read_i2c_byte          = &ixgbe_read_i2c_byte_generic, \
2964         .write_i2c_byte         = &ixgbe_write_i2c_byte_generic, \
2965         .read_i2c_sff8472       = &ixgbe_read_i2c_sff8472_generic, \
2966         .read_i2c_eeprom        = &ixgbe_read_i2c_eeprom_generic, \
2967         .write_i2c_eeprom       = &ixgbe_write_i2c_eeprom_generic, \
2968         .setup_link             = &ixgbe_setup_phy_link_generic, \
2969         .set_phy_power          = NULL, \
2970         .check_overtemp         = &ixgbe_tn_check_overtemp, \
2971         .get_firmware_version   = &ixgbe_get_phy_firmware_version_generic,
2972
2973 static const struct ixgbe_phy_operations phy_ops_X550 = {
2974         X550_COMMON_PHY
2975         .init                   = NULL,
2976         .identify               = &ixgbe_identify_phy_generic,
2977         .read_reg               = &ixgbe_read_phy_reg_generic,
2978         .write_reg              = &ixgbe_write_phy_reg_generic,
2979 };
2980
2981 static const struct ixgbe_phy_operations phy_ops_X550EM_x = {
2982         X550_COMMON_PHY
2983         .init                   = &ixgbe_init_phy_ops_X550em,
2984         .identify               = &ixgbe_identify_phy_x550em,
2985         .read_reg               = &ixgbe_read_phy_reg_generic,
2986         .write_reg              = &ixgbe_write_phy_reg_generic,
2987         .read_i2c_combined      = &ixgbe_read_i2c_combined_generic,
2988         .write_i2c_combined     = &ixgbe_write_i2c_combined_generic,
2989         .read_i2c_combined_unlocked = &ixgbe_read_i2c_combined_generic_unlocked,
2990         .write_i2c_combined_unlocked =
2991                                      &ixgbe_write_i2c_combined_generic_unlocked,
2992 };
2993
2994 static const struct ixgbe_phy_operations phy_ops_x550em_a = {
2995         X550_COMMON_PHY
2996         .init                   = &ixgbe_init_phy_ops_X550em,
2997         .identify               = &ixgbe_identify_phy_x550em,
2998         .read_reg               = &ixgbe_read_phy_reg_x550a,
2999         .write_reg              = &ixgbe_write_phy_reg_x550a,
3000 };
3001
3002 static const u32 ixgbe_mvals_X550[IXGBE_MVALS_IDX_LIMIT] = {
3003         IXGBE_MVALS_INIT(X550)
3004 };
3005
3006 static const u32 ixgbe_mvals_X550EM_x[IXGBE_MVALS_IDX_LIMIT] = {
3007         IXGBE_MVALS_INIT(X550EM_x)
3008 };
3009
3010 static const u32 ixgbe_mvals_x550em_a[IXGBE_MVALS_IDX_LIMIT] = {
3011         IXGBE_MVALS_INIT(X550EM_a)
3012 };
3013
3014 const struct ixgbe_info ixgbe_X550_info = {
3015         .mac                    = ixgbe_mac_X550,
3016         .get_invariants         = &ixgbe_get_invariants_X540,
3017         .mac_ops                = &mac_ops_X550,
3018         .eeprom_ops             = &eeprom_ops_X550,
3019         .phy_ops                = &phy_ops_X550,
3020         .mbx_ops                = &mbx_ops_generic,
3021         .mvals                  = ixgbe_mvals_X550,
3022 };
3023
3024 const struct ixgbe_info ixgbe_X550EM_x_info = {
3025         .mac                    = ixgbe_mac_X550EM_x,
3026         .get_invariants         = &ixgbe_get_invariants_X550_x,
3027         .mac_ops                = &mac_ops_X550EM_x,
3028         .eeprom_ops             = &eeprom_ops_X550EM_x,
3029         .phy_ops                = &phy_ops_X550EM_x,
3030         .mbx_ops                = &mbx_ops_generic,
3031         .mvals                  = ixgbe_mvals_X550EM_x,
3032 };
3033
3034 const struct ixgbe_info ixgbe_x550em_a_info = {
3035         .mac                    = ixgbe_mac_x550em_a,
3036         .get_invariants         = &ixgbe_get_invariants_X550_x,
3037         .mac_ops                = &mac_ops_x550em_a,
3038         .eeprom_ops             = &eeprom_ops_X550EM_x,
3039         .phy_ops                = &phy_ops_x550em_a,
3040         .mbx_ops                = &mbx_ops_generic,
3041         .mvals                  = ixgbe_mvals_x550em_a,
3042 };