2 * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs.
4 * Copyright (C) 2012 Marvell
6 * Rami Rosen <rosenr@marvell.com>
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
14 #include <linux/kernel.h>
15 #include <linux/netdevice.h>
16 #include <linux/etherdevice.h>
17 #include <linux/platform_device.h>
18 #include <linux/skbuff.h>
19 #include <linux/inetdevice.h>
20 #include <linux/mbus.h>
21 #include <linux/module.h>
22 #include <linux/interrupt.h>
23 #include <linux/if_vlan.h>
29 #include <linux/of_irq.h>
30 #include <linux/of_mdio.h>
31 #include <linux/of_net.h>
32 #include <linux/of_address.h>
33 #include <linux/phy.h>
34 #include <linux/clk.h>
37 #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2))
38 #define MVNETA_RXQ_HW_BUF_ALLOC BIT(1)
39 #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8)
40 #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8)
41 #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2))
42 #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16)
43 #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2))
44 #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2))
45 #define MVNETA_RXQ_BUF_SIZE_SHIFT 19
46 #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19)
47 #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2))
48 #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff
49 #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2))
50 #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16
51 #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255
52 #define MVNETA_PORT_RX_RESET 0x1cc0
53 #define MVNETA_PORT_RX_DMA_RESET BIT(0)
54 #define MVNETA_PHY_ADDR 0x2000
55 #define MVNETA_PHY_ADDR_MASK 0x1f
56 #define MVNETA_MBUS_RETRY 0x2010
57 #define MVNETA_UNIT_INTR_CAUSE 0x2080
58 #define MVNETA_UNIT_CONTROL 0x20B0
59 #define MVNETA_PHY_POLLING_ENABLE BIT(1)
60 #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3))
61 #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3))
62 #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2))
63 #define MVNETA_BASE_ADDR_ENABLE 0x2290
64 #define MVNETA_PORT_CONFIG 0x2400
65 #define MVNETA_UNI_PROMISC_MODE BIT(0)
66 #define MVNETA_DEF_RXQ(q) ((q) << 1)
67 #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4)
68 #define MVNETA_TX_UNSET_ERR_SUM BIT(12)
69 #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16)
70 #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19)
71 #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22)
72 #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25)
73 #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \
74 MVNETA_DEF_RXQ_ARP(q) | \
75 MVNETA_DEF_RXQ_TCP(q) | \
76 MVNETA_DEF_RXQ_UDP(q) | \
77 MVNETA_DEF_RXQ_BPDU(q) | \
78 MVNETA_TX_UNSET_ERR_SUM | \
79 MVNETA_RX_CSUM_WITH_PSEUDO_HDR)
80 #define MVNETA_PORT_CONFIG_EXTEND 0x2404
81 #define MVNETA_MAC_ADDR_LOW 0x2414
82 #define MVNETA_MAC_ADDR_HIGH 0x2418
83 #define MVNETA_SDMA_CONFIG 0x241c
84 #define MVNETA_SDMA_BRST_SIZE_16 4
85 #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1)
86 #define MVNETA_RX_NO_DATA_SWAP BIT(4)
87 #define MVNETA_TX_NO_DATA_SWAP BIT(5)
88 #define MVNETA_DESC_SWAP BIT(6)
89 #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22)
90 #define MVNETA_PORT_STATUS 0x2444
91 #define MVNETA_TX_IN_PRGRS BIT(1)
92 #define MVNETA_TX_FIFO_EMPTY BIT(8)
93 #define MVNETA_RX_MIN_FRAME_SIZE 0x247c
94 #define MVNETA_SERDES_CFG 0x24A0
95 #define MVNETA_SGMII_SERDES_PROTO 0x0cc7
96 #define MVNETA_QSGMII_SERDES_PROTO 0x0667
97 #define MVNETA_TYPE_PRIO 0x24bc
98 #define MVNETA_FORCE_UNI BIT(21)
99 #define MVNETA_TXQ_CMD_1 0x24e4
100 #define MVNETA_TXQ_CMD 0x2448
101 #define MVNETA_TXQ_DISABLE_SHIFT 8
102 #define MVNETA_TXQ_ENABLE_MASK 0x000000ff
103 #define MVNETA_GMAC_CLOCK_DIVIDER 0x24f4
104 #define MVNETA_GMAC_1MS_CLOCK_ENABLE BIT(31)
105 #define MVNETA_ACC_MODE 0x2500
106 #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2))
107 #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff
108 #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00
109 #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2))
111 /* Exception Interrupt Port/Queue Cause register */
113 #define MVNETA_INTR_NEW_CAUSE 0x25a0
114 #define MVNETA_INTR_NEW_MASK 0x25a4
116 /* bits 0..7 = TXQ SENT, one bit per queue.
117 * bits 8..15 = RXQ OCCUP, one bit per queue.
118 * bits 16..23 = RXQ FREE, one bit per queue.
119 * bit 29 = OLD_REG_SUM, see old reg ?
120 * bit 30 = TX_ERR_SUM, one bit for 4 ports
121 * bit 31 = MISC_SUM, one bit for 4 ports
123 #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0)
124 #define MVNETA_TX_INTR_MASK_ALL (0xff << 0)
125 #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8)
126 #define MVNETA_RX_INTR_MASK_ALL (0xff << 8)
127 #define MVNETA_MISCINTR_INTR_MASK BIT(31)
129 #define MVNETA_INTR_OLD_CAUSE 0x25a8
130 #define MVNETA_INTR_OLD_MASK 0x25ac
132 /* Data Path Port/Queue Cause Register */
133 #define MVNETA_INTR_MISC_CAUSE 0x25b0
134 #define MVNETA_INTR_MISC_MASK 0x25b4
136 #define MVNETA_CAUSE_PHY_STATUS_CHANGE BIT(0)
137 #define MVNETA_CAUSE_LINK_CHANGE BIT(1)
138 #define MVNETA_CAUSE_PTP BIT(4)
140 #define MVNETA_CAUSE_INTERNAL_ADDR_ERR BIT(7)
141 #define MVNETA_CAUSE_RX_OVERRUN BIT(8)
142 #define MVNETA_CAUSE_RX_CRC_ERROR BIT(9)
143 #define MVNETA_CAUSE_RX_LARGE_PKT BIT(10)
144 #define MVNETA_CAUSE_TX_UNDERUN BIT(11)
145 #define MVNETA_CAUSE_PRBS_ERR BIT(12)
146 #define MVNETA_CAUSE_PSC_SYNC_CHANGE BIT(13)
147 #define MVNETA_CAUSE_SERDES_SYNC_ERR BIT(14)
149 #define MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT 16
150 #define MVNETA_CAUSE_BMU_ALLOC_ERR_ALL_MASK (0xF << MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT)
151 #define MVNETA_CAUSE_BMU_ALLOC_ERR_MASK(pool) (1 << (MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT + (pool)))
153 #define MVNETA_CAUSE_TXQ_ERROR_SHIFT 24
154 #define MVNETA_CAUSE_TXQ_ERROR_ALL_MASK (0xFF << MVNETA_CAUSE_TXQ_ERROR_SHIFT)
155 #define MVNETA_CAUSE_TXQ_ERROR_MASK(q) (1 << (MVNETA_CAUSE_TXQ_ERROR_SHIFT + (q)))
157 #define MVNETA_INTR_ENABLE 0x25b8
158 #define MVNETA_TXQ_INTR_ENABLE_ALL_MASK 0x0000ff00
159 #define MVNETA_RXQ_INTR_ENABLE_ALL_MASK 0xff000000 // note: neta says it's 0x000000FF
161 #define MVNETA_RXQ_CMD 0x2680
162 #define MVNETA_RXQ_DISABLE_SHIFT 8
163 #define MVNETA_RXQ_ENABLE_MASK 0x000000ff
164 #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4))
165 #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4))
166 #define MVNETA_GMAC_CTRL_0 0x2c00
167 #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2
168 #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc
169 #define MVNETA_GMAC0_PORT_ENABLE BIT(0)
170 #define MVNETA_GMAC_CTRL_2 0x2c08
171 #define MVNETA_GMAC2_INBAND_AN_ENABLE BIT(0)
172 #define MVNETA_GMAC2_PCS_ENABLE BIT(3)
173 #define MVNETA_GMAC2_PORT_RGMII BIT(4)
174 #define MVNETA_GMAC2_PORT_RESET BIT(6)
175 #define MVNETA_GMAC_STATUS 0x2c10
176 #define MVNETA_GMAC_LINK_UP BIT(0)
177 #define MVNETA_GMAC_SPEED_1000 BIT(1)
178 #define MVNETA_GMAC_SPEED_100 BIT(2)
179 #define MVNETA_GMAC_FULL_DUPLEX BIT(3)
180 #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4)
181 #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5)
182 #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6)
183 #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7)
184 #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c
185 #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0)
186 #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1)
187 #define MVNETA_GMAC_INBAND_AN_ENABLE BIT(2)
188 #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5)
189 #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6)
190 #define MVNETA_GMAC_AN_SPEED_EN BIT(7)
191 #define MVNETA_GMAC_AN_FLOW_CTRL_EN BIT(11)
192 #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12)
193 #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13)
194 #define MVNETA_MIB_COUNTERS_BASE 0x3080
195 #define MVNETA_MIB_LATE_COLLISION 0x7c
196 #define MVNETA_DA_FILT_SPEC_MCAST 0x3400
197 #define MVNETA_DA_FILT_OTH_MCAST 0x3500
198 #define MVNETA_DA_FILT_UCAST_BASE 0x3600
199 #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2))
200 #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2))
201 #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000
202 #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16)
203 #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2))
204 #define MVNETA_TXQ_DEC_SENT_SHIFT 16
205 #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2))
206 #define MVNETA_TXQ_SENT_DESC_SHIFT 16
207 #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000
208 #define MVNETA_PORT_TX_RESET 0x3cf0
209 #define MVNETA_PORT_TX_DMA_RESET BIT(0)
210 #define MVNETA_TX_MTU 0x3e0c
211 #define MVNETA_TX_TOKEN_SIZE 0x3e14
212 #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff
213 #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2))
214 #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff
216 #define MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
218 /* Descriptor ring Macros */
219 #define MVNETA_QUEUE_NEXT_DESC(q, index) \
220 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
222 /* Various constants */
225 #define MVNETA_TXDONE_COAL_PKTS 1
226 #define MVNETA_RX_COAL_PKTS 32
227 #define MVNETA_RX_COAL_USEC 100
229 /* The two bytes Marvell header. Either contains a special value used
230 * by Marvell switches when a specific hardware mode is enabled (not
231 * supported by this driver) or is filled automatically by zeroes on
232 * the RX side. Those two bytes being at the front of the Ethernet
233 * header, they allow to have the IP header aligned on a 4 bytes
234 * boundary automatically: the hardware skips those two bytes on its
237 #define MVNETA_MH_SIZE 2
239 #define MVNETA_VLAN_TAG_LEN 4
241 #define MVNETA_CPU_D_CACHE_LINE_SIZE 32
242 #define MVNETA_TX_CSUM_MAX_SIZE 9800
243 #define MVNETA_ACC_MODE_EXT 1
245 /* Timeout constants */
246 #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000
247 #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000
248 #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000
250 #define MVNETA_TX_MTU_MAX 0x3ffff
252 /* TSO header size */
253 #define TSO_HEADER_SIZE 128
255 /* Max number of Rx descriptors */
256 #define MVNETA_MAX_RXD 128
258 /* Max number of Tx descriptors */
259 #define MVNETA_MAX_TXD 532
261 /* Max number of allowed TCP segments for software TSO */
262 #define MVNETA_MAX_TSO_SEGS 100
264 #define MVNETA_MAX_SKB_DESCS (MVNETA_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
266 /* descriptor aligned size */
267 #define MVNETA_DESC_ALIGNED_SIZE 32
269 #define MVNETA_RX_PKT_SIZE(mtu) \
270 ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \
271 ETH_HLEN + ETH_FCS_LEN, \
272 MVNETA_CPU_D_CACHE_LINE_SIZE)
274 #define IS_TSO_HEADER(txq, addr) \
275 ((addr >= txq->tso_hdrs_phys) && \
276 (addr < txq->tso_hdrs_phys + txq->size * TSO_HEADER_SIZE))
278 #define MVNETA_RX_BUF_SIZE(pkt_size) ((pkt_size) + NET_SKB_PAD)
280 struct mvneta_pcpu_stats {
281 struct u64_stats_sync syncp;
290 unsigned int frag_size;
292 struct mvneta_rx_queue *rxqs;
293 struct mvneta_tx_queue *txqs;
294 struct net_device *dev;
297 struct napi_struct napi;
304 struct mvneta_pcpu_stats *stats;
306 struct mii_bus *mii_bus;
307 struct phy_device *phy_dev;
308 phy_interface_t phy_interface;
309 struct device_node *phy_node;
313 int use_inband_status:1;
316 /* The mvneta_tx_desc and mvneta_rx_desc structures describe the
317 * layout of the transmit and reception DMA descriptors, and their
318 * layout is therefore defined by the hardware design
321 #define MVNETA_TX_L3_OFF_SHIFT 0
322 #define MVNETA_TX_IP_HLEN_SHIFT 8
323 #define MVNETA_TX_L4_UDP BIT(16)
324 #define MVNETA_TX_L3_IP6 BIT(17)
325 #define MVNETA_TXD_IP_CSUM BIT(18)
326 #define MVNETA_TXD_Z_PAD BIT(19)
327 #define MVNETA_TXD_L_DESC BIT(20)
328 #define MVNETA_TXD_F_DESC BIT(21)
329 #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \
330 MVNETA_TXD_L_DESC | \
332 #define MVNETA_TX_L4_CSUM_FULL BIT(30)
333 #define MVNETA_TX_L4_CSUM_NOT BIT(31)
335 #define MVNETA_RXD_ERR_CRC 0x0
336 #define MVNETA_RXD_ERR_SUMMARY BIT(16)
337 #define MVNETA_RXD_ERR_OVERRUN BIT(17)
338 #define MVNETA_RXD_ERR_LEN BIT(18)
339 #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18))
340 #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18))
341 #define MVNETA_RXD_L3_IP4 BIT(25)
342 #define MVNETA_RXD_FIRST_LAST_DESC (BIT(26) | BIT(27))
343 #define MVNETA_RXD_L4_CSUM_OK BIT(30)
345 #if defined(__LITTLE_ENDIAN)
346 struct mvneta_tx_desc {
347 u32 command; /* Options used by HW for packet transmitting.*/
348 u16 reserverd1; /* csum_l4 (for future use) */
349 u16 data_size; /* Data size of transmitted packet in bytes */
350 u32 buf_phys_addr; /* Physical addr of transmitted buffer */
351 u32 reserved2; /* hw_cmd - (for future use, PMT) */
352 u32 reserved3[4]; /* Reserved - (for future use) */
355 struct mvneta_rx_desc {
356 u32 status; /* Info about received packet */
357 u16 reserved1; /* pnc_info - (for future use, PnC) */
358 u16 data_size; /* Size of received packet in bytes */
360 u32 buf_phys_addr; /* Physical address of the buffer */
361 u32 reserved2; /* pnc_flow_id (for future use, PnC) */
363 u32 buf_cookie; /* cookie for access to RX buffer in rx path */
364 u16 reserved3; /* prefetch_cmd, for future use */
365 u16 reserved4; /* csum_l4 - (for future use, PnC) */
367 u32 reserved5; /* pnc_extra PnC (for future use, PnC) */
368 u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */
371 struct mvneta_tx_desc {
372 u16 data_size; /* Data size of transmitted packet in bytes */
373 u16 reserverd1; /* csum_l4 (for future use) */
374 u32 command; /* Options used by HW for packet transmitting.*/
375 u32 reserved2; /* hw_cmd - (for future use, PMT) */
376 u32 buf_phys_addr; /* Physical addr of transmitted buffer */
377 u32 reserved3[4]; /* Reserved - (for future use) */
380 struct mvneta_rx_desc {
381 u16 data_size; /* Size of received packet in bytes */
382 u16 reserved1; /* pnc_info - (for future use, PnC) */
383 u32 status; /* Info about received packet */
385 u32 reserved2; /* pnc_flow_id (for future use, PnC) */
386 u32 buf_phys_addr; /* Physical address of the buffer */
388 u16 reserved4; /* csum_l4 - (for future use, PnC) */
389 u16 reserved3; /* prefetch_cmd, for future use */
390 u32 buf_cookie; /* cookie for access to RX buffer in rx path */
392 u32 reserved5; /* pnc_extra PnC (for future use, PnC) */
393 u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */
397 struct mvneta_tx_queue {
398 /* Number of this TX queue, in the range 0-7 */
401 /* Number of TX DMA descriptors in the descriptor ring */
404 /* Number of currently used TX DMA descriptor in the
408 int tx_stop_threshold;
409 int tx_wake_threshold;
411 /* Array of transmitted skb */
412 struct sk_buff **tx_skb;
414 /* Index of last TX DMA descriptor that was inserted */
417 /* Index of the TX DMA descriptor to be cleaned up */
422 /* Virtual address of the TX DMA descriptors array */
423 struct mvneta_tx_desc *descs;
425 /* DMA address of the TX DMA descriptors array */
426 dma_addr_t descs_phys;
428 /* Index of the last TX DMA descriptor */
431 /* Index of the next TX DMA descriptor to process */
432 int next_desc_to_proc;
434 /* DMA buffers for TSO headers */
437 /* DMA address of TSO headers */
438 dma_addr_t tso_hdrs_phys;
441 struct mvneta_rx_queue {
442 /* rx queue number, in the range 0-7 */
445 /* num of rx descriptors in the rx descriptor ring */
448 /* counter of times when mvneta_refill() failed */
454 /* Virtual address of the RX DMA descriptors array */
455 struct mvneta_rx_desc *descs;
457 /* DMA address of the RX DMA descriptors array */
458 dma_addr_t descs_phys;
460 /* Index of the last RX DMA descriptor */
463 /* Index of the next RX DMA descriptor to process */
464 int next_desc_to_proc;
467 /* The hardware supports eight (8) rx queues, but we are only allowing
468 * the first one to be used. Therefore, let's just allocate one queue.
470 static int rxq_number = 1;
471 static int txq_number = 8;
475 static int rx_copybreak __read_mostly = 256;
477 #define MVNETA_DRIVER_NAME "mvneta"
478 #define MVNETA_DRIVER_VERSION "1.0"
480 /* Utility/helper methods */
482 /* Write helper method */
483 static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data)
485 writel(data, pp->base + offset);
488 /* Read helper method */
489 static u32 mvreg_read(struct mvneta_port *pp, u32 offset)
491 return readl(pp->base + offset);
494 /* Increment txq get counter */
495 static void mvneta_txq_inc_get(struct mvneta_tx_queue *txq)
497 txq->txq_get_index++;
498 if (txq->txq_get_index == txq->size)
499 txq->txq_get_index = 0;
502 /* Increment txq put counter */
503 static void mvneta_txq_inc_put(struct mvneta_tx_queue *txq)
505 txq->txq_put_index++;
506 if (txq->txq_put_index == txq->size)
507 txq->txq_put_index = 0;
511 /* Clear all MIB counters */
512 static void mvneta_mib_counters_clear(struct mvneta_port *pp)
517 /* Perform dummy reads from MIB counters */
518 for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4)
519 dummy = mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i));
522 /* Get System Network Statistics */
523 struct rtnl_link_stats64 *mvneta_get_stats64(struct net_device *dev,
524 struct rtnl_link_stats64 *stats)
526 struct mvneta_port *pp = netdev_priv(dev);
530 for_each_possible_cpu(cpu) {
531 struct mvneta_pcpu_stats *cpu_stats;
537 cpu_stats = per_cpu_ptr(pp->stats, cpu);
539 start = u64_stats_fetch_begin_irq(&cpu_stats->syncp);
540 rx_packets = cpu_stats->rx_packets;
541 rx_bytes = cpu_stats->rx_bytes;
542 tx_packets = cpu_stats->tx_packets;
543 tx_bytes = cpu_stats->tx_bytes;
544 } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start));
546 stats->rx_packets += rx_packets;
547 stats->rx_bytes += rx_bytes;
548 stats->tx_packets += tx_packets;
549 stats->tx_bytes += tx_bytes;
552 stats->rx_errors = dev->stats.rx_errors;
553 stats->rx_dropped = dev->stats.rx_dropped;
555 stats->tx_dropped = dev->stats.tx_dropped;
560 /* Rx descriptors helper methods */
562 /* Checks whether the RX descriptor having this status is both the first
563 * and the last descriptor for the RX packet. Each RX packet is currently
564 * received through a single RX descriptor, so not having each RX
565 * descriptor with its first and last bits set is an error
567 static int mvneta_rxq_desc_is_first_last(u32 status)
569 return (status & MVNETA_RXD_FIRST_LAST_DESC) ==
570 MVNETA_RXD_FIRST_LAST_DESC;
573 /* Add number of descriptors ready to receive new packets */
574 static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp,
575 struct mvneta_rx_queue *rxq,
578 /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can
581 while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) {
582 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
583 (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX <<
584 MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
585 ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX;
588 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id),
589 (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT));
592 /* Get number of RX descriptors occupied by received packets */
593 static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp,
594 struct mvneta_rx_queue *rxq)
598 val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id));
599 return val & MVNETA_RXQ_OCCUPIED_ALL_MASK;
602 /* Update num of rx desc called upon return from rx path or
603 * from mvneta_rxq_drop_pkts().
605 static void mvneta_rxq_desc_num_update(struct mvneta_port *pp,
606 struct mvneta_rx_queue *rxq,
607 int rx_done, int rx_filled)
611 if ((rx_done <= 0xff) && (rx_filled <= 0xff)) {
613 (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT);
614 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
618 /* Only 255 descriptors can be added at once */
619 while ((rx_done > 0) || (rx_filled > 0)) {
620 if (rx_done <= 0xff) {
627 if (rx_filled <= 0xff) {
628 val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
631 val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT;
634 mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val);
638 /* Get pointer to next RX descriptor to be processed by SW */
639 static struct mvneta_rx_desc *
640 mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq)
642 int rx_desc = rxq->next_desc_to_proc;
644 rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc);
645 prefetch(rxq->descs + rxq->next_desc_to_proc);
646 return rxq->descs + rx_desc;
649 /* Change maximum receive size of the port. */
650 static void mvneta_max_rx_size_set(struct mvneta_port *pp, int max_rx_size)
654 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
655 val &= ~MVNETA_GMAC_MAX_RX_SIZE_MASK;
656 val |= ((max_rx_size - MVNETA_MH_SIZE) / 2) <<
657 MVNETA_GMAC_MAX_RX_SIZE_SHIFT;
658 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
662 /* Set rx queue offset */
663 static void mvneta_rxq_offset_set(struct mvneta_port *pp,
664 struct mvneta_rx_queue *rxq,
669 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
670 val &= ~MVNETA_RXQ_PKT_OFFSET_ALL_MASK;
673 val |= MVNETA_RXQ_PKT_OFFSET_MASK(offset >> 3);
674 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
678 /* Tx descriptors helper methods */
680 /* Update HW with number of TX descriptors to be sent */
681 static void mvneta_txq_pend_desc_add(struct mvneta_port *pp,
682 struct mvneta_tx_queue *txq,
687 /* Only 255 descriptors can be added at once ; Assume caller
688 * process TX desriptors in quanta less than 256
691 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
694 /* Get pointer to next TX descriptor to be processed (send) by HW */
695 static struct mvneta_tx_desc *
696 mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq)
698 int tx_desc = txq->next_desc_to_proc;
700 txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc);
701 return txq->descs + tx_desc;
704 /* Release the last allocated TX descriptor. Useful to handle DMA
705 * mapping failures in the TX path.
707 static void mvneta_txq_desc_put(struct mvneta_tx_queue *txq)
709 if (txq->next_desc_to_proc == 0)
710 txq->next_desc_to_proc = txq->last_desc - 1;
712 txq->next_desc_to_proc--;
715 /* Set rxq buf size */
716 static void mvneta_rxq_buf_size_set(struct mvneta_port *pp,
717 struct mvneta_rx_queue *rxq,
722 val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id));
724 val &= ~MVNETA_RXQ_BUF_SIZE_MASK;
725 val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT);
727 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val);
730 /* Disable buffer management (BM) */
731 static void mvneta_rxq_bm_disable(struct mvneta_port *pp,
732 struct mvneta_rx_queue *rxq)
736 val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id));
737 val &= ~MVNETA_RXQ_HW_BUF_ALLOC;
738 mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val);
741 /* Start the Ethernet port RX and TX activity */
742 static void mvneta_port_up(struct mvneta_port *pp)
747 /* Enable all initialized TXs. */
748 mvneta_mib_counters_clear(pp);
750 for (queue = 0; queue < txq_number; queue++) {
751 struct mvneta_tx_queue *txq = &pp->txqs[queue];
752 if (txq->descs != NULL)
753 q_map |= (1 << queue);
755 mvreg_write(pp, MVNETA_TXQ_CMD, q_map);
757 /* Enable all initialized RXQs. */
759 for (queue = 0; queue < rxq_number; queue++) {
760 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
761 if (rxq->descs != NULL)
762 q_map |= (1 << queue);
765 mvreg_write(pp, MVNETA_RXQ_CMD, q_map);
768 /* Stop the Ethernet port activity */
769 static void mvneta_port_down(struct mvneta_port *pp)
774 /* Stop Rx port activity. Check port Rx activity. */
775 val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK;
777 /* Issue stop command for active channels only */
779 mvreg_write(pp, MVNETA_RXQ_CMD,
780 val << MVNETA_RXQ_DISABLE_SHIFT);
782 /* Wait for all Rx activity to terminate. */
785 if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) {
787 "TIMEOUT for RX stopped ! rx_queue_cmd: 0x08%x\n",
793 val = mvreg_read(pp, MVNETA_RXQ_CMD);
794 } while (val & 0xff);
796 /* Stop Tx port activity. Check port Tx activity. Issue stop
797 * command for active channels only
799 val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK;
802 mvreg_write(pp, MVNETA_TXQ_CMD,
803 (val << MVNETA_TXQ_DISABLE_SHIFT));
805 /* Wait for all Tx activity to terminate. */
808 if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) {
810 "TIMEOUT for TX stopped status=0x%08x\n",
816 /* Check TX Command reg that all Txqs are stopped */
817 val = mvreg_read(pp, MVNETA_TXQ_CMD);
819 } while (val & 0xff);
821 /* Double check to verify that TX FIFO is empty */
824 if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) {
826 "TX FIFO empty timeout status=0x08%x\n",
832 val = mvreg_read(pp, MVNETA_PORT_STATUS);
833 } while (!(val & MVNETA_TX_FIFO_EMPTY) &&
834 (val & MVNETA_TX_IN_PRGRS));
839 /* Enable the port by setting the port enable bit of the MAC control register */
840 static void mvneta_port_enable(struct mvneta_port *pp)
845 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
846 val |= MVNETA_GMAC0_PORT_ENABLE;
847 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
850 /* Disable the port and wait for about 200 usec before retuning */
851 static void mvneta_port_disable(struct mvneta_port *pp)
855 /* Reset the Enable bit in the Serial Control Register */
856 val = mvreg_read(pp, MVNETA_GMAC_CTRL_0);
857 val &= ~MVNETA_GMAC0_PORT_ENABLE;
858 mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
863 /* Multicast tables methods */
865 /* Set all entries in Unicast MAC Table; queue==-1 means reject all */
866 static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue)
874 val = 0x1 | (queue << 1);
875 val |= (val << 24) | (val << 16) | (val << 8);
878 for (offset = 0; offset <= 0xc; offset += 4)
879 mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val);
882 /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */
883 static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue)
891 val = 0x1 | (queue << 1);
892 val |= (val << 24) | (val << 16) | (val << 8);
895 for (offset = 0; offset <= 0xfc; offset += 4)
896 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val);
900 /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */
901 static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue)
907 memset(pp->mcast_count, 0, sizeof(pp->mcast_count));
910 memset(pp->mcast_count, 1, sizeof(pp->mcast_count));
911 val = 0x1 | (queue << 1);
912 val |= (val << 24) | (val << 16) | (val << 8);
915 for (offset = 0; offset <= 0xfc; offset += 4)
916 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val);
919 /* This method sets defaults to the NETA port:
920 * Clears interrupt Cause and Mask registers.
921 * Clears all MAC tables.
922 * Sets defaults to all registers.
923 * Resets RX and TX descriptor rings.
925 * This method can be called after mvneta_port_down() to return the port
926 * settings to defaults.
928 static void mvneta_defaults_set(struct mvneta_port *pp)
934 /* Clear all Cause registers */
935 mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0);
936 mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0);
937 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
939 /* Mask all interrupts */
940 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
941 mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
942 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
943 mvreg_write(pp, MVNETA_INTR_ENABLE, 0);
945 /* Enable MBUS Retry bit16 */
946 mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20);
948 /* Set CPU queue access map - all CPUs have access to all RX
949 * queues and to all TX queues
951 for (cpu = 0; cpu < CONFIG_NR_CPUS; cpu++)
952 mvreg_write(pp, MVNETA_CPU_MAP(cpu),
953 (MVNETA_CPU_RXQ_ACCESS_ALL_MASK |
954 MVNETA_CPU_TXQ_ACCESS_ALL_MASK));
956 /* Reset RX and TX DMAs */
957 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
958 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
960 /* Disable Legacy WRR, Disable EJP, Release from reset */
961 mvreg_write(pp, MVNETA_TXQ_CMD_1, 0);
962 for (queue = 0; queue < txq_number; queue++) {
963 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0);
964 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0);
967 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
968 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
970 /* Set Port Acceleration Mode */
971 val = MVNETA_ACC_MODE_EXT;
972 mvreg_write(pp, MVNETA_ACC_MODE, val);
974 /* Update val of portCfg register accordingly with all RxQueue types */
975 val = MVNETA_PORT_CONFIG_DEFL_VALUE(rxq_def);
976 mvreg_write(pp, MVNETA_PORT_CONFIG, val);
979 mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val);
980 mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64);
982 /* Build PORT_SDMA_CONFIG_REG */
985 /* Default burst size */
986 val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
987 val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16);
988 val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP;
990 #if defined(__BIG_ENDIAN)
991 val |= MVNETA_DESC_SWAP;
994 /* Assign port SDMA configuration */
995 mvreg_write(pp, MVNETA_SDMA_CONFIG, val);
997 /* Disable PHY polling in hardware, since we're using the
998 * kernel phylib to do this.
1000 val = mvreg_read(pp, MVNETA_UNIT_CONTROL);
1001 val &= ~MVNETA_PHY_POLLING_ENABLE;
1002 mvreg_write(pp, MVNETA_UNIT_CONTROL, val);
1004 if (pp->use_inband_status) {
1005 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
1006 val &= ~(MVNETA_GMAC_FORCE_LINK_PASS |
1007 MVNETA_GMAC_FORCE_LINK_DOWN |
1008 MVNETA_GMAC_AN_FLOW_CTRL_EN);
1009 val |= MVNETA_GMAC_INBAND_AN_ENABLE |
1010 MVNETA_GMAC_AN_SPEED_EN |
1011 MVNETA_GMAC_AN_DUPLEX_EN;
1012 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
1013 val = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER);
1014 val |= MVNETA_GMAC_1MS_CLOCK_ENABLE;
1015 mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, val);
1018 mvneta_set_ucast_table(pp, -1);
1019 mvneta_set_special_mcast_table(pp, -1);
1020 mvneta_set_other_mcast_table(pp, -1);
1022 /* Set port interrupt enable register - default enable all */
1023 mvreg_write(pp, MVNETA_INTR_ENABLE,
1024 (MVNETA_RXQ_INTR_ENABLE_ALL_MASK
1025 | MVNETA_TXQ_INTR_ENABLE_ALL_MASK));
1028 /* Set max sizes for tx queues */
1029 static void mvneta_txq_max_tx_size_set(struct mvneta_port *pp, int max_tx_size)
1035 mtu = max_tx_size * 8;
1036 if (mtu > MVNETA_TX_MTU_MAX)
1037 mtu = MVNETA_TX_MTU_MAX;
1040 val = mvreg_read(pp, MVNETA_TX_MTU);
1041 val &= ~MVNETA_TX_MTU_MAX;
1043 mvreg_write(pp, MVNETA_TX_MTU, val);
1045 /* TX token size and all TXQs token size must be larger that MTU */
1046 val = mvreg_read(pp, MVNETA_TX_TOKEN_SIZE);
1048 size = val & MVNETA_TX_TOKEN_SIZE_MAX;
1051 val &= ~MVNETA_TX_TOKEN_SIZE_MAX;
1053 mvreg_write(pp, MVNETA_TX_TOKEN_SIZE, val);
1055 for (queue = 0; queue < txq_number; queue++) {
1056 val = mvreg_read(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue));
1058 size = val & MVNETA_TXQ_TOKEN_SIZE_MAX;
1061 val &= ~MVNETA_TXQ_TOKEN_SIZE_MAX;
1063 mvreg_write(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue), val);
1068 /* Set unicast address */
1069 static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble,
1072 unsigned int unicast_reg;
1073 unsigned int tbl_offset;
1074 unsigned int reg_offset;
1076 /* Locate the Unicast table entry */
1077 last_nibble = (0xf & last_nibble);
1079 /* offset from unicast tbl base */
1080 tbl_offset = (last_nibble / 4) * 4;
1082 /* offset within the above reg */
1083 reg_offset = last_nibble % 4;
1085 unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset));
1088 /* Clear accepts frame bit at specified unicast DA tbl entry */
1089 unicast_reg &= ~(0xff << (8 * reg_offset));
1091 unicast_reg &= ~(0xff << (8 * reg_offset));
1092 unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
1095 mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg);
1098 /* Set mac address */
1099 static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr,
1106 mac_l = (addr[4] << 8) | (addr[5]);
1107 mac_h = (addr[0] << 24) | (addr[1] << 16) |
1108 (addr[2] << 8) | (addr[3] << 0);
1110 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l);
1111 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h);
1114 /* Accept frames of this address */
1115 mvneta_set_ucast_addr(pp, addr[5], queue);
1118 /* Set the number of packets that will be received before RX interrupt
1119 * will be generated by HW.
1121 static void mvneta_rx_pkts_coal_set(struct mvneta_port *pp,
1122 struct mvneta_rx_queue *rxq, u32 value)
1124 mvreg_write(pp, MVNETA_RXQ_THRESHOLD_REG(rxq->id),
1125 value | MVNETA_RXQ_NON_OCCUPIED(0));
1126 rxq->pkts_coal = value;
1129 /* Set the time delay in usec before RX interrupt will be generated by
1132 static void mvneta_rx_time_coal_set(struct mvneta_port *pp,
1133 struct mvneta_rx_queue *rxq, u32 value)
1136 unsigned long clk_rate;
1138 clk_rate = clk_get_rate(pp->clk);
1139 val = (clk_rate / 1000000) * value;
1141 mvreg_write(pp, MVNETA_RXQ_TIME_COAL_REG(rxq->id), val);
1142 rxq->time_coal = value;
1145 /* Set threshold for TX_DONE pkts coalescing */
1146 static void mvneta_tx_done_pkts_coal_set(struct mvneta_port *pp,
1147 struct mvneta_tx_queue *txq, u32 value)
1151 val = mvreg_read(pp, MVNETA_TXQ_SIZE_REG(txq->id));
1153 val &= ~MVNETA_TXQ_SENT_THRESH_ALL_MASK;
1154 val |= MVNETA_TXQ_SENT_THRESH_MASK(value);
1156 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), val);
1158 txq->done_pkts_coal = value;
1161 /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */
1162 static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc,
1163 u32 phys_addr, u32 cookie)
1165 rx_desc->buf_cookie = cookie;
1166 rx_desc->buf_phys_addr = phys_addr;
1169 /* Decrement sent descriptors counter */
1170 static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp,
1171 struct mvneta_tx_queue *txq,
1176 /* Only 255 TX descriptors can be updated at once */
1177 while (sent_desc > 0xff) {
1178 val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT;
1179 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
1180 sent_desc = sent_desc - 0xff;
1183 val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT;
1184 mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val);
1187 /* Get number of TX descriptors already sent by HW */
1188 static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp,
1189 struct mvneta_tx_queue *txq)
1194 val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id));
1195 sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >>
1196 MVNETA_TXQ_SENT_DESC_SHIFT;
1201 /* Get number of sent descriptors and decrement counter.
1202 * The number of sent descriptors is returned.
1204 static int mvneta_txq_sent_desc_proc(struct mvneta_port *pp,
1205 struct mvneta_tx_queue *txq)
1209 /* Get number of sent descriptors */
1210 sent_desc = mvneta_txq_sent_desc_num_get(pp, txq);
1212 /* Decrement sent descriptors counter */
1214 mvneta_txq_sent_desc_dec(pp, txq, sent_desc);
1219 /* Set TXQ descriptors fields relevant for CSUM calculation */
1220 static u32 mvneta_txq_desc_csum(int l3_offs, int l3_proto,
1221 int ip_hdr_len, int l4_proto)
1225 /* Fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk,
1226 * G_L4_chk, L4_type; required only for checksum
1229 command = l3_offs << MVNETA_TX_L3_OFF_SHIFT;
1230 command |= ip_hdr_len << MVNETA_TX_IP_HLEN_SHIFT;
1232 if (l3_proto == htons(ETH_P_IP))
1233 command |= MVNETA_TXD_IP_CSUM;
1235 command |= MVNETA_TX_L3_IP6;
1237 if (l4_proto == IPPROTO_TCP)
1238 command |= MVNETA_TX_L4_CSUM_FULL;
1239 else if (l4_proto == IPPROTO_UDP)
1240 command |= MVNETA_TX_L4_UDP | MVNETA_TX_L4_CSUM_FULL;
1242 command |= MVNETA_TX_L4_CSUM_NOT;
1248 /* Display more error info */
1249 static void mvneta_rx_error(struct mvneta_port *pp,
1250 struct mvneta_rx_desc *rx_desc)
1252 u32 status = rx_desc->status;
1254 if (!mvneta_rxq_desc_is_first_last(status)) {
1256 "bad rx status %08x (buffer oversize), size=%d\n",
1257 status, rx_desc->data_size);
1261 switch (status & MVNETA_RXD_ERR_CODE_MASK) {
1262 case MVNETA_RXD_ERR_CRC:
1263 netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n",
1264 status, rx_desc->data_size);
1266 case MVNETA_RXD_ERR_OVERRUN:
1267 netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n",
1268 status, rx_desc->data_size);
1270 case MVNETA_RXD_ERR_LEN:
1271 netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n",
1272 status, rx_desc->data_size);
1274 case MVNETA_RXD_ERR_RESOURCE:
1275 netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n",
1276 status, rx_desc->data_size);
1281 /* Handle RX checksum offload based on the descriptor's status */
1282 static void mvneta_rx_csum(struct mvneta_port *pp, u32 status,
1283 struct sk_buff *skb)
1285 if ((status & MVNETA_RXD_L3_IP4) &&
1286 (status & MVNETA_RXD_L4_CSUM_OK)) {
1288 skb->ip_summed = CHECKSUM_UNNECESSARY;
1292 skb->ip_summed = CHECKSUM_NONE;
1295 /* Return tx queue pointer (find last set bit) according to <cause> returned
1296 * form tx_done reg. <cause> must not be null. The return value is always a
1297 * valid queue for matching the first one found in <cause>.
1299 static struct mvneta_tx_queue *mvneta_tx_done_policy(struct mvneta_port *pp,
1302 int queue = fls(cause) - 1;
1304 return &pp->txqs[queue];
1307 /* Free tx queue skbuffs */
1308 static void mvneta_txq_bufs_free(struct mvneta_port *pp,
1309 struct mvneta_tx_queue *txq, int num)
1313 for (i = 0; i < num; i++) {
1314 struct mvneta_tx_desc *tx_desc = txq->descs +
1316 struct sk_buff *skb = txq->tx_skb[txq->txq_get_index];
1318 mvneta_txq_inc_get(txq);
1320 if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr))
1321 dma_unmap_single(pp->dev->dev.parent,
1322 tx_desc->buf_phys_addr,
1323 tx_desc->data_size, DMA_TO_DEVICE);
1326 dev_kfree_skb_any(skb);
1330 /* Handle end of transmission */
1331 static void mvneta_txq_done(struct mvneta_port *pp,
1332 struct mvneta_tx_queue *txq)
1334 struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id);
1337 tx_done = mvneta_txq_sent_desc_proc(pp, txq);
1341 mvneta_txq_bufs_free(pp, txq, tx_done);
1343 txq->count -= tx_done;
1345 if (netif_tx_queue_stopped(nq)) {
1346 if (txq->count <= txq->tx_wake_threshold)
1347 netif_tx_wake_queue(nq);
1351 static void *mvneta_frag_alloc(const struct mvneta_port *pp)
1353 if (likely(pp->frag_size <= PAGE_SIZE))
1354 return netdev_alloc_frag(pp->frag_size);
1356 return kmalloc(pp->frag_size, GFP_ATOMIC);
1359 static void mvneta_frag_free(const struct mvneta_port *pp, void *data)
1361 if (likely(pp->frag_size <= PAGE_SIZE))
1362 skb_free_frag(data);
1367 /* Refill processing */
1368 static int mvneta_rx_refill(struct mvneta_port *pp,
1369 struct mvneta_rx_desc *rx_desc)
1372 dma_addr_t phys_addr;
1375 data = mvneta_frag_alloc(pp);
1379 phys_addr = dma_map_single(pp->dev->dev.parent, data,
1380 MVNETA_RX_BUF_SIZE(pp->pkt_size),
1382 if (unlikely(dma_mapping_error(pp->dev->dev.parent, phys_addr))) {
1383 mvneta_frag_free(pp, data);
1387 mvneta_rx_desc_fill(rx_desc, phys_addr, (u32)data);
1391 /* Handle tx checksum */
1392 static u32 mvneta_skb_tx_csum(struct mvneta_port *pp, struct sk_buff *skb)
1394 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1396 __be16 l3_proto = vlan_get_protocol(skb);
1399 if (l3_proto == htons(ETH_P_IP)) {
1400 struct iphdr *ip4h = ip_hdr(skb);
1402 /* Calculate IPv4 checksum and L4 checksum */
1403 ip_hdr_len = ip4h->ihl;
1404 l4_proto = ip4h->protocol;
1405 } else if (l3_proto == htons(ETH_P_IPV6)) {
1406 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1408 /* Read l4_protocol from one of IPv6 extra headers */
1409 if (skb_network_header_len(skb) > 0)
1410 ip_hdr_len = (skb_network_header_len(skb) >> 2);
1411 l4_proto = ip6h->nexthdr;
1413 return MVNETA_TX_L4_CSUM_NOT;
1415 return mvneta_txq_desc_csum(skb_network_offset(skb),
1416 l3_proto, ip_hdr_len, l4_proto);
1419 return MVNETA_TX_L4_CSUM_NOT;
1422 /* Returns rx queue pointer (find last set bit) according to causeRxTx
1425 static struct mvneta_rx_queue *mvneta_rx_policy(struct mvneta_port *pp,
1428 int queue = fls(cause >> 8) - 1;
1430 return (queue < 0 || queue >= rxq_number) ? NULL : &pp->rxqs[queue];
1433 /* Drop packets received by the RXQ and free buffers */
1434 static void mvneta_rxq_drop_pkts(struct mvneta_port *pp,
1435 struct mvneta_rx_queue *rxq)
1439 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
1440 for (i = 0; i < rxq->size; i++) {
1441 struct mvneta_rx_desc *rx_desc = rxq->descs + i;
1442 void *data = (void *)rx_desc->buf_cookie;
1444 mvneta_frag_free(pp, data);
1445 dma_unmap_single(pp->dev->dev.parent, rx_desc->buf_phys_addr,
1446 MVNETA_RX_BUF_SIZE(pp->pkt_size), DMA_FROM_DEVICE);
1450 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
1453 /* Main rx processing */
1454 static int mvneta_rx(struct mvneta_port *pp, int rx_todo,
1455 struct mvneta_rx_queue *rxq)
1457 struct net_device *dev = pp->dev;
1458 int rx_done, rx_filled;
1462 /* Get number of received packets */
1463 rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
1465 if (rx_todo > rx_done)
1471 /* Fairness NAPI loop */
1472 while (rx_done < rx_todo) {
1473 struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq);
1474 struct sk_buff *skb;
1475 unsigned char *data;
1481 rx_status = rx_desc->status;
1482 rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE);
1483 data = (unsigned char *)rx_desc->buf_cookie;
1485 if (!mvneta_rxq_desc_is_first_last(rx_status) ||
1486 (rx_status & MVNETA_RXD_ERR_SUMMARY)) {
1488 dev->stats.rx_errors++;
1489 mvneta_rx_error(pp, rx_desc);
1490 /* leave the descriptor untouched */
1494 if (rx_bytes <= rx_copybreak) {
1495 /* better copy a small frame and not unmap the DMA region */
1496 skb = netdev_alloc_skb_ip_align(dev, rx_bytes);
1498 goto err_drop_frame;
1500 dma_sync_single_range_for_cpu(dev->dev.parent,
1501 rx_desc->buf_phys_addr,
1502 MVNETA_MH_SIZE + NET_SKB_PAD,
1505 memcpy(skb_put(skb, rx_bytes),
1506 data + MVNETA_MH_SIZE + NET_SKB_PAD,
1509 skb->protocol = eth_type_trans(skb, dev);
1510 mvneta_rx_csum(pp, rx_status, skb);
1511 napi_gro_receive(&pp->napi, skb);
1514 rcvd_bytes += rx_bytes;
1516 /* leave the descriptor and buffer untouched */
1520 skb = build_skb(data, pp->frag_size > PAGE_SIZE ? 0 : pp->frag_size);
1522 goto err_drop_frame;
1524 dma_unmap_single(dev->dev.parent, rx_desc->buf_phys_addr,
1525 MVNETA_RX_BUF_SIZE(pp->pkt_size), DMA_FROM_DEVICE);
1528 rcvd_bytes += rx_bytes;
1530 /* Linux processing */
1531 skb_reserve(skb, MVNETA_MH_SIZE + NET_SKB_PAD);
1532 skb_put(skb, rx_bytes);
1534 skb->protocol = eth_type_trans(skb, dev);
1536 mvneta_rx_csum(pp, rx_status, skb);
1538 napi_gro_receive(&pp->napi, skb);
1540 /* Refill processing */
1541 err = mvneta_rx_refill(pp, rx_desc);
1543 netdev_err(dev, "Linux processing - Can't refill\n");
1550 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
1552 u64_stats_update_begin(&stats->syncp);
1553 stats->rx_packets += rcvd_pkts;
1554 stats->rx_bytes += rcvd_bytes;
1555 u64_stats_update_end(&stats->syncp);
1558 /* Update rxq management counters */
1559 mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_filled);
1565 mvneta_tso_put_hdr(struct sk_buff *skb,
1566 struct mvneta_port *pp, struct mvneta_tx_queue *txq)
1568 struct mvneta_tx_desc *tx_desc;
1569 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
1571 txq->tx_skb[txq->txq_put_index] = NULL;
1572 tx_desc = mvneta_txq_next_desc_get(txq);
1573 tx_desc->data_size = hdr_len;
1574 tx_desc->command = mvneta_skb_tx_csum(pp, skb);
1575 tx_desc->command |= MVNETA_TXD_F_DESC;
1576 tx_desc->buf_phys_addr = txq->tso_hdrs_phys +
1577 txq->txq_put_index * TSO_HEADER_SIZE;
1578 mvneta_txq_inc_put(txq);
1582 mvneta_tso_put_data(struct net_device *dev, struct mvneta_tx_queue *txq,
1583 struct sk_buff *skb, char *data, int size,
1584 bool last_tcp, bool is_last)
1586 struct mvneta_tx_desc *tx_desc;
1588 tx_desc = mvneta_txq_next_desc_get(txq);
1589 tx_desc->data_size = size;
1590 tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, data,
1591 size, DMA_TO_DEVICE);
1592 if (unlikely(dma_mapping_error(dev->dev.parent,
1593 tx_desc->buf_phys_addr))) {
1594 mvneta_txq_desc_put(txq);
1598 tx_desc->command = 0;
1599 txq->tx_skb[txq->txq_put_index] = NULL;
1602 /* last descriptor in the TCP packet */
1603 tx_desc->command = MVNETA_TXD_L_DESC;
1605 /* last descriptor in SKB */
1607 txq->tx_skb[txq->txq_put_index] = skb;
1609 mvneta_txq_inc_put(txq);
1613 static int mvneta_tx_tso(struct sk_buff *skb, struct net_device *dev,
1614 struct mvneta_tx_queue *txq)
1616 int total_len, data_left;
1618 struct mvneta_port *pp = netdev_priv(dev);
1620 int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
1623 /* Count needed descriptors */
1624 if ((txq->count + tso_count_descs(skb)) >= txq->size)
1627 if (skb_headlen(skb) < (skb_transport_offset(skb) + tcp_hdrlen(skb))) {
1628 pr_info("*** Is this even possible???!?!?\n");
1632 /* Initialize the TSO handler, and prepare the first payload */
1633 tso_start(skb, &tso);
1635 total_len = skb->len - hdr_len;
1636 while (total_len > 0) {
1639 data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len);
1640 total_len -= data_left;
1643 /* prepare packet headers: MAC + IP + TCP */
1644 hdr = txq->tso_hdrs + txq->txq_put_index * TSO_HEADER_SIZE;
1645 tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0);
1647 mvneta_tso_put_hdr(skb, pp, txq);
1649 while (data_left > 0) {
1653 size = min_t(int, tso.size, data_left);
1655 if (mvneta_tso_put_data(dev, txq, skb,
1662 tso_build_data(skb, &tso, size);
1669 /* Release all used data descriptors; header descriptors must not
1672 for (i = desc_count - 1; i >= 0; i--) {
1673 struct mvneta_tx_desc *tx_desc = txq->descs + i;
1674 if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr))
1675 dma_unmap_single(pp->dev->dev.parent,
1676 tx_desc->buf_phys_addr,
1679 mvneta_txq_desc_put(txq);
1684 /* Handle tx fragmentation processing */
1685 static int mvneta_tx_frag_process(struct mvneta_port *pp, struct sk_buff *skb,
1686 struct mvneta_tx_queue *txq)
1688 struct mvneta_tx_desc *tx_desc;
1689 int i, nr_frags = skb_shinfo(skb)->nr_frags;
1691 for (i = 0; i < nr_frags; i++) {
1692 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1693 void *addr = page_address(frag->page.p) + frag->page_offset;
1695 tx_desc = mvneta_txq_next_desc_get(txq);
1696 tx_desc->data_size = frag->size;
1698 tx_desc->buf_phys_addr =
1699 dma_map_single(pp->dev->dev.parent, addr,
1700 tx_desc->data_size, DMA_TO_DEVICE);
1702 if (dma_mapping_error(pp->dev->dev.parent,
1703 tx_desc->buf_phys_addr)) {
1704 mvneta_txq_desc_put(txq);
1708 if (i == nr_frags - 1) {
1709 /* Last descriptor */
1710 tx_desc->command = MVNETA_TXD_L_DESC | MVNETA_TXD_Z_PAD;
1711 txq->tx_skb[txq->txq_put_index] = skb;
1713 /* Descriptor in the middle: Not First, Not Last */
1714 tx_desc->command = 0;
1715 txq->tx_skb[txq->txq_put_index] = NULL;
1717 mvneta_txq_inc_put(txq);
1723 /* Release all descriptors that were used to map fragments of
1724 * this packet, as well as the corresponding DMA mappings
1726 for (i = i - 1; i >= 0; i--) {
1727 tx_desc = txq->descs + i;
1728 dma_unmap_single(pp->dev->dev.parent,
1729 tx_desc->buf_phys_addr,
1732 mvneta_txq_desc_put(txq);
1738 /* Main tx processing */
1739 static int mvneta_tx(struct sk_buff *skb, struct net_device *dev)
1741 struct mvneta_port *pp = netdev_priv(dev);
1742 u16 txq_id = skb_get_queue_mapping(skb);
1743 struct mvneta_tx_queue *txq = &pp->txqs[txq_id];
1744 struct mvneta_tx_desc *tx_desc;
1749 if (!netif_running(dev))
1752 if (skb_is_gso(skb)) {
1753 frags = mvneta_tx_tso(skb, dev, txq);
1757 frags = skb_shinfo(skb)->nr_frags + 1;
1759 /* Get a descriptor for the first part of the packet */
1760 tx_desc = mvneta_txq_next_desc_get(txq);
1762 tx_cmd = mvneta_skb_tx_csum(pp, skb);
1764 tx_desc->data_size = skb_headlen(skb);
1766 tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, skb->data,
1769 if (unlikely(dma_mapping_error(dev->dev.parent,
1770 tx_desc->buf_phys_addr))) {
1771 mvneta_txq_desc_put(txq);
1777 /* First and Last descriptor */
1778 tx_cmd |= MVNETA_TXD_FLZ_DESC;
1779 tx_desc->command = tx_cmd;
1780 txq->tx_skb[txq->txq_put_index] = skb;
1781 mvneta_txq_inc_put(txq);
1783 /* First but not Last */
1784 tx_cmd |= MVNETA_TXD_F_DESC;
1785 txq->tx_skb[txq->txq_put_index] = NULL;
1786 mvneta_txq_inc_put(txq);
1787 tx_desc->command = tx_cmd;
1788 /* Continue with other skb fragments */
1789 if (mvneta_tx_frag_process(pp, skb, txq)) {
1790 dma_unmap_single(dev->dev.parent,
1791 tx_desc->buf_phys_addr,
1794 mvneta_txq_desc_put(txq);
1802 struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats);
1803 struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id);
1805 txq->count += frags;
1806 mvneta_txq_pend_desc_add(pp, txq, frags);
1808 if (txq->count >= txq->tx_stop_threshold)
1809 netif_tx_stop_queue(nq);
1811 u64_stats_update_begin(&stats->syncp);
1812 stats->tx_packets++;
1813 stats->tx_bytes += len;
1814 u64_stats_update_end(&stats->syncp);
1816 dev->stats.tx_dropped++;
1817 dev_kfree_skb_any(skb);
1820 return NETDEV_TX_OK;
1824 /* Free tx resources, when resetting a port */
1825 static void mvneta_txq_done_force(struct mvneta_port *pp,
1826 struct mvneta_tx_queue *txq)
1829 int tx_done = txq->count;
1831 mvneta_txq_bufs_free(pp, txq, tx_done);
1835 txq->txq_put_index = 0;
1836 txq->txq_get_index = 0;
1839 /* Handle tx done - called in softirq context. The <cause_tx_done> argument
1840 * must be a valid cause according to MVNETA_TXQ_INTR_MASK_ALL.
1842 static void mvneta_tx_done_gbe(struct mvneta_port *pp, u32 cause_tx_done)
1844 struct mvneta_tx_queue *txq;
1845 struct netdev_queue *nq;
1847 while (cause_tx_done) {
1848 txq = mvneta_tx_done_policy(pp, cause_tx_done);
1850 nq = netdev_get_tx_queue(pp->dev, txq->id);
1851 __netif_tx_lock(nq, smp_processor_id());
1854 mvneta_txq_done(pp, txq);
1856 __netif_tx_unlock(nq);
1857 cause_tx_done &= ~((1 << txq->id));
1861 /* Compute crc8 of the specified address, using a unique algorithm ,
1862 * according to hw spec, different than generic crc8 algorithm
1864 static int mvneta_addr_crc(unsigned char *addr)
1869 for (i = 0; i < ETH_ALEN; i++) {
1872 crc = (crc ^ addr[i]) << 8;
1873 for (j = 7; j >= 0; j--) {
1874 if (crc & (0x100 << j))
1882 /* This method controls the net device special MAC multicast support.
1883 * The Special Multicast Table for MAC addresses supports MAC of the form
1884 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF).
1885 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
1886 * Table entries in the DA-Filter table. This method set the Special
1887 * Multicast Table appropriate entry.
1889 static void mvneta_set_special_mcast_addr(struct mvneta_port *pp,
1890 unsigned char last_byte,
1893 unsigned int smc_table_reg;
1894 unsigned int tbl_offset;
1895 unsigned int reg_offset;
1897 /* Register offset from SMC table base */
1898 tbl_offset = (last_byte / 4);
1899 /* Entry offset within the above reg */
1900 reg_offset = last_byte % 4;
1902 smc_table_reg = mvreg_read(pp, (MVNETA_DA_FILT_SPEC_MCAST
1906 smc_table_reg &= ~(0xff << (8 * reg_offset));
1908 smc_table_reg &= ~(0xff << (8 * reg_offset));
1909 smc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
1912 mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + tbl_offset * 4,
1916 /* This method controls the network device Other MAC multicast support.
1917 * The Other Multicast Table is used for multicast of another type.
1918 * A CRC-8 is used as an index to the Other Multicast Table entries
1919 * in the DA-Filter table.
1920 * The method gets the CRC-8 value from the calling routine and
1921 * sets the Other Multicast Table appropriate entry according to the
1924 static void mvneta_set_other_mcast_addr(struct mvneta_port *pp,
1928 unsigned int omc_table_reg;
1929 unsigned int tbl_offset;
1930 unsigned int reg_offset;
1932 tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */
1933 reg_offset = crc8 % 4; /* Entry offset within the above reg */
1935 omc_table_reg = mvreg_read(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset);
1938 /* Clear accepts frame bit at specified Other DA table entry */
1939 omc_table_reg &= ~(0xff << (8 * reg_offset));
1941 omc_table_reg &= ~(0xff << (8 * reg_offset));
1942 omc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset));
1945 mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset, omc_table_reg);
1948 /* The network device supports multicast using two tables:
1949 * 1) Special Multicast Table for MAC addresses of the form
1950 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF).
1951 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
1952 * Table entries in the DA-Filter table.
1953 * 2) Other Multicast Table for multicast of another type. A CRC-8 value
1954 * is used as an index to the Other Multicast Table entries in the
1957 static int mvneta_mcast_addr_set(struct mvneta_port *pp, unsigned char *p_addr,
1960 unsigned char crc_result = 0;
1962 if (memcmp(p_addr, "\x01\x00\x5e\x00\x00", 5) == 0) {
1963 mvneta_set_special_mcast_addr(pp, p_addr[5], queue);
1967 crc_result = mvneta_addr_crc(p_addr);
1969 if (pp->mcast_count[crc_result] == 0) {
1970 netdev_info(pp->dev, "No valid Mcast for crc8=0x%02x\n",
1975 pp->mcast_count[crc_result]--;
1976 if (pp->mcast_count[crc_result] != 0) {
1977 netdev_info(pp->dev,
1978 "After delete there are %d valid Mcast for crc8=0x%02x\n",
1979 pp->mcast_count[crc_result], crc_result);
1983 pp->mcast_count[crc_result]++;
1985 mvneta_set_other_mcast_addr(pp, crc_result, queue);
1990 /* Configure Fitering mode of Ethernet port */
1991 static void mvneta_rx_unicast_promisc_set(struct mvneta_port *pp,
1994 u32 port_cfg_reg, val;
1996 port_cfg_reg = mvreg_read(pp, MVNETA_PORT_CONFIG);
1998 val = mvreg_read(pp, MVNETA_TYPE_PRIO);
2000 /* Set / Clear UPM bit in port configuration register */
2002 /* Accept all Unicast addresses */
2003 port_cfg_reg |= MVNETA_UNI_PROMISC_MODE;
2004 val |= MVNETA_FORCE_UNI;
2005 mvreg_write(pp, MVNETA_MAC_ADDR_LOW, 0xffff);
2006 mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, 0xffffffff);
2008 /* Reject all Unicast addresses */
2009 port_cfg_reg &= ~MVNETA_UNI_PROMISC_MODE;
2010 val &= ~MVNETA_FORCE_UNI;
2013 mvreg_write(pp, MVNETA_PORT_CONFIG, port_cfg_reg);
2014 mvreg_write(pp, MVNETA_TYPE_PRIO, val);
2017 /* register unicast and multicast addresses */
2018 static void mvneta_set_rx_mode(struct net_device *dev)
2020 struct mvneta_port *pp = netdev_priv(dev);
2021 struct netdev_hw_addr *ha;
2023 if (dev->flags & IFF_PROMISC) {
2024 /* Accept all: Multicast + Unicast */
2025 mvneta_rx_unicast_promisc_set(pp, 1);
2026 mvneta_set_ucast_table(pp, rxq_def);
2027 mvneta_set_special_mcast_table(pp, rxq_def);
2028 mvneta_set_other_mcast_table(pp, rxq_def);
2030 /* Accept single Unicast */
2031 mvneta_rx_unicast_promisc_set(pp, 0);
2032 mvneta_set_ucast_table(pp, -1);
2033 mvneta_mac_addr_set(pp, dev->dev_addr, rxq_def);
2035 if (dev->flags & IFF_ALLMULTI) {
2036 /* Accept all multicast */
2037 mvneta_set_special_mcast_table(pp, rxq_def);
2038 mvneta_set_other_mcast_table(pp, rxq_def);
2040 /* Accept only initialized multicast */
2041 mvneta_set_special_mcast_table(pp, -1);
2042 mvneta_set_other_mcast_table(pp, -1);
2044 if (!netdev_mc_empty(dev)) {
2045 netdev_for_each_mc_addr(ha, dev) {
2046 mvneta_mcast_addr_set(pp, ha->addr,
2054 /* Interrupt handling - the callback for request_irq() */
2055 static irqreturn_t mvneta_isr(int irq, void *dev_id)
2057 struct mvneta_port *pp = (struct mvneta_port *)dev_id;
2059 /* Mask all interrupts */
2060 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
2062 napi_schedule(&pp->napi);
2067 static int mvneta_fixed_link_update(struct mvneta_port *pp,
2068 struct phy_device *phy)
2070 struct fixed_phy_status status;
2071 struct fixed_phy_status changed = {};
2072 u32 gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS);
2074 status.link = !!(gmac_stat & MVNETA_GMAC_LINK_UP);
2075 if (gmac_stat & MVNETA_GMAC_SPEED_1000)
2076 status.speed = SPEED_1000;
2077 else if (gmac_stat & MVNETA_GMAC_SPEED_100)
2078 status.speed = SPEED_100;
2080 status.speed = SPEED_10;
2081 status.duplex = !!(gmac_stat & MVNETA_GMAC_FULL_DUPLEX);
2085 fixed_phy_update_state(phy, &status, &changed);
2090 * Bits 0 - 7 of the causeRxTx register indicate that are transmitted
2091 * packets on the corresponding TXQ (Bit 0 is for TX queue 1).
2092 * Bits 8 -15 of the cause Rx Tx register indicate that are received
2093 * packets on the corresponding RXQ (Bit 8 is for RX queue 0).
2094 * Each CPU has its own causeRxTx register
2096 static int mvneta_poll(struct napi_struct *napi, int budget)
2100 unsigned long flags;
2101 struct mvneta_port *pp = netdev_priv(napi->dev);
2103 if (!netif_running(pp->dev)) {
2104 napi_complete(napi);
2108 /* Read cause register */
2109 cause_rx_tx = mvreg_read(pp, MVNETA_INTR_NEW_CAUSE);
2110 if (cause_rx_tx & MVNETA_MISCINTR_INTR_MASK) {
2111 u32 cause_misc = mvreg_read(pp, MVNETA_INTR_MISC_CAUSE);
2113 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
2114 if (pp->use_inband_status && (cause_misc &
2115 (MVNETA_CAUSE_PHY_STATUS_CHANGE |
2116 MVNETA_CAUSE_LINK_CHANGE |
2117 MVNETA_CAUSE_PSC_SYNC_CHANGE))) {
2118 mvneta_fixed_link_update(pp, pp->phy_dev);
2122 /* Release Tx descriptors */
2123 if (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL) {
2124 mvneta_tx_done_gbe(pp, (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL));
2125 cause_rx_tx &= ~MVNETA_TX_INTR_MASK_ALL;
2128 /* For the case where the last mvneta_poll did not process all
2131 cause_rx_tx |= pp->cause_rx_tx;
2132 if (rxq_number > 1) {
2133 while ((cause_rx_tx & MVNETA_RX_INTR_MASK_ALL) && (budget > 0)) {
2135 struct mvneta_rx_queue *rxq;
2136 /* get rx queue number from cause_rx_tx */
2137 rxq = mvneta_rx_policy(pp, cause_rx_tx);
2141 /* process the packet in that rx queue */
2142 count = mvneta_rx(pp, budget, rxq);
2146 /* set off the rx bit of the
2147 * corresponding bit in the cause rx
2148 * tx register, so that next iteration
2149 * will find the next rx queue where
2150 * packets are received on
2152 cause_rx_tx &= ~((1 << rxq->id) << 8);
2156 rx_done = mvneta_rx(pp, budget, &pp->rxqs[rxq_def]);
2162 napi_complete(napi);
2163 local_irq_save(flags);
2164 mvreg_write(pp, MVNETA_INTR_NEW_MASK,
2165 MVNETA_RX_INTR_MASK(rxq_number) |
2166 MVNETA_TX_INTR_MASK(txq_number) |
2167 MVNETA_MISCINTR_INTR_MASK);
2168 local_irq_restore(flags);
2171 pp->cause_rx_tx = cause_rx_tx;
2175 /* Handle rxq fill: allocates rxq skbs; called when initializing a port */
2176 static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq,
2181 for (i = 0; i < num; i++) {
2182 memset(rxq->descs + i, 0, sizeof(struct mvneta_rx_desc));
2183 if (mvneta_rx_refill(pp, rxq->descs + i) != 0) {
2184 netdev_err(pp->dev, "%s:rxq %d, %d of %d buffs filled\n",
2185 __func__, rxq->id, i, num);
2190 /* Add this number of RX descriptors as non occupied (ready to
2193 mvneta_rxq_non_occup_desc_add(pp, rxq, i);
2198 /* Free all packets pending transmit from all TXQs and reset TX port */
2199 static void mvneta_tx_reset(struct mvneta_port *pp)
2203 /* free the skb's in the tx ring */
2204 for (queue = 0; queue < txq_number; queue++)
2205 mvneta_txq_done_force(pp, &pp->txqs[queue]);
2207 mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET);
2208 mvreg_write(pp, MVNETA_PORT_TX_RESET, 0);
2211 static void mvneta_rx_reset(struct mvneta_port *pp)
2213 mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET);
2214 mvreg_write(pp, MVNETA_PORT_RX_RESET, 0);
2217 /* Rx/Tx queue initialization/cleanup methods */
2219 /* Create a specified RX queue */
2220 static int mvneta_rxq_init(struct mvneta_port *pp,
2221 struct mvneta_rx_queue *rxq)
2224 rxq->size = pp->rx_ring_size;
2226 /* Allocate memory for RX descriptors */
2227 rxq->descs = dma_alloc_coherent(pp->dev->dev.parent,
2228 rxq->size * MVNETA_DESC_ALIGNED_SIZE,
2229 &rxq->descs_phys, GFP_KERNEL);
2230 if (rxq->descs == NULL)
2233 BUG_ON(rxq->descs !=
2234 PTR_ALIGN(rxq->descs, MVNETA_CPU_D_CACHE_LINE_SIZE));
2236 rxq->last_desc = rxq->size - 1;
2238 /* Set Rx descriptors queue starting address */
2239 mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys);
2240 mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size);
2243 mvneta_rxq_offset_set(pp, rxq, NET_SKB_PAD);
2245 /* Set coalescing pkts and time */
2246 mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal);
2247 mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal);
2249 /* Fill RXQ with buffers from RX pool */
2250 mvneta_rxq_buf_size_set(pp, rxq, MVNETA_RX_BUF_SIZE(pp->pkt_size));
2251 mvneta_rxq_bm_disable(pp, rxq);
2252 mvneta_rxq_fill(pp, rxq, rxq->size);
2257 /* Cleanup Rx queue */
2258 static void mvneta_rxq_deinit(struct mvneta_port *pp,
2259 struct mvneta_rx_queue *rxq)
2261 mvneta_rxq_drop_pkts(pp, rxq);
2264 dma_free_coherent(pp->dev->dev.parent,
2265 rxq->size * MVNETA_DESC_ALIGNED_SIZE,
2271 rxq->next_desc_to_proc = 0;
2272 rxq->descs_phys = 0;
2275 /* Create and initialize a tx queue */
2276 static int mvneta_txq_init(struct mvneta_port *pp,
2277 struct mvneta_tx_queue *txq)
2279 txq->size = pp->tx_ring_size;
2281 /* A queue must always have room for at least one skb.
2282 * Therefore, stop the queue when the free entries reaches
2283 * the maximum number of descriptors per skb.
2285 txq->tx_stop_threshold = txq->size - MVNETA_MAX_SKB_DESCS;
2286 txq->tx_wake_threshold = txq->tx_stop_threshold / 2;
2289 /* Allocate memory for TX descriptors */
2290 txq->descs = dma_alloc_coherent(pp->dev->dev.parent,
2291 txq->size * MVNETA_DESC_ALIGNED_SIZE,
2292 &txq->descs_phys, GFP_KERNEL);
2293 if (txq->descs == NULL)
2296 /* Make sure descriptor address is cache line size aligned */
2297 BUG_ON(txq->descs !=
2298 PTR_ALIGN(txq->descs, MVNETA_CPU_D_CACHE_LINE_SIZE));
2300 txq->last_desc = txq->size - 1;
2302 /* Set maximum bandwidth for enabled TXQs */
2303 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff);
2304 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff);
2306 /* Set Tx descriptors queue starting address */
2307 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys);
2308 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size);
2310 txq->tx_skb = kmalloc(txq->size * sizeof(*txq->tx_skb), GFP_KERNEL);
2311 if (txq->tx_skb == NULL) {
2312 dma_free_coherent(pp->dev->dev.parent,
2313 txq->size * MVNETA_DESC_ALIGNED_SIZE,
2314 txq->descs, txq->descs_phys);
2318 /* Allocate DMA buffers for TSO MAC/IP/TCP headers */
2319 txq->tso_hdrs = dma_alloc_coherent(pp->dev->dev.parent,
2320 txq->size * TSO_HEADER_SIZE,
2321 &txq->tso_hdrs_phys, GFP_KERNEL);
2322 if (txq->tso_hdrs == NULL) {
2324 dma_free_coherent(pp->dev->dev.parent,
2325 txq->size * MVNETA_DESC_ALIGNED_SIZE,
2326 txq->descs, txq->descs_phys);
2329 mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal);
2334 /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/
2335 static void mvneta_txq_deinit(struct mvneta_port *pp,
2336 struct mvneta_tx_queue *txq)
2341 dma_free_coherent(pp->dev->dev.parent,
2342 txq->size * TSO_HEADER_SIZE,
2343 txq->tso_hdrs, txq->tso_hdrs_phys);
2345 dma_free_coherent(pp->dev->dev.parent,
2346 txq->size * MVNETA_DESC_ALIGNED_SIZE,
2347 txq->descs, txq->descs_phys);
2351 txq->next_desc_to_proc = 0;
2352 txq->descs_phys = 0;
2354 /* Set minimum bandwidth for disabled TXQs */
2355 mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0);
2356 mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0);
2358 /* Set Tx descriptors queue starting address and size */
2359 mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0);
2360 mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0);
2363 /* Cleanup all Tx queues */
2364 static void mvneta_cleanup_txqs(struct mvneta_port *pp)
2368 for (queue = 0; queue < txq_number; queue++)
2369 mvneta_txq_deinit(pp, &pp->txqs[queue]);
2372 /* Cleanup all Rx queues */
2373 static void mvneta_cleanup_rxqs(struct mvneta_port *pp)
2377 for (queue = 0; queue < rxq_number; queue++)
2378 mvneta_rxq_deinit(pp, &pp->rxqs[queue]);
2382 /* Init all Rx queues */
2383 static int mvneta_setup_rxqs(struct mvneta_port *pp)
2387 for (queue = 0; queue < rxq_number; queue++) {
2388 int err = mvneta_rxq_init(pp, &pp->rxqs[queue]);
2390 netdev_err(pp->dev, "%s: can't create rxq=%d\n",
2392 mvneta_cleanup_rxqs(pp);
2400 /* Init all tx queues */
2401 static int mvneta_setup_txqs(struct mvneta_port *pp)
2405 for (queue = 0; queue < txq_number; queue++) {
2406 int err = mvneta_txq_init(pp, &pp->txqs[queue]);
2408 netdev_err(pp->dev, "%s: can't create txq=%d\n",
2410 mvneta_cleanup_txqs(pp);
2418 static void mvneta_start_dev(struct mvneta_port *pp)
2420 mvneta_max_rx_size_set(pp, pp->pkt_size);
2421 mvneta_txq_max_tx_size_set(pp, pp->pkt_size);
2423 /* start the Rx/Tx activity */
2424 mvneta_port_enable(pp);
2426 /* Enable polling on the port */
2427 napi_enable(&pp->napi);
2429 /* Unmask interrupts */
2430 mvreg_write(pp, MVNETA_INTR_NEW_MASK,
2431 MVNETA_RX_INTR_MASK(rxq_number) |
2432 MVNETA_TX_INTR_MASK(txq_number) |
2433 MVNETA_MISCINTR_INTR_MASK);
2434 mvreg_write(pp, MVNETA_INTR_MISC_MASK,
2435 MVNETA_CAUSE_PHY_STATUS_CHANGE |
2436 MVNETA_CAUSE_LINK_CHANGE |
2437 MVNETA_CAUSE_PSC_SYNC_CHANGE);
2439 phy_start(pp->phy_dev);
2440 netif_tx_start_all_queues(pp->dev);
2443 static void mvneta_stop_dev(struct mvneta_port *pp)
2445 phy_stop(pp->phy_dev);
2447 napi_disable(&pp->napi);
2449 netif_carrier_off(pp->dev);
2451 mvneta_port_down(pp);
2452 netif_tx_stop_all_queues(pp->dev);
2454 /* Stop the port activity */
2455 mvneta_port_disable(pp);
2457 /* Clear all ethernet port interrupts */
2458 mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
2459 mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0);
2461 /* Mask all ethernet port interrupts */
2462 mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
2463 mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
2464 mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
2466 mvneta_tx_reset(pp);
2467 mvneta_rx_reset(pp);
2470 /* Return positive if MTU is valid */
2471 static int mvneta_check_mtu_valid(struct net_device *dev, int mtu)
2474 netdev_err(dev, "cannot change mtu to less than 68\n");
2478 /* 9676 == 9700 - 20 and rounding to 8 */
2480 netdev_info(dev, "Illegal MTU value %d, round to 9676\n", mtu);
2484 if (!IS_ALIGNED(MVNETA_RX_PKT_SIZE(mtu), 8)) {
2485 netdev_info(dev, "Illegal MTU value %d, rounding to %d\n",
2486 mtu, ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8));
2487 mtu = ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8);
2493 /* Change the device mtu */
2494 static int mvneta_change_mtu(struct net_device *dev, int mtu)
2496 struct mvneta_port *pp = netdev_priv(dev);
2499 mtu = mvneta_check_mtu_valid(dev, mtu);
2505 if (!netif_running(dev))
2508 /* The interface is running, so we have to force a
2509 * reallocation of the queues
2511 mvneta_stop_dev(pp);
2513 mvneta_cleanup_txqs(pp);
2514 mvneta_cleanup_rxqs(pp);
2516 pp->pkt_size = MVNETA_RX_PKT_SIZE(dev->mtu);
2517 pp->frag_size = SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(pp->pkt_size)) +
2518 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2520 ret = mvneta_setup_rxqs(pp);
2522 netdev_err(dev, "unable to setup rxqs after MTU change\n");
2526 ret = mvneta_setup_txqs(pp);
2528 netdev_err(dev, "unable to setup txqs after MTU change\n");
2532 mvneta_start_dev(pp);
2538 /* Get mac address */
2539 static void mvneta_get_mac_addr(struct mvneta_port *pp, unsigned char *addr)
2541 u32 mac_addr_l, mac_addr_h;
2543 mac_addr_l = mvreg_read(pp, MVNETA_MAC_ADDR_LOW);
2544 mac_addr_h = mvreg_read(pp, MVNETA_MAC_ADDR_HIGH);
2545 addr[0] = (mac_addr_h >> 24) & 0xFF;
2546 addr[1] = (mac_addr_h >> 16) & 0xFF;
2547 addr[2] = (mac_addr_h >> 8) & 0xFF;
2548 addr[3] = mac_addr_h & 0xFF;
2549 addr[4] = (mac_addr_l >> 8) & 0xFF;
2550 addr[5] = mac_addr_l & 0xFF;
2553 /* Handle setting mac address */
2554 static int mvneta_set_mac_addr(struct net_device *dev, void *addr)
2556 struct mvneta_port *pp = netdev_priv(dev);
2557 struct sockaddr *sockaddr = addr;
2560 ret = eth_prepare_mac_addr_change(dev, addr);
2563 /* Remove previous address table entry */
2564 mvneta_mac_addr_set(pp, dev->dev_addr, -1);
2566 /* Set new addr in hw */
2567 mvneta_mac_addr_set(pp, sockaddr->sa_data, rxq_def);
2569 eth_commit_mac_addr_change(dev, addr);
2573 static void mvneta_adjust_link(struct net_device *ndev)
2575 struct mvneta_port *pp = netdev_priv(ndev);
2576 struct phy_device *phydev = pp->phy_dev;
2577 int status_change = 0;
2580 if ((pp->speed != phydev->speed) ||
2581 (pp->duplex != phydev->duplex)) {
2584 val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG);
2585 val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED |
2586 MVNETA_GMAC_CONFIG_GMII_SPEED |
2587 MVNETA_GMAC_CONFIG_FULL_DUPLEX);
2590 val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX;
2592 if (phydev->speed == SPEED_1000)
2593 val |= MVNETA_GMAC_CONFIG_GMII_SPEED;
2594 else if (phydev->speed == SPEED_100)
2595 val |= MVNETA_GMAC_CONFIG_MII_SPEED;
2597 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val);
2599 pp->duplex = phydev->duplex;
2600 pp->speed = phydev->speed;
2604 if (phydev->link != pp->link) {
2605 if (!phydev->link) {
2610 pp->link = phydev->link;
2614 if (status_change) {
2616 if (!pp->use_inband_status) {
2617 u32 val = mvreg_read(pp,
2618 MVNETA_GMAC_AUTONEG_CONFIG);
2619 val &= ~MVNETA_GMAC_FORCE_LINK_DOWN;
2620 val |= MVNETA_GMAC_FORCE_LINK_PASS;
2621 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG,
2626 if (!pp->use_inband_status) {
2627 u32 val = mvreg_read(pp,
2628 MVNETA_GMAC_AUTONEG_CONFIG);
2629 val &= ~MVNETA_GMAC_FORCE_LINK_PASS;
2630 val |= MVNETA_GMAC_FORCE_LINK_DOWN;
2631 mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG,
2634 mvneta_port_down(pp);
2636 phy_print_status(phydev);
2640 static int mvneta_mdio_probe(struct mvneta_port *pp)
2642 struct phy_device *phy_dev;
2644 phy_dev = of_phy_connect(pp->dev, pp->phy_node, mvneta_adjust_link, 0,
2647 netdev_err(pp->dev, "could not find the PHY\n");
2651 phy_dev->supported &= PHY_GBIT_FEATURES;
2652 phy_dev->advertising = phy_dev->supported;
2654 pp->phy_dev = phy_dev;
2662 static void mvneta_mdio_remove(struct mvneta_port *pp)
2664 phy_disconnect(pp->phy_dev);
2668 static int mvneta_open(struct net_device *dev)
2670 struct mvneta_port *pp = netdev_priv(dev);
2673 pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu);
2674 pp->frag_size = SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(pp->pkt_size)) +
2675 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2677 ret = mvneta_setup_rxqs(pp);
2681 ret = mvneta_setup_txqs(pp);
2683 goto err_cleanup_rxqs;
2685 /* Connect to port interrupt line */
2686 ret = request_irq(pp->dev->irq, mvneta_isr, 0,
2687 MVNETA_DRIVER_NAME, pp);
2689 netdev_err(pp->dev, "cannot request irq %d\n", pp->dev->irq);
2690 goto err_cleanup_txqs;
2693 /* In default link is down */
2694 netif_carrier_off(pp->dev);
2696 ret = mvneta_mdio_probe(pp);
2698 netdev_err(dev, "cannot probe MDIO bus\n");
2702 mvneta_start_dev(pp);
2707 free_irq(pp->dev->irq, pp);
2709 mvneta_cleanup_txqs(pp);
2711 mvneta_cleanup_rxqs(pp);
2715 /* Stop the port, free port interrupt line */
2716 static int mvneta_stop(struct net_device *dev)
2718 struct mvneta_port *pp = netdev_priv(dev);
2720 mvneta_stop_dev(pp);
2721 mvneta_mdio_remove(pp);
2722 free_irq(dev->irq, pp);
2723 mvneta_cleanup_rxqs(pp);
2724 mvneta_cleanup_txqs(pp);
2729 static int mvneta_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2731 struct mvneta_port *pp = netdev_priv(dev);
2736 return phy_mii_ioctl(pp->phy_dev, ifr, cmd);
2739 /* Ethtool methods */
2741 /* Get settings (phy address, speed) for ethtools */
2742 int mvneta_ethtool_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2744 struct mvneta_port *pp = netdev_priv(dev);
2749 return phy_ethtool_gset(pp->phy_dev, cmd);
2752 /* Set settings (phy address, speed) for ethtools */
2753 int mvneta_ethtool_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2755 struct mvneta_port *pp = netdev_priv(dev);
2760 return phy_ethtool_sset(pp->phy_dev, cmd);
2763 /* Set interrupt coalescing for ethtools */
2764 static int mvneta_ethtool_set_coalesce(struct net_device *dev,
2765 struct ethtool_coalesce *c)
2767 struct mvneta_port *pp = netdev_priv(dev);
2770 for (queue = 0; queue < rxq_number; queue++) {
2771 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
2772 rxq->time_coal = c->rx_coalesce_usecs;
2773 rxq->pkts_coal = c->rx_max_coalesced_frames;
2774 mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal);
2775 mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal);
2778 for (queue = 0; queue < txq_number; queue++) {
2779 struct mvneta_tx_queue *txq = &pp->txqs[queue];
2780 txq->done_pkts_coal = c->tx_max_coalesced_frames;
2781 mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal);
2787 /* get coalescing for ethtools */
2788 static int mvneta_ethtool_get_coalesce(struct net_device *dev,
2789 struct ethtool_coalesce *c)
2791 struct mvneta_port *pp = netdev_priv(dev);
2793 c->rx_coalesce_usecs = pp->rxqs[0].time_coal;
2794 c->rx_max_coalesced_frames = pp->rxqs[0].pkts_coal;
2796 c->tx_max_coalesced_frames = pp->txqs[0].done_pkts_coal;
2801 static void mvneta_ethtool_get_drvinfo(struct net_device *dev,
2802 struct ethtool_drvinfo *drvinfo)
2804 strlcpy(drvinfo->driver, MVNETA_DRIVER_NAME,
2805 sizeof(drvinfo->driver));
2806 strlcpy(drvinfo->version, MVNETA_DRIVER_VERSION,
2807 sizeof(drvinfo->version));
2808 strlcpy(drvinfo->bus_info, dev_name(&dev->dev),
2809 sizeof(drvinfo->bus_info));
2813 static void mvneta_ethtool_get_ringparam(struct net_device *netdev,
2814 struct ethtool_ringparam *ring)
2816 struct mvneta_port *pp = netdev_priv(netdev);
2818 ring->rx_max_pending = MVNETA_MAX_RXD;
2819 ring->tx_max_pending = MVNETA_MAX_TXD;
2820 ring->rx_pending = pp->rx_ring_size;
2821 ring->tx_pending = pp->tx_ring_size;
2824 static int mvneta_ethtool_set_ringparam(struct net_device *dev,
2825 struct ethtool_ringparam *ring)
2827 struct mvneta_port *pp = netdev_priv(dev);
2829 if ((ring->rx_pending == 0) || (ring->tx_pending == 0))
2831 pp->rx_ring_size = ring->rx_pending < MVNETA_MAX_RXD ?
2832 ring->rx_pending : MVNETA_MAX_RXD;
2834 pp->tx_ring_size = clamp_t(u16, ring->tx_pending,
2835 MVNETA_MAX_SKB_DESCS * 2, MVNETA_MAX_TXD);
2836 if (pp->tx_ring_size != ring->tx_pending)
2837 netdev_warn(dev, "TX queue size set to %u (requested %u)\n",
2838 pp->tx_ring_size, ring->tx_pending);
2840 if (netif_running(dev)) {
2842 if (mvneta_open(dev)) {
2844 "error on opening device after ring param change\n");
2852 static const struct net_device_ops mvneta_netdev_ops = {
2853 .ndo_open = mvneta_open,
2854 .ndo_stop = mvneta_stop,
2855 .ndo_start_xmit = mvneta_tx,
2856 .ndo_set_rx_mode = mvneta_set_rx_mode,
2857 .ndo_set_mac_address = mvneta_set_mac_addr,
2858 .ndo_change_mtu = mvneta_change_mtu,
2859 .ndo_get_stats64 = mvneta_get_stats64,
2860 .ndo_do_ioctl = mvneta_ioctl,
2863 const struct ethtool_ops mvneta_eth_tool_ops = {
2864 .get_link = ethtool_op_get_link,
2865 .get_settings = mvneta_ethtool_get_settings,
2866 .set_settings = mvneta_ethtool_set_settings,
2867 .set_coalesce = mvneta_ethtool_set_coalesce,
2868 .get_coalesce = mvneta_ethtool_get_coalesce,
2869 .get_drvinfo = mvneta_ethtool_get_drvinfo,
2870 .get_ringparam = mvneta_ethtool_get_ringparam,
2871 .set_ringparam = mvneta_ethtool_set_ringparam,
2875 static int mvneta_init(struct device *dev, struct mvneta_port *pp)
2880 mvneta_port_disable(pp);
2882 /* Set port default values */
2883 mvneta_defaults_set(pp);
2885 pp->txqs = devm_kcalloc(dev, txq_number, sizeof(struct mvneta_tx_queue),
2890 /* Initialize TX descriptor rings */
2891 for (queue = 0; queue < txq_number; queue++) {
2892 struct mvneta_tx_queue *txq = &pp->txqs[queue];
2894 txq->size = pp->tx_ring_size;
2895 txq->done_pkts_coal = MVNETA_TXDONE_COAL_PKTS;
2898 pp->rxqs = devm_kcalloc(dev, rxq_number, sizeof(struct mvneta_rx_queue),
2903 /* Create Rx descriptor rings */
2904 for (queue = 0; queue < rxq_number; queue++) {
2905 struct mvneta_rx_queue *rxq = &pp->rxqs[queue];
2907 rxq->size = pp->rx_ring_size;
2908 rxq->pkts_coal = MVNETA_RX_COAL_PKTS;
2909 rxq->time_coal = MVNETA_RX_COAL_USEC;
2915 /* platform glue : initialize decoding windows */
2916 static void mvneta_conf_mbus_windows(struct mvneta_port *pp,
2917 const struct mbus_dram_target_info *dram)
2923 for (i = 0; i < 6; i++) {
2924 mvreg_write(pp, MVNETA_WIN_BASE(i), 0);
2925 mvreg_write(pp, MVNETA_WIN_SIZE(i), 0);
2928 mvreg_write(pp, MVNETA_WIN_REMAP(i), 0);
2934 for (i = 0; i < dram->num_cs; i++) {
2935 const struct mbus_dram_window *cs = dram->cs + i;
2936 mvreg_write(pp, MVNETA_WIN_BASE(i), (cs->base & 0xffff0000) |
2937 (cs->mbus_attr << 8) | dram->mbus_dram_target_id);
2939 mvreg_write(pp, MVNETA_WIN_SIZE(i),
2940 (cs->size - 1) & 0xffff0000);
2942 win_enable &= ~(1 << i);
2943 win_protect |= 3 << (2 * i);
2946 mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable);
2949 /* Power up the port */
2950 static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode)
2954 /* MAC Cause register should be cleared */
2955 mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0);
2957 ctrl = mvreg_read(pp, MVNETA_GMAC_CTRL_2);
2959 /* Even though it might look weird, when we're configured in
2960 * SGMII or QSGMII mode, the RGMII bit needs to be set.
2963 case PHY_INTERFACE_MODE_QSGMII:
2964 mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO);
2965 ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII;
2967 case PHY_INTERFACE_MODE_SGMII:
2968 mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO);
2969 ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII;
2971 case PHY_INTERFACE_MODE_RGMII:
2972 case PHY_INTERFACE_MODE_RGMII_ID:
2973 ctrl |= MVNETA_GMAC2_PORT_RGMII;
2979 if (pp->use_inband_status)
2980 ctrl |= MVNETA_GMAC2_INBAND_AN_ENABLE;
2982 /* Cancel Port Reset */
2983 ctrl &= ~MVNETA_GMAC2_PORT_RESET;
2984 mvreg_write(pp, MVNETA_GMAC_CTRL_2, ctrl);
2986 while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) &
2987 MVNETA_GMAC2_PORT_RESET) != 0)
2993 /* Device initialization routine */
2994 static int mvneta_probe(struct platform_device *pdev)
2996 const struct mbus_dram_target_info *dram_target_info;
2997 struct resource *res;
2998 struct device_node *dn = pdev->dev.of_node;
2999 struct device_node *phy_node;
3000 struct mvneta_port *pp;
3001 struct net_device *dev;
3002 const char *dt_mac_addr;
3003 char hw_mac_addr[ETH_ALEN];
3004 const char *mac_from;
3009 /* Our multiqueue support is not complete, so for now, only
3010 * allow the usage of the first RX queue
3013 dev_err(&pdev->dev, "Invalid rxq_def argument: %d\n", rxq_def);
3017 dev = alloc_etherdev_mqs(sizeof(struct mvneta_port), txq_number, rxq_number);
3021 dev->irq = irq_of_parse_and_map(dn, 0);
3022 if (dev->irq == 0) {
3024 goto err_free_netdev;
3027 phy_node = of_parse_phandle(dn, "phy", 0);
3029 if (!of_phy_is_fixed_link(dn)) {
3030 dev_err(&pdev->dev, "no PHY specified\n");
3035 err = of_phy_register_fixed_link(dn);
3037 dev_err(&pdev->dev, "cannot register fixed PHY\n");
3042 /* In the case of a fixed PHY, the DT node associated
3043 * to the PHY is the Ethernet MAC DT node.
3045 phy_node = of_node_get(dn);
3048 phy_mode = of_get_phy_mode(dn);
3050 dev_err(&pdev->dev, "incorrect phy-mode\n");
3052 goto err_put_phy_node;
3055 dev->tx_queue_len = MVNETA_MAX_TXD;
3056 dev->watchdog_timeo = 5 * HZ;
3057 dev->netdev_ops = &mvneta_netdev_ops;
3059 dev->ethtool_ops = &mvneta_eth_tool_ops;
3061 pp = netdev_priv(dev);
3062 pp->phy_node = phy_node;
3063 pp->phy_interface = phy_mode;
3064 pp->use_inband_status = (phy_mode == PHY_INTERFACE_MODE_SGMII) &&
3067 pp->clk = devm_clk_get(&pdev->dev, NULL);
3068 if (IS_ERR(pp->clk)) {
3069 err = PTR_ERR(pp->clk);
3070 goto err_put_phy_node;
3073 clk_prepare_enable(pp->clk);
3075 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3076 pp->base = devm_ioremap_resource(&pdev->dev, res);
3077 if (IS_ERR(pp->base)) {
3078 err = PTR_ERR(pp->base);
3082 /* Alloc per-cpu stats */
3083 pp->stats = netdev_alloc_pcpu_stats(struct mvneta_pcpu_stats);
3089 dt_mac_addr = of_get_mac_address(dn);
3091 mac_from = "device tree";
3092 memcpy(dev->dev_addr, dt_mac_addr, ETH_ALEN);
3094 mvneta_get_mac_addr(pp, hw_mac_addr);
3095 if (is_valid_ether_addr(hw_mac_addr)) {
3096 mac_from = "hardware";
3097 memcpy(dev->dev_addr, hw_mac_addr, ETH_ALEN);
3099 mac_from = "random";
3100 eth_hw_addr_random(dev);
3104 pp->tx_ring_size = MVNETA_MAX_TXD;
3105 pp->rx_ring_size = MVNETA_MAX_RXD;
3108 SET_NETDEV_DEV(dev, &pdev->dev);
3110 err = mvneta_init(&pdev->dev, pp);
3112 goto err_free_stats;
3114 err = mvneta_port_power_up(pp, phy_mode);
3116 dev_err(&pdev->dev, "can't power up port\n");
3117 goto err_free_stats;
3120 dram_target_info = mv_mbus_dram_info();
3121 if (dram_target_info)
3122 mvneta_conf_mbus_windows(pp, dram_target_info);
3124 netif_napi_add(dev, &pp->napi, mvneta_poll, NAPI_POLL_WEIGHT);
3126 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO;
3127 dev->hw_features |= dev->features;
3128 dev->vlan_features |= dev->features;
3129 dev->priv_flags |= IFF_UNICAST_FLT;
3130 dev->gso_max_segs = MVNETA_MAX_TSO_SEGS;
3132 err = register_netdev(dev);
3134 dev_err(&pdev->dev, "failed to register\n");
3135 goto err_free_stats;
3138 netdev_info(dev, "Using %s mac address %pM\n", mac_from,
3141 platform_set_drvdata(pdev, pp->dev);
3143 if (pp->use_inband_status) {
3144 struct phy_device *phy = of_phy_find_device(dn);
3146 mvneta_fixed_link_update(pp, phy);
3152 free_percpu(pp->stats);
3154 clk_disable_unprepare(pp->clk);
3156 of_node_put(phy_node);
3158 irq_dispose_mapping(dev->irq);
3164 /* Device removal routine */
3165 static int mvneta_remove(struct platform_device *pdev)
3167 struct net_device *dev = platform_get_drvdata(pdev);
3168 struct mvneta_port *pp = netdev_priv(dev);
3170 unregister_netdev(dev);
3171 clk_disable_unprepare(pp->clk);
3172 free_percpu(pp->stats);
3173 irq_dispose_mapping(dev->irq);
3174 of_node_put(pp->phy_node);
3180 static const struct of_device_id mvneta_match[] = {
3181 { .compatible = "marvell,armada-370-neta" },
3184 MODULE_DEVICE_TABLE(of, mvneta_match);
3186 static struct platform_driver mvneta_driver = {
3187 .probe = mvneta_probe,
3188 .remove = mvneta_remove,
3190 .name = MVNETA_DRIVER_NAME,
3191 .of_match_table = mvneta_match,
3195 module_platform_driver(mvneta_driver);
3197 MODULE_DESCRIPTION("Marvell NETA Ethernet Driver - www.marvell.com");
3198 MODULE_AUTHOR("Rami Rosen <rosenr@marvell.com>, Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
3199 MODULE_LICENSE("GPL");
3201 module_param(rxq_number, int, S_IRUGO);
3202 module_param(txq_number, int, S_IRUGO);
3204 module_param(rxq_def, int, S_IRUGO);
3205 module_param(rx_copybreak, int, S_IRUGO | S_IWUSR);
projects / cascardo / linux.git / blob