drivers/net/ethernet/mellanox/mlx4/cmd.c

   1 /*
   2  * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
   4  * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc.  All rights reserved.
   5  *
   6  * This software is available to you under a choice of one of two
   7  * licenses.  You may choose to be licensed under the terms of the GNU
   8  * General Public License (GPL) Version 2, available from the file
   9  * COPYING in the main directory of this source tree, or the
  10  * OpenIB.org BSD license below:
  11  *
  12  *     Redistribution and use in source and binary forms, with or
  13  *     without modification, are permitted provided that the following
  14  *     conditions are met:
  15  *
  16  *      - Redistributions of source code must retain the above
  17  *        copyright notice, this list of conditions and the following
  18  *        disclaimer.
  19  *
  20  *      - Redistributions in binary form must reproduce the above
  21  *        copyright notice, this list of conditions and the following
  22  *        disclaimer in the documentation and/or other materials
  23  *        provided with the distribution.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32  * SOFTWARE.
  33  */
  34
  35 #include <linux/sched.h>
  36 #include <linux/slab.h>
  37 #include <linux/export.h>
  38 #include <linux/pci.h>
  39 #include <linux/errno.h>
  40
  41 #include <linux/mlx4/cmd.h>
  42 #include <linux/mlx4/device.h>
  43 #include <linux/semaphore.h>
  44 #include <rdma/ib_smi.h>
  45
  46 #include <asm/io.h>
  47
  48 #include "mlx4.h"
  49 #include "fw.h"
  50
  51 #define CMD_POLL_TOKEN 0xffff
  52 #define INBOX_MASK      0xffffffffffffff00ULL
  53
  54 #define CMD_CHAN_VER 1
  55 #define CMD_CHAN_IF_REV 1
  56
  57 enum {
  58         /* command completed successfully: */
  59         CMD_STAT_OK             = 0x00,
  60         /* Internal error (such as a bus error) occurred while processing command: */
  61         CMD_STAT_INTERNAL_ERR   = 0x01,
  62         /* Operation/command not supported or opcode modifier not supported: */
  63         CMD_STAT_BAD_OP         = 0x02,
  64         /* Parameter not supported or parameter out of range: */
  65         CMD_STAT_BAD_PARAM      = 0x03,
  66         /* System not enabled or bad system state: */
  67         CMD_STAT_BAD_SYS_STATE  = 0x04,
  68         /* Attempt to access reserved or unallocaterd resource: */
  69         CMD_STAT_BAD_RESOURCE   = 0x05,
  70         /* Requested resource is currently executing a command, or is otherwise busy: */
  71         CMD_STAT_RESOURCE_BUSY  = 0x06,
  72         /* Required capability exceeds device limits: */
  73         CMD_STAT_EXCEED_LIM     = 0x08,
  74         /* Resource is not in the appropriate state or ownership: */
  75         CMD_STAT_BAD_RES_STATE  = 0x09,
  76         /* Index out of range: */
  77         CMD_STAT_BAD_INDEX      = 0x0a,
  78         /* FW image corrupted: */
  79         CMD_STAT_BAD_NVMEM      = 0x0b,
  80         /* Error in ICM mapping (e.g. not enough auxiliary ICM pages to execute command): */
  81         CMD_STAT_ICM_ERROR      = 0x0c,
  82         /* Attempt to modify a QP/EE which is not in the presumed state: */
  83         CMD_STAT_BAD_QP_STATE   = 0x10,
  84         /* Bad segment parameters (Address/Size): */
  85         CMD_STAT_BAD_SEG_PARAM  = 0x20,
  86         /* Memory Region has Memory Windows bound to: */
  87         CMD_STAT_REG_BOUND      = 0x21,
  88         /* HCA local attached memory not present: */
  89         CMD_STAT_LAM_NOT_PRE    = 0x22,
  90         /* Bad management packet (silently discarded): */
  91         CMD_STAT_BAD_PKT        = 0x30,
  92         /* More outstanding CQEs in CQ than new CQ size: */
  93         CMD_STAT_BAD_SIZE       = 0x40,
  94         /* Multi Function device support required: */
  95         CMD_STAT_MULTI_FUNC_REQ = 0x50,
  96 };
  97
  98 enum {
  99         HCR_IN_PARAM_OFFSET     = 0x00,
 100         HCR_IN_MODIFIER_OFFSET  = 0x08,
 101         HCR_OUT_PARAM_OFFSET    = 0x0c,
 102         HCR_TOKEN_OFFSET        = 0x14,
 103         HCR_STATUS_OFFSET       = 0x18,
 104
 105         HCR_OPMOD_SHIFT         = 12,
 106         HCR_T_BIT               = 21,
 107         HCR_E_BIT               = 22,
 108         HCR_GO_BIT              = 23
 109 };
 110
 111 enum {
 112         GO_BIT_TIMEOUT_MSECS    = 10000
 113 };
 114
 115 struct mlx4_cmd_context {
 116         struct completion       done;
 117         int                     result;
 118         int                     next;
 119         u64                     out_param;
 120         u16                     token;
 121         u8                      fw_status;
 122 };
 123
 124 static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave,
 125                                     struct mlx4_vhcr_cmd *in_vhcr);
 126
 127 static int mlx4_status_to_errno(u8 status)
 128 {
 129         static const int trans_table[] = {
 130                 [CMD_STAT_INTERNAL_ERR]   = -EIO,
 131                 [CMD_STAT_BAD_OP]         = -EPERM,
 132                 [CMD_STAT_BAD_PARAM]      = -EINVAL,
 133                 [CMD_STAT_BAD_SYS_STATE]  = -ENXIO,
 134                 [CMD_STAT_BAD_RESOURCE]   = -EBADF,
 135                 [CMD_STAT_RESOURCE_BUSY]  = -EBUSY,
 136                 [CMD_STAT_EXCEED_LIM]     = -ENOMEM,
 137                 [CMD_STAT_BAD_RES_STATE]  = -EBADF,
 138                 [CMD_STAT_BAD_INDEX]      = -EBADF,
 139                 [CMD_STAT_BAD_NVMEM]      = -EFAULT,
 140                 [CMD_STAT_ICM_ERROR]      = -ENFILE,
 141                 [CMD_STAT_BAD_QP_STATE]   = -EINVAL,
 142                 [CMD_STAT_BAD_SEG_PARAM]  = -EFAULT,
 143                 [CMD_STAT_REG_BOUND]      = -EBUSY,
 144                 [CMD_STAT_LAM_NOT_PRE]    = -EAGAIN,
 145                 [CMD_STAT_BAD_PKT]        = -EINVAL,
 146                 [CMD_STAT_BAD_SIZE]       = -ENOMEM,
 147                 [CMD_STAT_MULTI_FUNC_REQ] = -EACCES,
 148         };
 149
 150         if (status >= ARRAY_SIZE(trans_table) ||
 151             (status != CMD_STAT_OK && trans_table[status] == 0))
 152                 return -EIO;
 153
 154         return trans_table[status];
 155 }
 156
 157 static u8 mlx4_errno_to_status(int errno)
 158 {
 159         switch (errno) {
 160         case -EPERM:
 161                 return CMD_STAT_BAD_OP;
 162         case -EINVAL:
 163                 return CMD_STAT_BAD_PARAM;
 164         case -ENXIO:
 165                 return CMD_STAT_BAD_SYS_STATE;
 166         case -EBUSY:
 167                 return CMD_STAT_RESOURCE_BUSY;
 168         case -ENOMEM:
 169                 return CMD_STAT_EXCEED_LIM;
 170         case -ENFILE:
 171                 return CMD_STAT_ICM_ERROR;
 172         default:
 173                 return CMD_STAT_INTERNAL_ERR;
 174         }
 175 }
 176
 177 static int comm_pending(struct mlx4_dev *dev)
 178 {
 179         struct mlx4_priv *priv = mlx4_priv(dev);
 180         u32 status = readl(&priv->mfunc.comm->slave_read);
 181
 182         return (swab32(status) >> 31) != priv->cmd.comm_toggle;
 183 }
 184
 185 static void mlx4_comm_cmd_post(struct mlx4_dev *dev, u8 cmd, u16 param)
 186 {
 187         struct mlx4_priv *priv = mlx4_priv(dev);
 188         u32 val;
 189
 190         priv->cmd.comm_toggle ^= 1;
 191         val = param | (cmd << 16) | (priv->cmd.comm_toggle << 31);
 192         __raw_writel((__force u32) cpu_to_be32(val),
 193                      &priv->mfunc.comm->slave_write);
 194         mmiowb();
 195 }
 196
 197 static int mlx4_comm_cmd_poll(struct mlx4_dev *dev, u8 cmd, u16 param,
 198                        unsigned long timeout)
 199 {
 200         struct mlx4_priv *priv = mlx4_priv(dev);
 201         unsigned long end;
 202         int err = 0;
 203         int ret_from_pending = 0;
 204
 205         /* First, verify that the master reports correct status */
 206         if (comm_pending(dev)) {
 207                 mlx4_warn(dev, "Communication channel is not idle."
 208                           "my toggle is %d (cmd:0x%x)\n",
 209                           priv->cmd.comm_toggle, cmd);
 210                 return -EAGAIN;
 211         }
 212
 213         /* Write command */
 214         down(&priv->cmd.poll_sem);
 215         mlx4_comm_cmd_post(dev, cmd, param);
 216
 217         end = msecs_to_jiffies(timeout) + jiffies;
 218         while (comm_pending(dev) && time_before(jiffies, end))
 219                 cond_resched();
 220         ret_from_pending = comm_pending(dev);
 221         if (ret_from_pending) {
 222                 /* check if the slave is trying to boot in the middle of
 223                  * FLR process. The only non-zero result in the RESET command
 224                  * is MLX4_DELAY_RESET_SLAVE*/
 225                 if ((MLX4_COMM_CMD_RESET == cmd)) {
 226                         err = MLX4_DELAY_RESET_SLAVE;
 227                 } else {
 228                         mlx4_warn(dev, "Communication channel timed out\n");
 229                         err = -ETIMEDOUT;
 230                 }
 231         }
 232
 233         up(&priv->cmd.poll_sem);
 234         return err;
 235 }
 236
 237 static int mlx4_comm_cmd_wait(struct mlx4_dev *dev, u8 op,
 238                               u16 param, unsigned long timeout)
 239 {
 240         struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
 241         struct mlx4_cmd_context *context;
 242         unsigned long end;
 243         int err = 0;
 244
 245         down(&cmd->event_sem);
 246
 247         spin_lock(&cmd->context_lock);
 248         BUG_ON(cmd->free_head < 0);
 249         context = &cmd->context[cmd->free_head];
 250         context->token += cmd->token_mask + 1;
 251         cmd->free_head = context->next;
 252         spin_unlock(&cmd->context_lock);
 253
 254         init_completion(&context->done);
 255
 256         mlx4_comm_cmd_post(dev, op, param);
 257
 258         if (!wait_for_completion_timeout(&context->done,
 259                                          msecs_to_jiffies(timeout))) {
 260                 err = -EBUSY;
 261                 goto out;
 262         }
 263
 264         err = context->result;
 265         if (err && context->fw_status != CMD_STAT_MULTI_FUNC_REQ) {
 266                 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
 267                          op, context->fw_status);
 268                 goto out;
 269         }
 270
 271 out:
 272         /* wait for comm channel ready
 273          * this is necessary for prevention the race
 274          * when switching between event to polling mode
 275          */
 276         end = msecs_to_jiffies(timeout) + jiffies;
 277         while (comm_pending(dev) && time_before(jiffies, end))
 278                 cond_resched();
 279
 280         spin_lock(&cmd->context_lock);
 281         context->next = cmd->free_head;
 282         cmd->free_head = context - cmd->context;
 283         spin_unlock(&cmd->context_lock);
 284
 285         up(&cmd->event_sem);
 286         return err;
 287 }
 288
 289 int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
 290                   unsigned long timeout)
 291 {
 292         if (mlx4_priv(dev)->cmd.use_events)
 293                 return mlx4_comm_cmd_wait(dev, cmd, param, timeout);
 294         return mlx4_comm_cmd_poll(dev, cmd, param, timeout);
 295 }
 296
 297 static int cmd_pending(struct mlx4_dev *dev)
 298 {
 299         u32 status;
 300
 301         if (pci_channel_offline(dev->pdev))
 302                 return -EIO;
 303
 304         status = readl(mlx4_priv(dev)->cmd.hcr + HCR_STATUS_OFFSET);
 305
 306         return (status & swab32(1 << HCR_GO_BIT)) ||
 307                 (mlx4_priv(dev)->cmd.toggle ==
 308                  !!(status & swab32(1 << HCR_T_BIT)));
 309 }
 310
 311 static int mlx4_cmd_post(struct mlx4_dev *dev, u64 in_param, u64 out_param,
 312                          u32 in_modifier, u8 op_modifier, u16 op, u16 token,
 313                          int event)
 314 {
 315         struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
 316         u32 __iomem *hcr = cmd->hcr;
 317         int ret = -EAGAIN;
 318         unsigned long end;
 319
 320         mutex_lock(&cmd->hcr_mutex);
 321
 322         if (pci_channel_offline(dev->pdev)) {
 323                 /*
 324                  * Device is going through error recovery
 325                  * and cannot accept commands.
 326                  */
 327                 ret = -EIO;
 328                 goto out;
 329         }
 330
 331         end = jiffies;
 332         if (event)
 333                 end += msecs_to_jiffies(GO_BIT_TIMEOUT_MSECS);
 334
 335         while (cmd_pending(dev)) {
 336                 if (pci_channel_offline(dev->pdev)) {
 337                         /*
 338                          * Device is going through error recovery
 339                          * and cannot accept commands.
 340                          */
 341                         ret = -EIO;
 342                         goto out;
 343                 }
 344
 345                 if (time_after_eq(jiffies, end)) {
 346                         mlx4_err(dev, "%s:cmd_pending failed\n", __func__);
 347                         goto out;
 348                 }
 349                 cond_resched();
 350         }
 351
 352         /*
 353          * We use writel (instead of something like memcpy_toio)
 354          * because writes of less than 32 bits to the HCR don't work
 355          * (and some architectures such as ia64 implement memcpy_toio
 356          * in terms of writeb).
 357          */
 358         __raw_writel((__force u32) cpu_to_be32(in_param >> 32),           hcr + 0);
 359         __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful),  hcr + 1);
 360         __raw_writel((__force u32) cpu_to_be32(in_modifier),              hcr + 2);
 361         __raw_writel((__force u32) cpu_to_be32(out_param >> 32),          hcr + 3);
 362         __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), hcr + 4);
 363         __raw_writel((__force u32) cpu_to_be32(token << 16),              hcr + 5);
 364
 365         /* __raw_writel may not order writes. */
 366         wmb();
 367
 368         __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT)                |
 369                                                (cmd->toggle << HCR_T_BIT)       |
 370                                                (event ? (1 << HCR_E_BIT) : 0)   |
 371                                                (op_modifier << HCR_OPMOD_SHIFT) |
 372                                                op), hcr + 6);
 373
 374         /*
 375          * Make sure that our HCR writes don't get mixed in with
 376          * writes from another CPU starting a FW command.
 377          */
 378         mmiowb();
 379
 380         cmd->toggle = cmd->toggle ^ 1;
 381
 382         ret = 0;
 383
 384 out:
 385         mutex_unlock(&cmd->hcr_mutex);
 386         return ret;
 387 }
 388
 389 static int mlx4_slave_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
 390                           int out_is_imm, u32 in_modifier, u8 op_modifier,
 391                           u16 op, unsigned long timeout)
 392 {
 393         struct mlx4_priv *priv = mlx4_priv(dev);
 394         struct mlx4_vhcr_cmd *vhcr = priv->mfunc.vhcr;
 395         int ret;
 396
 397         mutex_lock(&priv->cmd.slave_cmd_mutex);
 398
 399         vhcr->in_param = cpu_to_be64(in_param);
 400         vhcr->out_param = out_param ? cpu_to_be64(*out_param) : 0;
 401         vhcr->in_modifier = cpu_to_be32(in_modifier);
 402         vhcr->opcode = cpu_to_be16((((u16) op_modifier) << 12) | (op & 0xfff));
 403         vhcr->token = cpu_to_be16(CMD_POLL_TOKEN);
 404         vhcr->status = 0;
 405         vhcr->flags = !!(priv->cmd.use_events) << 6;
 406
 407         if (mlx4_is_master(dev)) {
 408                 ret = mlx4_master_process_vhcr(dev, dev->caps.function, vhcr);
 409                 if (!ret) {
 410                         if (out_is_imm) {
 411                                 if (out_param)
 412                                         *out_param =
 413                                                 be64_to_cpu(vhcr->out_param);
 414                                 else {
 415                                         mlx4_err(dev, "response expected while"
 416                                                  "output mailbox is NULL for "
 417                                                  "command 0x%x\n", op);
 418                                         vhcr->status = CMD_STAT_BAD_PARAM;
 419                                 }
 420                         }
 421                         ret = mlx4_status_to_errno(vhcr->status);
 422                 }
 423         } else {
 424                 ret = mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_POST, 0,
 425                                     MLX4_COMM_TIME + timeout);
 426                 if (!ret) {
 427                         if (out_is_imm) {
 428                                 if (out_param)
 429                                         *out_param =
 430                                                 be64_to_cpu(vhcr->out_param);
 431                                 else {
 432                                         mlx4_err(dev, "response expected while"
 433                                                  "output mailbox is NULL for "
 434                                                  "command 0x%x\n", op);
 435                                         vhcr->status = CMD_STAT_BAD_PARAM;
 436                                 }
 437                         }
 438                         ret = mlx4_status_to_errno(vhcr->status);
 439                 } else
 440                         mlx4_err(dev, "failed execution of VHCR_POST command"
 441                                  "opcode 0x%x\n", op);
 442         }
 443
 444         mutex_unlock(&priv->cmd.slave_cmd_mutex);
 445         return ret;
 446 }
 447
 448 static int mlx4_cmd_poll(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
 449                          int out_is_imm, u32 in_modifier, u8 op_modifier,
 450                          u16 op, unsigned long timeout)
 451 {
 452         struct mlx4_priv *priv = mlx4_priv(dev);
 453         void __iomem *hcr = priv->cmd.hcr;
 454         int err = 0;
 455         unsigned long end;
 456         u32 stat;
 457
 458         down(&priv->cmd.poll_sem);
 459
 460         if (pci_channel_offline(dev->pdev)) {
 461                 /*
 462                  * Device is going through error recovery
 463                  * and cannot accept commands.
 464                  */
 465                 err = -EIO;
 466                 goto out;
 467         }
 468
 469         err = mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0,
 470                             in_modifier, op_modifier, op, CMD_POLL_TOKEN, 0);
 471         if (err)
 472                 goto out;
 473
 474         end = msecs_to_jiffies(timeout) + jiffies;
 475         while (cmd_pending(dev) && time_before(jiffies, end)) {
 476                 if (pci_channel_offline(dev->pdev)) {
 477                         /*
 478                          * Device is going through error recovery
 479                          * and cannot accept commands.
 480                          */
 481                         err = -EIO;
 482                         goto out;
 483                 }
 484
 485                 cond_resched();
 486         }
 487
 488         if (cmd_pending(dev)) {
 489                 err = -ETIMEDOUT;
 490                 goto out;
 491         }
 492
 493         if (out_is_imm)
 494                 *out_param =
 495                         (u64) be32_to_cpu((__force __be32)
 496                                           __raw_readl(hcr + HCR_OUT_PARAM_OFFSET)) << 32 |
 497                         (u64) be32_to_cpu((__force __be32)
 498                                           __raw_readl(hcr + HCR_OUT_PARAM_OFFSET + 4));
 499         stat = be32_to_cpu((__force __be32)
 500                            __raw_readl(hcr + HCR_STATUS_OFFSET)) >> 24;
 501         err = mlx4_status_to_errno(stat);
 502         if (err)
 503                 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
 504                          op, stat);
 505
 506 out:
 507         up(&priv->cmd.poll_sem);
 508         return err;
 509 }
 510
 511 void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param)
 512 {
 513         struct mlx4_priv *priv = mlx4_priv(dev);
 514         struct mlx4_cmd_context *context =
 515                 &priv->cmd.context[token & priv->cmd.token_mask];
 516
 517         /* previously timed out command completing at long last */
 518         if (token != context->token)
 519                 return;
 520
 521         context->fw_status = status;
 522         context->result    = mlx4_status_to_errno(status);
 523         context->out_param = out_param;
 524
 525         complete(&context->done);
 526 }
 527
 528 static int mlx4_cmd_wait(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
 529                          int out_is_imm, u32 in_modifier, u8 op_modifier,
 530                          u16 op, unsigned long timeout)
 531 {
 532         struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
 533         struct mlx4_cmd_context *context;
 534         int err = 0;
 535
 536         down(&cmd->event_sem);
 537
 538         spin_lock(&cmd->context_lock);
 539         BUG_ON(cmd->free_head < 0);
 540         context = &cmd->context[cmd->free_head];
 541         context->token += cmd->token_mask + 1;
 542         cmd->free_head = context->next;
 543         spin_unlock(&cmd->context_lock);
 544
 545         init_completion(&context->done);
 546
 547         mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0,
 548                       in_modifier, op_modifier, op, context->token, 1);
 549
 550         if (!wait_for_completion_timeout(&context->done,
 551                                          msecs_to_jiffies(timeout))) {
 552                 err = -EBUSY;
 553                 goto out;
 554         }
 555
 556         err = context->result;
 557         if (err) {
 558                 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
 559                          op, context->fw_status);
 560                 goto out;
 561         }
 562
 563         if (out_is_imm)
 564                 *out_param = context->out_param;
 565
 566 out:
 567         spin_lock(&cmd->context_lock);
 568         context->next = cmd->free_head;
 569         cmd->free_head = context - cmd->context;
 570         spin_unlock(&cmd->context_lock);
 571
 572         up(&cmd->event_sem);
 573         return err;
 574 }
 575
 576 int __mlx4_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
 577                int out_is_imm, u32 in_modifier, u8 op_modifier,
 578                u16 op, unsigned long timeout, int native)
 579 {
 580         if (pci_channel_offline(dev->pdev))
 581                 return -EIO;
 582
 583         if (!mlx4_is_mfunc(dev) || (native && mlx4_is_master(dev))) {
 584                 if (mlx4_priv(dev)->cmd.use_events)
 585                         return mlx4_cmd_wait(dev, in_param, out_param,
 586                                              out_is_imm, in_modifier,
 587                                              op_modifier, op, timeout);
 588                 else
 589                         return mlx4_cmd_poll(dev, in_param, out_param,
 590                                              out_is_imm, in_modifier,
 591                                              op_modifier, op, timeout);
 592         }
 593         return mlx4_slave_cmd(dev, in_param, out_param, out_is_imm,
 594                               in_modifier, op_modifier, op, timeout);
 595 }
 596 EXPORT_SYMBOL_GPL(__mlx4_cmd);
 597
 598
 599 static int mlx4_ARM_COMM_CHANNEL(struct mlx4_dev *dev)
 600 {
 601         return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_ARM_COMM_CHANNEL,
 602                         MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
 603 }
 604
 605 static int mlx4_ACCESS_MEM(struct mlx4_dev *dev, u64 master_addr,
 606                            int slave, u64 slave_addr,
 607                            int size, int is_read)
 608 {
 609         u64 in_param;
 610         u64 out_param;
 611
 612         if ((slave_addr & 0xfff) | (master_addr & 0xfff) |
 613             (slave & ~0x7f) | (size & 0xff)) {
 614                 mlx4_err(dev, "Bad access mem params - slave_addr:0x%llx "
 615                               "master_addr:0x%llx slave_id:%d size:%d\n",
 616                               slave_addr, master_addr, slave, size);
 617                 return -EINVAL;
 618         }
 619
 620         if (is_read) {
 621                 in_param = (u64) slave | slave_addr;
 622                 out_param = (u64) dev->caps.function | master_addr;
 623         } else {
 624                 in_param = (u64) dev->caps.function | master_addr;
 625                 out_param = (u64) slave | slave_addr;
 626         }
 627
 628         return mlx4_cmd_imm(dev, in_param, &out_param, size, 0,
 629                             MLX4_CMD_ACCESS_MEM,
 630                             MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
 631 }
 632
 633 static int query_pkey_block(struct mlx4_dev *dev, u8 port, u16 index, u16 *pkey,
 634                                struct mlx4_cmd_mailbox *inbox,
 635                                struct mlx4_cmd_mailbox *outbox)
 636 {
 637         struct ib_smp *in_mad = (struct ib_smp *)(inbox->buf);
 638         struct ib_smp *out_mad = (struct ib_smp *)(outbox->buf);
 639         int err;
 640         int i;
 641
 642         if (index & 0x1f)
 643                 return -EINVAL;
 644
 645         in_mad->attr_mod = cpu_to_be32(index / 32);
 646
 647         err = mlx4_cmd_box(dev, inbox->dma, outbox->dma, port, 3,
 648                            MLX4_CMD_MAD_IFC, MLX4_CMD_TIME_CLASS_C,
 649                            MLX4_CMD_NATIVE);
 650         if (err)
 651                 return err;
 652
 653         for (i = 0; i < 32; ++i)
 654                 pkey[i] = be16_to_cpu(((__be16 *) out_mad->data)[i]);
 655
 656         return err;
 657 }
 658
 659 static int get_full_pkey_table(struct mlx4_dev *dev, u8 port, u16 *table,
 660                                struct mlx4_cmd_mailbox *inbox,
 661                                struct mlx4_cmd_mailbox *outbox)
 662 {
 663         int i;
 664         int err;
 665
 666         for (i = 0; i < dev->caps.pkey_table_len[port]; i += 32) {
 667                 err = query_pkey_block(dev, port, i, table + i, inbox, outbox);
 668                 if (err)
 669                         return err;
 670         }
 671
 672         return 0;
 673 }
 674 #define PORT_CAPABILITY_LOCATION_IN_SMP 20
 675 #define PORT_STATE_OFFSET 32
 676
 677 static enum ib_port_state vf_port_state(struct mlx4_dev *dev, int port, int vf)
 678 {
 679         if (mlx4_get_slave_port_state(dev, vf, port) == SLAVE_PORT_UP)
 680                 return IB_PORT_ACTIVE;
 681         else
 682                 return IB_PORT_DOWN;
 683 }
 684
 685 static int mlx4_MAD_IFC_wrapper(struct mlx4_dev *dev, int slave,
 686                                 struct mlx4_vhcr *vhcr,
 687                                 struct mlx4_cmd_mailbox *inbox,
 688                                 struct mlx4_cmd_mailbox *outbox,
 689                                 struct mlx4_cmd_info *cmd)
 690 {
 691         struct ib_smp *smp = inbox->buf;
 692         u32 index;
 693         u8 port;
 694         u16 *table;
 695         int err;
 696         int vidx, pidx;
 697         struct mlx4_priv *priv = mlx4_priv(dev);
 698         struct ib_smp *outsmp = outbox->buf;
 699         __be16 *outtab = (__be16 *)(outsmp->data);
 700         __be32 slave_cap_mask;
 701         __be64 slave_node_guid;
 702         port = vhcr->in_modifier;
 703
 704         if (smp->base_version == 1 &&
 705             smp->mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED &&
 706             smp->class_version == 1) {
 707                 if (smp->method == IB_MGMT_METHOD_GET) {
 708                         if (smp->attr_id == IB_SMP_ATTR_PKEY_TABLE) {
 709                                 index = be32_to_cpu(smp->attr_mod);
 710                                 if (port < 1 || port > dev->caps.num_ports)
 711                                         return -EINVAL;
 712                                 table = kcalloc(dev->caps.pkey_table_len[port], sizeof *table, GFP_KERNEL);
 713                                 if (!table)
 714                                         return -ENOMEM;
 715                                 /* need to get the full pkey table because the paravirtualized
 716                                  * pkeys may be scattered among several pkey blocks.
 717                                  */
 718                                 err = get_full_pkey_table(dev, port, table, inbox, outbox);
 719                                 if (!err) {
 720                                         for (vidx = index * 32; vidx < (index + 1) * 32; ++vidx) {
 721                                                 pidx = priv->virt2phys_pkey[slave][port - 1][vidx];
 722                                                 outtab[vidx % 32] = cpu_to_be16(table[pidx]);
 723                                         }
 724                                 }
 725                                 kfree(table);
 726                                 return err;
 727                         }
 728                         if (smp->attr_id == IB_SMP_ATTR_PORT_INFO) {
 729                                 /*get the slave specific caps:*/
 730                                 /*do the command */
 731                                 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
 732                                             vhcr->in_modifier, vhcr->op_modifier,
 733                                             vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
 734                                 /* modify the response for slaves */
 735                                 if (!err && slave != mlx4_master_func_num(dev)) {
 736                                         u8 *state = outsmp->data + PORT_STATE_OFFSET;
 737
 738                                         *state = (*state & 0xf0) | vf_port_state(dev, port, slave);
 739                                         slave_cap_mask = priv->mfunc.master.slave_state[slave].ib_cap_mask[port];
 740                                         memcpy(outsmp->data + PORT_CAPABILITY_LOCATION_IN_SMP, &slave_cap_mask, 4);
 741                                 }
 742                                 return err;
 743                         }
 744                         if (smp->attr_id == IB_SMP_ATTR_GUID_INFO) {
 745                                 /* compute slave's gid block */
 746                                 smp->attr_mod = cpu_to_be32(slave / 8);
 747                                 /* execute cmd */
 748                                 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
 749                                              vhcr->in_modifier, vhcr->op_modifier,
 750                                              vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
 751                                 if (!err) {
 752                                         /* if needed, move slave gid to index 0 */
 753                                         if (slave % 8)
 754                                                 memcpy(outsmp->data,
 755                                                        outsmp->data + (slave % 8) * 8, 8);
 756                                         /* delete all other gids */
 757                                         memset(outsmp->data + 8, 0, 56);
 758                                 }
 759                                 return err;
 760                         }
 761                         if (smp->attr_id == IB_SMP_ATTR_NODE_INFO) {
 762                                 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
 763                                              vhcr->in_modifier, vhcr->op_modifier,
 764                                              vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
 765                                 if (!err) {
 766                                         slave_node_guid =  mlx4_get_slave_node_guid(dev, slave);
 767                                         memcpy(outsmp->data + 12, &slave_node_guid, 8);
 768                                 }
 769                                 return err;
 770                         }
 771                 }
 772         }
 773         if (slave != mlx4_master_func_num(dev) &&
 774             ((smp->mgmt_class == IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE) ||
 775              (smp->mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED &&
 776               smp->method == IB_MGMT_METHOD_SET))) {
 777                 mlx4_err(dev, "slave %d is trying to execute a Subnet MGMT MAD, "
 778                          "class 0x%x, method 0x%x for attr 0x%x. Rejecting\n",
 779                          slave, smp->method, smp->mgmt_class,
 780                          be16_to_cpu(smp->attr_id));
 781                 return -EPERM;
 782         }
 783         /*default:*/
 784         return mlx4_cmd_box(dev, inbox->dma, outbox->dma,
 785                                     vhcr->in_modifier, vhcr->op_modifier,
 786                                     vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
 787 }
 788
 789 int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
 790                      struct mlx4_vhcr *vhcr,
 791                      struct mlx4_cmd_mailbox *inbox,
 792                      struct mlx4_cmd_mailbox *outbox,
 793                      struct mlx4_cmd_info *cmd)
 794 {
 795         u64 in_param;
 796         u64 out_param;
 797         int err;
 798
 799         in_param = cmd->has_inbox ? (u64) inbox->dma : vhcr->in_param;
 800         out_param = cmd->has_outbox ? (u64) outbox->dma : vhcr->out_param;
 801         if (cmd->encode_slave_id) {
 802                 in_param &= 0xffffffffffffff00ll;
 803                 in_param |= slave;
 804         }
 805
 806         err = __mlx4_cmd(dev, in_param, &out_param, cmd->out_is_imm,
 807                          vhcr->in_modifier, vhcr->op_modifier, vhcr->op,
 808                          MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
 809
 810         if (cmd->out_is_imm)
 811                 vhcr->out_param = out_param;
 812
 813         return err;
 814 }
 815
 816 static struct mlx4_cmd_info cmd_info[] = {
 817         {
 818                 .opcode = MLX4_CMD_QUERY_FW,
 819                 .has_inbox = false,
 820                 .has_outbox = true,
 821                 .out_is_imm = false,
 822                 .encode_slave_id = false,
 823                 .verify = NULL,
 824                 .wrapper = mlx4_QUERY_FW_wrapper
 825         },
 826         {
 827                 .opcode = MLX4_CMD_QUERY_HCA,
 828                 .has_inbox = false,
 829                 .has_outbox = true,
 830                 .out_is_imm = false,
 831                 .encode_slave_id = false,
 832                 .verify = NULL,
 833                 .wrapper = NULL
 834         },
 835         {
 836                 .opcode = MLX4_CMD_QUERY_DEV_CAP,
 837                 .has_inbox = false,
 838                 .has_outbox = true,
 839                 .out_is_imm = false,
 840                 .encode_slave_id = false,
 841                 .verify = NULL,
 842                 .wrapper = mlx4_QUERY_DEV_CAP_wrapper
 843         },
 844         {
 845                 .opcode = MLX4_CMD_QUERY_FUNC_CAP,
 846                 .has_inbox = false,
 847                 .has_outbox = true,
 848                 .out_is_imm = false,
 849                 .encode_slave_id = false,
 850                 .verify = NULL,
 851                 .wrapper = mlx4_QUERY_FUNC_CAP_wrapper
 852         },
 853         {
 854                 .opcode = MLX4_CMD_QUERY_ADAPTER,
 855                 .has_inbox = false,
 856                 .has_outbox = true,
 857                 .out_is_imm = false,
 858                 .encode_slave_id = false,
 859                 .verify = NULL,
 860                 .wrapper = NULL
 861         },
 862         {
 863                 .opcode = MLX4_CMD_INIT_PORT,
 864                 .has_inbox = false,
 865                 .has_outbox = false,
 866                 .out_is_imm = false,
 867                 .encode_slave_id = false,
 868                 .verify = NULL,
 869                 .wrapper = mlx4_INIT_PORT_wrapper
 870         },
 871         {
 872                 .opcode = MLX4_CMD_CLOSE_PORT,
 873                 .has_inbox = false,
 874                 .has_outbox = false,
 875                 .out_is_imm  = false,
 876                 .encode_slave_id = false,
 877                 .verify = NULL,
 878                 .wrapper = mlx4_CLOSE_PORT_wrapper
 879         },
 880         {
 881                 .opcode = MLX4_CMD_QUERY_PORT,
 882                 .has_inbox = false,
 883                 .has_outbox = true,
 884                 .out_is_imm = false,
 885                 .encode_slave_id = false,
 886                 .verify = NULL,
 887                 .wrapper = mlx4_QUERY_PORT_wrapper
 888         },
 889         {
 890                 .opcode = MLX4_CMD_SET_PORT,
 891                 .has_inbox = true,
 892                 .has_outbox = false,
 893                 .out_is_imm = false,
 894                 .encode_slave_id = false,
 895                 .verify = NULL,
 896                 .wrapper = mlx4_SET_PORT_wrapper
 897         },
 898         {
 899                 .opcode = MLX4_CMD_MAP_EQ,
 900                 .has_inbox = false,
 901                 .has_outbox = false,
 902                 .out_is_imm = false,
 903                 .encode_slave_id = false,
 904                 .verify = NULL,
 905                 .wrapper = mlx4_MAP_EQ_wrapper
 906         },
 907         {
 908                 .opcode = MLX4_CMD_SW2HW_EQ,
 909                 .has_inbox = true,
 910                 .has_outbox = false,
 911                 .out_is_imm = false,
 912                 .encode_slave_id = true,
 913                 .verify = NULL,
 914                 .wrapper = mlx4_SW2HW_EQ_wrapper
 915         },
 916         {
 917                 .opcode = MLX4_CMD_HW_HEALTH_CHECK,
 918                 .has_inbox = false,
 919                 .has_outbox = false,
 920                 .out_is_imm = false,
 921                 .encode_slave_id = false,
 922                 .verify = NULL,
 923                 .wrapper = NULL
 924         },
 925         {
 926                 .opcode = MLX4_CMD_NOP,
 927                 .has_inbox = false,
 928                 .has_outbox = false,
 929                 .out_is_imm = false,
 930                 .encode_slave_id = false,
 931                 .verify = NULL,
 932                 .wrapper = NULL
 933         },
 934         {
 935                 .opcode = MLX4_CMD_ALLOC_RES,
 936                 .has_inbox = false,
 937                 .has_outbox = false,
 938                 .out_is_imm = true,
 939                 .encode_slave_id = false,
 940                 .verify = NULL,
 941                 .wrapper = mlx4_ALLOC_RES_wrapper
 942         },
 943         {
 944                 .opcode = MLX4_CMD_FREE_RES,
 945                 .has_inbox = false,
 946                 .has_outbox = false,
 947                 .out_is_imm = false,
 948                 .encode_slave_id = false,
 949                 .verify = NULL,
 950                 .wrapper = mlx4_FREE_RES_wrapper
 951         },
 952         {
 953                 .opcode = MLX4_CMD_SW2HW_MPT,
 954                 .has_inbox = true,
 955                 .has_outbox = false,
 956                 .out_is_imm = false,
 957                 .encode_slave_id = true,
 958                 .verify = NULL,
 959                 .wrapper = mlx4_SW2HW_MPT_wrapper
 960         },
 961         {
 962                 .opcode = MLX4_CMD_QUERY_MPT,
 963                 .has_inbox = false,
 964                 .has_outbox = true,
 965                 .out_is_imm = false,
 966                 .encode_slave_id = false,
 967                 .verify = NULL,
 968                 .wrapper = mlx4_QUERY_MPT_wrapper
 969         },
 970         {
 971                 .opcode = MLX4_CMD_HW2SW_MPT,
 972                 .has_inbox = false,
 973                 .has_outbox = false,
 974                 .out_is_imm = false,
 975                 .encode_slave_id = false,
 976                 .verify = NULL,
 977                 .wrapper = mlx4_HW2SW_MPT_wrapper
 978         },
 979         {
 980                 .opcode = MLX4_CMD_READ_MTT,
 981                 .has_inbox = false,
 982                 .has_outbox = true,
 983                 .out_is_imm = false,
 984                 .encode_slave_id = false,
 985                 .verify = NULL,
 986                 .wrapper = NULL
 987         },
 988         {
 989                 .opcode = MLX4_CMD_WRITE_MTT,
 990                 .has_inbox = true,
 991                 .has_outbox = false,
 992                 .out_is_imm = false,
 993                 .encode_slave_id = false,
 994                 .verify = NULL,
 995                 .wrapper = mlx4_WRITE_MTT_wrapper
 996         },
 997         {
 998                 .opcode = MLX4_CMD_SYNC_TPT,
 999                 .has_inbox = true,
1000                 .has_outbox = false,
1001                 .out_is_imm = false,
1002                 .encode_slave_id = false,
1003                 .verify = NULL,
1004                 .wrapper = NULL
1005         },
1006         {
1007                 .opcode = MLX4_CMD_HW2SW_EQ,
1008                 .has_inbox = false,
1009                 .has_outbox = true,
1010                 .out_is_imm = false,
1011                 .encode_slave_id = true,
1012                 .verify = NULL,
1013                 .wrapper = mlx4_HW2SW_EQ_wrapper
1014         },
1015         {
1016                 .opcode = MLX4_CMD_QUERY_EQ,
1017                 .has_inbox = false,
1018                 .has_outbox = true,
1019                 .out_is_imm = false,
1020                 .encode_slave_id = true,
1021                 .verify = NULL,
1022                 .wrapper = mlx4_QUERY_EQ_wrapper
1023         },
1024         {
1025                 .opcode = MLX4_CMD_SW2HW_CQ,
1026                 .has_inbox = true,
1027                 .has_outbox = false,
1028                 .out_is_imm = false,
1029                 .encode_slave_id = true,
1030                 .verify = NULL,
1031                 .wrapper = mlx4_SW2HW_CQ_wrapper
1032         },
1033         {
1034                 .opcode = MLX4_CMD_HW2SW_CQ,
1035                 .has_inbox = false,
1036                 .has_outbox = false,
1037                 .out_is_imm = false,
1038                 .encode_slave_id = false,
1039                 .verify = NULL,
1040                 .wrapper = mlx4_HW2SW_CQ_wrapper
1041         },
1042         {
1043                 .opcode = MLX4_CMD_QUERY_CQ,
1044                 .has_inbox = false,
1045                 .has_outbox = true,
1046                 .out_is_imm = false,
1047                 .encode_slave_id = false,
1048                 .verify = NULL,
1049                 .wrapper = mlx4_QUERY_CQ_wrapper
1050         },
1051         {
1052                 .opcode = MLX4_CMD_MODIFY_CQ,
1053                 .has_inbox = true,
1054                 .has_outbox = false,
1055                 .out_is_imm = true,
1056                 .encode_slave_id = false,
1057                 .verify = NULL,
1058                 .wrapper = mlx4_MODIFY_CQ_wrapper
1059         },
1060         {
1061                 .opcode = MLX4_CMD_SW2HW_SRQ,
1062                 .has_inbox = true,
1063                 .has_outbox = false,
1064                 .out_is_imm = false,
1065                 .encode_slave_id = true,
1066                 .verify = NULL,
1067                 .wrapper = mlx4_SW2HW_SRQ_wrapper
1068         },
1069         {
1070                 .opcode = MLX4_CMD_HW2SW_SRQ,
1071                 .has_inbox = false,
1072                 .has_outbox = false,
1073                 .out_is_imm = false,
1074                 .encode_slave_id = false,
1075                 .verify = NULL,
1076                 .wrapper = mlx4_HW2SW_SRQ_wrapper
1077         },
1078         {
1079                 .opcode = MLX4_CMD_QUERY_SRQ,
1080                 .has_inbox = false,
1081                 .has_outbox = true,
1082                 .out_is_imm = false,
1083                 .encode_slave_id = false,
1084                 .verify = NULL,
1085                 .wrapper = mlx4_QUERY_SRQ_wrapper
1086         },
1087         {
1088                 .opcode = MLX4_CMD_ARM_SRQ,
1089                 .has_inbox = false,
1090                 .has_outbox = false,
1091                 .out_is_imm = false,
1092                 .encode_slave_id = false,
1093                 .verify = NULL,
1094                 .wrapper = mlx4_ARM_SRQ_wrapper
1095         },
1096         {
1097                 .opcode = MLX4_CMD_RST2INIT_QP,
1098                 .has_inbox = true,
1099                 .has_outbox = false,
1100                 .out_is_imm = false,
1101                 .encode_slave_id = true,
1102                 .verify = NULL,
1103                 .wrapper = mlx4_RST2INIT_QP_wrapper
1104         },
1105         {
1106                 .opcode = MLX4_CMD_INIT2INIT_QP,
1107                 .has_inbox = true,
1108                 .has_outbox = false,
1109                 .out_is_imm = false,
1110                 .encode_slave_id = false,
1111                 .verify = NULL,
1112                 .wrapper = mlx4_INIT2INIT_QP_wrapper
1113         },
1114         {
1115                 .opcode = MLX4_CMD_INIT2RTR_QP,
1116                 .has_inbox = true,
1117                 .has_outbox = false,
1118                 .out_is_imm = false,
1119                 .encode_slave_id = false,
1120                 .verify = NULL,
1121                 .wrapper = mlx4_INIT2RTR_QP_wrapper
1122         },
1123         {
1124                 .opcode = MLX4_CMD_RTR2RTS_QP,
1125                 .has_inbox = true,
1126                 .has_outbox = false,
1127                 .out_is_imm = false,
1128                 .encode_slave_id = false,
1129                 .verify = NULL,
1130                 .wrapper = mlx4_RTR2RTS_QP_wrapper
1131         },
1132         {
1133                 .opcode = MLX4_CMD_RTS2RTS_QP,
1134                 .has_inbox = true,
1135                 .has_outbox = false,
1136                 .out_is_imm = false,
1137                 .encode_slave_id = false,
1138                 .verify = NULL,
1139                 .wrapper = mlx4_RTS2RTS_QP_wrapper
1140         },
1141         {
1142                 .opcode = MLX4_CMD_SQERR2RTS_QP,
1143                 .has_inbox = true,
1144                 .has_outbox = false,
1145                 .out_is_imm = false,
1146                 .encode_slave_id = false,
1147                 .verify = NULL,
1148                 .wrapper = mlx4_SQERR2RTS_QP_wrapper
1149         },
1150         {
1151                 .opcode = MLX4_CMD_2ERR_QP,
1152                 .has_inbox = false,
1153                 .has_outbox = false,
1154                 .out_is_imm = false,
1155                 .encode_slave_id = false,
1156                 .verify = NULL,
1157                 .wrapper = mlx4_GEN_QP_wrapper
1158         },
1159         {
1160                 .opcode = MLX4_CMD_RTS2SQD_QP,
1161                 .has_inbox = false,
1162                 .has_outbox = false,
1163                 .out_is_imm = false,
1164                 .encode_slave_id = false,
1165                 .verify = NULL,
1166                 .wrapper = mlx4_GEN_QP_wrapper
1167         },
1168         {
1169                 .opcode = MLX4_CMD_SQD2SQD_QP,
1170                 .has_inbox = true,
1171                 .has_outbox = false,
1172                 .out_is_imm = false,
1173                 .encode_slave_id = false,
1174                 .verify = NULL,
1175                 .wrapper = mlx4_SQD2SQD_QP_wrapper
1176         },
1177         {
1178                 .opcode = MLX4_CMD_SQD2RTS_QP,
1179                 .has_inbox = true,
1180                 .has_outbox = false,
1181                 .out_is_imm = false,
1182                 .encode_slave_id = false,
1183                 .verify = NULL,
1184                 .wrapper = mlx4_SQD2RTS_QP_wrapper
1185         },
1186         {
1187                 .opcode = MLX4_CMD_2RST_QP,
1188                 .has_inbox = false,
1189                 .has_outbox = false,
1190                 .out_is_imm = false,
1191                 .encode_slave_id = false,
1192                 .verify = NULL,
1193                 .wrapper = mlx4_2RST_QP_wrapper
1194         },
1195         {
1196                 .opcode = MLX4_CMD_QUERY_QP,
1197                 .has_inbox = false,
1198                 .has_outbox = true,
1199                 .out_is_imm = false,
1200                 .encode_slave_id = false,
1201                 .verify = NULL,
1202                 .wrapper = mlx4_GEN_QP_wrapper
1203         },
1204         {
1205                 .opcode = MLX4_CMD_SUSPEND_QP,
1206                 .has_inbox = false,
1207                 .has_outbox = false,
1208                 .out_is_imm = false,
1209                 .encode_slave_id = false,
1210                 .verify = NULL,
1211                 .wrapper = mlx4_GEN_QP_wrapper
1212         },
1213         {
1214                 .opcode = MLX4_CMD_UNSUSPEND_QP,
1215                 .has_inbox = false,
1216                 .has_outbox = false,
1217                 .out_is_imm = false,
1218                 .encode_slave_id = false,
1219                 .verify = NULL,
1220                 .wrapper = mlx4_GEN_QP_wrapper
1221         },
1222         {
1223                 .opcode = MLX4_CMD_CONF_SPECIAL_QP,
1224                 .has_inbox = false,
1225                 .has_outbox = false,
1226                 .out_is_imm = false,
1227                 .encode_slave_id = false,
1228                 .verify = NULL, /* XXX verify: only demux can do this */
1229                 .wrapper = NULL
1230         },
1231         {
1232                 .opcode = MLX4_CMD_MAD_IFC,
1233                 .has_inbox = true,
1234                 .has_outbox = true,
1235                 .out_is_imm = false,
1236                 .encode_slave_id = false,
1237                 .verify = NULL,
1238                 .wrapper = mlx4_MAD_IFC_wrapper
1239         },
1240         {
1241                 .opcode = MLX4_CMD_QUERY_IF_STAT,
1242                 .has_inbox = false,
1243                 .has_outbox = true,
1244                 .out_is_imm = false,
1245                 .encode_slave_id = false,
1246                 .verify = NULL,
1247                 .wrapper = mlx4_QUERY_IF_STAT_wrapper
1248         },
1249         /* Native multicast commands are not available for guests */
1250         {
1251                 .opcode = MLX4_CMD_QP_ATTACH,
1252                 .has_inbox = true,
1253                 .has_outbox = false,
1254                 .out_is_imm = false,
1255                 .encode_slave_id = false,
1256                 .verify = NULL,
1257                 .wrapper = mlx4_QP_ATTACH_wrapper
1258         },
1259         {
1260                 .opcode = MLX4_CMD_PROMISC,
1261                 .has_inbox = false,
1262                 .has_outbox = false,
1263                 .out_is_imm = false,
1264                 .encode_slave_id = false,
1265                 .verify = NULL,
1266                 .wrapper = mlx4_PROMISC_wrapper
1267         },
1268         /* Ethernet specific commands */
1269         {
1270                 .opcode = MLX4_CMD_SET_VLAN_FLTR,
1271                 .has_inbox = true,
1272                 .has_outbox = false,
1273                 .out_is_imm = false,
1274                 .encode_slave_id = false,
1275                 .verify = NULL,
1276                 .wrapper = mlx4_SET_VLAN_FLTR_wrapper
1277         },
1278         {
1279                 .opcode = MLX4_CMD_SET_MCAST_FLTR,
1280                 .has_inbox = false,
1281                 .has_outbox = false,
1282                 .out_is_imm = false,
1283                 .encode_slave_id = false,
1284                 .verify = NULL,
1285                 .wrapper = mlx4_SET_MCAST_FLTR_wrapper
1286         },
1287         {
1288                 .opcode = MLX4_CMD_DUMP_ETH_STATS,
1289                 .has_inbox = false,
1290                 .has_outbox = true,
1291                 .out_is_imm = false,
1292                 .encode_slave_id = false,
1293                 .verify = NULL,
1294                 .wrapper = mlx4_DUMP_ETH_STATS_wrapper
1295         },
1296         {
1297                 .opcode = MLX4_CMD_INFORM_FLR_DONE,
1298                 .has_inbox = false,
1299                 .has_outbox = false,
1300                 .out_is_imm = false,
1301                 .encode_slave_id = false,
1302                 .verify = NULL,
1303                 .wrapper = NULL
1304         },
1305         /* flow steering commands */
1306         {
1307                 .opcode = MLX4_QP_FLOW_STEERING_ATTACH,
1308                 .has_inbox = true,
1309                 .has_outbox = false,
1310                 .out_is_imm = true,
1311                 .encode_slave_id = false,
1312                 .verify = NULL,
1313                 .wrapper = mlx4_QP_FLOW_STEERING_ATTACH_wrapper
1314         },
1315         {
1316                 .opcode = MLX4_QP_FLOW_STEERING_DETACH,
1317                 .has_inbox = false,
1318                 .has_outbox = false,
1319                 .out_is_imm = false,
1320                 .encode_slave_id = false,
1321                 .verify = NULL,
1322                 .wrapper = mlx4_QP_FLOW_STEERING_DETACH_wrapper
1323         },
1324 };
1325
1326 static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave,
1327                                     struct mlx4_vhcr_cmd *in_vhcr)
1328 {
1329         struct mlx4_priv *priv = mlx4_priv(dev);
1330         struct mlx4_cmd_info *cmd = NULL;
1331         struct mlx4_vhcr_cmd *vhcr_cmd = in_vhcr ? in_vhcr : priv->mfunc.vhcr;
1332         struct mlx4_vhcr *vhcr;
1333         struct mlx4_cmd_mailbox *inbox = NULL;
1334         struct mlx4_cmd_mailbox *outbox = NULL;
1335         u64 in_param;
1336         u64 out_param;
1337         int ret = 0;
1338         int i;
1339         int err = 0;
1340
1341         /* Create sw representation of Virtual HCR */
1342         vhcr = kzalloc(sizeof(struct mlx4_vhcr), GFP_KERNEL);
1343         if (!vhcr)
1344                 return -ENOMEM;
1345
1346         /* DMA in the vHCR */
1347         if (!in_vhcr) {
1348                 ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave,
1349                                       priv->mfunc.master.slave_state[slave].vhcr_dma,
1350                                       ALIGN(sizeof(struct mlx4_vhcr_cmd),
1351                                             MLX4_ACCESS_MEM_ALIGN), 1);
1352                 if (ret) {
1353                         mlx4_err(dev, "%s:Failed reading vhcr"
1354                                  "ret: 0x%x\n", __func__, ret);
1355                         kfree(vhcr);
1356                         return ret;
1357                 }
1358         }
1359
1360         /* Fill SW VHCR fields */
1361         vhcr->in_param = be64_to_cpu(vhcr_cmd->in_param);
1362         vhcr->out_param = be64_to_cpu(vhcr_cmd->out_param);
1363         vhcr->in_modifier = be32_to_cpu(vhcr_cmd->in_modifier);
1364         vhcr->token = be16_to_cpu(vhcr_cmd->token);
1365         vhcr->op = be16_to_cpu(vhcr_cmd->opcode) & 0xfff;
1366         vhcr->op_modifier = (u8) (be16_to_cpu(vhcr_cmd->opcode) >> 12);
1367         vhcr->e_bit = vhcr_cmd->flags & (1 << 6);
1368
1369         /* Lookup command */
1370         for (i = 0; i < ARRAY_SIZE(cmd_info); ++i) {
1371                 if (vhcr->op == cmd_info[i].opcode) {
1372                         cmd = &cmd_info[i];
1373                         break;
1374                 }
1375         }
1376         if (!cmd) {
1377                 mlx4_err(dev, "Unknown command:0x%x accepted from slave:%d\n",
1378                          vhcr->op, slave);
1379                 vhcr_cmd->status = CMD_STAT_BAD_PARAM;
1380                 goto out_status;
1381         }
1382
1383         /* Read inbox */
1384         if (cmd->has_inbox) {
1385                 vhcr->in_param &= INBOX_MASK;
1386                 inbox = mlx4_alloc_cmd_mailbox(dev);
1387                 if (IS_ERR(inbox)) {
1388                         vhcr_cmd->status = CMD_STAT_BAD_SIZE;
1389                         inbox = NULL;
1390                         goto out_status;
1391                 }
1392
1393                 if (mlx4_ACCESS_MEM(dev, inbox->dma, slave,
1394                                     vhcr->in_param,
1395                                     MLX4_MAILBOX_SIZE, 1)) {
1396                         mlx4_err(dev, "%s: Failed reading inbox (cmd:0x%x)\n",
1397                                  __func__, cmd->opcode);
1398                         vhcr_cmd->status = CMD_STAT_INTERNAL_ERR;
1399                         goto out_status;
1400                 }
1401         }
1402
1403         /* Apply permission and bound checks if applicable */
1404         if (cmd->verify && cmd->verify(dev, slave, vhcr, inbox)) {
1405                 mlx4_warn(dev, "Command:0x%x from slave: %d failed protection "
1406                           "checks for resource_id:%d\n", vhcr->op, slave,
1407                           vhcr->in_modifier);
1408                 vhcr_cmd->status = CMD_STAT_BAD_OP;
1409                 goto out_status;
1410         }
1411
1412         /* Allocate outbox */
1413         if (cmd->has_outbox) {
1414                 outbox = mlx4_alloc_cmd_mailbox(dev);
1415                 if (IS_ERR(outbox)) {
1416                         vhcr_cmd->status = CMD_STAT_BAD_SIZE;
1417                         outbox = NULL;
1418                         goto out_status;
1419                 }
1420         }
1421
1422         /* Execute the command! */
1423         if (cmd->wrapper) {
1424                 err = cmd->wrapper(dev, slave, vhcr, inbox, outbox,
1425                                    cmd);
1426                 if (cmd->out_is_imm)
1427                         vhcr_cmd->out_param = cpu_to_be64(vhcr->out_param);
1428         } else {
1429                 in_param = cmd->has_inbox ? (u64) inbox->dma :
1430                         vhcr->in_param;
1431                 out_param = cmd->has_outbox ? (u64) outbox->dma :
1432                         vhcr->out_param;
1433                 err = __mlx4_cmd(dev, in_param, &out_param,
1434                                  cmd->out_is_imm, vhcr->in_modifier,
1435                                  vhcr->op_modifier, vhcr->op,
1436                                  MLX4_CMD_TIME_CLASS_A,
1437                                  MLX4_CMD_NATIVE);
1438
1439                 if (cmd->out_is_imm) {
1440                         vhcr->out_param = out_param;
1441                         vhcr_cmd->out_param = cpu_to_be64(vhcr->out_param);
1442                 }
1443         }
1444
1445         if (err) {
1446                 mlx4_warn(dev, "vhcr command:0x%x slave:%d failed with"
1447                           " error:%d, status %d\n",
1448                           vhcr->op, slave, vhcr->errno, err);
1449                 vhcr_cmd->status = mlx4_errno_to_status(err);
1450                 goto out_status;
1451         }
1452
1453
1454         /* Write outbox if command completed successfully */
1455         if (cmd->has_outbox && !vhcr_cmd->status) {
1456                 ret = mlx4_ACCESS_MEM(dev, outbox->dma, slave,
1457                                       vhcr->out_param,
1458                                       MLX4_MAILBOX_SIZE, MLX4_CMD_WRAPPED);
1459                 if (ret) {
1460                         /* If we failed to write back the outbox after the
1461                          *command was successfully executed, we must fail this
1462                          * slave, as it is now in undefined state */
1463                         mlx4_err(dev, "%s:Failed writing outbox\n", __func__);
1464                         goto out;
1465                 }
1466         }
1467
1468 out_status:
1469         /* DMA back vhcr result */
1470         if (!in_vhcr) {
1471                 ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave,
1472                                       priv->mfunc.master.slave_state[slave].vhcr_dma,
1473                                       ALIGN(sizeof(struct mlx4_vhcr),
1474                                             MLX4_ACCESS_MEM_ALIGN),
1475                                       MLX4_CMD_WRAPPED);
1476                 if (ret)
1477                         mlx4_err(dev, "%s:Failed writing vhcr result\n",
1478                                  __func__);
1479                 else if (vhcr->e_bit &&
1480                          mlx4_GEN_EQE(dev, slave, &priv->mfunc.master.cmd_eqe))
1481                                 mlx4_warn(dev, "Failed to generate command completion "
1482                                           "eqe for slave %d\n", slave);
1483         }
1484
1485 out:
1486         kfree(vhcr);
1487         mlx4_free_cmd_mailbox(dev, inbox);
1488         mlx4_free_cmd_mailbox(dev, outbox);
1489         return ret;
1490 }
1491
1492 static int mlx4_master_activate_admin_state(struct mlx4_priv *priv, int slave)
1493 {
1494         int port, err;
1495         struct mlx4_vport_state *vp_admin;
1496         struct mlx4_vport_oper_state *vp_oper;
1497
1498         for (port = 1; port <= MLX4_MAX_PORTS; port++) {
1499                 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
1500                 vp_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
1501                 vp_oper->state = *vp_admin;
1502                 if (MLX4_VGT != vp_admin->default_vlan) {
1503                         err = __mlx4_register_vlan(&priv->dev, port,
1504                                                    vp_admin->default_vlan, &(vp_oper->vlan_idx));
1505                         if (err) {
1506                                 vp_oper->vlan_idx = NO_INDX;
1507                                 mlx4_warn((&priv->dev),
1508                                           "No vlan resorces slave %d, port %d\n",
1509                                           slave, port);
1510                                 return err;
1511                         }
1512                         mlx4_dbg((&(priv->dev)), "alloc vlan %d idx  %d slave %d port %d\n",
1513                                  (int)(vp_oper->state.default_vlan),
1514                                  vp_oper->vlan_idx, slave, port);
1515                 }
1516                 if (vp_admin->spoofchk) {
1517                         vp_oper->mac_idx = __mlx4_register_mac(&priv->dev,
1518                                                                port,
1519                                                                vp_admin->mac);
1520                         if (0 > vp_oper->mac_idx) {
1521                                 err = vp_oper->mac_idx;
1522                                 vp_oper->mac_idx = NO_INDX;
1523                                 mlx4_warn((&priv->dev),
1524                                           "No mac resorces slave %d, port %d\n",
1525                                           slave, port);
1526                                 return err;
1527                         }
1528                         mlx4_dbg((&(priv->dev)), "alloc mac %llx idx  %d slave %d port %d\n",
1529                                  vp_oper->state.mac, vp_oper->mac_idx, slave, port);
1530                 }
1531         }
1532         return 0;
1533 }
1534
1535 static void mlx4_master_deactivate_admin_state(struct mlx4_priv *priv, int slave)
1536 {
1537         int port;
1538         struct mlx4_vport_oper_state *vp_oper;
1539
1540         for (port = 1; port <= MLX4_MAX_PORTS; port++) {
1541                 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
1542                 if (NO_INDX != vp_oper->vlan_idx) {
1543                         __mlx4_unregister_vlan(&priv->dev,
1544                                                port, vp_oper->vlan_idx);
1545                         vp_oper->vlan_idx = NO_INDX;
1546                 }
1547                 if (NO_INDX != vp_oper->mac_idx) {
1548                         __mlx4_unregister_mac(&priv->dev, port, vp_oper->mac_idx);
1549                         vp_oper->mac_idx = NO_INDX;
1550                 }
1551         }
1552         return;
1553 }
1554
1555 static void mlx4_master_do_cmd(struct mlx4_dev *dev, int slave, u8 cmd,
1556                                u16 param, u8 toggle)
1557 {
1558         struct mlx4_priv *priv = mlx4_priv(dev);
1559         struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
1560         u32 reply;
1561         u8 is_going_down = 0;
1562         int i;
1563         unsigned long flags;
1564
1565         slave_state[slave].comm_toggle ^= 1;
1566         reply = (u32) slave_state[slave].comm_toggle << 31;
1567         if (toggle != slave_state[slave].comm_toggle) {
1568                 mlx4_warn(dev, "Incorrect toggle %d from slave %d. *** MASTER"
1569                           "STATE COMPROMISIED ***\n", toggle, slave);
1570                 goto reset_slave;
1571         }
1572         if (cmd == MLX4_COMM_CMD_RESET) {
1573                 mlx4_warn(dev, "Received reset from slave:%d\n", slave);
1574                 slave_state[slave].active = false;
1575                 mlx4_master_deactivate_admin_state(priv, slave);
1576                 for (i = 0; i < MLX4_EVENT_TYPES_NUM; ++i) {
1577                                 slave_state[slave].event_eq[i].eqn = -1;
1578                                 slave_state[slave].event_eq[i].token = 0;
1579                 }
1580                 /*check if we are in the middle of FLR process,
1581                 if so return "retry" status to the slave*/
1582                 if (MLX4_COMM_CMD_FLR == slave_state[slave].last_cmd)
1583                         goto inform_slave_state;
1584
1585                 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_SLAVE_SHUTDOWN, slave);
1586
1587                 /* write the version in the event field */
1588                 reply |= mlx4_comm_get_version();
1589
1590                 goto reset_slave;
1591         }
1592         /*command from slave in the middle of FLR*/
1593         if (cmd != MLX4_COMM_CMD_RESET &&
1594             MLX4_COMM_CMD_FLR == slave_state[slave].last_cmd) {
1595                 mlx4_warn(dev, "slave:%d is Trying to run cmd(0x%x) "
1596                           "in the middle of FLR\n", slave, cmd);
1597                 return;
1598         }
1599
1600         switch (cmd) {
1601         case MLX4_COMM_CMD_VHCR0:
1602                 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_RESET)
1603                         goto reset_slave;
1604                 slave_state[slave].vhcr_dma = ((u64) param) << 48;
1605                 priv->mfunc.master.slave_state[slave].cookie = 0;
1606                 mutex_init(&priv->mfunc.master.gen_eqe_mutex[slave]);
1607                 break;
1608         case MLX4_COMM_CMD_VHCR1:
1609                 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR0)
1610                         goto reset_slave;
1611                 slave_state[slave].vhcr_dma |= ((u64) param) << 32;
1612                 break;
1613         case MLX4_COMM_CMD_VHCR2:
1614                 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR1)
1615                         goto reset_slave;
1616                 slave_state[slave].vhcr_dma |= ((u64) param) << 16;
1617                 break;
1618         case MLX4_COMM_CMD_VHCR_EN:
1619                 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR2)
1620                         goto reset_slave;
1621                 slave_state[slave].vhcr_dma |= param;
1622                 if (mlx4_master_activate_admin_state(priv, slave))
1623                                 goto reset_slave;
1624                 slave_state[slave].active = true;
1625                 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_SLAVE_INIT, slave);
1626                 break;
1627         case MLX4_COMM_CMD_VHCR_POST:
1628                 if ((slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR_EN) &&
1629                     (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR_POST))
1630                         goto reset_slave;
1631
1632                 mutex_lock(&priv->cmd.slave_cmd_mutex);
1633                 if (mlx4_master_process_vhcr(dev, slave, NULL)) {
1634                         mlx4_err(dev, "Failed processing vhcr for slave:%d,"
1635                                  " resetting slave.\n", slave);
1636                         mutex_unlock(&priv->cmd.slave_cmd_mutex);
1637                         goto reset_slave;
1638                 }
1639                 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1640                 break;
1641         default:
1642                 mlx4_warn(dev, "Bad comm cmd:%d from slave:%d\n", cmd, slave);
1643                 goto reset_slave;
1644         }
1645         spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
1646         if (!slave_state[slave].is_slave_going_down)
1647                 slave_state[slave].last_cmd = cmd;
1648         else
1649                 is_going_down = 1;
1650         spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
1651         if (is_going_down) {
1652                 mlx4_warn(dev, "Slave is going down aborting command(%d)"
1653                           " executing from slave:%d\n",
1654                           cmd, slave);
1655                 return;
1656         }
1657         __raw_writel((__force u32) cpu_to_be32(reply),
1658                      &priv->mfunc.comm[slave].slave_read);
1659         mmiowb();
1660
1661         return;
1662
1663 reset_slave:
1664         /* cleanup any slave resources */
1665         mlx4_delete_all_resources_for_slave(dev, slave);
1666         spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
1667         if (!slave_state[slave].is_slave_going_down)
1668                 slave_state[slave].last_cmd = MLX4_COMM_CMD_RESET;
1669         spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
1670         /*with slave in the middle of flr, no need to clean resources again.*/
1671 inform_slave_state:
1672         memset(&slave_state[slave].event_eq, 0,
1673                sizeof(struct mlx4_slave_event_eq_info));
1674         __raw_writel((__force u32) cpu_to_be32(reply),
1675                      &priv->mfunc.comm[slave].slave_read);
1676         wmb();
1677 }
1678
1679 /* master command processing */
1680 void mlx4_master_comm_channel(struct work_struct *work)
1681 {
1682         struct mlx4_mfunc_master_ctx *master =
1683                 container_of(work,
1684                              struct mlx4_mfunc_master_ctx,
1685                              comm_work);
1686         struct mlx4_mfunc *mfunc =
1687                 container_of(master, struct mlx4_mfunc, master);
1688         struct mlx4_priv *priv =
1689                 container_of(mfunc, struct mlx4_priv, mfunc);
1690         struct mlx4_dev *dev = &priv->dev;
1691         __be32 *bit_vec;
1692         u32 comm_cmd;
1693         u32 vec;
1694         int i, j, slave;
1695         int toggle;
1696         int served = 0;
1697         int reported = 0;
1698         u32 slt;
1699
1700         bit_vec = master->comm_arm_bit_vector;
1701         for (i = 0; i < COMM_CHANNEL_BIT_ARRAY_SIZE; i++) {
1702                 vec = be32_to_cpu(bit_vec[i]);
1703                 for (j = 0; j < 32; j++) {
1704                         if (!(vec & (1 << j)))
1705                                 continue;
1706                         ++reported;
1707                         slave = (i * 32) + j;
1708                         comm_cmd = swab32(readl(
1709                                           &mfunc->comm[slave].slave_write));
1710                         slt = swab32(readl(&mfunc->comm[slave].slave_read))
1711                                      >> 31;
1712                         toggle = comm_cmd >> 31;
1713                         if (toggle != slt) {
1714                                 if (master->slave_state[slave].comm_toggle
1715                                     != slt) {
1716                                         printk(KERN_INFO "slave %d out of sync."
1717                                                " read toggle %d, state toggle %d. "
1718                                                "Resynching.\n", slave, slt,
1719                                                master->slave_state[slave].comm_toggle);
1720                                         master->slave_state[slave].comm_toggle =
1721                                                 slt;
1722                                 }
1723                                 mlx4_master_do_cmd(dev, slave,
1724                                                    comm_cmd >> 16 & 0xff,
1725                                                    comm_cmd & 0xffff, toggle);
1726                                 ++served;
1727                         }
1728                 }
1729         }
1730
1731         if (reported && reported != served)
1732                 mlx4_warn(dev, "Got command event with bitmask from %d slaves"
1733                           " but %d were served\n",
1734                           reported, served);
1735
1736         if (mlx4_ARM_COMM_CHANNEL(dev))
1737                 mlx4_warn(dev, "Failed to arm comm channel events\n");
1738 }
1739
1740 static int sync_toggles(struct mlx4_dev *dev)
1741 {
1742         struct mlx4_priv *priv = mlx4_priv(dev);
1743         int wr_toggle;
1744         int rd_toggle;
1745         unsigned long end;
1746
1747         wr_toggle = swab32(readl(&priv->mfunc.comm->slave_write)) >> 31;
1748         end = jiffies + msecs_to_jiffies(5000);
1749
1750         while (time_before(jiffies, end)) {
1751                 rd_toggle = swab32(readl(&priv->mfunc.comm->slave_read)) >> 31;
1752                 if (rd_toggle == wr_toggle) {
1753                         priv->cmd.comm_toggle = rd_toggle;
1754                         return 0;
1755                 }
1756
1757                 cond_resched();
1758         }
1759
1760         /*
1761          * we could reach here if for example the previous VM using this
1762          * function misbehaved and left the channel with unsynced state. We
1763          * should fix this here and give this VM a chance to use a properly
1764          * synced channel
1765          */
1766         mlx4_warn(dev, "recovering from previously mis-behaved VM\n");
1767         __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_read);
1768         __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_write);
1769         priv->cmd.comm_toggle = 0;
1770
1771         return 0;
1772 }
1773
1774 int mlx4_multi_func_init(struct mlx4_dev *dev)
1775 {
1776         struct mlx4_priv *priv = mlx4_priv(dev);
1777         struct mlx4_slave_state *s_state;
1778         int i, j, err, port;
1779
1780         if (mlx4_is_master(dev))
1781                 priv->mfunc.comm =
1782                 ioremap(pci_resource_start(dev->pdev, priv->fw.comm_bar) +
1783                         priv->fw.comm_base, MLX4_COMM_PAGESIZE);
1784         else
1785                 priv->mfunc.comm =
1786                 ioremap(pci_resource_start(dev->pdev, 2) +
1787                         MLX4_SLAVE_COMM_BASE, MLX4_COMM_PAGESIZE);
1788         if (!priv->mfunc.comm) {
1789                 mlx4_err(dev, "Couldn't map communication vector.\n");
1790                 goto err_vhcr;
1791         }
1792
1793         if (mlx4_is_master(dev)) {
1794                 priv->mfunc.master.slave_state =
1795                         kzalloc(dev->num_slaves *
1796                                 sizeof(struct mlx4_slave_state), GFP_KERNEL);
1797                 if (!priv->mfunc.master.slave_state)
1798                         goto err_comm;
1799
1800                 priv->mfunc.master.vf_admin =
1801                         kzalloc(dev->num_slaves *
1802                                 sizeof(struct mlx4_vf_admin_state), GFP_KERNEL);
1803                 if (!priv->mfunc.master.vf_admin)
1804                         goto err_comm_admin;
1805
1806                 priv->mfunc.master.vf_oper =
1807                         kzalloc(dev->num_slaves *
1808                                 sizeof(struct mlx4_vf_oper_state), GFP_KERNEL);
1809                 if (!priv->mfunc.master.vf_oper)
1810                         goto err_comm_oper;
1811
1812                 for (i = 0; i < dev->num_slaves; ++i) {
1813                         s_state = &priv->mfunc.master.slave_state[i];
1814                         s_state->last_cmd = MLX4_COMM_CMD_RESET;
1815                         for (j = 0; j < MLX4_EVENT_TYPES_NUM; ++j)
1816                                 s_state->event_eq[j].eqn = -1;
1817                         __raw_writel((__force u32) 0,
1818                                      &priv->mfunc.comm[i].slave_write);
1819                         __raw_writel((__force u32) 0,
1820                                      &priv->mfunc.comm[i].slave_read);
1821                         mmiowb();
1822                         for (port = 1; port <= MLX4_MAX_PORTS; port++) {
1823                                 s_state->vlan_filter[port] =
1824                                         kzalloc(sizeof(struct mlx4_vlan_fltr),
1825                                                 GFP_KERNEL);
1826                                 if (!s_state->vlan_filter[port]) {
1827                                         if (--port)
1828                                                 kfree(s_state->vlan_filter[port]);
1829                                         goto err_slaves;
1830                                 }
1831                                 INIT_LIST_HEAD(&s_state->mcast_filters[port]);
1832                                 priv->mfunc.master.vf_admin[i].vport[port].default_vlan = MLX4_VGT;
1833                                 priv->mfunc.master.vf_oper[i].vport[port].state.default_vlan = MLX4_VGT;
1834                                 priv->mfunc.master.vf_oper[i].vport[port].vlan_idx = NO_INDX;
1835                                 priv->mfunc.master.vf_oper[i].vport[port].mac_idx = NO_INDX;
1836                         }
1837                         spin_lock_init(&s_state->lock);
1838                 }
1839
1840                 memset(&priv->mfunc.master.cmd_eqe, 0, dev->caps.eqe_size);
1841                 priv->mfunc.master.cmd_eqe.type = MLX4_EVENT_TYPE_CMD;
1842                 INIT_WORK(&priv->mfunc.master.comm_work,
1843                           mlx4_master_comm_channel);
1844                 INIT_WORK(&priv->mfunc.master.slave_event_work,
1845                           mlx4_gen_slave_eqe);
1846                 INIT_WORK(&priv->mfunc.master.slave_flr_event_work,
1847                           mlx4_master_handle_slave_flr);
1848                 spin_lock_init(&priv->mfunc.master.slave_state_lock);
1849                 spin_lock_init(&priv->mfunc.master.slave_eq.event_lock);
1850                 priv->mfunc.master.comm_wq =
1851                         create_singlethread_workqueue("mlx4_comm");
1852                 if (!priv->mfunc.master.comm_wq)
1853                         goto err_slaves;
1854
1855                 if (mlx4_init_resource_tracker(dev))
1856                         goto err_thread;
1857
1858                 err = mlx4_ARM_COMM_CHANNEL(dev);
1859                 if (err) {
1860                         mlx4_err(dev, " Failed to arm comm channel eq: %x\n",
1861                                  err);
1862                         goto err_resource;
1863                 }
1864
1865         } else {
1866                 err = sync_toggles(dev);
1867                 if (err) {
1868                         mlx4_err(dev, "Couldn't sync toggles\n");
1869                         goto err_comm;
1870                 }
1871         }
1872         return 0;
1873
1874 err_resource:
1875         mlx4_free_resource_tracker(dev, RES_TR_FREE_ALL);
1876 err_thread:
1877         flush_workqueue(priv->mfunc.master.comm_wq);
1878         destroy_workqueue(priv->mfunc.master.comm_wq);
1879 err_slaves:
1880         while (--i) {
1881                 for (port = 1; port <= MLX4_MAX_PORTS; port++)
1882                         kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]);
1883         }
1884         kfree(priv->mfunc.master.vf_oper);
1885 err_comm_oper:
1886         kfree(priv->mfunc.master.vf_admin);
1887 err_comm_admin:
1888         kfree(priv->mfunc.master.slave_state);
1889 err_comm:
1890         iounmap(priv->mfunc.comm);
1891 err_vhcr:
1892         dma_free_coherent(&(dev->pdev->dev), PAGE_SIZE,
1893                                              priv->mfunc.vhcr,
1894                                              priv->mfunc.vhcr_dma);
1895         priv->mfunc.vhcr = NULL;
1896         return -ENOMEM;
1897 }
1898
1899 int mlx4_cmd_init(struct mlx4_dev *dev)
1900 {
1901         struct mlx4_priv *priv = mlx4_priv(dev);
1902
1903         mutex_init(&priv->cmd.hcr_mutex);
1904         mutex_init(&priv->cmd.slave_cmd_mutex);
1905         sema_init(&priv->cmd.poll_sem, 1);
1906         priv->cmd.use_events = 0;
1907         priv->cmd.toggle     = 1;
1908
1909         priv->cmd.hcr = NULL;
1910         priv->mfunc.vhcr = NULL;
1911
1912         if (!mlx4_is_slave(dev)) {
1913                 priv->cmd.hcr = ioremap(pci_resource_start(dev->pdev, 0) +
1914                                         MLX4_HCR_BASE, MLX4_HCR_SIZE);
1915                 if (!priv->cmd.hcr) {
1916                         mlx4_err(dev, "Couldn't map command register.\n");
1917                         return -ENOMEM;
1918                 }
1919         }
1920
1921         if (mlx4_is_mfunc(dev)) {
1922                 priv->mfunc.vhcr = dma_alloc_coherent(&(dev->pdev->dev), PAGE_SIZE,
1923                                                       &priv->mfunc.vhcr_dma,
1924                                                       GFP_KERNEL);
1925                 if (!priv->mfunc.vhcr)
1926                         goto err_hcr;
1927         }
1928
1929         priv->cmd.pool = pci_pool_create("mlx4_cmd", dev->pdev,
1930                                          MLX4_MAILBOX_SIZE,
1931                                          MLX4_MAILBOX_SIZE, 0);
1932         if (!priv->cmd.pool)
1933                 goto err_vhcr;
1934
1935         return 0;
1936
1937 err_vhcr:
1938         if (mlx4_is_mfunc(dev))
1939                 dma_free_coherent(&(dev->pdev->dev), PAGE_SIZE,
1940                                   priv->mfunc.vhcr, priv->mfunc.vhcr_dma);
1941         priv->mfunc.vhcr = NULL;
1942
1943 err_hcr:
1944         if (!mlx4_is_slave(dev))
1945                 iounmap(priv->cmd.hcr);
1946         return -ENOMEM;
1947 }
1948
1949 void mlx4_multi_func_cleanup(struct mlx4_dev *dev)
1950 {
1951         struct mlx4_priv *priv = mlx4_priv(dev);
1952         int i, port;
1953
1954         if (mlx4_is_master(dev)) {
1955                 flush_workqueue(priv->mfunc.master.comm_wq);
1956                 destroy_workqueue(priv->mfunc.master.comm_wq);
1957                 for (i = 0; i < dev->num_slaves; i++) {
1958                         for (port = 1; port <= MLX4_MAX_PORTS; port++)
1959                                 kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]);
1960                 }
1961                 kfree(priv->mfunc.master.slave_state);
1962                 kfree(priv->mfunc.master.vf_admin);
1963                 kfree(priv->mfunc.master.vf_oper);
1964         }
1965
1966         iounmap(priv->mfunc.comm);
1967 }
1968
1969 void mlx4_cmd_cleanup(struct mlx4_dev *dev)
1970 {
1971         struct mlx4_priv *priv = mlx4_priv(dev);
1972
1973         pci_pool_destroy(priv->cmd.pool);
1974
1975         if (!mlx4_is_slave(dev))
1976                 iounmap(priv->cmd.hcr);
1977         if (mlx4_is_mfunc(dev))
1978                 dma_free_coherent(&(dev->pdev->dev), PAGE_SIZE,
1979                                   priv->mfunc.vhcr, priv->mfunc.vhcr_dma);
1980         priv->mfunc.vhcr = NULL;
1981 }
1982
1983 /*
1984  * Switch to using events to issue FW commands (can only be called
1985  * after event queue for command events has been initialized).
1986  */
1987 int mlx4_cmd_use_events(struct mlx4_dev *dev)
1988 {
1989         struct mlx4_priv *priv = mlx4_priv(dev);
1990         int i;
1991         int err = 0;
1992
1993         priv->cmd.context = kmalloc(priv->cmd.max_cmds *
1994                                    sizeof (struct mlx4_cmd_context),
1995                                    GFP_KERNEL);
1996         if (!priv->cmd.context)
1997                 return -ENOMEM;
1998
1999         for (i = 0; i < priv->cmd.max_cmds; ++i) {
2000                 priv->cmd.context[i].token = i;
2001                 priv->cmd.context[i].next  = i + 1;
2002         }
2003
2004         priv->cmd.context[priv->cmd.max_cmds - 1].next = -1;
2005         priv->cmd.free_head = 0;
2006
2007         sema_init(&priv->cmd.event_sem, priv->cmd.max_cmds);
2008         spin_lock_init(&priv->cmd.context_lock);
2009
2010         for (priv->cmd.token_mask = 1;
2011              priv->cmd.token_mask < priv->cmd.max_cmds;
2012              priv->cmd.token_mask <<= 1)
2013                 ; /* nothing */
2014         --priv->cmd.token_mask;
2015
2016         down(&priv->cmd.poll_sem);
2017         priv->cmd.use_events = 1;
2018
2019         return err;
2020 }
2021
2022 /*
2023  * Switch back to polling (used when shutting down the device)
2024  */
2025 void mlx4_cmd_use_polling(struct mlx4_dev *dev)
2026 {
2027         struct mlx4_priv *priv = mlx4_priv(dev);
2028         int i;
2029
2030         priv->cmd.use_events = 0;
2031
2032         for (i = 0; i < priv->cmd.max_cmds; ++i)
2033                 down(&priv->cmd.event_sem);
2034
2035         kfree(priv->cmd.context);
2036
2037         up(&priv->cmd.poll_sem);
2038 }
2039
2040 struct mlx4_cmd_mailbox *mlx4_alloc_cmd_mailbox(struct mlx4_dev *dev)
2041 {
2042         struct mlx4_cmd_mailbox *mailbox;
2043
2044         mailbox = kmalloc(sizeof *mailbox, GFP_KERNEL);
2045         if (!mailbox)
2046                 return ERR_PTR(-ENOMEM);
2047
2048         mailbox->buf = pci_pool_alloc(mlx4_priv(dev)->cmd.pool, GFP_KERNEL,
2049                                       &mailbox->dma);
2050         if (!mailbox->buf) {
2051                 kfree(mailbox);
2052                 return ERR_PTR(-ENOMEM);
2053         }
2054
2055         return mailbox;
2056 }
2057 EXPORT_SYMBOL_GPL(mlx4_alloc_cmd_mailbox);
2058
2059 void mlx4_free_cmd_mailbox(struct mlx4_dev *dev,
2060                            struct mlx4_cmd_mailbox *mailbox)
2061 {
2062         if (!mailbox)
2063                 return;
2064
2065         pci_pool_free(mlx4_priv(dev)->cmd.pool, mailbox->buf, mailbox->dma);
2066         kfree(mailbox);
2067 }
2068 EXPORT_SYMBOL_GPL(mlx4_free_cmd_mailbox);
2069
2070 u32 mlx4_comm_get_version(void)
2071 {
2072          return ((u32) CMD_CHAN_IF_REV << 8) | (u32) CMD_CHAN_VER;
2073 }
2074
2075 static int mlx4_get_slave_indx(struct mlx4_dev *dev, int vf)
2076 {
2077         if ((vf < 0) || (vf >= dev->num_vfs)) {
2078                 mlx4_err(dev, "Bad vf number:%d (number of activated vf: %d)\n", vf, dev->num_vfs);
2079                 return -EINVAL;
2080         }
2081
2082         return vf+1;
2083 }
2084
2085 int mlx4_set_vf_mac(struct mlx4_dev *dev, int port, int vf, u64 mac)
2086 {
2087         struct mlx4_priv *priv = mlx4_priv(dev);
2088         struct mlx4_vport_state *s_info;
2089         int slave;
2090
2091         if (!mlx4_is_master(dev))
2092                 return -EPROTONOSUPPORT;
2093
2094         slave = mlx4_get_slave_indx(dev, vf);
2095         if (slave < 0)
2096                 return -EINVAL;
2097
2098         s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
2099         s_info->mac = mac;
2100         mlx4_info(dev, "default mac on vf %d port %d to %llX will take afect only after vf restart\n",
2101                   vf, port, s_info->mac);
2102         return 0;
2103 }
2104 EXPORT_SYMBOL_GPL(mlx4_set_vf_mac);
2105
2106 int mlx4_set_vf_vlan(struct mlx4_dev *dev, int port, int vf, u16 vlan, u8 qos)
2107 {
2108         struct mlx4_priv *priv = mlx4_priv(dev);
2109         struct mlx4_vport_state *s_info;
2110         int slave;
2111
2112         if ((!mlx4_is_master(dev)) ||
2113             !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_VLAN_CONTROL))
2114                 return -EPROTONOSUPPORT;
2115
2116         if ((vlan > 4095) || (qos > 7))
2117                 return -EINVAL;
2118
2119         slave = mlx4_get_slave_indx(dev, vf);
2120         if (slave < 0)
2121                 return -EINVAL;
2122
2123         s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
2124         if ((0 == vlan) && (0 == qos))
2125                 s_info->default_vlan = MLX4_VGT;
2126         else
2127                 s_info->default_vlan = vlan;
2128         s_info->default_qos = qos;
2129         return 0;
2130 }
2131 EXPORT_SYMBOL_GPL(mlx4_set_vf_vlan);
2132
2133 int mlx4_set_vf_spoofchk(struct mlx4_dev *dev, int port, int vf, bool setting)
2134 {
2135         struct mlx4_priv *priv = mlx4_priv(dev);
2136         struct mlx4_vport_state *s_info;
2137         int slave;
2138
2139         if ((!mlx4_is_master(dev)) ||
2140             !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FSM))
2141                 return -EPROTONOSUPPORT;
2142
2143         slave = mlx4_get_slave_indx(dev, vf);
2144         if (slave < 0)
2145                 return -EINVAL;
2146
2147         s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
2148         s_info->spoofchk = setting;
2149
2150         return 0;
2151 }
2152 EXPORT_SYMBOL_GPL(mlx4_set_vf_spoofchk);
2153
2154 int mlx4_get_vf_config(struct mlx4_dev *dev, int port, int vf, struct ifla_vf_info *ivf)
2155 {
2156         struct mlx4_priv *priv = mlx4_priv(dev);
2157         struct mlx4_vport_state *s_info;
2158         int slave;
2159
2160         if (!mlx4_is_master(dev))
2161                 return -EPROTONOSUPPORT;
2162
2163         slave = mlx4_get_slave_indx(dev, vf);
2164         if (slave < 0)
2165                 return -EINVAL;
2166
2167         s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
2168         ivf->vf = vf;
2169
2170         /* need to convert it to a func */
2171         ivf->mac[0] = ((s_info->mac >> (5*8)) & 0xff);
2172         ivf->mac[1] = ((s_info->mac >> (4*8)) & 0xff);
2173         ivf->mac[2] = ((s_info->mac >> (3*8)) & 0xff);
2174         ivf->mac[3] = ((s_info->mac >> (2*8)) & 0xff);
2175         ivf->mac[4] = ((s_info->mac >> (1*8)) & 0xff);
2176         ivf->mac[5] = ((s_info->mac)  & 0xff);
2177
2178         ivf->vlan       = s_info->default_vlan;
2179         ivf->qos        = s_info->default_qos;
2180         ivf->tx_rate    = s_info->tx_rate;
2181         ivf->spoofchk   = s_info->spoofchk;
2182         ivf->linkstate  = s_info->link_state;
2183
2184         return 0;
2185 }
2186 EXPORT_SYMBOL_GPL(mlx4_get_vf_config);
2187
2188 int mlx4_set_vf_link_state(struct mlx4_dev *dev, int port, int vf, int link_state)
2189 {
2190         struct mlx4_priv *priv = mlx4_priv(dev);
2191         struct mlx4_vport_state *s_info;
2192         struct mlx4_vport_oper_state *vp_oper;
2193         int slave;
2194         u8 link_stat_event;
2195
2196         slave = mlx4_get_slave_indx(dev, vf);
2197         if (slave < 0)
2198                 return -EINVAL;
2199
2200         switch (link_state) {
2201         case IFLA_VF_LINK_STATE_AUTO:
2202                 /* get current link state */
2203                 if (!priv->sense.do_sense_port[port])
2204                         link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_ACTIVE;
2205                 else
2206                         link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_DOWN;
2207             break;
2208
2209         case IFLA_VF_LINK_STATE_ENABLE:
2210                 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_ACTIVE;
2211             break;
2212
2213         case IFLA_VF_LINK_STATE_DISABLE:
2214                 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_DOWN;
2215             break;
2216
2217         default:
2218                 mlx4_warn(dev, "unknown value for link_state %02x on slave %d port %d\n",
2219                           link_state, slave, port);
2220                 return -EINVAL;
2221         };
2222         /* update the admin & oper state on the link state */
2223         s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
2224         vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
2225         s_info->link_state = link_state;
2226         vp_oper->state.link_state = link_state;
2227
2228         /* send event */
2229         mlx4_gen_port_state_change_eqe(dev, slave, port, link_stat_event);
2230         return 0;
2231 }
2232 EXPORT_SYMBOL_GPL(mlx4_set_vf_link_state);