drivers/net/ethernet/mellanox/mlx5/core/cmd.c

   1 /*
   2  * Copyright (c) 2013-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/highmem.h>
  34 #include <linux/module.h>
  35 #include <linux/errno.h>
  36 #include <linux/pci.h>
  37 #include <linux/dma-mapping.h>
  38 #include <linux/slab.h>
  39 #include <linux/delay.h>
  40 #include <linux/random.h>
  41 #include <linux/io-mapping.h>
  42 #include <linux/mlx5/driver.h>
  43 #include <linux/debugfs.h>
  44
  45 #include "mlx5_core.h"
  46
  47 enum {
  48         CMD_IF_REV = 5,
  49 };
  50
  51 enum {
  52         CMD_MODE_POLLING,
  53         CMD_MODE_EVENTS
  54 };
  55
  56 enum {
  57         NUM_LONG_LISTS    = 2,
  58         NUM_MED_LISTS     = 64,
  59         LONG_LIST_SIZE    = (2ULL * 1024 * 1024 * 1024 / PAGE_SIZE) * 8 + 16 +
  60                                 MLX5_CMD_DATA_BLOCK_SIZE,
  61         MED_LIST_SIZE     = 16 + MLX5_CMD_DATA_BLOCK_SIZE,
  62 };
  63
  64 enum {
  65         MLX5_CMD_DELIVERY_STAT_OK                       = 0x0,
  66         MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR               = 0x1,
  67         MLX5_CMD_DELIVERY_STAT_TOK_ERR                  = 0x2,
  68         MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR          = 0x3,
  69         MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR        = 0x4,
  70         MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR         = 0x5,
  71         MLX5_CMD_DELIVERY_STAT_FW_ERR                   = 0x6,
  72         MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR            = 0x7,
  73         MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR           = 0x8,
  74         MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR      = 0x9,
  75         MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR            = 0x10,
  76 };
  77
  78 static struct mlx5_cmd_work_ent *alloc_cmd(struct mlx5_cmd *cmd,
  79                                            struct mlx5_cmd_msg *in,
  80                                            struct mlx5_cmd_msg *out,
  81                                            void *uout, int uout_size,
  82                                            mlx5_cmd_cbk_t cbk,
  83                                            void *context, int page_queue)
  84 {
  85         gfp_t alloc_flags = cbk ? GFP_ATOMIC : GFP_KERNEL;
  86         struct mlx5_cmd_work_ent *ent;
  87
  88         ent = kzalloc(sizeof(*ent), alloc_flags);
  89         if (!ent)
  90                 return ERR_PTR(-ENOMEM);
  91
  92         ent->in         = in;
  93         ent->out        = out;
  94         ent->uout       = uout;
  95         ent->uout_size  = uout_size;
  96         ent->callback   = cbk;
  97         ent->context    = context;
  98         ent->cmd        = cmd;
  99         ent->page_queue = page_queue;
 100
 101         return ent;
 102 }
 103
 104 static u8 alloc_token(struct mlx5_cmd *cmd)
 105 {
 106         u8 token;
 107
 108         spin_lock(&cmd->token_lock);
 109         cmd->token++;
 110         if (cmd->token == 0)
 111                 cmd->token++;
 112         token = cmd->token;
 113         spin_unlock(&cmd->token_lock);
 114
 115         return token;
 116 }
 117
 118 static int alloc_ent(struct mlx5_cmd *cmd)
 119 {
 120         unsigned long flags;
 121         int ret;
 122
 123         spin_lock_irqsave(&cmd->alloc_lock, flags);
 124         ret = find_first_bit(&cmd->bitmask, cmd->max_reg_cmds);
 125         if (ret < cmd->max_reg_cmds)
 126                 clear_bit(ret, &cmd->bitmask);
 127         spin_unlock_irqrestore(&cmd->alloc_lock, flags);
 128
 129         return ret < cmd->max_reg_cmds ? ret : -ENOMEM;
 130 }
 131
 132 static void free_ent(struct mlx5_cmd *cmd, int idx)
 133 {
 134         unsigned long flags;
 135
 136         spin_lock_irqsave(&cmd->alloc_lock, flags);
 137         set_bit(idx, &cmd->bitmask);
 138         spin_unlock_irqrestore(&cmd->alloc_lock, flags);
 139 }
 140
 141 static struct mlx5_cmd_layout *get_inst(struct mlx5_cmd *cmd, int idx)
 142 {
 143         return cmd->cmd_buf + (idx << cmd->log_stride);
 144 }
 145
 146 static u8 xor8_buf(void *buf, int len)
 147 {
 148         u8 *ptr = buf;
 149         u8 sum = 0;
 150         int i;
 151
 152         for (i = 0; i < len; i++)
 153                 sum ^= ptr[i];
 154
 155         return sum;
 156 }
 157
 158 static int verify_block_sig(struct mlx5_cmd_prot_block *block)
 159 {
 160         if (xor8_buf(block->rsvd0, sizeof(*block) - sizeof(block->data) - 1) != 0xff)
 161                 return -EINVAL;
 162
 163         if (xor8_buf(block, sizeof(*block)) != 0xff)
 164                 return -EINVAL;
 165
 166         return 0;
 167 }
 168
 169 static void calc_block_sig(struct mlx5_cmd_prot_block *block, u8 token,
 170                            int csum)
 171 {
 172         block->token = token;
 173         if (csum) {
 174                 block->ctrl_sig = ~xor8_buf(block->rsvd0, sizeof(*block) -
 175                                             sizeof(block->data) - 2);
 176                 block->sig = ~xor8_buf(block, sizeof(*block) - 1);
 177         }
 178 }
 179
 180 static void calc_chain_sig(struct mlx5_cmd_msg *msg, u8 token, int csum)
 181 {
 182         struct mlx5_cmd_mailbox *next = msg->next;
 183
 184         while (next) {
 185                 calc_block_sig(next->buf, token, csum);
 186                 next = next->next;
 187         }
 188 }
 189
 190 static void set_signature(struct mlx5_cmd_work_ent *ent, int csum)
 191 {
 192         ent->lay->sig = ~xor8_buf(ent->lay, sizeof(*ent->lay));
 193         calc_chain_sig(ent->in, ent->token, csum);
 194         calc_chain_sig(ent->out, ent->token, csum);
 195 }
 196
 197 static void poll_timeout(struct mlx5_cmd_work_ent *ent)
 198 {
 199         unsigned long poll_end = jiffies + msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC + 1000);
 200         u8 own;
 201
 202         do {
 203                 own = ent->lay->status_own;
 204                 if (!(own & CMD_OWNER_HW)) {
 205                         ent->ret = 0;
 206                         return;
 207                 }
 208                 usleep_range(5000, 10000);
 209         } while (time_before(jiffies, poll_end));
 210
 211         ent->ret = -ETIMEDOUT;
 212 }
 213
 214 static void free_cmd(struct mlx5_cmd_work_ent *ent)
 215 {
 216         kfree(ent);
 217 }
 218
 219
 220 static int verify_signature(struct mlx5_cmd_work_ent *ent)
 221 {
 222         struct mlx5_cmd_mailbox *next = ent->out->next;
 223         int err;
 224         u8 sig;
 225
 226         sig = xor8_buf(ent->lay, sizeof(*ent->lay));
 227         if (sig != 0xff)
 228                 return -EINVAL;
 229
 230         while (next) {
 231                 err = verify_block_sig(next->buf);
 232                 if (err)
 233                         return err;
 234
 235                 next = next->next;
 236         }
 237
 238         return 0;
 239 }
 240
 241 static void dump_buf(void *buf, int size, int data_only, int offset)
 242 {
 243         __be32 *p = buf;
 244         int i;
 245
 246         for (i = 0; i < size; i += 16) {
 247                 pr_debug("%03x: %08x %08x %08x %08x\n", offset, be32_to_cpu(p[0]),
 248                          be32_to_cpu(p[1]), be32_to_cpu(p[2]),
 249                          be32_to_cpu(p[3]));
 250                 p += 4;
 251                 offset += 16;
 252         }
 253         if (!data_only)
 254                 pr_debug("\n");
 255 }
 256
 257 enum {
 258         MLX5_DRIVER_STATUS_ABORTED = 0xfe,
 259         MLX5_DRIVER_SYND = 0xbadd00de,
 260 };
 261
 262 static int mlx5_internal_err_ret_value(struct mlx5_core_dev *dev, u16 op,
 263                                        u32 *synd, u8 *status)
 264 {
 265         *synd = 0;
 266         *status = 0;
 267
 268         switch (op) {
 269         case MLX5_CMD_OP_TEARDOWN_HCA:
 270         case MLX5_CMD_OP_DISABLE_HCA:
 271         case MLX5_CMD_OP_MANAGE_PAGES:
 272         case MLX5_CMD_OP_DESTROY_MKEY:
 273         case MLX5_CMD_OP_DESTROY_EQ:
 274         case MLX5_CMD_OP_DESTROY_CQ:
 275         case MLX5_CMD_OP_DESTROY_QP:
 276         case MLX5_CMD_OP_DESTROY_PSV:
 277         case MLX5_CMD_OP_DESTROY_SRQ:
 278         case MLX5_CMD_OP_DESTROY_XRC_SRQ:
 279         case MLX5_CMD_OP_DESTROY_DCT:
 280         case MLX5_CMD_OP_DEALLOC_Q_COUNTER:
 281         case MLX5_CMD_OP_DEALLOC_PD:
 282         case MLX5_CMD_OP_DEALLOC_UAR:
 283         case MLX5_CMD_OP_DETTACH_FROM_MCG:
 284         case MLX5_CMD_OP_DEALLOC_XRCD:
 285         case MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN:
 286         case MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT:
 287         case MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY:
 288         case MLX5_CMD_OP_DESTROY_TIR:
 289         case MLX5_CMD_OP_DESTROY_SQ:
 290         case MLX5_CMD_OP_DESTROY_RQ:
 291         case MLX5_CMD_OP_DESTROY_RMP:
 292         case MLX5_CMD_OP_DESTROY_TIS:
 293         case MLX5_CMD_OP_DESTROY_RQT:
 294         case MLX5_CMD_OP_DESTROY_FLOW_TABLE:
 295         case MLX5_CMD_OP_DESTROY_FLOW_GROUP:
 296         case MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY:
 297         case MLX5_CMD_OP_DEALLOC_FLOW_COUNTER:
 298         case MLX5_CMD_OP_2ERR_QP:
 299         case MLX5_CMD_OP_2RST_QP:
 300         case MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT:
 301         case MLX5_CMD_OP_MODIFY_FLOW_TABLE:
 302         case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY:
 303         case MLX5_CMD_OP_SET_FLOW_TABLE_ROOT:
 304                 return MLX5_CMD_STAT_OK;
 305
 306         case MLX5_CMD_OP_QUERY_HCA_CAP:
 307         case MLX5_CMD_OP_QUERY_ADAPTER:
 308         case MLX5_CMD_OP_INIT_HCA:
 309         case MLX5_CMD_OP_ENABLE_HCA:
 310         case MLX5_CMD_OP_QUERY_PAGES:
 311         case MLX5_CMD_OP_SET_HCA_CAP:
 312         case MLX5_CMD_OP_QUERY_ISSI:
 313         case MLX5_CMD_OP_SET_ISSI:
 314         case MLX5_CMD_OP_CREATE_MKEY:
 315         case MLX5_CMD_OP_QUERY_MKEY:
 316         case MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS:
 317         case MLX5_CMD_OP_PAGE_FAULT_RESUME:
 318         case MLX5_CMD_OP_CREATE_EQ:
 319         case MLX5_CMD_OP_QUERY_EQ:
 320         case MLX5_CMD_OP_GEN_EQE:
 321         case MLX5_CMD_OP_CREATE_CQ:
 322         case MLX5_CMD_OP_QUERY_CQ:
 323         case MLX5_CMD_OP_MODIFY_CQ:
 324         case MLX5_CMD_OP_CREATE_QP:
 325         case MLX5_CMD_OP_RST2INIT_QP:
 326         case MLX5_CMD_OP_INIT2RTR_QP:
 327         case MLX5_CMD_OP_RTR2RTS_QP:
 328         case MLX5_CMD_OP_RTS2RTS_QP:
 329         case MLX5_CMD_OP_SQERR2RTS_QP:
 330         case MLX5_CMD_OP_QUERY_QP:
 331         case MLX5_CMD_OP_SQD_RTS_QP:
 332         case MLX5_CMD_OP_INIT2INIT_QP:
 333         case MLX5_CMD_OP_CREATE_PSV:
 334         case MLX5_CMD_OP_CREATE_SRQ:
 335         case MLX5_CMD_OP_QUERY_SRQ:
 336         case MLX5_CMD_OP_ARM_RQ:
 337         case MLX5_CMD_OP_CREATE_XRC_SRQ:
 338         case MLX5_CMD_OP_QUERY_XRC_SRQ:
 339         case MLX5_CMD_OP_ARM_XRC_SRQ:
 340         case MLX5_CMD_OP_CREATE_DCT:
 341         case MLX5_CMD_OP_DRAIN_DCT:
 342         case MLX5_CMD_OP_QUERY_DCT:
 343         case MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION:
 344         case MLX5_CMD_OP_QUERY_VPORT_STATE:
 345         case MLX5_CMD_OP_MODIFY_VPORT_STATE:
 346         case MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT:
 347         case MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT:
 348         case MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT:
 349         case MLX5_CMD_OP_QUERY_ROCE_ADDRESS:
 350         case MLX5_CMD_OP_SET_ROCE_ADDRESS:
 351         case MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT:
 352         case MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT:
 353         case MLX5_CMD_OP_QUERY_HCA_VPORT_GID:
 354         case MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY:
 355         case MLX5_CMD_OP_QUERY_VPORT_COUNTER:
 356         case MLX5_CMD_OP_ALLOC_Q_COUNTER:
 357         case MLX5_CMD_OP_QUERY_Q_COUNTER:
 358         case MLX5_CMD_OP_ALLOC_PD:
 359         case MLX5_CMD_OP_ALLOC_UAR:
 360         case MLX5_CMD_OP_CONFIG_INT_MODERATION:
 361         case MLX5_CMD_OP_ACCESS_REG:
 362         case MLX5_CMD_OP_ATTACH_TO_MCG:
 363         case MLX5_CMD_OP_GET_DROPPED_PACKET_LOG:
 364         case MLX5_CMD_OP_MAD_IFC:
 365         case MLX5_CMD_OP_QUERY_MAD_DEMUX:
 366         case MLX5_CMD_OP_SET_MAD_DEMUX:
 367         case MLX5_CMD_OP_NOP:
 368         case MLX5_CMD_OP_ALLOC_XRCD:
 369         case MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN:
 370         case MLX5_CMD_OP_QUERY_CONG_STATUS:
 371         case MLX5_CMD_OP_MODIFY_CONG_STATUS:
 372         case MLX5_CMD_OP_QUERY_CONG_PARAMS:
 373         case MLX5_CMD_OP_MODIFY_CONG_PARAMS:
 374         case MLX5_CMD_OP_QUERY_CONG_STATISTICS:
 375         case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT:
 376         case MLX5_CMD_OP_SET_L2_TABLE_ENTRY:
 377         case MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY:
 378         case MLX5_CMD_OP_CREATE_TIR:
 379         case MLX5_CMD_OP_MODIFY_TIR:
 380         case MLX5_CMD_OP_QUERY_TIR:
 381         case MLX5_CMD_OP_CREATE_SQ:
 382         case MLX5_CMD_OP_MODIFY_SQ:
 383         case MLX5_CMD_OP_QUERY_SQ:
 384         case MLX5_CMD_OP_CREATE_RQ:
 385         case MLX5_CMD_OP_MODIFY_RQ:
 386         case MLX5_CMD_OP_QUERY_RQ:
 387         case MLX5_CMD_OP_CREATE_RMP:
 388         case MLX5_CMD_OP_MODIFY_RMP:
 389         case MLX5_CMD_OP_QUERY_RMP:
 390         case MLX5_CMD_OP_CREATE_TIS:
 391         case MLX5_CMD_OP_MODIFY_TIS:
 392         case MLX5_CMD_OP_QUERY_TIS:
 393         case MLX5_CMD_OP_CREATE_RQT:
 394         case MLX5_CMD_OP_MODIFY_RQT:
 395         case MLX5_CMD_OP_QUERY_RQT:
 396
 397         case MLX5_CMD_OP_CREATE_FLOW_TABLE:
 398         case MLX5_CMD_OP_QUERY_FLOW_TABLE:
 399         case MLX5_CMD_OP_CREATE_FLOW_GROUP:
 400         case MLX5_CMD_OP_QUERY_FLOW_GROUP:
 401
 402         case MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY:
 403         case MLX5_CMD_OP_ALLOC_FLOW_COUNTER:
 404         case MLX5_CMD_OP_QUERY_FLOW_COUNTER:
 405                 *status = MLX5_DRIVER_STATUS_ABORTED;
 406                 *synd = MLX5_DRIVER_SYND;
 407                 return -EIO;
 408         default:
 409                 mlx5_core_err(dev, "Unknown FW command (%d)\n", op);
 410                 return -EINVAL;
 411         }
 412 }
 413
 414 const char *mlx5_command_str(int command)
 415 {
 416 #define MLX5_COMMAND_STR_CASE(__cmd) case MLX5_CMD_OP_ ## __cmd: return #__cmd
 417
 418         switch (command) {
 419         MLX5_COMMAND_STR_CASE(QUERY_HCA_CAP);
 420         MLX5_COMMAND_STR_CASE(QUERY_ADAPTER);
 421         MLX5_COMMAND_STR_CASE(INIT_HCA);
 422         MLX5_COMMAND_STR_CASE(TEARDOWN_HCA);
 423         MLX5_COMMAND_STR_CASE(ENABLE_HCA);
 424         MLX5_COMMAND_STR_CASE(DISABLE_HCA);
 425         MLX5_COMMAND_STR_CASE(QUERY_PAGES);
 426         MLX5_COMMAND_STR_CASE(MANAGE_PAGES);
 427         MLX5_COMMAND_STR_CASE(SET_HCA_CAP);
 428         MLX5_COMMAND_STR_CASE(QUERY_ISSI);
 429         MLX5_COMMAND_STR_CASE(SET_ISSI);
 430         MLX5_COMMAND_STR_CASE(CREATE_MKEY);
 431         MLX5_COMMAND_STR_CASE(QUERY_MKEY);
 432         MLX5_COMMAND_STR_CASE(DESTROY_MKEY);
 433         MLX5_COMMAND_STR_CASE(QUERY_SPECIAL_CONTEXTS);
 434         MLX5_COMMAND_STR_CASE(PAGE_FAULT_RESUME);
 435         MLX5_COMMAND_STR_CASE(CREATE_EQ);
 436         MLX5_COMMAND_STR_CASE(DESTROY_EQ);
 437         MLX5_COMMAND_STR_CASE(QUERY_EQ);
 438         MLX5_COMMAND_STR_CASE(GEN_EQE);
 439         MLX5_COMMAND_STR_CASE(CREATE_CQ);
 440         MLX5_COMMAND_STR_CASE(DESTROY_CQ);
 441         MLX5_COMMAND_STR_CASE(QUERY_CQ);
 442         MLX5_COMMAND_STR_CASE(MODIFY_CQ);
 443         MLX5_COMMAND_STR_CASE(CREATE_QP);
 444         MLX5_COMMAND_STR_CASE(DESTROY_QP);
 445         MLX5_COMMAND_STR_CASE(RST2INIT_QP);
 446         MLX5_COMMAND_STR_CASE(INIT2RTR_QP);
 447         MLX5_COMMAND_STR_CASE(RTR2RTS_QP);
 448         MLX5_COMMAND_STR_CASE(RTS2RTS_QP);
 449         MLX5_COMMAND_STR_CASE(SQERR2RTS_QP);
 450         MLX5_COMMAND_STR_CASE(2ERR_QP);
 451         MLX5_COMMAND_STR_CASE(2RST_QP);
 452         MLX5_COMMAND_STR_CASE(QUERY_QP);
 453         MLX5_COMMAND_STR_CASE(SQD_RTS_QP);
 454         MLX5_COMMAND_STR_CASE(INIT2INIT_QP);
 455         MLX5_COMMAND_STR_CASE(CREATE_PSV);
 456         MLX5_COMMAND_STR_CASE(DESTROY_PSV);
 457         MLX5_COMMAND_STR_CASE(CREATE_SRQ);
 458         MLX5_COMMAND_STR_CASE(DESTROY_SRQ);
 459         MLX5_COMMAND_STR_CASE(QUERY_SRQ);
 460         MLX5_COMMAND_STR_CASE(ARM_RQ);
 461         MLX5_COMMAND_STR_CASE(CREATE_XRC_SRQ);
 462         MLX5_COMMAND_STR_CASE(DESTROY_XRC_SRQ);
 463         MLX5_COMMAND_STR_CASE(QUERY_XRC_SRQ);
 464         MLX5_COMMAND_STR_CASE(ARM_XRC_SRQ);
 465         MLX5_COMMAND_STR_CASE(CREATE_DCT);
 466         MLX5_COMMAND_STR_CASE(DESTROY_DCT);
 467         MLX5_COMMAND_STR_CASE(DRAIN_DCT);
 468         MLX5_COMMAND_STR_CASE(QUERY_DCT);
 469         MLX5_COMMAND_STR_CASE(ARM_DCT_FOR_KEY_VIOLATION);
 470         MLX5_COMMAND_STR_CASE(QUERY_VPORT_STATE);
 471         MLX5_COMMAND_STR_CASE(MODIFY_VPORT_STATE);
 472         MLX5_COMMAND_STR_CASE(QUERY_ESW_VPORT_CONTEXT);
 473         MLX5_COMMAND_STR_CASE(MODIFY_ESW_VPORT_CONTEXT);
 474         MLX5_COMMAND_STR_CASE(QUERY_NIC_VPORT_CONTEXT);
 475         MLX5_COMMAND_STR_CASE(MODIFY_NIC_VPORT_CONTEXT);
 476         MLX5_COMMAND_STR_CASE(QUERY_ROCE_ADDRESS);
 477         MLX5_COMMAND_STR_CASE(SET_ROCE_ADDRESS);
 478         MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_CONTEXT);
 479         MLX5_COMMAND_STR_CASE(MODIFY_HCA_VPORT_CONTEXT);
 480         MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_GID);
 481         MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_PKEY);
 482         MLX5_COMMAND_STR_CASE(QUERY_VPORT_COUNTER);
 483         MLX5_COMMAND_STR_CASE(ALLOC_Q_COUNTER);
 484         MLX5_COMMAND_STR_CASE(DEALLOC_Q_COUNTER);
 485         MLX5_COMMAND_STR_CASE(QUERY_Q_COUNTER);
 486         MLX5_COMMAND_STR_CASE(ALLOC_PD);
 487         MLX5_COMMAND_STR_CASE(DEALLOC_PD);
 488         MLX5_COMMAND_STR_CASE(ALLOC_UAR);
 489         MLX5_COMMAND_STR_CASE(DEALLOC_UAR);
 490         MLX5_COMMAND_STR_CASE(CONFIG_INT_MODERATION);
 491         MLX5_COMMAND_STR_CASE(ACCESS_REG);
 492         MLX5_COMMAND_STR_CASE(ATTACH_TO_MCG);
 493         MLX5_COMMAND_STR_CASE(DETTACH_FROM_MCG);
 494         MLX5_COMMAND_STR_CASE(GET_DROPPED_PACKET_LOG);
 495         MLX5_COMMAND_STR_CASE(MAD_IFC);
 496         MLX5_COMMAND_STR_CASE(QUERY_MAD_DEMUX);
 497         MLX5_COMMAND_STR_CASE(SET_MAD_DEMUX);
 498         MLX5_COMMAND_STR_CASE(NOP);
 499         MLX5_COMMAND_STR_CASE(ALLOC_XRCD);
 500         MLX5_COMMAND_STR_CASE(DEALLOC_XRCD);
 501         MLX5_COMMAND_STR_CASE(ALLOC_TRANSPORT_DOMAIN);
 502         MLX5_COMMAND_STR_CASE(DEALLOC_TRANSPORT_DOMAIN);
 503         MLX5_COMMAND_STR_CASE(QUERY_CONG_STATUS);
 504         MLX5_COMMAND_STR_CASE(MODIFY_CONG_STATUS);
 505         MLX5_COMMAND_STR_CASE(QUERY_CONG_PARAMS);
 506         MLX5_COMMAND_STR_CASE(MODIFY_CONG_PARAMS);
 507         MLX5_COMMAND_STR_CASE(QUERY_CONG_STATISTICS);
 508         MLX5_COMMAND_STR_CASE(ADD_VXLAN_UDP_DPORT);
 509         MLX5_COMMAND_STR_CASE(DELETE_VXLAN_UDP_DPORT);
 510         MLX5_COMMAND_STR_CASE(SET_L2_TABLE_ENTRY);
 511         MLX5_COMMAND_STR_CASE(QUERY_L2_TABLE_ENTRY);
 512         MLX5_COMMAND_STR_CASE(DELETE_L2_TABLE_ENTRY);
 513         MLX5_COMMAND_STR_CASE(SET_WOL_ROL);
 514         MLX5_COMMAND_STR_CASE(QUERY_WOL_ROL);
 515         MLX5_COMMAND_STR_CASE(CREATE_TIR);
 516         MLX5_COMMAND_STR_CASE(MODIFY_TIR);
 517         MLX5_COMMAND_STR_CASE(DESTROY_TIR);
 518         MLX5_COMMAND_STR_CASE(QUERY_TIR);
 519         MLX5_COMMAND_STR_CASE(CREATE_SQ);
 520         MLX5_COMMAND_STR_CASE(MODIFY_SQ);
 521         MLX5_COMMAND_STR_CASE(DESTROY_SQ);
 522         MLX5_COMMAND_STR_CASE(QUERY_SQ);
 523         MLX5_COMMAND_STR_CASE(CREATE_RQ);
 524         MLX5_COMMAND_STR_CASE(MODIFY_RQ);
 525         MLX5_COMMAND_STR_CASE(DESTROY_RQ);
 526         MLX5_COMMAND_STR_CASE(QUERY_RQ);
 527         MLX5_COMMAND_STR_CASE(CREATE_RMP);
 528         MLX5_COMMAND_STR_CASE(MODIFY_RMP);
 529         MLX5_COMMAND_STR_CASE(DESTROY_RMP);
 530         MLX5_COMMAND_STR_CASE(QUERY_RMP);
 531         MLX5_COMMAND_STR_CASE(CREATE_TIS);
 532         MLX5_COMMAND_STR_CASE(MODIFY_TIS);
 533         MLX5_COMMAND_STR_CASE(DESTROY_TIS);
 534         MLX5_COMMAND_STR_CASE(QUERY_TIS);
 535         MLX5_COMMAND_STR_CASE(CREATE_RQT);
 536         MLX5_COMMAND_STR_CASE(MODIFY_RQT);
 537         MLX5_COMMAND_STR_CASE(DESTROY_RQT);
 538         MLX5_COMMAND_STR_CASE(QUERY_RQT);
 539         MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ROOT);
 540         MLX5_COMMAND_STR_CASE(CREATE_FLOW_TABLE);
 541         MLX5_COMMAND_STR_CASE(DESTROY_FLOW_TABLE);
 542         MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE);
 543         MLX5_COMMAND_STR_CASE(CREATE_FLOW_GROUP);
 544         MLX5_COMMAND_STR_CASE(DESTROY_FLOW_GROUP);
 545         MLX5_COMMAND_STR_CASE(QUERY_FLOW_GROUP);
 546         MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ENTRY);
 547         MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE_ENTRY);
 548         MLX5_COMMAND_STR_CASE(DELETE_FLOW_TABLE_ENTRY);
 549         MLX5_COMMAND_STR_CASE(ALLOC_FLOW_COUNTER);
 550         MLX5_COMMAND_STR_CASE(DEALLOC_FLOW_COUNTER);
 551         MLX5_COMMAND_STR_CASE(QUERY_FLOW_COUNTER);
 552         MLX5_COMMAND_STR_CASE(MODIFY_FLOW_TABLE);
 553         default: return "unknown command opcode";
 554         }
 555 }
 556
 557 static void dump_command(struct mlx5_core_dev *dev,
 558                          struct mlx5_cmd_work_ent *ent, int input)
 559 {
 560         u16 op = be16_to_cpu(((struct mlx5_inbox_hdr *)(ent->lay->in))->opcode);
 561         struct mlx5_cmd_msg *msg = input ? ent->in : ent->out;
 562         struct mlx5_cmd_mailbox *next = msg->next;
 563         int data_only;
 564         u32 offset = 0;
 565         int dump_len;
 566
 567         data_only = !!(mlx5_core_debug_mask & (1 << MLX5_CMD_DATA));
 568
 569         if (data_only)
 570                 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_DATA,
 571                                    "dump command data %s(0x%x) %s\n",
 572                                    mlx5_command_str(op), op,
 573                                    input ? "INPUT" : "OUTPUT");
 574         else
 575                 mlx5_core_dbg(dev, "dump command %s(0x%x) %s\n",
 576                               mlx5_command_str(op), op,
 577                               input ? "INPUT" : "OUTPUT");
 578
 579         if (data_only) {
 580                 if (input) {
 581                         dump_buf(ent->lay->in, sizeof(ent->lay->in), 1, offset);
 582                         offset += sizeof(ent->lay->in);
 583                 } else {
 584                         dump_buf(ent->lay->out, sizeof(ent->lay->out), 1, offset);
 585                         offset += sizeof(ent->lay->out);
 586                 }
 587         } else {
 588                 dump_buf(ent->lay, sizeof(*ent->lay), 0, offset);
 589                 offset += sizeof(*ent->lay);
 590         }
 591
 592         while (next && offset < msg->len) {
 593                 if (data_only) {
 594                         dump_len = min_t(int, MLX5_CMD_DATA_BLOCK_SIZE, msg->len - offset);
 595                         dump_buf(next->buf, dump_len, 1, offset);
 596                         offset += MLX5_CMD_DATA_BLOCK_SIZE;
 597                 } else {
 598                         mlx5_core_dbg(dev, "command block:\n");
 599                         dump_buf(next->buf, sizeof(struct mlx5_cmd_prot_block), 0, offset);
 600                         offset += sizeof(struct mlx5_cmd_prot_block);
 601                 }
 602                 next = next->next;
 603         }
 604
 605         if (data_only)
 606                 pr_debug("\n");
 607 }
 608
 609 static void cmd_work_handler(struct work_struct *work)
 610 {
 611         struct mlx5_cmd_work_ent *ent = container_of(work, struct mlx5_cmd_work_ent, work);
 612         struct mlx5_cmd *cmd = ent->cmd;
 613         struct mlx5_core_dev *dev = container_of(cmd, struct mlx5_core_dev, cmd);
 614         struct mlx5_cmd_layout *lay;
 615         struct semaphore *sem;
 616         unsigned long flags;
 617
 618         sem = ent->page_queue ? &cmd->pages_sem : &cmd->sem;
 619         down(sem);
 620         if (!ent->page_queue) {
 621                 ent->idx = alloc_ent(cmd);
 622                 if (ent->idx < 0) {
 623                         mlx5_core_err(dev, "failed to allocate command entry\n");
 624                         up(sem);
 625                         return;
 626                 }
 627         } else {
 628                 ent->idx = cmd->max_reg_cmds;
 629                 spin_lock_irqsave(&cmd->alloc_lock, flags);
 630                 clear_bit(ent->idx, &cmd->bitmask);
 631                 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
 632         }
 633
 634         ent->token = alloc_token(cmd);
 635         cmd->ent_arr[ent->idx] = ent;
 636         lay = get_inst(cmd, ent->idx);
 637         ent->lay = lay;
 638         memset(lay, 0, sizeof(*lay));
 639         memcpy(lay->in, ent->in->first.data, sizeof(lay->in));
 640         ent->op = be32_to_cpu(lay->in[0]) >> 16;
 641         if (ent->in->next)
 642                 lay->in_ptr = cpu_to_be64(ent->in->next->dma);
 643         lay->inlen = cpu_to_be32(ent->in->len);
 644         if (ent->out->next)
 645                 lay->out_ptr = cpu_to_be64(ent->out->next->dma);
 646         lay->outlen = cpu_to_be32(ent->out->len);
 647         lay->type = MLX5_PCI_CMD_XPORT;
 648         lay->token = ent->token;
 649         lay->status_own = CMD_OWNER_HW;
 650         set_signature(ent, !cmd->checksum_disabled);
 651         dump_command(dev, ent, 1);
 652         ent->ts1 = ktime_get_ns();
 653
 654         /* ring doorbell after the descriptor is valid */
 655         mlx5_core_dbg(dev, "writing 0x%x to command doorbell\n", 1 << ent->idx);
 656         wmb();
 657         iowrite32be(1 << ent->idx, &dev->iseg->cmd_dbell);
 658         mmiowb();
 659         /* if not in polling don't use ent after this point */
 660         if (cmd->mode == CMD_MODE_POLLING) {
 661                 poll_timeout(ent);
 662                 /* make sure we read the descriptor after ownership is SW */
 663                 rmb();
 664                 mlx5_cmd_comp_handler(dev, 1UL << ent->idx);
 665         }
 666 }
 667
 668 static const char *deliv_status_to_str(u8 status)
 669 {
 670         switch (status) {
 671         case MLX5_CMD_DELIVERY_STAT_OK:
 672                 return "no errors";
 673         case MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR:
 674                 return "signature error";
 675         case MLX5_CMD_DELIVERY_STAT_TOK_ERR:
 676                 return "token error";
 677         case MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR:
 678                 return "bad block number";
 679         case MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR:
 680                 return "output pointer not aligned to block size";
 681         case MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR:
 682                 return "input pointer not aligned to block size";
 683         case MLX5_CMD_DELIVERY_STAT_FW_ERR:
 684                 return "firmware internal error";
 685         case MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR:
 686                 return "command input length error";
 687         case MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR:
 688                 return "command ouput length error";
 689         case MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR:
 690                 return "reserved fields not cleared";
 691         case MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR:
 692                 return "bad command descriptor type";
 693         default:
 694                 return "unknown status code";
 695         }
 696 }
 697
 698 static u16 msg_to_opcode(struct mlx5_cmd_msg *in)
 699 {
 700         struct mlx5_inbox_hdr *hdr = (struct mlx5_inbox_hdr *)(in->first.data);
 701
 702         return be16_to_cpu(hdr->opcode);
 703 }
 704
 705 static int wait_func(struct mlx5_core_dev *dev, struct mlx5_cmd_work_ent *ent)
 706 {
 707         unsigned long timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC);
 708         struct mlx5_cmd *cmd = &dev->cmd;
 709         int err;
 710
 711         if (cmd->mode == CMD_MODE_POLLING) {
 712                 wait_for_completion(&ent->done);
 713         } else if (!wait_for_completion_timeout(&ent->done, timeout)) {
 714                 ent->ret = -ETIMEDOUT;
 715                 mlx5_cmd_comp_handler(dev, 1UL << ent->idx);
 716         }
 717
 718         err = ent->ret;
 719
 720         if (err == -ETIMEDOUT) {
 721                 mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n",
 722                                mlx5_command_str(msg_to_opcode(ent->in)),
 723                                msg_to_opcode(ent->in));
 724         }
 725         mlx5_core_dbg(dev, "err %d, delivery status %s(%d)\n",
 726                       err, deliv_status_to_str(ent->status), ent->status);
 727
 728         return err;
 729 }
 730
 731 static __be32 *get_synd_ptr(struct mlx5_outbox_hdr *out)
 732 {
 733         return &out->syndrome;
 734 }
 735
 736 static u8 *get_status_ptr(struct mlx5_outbox_hdr *out)
 737 {
 738         return &out->status;
 739 }
 740
 741 /*  Notes:
 742  *    1. Callback functions may not sleep
 743  *    2. page queue commands do not support asynchrous completion
 744  */
 745 static int mlx5_cmd_invoke(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *in,
 746                            struct mlx5_cmd_msg *out, void *uout, int uout_size,
 747                            mlx5_cmd_cbk_t callback,
 748                            void *context, int page_queue, u8 *status)
 749 {
 750         struct mlx5_cmd *cmd = &dev->cmd;
 751         struct mlx5_cmd_work_ent *ent;
 752         struct mlx5_cmd_stats *stats;
 753         int err = 0;
 754         s64 ds;
 755         u16 op;
 756
 757         if (callback && page_queue)
 758                 return -EINVAL;
 759
 760         ent = alloc_cmd(cmd, in, out, uout, uout_size, callback, context,
 761                         page_queue);
 762         if (IS_ERR(ent))
 763                 return PTR_ERR(ent);
 764
 765         if (!callback)
 766                 init_completion(&ent->done);
 767
 768         INIT_WORK(&ent->work, cmd_work_handler);
 769         if (page_queue) {
 770                 cmd_work_handler(&ent->work);
 771         } else if (!queue_work(cmd->wq, &ent->work)) {
 772                 mlx5_core_warn(dev, "failed to queue work\n");
 773                 err = -ENOMEM;
 774                 goto out_free;
 775         }
 776
 777         if (callback)
 778                 goto out;
 779
 780         err = wait_func(dev, ent);
 781         if (err == -ETIMEDOUT)
 782                 goto out_free;
 783
 784         ds = ent->ts2 - ent->ts1;
 785         op = be16_to_cpu(((struct mlx5_inbox_hdr *)in->first.data)->opcode);
 786         if (op < ARRAY_SIZE(cmd->stats)) {
 787                 stats = &cmd->stats[op];
 788                 spin_lock_irq(&stats->lock);
 789                 stats->sum += ds;
 790                 ++stats->n;
 791                 spin_unlock_irq(&stats->lock);
 792         }
 793         mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_TIME,
 794                            "fw exec time for %s is %lld nsec\n",
 795                            mlx5_command_str(op), ds);
 796         *status = ent->status;
 797
 798 out_free:
 799         free_cmd(ent);
 800 out:
 801         return err;
 802 }
 803
 804 static ssize_t dbg_write(struct file *filp, const char __user *buf,
 805                          size_t count, loff_t *pos)
 806 {
 807         struct mlx5_core_dev *dev = filp->private_data;
 808         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
 809         char lbuf[3];
 810         int err;
 811
 812         if (!dbg->in_msg || !dbg->out_msg)
 813                 return -ENOMEM;
 814
 815         if (copy_from_user(lbuf, buf, sizeof(lbuf)))
 816                 return -EFAULT;
 817
 818         lbuf[sizeof(lbuf) - 1] = 0;
 819
 820         if (strcmp(lbuf, "go"))
 821                 return -EINVAL;
 822
 823         err = mlx5_cmd_exec(dev, dbg->in_msg, dbg->inlen, dbg->out_msg, dbg->outlen);
 824
 825         return err ? err : count;
 826 }
 827
 828
 829 static const struct file_operations fops = {
 830         .owner  = THIS_MODULE,
 831         .open   = simple_open,
 832         .write  = dbg_write,
 833 };
 834
 835 static int mlx5_copy_to_msg(struct mlx5_cmd_msg *to, void *from, int size)
 836 {
 837         struct mlx5_cmd_prot_block *block;
 838         struct mlx5_cmd_mailbox *next;
 839         int copy;
 840
 841         if (!to || !from)
 842                 return -ENOMEM;
 843
 844         copy = min_t(int, size, sizeof(to->first.data));
 845         memcpy(to->first.data, from, copy);
 846         size -= copy;
 847         from += copy;
 848
 849         next = to->next;
 850         while (size) {
 851                 if (!next) {
 852                         /* this is a BUG */
 853                         return -ENOMEM;
 854                 }
 855
 856                 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
 857                 block = next->buf;
 858                 memcpy(block->data, from, copy);
 859                 from += copy;
 860                 size -= copy;
 861                 next = next->next;
 862         }
 863
 864         return 0;
 865 }
 866
 867 static int mlx5_copy_from_msg(void *to, struct mlx5_cmd_msg *from, int size)
 868 {
 869         struct mlx5_cmd_prot_block *block;
 870         struct mlx5_cmd_mailbox *next;
 871         int copy;
 872
 873         if (!to || !from)
 874                 return -ENOMEM;
 875
 876         copy = min_t(int, size, sizeof(from->first.data));
 877         memcpy(to, from->first.data, copy);
 878         size -= copy;
 879         to += copy;
 880
 881         next = from->next;
 882         while (size) {
 883                 if (!next) {
 884                         /* this is a BUG */
 885                         return -ENOMEM;
 886                 }
 887
 888                 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
 889                 block = next->buf;
 890
 891                 memcpy(to, block->data, copy);
 892                 to += copy;
 893                 size -= copy;
 894                 next = next->next;
 895         }
 896
 897         return 0;
 898 }
 899
 900 static struct mlx5_cmd_mailbox *alloc_cmd_box(struct mlx5_core_dev *dev,
 901                                               gfp_t flags)
 902 {
 903         struct mlx5_cmd_mailbox *mailbox;
 904
 905         mailbox = kmalloc(sizeof(*mailbox), flags);
 906         if (!mailbox)
 907                 return ERR_PTR(-ENOMEM);
 908
 909         mailbox->buf = pci_pool_alloc(dev->cmd.pool, flags,
 910                                       &mailbox->dma);
 911         if (!mailbox->buf) {
 912                 mlx5_core_dbg(dev, "failed allocation\n");
 913                 kfree(mailbox);
 914                 return ERR_PTR(-ENOMEM);
 915         }
 916         memset(mailbox->buf, 0, sizeof(struct mlx5_cmd_prot_block));
 917         mailbox->next = NULL;
 918
 919         return mailbox;
 920 }
 921
 922 static void free_cmd_box(struct mlx5_core_dev *dev,
 923                          struct mlx5_cmd_mailbox *mailbox)
 924 {
 925         pci_pool_free(dev->cmd.pool, mailbox->buf, mailbox->dma);
 926         kfree(mailbox);
 927 }
 928
 929 static struct mlx5_cmd_msg *mlx5_alloc_cmd_msg(struct mlx5_core_dev *dev,
 930                                                gfp_t flags, int size)
 931 {
 932         struct mlx5_cmd_mailbox *tmp, *head = NULL;
 933         struct mlx5_cmd_prot_block *block;
 934         struct mlx5_cmd_msg *msg;
 935         int blen;
 936         int err;
 937         int n;
 938         int i;
 939
 940         msg = kzalloc(sizeof(*msg), flags);
 941         if (!msg)
 942                 return ERR_PTR(-ENOMEM);
 943
 944         blen = size - min_t(int, sizeof(msg->first.data), size);
 945         n = (blen + MLX5_CMD_DATA_BLOCK_SIZE - 1) / MLX5_CMD_DATA_BLOCK_SIZE;
 946
 947         for (i = 0; i < n; i++) {
 948                 tmp = alloc_cmd_box(dev, flags);
 949                 if (IS_ERR(tmp)) {
 950                         mlx5_core_warn(dev, "failed allocating block\n");
 951                         err = PTR_ERR(tmp);
 952                         goto err_alloc;
 953                 }
 954
 955                 block = tmp->buf;
 956                 tmp->next = head;
 957                 block->next = cpu_to_be64(tmp->next ? tmp->next->dma : 0);
 958                 block->block_num = cpu_to_be32(n - i - 1);
 959                 head = tmp;
 960         }
 961         msg->next = head;
 962         msg->len = size;
 963         return msg;
 964
 965 err_alloc:
 966         while (head) {
 967                 tmp = head->next;
 968                 free_cmd_box(dev, head);
 969                 head = tmp;
 970         }
 971         kfree(msg);
 972
 973         return ERR_PTR(err);
 974 }
 975
 976 static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,
 977                                   struct mlx5_cmd_msg *msg)
 978 {
 979         struct mlx5_cmd_mailbox *head = msg->next;
 980         struct mlx5_cmd_mailbox *next;
 981
 982         while (head) {
 983                 next = head->next;
 984                 free_cmd_box(dev, head);
 985                 head = next;
 986         }
 987         kfree(msg);
 988 }
 989
 990 static ssize_t data_write(struct file *filp, const char __user *buf,
 991                           size_t count, loff_t *pos)
 992 {
 993         struct mlx5_core_dev *dev = filp->private_data;
 994         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
 995         void *ptr;
 996         int err;
 997
 998         if (*pos != 0)
 999                 return -EINVAL;
1000
1001         kfree(dbg->in_msg);
1002         dbg->in_msg = NULL;
1003         dbg->inlen = 0;
1004
1005         ptr = kzalloc(count, GFP_KERNEL);
1006         if (!ptr)
1007                 return -ENOMEM;
1008
1009         if (copy_from_user(ptr, buf, count)) {
1010                 err = -EFAULT;
1011                 goto out;
1012         }
1013         dbg->in_msg = ptr;
1014         dbg->inlen = count;
1015
1016         *pos = count;
1017
1018         return count;
1019
1020 out:
1021         kfree(ptr);
1022         return err;
1023 }
1024
1025 static ssize_t data_read(struct file *filp, char __user *buf, size_t count,
1026                          loff_t *pos)
1027 {
1028         struct mlx5_core_dev *dev = filp->private_data;
1029         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1030         int copy;
1031
1032         if (*pos)
1033                 return 0;
1034
1035         if (!dbg->out_msg)
1036                 return -ENOMEM;
1037
1038         copy = min_t(int, count, dbg->outlen);
1039         if (copy_to_user(buf, dbg->out_msg, copy))
1040                 return -EFAULT;
1041
1042         *pos += copy;
1043
1044         return copy;
1045 }
1046
1047 static const struct file_operations dfops = {
1048         .owner  = THIS_MODULE,
1049         .open   = simple_open,
1050         .write  = data_write,
1051         .read   = data_read,
1052 };
1053
1054 static ssize_t outlen_read(struct file *filp, char __user *buf, size_t count,
1055                            loff_t *pos)
1056 {
1057         struct mlx5_core_dev *dev = filp->private_data;
1058         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1059         char outlen[8];
1060         int err;
1061
1062         if (*pos)
1063                 return 0;
1064
1065         err = snprintf(outlen, sizeof(outlen), "%d", dbg->outlen);
1066         if (err < 0)
1067                 return err;
1068
1069         if (copy_to_user(buf, &outlen, err))
1070                 return -EFAULT;
1071
1072         *pos += err;
1073
1074         return err;
1075 }
1076
1077 static ssize_t outlen_write(struct file *filp, const char __user *buf,
1078                             size_t count, loff_t *pos)
1079 {
1080         struct mlx5_core_dev *dev = filp->private_data;
1081         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1082         char outlen_str[8];
1083         int outlen;
1084         void *ptr;
1085         int err;
1086
1087         if (*pos != 0 || count > 6)
1088                 return -EINVAL;
1089
1090         kfree(dbg->out_msg);
1091         dbg->out_msg = NULL;
1092         dbg->outlen = 0;
1093
1094         if (copy_from_user(outlen_str, buf, count))
1095                 return -EFAULT;
1096
1097         outlen_str[7] = 0;
1098
1099         err = sscanf(outlen_str, "%d", &outlen);
1100         if (err < 0)
1101                 return err;
1102
1103         ptr = kzalloc(outlen, GFP_KERNEL);
1104         if (!ptr)
1105                 return -ENOMEM;
1106
1107         dbg->out_msg = ptr;
1108         dbg->outlen = outlen;
1109
1110         *pos = count;
1111
1112         return count;
1113 }
1114
1115 static const struct file_operations olfops = {
1116         .owner  = THIS_MODULE,
1117         .open   = simple_open,
1118         .write  = outlen_write,
1119         .read   = outlen_read,
1120 };
1121
1122 static void set_wqname(struct mlx5_core_dev *dev)
1123 {
1124         struct mlx5_cmd *cmd = &dev->cmd;
1125
1126         snprintf(cmd->wq_name, sizeof(cmd->wq_name), "mlx5_cmd_%s",
1127                  dev_name(&dev->pdev->dev));
1128 }
1129
1130 static void clean_debug_files(struct mlx5_core_dev *dev)
1131 {
1132         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1133
1134         if (!mlx5_debugfs_root)
1135                 return;
1136
1137         mlx5_cmdif_debugfs_cleanup(dev);
1138         debugfs_remove_recursive(dbg->dbg_root);
1139 }
1140
1141 static int create_debugfs_files(struct mlx5_core_dev *dev)
1142 {
1143         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1144         int err = -ENOMEM;
1145
1146         if (!mlx5_debugfs_root)
1147                 return 0;
1148
1149         dbg->dbg_root = debugfs_create_dir("cmd", dev->priv.dbg_root);
1150         if (!dbg->dbg_root)
1151                 return err;
1152
1153         dbg->dbg_in = debugfs_create_file("in", 0400, dbg->dbg_root,
1154                                           dev, &dfops);
1155         if (!dbg->dbg_in)
1156                 goto err_dbg;
1157
1158         dbg->dbg_out = debugfs_create_file("out", 0200, dbg->dbg_root,
1159                                            dev, &dfops);
1160         if (!dbg->dbg_out)
1161                 goto err_dbg;
1162
1163         dbg->dbg_outlen = debugfs_create_file("out_len", 0600, dbg->dbg_root,
1164                                               dev, &olfops);
1165         if (!dbg->dbg_outlen)
1166                 goto err_dbg;
1167
1168         dbg->dbg_status = debugfs_create_u8("status", 0600, dbg->dbg_root,
1169                                             &dbg->status);
1170         if (!dbg->dbg_status)
1171                 goto err_dbg;
1172
1173         dbg->dbg_run = debugfs_create_file("run", 0200, dbg->dbg_root, dev, &fops);
1174         if (!dbg->dbg_run)
1175                 goto err_dbg;
1176
1177         mlx5_cmdif_debugfs_init(dev);
1178
1179         return 0;
1180
1181 err_dbg:
1182         clean_debug_files(dev);
1183         return err;
1184 }
1185
1186 static void mlx5_cmd_change_mod(struct mlx5_core_dev *dev, int mode)
1187 {
1188         struct mlx5_cmd *cmd = &dev->cmd;
1189         int i;
1190
1191         for (i = 0; i < cmd->max_reg_cmds; i++)
1192                 down(&cmd->sem);
1193         down(&cmd->pages_sem);
1194
1195         cmd->mode = mode;
1196
1197         up(&cmd->pages_sem);
1198         for (i = 0; i < cmd->max_reg_cmds; i++)
1199                 up(&cmd->sem);
1200 }
1201
1202 void mlx5_cmd_use_events(struct mlx5_core_dev *dev)
1203 {
1204         mlx5_cmd_change_mod(dev, CMD_MODE_EVENTS);
1205 }
1206
1207 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev)
1208 {
1209         mlx5_cmd_change_mod(dev, CMD_MODE_POLLING);
1210 }
1211
1212 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg)
1213 {
1214         unsigned long flags;
1215
1216         if (msg->cache) {
1217                 spin_lock_irqsave(&msg->cache->lock, flags);
1218                 list_add_tail(&msg->list, &msg->cache->head);
1219                 spin_unlock_irqrestore(&msg->cache->lock, flags);
1220         } else {
1221                 mlx5_free_cmd_msg(dev, msg);
1222         }
1223 }
1224
1225 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec)
1226 {
1227         struct mlx5_cmd *cmd = &dev->cmd;
1228         struct mlx5_cmd_work_ent *ent;
1229         mlx5_cmd_cbk_t callback;
1230         void *context;
1231         int err;
1232         int i;
1233         s64 ds;
1234         struct mlx5_cmd_stats *stats;
1235         unsigned long flags;
1236         unsigned long vector;
1237
1238         /* there can be at most 32 command queues */
1239         vector = vec & 0xffffffff;
1240         for (i = 0; i < (1 << cmd->log_sz); i++) {
1241                 if (test_bit(i, &vector)) {
1242                         struct semaphore *sem;
1243
1244                         ent = cmd->ent_arr[i];
1245                         if (ent->page_queue)
1246                                 sem = &cmd->pages_sem;
1247                         else
1248                                 sem = &cmd->sem;
1249                         ent->ts2 = ktime_get_ns();
1250                         memcpy(ent->out->first.data, ent->lay->out, sizeof(ent->lay->out));
1251                         dump_command(dev, ent, 0);
1252                         if (!ent->ret) {
1253                                 if (!cmd->checksum_disabled)
1254                                         ent->ret = verify_signature(ent);
1255                                 else
1256                                         ent->ret = 0;
1257                                 if (vec & MLX5_TRIGGERED_CMD_COMP)
1258                                         ent->status = MLX5_DRIVER_STATUS_ABORTED;
1259                                 else
1260                                         ent->status = ent->lay->status_own >> 1;
1261
1262                                 mlx5_core_dbg(dev, "command completed. ret 0x%x, delivery status %s(0x%x)\n",
1263                                               ent->ret, deliv_status_to_str(ent->status), ent->status);
1264                         }
1265                         free_ent(cmd, ent->idx);
1266
1267                         if (ent->callback) {
1268                                 ds = ent->ts2 - ent->ts1;
1269                                 if (ent->op < ARRAY_SIZE(cmd->stats)) {
1270                                         stats = &cmd->stats[ent->op];
1271                                         spin_lock_irqsave(&stats->lock, flags);
1272                                         stats->sum += ds;
1273                                         ++stats->n;
1274                                         spin_unlock_irqrestore(&stats->lock, flags);
1275                                 }
1276
1277                                 callback = ent->callback;
1278                                 context = ent->context;
1279                                 err = ent->ret;
1280                                 if (!err)
1281                                         err = mlx5_copy_from_msg(ent->uout,
1282                                                                  ent->out,
1283                                                                  ent->uout_size);
1284
1285                                 mlx5_free_cmd_msg(dev, ent->out);
1286                                 free_msg(dev, ent->in);
1287
1288                                 err = err ? err : ent->status;
1289                                 free_cmd(ent);
1290                                 callback(err, context);
1291                         } else {
1292                                 complete(&ent->done);
1293                         }
1294                         up(sem);
1295                 }
1296         }
1297 }
1298 EXPORT_SYMBOL(mlx5_cmd_comp_handler);
1299
1300 static int status_to_err(u8 status)
1301 {
1302         return status ? -1 : 0; /* TBD more meaningful codes */
1303 }
1304
1305 static struct mlx5_cmd_msg *alloc_msg(struct mlx5_core_dev *dev, int in_size,
1306                                       gfp_t gfp)
1307 {
1308         struct mlx5_cmd_msg *msg = ERR_PTR(-ENOMEM);
1309         struct mlx5_cmd *cmd = &dev->cmd;
1310         struct cache_ent *ent = NULL;
1311
1312         if (in_size > MED_LIST_SIZE && in_size <= LONG_LIST_SIZE)
1313                 ent = &cmd->cache.large;
1314         else if (in_size > 16 && in_size <= MED_LIST_SIZE)
1315                 ent = &cmd->cache.med;
1316
1317         if (ent) {
1318                 spin_lock_irq(&ent->lock);
1319                 if (!list_empty(&ent->head)) {
1320                         msg = list_entry(ent->head.next, typeof(*msg), list);
1321                         /* For cached lists, we must explicitly state what is
1322                          * the real size
1323                          */
1324                         msg->len = in_size;
1325                         list_del(&msg->list);
1326                 }
1327                 spin_unlock_irq(&ent->lock);
1328         }
1329
1330         if (IS_ERR(msg))
1331                 msg = mlx5_alloc_cmd_msg(dev, gfp, in_size);
1332
1333         return msg;
1334 }
1335
1336 static u16 opcode_from_in(struct mlx5_inbox_hdr *in)
1337 {
1338         return be16_to_cpu(in->opcode);
1339 }
1340
1341 static int is_manage_pages(struct mlx5_inbox_hdr *in)
1342 {
1343         return be16_to_cpu(in->opcode) == MLX5_CMD_OP_MANAGE_PAGES;
1344 }
1345
1346 static int cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1347                     int out_size, mlx5_cmd_cbk_t callback, void *context)
1348 {
1349         struct mlx5_cmd_msg *inb;
1350         struct mlx5_cmd_msg *outb;
1351         int pages_queue;
1352         gfp_t gfp;
1353         int err;
1354         u8 status = 0;
1355         u32 drv_synd;
1356
1357         if (pci_channel_offline(dev->pdev) ||
1358             dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1359                 err = mlx5_internal_err_ret_value(dev, opcode_from_in(in), &drv_synd, &status);
1360                 *get_synd_ptr(out) = cpu_to_be32(drv_synd);
1361                 *get_status_ptr(out) = status;
1362                 return err;
1363         }
1364
1365         pages_queue = is_manage_pages(in);
1366         gfp = callback ? GFP_ATOMIC : GFP_KERNEL;
1367
1368         inb = alloc_msg(dev, in_size, gfp);
1369         if (IS_ERR(inb)) {
1370                 err = PTR_ERR(inb);
1371                 return err;
1372         }
1373
1374         err = mlx5_copy_to_msg(inb, in, in_size);
1375         if (err) {
1376                 mlx5_core_warn(dev, "err %d\n", err);
1377                 goto out_in;
1378         }
1379
1380         outb = mlx5_alloc_cmd_msg(dev, gfp, out_size);
1381         if (IS_ERR(outb)) {
1382                 err = PTR_ERR(outb);
1383                 goto out_in;
1384         }
1385
1386         err = mlx5_cmd_invoke(dev, inb, outb, out, out_size, callback, context,
1387                               pages_queue, &status);
1388         if (err)
1389                 goto out_out;
1390
1391         mlx5_core_dbg(dev, "err %d, status %d\n", err, status);
1392         if (status) {
1393                 err = status_to_err(status);
1394                 goto out_out;
1395         }
1396
1397         if (!callback)
1398                 err = mlx5_copy_from_msg(out, outb, out_size);
1399
1400 out_out:
1401         if (!callback)
1402                 mlx5_free_cmd_msg(dev, outb);
1403
1404 out_in:
1405         if (!callback)
1406                 free_msg(dev, inb);
1407         return err;
1408 }
1409
1410 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1411                   int out_size)
1412 {
1413         return cmd_exec(dev, in, in_size, out, out_size, NULL, NULL);
1414 }
1415 EXPORT_SYMBOL(mlx5_cmd_exec);
1416
1417 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
1418                      void *out, int out_size, mlx5_cmd_cbk_t callback,
1419                      void *context)
1420 {
1421         return cmd_exec(dev, in, in_size, out, out_size, callback, context);
1422 }
1423 EXPORT_SYMBOL(mlx5_cmd_exec_cb);
1424
1425 static void destroy_msg_cache(struct mlx5_core_dev *dev)
1426 {
1427         struct mlx5_cmd *cmd = &dev->cmd;
1428         struct mlx5_cmd_msg *msg;
1429         struct mlx5_cmd_msg *n;
1430
1431         list_for_each_entry_safe(msg, n, &cmd->cache.large.head, list) {
1432                 list_del(&msg->list);
1433                 mlx5_free_cmd_msg(dev, msg);
1434         }
1435
1436         list_for_each_entry_safe(msg, n, &cmd->cache.med.head, list) {
1437                 list_del(&msg->list);
1438                 mlx5_free_cmd_msg(dev, msg);
1439         }
1440 }
1441
1442 static int create_msg_cache(struct mlx5_core_dev *dev)
1443 {
1444         struct mlx5_cmd *cmd = &dev->cmd;
1445         struct mlx5_cmd_msg *msg;
1446         int err;
1447         int i;
1448
1449         spin_lock_init(&cmd->cache.large.lock);
1450         INIT_LIST_HEAD(&cmd->cache.large.head);
1451         spin_lock_init(&cmd->cache.med.lock);
1452         INIT_LIST_HEAD(&cmd->cache.med.head);
1453
1454         for (i = 0; i < NUM_LONG_LISTS; i++) {
1455                 msg = mlx5_alloc_cmd_msg(dev, GFP_KERNEL, LONG_LIST_SIZE);
1456                 if (IS_ERR(msg)) {
1457                         err = PTR_ERR(msg);
1458                         goto ex_err;
1459                 }
1460                 msg->cache = &cmd->cache.large;
1461                 list_add_tail(&msg->list, &cmd->cache.large.head);
1462         }
1463
1464         for (i = 0; i < NUM_MED_LISTS; i++) {
1465                 msg = mlx5_alloc_cmd_msg(dev, GFP_KERNEL, MED_LIST_SIZE);
1466                 if (IS_ERR(msg)) {
1467                         err = PTR_ERR(msg);
1468                         goto ex_err;
1469                 }
1470                 msg->cache = &cmd->cache.med;
1471                 list_add_tail(&msg->list, &cmd->cache.med.head);
1472         }
1473
1474         return 0;
1475
1476 ex_err:
1477         destroy_msg_cache(dev);
1478         return err;
1479 }
1480
1481 static int alloc_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1482 {
1483         struct device *ddev = &dev->pdev->dev;
1484
1485         cmd->cmd_alloc_buf = dma_zalloc_coherent(ddev, MLX5_ADAPTER_PAGE_SIZE,
1486                                                  &cmd->alloc_dma, GFP_KERNEL);
1487         if (!cmd->cmd_alloc_buf)
1488                 return -ENOMEM;
1489
1490         /* make sure it is aligned to 4K */
1491         if (!((uintptr_t)cmd->cmd_alloc_buf & (MLX5_ADAPTER_PAGE_SIZE - 1))) {
1492                 cmd->cmd_buf = cmd->cmd_alloc_buf;
1493                 cmd->dma = cmd->alloc_dma;
1494                 cmd->alloc_size = MLX5_ADAPTER_PAGE_SIZE;
1495                 return 0;
1496         }
1497
1498         dma_free_coherent(ddev, MLX5_ADAPTER_PAGE_SIZE, cmd->cmd_alloc_buf,
1499                           cmd->alloc_dma);
1500         cmd->cmd_alloc_buf = dma_zalloc_coherent(ddev,
1501                                                  2 * MLX5_ADAPTER_PAGE_SIZE - 1,
1502                                                  &cmd->alloc_dma, GFP_KERNEL);
1503         if (!cmd->cmd_alloc_buf)
1504                 return -ENOMEM;
1505
1506         cmd->cmd_buf = PTR_ALIGN(cmd->cmd_alloc_buf, MLX5_ADAPTER_PAGE_SIZE);
1507         cmd->dma = ALIGN(cmd->alloc_dma, MLX5_ADAPTER_PAGE_SIZE);
1508         cmd->alloc_size = 2 * MLX5_ADAPTER_PAGE_SIZE - 1;
1509         return 0;
1510 }
1511
1512 static void free_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1513 {
1514         struct device *ddev = &dev->pdev->dev;
1515
1516         dma_free_coherent(ddev, cmd->alloc_size, cmd->cmd_alloc_buf,
1517                           cmd->alloc_dma);
1518 }
1519
1520 int mlx5_cmd_init(struct mlx5_core_dev *dev)
1521 {
1522         int size = sizeof(struct mlx5_cmd_prot_block);
1523         int align = roundup_pow_of_two(size);
1524         struct mlx5_cmd *cmd = &dev->cmd;
1525         u32 cmd_h, cmd_l;
1526         u16 cmd_if_rev;
1527         int err;
1528         int i;
1529
1530         memset(cmd, 0, sizeof(*cmd));
1531         cmd_if_rev = cmdif_rev(dev);
1532         if (cmd_if_rev != CMD_IF_REV) {
1533                 dev_err(&dev->pdev->dev,
1534                         "Driver cmdif rev(%d) differs from firmware's(%d)\n",
1535                         CMD_IF_REV, cmd_if_rev);
1536                 return -EINVAL;
1537         }
1538
1539         cmd->pool = pci_pool_create("mlx5_cmd", dev->pdev, size, align, 0);
1540         if (!cmd->pool)
1541                 return -ENOMEM;
1542
1543         err = alloc_cmd_page(dev, cmd);
1544         if (err)
1545                 goto err_free_pool;
1546
1547         cmd_l = ioread32be(&dev->iseg->cmdq_addr_l_sz) & 0xff;
1548         cmd->log_sz = cmd_l >> 4 & 0xf;
1549         cmd->log_stride = cmd_l & 0xf;
1550         if (1 << cmd->log_sz > MLX5_MAX_COMMANDS) {
1551                 dev_err(&dev->pdev->dev, "firmware reports too many outstanding commands %d\n",
1552                         1 << cmd->log_sz);
1553                 err = -EINVAL;
1554                 goto err_free_page;
1555         }
1556
1557         if (cmd->log_sz + cmd->log_stride > MLX5_ADAPTER_PAGE_SHIFT) {
1558                 dev_err(&dev->pdev->dev, "command queue size overflow\n");
1559                 err = -EINVAL;
1560                 goto err_free_page;
1561         }
1562
1563         cmd->checksum_disabled = 1;
1564         cmd->max_reg_cmds = (1 << cmd->log_sz) - 1;
1565         cmd->bitmask = (1 << cmd->max_reg_cmds) - 1;
1566
1567         cmd->cmdif_rev = ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
1568         if (cmd->cmdif_rev > CMD_IF_REV) {
1569                 dev_err(&dev->pdev->dev, "driver does not support command interface version. driver %d, firmware %d\n",
1570                         CMD_IF_REV, cmd->cmdif_rev);
1571                 err = -ENOTSUPP;
1572                 goto err_free_page;
1573         }
1574
1575         spin_lock_init(&cmd->alloc_lock);
1576         spin_lock_init(&cmd->token_lock);
1577         for (i = 0; i < ARRAY_SIZE(cmd->stats); i++)
1578                 spin_lock_init(&cmd->stats[i].lock);
1579
1580         sema_init(&cmd->sem, cmd->max_reg_cmds);
1581         sema_init(&cmd->pages_sem, 1);
1582
1583         cmd_h = (u32)((u64)(cmd->dma) >> 32);
1584         cmd_l = (u32)(cmd->dma);
1585         if (cmd_l & 0xfff) {
1586                 dev_err(&dev->pdev->dev, "invalid command queue address\n");
1587                 err = -ENOMEM;
1588                 goto err_free_page;
1589         }
1590
1591         iowrite32be(cmd_h, &dev->iseg->cmdq_addr_h);
1592         iowrite32be(cmd_l, &dev->iseg->cmdq_addr_l_sz);
1593
1594         /* Make sure firmware sees the complete address before we proceed */
1595         wmb();
1596
1597         mlx5_core_dbg(dev, "descriptor at dma 0x%llx\n", (unsigned long long)(cmd->dma));
1598
1599         cmd->mode = CMD_MODE_POLLING;
1600
1601         err = create_msg_cache(dev);
1602         if (err) {
1603                 dev_err(&dev->pdev->dev, "failed to create command cache\n");
1604                 goto err_free_page;
1605         }
1606
1607         set_wqname(dev);
1608         cmd->wq = create_singlethread_workqueue(cmd->wq_name);
1609         if (!cmd->wq) {
1610                 dev_err(&dev->pdev->dev, "failed to create command workqueue\n");
1611                 err = -ENOMEM;
1612                 goto err_cache;
1613         }
1614
1615         err = create_debugfs_files(dev);
1616         if (err) {
1617                 err = -ENOMEM;
1618                 goto err_wq;
1619         }
1620
1621         return 0;
1622
1623 err_wq:
1624         destroy_workqueue(cmd->wq);
1625
1626 err_cache:
1627         destroy_msg_cache(dev);
1628
1629 err_free_page:
1630         free_cmd_page(dev, cmd);
1631
1632 err_free_pool:
1633         pci_pool_destroy(cmd->pool);
1634
1635         return err;
1636 }
1637 EXPORT_SYMBOL(mlx5_cmd_init);
1638
1639 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev)
1640 {
1641         struct mlx5_cmd *cmd = &dev->cmd;
1642
1643         clean_debug_files(dev);
1644         destroy_workqueue(cmd->wq);
1645         destroy_msg_cache(dev);
1646         free_cmd_page(dev, cmd);
1647         pci_pool_destroy(cmd->pool);
1648 }
1649 EXPORT_SYMBOL(mlx5_cmd_cleanup);
1650
1651 static const char *cmd_status_str(u8 status)
1652 {
1653         switch (status) {
1654         case MLX5_CMD_STAT_OK:
1655                 return "OK";
1656         case MLX5_CMD_STAT_INT_ERR:
1657                 return "internal error";
1658         case MLX5_CMD_STAT_BAD_OP_ERR:
1659                 return "bad operation";
1660         case MLX5_CMD_STAT_BAD_PARAM_ERR:
1661                 return "bad parameter";
1662         case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:
1663                 return "bad system state";
1664         case MLX5_CMD_STAT_BAD_RES_ERR:
1665                 return "bad resource";
1666         case MLX5_CMD_STAT_RES_BUSY:
1667                 return "resource busy";
1668         case MLX5_CMD_STAT_LIM_ERR:
1669                 return "limits exceeded";
1670         case MLX5_CMD_STAT_BAD_RES_STATE_ERR:
1671                 return "bad resource state";
1672         case MLX5_CMD_STAT_IX_ERR:
1673                 return "bad index";
1674         case MLX5_CMD_STAT_NO_RES_ERR:
1675                 return "no resources";
1676         case MLX5_CMD_STAT_BAD_INP_LEN_ERR:
1677                 return "bad input length";
1678         case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:
1679                 return "bad output length";
1680         case MLX5_CMD_STAT_BAD_QP_STATE_ERR:
1681                 return "bad QP state";
1682         case MLX5_CMD_STAT_BAD_PKT_ERR:
1683                 return "bad packet (discarded)";
1684         case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:
1685                 return "bad size too many outstanding CQEs";
1686         default:
1687                 return "unknown status";
1688         }
1689 }
1690
1691 static int cmd_status_to_err(u8 status)
1692 {
1693         switch (status) {
1694         case MLX5_CMD_STAT_OK:                          return 0;
1695         case MLX5_CMD_STAT_INT_ERR:                     return -EIO;
1696         case MLX5_CMD_STAT_BAD_OP_ERR:                  return -EINVAL;
1697         case MLX5_CMD_STAT_BAD_PARAM_ERR:               return -EINVAL;
1698         case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:           return -EIO;
1699         case MLX5_CMD_STAT_BAD_RES_ERR:                 return -EINVAL;
1700         case MLX5_CMD_STAT_RES_BUSY:                    return -EBUSY;
1701         case MLX5_CMD_STAT_LIM_ERR:                     return -ENOMEM;
1702         case MLX5_CMD_STAT_BAD_RES_STATE_ERR:           return -EINVAL;
1703         case MLX5_CMD_STAT_IX_ERR:                      return -EINVAL;
1704         case MLX5_CMD_STAT_NO_RES_ERR:                  return -EAGAIN;
1705         case MLX5_CMD_STAT_BAD_INP_LEN_ERR:             return -EIO;
1706         case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:            return -EIO;
1707         case MLX5_CMD_STAT_BAD_QP_STATE_ERR:            return -EINVAL;
1708         case MLX5_CMD_STAT_BAD_PKT_ERR:                 return -EINVAL;
1709         case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:      return -EINVAL;
1710         default:                                        return -EIO;
1711         }
1712 }
1713
1714 /* this will be available till all the commands use set/get macros */
1715 int mlx5_cmd_status_to_err(struct mlx5_outbox_hdr *hdr)
1716 {
1717         if (!hdr->status)
1718                 return 0;
1719
1720         pr_warn("command failed, status %s(0x%x), syndrome 0x%x\n",
1721                 cmd_status_str(hdr->status), hdr->status,
1722                 be32_to_cpu(hdr->syndrome));
1723
1724         return cmd_status_to_err(hdr->status);
1725 }
1726
1727 int mlx5_cmd_status_to_err_v2(void *ptr)
1728 {
1729         u32     syndrome;
1730         u8      status;
1731
1732         status = be32_to_cpu(*(__be32 *)ptr) >> 24;
1733         if (!status)
1734                 return 0;
1735
1736         syndrome = be32_to_cpu(*(__be32 *)(ptr + 4));
1737
1738         pr_warn("command failed, status %s(0x%x), syndrome 0x%x\n",
1739                 cmd_status_str(status), status, syndrome);
1740
1741         return cmd_status_to_err(status);
1742 }