drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include "en.h"
  38 #include "en_tc.h"
  39 #include "eswitch.h"
  40 #include "vxlan.h"
  41
  42 struct mlx5e_rq_param {
  43         u32                     rqc[MLX5_ST_SZ_DW(rqc)];
  44         struct mlx5_wq_param    wq;
  45         bool                    am_enabled;
  46 };
  47
  48 struct mlx5e_sq_param {
  49         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
  50         struct mlx5_wq_param       wq;
  51         u16                        max_inline;
  52         u8                         min_inline_mode;
  53         bool                       icosq;
  54 };
  55
  56 struct mlx5e_cq_param {
  57         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
  58         struct mlx5_wq_param       wq;
  59         u16                        eq_ix;
  60         u8                         cq_period_mode;
  61 };
  62
  63 struct mlx5e_channel_param {
  64         struct mlx5e_rq_param      rq;
  65         struct mlx5e_sq_param      sq;
  66         struct mlx5e_sq_param      icosq;
  67         struct mlx5e_cq_param      rx_cq;
  68         struct mlx5e_cq_param      tx_cq;
  69         struct mlx5e_cq_param      icosq_cq;
  70 };
  71
  72 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
  73 {
  74         struct mlx5_core_dev *mdev = priv->mdev;
  75         u8 port_state;
  76
  77         port_state = mlx5_query_vport_state(mdev,
  78                 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
  79
  80         if (port_state == VPORT_STATE_UP) {
  81                 netdev_info(priv->netdev, "Link up\n");
  82                 netif_carrier_on(priv->netdev);
  83         } else {
  84                 netdev_info(priv->netdev, "Link down\n");
  85                 netif_carrier_off(priv->netdev);
  86         }
  87 }
  88
  89 static void mlx5e_update_carrier_work(struct work_struct *work)
  90 {
  91         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
  92                                                update_carrier_work);
  93
  94         mutex_lock(&priv->state_lock);
  95         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
  96                 mlx5e_update_carrier(priv);
  97         mutex_unlock(&priv->state_lock);
  98 }
  99
 100 static void mlx5e_tx_timeout_work(struct work_struct *work)
 101 {
 102         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 103                                                tx_timeout_work);
 104         int err;
 105
 106         rtnl_lock();
 107         mutex_lock(&priv->state_lock);
 108         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
 109                 goto unlock;
 110         mlx5e_close_locked(priv->netdev);
 111         err = mlx5e_open_locked(priv->netdev);
 112         if (err)
 113                 netdev_err(priv->netdev, "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
 114                            err);
 115 unlock:
 116         mutex_unlock(&priv->state_lock);
 117         rtnl_unlock();
 118 }
 119
 120 static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
 121 {
 122         struct mlx5e_sw_stats *s = &priv->stats.sw;
 123         struct mlx5e_rq_stats *rq_stats;
 124         struct mlx5e_sq_stats *sq_stats;
 125         u64 tx_offload_none = 0;
 126         int i, j;
 127
 128         memset(s, 0, sizeof(*s));
 129         for (i = 0; i < priv->params.num_channels; i++) {
 130                 rq_stats = &priv->channel[i]->rq.stats;
 131
 132                 s->rx_packets   += rq_stats->packets;
 133                 s->rx_bytes     += rq_stats->bytes;
 134                 s->rx_lro_packets += rq_stats->lro_packets;
 135                 s->rx_lro_bytes += rq_stats->lro_bytes;
 136                 s->rx_csum_none += rq_stats->csum_none;
 137                 s->rx_csum_complete += rq_stats->csum_complete;
 138                 s->rx_csum_unnecessary_inner += rq_stats->csum_unnecessary_inner;
 139                 s->rx_wqe_err   += rq_stats->wqe_err;
 140                 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
 141                 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
 142                 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
 143                 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
 144                 s->rx_cache_reuse += rq_stats->cache_reuse;
 145                 s->rx_cache_full  += rq_stats->cache_full;
 146                 s->rx_cache_empty += rq_stats->cache_empty;
 147                 s->rx_cache_busy  += rq_stats->cache_busy;
 148
 149                 for (j = 0; j < priv->params.num_tc; j++) {
 150                         sq_stats = &priv->channel[i]->sq[j].stats;
 151
 152                         s->tx_packets           += sq_stats->packets;
 153                         s->tx_bytes             += sq_stats->bytes;
 154                         s->tx_tso_packets       += sq_stats->tso_packets;
 155                         s->tx_tso_bytes         += sq_stats->tso_bytes;
 156                         s->tx_tso_inner_packets += sq_stats->tso_inner_packets;
 157                         s->tx_tso_inner_bytes   += sq_stats->tso_inner_bytes;
 158                         s->tx_queue_stopped     += sq_stats->stopped;
 159                         s->tx_queue_wake        += sq_stats->wake;
 160                         s->tx_queue_dropped     += sq_stats->dropped;
 161                         s->tx_xmit_more         += sq_stats->xmit_more;
 162                         s->tx_csum_partial_inner += sq_stats->csum_partial_inner;
 163                         tx_offload_none         += sq_stats->csum_none;
 164                 }
 165         }
 166
 167         /* Update calculated offload counters */
 168         s->tx_csum_partial = s->tx_packets - tx_offload_none - s->tx_csum_partial_inner;
 169         s->rx_csum_unnecessary = s->rx_packets - s->rx_csum_none - s->rx_csum_complete;
 170
 171         s->link_down_events_phy = MLX5_GET(ppcnt_reg,
 172                                 priv->stats.pport.phy_counters,
 173                                 counter_set.phys_layer_cntrs.link_down_events);
 174 }
 175
 176 static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
 177 {
 178         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
 179         u32 *out = (u32 *)priv->stats.vport.query_vport_out;
 180         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {0};
 181         struct mlx5_core_dev *mdev = priv->mdev;
 182
 183         MLX5_SET(query_vport_counter_in, in, opcode,
 184                  MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 185         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 186         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 187
 188         memset(out, 0, outlen);
 189         mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
 190 }
 191
 192 static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
 193 {
 194         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
 195         struct mlx5_core_dev *mdev = priv->mdev;
 196         int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
 197         int prio;
 198         void *out;
 199         u32 *in;
 200
 201         in = mlx5_vzalloc(sz);
 202         if (!in)
 203                 goto free_out;
 204
 205         MLX5_SET(ppcnt_reg, in, local_port, 1);
 206
 207         out = pstats->IEEE_802_3_counters;
 208         MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
 209         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 210
 211         out = pstats->RFC_2863_counters;
 212         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
 213         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 214
 215         out = pstats->RFC_2819_counters;
 216         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
 217         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 218
 219         out = pstats->phy_counters;
 220         MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
 221         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 222
 223         MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
 224         for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
 225                 out = pstats->per_prio_counters[prio];
 226                 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
 227                 mlx5_core_access_reg(mdev, in, sz, out, sz,
 228                                      MLX5_REG_PPCNT, 0, 0);
 229         }
 230
 231 free_out:
 232         kvfree(in);
 233 }
 234
 235 static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
 236 {
 237         struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
 238
 239         if (!priv->q_counter)
 240                 return;
 241
 242         mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
 243                                       &qcnt->rx_out_of_buffer);
 244 }
 245
 246 void mlx5e_update_stats(struct mlx5e_priv *priv)
 247 {
 248         mlx5e_update_q_counter(priv);
 249         mlx5e_update_vport_counters(priv);
 250         mlx5e_update_pport_counters(priv);
 251         mlx5e_update_sw_counters(priv);
 252 }
 253
 254 void mlx5e_update_stats_work(struct work_struct *work)
 255 {
 256         struct delayed_work *dwork = to_delayed_work(work);
 257         struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
 258                                                update_stats_work);
 259         mutex_lock(&priv->state_lock);
 260         if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
 261                 priv->profile->update_stats(priv);
 262                 queue_delayed_work(priv->wq, dwork,
 263                                    msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
 264         }
 265         mutex_unlock(&priv->state_lock);
 266 }
 267
 268 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 269                               enum mlx5_dev_event event, unsigned long param)
 270 {
 271         struct mlx5e_priv *priv = vpriv;
 272
 273         if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
 274                 return;
 275
 276         switch (event) {
 277         case MLX5_DEV_EVENT_PORT_UP:
 278         case MLX5_DEV_EVENT_PORT_DOWN:
 279                 queue_work(priv->wq, &priv->update_carrier_work);
 280                 break;
 281
 282         default:
 283                 break;
 284         }
 285 }
 286
 287 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 288 {
 289         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
 290 }
 291
 292 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 293 {
 294         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
 295         synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
 296 }
 297
 298 #define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 299 #define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 300
 301 static inline int mlx5e_get_wqe_mtt_sz(void)
 302 {
 303         /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes.
 304          * To avoid copying garbage after the mtt array, we allocate
 305          * a little more.
 306          */
 307         return ALIGN(MLX5_MPWRQ_PAGES_PER_WQE * sizeof(__be64),
 308                      MLX5_UMR_MTT_ALIGNMENT);
 309 }
 310
 311 static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq, struct mlx5e_sq *sq,
 312                                        struct mlx5e_umr_wqe *wqe, u16 ix)
 313 {
 314         struct mlx5_wqe_ctrl_seg      *cseg = &wqe->ctrl;
 315         struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
 316         struct mlx5_wqe_data_seg      *dseg = &wqe->data;
 317         struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
 318         u8 ds_cnt = DIV_ROUND_UP(sizeof(*wqe), MLX5_SEND_WQE_DS);
 319         u32 umr_wqe_mtt_offset = mlx5e_get_wqe_mtt_offset(rq, ix);
 320
 321         cseg->qpn_ds    = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
 322                                       ds_cnt);
 323         cseg->fm_ce_se  = MLX5_WQE_CTRL_CQ_UPDATE;
 324         cseg->imm       = rq->mkey_be;
 325
 326         ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN;
 327         ucseg->klm_octowords =
 328                 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
 329         ucseg->bsf_octowords =
 330                 cpu_to_be16(MLX5_MTT_OCTW(umr_wqe_mtt_offset));
 331         ucseg->mkey_mask     = cpu_to_be64(MLX5_MKEY_MASK_FREE);
 332
 333         dseg->lkey = sq->mkey_be;
 334         dseg->addr = cpu_to_be64(wi->umr.mtt_addr);
 335 }
 336
 337 static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
 338                                      struct mlx5e_channel *c)
 339 {
 340         int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 341         int mtt_sz = mlx5e_get_wqe_mtt_sz();
 342         int mtt_alloc = mtt_sz + MLX5_UMR_ALIGN - 1;
 343         int i;
 344
 345         rq->mpwqe.info = kzalloc_node(wq_sz * sizeof(*rq->mpwqe.info),
 346                                       GFP_KERNEL, cpu_to_node(c->cpu));
 347         if (!rq->mpwqe.info)
 348                 goto err_out;
 349
 350         /* We allocate more than mtt_sz as we will align the pointer */
 351         rq->mpwqe.mtt_no_align = kzalloc_node(mtt_alloc * wq_sz, GFP_KERNEL,
 352                                         cpu_to_node(c->cpu));
 353         if (unlikely(!rq->mpwqe.mtt_no_align))
 354                 goto err_free_wqe_info;
 355
 356         for (i = 0; i < wq_sz; i++) {
 357                 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
 358
 359                 wi->umr.mtt = PTR_ALIGN(rq->mpwqe.mtt_no_align + i * mtt_alloc,
 360                                         MLX5_UMR_ALIGN);
 361                 wi->umr.mtt_addr = dma_map_single(c->pdev, wi->umr.mtt, mtt_sz,
 362                                                   PCI_DMA_TODEVICE);
 363                 if (unlikely(dma_mapping_error(c->pdev, wi->umr.mtt_addr)))
 364                         goto err_unmap_mtts;
 365
 366                 mlx5e_build_umr_wqe(rq, &c->icosq, &wi->umr.wqe, i);
 367         }
 368
 369         return 0;
 370
 371 err_unmap_mtts:
 372         while (--i >= 0) {
 373                 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
 374
 375                 dma_unmap_single(c->pdev, wi->umr.mtt_addr, mtt_sz,
 376                                  PCI_DMA_TODEVICE);
 377         }
 378         kfree(rq->mpwqe.mtt_no_align);
 379 err_free_wqe_info:
 380         kfree(rq->mpwqe.info);
 381
 382 err_out:
 383         return -ENOMEM;
 384 }
 385
 386 static void mlx5e_rq_free_mpwqe_info(struct mlx5e_rq *rq)
 387 {
 388         int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 389         int mtt_sz = mlx5e_get_wqe_mtt_sz();
 390         int i;
 391
 392         for (i = 0; i < wq_sz; i++) {
 393                 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[i];
 394
 395                 dma_unmap_single(rq->pdev, wi->umr.mtt_addr, mtt_sz,
 396                                  PCI_DMA_TODEVICE);
 397         }
 398         kfree(rq->mpwqe.mtt_no_align);
 399         kfree(rq->mpwqe.info);
 400 }
 401
 402 static int mlx5e_create_rq(struct mlx5e_channel *c,
 403                            struct mlx5e_rq_param *param,
 404                            struct mlx5e_rq *rq)
 405 {
 406         struct mlx5e_priv *priv = c->priv;
 407         struct mlx5_core_dev *mdev = priv->mdev;
 408         void *rqc = param->rqc;
 409         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 410         u32 byte_count;
 411         u32 frag_sz;
 412         int npages;
 413         int wq_sz;
 414         int err;
 415         int i;
 416
 417         param->wq.db_numa_node = cpu_to_node(c->cpu);
 418
 419         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
 420                                 &rq->wq_ctrl);
 421         if (err)
 422                 return err;
 423
 424         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
 425
 426         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 427
 428         rq->wq_type = priv->params.rq_wq_type;
 429         rq->pdev    = c->pdev;
 430         rq->netdev  = c->netdev;
 431         rq->tstamp  = &priv->tstamp;
 432         rq->channel = c;
 433         rq->ix      = c->ix;
 434         rq->priv    = c->priv;
 435
 436         switch (priv->params.rq_wq_type) {
 437         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 438                 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_mpwrq;
 439                 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
 440                 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
 441
 442                 rq->mpwqe.mtt_offset = c->ix *
 443                         MLX5E_REQUIRED_MTTS(1, BIT(priv->params.log_rq_size));
 444
 445                 rq->mpwqe_stride_sz = BIT(priv->params.mpwqe_log_stride_sz);
 446                 rq->mpwqe_num_strides = BIT(priv->params.mpwqe_log_num_strides);
 447
 448                 rq->buff.wqe_sz = rq->mpwqe_stride_sz * rq->mpwqe_num_strides;
 449                 byte_count = rq->buff.wqe_sz;
 450                 rq->mkey_be = cpu_to_be32(c->priv->umr_mkey.key);
 451                 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
 452                 if (err)
 453                         goto err_rq_wq_destroy;
 454                 break;
 455         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 456                 rq->dma_info = kzalloc_node(wq_sz * sizeof(*rq->dma_info),
 457                                             GFP_KERNEL, cpu_to_node(c->cpu));
 458                 if (!rq->dma_info) {
 459                         err = -ENOMEM;
 460                         goto err_rq_wq_destroy;
 461                 }
 462
 463                 rq->handle_rx_cqe = mlx5e_handle_rx_cqe;
 464                 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
 465                 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
 466
 467                 rq->buff.wqe_sz = (priv->params.lro_en) ?
 468                                 priv->params.lro_wqe_sz :
 469                                 MLX5E_SW2HW_MTU(priv->netdev->mtu);
 470                 byte_count = rq->buff.wqe_sz;
 471
 472                 /* calc the required page order */
 473                 frag_sz = MLX5_RX_HEADROOM +
 474                           byte_count /* packet data */ +
 475                           SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
 476                 frag_sz = SKB_DATA_ALIGN(frag_sz);
 477
 478                 npages = DIV_ROUND_UP(frag_sz, PAGE_SIZE);
 479                 rq->buff.page_order = order_base_2(npages);
 480
 481                 byte_count |= MLX5_HW_START_PADDING;
 482                 rq->mkey_be = c->mkey_be;
 483         }
 484
 485         for (i = 0; i < wq_sz; i++) {
 486                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
 487
 488                 wqe->data.byte_count = cpu_to_be32(byte_count);
 489                 wqe->data.lkey = rq->mkey_be;
 490         }
 491
 492         INIT_WORK(&rq->am.work, mlx5e_rx_am_work);
 493         rq->am.mode = priv->params.rx_cq_period_mode;
 494
 495         rq->page_cache.head = 0;
 496         rq->page_cache.tail = 0;
 497
 498         return 0;
 499
 500 err_rq_wq_destroy:
 501         mlx5_wq_destroy(&rq->wq_ctrl);
 502
 503         return err;
 504 }
 505
 506 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 507 {
 508         int i;
 509
 510         switch (rq->wq_type) {
 511         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 512                 mlx5e_rq_free_mpwqe_info(rq);
 513                 break;
 514         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 515                 kfree(rq->dma_info);
 516         }
 517
 518         for (i = rq->page_cache.head; i != rq->page_cache.tail;
 519              i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
 520                 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
 521
 522                 mlx5e_page_release(rq, dma_info, false);
 523         }
 524         mlx5_wq_destroy(&rq->wq_ctrl);
 525 }
 526
 527 static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 528 {
 529         struct mlx5e_priv *priv = rq->priv;
 530         struct mlx5_core_dev *mdev = priv->mdev;
 531
 532         void *in;
 533         void *rqc;
 534         void *wq;
 535         int inlen;
 536         int err;
 537
 538         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 539                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 540         in = mlx5_vzalloc(inlen);
 541         if (!in)
 542                 return -ENOMEM;
 543
 544         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 545         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 546
 547         memcpy(rqc, param->rqc, sizeof(param->rqc));
 548
 549         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 550         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 551         MLX5_SET(rqc,  rqc, vsd, priv->params.vlan_strip_disable);
 552         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 553                                                 MLX5_ADAPTER_PAGE_SHIFT);
 554         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 555
 556         mlx5_fill_page_array(&rq->wq_ctrl.buf,
 557                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 558
 559         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 560
 561         kvfree(in);
 562
 563         return err;
 564 }
 565
 566 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
 567                                  int next_state)
 568 {
 569         struct mlx5e_channel *c = rq->channel;
 570         struct mlx5e_priv *priv = c->priv;
 571         struct mlx5_core_dev *mdev = priv->mdev;
 572
 573         void *in;
 574         void *rqc;
 575         int inlen;
 576         int err;
 577
 578         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 579         in = mlx5_vzalloc(inlen);
 580         if (!in)
 581                 return -ENOMEM;
 582
 583         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 584
 585         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 586         MLX5_SET(rqc, rqc, state, next_state);
 587
 588         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 589
 590         kvfree(in);
 591
 592         return err;
 593 }
 594
 595 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
 596 {
 597         struct mlx5e_channel *c = rq->channel;
 598         struct mlx5e_priv *priv = c->priv;
 599         struct mlx5_core_dev *mdev = priv->mdev;
 600
 601         void *in;
 602         void *rqc;
 603         int inlen;
 604         int err;
 605
 606         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 607         in = mlx5_vzalloc(inlen);
 608         if (!in)
 609                 return -ENOMEM;
 610
 611         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 612
 613         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 614         MLX5_SET64(modify_rq_in, in, modify_bitmask,
 615                    MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
 616         MLX5_SET(rqc, rqc, vsd, vsd);
 617         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 618
 619         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 620
 621         kvfree(in);
 622
 623         return err;
 624 }
 625
 626 static void mlx5e_disable_rq(struct mlx5e_rq *rq)
 627 {
 628         mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
 629 }
 630
 631 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
 632 {
 633         unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
 634         struct mlx5e_channel *c = rq->channel;
 635         struct mlx5e_priv *priv = c->priv;
 636         struct mlx5_wq_ll *wq = &rq->wq;
 637
 638         while (time_before(jiffies, exp_time)) {
 639                 if (wq->cur_sz >= priv->params.min_rx_wqes)
 640                         return 0;
 641
 642                 msleep(20);
 643         }
 644
 645         return -ETIMEDOUT;
 646 }
 647
 648 static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
 649 {
 650         struct mlx5_wq_ll *wq = &rq->wq;
 651         struct mlx5e_rx_wqe *wqe;
 652         __be16 wqe_ix_be;
 653         u16 wqe_ix;
 654
 655         /* UMR WQE (if in progress) is always at wq->head */
 656         if (test_bit(MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS, &rq->state))
 657                 mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]);
 658
 659         while (!mlx5_wq_ll_is_empty(wq)) {
 660                 wqe_ix_be = *wq->tail_next;
 661                 wqe_ix    = be16_to_cpu(wqe_ix_be);
 662                 wqe       = mlx5_wq_ll_get_wqe(&rq->wq, wqe_ix);
 663                 rq->dealloc_wqe(rq, wqe_ix);
 664                 mlx5_wq_ll_pop(&rq->wq, wqe_ix_be,
 665                                &wqe->next.next_wqe_index);
 666         }
 667 }
 668
 669 static int mlx5e_open_rq(struct mlx5e_channel *c,
 670                          struct mlx5e_rq_param *param,
 671                          struct mlx5e_rq *rq)
 672 {
 673         struct mlx5e_sq *sq = &c->icosq;
 674         u16 pi = sq->pc & sq->wq.sz_m1;
 675         int err;
 676
 677         err = mlx5e_create_rq(c, param, rq);
 678         if (err)
 679                 return err;
 680
 681         err = mlx5e_enable_rq(rq, param);
 682         if (err)
 683                 goto err_destroy_rq;
 684
 685         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 686         if (err)
 687                 goto err_disable_rq;
 688
 689         if (param->am_enabled)
 690                 set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
 691
 692         sq->ico_wqe_info[pi].opcode     = MLX5_OPCODE_NOP;
 693         sq->ico_wqe_info[pi].num_wqebbs = 1;
 694         mlx5e_send_nop(sq, true); /* trigger mlx5e_post_rx_wqes() */
 695
 696         return 0;
 697
 698 err_disable_rq:
 699         mlx5e_disable_rq(rq);
 700 err_destroy_rq:
 701         mlx5e_destroy_rq(rq);
 702
 703         return err;
 704 }
 705
 706 static void mlx5e_close_rq(struct mlx5e_rq *rq)
 707 {
 708         set_bit(MLX5E_RQ_STATE_FLUSH, &rq->state);
 709         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 710         cancel_work_sync(&rq->am.work);
 711
 712         mlx5e_disable_rq(rq);
 713         mlx5e_free_rx_descs(rq);
 714         mlx5e_destroy_rq(rq);
 715 }
 716
 717 static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
 718 {
 719         kfree(sq->wqe_info);
 720         kfree(sq->dma_fifo);
 721         kfree(sq->skb);
 722 }
 723
 724 static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
 725 {
 726         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 727         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
 728
 729         sq->skb = kzalloc_node(wq_sz * sizeof(*sq->skb), GFP_KERNEL, numa);
 730         sq->dma_fifo = kzalloc_node(df_sz * sizeof(*sq->dma_fifo), GFP_KERNEL,
 731                                     numa);
 732         sq->wqe_info = kzalloc_node(wq_sz * sizeof(*sq->wqe_info), GFP_KERNEL,
 733                                     numa);
 734
 735         if (!sq->skb || !sq->dma_fifo || !sq->wqe_info) {
 736                 mlx5e_free_sq_db(sq);
 737                 return -ENOMEM;
 738         }
 739
 740         sq->dma_fifo_mask = df_sz - 1;
 741
 742         return 0;
 743 }
 744
 745 static int mlx5e_create_sq(struct mlx5e_channel *c,
 746                            int tc,
 747                            struct mlx5e_sq_param *param,
 748                            struct mlx5e_sq *sq)
 749 {
 750         struct mlx5e_priv *priv = c->priv;
 751         struct mlx5_core_dev *mdev = priv->mdev;
 752
 753         void *sqc = param->sqc;
 754         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
 755         int err;
 756
 757         err = mlx5_alloc_map_uar(mdev, &sq->uar, !!MLX5_CAP_GEN(mdev, bf));
 758         if (err)
 759                 return err;
 760
 761         param->wq.db_numa_node = cpu_to_node(c->cpu);
 762
 763         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
 764                                  &sq->wq_ctrl);
 765         if (err)
 766                 goto err_unmap_free_uar;
 767
 768         sq->wq.db       = &sq->wq.db[MLX5_SND_DBR];
 769         if (sq->uar.bf_map) {
 770                 set_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state);
 771                 sq->uar_map = sq->uar.bf_map;
 772         } else {
 773                 sq->uar_map = sq->uar.map;
 774         }
 775         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
 776         sq->max_inline  = param->max_inline;
 777         sq->min_inline_mode =
 778                 MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5E_INLINE_MODE_VPORT_CONTEXT ?
 779                 param->min_inline_mode : 0;
 780
 781         err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
 782         if (err)
 783                 goto err_sq_wq_destroy;
 784
 785         if (param->icosq) {
 786                 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 787
 788                 sq->ico_wqe_info = kzalloc_node(sizeof(*sq->ico_wqe_info) *
 789                                                 wq_sz,
 790                                                 GFP_KERNEL,
 791                                                 cpu_to_node(c->cpu));
 792                 if (!sq->ico_wqe_info) {
 793                         err = -ENOMEM;
 794                         goto err_free_sq_db;
 795                 }
 796         } else {
 797                 int txq_ix;
 798
 799                 txq_ix = c->ix + tc * priv->params.num_channels;
 800                 sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
 801                 priv->txq_to_sq_map[txq_ix] = sq;
 802         }
 803
 804         sq->pdev      = c->pdev;
 805         sq->tstamp    = &priv->tstamp;
 806         sq->mkey_be   = c->mkey_be;
 807         sq->channel   = c;
 808         sq->tc        = tc;
 809         sq->edge      = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
 810         sq->bf_budget = MLX5E_SQ_BF_BUDGET;
 811
 812         return 0;
 813
 814 err_free_sq_db:
 815         mlx5e_free_sq_db(sq);
 816
 817 err_sq_wq_destroy:
 818         mlx5_wq_destroy(&sq->wq_ctrl);
 819
 820 err_unmap_free_uar:
 821         mlx5_unmap_free_uar(mdev, &sq->uar);
 822
 823         return err;
 824 }
 825
 826 static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
 827 {
 828         struct mlx5e_channel *c = sq->channel;
 829         struct mlx5e_priv *priv = c->priv;
 830
 831         kfree(sq->ico_wqe_info);
 832         mlx5e_free_sq_db(sq);
 833         mlx5_wq_destroy(&sq->wq_ctrl);
 834         mlx5_unmap_free_uar(priv->mdev, &sq->uar);
 835 }
 836
 837 static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
 838 {
 839         struct mlx5e_channel *c = sq->channel;
 840         struct mlx5e_priv *priv = c->priv;
 841         struct mlx5_core_dev *mdev = priv->mdev;
 842
 843         void *in;
 844         void *sqc;
 845         void *wq;
 846         int inlen;
 847         int err;
 848
 849         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
 850                 sizeof(u64) * sq->wq_ctrl.buf.npages;
 851         in = mlx5_vzalloc(inlen);
 852         if (!in)
 853                 return -ENOMEM;
 854
 855         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
 856         wq = MLX5_ADDR_OF(sqc, sqc, wq);
 857
 858         memcpy(sqc, param->sqc, sizeof(param->sqc));
 859
 860         MLX5_SET(sqc,  sqc, tis_num_0, param->icosq ? 0 : priv->tisn[sq->tc]);
 861         MLX5_SET(sqc,  sqc, cqn,                sq->cq.mcq.cqn);
 862         MLX5_SET(sqc,  sqc, min_wqe_inline_mode, sq->min_inline_mode);
 863         MLX5_SET(sqc,  sqc, state,              MLX5_SQC_STATE_RST);
 864         MLX5_SET(sqc,  sqc, tis_lst_sz,         param->icosq ? 0 : 1);
 865         MLX5_SET(sqc,  sqc, flush_in_error_en,  1);
 866
 867         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
 868         MLX5_SET(wq,   wq, uar_page,      sq->uar.index);
 869         MLX5_SET(wq,   wq, log_wq_pg_sz,  sq->wq_ctrl.buf.page_shift -
 870                                           MLX5_ADAPTER_PAGE_SHIFT);
 871         MLX5_SET64(wq, wq, dbr_addr,      sq->wq_ctrl.db.dma);
 872
 873         mlx5_fill_page_array(&sq->wq_ctrl.buf,
 874                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 875
 876         err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
 877
 878         kvfree(in);
 879
 880         return err;
 881 }
 882
 883 static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state,
 884                            int next_state, bool update_rl, int rl_index)
 885 {
 886         struct mlx5e_channel *c = sq->channel;
 887         struct mlx5e_priv *priv = c->priv;
 888         struct mlx5_core_dev *mdev = priv->mdev;
 889
 890         void *in;
 891         void *sqc;
 892         int inlen;
 893         int err;
 894
 895         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
 896         in = mlx5_vzalloc(inlen);
 897         if (!in)
 898                 return -ENOMEM;
 899
 900         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
 901
 902         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
 903         MLX5_SET(sqc, sqc, state, next_state);
 904         if (update_rl && next_state == MLX5_SQC_STATE_RDY) {
 905                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
 906                 MLX5_SET(sqc,  sqc, packet_pacing_rate_limit_index, rl_index);
 907         }
 908
 909         err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
 910
 911         kvfree(in);
 912
 913         return err;
 914 }
 915
 916 static void mlx5e_disable_sq(struct mlx5e_sq *sq)
 917 {
 918         struct mlx5e_channel *c = sq->channel;
 919         struct mlx5e_priv *priv = c->priv;
 920         struct mlx5_core_dev *mdev = priv->mdev;
 921
 922         mlx5_core_destroy_sq(mdev, sq->sqn);
 923         if (sq->rate_limit)
 924                 mlx5_rl_remove_rate(mdev, sq->rate_limit);
 925 }
 926
 927 static int mlx5e_open_sq(struct mlx5e_channel *c,
 928                          int tc,
 929                          struct mlx5e_sq_param *param,
 930                          struct mlx5e_sq *sq)
 931 {
 932         int err;
 933
 934         err = mlx5e_create_sq(c, tc, param, sq);
 935         if (err)
 936                 return err;
 937
 938         err = mlx5e_enable_sq(sq, param);
 939         if (err)
 940                 goto err_destroy_sq;
 941
 942         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY,
 943                               false, 0);
 944         if (err)
 945                 goto err_disable_sq;
 946
 947         if (sq->txq) {
 948                 netdev_tx_reset_queue(sq->txq);
 949                 netif_tx_start_queue(sq->txq);
 950         }
 951
 952         return 0;
 953
 954 err_disable_sq:
 955         mlx5e_disable_sq(sq);
 956 err_destroy_sq:
 957         mlx5e_destroy_sq(sq);
 958
 959         return err;
 960 }
 961
 962 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
 963 {
 964         __netif_tx_lock_bh(txq);
 965         netif_tx_stop_queue(txq);
 966         __netif_tx_unlock_bh(txq);
 967 }
 968
 969 static void mlx5e_close_sq(struct mlx5e_sq *sq)
 970 {
 971         set_bit(MLX5E_SQ_STATE_FLUSH, &sq->state);
 972         /* prevent netif_tx_wake_queue */
 973         napi_synchronize(&sq->channel->napi);
 974
 975         if (sq->txq) {
 976                 netif_tx_disable_queue(sq->txq);
 977
 978                 /* last doorbell out, godspeed .. */
 979                 if (mlx5e_sq_has_room_for(sq, 1))
 980                         mlx5e_send_nop(sq, true);
 981         }
 982
 983         mlx5e_disable_sq(sq);
 984         mlx5e_free_tx_descs(sq);
 985         mlx5e_destroy_sq(sq);
 986 }
 987
 988 static int mlx5e_create_cq(struct mlx5e_channel *c,
 989                            struct mlx5e_cq_param *param,
 990                            struct mlx5e_cq *cq)
 991 {
 992         struct mlx5e_priv *priv = c->priv;
 993         struct mlx5_core_dev *mdev = priv->mdev;
 994         struct mlx5_core_cq *mcq = &cq->mcq;
 995         int eqn_not_used;
 996         unsigned int irqn;
 997         int err;
 998         u32 i;
 999
1000         param->wq.buf_numa_node = cpu_to_node(c->cpu);
1001         param->wq.db_numa_node  = cpu_to_node(c->cpu);
1002         param->eq_ix   = c->ix;
1003
1004         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1005                                &cq->wq_ctrl);
1006         if (err)
1007                 return err;
1008
1009         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1010
1011         cq->napi        = &c->napi;
1012
1013         mcq->cqe_sz     = 64;
1014         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1015         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1016         *mcq->set_ci_db = 0;
1017         *mcq->arm_db    = 0;
1018         mcq->vector     = param->eq_ix;
1019         mcq->comp       = mlx5e_completion_event;
1020         mcq->event      = mlx5e_cq_error_event;
1021         mcq->irqn       = irqn;
1022         mcq->uar        = &mdev->mlx5e_res.cq_uar;
1023
1024         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1025                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1026
1027                 cqe->op_own = 0xf1;
1028         }
1029
1030         cq->channel = c;
1031         cq->priv = priv;
1032
1033         return 0;
1034 }
1035
1036 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1037 {
1038         mlx5_wq_destroy(&cq->wq_ctrl);
1039 }
1040
1041 static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1042 {
1043         struct mlx5e_priv *priv = cq->priv;
1044         struct mlx5_core_dev *mdev = priv->mdev;
1045         struct mlx5_core_cq *mcq = &cq->mcq;
1046
1047         void *in;
1048         void *cqc;
1049         int inlen;
1050         unsigned int irqn_not_used;
1051         int eqn;
1052         int err;
1053
1054         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1055                 sizeof(u64) * cq->wq_ctrl.buf.npages;
1056         in = mlx5_vzalloc(inlen);
1057         if (!in)
1058                 return -ENOMEM;
1059
1060         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1061
1062         memcpy(cqc, param->cqc, sizeof(param->cqc));
1063
1064         mlx5_fill_page_array(&cq->wq_ctrl.buf,
1065                              (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1066
1067         mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1068
1069         MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
1070         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
1071         MLX5_SET(cqc,   cqc, uar_page,      mcq->uar->index);
1072         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1073                                             MLX5_ADAPTER_PAGE_SHIFT);
1074         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
1075
1076         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1077
1078         kvfree(in);
1079
1080         if (err)
1081                 return err;
1082
1083         mlx5e_cq_arm(cq);
1084
1085         return 0;
1086 }
1087
1088 static void mlx5e_disable_cq(struct mlx5e_cq *cq)
1089 {
1090         struct mlx5e_priv *priv = cq->priv;
1091         struct mlx5_core_dev *mdev = priv->mdev;
1092
1093         mlx5_core_destroy_cq(mdev, &cq->mcq);
1094 }
1095
1096 static int mlx5e_open_cq(struct mlx5e_channel *c,
1097                          struct mlx5e_cq_param *param,
1098                          struct mlx5e_cq *cq,
1099                          struct mlx5e_cq_moder moderation)
1100 {
1101         int err;
1102         struct mlx5e_priv *priv = c->priv;
1103         struct mlx5_core_dev *mdev = priv->mdev;
1104
1105         err = mlx5e_create_cq(c, param, cq);
1106         if (err)
1107                 return err;
1108
1109         err = mlx5e_enable_cq(cq, param);
1110         if (err)
1111                 goto err_destroy_cq;
1112
1113         if (MLX5_CAP_GEN(mdev, cq_moderation))
1114                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
1115                                                moderation.usec,
1116                                                moderation.pkts);
1117         return 0;
1118
1119 err_destroy_cq:
1120         mlx5e_destroy_cq(cq);
1121
1122         return err;
1123 }
1124
1125 static void mlx5e_close_cq(struct mlx5e_cq *cq)
1126 {
1127         mlx5e_disable_cq(cq);
1128         mlx5e_destroy_cq(cq);
1129 }
1130
1131 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1132 {
1133         return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1134 }
1135
1136 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1137                              struct mlx5e_channel_param *cparam)
1138 {
1139         struct mlx5e_priv *priv = c->priv;
1140         int err;
1141         int tc;
1142
1143         for (tc = 0; tc < c->num_tc; tc++) {
1144                 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
1145                                     priv->params.tx_cq_moderation);
1146                 if (err)
1147                         goto err_close_tx_cqs;
1148         }
1149
1150         return 0;
1151
1152 err_close_tx_cqs:
1153         for (tc--; tc >= 0; tc--)
1154                 mlx5e_close_cq(&c->sq[tc].cq);
1155
1156         return err;
1157 }
1158
1159 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1160 {
1161         int tc;
1162
1163         for (tc = 0; tc < c->num_tc; tc++)
1164                 mlx5e_close_cq(&c->sq[tc].cq);
1165 }
1166
1167 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1168                           struct mlx5e_channel_param *cparam)
1169 {
1170         int err;
1171         int tc;
1172
1173         for (tc = 0; tc < c->num_tc; tc++) {
1174                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1175                 if (err)
1176                         goto err_close_sqs;
1177         }
1178
1179         return 0;
1180
1181 err_close_sqs:
1182         for (tc--; tc >= 0; tc--)
1183                 mlx5e_close_sq(&c->sq[tc]);
1184
1185         return err;
1186 }
1187
1188 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1189 {
1190         int tc;
1191
1192         for (tc = 0; tc < c->num_tc; tc++)
1193                 mlx5e_close_sq(&c->sq[tc]);
1194 }
1195
1196 static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
1197 {
1198         int i;
1199
1200         for (i = 0; i < priv->profile->max_tc; i++)
1201                 priv->channeltc_to_txq_map[ix][i] =
1202                         ix + i * priv->params.num_channels;
1203 }
1204
1205 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1206                                 struct mlx5e_sq *sq, u32 rate)
1207 {
1208         struct mlx5e_priv *priv = netdev_priv(dev);
1209         struct mlx5_core_dev *mdev = priv->mdev;
1210         u16 rl_index = 0;
1211         int err;
1212
1213         if (rate == sq->rate_limit)
1214                 /* nothing to do */
1215                 return 0;
1216
1217         if (sq->rate_limit)
1218                 /* remove current rl index to free space to next ones */
1219                 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1220
1221         sq->rate_limit = 0;
1222
1223         if (rate) {
1224                 err = mlx5_rl_add_rate(mdev, rate, &rl_index);
1225                 if (err) {
1226                         netdev_err(dev, "Failed configuring rate %u: %d\n",
1227                                    rate, err);
1228                         return err;
1229                 }
1230         }
1231
1232         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY,
1233                               MLX5_SQC_STATE_RDY, true, rl_index);
1234         if (err) {
1235                 netdev_err(dev, "Failed configuring rate %u: %d\n",
1236                            rate, err);
1237                 /* remove the rate from the table */
1238                 if (rate)
1239                         mlx5_rl_remove_rate(mdev, rate);
1240                 return err;
1241         }
1242
1243         sq->rate_limit = rate;
1244         return 0;
1245 }
1246
1247 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1248 {
1249         struct mlx5e_priv *priv = netdev_priv(dev);
1250         struct mlx5_core_dev *mdev = priv->mdev;
1251         struct mlx5e_sq *sq = priv->txq_to_sq_map[index];
1252         int err = 0;
1253
1254         if (!mlx5_rl_is_supported(mdev)) {
1255                 netdev_err(dev, "Rate limiting is not supported on this device\n");
1256                 return -EINVAL;
1257         }
1258
1259         /* rate is given in Mb/sec, HW config is in Kb/sec */
1260         rate = rate << 10;
1261
1262         /* Check whether rate in valid range, 0 is always valid */
1263         if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1264                 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1265                 return -ERANGE;
1266         }
1267
1268         mutex_lock(&priv->state_lock);
1269         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1270                 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1271         if (!err)
1272                 priv->tx_rates[index] = rate;
1273         mutex_unlock(&priv->state_lock);
1274
1275         return err;
1276 }
1277
1278 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1279                               struct mlx5e_channel_param *cparam,
1280                               struct mlx5e_channel **cp)
1281 {
1282         struct mlx5e_cq_moder icosq_cq_moder = {0, 0};
1283         struct net_device *netdev = priv->netdev;
1284         struct mlx5e_cq_moder rx_cq_profile;
1285         int cpu = mlx5e_get_cpu(priv, ix);
1286         struct mlx5e_channel *c;
1287         struct mlx5e_sq *sq;
1288         int err;
1289         int i;
1290
1291         c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1292         if (!c)
1293                 return -ENOMEM;
1294
1295         c->priv     = priv;
1296         c->ix       = ix;
1297         c->cpu      = cpu;
1298         c->pdev     = &priv->mdev->pdev->dev;
1299         c->netdev   = priv->netdev;
1300         c->mkey_be  = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1301         c->num_tc   = priv->params.num_tc;
1302
1303         if (priv->params.rx_am_enabled)
1304                 rx_cq_profile = mlx5e_am_get_def_profile(priv->params.rx_cq_period_mode);
1305         else
1306                 rx_cq_profile = priv->params.rx_cq_moderation;
1307
1308         mlx5e_build_channeltc_to_txq_map(priv, ix);
1309
1310         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1311
1312         err = mlx5e_open_cq(c, &cparam->icosq_cq, &c->icosq.cq, icosq_cq_moder);
1313         if (err)
1314                 goto err_napi_del;
1315
1316         err = mlx5e_open_tx_cqs(c, cparam);
1317         if (err)
1318                 goto err_close_icosq_cq;
1319
1320         err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
1321                             rx_cq_profile);
1322         if (err)
1323                 goto err_close_tx_cqs;
1324
1325         napi_enable(&c->napi);
1326
1327         err = mlx5e_open_sq(c, 0, &cparam->icosq, &c->icosq);
1328         if (err)
1329                 goto err_disable_napi;
1330
1331         err = mlx5e_open_sqs(c, cparam);
1332         if (err)
1333                 goto err_close_icosq;
1334
1335         for (i = 0; i < priv->params.num_tc; i++) {
1336                 u32 txq_ix = priv->channeltc_to_txq_map[ix][i];
1337
1338                 if (priv->tx_rates[txq_ix]) {
1339                         sq = priv->txq_to_sq_map[txq_ix];
1340                         mlx5e_set_sq_maxrate(priv->netdev, sq,
1341                                              priv->tx_rates[txq_ix]);
1342                 }
1343         }
1344
1345         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1346         if (err)
1347                 goto err_close_sqs;
1348
1349         netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1350         *cp = c;
1351
1352         return 0;
1353
1354 err_close_sqs:
1355         mlx5e_close_sqs(c);
1356
1357 err_close_icosq:
1358         mlx5e_close_sq(&c->icosq);
1359
1360 err_disable_napi:
1361         napi_disable(&c->napi);
1362         mlx5e_close_cq(&c->rq.cq);
1363
1364 err_close_tx_cqs:
1365         mlx5e_close_tx_cqs(c);
1366
1367 err_close_icosq_cq:
1368         mlx5e_close_cq(&c->icosq.cq);
1369
1370 err_napi_del:
1371         netif_napi_del(&c->napi);
1372         napi_hash_del(&c->napi);
1373         kfree(c);
1374
1375         return err;
1376 }
1377
1378 static void mlx5e_close_channel(struct mlx5e_channel *c)
1379 {
1380         mlx5e_close_rq(&c->rq);
1381         mlx5e_close_sqs(c);
1382         mlx5e_close_sq(&c->icosq);
1383         napi_disable(&c->napi);
1384         mlx5e_close_cq(&c->rq.cq);
1385         mlx5e_close_tx_cqs(c);
1386         mlx5e_close_cq(&c->icosq.cq);
1387         netif_napi_del(&c->napi);
1388
1389         napi_hash_del(&c->napi);
1390         synchronize_rcu();
1391
1392         kfree(c);
1393 }
1394
1395 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1396                                  struct mlx5e_rq_param *param)
1397 {
1398         void *rqc = param->rqc;
1399         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1400
1401         switch (priv->params.rq_wq_type) {
1402         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1403                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
1404                          priv->params.mpwqe_log_num_strides - 9);
1405                 MLX5_SET(wq, wq, log_wqe_stride_size,
1406                          priv->params.mpwqe_log_stride_sz - 6);
1407                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1408                 break;
1409         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1410                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1411         }
1412
1413         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1414         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1415         MLX5_SET(wq, wq, log_wq_sz,        priv->params.log_rq_size);
1416         MLX5_SET(wq, wq, pd,               priv->mdev->mlx5e_res.pdn);
1417         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
1418
1419         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1420         param->wq.linear = 1;
1421
1422         param->am_enabled = priv->params.rx_am_enabled;
1423 }
1424
1425 static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1426 {
1427         void *rqc = param->rqc;
1428         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1429
1430         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1431         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1432 }
1433
1434 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1435                                         struct mlx5e_sq_param *param)
1436 {
1437         void *sqc = param->sqc;
1438         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1439
1440         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1441         MLX5_SET(wq, wq, pd,            priv->mdev->mlx5e_res.pdn);
1442
1443         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1444 }
1445
1446 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1447                                  struct mlx5e_sq_param *param)
1448 {
1449         void *sqc = param->sqc;
1450         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1451
1452         mlx5e_build_sq_param_common(priv, param);
1453         MLX5_SET(wq, wq, log_wq_sz,     priv->params.log_sq_size);
1454
1455         param->max_inline = priv->params.tx_max_inline;
1456         param->min_inline_mode = priv->params.tx_min_inline_mode;
1457 }
1458
1459 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1460                                         struct mlx5e_cq_param *param)
1461 {
1462         void *cqc = param->cqc;
1463
1464         MLX5_SET(cqc, cqc, uar_page, priv->mdev->mlx5e_res.cq_uar.index);
1465 }
1466
1467 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1468                                     struct mlx5e_cq_param *param)
1469 {
1470         void *cqc = param->cqc;
1471         u8 log_cq_size;
1472
1473         switch (priv->params.rq_wq_type) {
1474         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1475                 log_cq_size = priv->params.log_rq_size +
1476                         priv->params.mpwqe_log_num_strides;
1477                 break;
1478         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1479                 log_cq_size = priv->params.log_rq_size;
1480         }
1481
1482         MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
1483         if (priv->params.rx_cqe_compress) {
1484                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1485                 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1486         }
1487
1488         mlx5e_build_common_cq_param(priv, param);
1489
1490         param->cq_period_mode = priv->params.rx_cq_period_mode;
1491 }
1492
1493 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1494                                     struct mlx5e_cq_param *param)
1495 {
1496         void *cqc = param->cqc;
1497
1498         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1499
1500         mlx5e_build_common_cq_param(priv, param);
1501
1502         param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1503 }
1504
1505 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1506                                      struct mlx5e_cq_param *param,
1507                                      u8 log_wq_size)
1508 {
1509         void *cqc = param->cqc;
1510
1511         MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1512
1513         mlx5e_build_common_cq_param(priv, param);
1514
1515         param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1516 }
1517
1518 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
1519                                     struct mlx5e_sq_param *param,
1520                                     u8 log_wq_size)
1521 {
1522         void *sqc = param->sqc;
1523         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1524
1525         mlx5e_build_sq_param_common(priv, param);
1526
1527         MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
1528         MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
1529
1530         param->icosq = true;
1531 }
1532
1533 static void mlx5e_build_channel_param(struct mlx5e_priv *priv, struct mlx5e_channel_param *cparam)
1534 {
1535         u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
1536
1537         mlx5e_build_rq_param(priv, &cparam->rq);
1538         mlx5e_build_sq_param(priv, &cparam->sq);
1539         mlx5e_build_icosq_param(priv, &cparam->icosq, icosq_log_wq_sz);
1540         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1541         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1542         mlx5e_build_ico_cq_param(priv, &cparam->icosq_cq, icosq_log_wq_sz);
1543 }
1544
1545 static int mlx5e_open_channels(struct mlx5e_priv *priv)
1546 {
1547         struct mlx5e_channel_param *cparam;
1548         int nch = priv->params.num_channels;
1549         int err = -ENOMEM;
1550         int i;
1551         int j;
1552
1553         priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1554                                 GFP_KERNEL);
1555
1556         priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
1557                                       sizeof(struct mlx5e_sq *), GFP_KERNEL);
1558
1559         cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
1560
1561         if (!priv->channel || !priv->txq_to_sq_map || !cparam)
1562                 goto err_free_txq_to_sq_map;
1563
1564         mlx5e_build_channel_param(priv, cparam);
1565
1566         for (i = 0; i < nch; i++) {
1567                 err = mlx5e_open_channel(priv, i, cparam, &priv->channel[i]);
1568                 if (err)
1569                         goto err_close_channels;
1570         }
1571
1572         for (j = 0; j < nch; j++) {
1573                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1574                 if (err)
1575                         goto err_close_channels;
1576         }
1577
1578         /* FIXME: This is a W/A for tx timeout watch dog false alarm when
1579          * polling for inactive tx queues.
1580          */
1581         netif_tx_start_all_queues(priv->netdev);
1582
1583         kfree(cparam);
1584         return 0;
1585
1586 err_close_channels:
1587         for (i--; i >= 0; i--)
1588                 mlx5e_close_channel(priv->channel[i]);
1589
1590 err_free_txq_to_sq_map:
1591         kfree(priv->txq_to_sq_map);
1592         kfree(priv->channel);
1593         kfree(cparam);
1594
1595         return err;
1596 }
1597
1598 static void mlx5e_close_channels(struct mlx5e_priv *priv)
1599 {
1600         int i;
1601
1602         /* FIXME: This is a W/A only for tx timeout watch dog false alarm when
1603          * polling for inactive tx queues.
1604          */
1605         netif_tx_stop_all_queues(priv->netdev);
1606         netif_tx_disable(priv->netdev);
1607
1608         for (i = 0; i < priv->params.num_channels; i++)
1609                 mlx5e_close_channel(priv->channel[i]);
1610
1611         kfree(priv->txq_to_sq_map);
1612         kfree(priv->channel);
1613 }
1614
1615 static int mlx5e_rx_hash_fn(int hfunc)
1616 {
1617         return (hfunc == ETH_RSS_HASH_TOP) ?
1618                MLX5_RX_HASH_FN_TOEPLITZ :
1619                MLX5_RX_HASH_FN_INVERTED_XOR8;
1620 }
1621
1622 static int mlx5e_bits_invert(unsigned long a, int size)
1623 {
1624         int inv = 0;
1625         int i;
1626
1627         for (i = 0; i < size; i++)
1628                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1629
1630         return inv;
1631 }
1632
1633 static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1634 {
1635         int i;
1636
1637         for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1638                 int ix = i;
1639                 u32 rqn;
1640
1641                 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1642                         ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1643
1644                 ix = priv->params.indirection_rqt[ix];
1645                 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1646                                 priv->channel[ix]->rq.rqn :
1647                                 priv->drop_rq.rqn;
1648                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
1649         }
1650 }
1651
1652 static void mlx5e_fill_direct_rqt_rqn(struct mlx5e_priv *priv, void *rqtc,
1653                                       int ix)
1654 {
1655         u32 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1656                         priv->channel[ix]->rq.rqn :
1657                         priv->drop_rq.rqn;
1658
1659         MLX5_SET(rqtc, rqtc, rq_num[0], rqn);
1660 }
1661
1662 static int mlx5e_create_rqt(struct mlx5e_priv *priv, int sz,
1663                             int ix, struct mlx5e_rqt *rqt)
1664 {
1665         struct mlx5_core_dev *mdev = priv->mdev;
1666         void *rqtc;
1667         int inlen;
1668         int err;
1669         u32 *in;
1670
1671         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1672         in = mlx5_vzalloc(inlen);
1673         if (!in)
1674                 return -ENOMEM;
1675
1676         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1677
1678         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1679         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1680
1681         if (sz > 1) /* RSS */
1682                 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1683         else
1684                 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
1685
1686         err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
1687         if (!err)
1688                 rqt->enabled = true;
1689
1690         kvfree(in);
1691         return err;
1692 }
1693
1694 void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
1695 {
1696         rqt->enabled = false;
1697         mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
1698 }
1699
1700 static int mlx5e_create_indirect_rqts(struct mlx5e_priv *priv)
1701 {
1702         struct mlx5e_rqt *rqt = &priv->indir_rqt;
1703
1704         return mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, 0, rqt);
1705 }
1706
1707 int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
1708 {
1709         struct mlx5e_rqt *rqt;
1710         int err;
1711         int ix;
1712
1713         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
1714                 rqt = &priv->direct_tir[ix].rqt;
1715                 err = mlx5e_create_rqt(priv, 1 /*size */, ix, rqt);
1716                 if (err)
1717                         goto err_destroy_rqts;
1718         }
1719
1720         return 0;
1721
1722 err_destroy_rqts:
1723         for (ix--; ix >= 0; ix--)
1724                 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
1725
1726         return err;
1727 }
1728
1729 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix)
1730 {
1731         struct mlx5_core_dev *mdev = priv->mdev;
1732         void *rqtc;
1733         int inlen;
1734         u32 *in;
1735         int err;
1736
1737         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1738         in = mlx5_vzalloc(inlen);
1739         if (!in)
1740                 return -ENOMEM;
1741
1742         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
1743
1744         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1745         if (sz > 1) /* RSS */
1746                 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1747         else
1748                 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
1749
1750         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
1751
1752         err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
1753
1754         kvfree(in);
1755
1756         return err;
1757 }
1758
1759 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
1760 {
1761         u32 rqtn;
1762         int ix;
1763
1764         if (priv->indir_rqt.enabled) {
1765                 rqtn = priv->indir_rqt.rqtn;
1766                 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, 0);
1767         }
1768
1769         for (ix = 0; ix < priv->params.num_channels; ix++) {
1770                 if (!priv->direct_tir[ix].rqt.enabled)
1771                         continue;
1772                 rqtn = priv->direct_tir[ix].rqt.rqtn;
1773                 mlx5e_redirect_rqt(priv, rqtn, 1, ix);
1774         }
1775 }
1776
1777 static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
1778 {
1779         if (!priv->params.lro_en)
1780                 return;
1781
1782 #define ROUGH_MAX_L2_L3_HDR_SZ 256
1783
1784         MLX5_SET(tirc, tirc, lro_enable_mask,
1785                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1786                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1787         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1788                  (priv->params.lro_wqe_sz -
1789                   ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1790         MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1791                  MLX5_CAP_ETH(priv->mdev,
1792                               lro_timer_supported_periods[2]));
1793 }
1794
1795 void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv)
1796 {
1797         MLX5_SET(tirc, tirc, rx_hash_fn,
1798                  mlx5e_rx_hash_fn(priv->params.rss_hfunc));
1799         if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
1800                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
1801                                              rx_hash_toeplitz_key);
1802                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
1803                                                rx_hash_toeplitz_key);
1804
1805                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1806                 memcpy(rss_key, priv->params.toeplitz_hash_key, len);
1807         }
1808 }
1809
1810 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
1811 {
1812         struct mlx5_core_dev *mdev = priv->mdev;
1813
1814         void *in;
1815         void *tirc;
1816         int inlen;
1817         int err;
1818         int tt;
1819         int ix;
1820
1821         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1822         in = mlx5_vzalloc(inlen);
1823         if (!in)
1824                 return -ENOMEM;
1825
1826         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
1827         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
1828
1829         mlx5e_build_tir_ctx_lro(tirc, priv);
1830
1831         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
1832                 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
1833                                            inlen);
1834                 if (err)
1835                         goto free_in;
1836         }
1837
1838         for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
1839                 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
1840                                            in, inlen);
1841                 if (err)
1842                         goto free_in;
1843         }
1844
1845 free_in:
1846         kvfree(in);
1847
1848         return err;
1849 }
1850
1851 static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
1852 {
1853         struct mlx5_core_dev *mdev = priv->mdev;
1854         u16 hw_mtu = MLX5E_SW2HW_MTU(mtu);
1855         int err;
1856
1857         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
1858         if (err)
1859                 return err;
1860
1861         /* Update vport context MTU */
1862         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
1863         return 0;
1864 }
1865
1866 static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
1867 {
1868         struct mlx5_core_dev *mdev = priv->mdev;
1869         u16 hw_mtu = 0;
1870         int err;
1871
1872         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
1873         if (err || !hw_mtu) /* fallback to port oper mtu */
1874                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
1875
1876         *mtu = MLX5E_HW2SW_MTU(hw_mtu);
1877 }
1878
1879 static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
1880 {
1881         struct mlx5e_priv *priv = netdev_priv(netdev);
1882         u16 mtu;
1883         int err;
1884
1885         err = mlx5e_set_mtu(priv, netdev->mtu);
1886         if (err)
1887                 return err;
1888
1889         mlx5e_query_mtu(priv, &mtu);
1890         if (mtu != netdev->mtu)
1891                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
1892                             __func__, mtu, netdev->mtu);
1893
1894         netdev->mtu = mtu;
1895         return 0;
1896 }
1897
1898 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
1899 {
1900         struct mlx5e_priv *priv = netdev_priv(netdev);
1901         int nch = priv->params.num_channels;
1902         int ntc = priv->params.num_tc;
1903         int tc;
1904
1905         netdev_reset_tc(netdev);
1906
1907         if (ntc == 1)
1908                 return;
1909
1910         netdev_set_num_tc(netdev, ntc);
1911
1912         /* Map netdev TCs to offset 0
1913          * We have our own UP to TXQ mapping for QoS
1914          */
1915         for (tc = 0; tc < ntc; tc++)
1916                 netdev_set_tc_queue(netdev, tc, nch, 0);
1917 }
1918
1919 int mlx5e_open_locked(struct net_device *netdev)
1920 {
1921         struct mlx5e_priv *priv = netdev_priv(netdev);
1922         struct mlx5_core_dev *mdev = priv->mdev;
1923         int num_txqs;
1924         int err;
1925
1926         set_bit(MLX5E_STATE_OPENED, &priv->state);
1927
1928         mlx5e_netdev_set_tcs(netdev);
1929
1930         num_txqs = priv->params.num_channels * priv->params.num_tc;
1931         netif_set_real_num_tx_queues(netdev, num_txqs);
1932         netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
1933
1934         err = mlx5e_open_channels(priv);
1935         if (err) {
1936                 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
1937                            __func__, err);
1938                 goto err_clear_state_opened_flag;
1939         }
1940
1941         err = mlx5e_refresh_tirs_self_loopback_enable(priv->mdev);
1942         if (err) {
1943                 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
1944                            __func__, err);
1945                 goto err_close_channels;
1946         }
1947
1948         mlx5e_redirect_rqts(priv);
1949         mlx5e_update_carrier(priv);
1950         mlx5e_timestamp_init(priv);
1951 #ifdef CONFIG_RFS_ACCEL
1952         priv->netdev->rx_cpu_rmap = priv->mdev->rmap;
1953 #endif
1954         if (priv->profile->update_stats)
1955                 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
1956
1957         if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
1958                 err = mlx5e_add_sqs_fwd_rules(priv);
1959                 if (err)
1960                         goto err_close_channels;
1961         }
1962         return 0;
1963
1964 err_close_channels:
1965         mlx5e_close_channels(priv);
1966 err_clear_state_opened_flag:
1967         clear_bit(MLX5E_STATE_OPENED, &priv->state);
1968         return err;
1969 }
1970
1971 int mlx5e_open(struct net_device *netdev)
1972 {
1973         struct mlx5e_priv *priv = netdev_priv(netdev);
1974         int err;
1975
1976         mutex_lock(&priv->state_lock);
1977         err = mlx5e_open_locked(netdev);
1978         mutex_unlock(&priv->state_lock);
1979
1980         return err;
1981 }
1982
1983 int mlx5e_close_locked(struct net_device *netdev)
1984 {
1985         struct mlx5e_priv *priv = netdev_priv(netdev);
1986         struct mlx5_core_dev *mdev = priv->mdev;
1987
1988         /* May already be CLOSED in case a previous configuration operation
1989          * (e.g RX/TX queue size change) that involves close&open failed.
1990          */
1991         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
1992                 return 0;
1993
1994         clear_bit(MLX5E_STATE_OPENED, &priv->state);
1995
1996         if (MLX5_CAP_GEN(mdev, vport_group_manager))
1997                 mlx5e_remove_sqs_fwd_rules(priv);
1998
1999         mlx5e_timestamp_cleanup(priv);
2000         netif_carrier_off(priv->netdev);
2001         mlx5e_redirect_rqts(priv);
2002         mlx5e_close_channels(priv);
2003
2004         return 0;
2005 }
2006
2007 int mlx5e_close(struct net_device *netdev)
2008 {
2009         struct mlx5e_priv *priv = netdev_priv(netdev);
2010         int err;
2011
2012         if (!netif_device_present(netdev))
2013                 return -ENODEV;
2014
2015         mutex_lock(&priv->state_lock);
2016         err = mlx5e_close_locked(netdev);
2017         mutex_unlock(&priv->state_lock);
2018
2019         return err;
2020 }
2021
2022 static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
2023                                 struct mlx5e_rq *rq,
2024                                 struct mlx5e_rq_param *param)
2025 {
2026         struct mlx5_core_dev *mdev = priv->mdev;
2027         void *rqc = param->rqc;
2028         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2029         int err;
2030
2031         param->wq.db_numa_node = param->wq.buf_numa_node;
2032
2033         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
2034                                 &rq->wq_ctrl);
2035         if (err)
2036                 return err;
2037
2038         rq->priv = priv;
2039
2040         return 0;
2041 }
2042
2043 static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
2044                                 struct mlx5e_cq *cq,
2045                                 struct mlx5e_cq_param *param)
2046 {
2047         struct mlx5_core_dev *mdev = priv->mdev;
2048         struct mlx5_core_cq *mcq = &cq->mcq;
2049         int eqn_not_used;
2050         unsigned int irqn;
2051         int err;
2052
2053         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
2054                                &cq->wq_ctrl);
2055         if (err)
2056                 return err;
2057
2058         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
2059
2060         mcq->cqe_sz     = 64;
2061         mcq->set_ci_db  = cq->wq_ctrl.db.db;
2062         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
2063         *mcq->set_ci_db = 0;
2064         *mcq->arm_db    = 0;
2065         mcq->vector     = param->eq_ix;
2066         mcq->comp       = mlx5e_completion_event;
2067         mcq->event      = mlx5e_cq_error_event;
2068         mcq->irqn       = irqn;
2069         mcq->uar        = &mdev->mlx5e_res.cq_uar;
2070
2071         cq->priv = priv;
2072
2073         return 0;
2074 }
2075
2076 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
2077 {
2078         struct mlx5e_cq_param cq_param;
2079         struct mlx5e_rq_param rq_param;
2080         struct mlx5e_rq *rq = &priv->drop_rq;
2081         struct mlx5e_cq *cq = &priv->drop_rq.cq;
2082         int err;
2083
2084         memset(&cq_param, 0, sizeof(cq_param));
2085         memset(&rq_param, 0, sizeof(rq_param));
2086         mlx5e_build_drop_rq_param(&rq_param);
2087
2088         err = mlx5e_create_drop_cq(priv, cq, &cq_param);
2089         if (err)
2090                 return err;
2091
2092         err = mlx5e_enable_cq(cq, &cq_param);
2093         if (err)
2094                 goto err_destroy_cq;
2095
2096         err = mlx5e_create_drop_rq(priv, rq, &rq_param);
2097         if (err)
2098                 goto err_disable_cq;
2099
2100         err = mlx5e_enable_rq(rq, &rq_param);
2101         if (err)
2102                 goto err_destroy_rq;
2103
2104         return 0;
2105
2106 err_destroy_rq:
2107         mlx5e_destroy_rq(&priv->drop_rq);
2108
2109 err_disable_cq:
2110         mlx5e_disable_cq(&priv->drop_rq.cq);
2111
2112 err_destroy_cq:
2113         mlx5e_destroy_cq(&priv->drop_rq.cq);
2114
2115         return err;
2116 }
2117
2118 static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
2119 {
2120         mlx5e_disable_rq(&priv->drop_rq);
2121         mlx5e_destroy_rq(&priv->drop_rq);
2122         mlx5e_disable_cq(&priv->drop_rq.cq);
2123         mlx5e_destroy_cq(&priv->drop_rq.cq);
2124 }
2125
2126 static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
2127 {
2128         struct mlx5_core_dev *mdev = priv->mdev;
2129         u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
2130         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2131
2132         MLX5_SET(tisc, tisc, prio, tc << 1);
2133         MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
2134
2135         if (mlx5_lag_is_lacp_owner(mdev))
2136                 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
2137
2138         return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
2139 }
2140
2141 static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
2142 {
2143         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
2144 }
2145
2146 int mlx5e_create_tises(struct mlx5e_priv *priv)
2147 {
2148         int err;
2149         int tc;
2150
2151         for (tc = 0; tc < priv->profile->max_tc; tc++) {
2152                 err = mlx5e_create_tis(priv, tc);
2153                 if (err)
2154                         goto err_close_tises;
2155         }
2156
2157         return 0;
2158
2159 err_close_tises:
2160         for (tc--; tc >= 0; tc--)
2161                 mlx5e_destroy_tis(priv, tc);
2162
2163         return err;
2164 }
2165
2166 void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
2167 {
2168         int tc;
2169
2170         for (tc = 0; tc < priv->profile->max_tc; tc++)
2171                 mlx5e_destroy_tis(priv, tc);
2172 }
2173
2174 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2175                                       enum mlx5e_traffic_types tt)
2176 {
2177         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2178
2179         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2180
2181 #define MLX5_HASH_IP            (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2182                                  MLX5_HASH_FIELD_SEL_DST_IP)
2183
2184 #define MLX5_HASH_IP_L4PORTS    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2185                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2186                                  MLX5_HASH_FIELD_SEL_L4_SPORT |\
2187                                  MLX5_HASH_FIELD_SEL_L4_DPORT)
2188
2189 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2190                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2191                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2192
2193         mlx5e_build_tir_ctx_lro(tirc, priv);
2194
2195         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2196         MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2197         mlx5e_build_tir_ctx_hash(tirc, priv);
2198
2199         switch (tt) {
2200         case MLX5E_TT_IPV4_TCP:
2201                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2202                          MLX5_L3_PROT_TYPE_IPV4);
2203                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2204                          MLX5_L4_PROT_TYPE_TCP);
2205                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2206                          MLX5_HASH_IP_L4PORTS);
2207                 break;
2208
2209         case MLX5E_TT_IPV6_TCP:
2210                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2211                          MLX5_L3_PROT_TYPE_IPV6);
2212                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2213                          MLX5_L4_PROT_TYPE_TCP);
2214                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2215                          MLX5_HASH_IP_L4PORTS);
2216                 break;
2217
2218         case MLX5E_TT_IPV4_UDP:
2219                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2220                          MLX5_L3_PROT_TYPE_IPV4);
2221                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2222                          MLX5_L4_PROT_TYPE_UDP);
2223                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2224                          MLX5_HASH_IP_L4PORTS);
2225                 break;
2226
2227         case MLX5E_TT_IPV6_UDP:
2228                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2229                          MLX5_L3_PROT_TYPE_IPV6);
2230                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2231                          MLX5_L4_PROT_TYPE_UDP);
2232                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2233                          MLX5_HASH_IP_L4PORTS);
2234                 break;
2235
2236         case MLX5E_TT_IPV4_IPSEC_AH:
2237                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2238                          MLX5_L3_PROT_TYPE_IPV4);
2239                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2240                          MLX5_HASH_IP_IPSEC_SPI);
2241                 break;
2242
2243         case MLX5E_TT_IPV6_IPSEC_AH:
2244                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2245                          MLX5_L3_PROT_TYPE_IPV6);
2246                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2247                          MLX5_HASH_IP_IPSEC_SPI);
2248                 break;
2249
2250         case MLX5E_TT_IPV4_IPSEC_ESP:
2251                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2252                          MLX5_L3_PROT_TYPE_IPV4);
2253                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2254                          MLX5_HASH_IP_IPSEC_SPI);
2255                 break;
2256
2257         case MLX5E_TT_IPV6_IPSEC_ESP:
2258                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2259                          MLX5_L3_PROT_TYPE_IPV6);
2260                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2261                          MLX5_HASH_IP_IPSEC_SPI);
2262                 break;
2263
2264         case MLX5E_TT_IPV4:
2265                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2266                          MLX5_L3_PROT_TYPE_IPV4);
2267                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2268                          MLX5_HASH_IP);
2269                 break;
2270
2271         case MLX5E_TT_IPV6:
2272                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2273                          MLX5_L3_PROT_TYPE_IPV6);
2274                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2275                          MLX5_HASH_IP);
2276                 break;
2277         default:
2278                 WARN_ONCE(true,
2279                           "mlx5e_build_indir_tir_ctx: bad traffic type!\n");
2280         }
2281 }
2282
2283 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2284                                        u32 rqtn)
2285 {
2286         MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2287
2288         mlx5e_build_tir_ctx_lro(tirc, priv);
2289
2290         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2291         MLX5_SET(tirc, tirc, indirect_table, rqtn);
2292         MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2293 }
2294
2295 static int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
2296 {
2297         struct mlx5e_tir *tir;
2298         void *tirc;
2299         int inlen;
2300         int err;
2301         u32 *in;
2302         int tt;
2303
2304         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2305         in = mlx5_vzalloc(inlen);
2306         if (!in)
2307                 return -ENOMEM;
2308
2309         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2310                 memset(in, 0, inlen);
2311                 tir = &priv->indir_tir[tt];
2312                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2313                 mlx5e_build_indir_tir_ctx(priv, tirc, tt);
2314                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2315                 if (err)
2316                         goto err_destroy_tirs;
2317         }
2318
2319         kvfree(in);
2320
2321         return 0;
2322
2323 err_destroy_tirs:
2324         for (tt--; tt >= 0; tt--)
2325                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
2326
2327         kvfree(in);
2328
2329         return err;
2330 }
2331
2332 int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
2333 {
2334         int nch = priv->profile->max_nch(priv->mdev);
2335         struct mlx5e_tir *tir;
2336         void *tirc;
2337         int inlen;
2338         int err;
2339         u32 *in;
2340         int ix;
2341
2342         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2343         in = mlx5_vzalloc(inlen);
2344         if (!in)
2345                 return -ENOMEM;
2346
2347         for (ix = 0; ix < nch; ix++) {
2348                 memset(in, 0, inlen);
2349                 tir = &priv->direct_tir[ix];
2350                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2351                 mlx5e_build_direct_tir_ctx(priv, tirc,
2352                                            priv->direct_tir[ix].rqt.rqtn);
2353                 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2354                 if (err)
2355                         goto err_destroy_ch_tirs;
2356         }
2357
2358         kvfree(in);
2359
2360         return 0;
2361
2362 err_destroy_ch_tirs:
2363         for (ix--; ix >= 0; ix--)
2364                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
2365
2366         kvfree(in);
2367
2368         return err;
2369 }
2370
2371 static void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
2372 {
2373         int i;
2374
2375         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
2376                 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
2377 }
2378
2379 void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
2380 {
2381         int nch = priv->profile->max_nch(priv->mdev);
2382         int i;
2383
2384         for (i = 0; i < nch; i++)
2385                 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
2386 }
2387
2388 int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd)
2389 {
2390         int err = 0;
2391         int i;
2392
2393         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2394                 return 0;
2395
2396         for (i = 0; i < priv->params.num_channels; i++) {
2397                 err = mlx5e_modify_rq_vsd(&priv->channel[i]->rq, vsd);
2398                 if (err)
2399                         return err;
2400         }
2401
2402         return 0;
2403 }
2404
2405 static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
2406 {
2407         struct mlx5e_priv *priv = netdev_priv(netdev);
2408         bool was_opened;
2409         int err = 0;
2410
2411         if (tc && tc != MLX5E_MAX_NUM_TC)
2412                 return -EINVAL;
2413
2414         mutex_lock(&priv->state_lock);
2415
2416         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2417         if (was_opened)
2418                 mlx5e_close_locked(priv->netdev);
2419
2420         priv->params.num_tc = tc ? tc : 1;
2421
2422         if (was_opened)
2423                 err = mlx5e_open_locked(priv->netdev);
2424
2425         mutex_unlock(&priv->state_lock);
2426
2427         return err;
2428 }
2429
2430 static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
2431                               __be16 proto, struct tc_to_netdev *tc)
2432 {
2433         struct mlx5e_priv *priv = netdev_priv(dev);
2434
2435         if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
2436                 goto mqprio;
2437
2438         switch (tc->type) {
2439         case TC_SETUP_CLSFLOWER:
2440                 switch (tc->cls_flower->command) {
2441                 case TC_CLSFLOWER_REPLACE:
2442                         return mlx5e_configure_flower(priv, proto, tc->cls_flower);
2443                 case TC_CLSFLOWER_DESTROY:
2444                         return mlx5e_delete_flower(priv, tc->cls_flower);
2445                 case TC_CLSFLOWER_STATS:
2446                         return mlx5e_stats_flower(priv, tc->cls_flower);
2447                 }
2448         default:
2449                 return -EOPNOTSUPP;
2450         }
2451
2452 mqprio:
2453         if (tc->type != TC_SETUP_MQPRIO)
2454                 return -EINVAL;
2455
2456         return mlx5e_setup_tc(dev, tc->tc);
2457 }
2458
2459 struct rtnl_link_stats64 *
2460 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
2461 {
2462         struct mlx5e_priv *priv = netdev_priv(dev);
2463         struct mlx5e_sw_stats *sstats = &priv->stats.sw;
2464         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
2465         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
2466
2467         stats->rx_packets = sstats->rx_packets;
2468         stats->rx_bytes   = sstats->rx_bytes;
2469         stats->tx_packets = sstats->tx_packets;
2470         stats->tx_bytes   = sstats->tx_bytes;
2471
2472         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
2473         stats->tx_dropped = sstats->tx_queue_dropped;
2474
2475         stats->rx_length_errors =
2476                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
2477                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
2478                 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
2479         stats->rx_crc_errors =
2480                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
2481         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
2482         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
2483         stats->tx_carrier_errors =
2484                 PPORT_802_3_GET(pstats, a_symbol_error_during_carrier);
2485         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
2486                            stats->rx_frame_errors;
2487         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
2488
2489         /* vport multicast also counts packets that are dropped due to steering
2490          * or rx out of buffer
2491          */
2492         stats->multicast =
2493                 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
2494
2495         return stats;
2496 }
2497
2498 static void mlx5e_set_rx_mode(struct net_device *dev)
2499 {
2500         struct mlx5e_priv *priv = netdev_priv(dev);
2501
2502         queue_work(priv->wq, &priv->set_rx_mode_work);
2503 }
2504
2505 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
2506 {
2507         struct mlx5e_priv *priv = netdev_priv(netdev);
2508         struct sockaddr *saddr = addr;
2509
2510         if (!is_valid_ether_addr(saddr->sa_data))
2511                 return -EADDRNOTAVAIL;
2512
2513         netif_addr_lock_bh(netdev);
2514         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
2515         netif_addr_unlock_bh(netdev);
2516
2517         queue_work(priv->wq, &priv->set_rx_mode_work);
2518
2519         return 0;
2520 }
2521
2522 #define MLX5E_SET_FEATURE(netdev, feature, enable)      \
2523         do {                                            \
2524                 if (enable)                             \
2525                         netdev->features |= feature;    \
2526                 else                                    \
2527                         netdev->features &= ~feature;   \
2528         } while (0)
2529
2530 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
2531
2532 static int set_feature_lro(struct net_device *netdev, bool enable)
2533 {
2534         struct mlx5e_priv *priv = netdev_priv(netdev);
2535         bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2536         int err;
2537
2538         mutex_lock(&priv->state_lock);
2539
2540         if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2541                 mlx5e_close_locked(priv->netdev);
2542
2543         priv->params.lro_en = enable;
2544         err = mlx5e_modify_tirs_lro(priv);
2545         if (err) {
2546                 netdev_err(netdev, "lro modify failed, %d\n", err);
2547                 priv->params.lro_en = !enable;
2548         }
2549
2550         if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2551                 mlx5e_open_locked(priv->netdev);
2552
2553         mutex_unlock(&priv->state_lock);
2554
2555         return err;
2556 }
2557
2558 static int set_feature_vlan_filter(struct net_device *netdev, bool enable)
2559 {
2560         struct mlx5e_priv *priv = netdev_priv(netdev);
2561
2562         if (enable)
2563                 mlx5e_enable_vlan_filter(priv);
2564         else
2565                 mlx5e_disable_vlan_filter(priv);
2566
2567         return 0;
2568 }
2569
2570 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
2571 {
2572         struct mlx5e_priv *priv = netdev_priv(netdev);
2573
2574         if (!enable && mlx5e_tc_num_filters(priv)) {
2575                 netdev_err(netdev,
2576                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
2577                 return -EINVAL;
2578         }
2579
2580         return 0;
2581 }
2582
2583 static int set_feature_rx_all(struct net_device *netdev, bool enable)
2584 {
2585         struct mlx5e_priv *priv = netdev_priv(netdev);
2586         struct mlx5_core_dev *mdev = priv->mdev;
2587
2588         return mlx5_set_port_fcs(mdev, !enable);
2589 }
2590
2591 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
2592 {
2593         struct mlx5e_priv *priv = netdev_priv(netdev);
2594         int err;
2595
2596         mutex_lock(&priv->state_lock);
2597
2598         priv->params.vlan_strip_disable = !enable;
2599         err = mlx5e_modify_rqs_vsd(priv, !enable);
2600         if (err)
2601                 priv->params.vlan_strip_disable = enable;
2602
2603         mutex_unlock(&priv->state_lock);
2604
2605         return err;
2606 }
2607
2608 #ifdef CONFIG_RFS_ACCEL
2609 static int set_feature_arfs(struct net_device *netdev, bool enable)
2610 {
2611         struct mlx5e_priv *priv = netdev_priv(netdev);
2612         int err;
2613
2614         if (enable)
2615                 err = mlx5e_arfs_enable(priv);
2616         else
2617                 err = mlx5e_arfs_disable(priv);
2618
2619         return err;
2620 }
2621 #endif
2622
2623 static int mlx5e_handle_feature(struct net_device *netdev,
2624                                 netdev_features_t wanted_features,
2625                                 netdev_features_t feature,
2626                                 mlx5e_feature_handler feature_handler)
2627 {
2628         netdev_features_t changes = wanted_features ^ netdev->features;
2629         bool enable = !!(wanted_features & feature);
2630         int err;
2631
2632         if (!(changes & feature))
2633                 return 0;
2634
2635         err = feature_handler(netdev, enable);
2636         if (err) {
2637                 netdev_err(netdev, "%s feature 0x%llx failed err %d\n",
2638                            enable ? "Enable" : "Disable", feature, err);
2639                 return err;
2640         }
2641
2642         MLX5E_SET_FEATURE(netdev, feature, enable);
2643         return 0;
2644 }
2645
2646 static int mlx5e_set_features(struct net_device *netdev,
2647                               netdev_features_t features)
2648 {
2649         int err;
2650
2651         err  = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
2652                                     set_feature_lro);
2653         err |= mlx5e_handle_feature(netdev, features,
2654                                     NETIF_F_HW_VLAN_CTAG_FILTER,
2655                                     set_feature_vlan_filter);
2656         err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
2657                                     set_feature_tc_num_filters);
2658         err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
2659                                     set_feature_rx_all);
2660         err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
2661                                     set_feature_rx_vlan);
2662 #ifdef CONFIG_RFS_ACCEL
2663         err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE,
2664                                     set_feature_arfs);
2665 #endif
2666
2667         return err ? -EINVAL : 0;
2668 }
2669
2670 #define MXL5_HW_MIN_MTU 64
2671 #define MXL5E_MIN_MTU (MXL5_HW_MIN_MTU + ETH_FCS_LEN)
2672
2673 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
2674 {
2675         struct mlx5e_priv *priv = netdev_priv(netdev);
2676         struct mlx5_core_dev *mdev = priv->mdev;
2677         bool was_opened;
2678         u16 max_mtu;
2679         u16 min_mtu;
2680         int err = 0;
2681         bool reset;
2682
2683         mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2684
2685         max_mtu = MLX5E_HW2SW_MTU(max_mtu);
2686         min_mtu = MLX5E_HW2SW_MTU(MXL5E_MIN_MTU);
2687
2688         if (new_mtu > max_mtu || new_mtu < min_mtu) {
2689                 netdev_err(netdev,
2690                            "%s: Bad MTU (%d), valid range is: [%d..%d]\n",
2691                            __func__, new_mtu, min_mtu, max_mtu);
2692                 return -EINVAL;
2693         }
2694
2695         mutex_lock(&priv->state_lock);
2696
2697         reset = !priv->params.lro_en &&
2698                 (priv->params.rq_wq_type !=
2699                  MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
2700
2701         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2702         if (was_opened && reset)
2703                 mlx5e_close_locked(netdev);
2704
2705         netdev->mtu = new_mtu;
2706         mlx5e_set_dev_port_mtu(netdev);
2707
2708         if (was_opened && reset)
2709                 err = mlx5e_open_locked(netdev);
2710
2711         mutex_unlock(&priv->state_lock);
2712
2713         return err;
2714 }
2715
2716 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2717 {
2718         switch (cmd) {
2719         case SIOCSHWTSTAMP:
2720                 return mlx5e_hwstamp_set(dev, ifr);
2721         case SIOCGHWTSTAMP:
2722                 return mlx5e_hwstamp_get(dev, ifr);
2723         default:
2724                 return -EOPNOTSUPP;
2725         }
2726 }
2727
2728 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2729 {
2730         struct mlx5e_priv *priv = netdev_priv(dev);
2731         struct mlx5_core_dev *mdev = priv->mdev;
2732
2733         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
2734 }
2735
2736 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos)
2737 {
2738         struct mlx5e_priv *priv = netdev_priv(dev);
2739         struct mlx5_core_dev *mdev = priv->mdev;
2740
2741         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
2742                                            vlan, qos);
2743 }
2744
2745 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
2746 {
2747         struct mlx5e_priv *priv = netdev_priv(dev);
2748         struct mlx5_core_dev *mdev = priv->mdev;
2749
2750         return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
2751 }
2752
2753 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
2754 {
2755         struct mlx5e_priv *priv = netdev_priv(dev);
2756         struct mlx5_core_dev *mdev = priv->mdev;
2757
2758         return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
2759 }
2760 static int mlx5_vport_link2ifla(u8 esw_link)
2761 {
2762         switch (esw_link) {
2763         case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
2764                 return IFLA_VF_LINK_STATE_DISABLE;
2765         case MLX5_ESW_VPORT_ADMIN_STATE_UP:
2766                 return IFLA_VF_LINK_STATE_ENABLE;
2767         }
2768         return IFLA_VF_LINK_STATE_AUTO;
2769 }
2770
2771 static int mlx5_ifla_link2vport(u8 ifla_link)
2772 {
2773         switch (ifla_link) {
2774         case IFLA_VF_LINK_STATE_DISABLE:
2775                 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
2776         case IFLA_VF_LINK_STATE_ENABLE:
2777                 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
2778         }
2779         return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
2780 }
2781
2782 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
2783                                    int link_state)
2784 {
2785         struct mlx5e_priv *priv = netdev_priv(dev);
2786         struct mlx5_core_dev *mdev = priv->mdev;
2787
2788         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
2789                                             mlx5_ifla_link2vport(link_state));
2790 }
2791
2792 static int mlx5e_get_vf_config(struct net_device *dev,
2793                                int vf, struct ifla_vf_info *ivi)
2794 {
2795         struct mlx5e_priv *priv = netdev_priv(dev);
2796         struct mlx5_core_dev *mdev = priv->mdev;
2797         int err;
2798
2799         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
2800         if (err)
2801                 return err;
2802         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
2803         return 0;
2804 }
2805
2806 static int mlx5e_get_vf_stats(struct net_device *dev,
2807                               int vf, struct ifla_vf_stats *vf_stats)
2808 {
2809         struct mlx5e_priv *priv = netdev_priv(dev);
2810         struct mlx5_core_dev *mdev = priv->mdev;
2811
2812         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
2813                                             vf_stats);
2814 }
2815
2816 static void mlx5e_add_vxlan_port(struct net_device *netdev,
2817                                  struct udp_tunnel_info *ti)
2818 {
2819         struct mlx5e_priv *priv = netdev_priv(netdev);
2820
2821         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
2822                 return;
2823
2824         if (!mlx5e_vxlan_allowed(priv->mdev))
2825                 return;
2826
2827         mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);
2828 }
2829
2830 static void mlx5e_del_vxlan_port(struct net_device *netdev,
2831                                  struct udp_tunnel_info *ti)
2832 {
2833         struct mlx5e_priv *priv = netdev_priv(netdev);
2834
2835         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
2836                 return;
2837
2838         if (!mlx5e_vxlan_allowed(priv->mdev))
2839                 return;
2840
2841         mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0);
2842 }
2843
2844 static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
2845                                                     struct sk_buff *skb,
2846                                                     netdev_features_t features)
2847 {
2848         struct udphdr *udph;
2849         u16 proto;
2850         u16 port = 0;
2851
2852         switch (vlan_get_protocol(skb)) {
2853         case htons(ETH_P_IP):
2854                 proto = ip_hdr(skb)->protocol;
2855                 break;
2856         case htons(ETH_P_IPV6):
2857                 proto = ipv6_hdr(skb)->nexthdr;
2858                 break;
2859         default:
2860                 goto out;
2861         }
2862
2863         if (proto == IPPROTO_UDP) {
2864                 udph = udp_hdr(skb);
2865                 port = be16_to_cpu(udph->dest);
2866         }
2867
2868         /* Verify if UDP port is being offloaded by HW */
2869         if (port && mlx5e_vxlan_lookup_port(priv, port))
2870                 return features;
2871
2872 out:
2873         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
2874         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2875 }
2876
2877 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
2878                                               struct net_device *netdev,
2879                                               netdev_features_t features)
2880 {
2881         struct mlx5e_priv *priv = netdev_priv(netdev);
2882
2883         features = vlan_features_check(skb, features);
2884         features = vxlan_features_check(skb, features);
2885
2886         /* Validate if the tunneled packet is being offloaded by HW */
2887         if (skb->encapsulation &&
2888             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
2889                 return mlx5e_vxlan_features_check(priv, skb, features);
2890
2891         return features;
2892 }
2893
2894 static void mlx5e_tx_timeout(struct net_device *dev)
2895 {
2896         struct mlx5e_priv *priv = netdev_priv(dev);
2897         bool sched_work = false;
2898         int i;
2899
2900         netdev_err(dev, "TX timeout detected\n");
2901
2902         for (i = 0; i < priv->params.num_channels * priv->params.num_tc; i++) {
2903                 struct mlx5e_sq *sq = priv->txq_to_sq_map[i];
2904
2905                 if (!netif_xmit_stopped(netdev_get_tx_queue(dev, i)))
2906                         continue;
2907                 sched_work = true;
2908                 set_bit(MLX5E_SQ_STATE_FLUSH, &sq->state);
2909                 netdev_err(dev, "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x\n",
2910                            i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc);
2911         }
2912
2913         if (sched_work && test_bit(MLX5E_STATE_OPENED, &priv->state))
2914                 schedule_work(&priv->tx_timeout_work);
2915 }
2916
2917 static const struct net_device_ops mlx5e_netdev_ops_basic = {
2918         .ndo_open                = mlx5e_open,
2919         .ndo_stop                = mlx5e_close,
2920         .ndo_start_xmit          = mlx5e_xmit,
2921         .ndo_setup_tc            = mlx5e_ndo_setup_tc,
2922         .ndo_select_queue        = mlx5e_select_queue,
2923         .ndo_get_stats64         = mlx5e_get_stats,
2924         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
2925         .ndo_set_mac_address     = mlx5e_set_mac,
2926         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
2927         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
2928         .ndo_set_features        = mlx5e_set_features,
2929         .ndo_change_mtu          = mlx5e_change_mtu,
2930         .ndo_do_ioctl            = mlx5e_ioctl,
2931         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
2932 #ifdef CONFIG_RFS_ACCEL
2933         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
2934 #endif
2935         .ndo_tx_timeout          = mlx5e_tx_timeout,
2936 };
2937
2938 static const struct net_device_ops mlx5e_netdev_ops_sriov = {
2939         .ndo_open                = mlx5e_open,
2940         .ndo_stop                = mlx5e_close,
2941         .ndo_start_xmit          = mlx5e_xmit,
2942         .ndo_setup_tc            = mlx5e_ndo_setup_tc,
2943         .ndo_select_queue        = mlx5e_select_queue,
2944         .ndo_get_stats64         = mlx5e_get_stats,
2945         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
2946         .ndo_set_mac_address     = mlx5e_set_mac,
2947         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
2948         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
2949         .ndo_set_features        = mlx5e_set_features,
2950         .ndo_change_mtu          = mlx5e_change_mtu,
2951         .ndo_do_ioctl            = mlx5e_ioctl,
2952         .ndo_udp_tunnel_add      = mlx5e_add_vxlan_port,
2953         .ndo_udp_tunnel_del      = mlx5e_del_vxlan_port,
2954         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
2955         .ndo_features_check      = mlx5e_features_check,
2956 #ifdef CONFIG_RFS_ACCEL
2957         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
2958 #endif
2959         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
2960         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
2961         .ndo_set_vf_spoofchk     = mlx5e_set_vf_spoofchk,
2962         .ndo_set_vf_trust        = mlx5e_set_vf_trust,
2963         .ndo_get_vf_config       = mlx5e_get_vf_config,
2964         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
2965         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
2966         .ndo_tx_timeout          = mlx5e_tx_timeout,
2967 };
2968
2969 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2970 {
2971         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2972                 return -ENOTSUPP;
2973         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
2974             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
2975             !MLX5_CAP_ETH(mdev, csum_cap) ||
2976             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
2977             !MLX5_CAP_ETH(mdev, vlan_cap) ||
2978             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
2979             MLX5_CAP_FLOWTABLE(mdev,
2980                                flow_table_properties_nic_receive.max_ft_level)
2981                                < 3) {
2982                 mlx5_core_warn(mdev,
2983                                "Not creating net device, some required device capabilities are missing\n");
2984                 return -ENOTSUPP;
2985         }
2986         if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
2987                 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
2988         if (!MLX5_CAP_GEN(mdev, cq_moderation))
2989                 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
2990
2991         return 0;
2992 }
2993
2994 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
2995 {
2996         int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
2997
2998         return bf_buf_size -
2999                sizeof(struct mlx5e_tx_wqe) +
3000                2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
3001 }
3002
3003 #ifdef CONFIG_MLX5_CORE_EN_DCB
3004 static void mlx5e_ets_init(struct mlx5e_priv *priv)
3005 {
3006         int i;
3007
3008         priv->params.ets.ets_cap = mlx5_max_tc(priv->mdev) + 1;
3009         for (i = 0; i < priv->params.ets.ets_cap; i++) {
3010                 priv->params.ets.tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
3011                 priv->params.ets.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
3012                 priv->params.ets.prio_tc[i] = i;
3013         }
3014
3015         /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */
3016         priv->params.ets.prio_tc[0] = 1;
3017         priv->params.ets.prio_tc[1] = 0;
3018 }
3019 #endif
3020
3021 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
3022                                    u32 *indirection_rqt, int len,
3023                                    int num_channels)
3024 {
3025         int node = mdev->priv.numa_node;
3026         int node_num_of_cores;
3027         int i;
3028
3029         if (node == -1)
3030                 node = first_online_node;
3031
3032         node_num_of_cores = cpumask_weight(cpumask_of_node(node));
3033
3034         if (node_num_of_cores)
3035                 num_channels = min_t(int, num_channels, node_num_of_cores);
3036
3037         for (i = 0; i < len; i++)
3038                 indirection_rqt[i] = i % num_channels;
3039 }
3040
3041 static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
3042 {
3043         return MLX5_CAP_GEN(mdev, striding_rq) &&
3044                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
3045                 MLX5_CAP_ETH(mdev, reg_umr_sq);
3046 }
3047
3048 static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
3049 {
3050         enum pcie_link_width width;
3051         enum pci_bus_speed speed;
3052         int err = 0;
3053
3054         err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
3055         if (err)
3056                 return err;
3057
3058         if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
3059                 return -EINVAL;
3060
3061         switch (speed) {
3062         case PCIE_SPEED_2_5GT:
3063                 *pci_bw = 2500 * width;
3064                 break;
3065         case PCIE_SPEED_5_0GT:
3066                 *pci_bw = 5000 * width;
3067                 break;
3068         case PCIE_SPEED_8_0GT:
3069                 *pci_bw = 8000 * width;
3070                 break;
3071         default:
3072                 return -EINVAL;
3073         }
3074
3075         return 0;
3076 }
3077
3078 static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
3079 {
3080         return (link_speed && pci_bw &&
3081                 (pci_bw < 40000) && (pci_bw < link_speed));
3082 }
3083
3084 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
3085 {
3086         params->rx_cq_period_mode = cq_period_mode;
3087
3088         params->rx_cq_moderation.pkts =
3089                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
3090         params->rx_cq_moderation.usec =
3091                         MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
3092
3093         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
3094                 params->rx_cq_moderation.usec =
3095                         MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
3096 }
3097
3098 static void mlx5e_query_min_inline(struct mlx5_core_dev *mdev,
3099                                    u8 *min_inline_mode)
3100 {
3101         switch (MLX5_CAP_ETH(mdev, wqe_inline_mode)) {
3102         case MLX5E_INLINE_MODE_L2:
3103                 *min_inline_mode = MLX5_INLINE_MODE_L2;
3104                 break;
3105         case MLX5E_INLINE_MODE_VPORT_CONTEXT:
3106                 mlx5_query_nic_vport_min_inline(mdev,
3107                                                 min_inline_mode);
3108                 break;
3109         case MLX5_INLINE_MODE_NOT_REQUIRED:
3110                 *min_inline_mode = MLX5_INLINE_MODE_NONE;
3111                 break;
3112         }
3113 }
3114
3115 static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
3116                                         struct net_device *netdev,
3117                                         const struct mlx5e_profile *profile,
3118                                         void *ppriv)
3119 {
3120         struct mlx5e_priv *priv = netdev_priv(netdev);
3121         u32 link_speed = 0;
3122         u32 pci_bw = 0;
3123         u8 cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
3124                                          MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
3125                                          MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
3126
3127         priv->params.log_sq_size           =
3128                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
3129         priv->params.rq_wq_type = mlx5e_check_fragmented_striding_rq_cap(mdev) ?
3130                 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
3131                 MLX5_WQ_TYPE_LINKED_LIST;
3132
3133         /* set CQE compression */
3134         priv->params.rx_cqe_compress_admin = false;
3135         if (MLX5_CAP_GEN(mdev, cqe_compression) &&
3136             MLX5_CAP_GEN(mdev, vport_group_manager)) {
3137                 mlx5e_get_max_linkspeed(mdev, &link_speed);
3138                 mlx5e_get_pci_bw(mdev, &pci_bw);
3139                 mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
3140                               link_speed, pci_bw);
3141                 priv->params.rx_cqe_compress_admin =
3142                         cqe_compress_heuristic(link_speed, pci_bw);
3143         }
3144
3145         priv->params.rx_cqe_compress = priv->params.rx_cqe_compress_admin;
3146
3147         switch (priv->params.rq_wq_type) {
3148         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
3149                 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
3150                 priv->params.mpwqe_log_stride_sz =
3151                         priv->params.rx_cqe_compress ?
3152                         MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS :
3153                         MLX5_MPWRQ_LOG_STRIDE_SIZE;
3154                 priv->params.mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
3155                         priv->params.mpwqe_log_stride_sz;
3156                 priv->params.lro_en = true;
3157                 break;
3158         default: /* MLX5_WQ_TYPE_LINKED_LIST */
3159                 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
3160         }
3161
3162         mlx5_core_info(mdev,
3163                        "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
3164                        priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
3165                        BIT(priv->params.log_rq_size),
3166                        BIT(priv->params.mpwqe_log_stride_sz),
3167                        priv->params.rx_cqe_compress_admin);
3168
3169         priv->params.min_rx_wqes = mlx5_min_rx_wqes(priv->params.rq_wq_type,
3170                                             BIT(priv->params.log_rq_size));
3171
3172         priv->params.rx_am_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
3173         mlx5e_set_rx_cq_mode_params(&priv->params, cq_period_mode);
3174
3175         priv->params.tx_cq_moderation.usec =
3176                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3177         priv->params.tx_cq_moderation.pkts =
3178                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
3179         priv->params.tx_max_inline         = mlx5e_get_max_inline_cap(mdev);
3180         mlx5e_query_min_inline(mdev, &priv->params.tx_min_inline_mode);
3181         priv->params.num_tc                = 1;
3182         priv->params.rss_hfunc             = ETH_RSS_HASH_XOR;
3183
3184         netdev_rss_key_fill(priv->params.toeplitz_hash_key,
3185                             sizeof(priv->params.toeplitz_hash_key));
3186
3187         mlx5e_build_default_indir_rqt(mdev, priv->params.indirection_rqt,
3188                                       MLX5E_INDIR_RQT_SIZE, profile->max_nch(mdev));
3189
3190         priv->params.lro_wqe_sz            =
3191                 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
3192
3193         /* Initialize pflags */
3194         MLX5E_SET_PRIV_FLAG(priv, MLX5E_PFLAG_RX_CQE_BASED_MODER,
3195                             priv->params.rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
3196
3197         priv->mdev                         = mdev;
3198         priv->netdev                       = netdev;
3199         priv->params.num_channels          = profile->max_nch(mdev);
3200         priv->profile                      = profile;
3201         priv->ppriv                        = ppriv;
3202
3203 #ifdef CONFIG_MLX5_CORE_EN_DCB
3204         mlx5e_ets_init(priv);
3205 #endif
3206
3207         mutex_init(&priv->state_lock);
3208
3209         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3210         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3211         INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
3212         INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3213 }
3214
3215 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
3216 {
3217         struct mlx5e_priv *priv = netdev_priv(netdev);
3218
3219         mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
3220         if (is_zero_ether_addr(netdev->dev_addr) &&
3221             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
3222                 eth_hw_addr_random(netdev);
3223                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
3224         }
3225 }
3226
3227 static const struct switchdev_ops mlx5e_switchdev_ops = {
3228         .switchdev_port_attr_get        = mlx5e_attr_get,
3229 };
3230
3231 static void mlx5e_build_nic_netdev(struct net_device *netdev)
3232 {
3233         struct mlx5e_priv *priv = netdev_priv(netdev);
3234         struct mlx5_core_dev *mdev = priv->mdev;
3235         bool fcs_supported;
3236         bool fcs_enabled;
3237
3238         SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
3239
3240         if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
3241                 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
3242 #ifdef CONFIG_MLX5_CORE_EN_DCB
3243                 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
3244 #endif
3245         } else {
3246                 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
3247         }
3248
3249         netdev->watchdog_timeo    = 15 * HZ;
3250
3251         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
3252
3253         netdev->vlan_features    |= NETIF_F_SG;
3254         netdev->vlan_features    |= NETIF_F_IP_CSUM;
3255         netdev->vlan_features    |= NETIF_F_IPV6_CSUM;
3256         netdev->vlan_features    |= NETIF_F_GRO;
3257         netdev->vlan_features    |= NETIF_F_TSO;
3258         netdev->vlan_features    |= NETIF_F_TSO6;
3259         netdev->vlan_features    |= NETIF_F_RXCSUM;
3260         netdev->vlan_features    |= NETIF_F_RXHASH;
3261
3262         if (!!MLX5_CAP_ETH(mdev, lro_cap))
3263                 netdev->vlan_features    |= NETIF_F_LRO;
3264
3265         netdev->hw_features       = netdev->vlan_features;
3266         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
3267         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
3268         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
3269
3270         if (mlx5e_vxlan_allowed(mdev)) {
3271                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL |
3272                                            NETIF_F_GSO_UDP_TUNNEL_CSUM |
3273                                            NETIF_F_GSO_PARTIAL;
3274                 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
3275                 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
3276                 netdev->hw_enc_features |= NETIF_F_TSO;
3277                 netdev->hw_enc_features |= NETIF_F_TSO6;
3278                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
3279                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM |
3280                                            NETIF_F_GSO_PARTIAL;
3281                 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
3282         }
3283
3284         mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
3285
3286         if (fcs_supported)
3287                 netdev->hw_features |= NETIF_F_RXALL;
3288
3289         netdev->features          = netdev->hw_features;
3290         if (!priv->params.lro_en)
3291                 netdev->features  &= ~NETIF_F_LRO;
3292
3293         if (fcs_enabled)
3294                 netdev->features  &= ~NETIF_F_RXALL;
3295
3296 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
3297         if (FT_CAP(flow_modify_en) &&
3298             FT_CAP(modify_root) &&
3299             FT_CAP(identified_miss_table_mode) &&
3300             FT_CAP(flow_table_modify)) {
3301                 netdev->hw_features      |= NETIF_F_HW_TC;
3302 #ifdef CONFIG_RFS_ACCEL
3303                 netdev->hw_features      |= NETIF_F_NTUPLE;
3304 #endif
3305         }
3306
3307         netdev->features         |= NETIF_F_HIGHDMA;
3308
3309         netdev->priv_flags       |= IFF_UNICAST_FLT;
3310
3311         mlx5e_set_netdev_dev_addr(netdev);
3312
3313 #ifdef CONFIG_NET_SWITCHDEV
3314         if (MLX5_CAP_GEN(mdev, vport_group_manager))
3315                 netdev->switchdev_ops = &mlx5e_switchdev_ops;
3316 #endif
3317 }
3318
3319 static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
3320 {
3321         struct mlx5_core_dev *mdev = priv->mdev;
3322         int err;
3323
3324         err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
3325         if (err) {
3326                 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
3327                 priv->q_counter = 0;
3328         }
3329 }
3330
3331 static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
3332 {
3333         if (!priv->q_counter)
3334                 return;
3335
3336         mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
3337 }
3338
3339 static int mlx5e_create_umr_mkey(struct mlx5e_priv *priv)
3340 {
3341         struct mlx5_core_dev *mdev = priv->mdev;
3342         u64 npages = MLX5E_REQUIRED_MTTS(priv->profile->max_nch(mdev),
3343                                          BIT(MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE_MPW));
3344         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
3345         void *mkc;
3346         u32 *in;
3347         int err;
3348
3349         in = mlx5_vzalloc(inlen);
3350         if (!in)
3351                 return -ENOMEM;
3352
3353         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
3354
3355         npages = min_t(u32, ALIGN(U16_MAX, 4) * 2, npages);
3356
3357         MLX5_SET(mkc, mkc, free, 1);
3358         MLX5_SET(mkc, mkc, umr_en, 1);
3359         MLX5_SET(mkc, mkc, lw, 1);
3360         MLX5_SET(mkc, mkc, lr, 1);
3361         MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_MTT);
3362
3363         MLX5_SET(mkc, mkc, qpn, 0xffffff);
3364         MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
3365         MLX5_SET64(mkc, mkc, len, npages << PAGE_SHIFT);
3366         MLX5_SET(mkc, mkc, translations_octword_size,
3367                  MLX5_MTT_OCTW(npages));
3368         MLX5_SET(mkc, mkc, log_page_size, PAGE_SHIFT);
3369
3370         err = mlx5_core_create_mkey(mdev, &priv->umr_mkey, in, inlen);
3371
3372         kvfree(in);
3373         return err;
3374 }
3375
3376 static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
3377                            struct net_device *netdev,
3378                            const struct mlx5e_profile *profile,
3379                            void *ppriv)
3380 {
3381         struct mlx5e_priv *priv = netdev_priv(netdev);
3382
3383         mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv);
3384         mlx5e_build_nic_netdev(netdev);
3385         mlx5e_vxlan_init(priv);
3386 }
3387
3388 static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
3389 {
3390         struct mlx5_core_dev *mdev = priv->mdev;
3391         struct mlx5_eswitch *esw = mdev->priv.eswitch;
3392
3393         mlx5e_vxlan_cleanup(priv);
3394
3395         if (MLX5_CAP_GEN(mdev, vport_group_manager))
3396                 mlx5_eswitch_unregister_vport_rep(esw, 0);
3397 }
3398
3399 static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
3400 {
3401         struct mlx5_core_dev *mdev = priv->mdev;
3402         int err;
3403         int i;
3404
3405         err = mlx5e_create_indirect_rqts(priv);
3406         if (err) {
3407                 mlx5_core_warn(mdev, "create indirect rqts failed, %d\n", err);
3408                 return err;
3409         }
3410
3411         err = mlx5e_create_direct_rqts(priv);
3412         if (err) {
3413                 mlx5_core_warn(mdev, "create direct rqts failed, %d\n", err);
3414                 goto err_destroy_indirect_rqts;
3415         }
3416
3417         err = mlx5e_create_indirect_tirs(priv);
3418         if (err) {
3419                 mlx5_core_warn(mdev, "create indirect tirs failed, %d\n", err);
3420                 goto err_destroy_direct_rqts;
3421         }
3422
3423         err = mlx5e_create_direct_tirs(priv);
3424         if (err) {
3425                 mlx5_core_warn(mdev, "create direct tirs failed, %d\n", err);
3426                 goto err_destroy_indirect_tirs;
3427         }
3428
3429         err = mlx5e_create_flow_steering(priv);
3430         if (err) {
3431                 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
3432                 goto err_destroy_direct_tirs;
3433         }
3434
3435         err = mlx5e_tc_init(priv);
3436         if (err)
3437                 goto err_destroy_flow_steering;
3438
3439         return 0;
3440
3441 err_destroy_flow_steering:
3442         mlx5e_destroy_flow_steering(priv);
3443 err_destroy_direct_tirs:
3444         mlx5e_destroy_direct_tirs(priv);
3445 err_destroy_indirect_tirs:
3446         mlx5e_destroy_indirect_tirs(priv);
3447 err_destroy_direct_rqts:
3448         for (i = 0; i < priv->profile->max_nch(mdev); i++)
3449                 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
3450 err_destroy_indirect_rqts:
3451         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
3452         return err;
3453 }
3454
3455 static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
3456 {
3457         int i;
3458
3459         mlx5e_tc_cleanup(priv);
3460         mlx5e_destroy_flow_steering(priv);
3461         mlx5e_destroy_direct_tirs(priv);
3462         mlx5e_destroy_indirect_tirs(priv);
3463         for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
3464                 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
3465         mlx5e_destroy_rqt(priv, &priv->indir_rqt);
3466 }
3467
3468 static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
3469 {
3470         int err;
3471
3472         err = mlx5e_create_tises(priv);
3473         if (err) {
3474                 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
3475                 return err;
3476         }
3477
3478 #ifdef CONFIG_MLX5_CORE_EN_DCB
3479         mlx5e_dcbnl_ieee_setets_core(priv, &priv->params.ets);
3480 #endif
3481         return 0;
3482 }
3483
3484 static void mlx5e_nic_enable(struct mlx5e_priv *priv)
3485 {
3486         struct net_device *netdev = priv->netdev;
3487         struct mlx5_core_dev *mdev = priv->mdev;
3488         struct mlx5_eswitch *esw = mdev->priv.eswitch;
3489         struct mlx5_eswitch_rep rep;
3490
3491         mlx5_lag_add(mdev, netdev);
3492
3493         if (mlx5e_vxlan_allowed(mdev)) {
3494                 rtnl_lock();
3495                 udp_tunnel_get_rx_info(netdev);
3496                 rtnl_unlock();
3497         }
3498
3499         mlx5e_enable_async_events(priv);
3500         queue_work(priv->wq, &priv->set_rx_mode_work);
3501
3502         if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
3503                 mlx5_query_nic_vport_mac_address(mdev, 0, rep.hw_id);
3504                 rep.load = mlx5e_nic_rep_load;
3505                 rep.unload = mlx5e_nic_rep_unload;
3506                 rep.vport = 0;
3507                 rep.priv_data = priv;
3508                 mlx5_eswitch_register_vport_rep(esw, &rep);
3509         }
3510 }
3511
3512 static void mlx5e_nic_disable(struct mlx5e_priv *priv)
3513 {
3514         queue_work(priv->wq, &priv->set_rx_mode_work);
3515         mlx5e_disable_async_events(priv);
3516         mlx5_lag_remove(priv->mdev);
3517 }
3518
3519 static const struct mlx5e_profile mlx5e_nic_profile = {
3520         .init              = mlx5e_nic_init,
3521         .cleanup           = mlx5e_nic_cleanup,
3522         .init_rx           = mlx5e_init_nic_rx,
3523         .cleanup_rx        = mlx5e_cleanup_nic_rx,
3524         .init_tx           = mlx5e_init_nic_tx,
3525         .cleanup_tx        = mlx5e_cleanup_nic_tx,
3526         .enable            = mlx5e_nic_enable,
3527         .disable           = mlx5e_nic_disable,
3528         .update_stats      = mlx5e_update_stats,
3529         .max_nch           = mlx5e_get_max_num_channels,
3530         .max_tc            = MLX5E_MAX_NUM_TC,
3531 };
3532
3533 struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
3534                                        const struct mlx5e_profile *profile,
3535                                        void *ppriv)
3536 {
3537         int nch = profile->max_nch(mdev);
3538         struct net_device *netdev;
3539         struct mlx5e_priv *priv;
3540
3541         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
3542                                     nch * profile->max_tc,
3543                                     nch);
3544         if (!netdev) {
3545                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
3546                 return NULL;
3547         }
3548
3549         profile->init(mdev, netdev, profile, ppriv);
3550
3551         netif_carrier_off(netdev);
3552
3553         priv = netdev_priv(netdev);
3554
3555         priv->wq = create_singlethread_workqueue("mlx5e");
3556         if (!priv->wq)
3557                 goto err_cleanup_nic;
3558
3559         return netdev;
3560
3561 err_cleanup_nic:
3562         profile->cleanup(priv);
3563         free_netdev(netdev);
3564
3565         return NULL;
3566 }
3567
3568 int mlx5e_attach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev)
3569 {
3570         const struct mlx5e_profile *profile;
3571         struct mlx5e_priv *priv;
3572         int err;
3573
3574         priv = netdev_priv(netdev);
3575         profile = priv->profile;
3576         clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
3577
3578         err = mlx5e_create_umr_mkey(priv);
3579         if (err) {
3580                 mlx5_core_err(mdev, "create umr mkey failed, %d\n", err);
3581                 goto out;
3582         }
3583
3584         err = profile->init_tx(priv);
3585         if (err)
3586                 goto err_destroy_umr_mkey;
3587
3588         err = mlx5e_open_drop_rq(priv);
3589         if (err) {
3590                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
3591                 goto err_cleanup_tx;
3592         }
3593
3594         err = profile->init_rx(priv);
3595         if (err)
3596                 goto err_close_drop_rq;
3597
3598         mlx5e_create_q_counter(priv);
3599
3600         mlx5e_init_l2_addr(priv);
3601
3602         mlx5e_set_dev_port_mtu(netdev);
3603
3604         if (profile->enable)
3605                 profile->enable(priv);
3606
3607         rtnl_lock();
3608         if (netif_running(netdev))
3609                 mlx5e_open(netdev);
3610         netif_device_attach(netdev);
3611         rtnl_unlock();
3612
3613         return 0;
3614
3615 err_close_drop_rq:
3616         mlx5e_close_drop_rq(priv);
3617
3618 err_cleanup_tx:
3619         profile->cleanup_tx(priv);
3620
3621 err_destroy_umr_mkey:
3622         mlx5_core_destroy_mkey(mdev, &priv->umr_mkey);
3623
3624 out:
3625         return err;
3626 }
3627
3628 static void mlx5e_register_vport_rep(struct mlx5_core_dev *mdev)
3629 {
3630         struct mlx5_eswitch *esw = mdev->priv.eswitch;
3631         int total_vfs = MLX5_TOTAL_VPORTS(mdev);
3632         int vport;
3633         u8 mac[ETH_ALEN];
3634
3635         if (!MLX5_CAP_GEN(mdev, vport_group_manager))
3636                 return;
3637
3638         mlx5_query_nic_vport_mac_address(mdev, 0, mac);
3639
3640         for (vport = 1; vport < total_vfs; vport++) {
3641                 struct mlx5_eswitch_rep rep;
3642
3643                 rep.load = mlx5e_vport_rep_load;
3644                 rep.unload = mlx5e_vport_rep_unload;
3645                 rep.vport = vport;
3646                 ether_addr_copy(rep.hw_id, mac);
3647                 mlx5_eswitch_register_vport_rep(esw, &rep);
3648         }
3649 }
3650
3651 void mlx5e_detach_netdev(struct mlx5_core_dev *mdev, struct net_device *netdev)
3652 {
3653         struct mlx5e_priv *priv = netdev_priv(netdev);
3654         const struct mlx5e_profile *profile = priv->profile;
3655
3656         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
3657         if (profile->disable)
3658                 profile->disable(priv);
3659
3660         flush_workqueue(priv->wq);
3661
3662         rtnl_lock();
3663         if (netif_running(netdev))
3664                 mlx5e_close(netdev);
3665         netif_device_detach(netdev);
3666         rtnl_unlock();
3667
3668         mlx5e_destroy_q_counter(priv);
3669         profile->cleanup_rx(priv);
3670         mlx5e_close_drop_rq(priv);
3671         profile->cleanup_tx(priv);
3672         mlx5_core_destroy_mkey(priv->mdev, &priv->umr_mkey);
3673         cancel_delayed_work_sync(&priv->update_stats_work);
3674 }
3675
3676 /* mlx5e_attach and mlx5e_detach scope should be only creating/destroying
3677  * hardware contexts and to connect it to the current netdev.
3678  */
3679 static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
3680 {
3681         struct mlx5e_priv *priv = vpriv;
3682         struct net_device *netdev = priv->netdev;
3683         int err;
3684
3685         if (netif_device_present(netdev))
3686                 return 0;
3687
3688         err = mlx5e_create_mdev_resources(mdev);
3689         if (err)
3690                 return err;
3691
3692         err = mlx5e_attach_netdev(mdev, netdev);
3693         if (err) {
3694                 mlx5e_destroy_mdev_resources(mdev);
3695                 return err;
3696         }
3697
3698         return 0;
3699 }
3700
3701 static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
3702 {
3703         struct mlx5e_priv *priv = vpriv;
3704         struct net_device *netdev = priv->netdev;
3705
3706         if (!netif_device_present(netdev))
3707                 return;
3708
3709         mlx5e_detach_netdev(mdev, netdev);
3710         mlx5e_destroy_mdev_resources(mdev);
3711 }
3712
3713 static void *mlx5e_add(struct mlx5_core_dev *mdev)
3714 {
3715         struct mlx5_eswitch *esw = mdev->priv.eswitch;
3716         int total_vfs = MLX5_TOTAL_VPORTS(mdev);
3717         void *ppriv = NULL;
3718         void *priv;
3719         int vport;
3720         int err;
3721         struct net_device *netdev;
3722
3723         err = mlx5e_check_required_hca_cap(mdev);
3724         if (err)
3725                 return NULL;
3726
3727         mlx5e_register_vport_rep(mdev);
3728
3729         if (MLX5_CAP_GEN(mdev, vport_group_manager))
3730                 ppriv = &esw->offloads.vport_reps[0];
3731
3732         netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, ppriv);
3733         if (!netdev) {
3734                 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
3735                 goto err_unregister_reps;
3736         }
3737
3738         priv = netdev_priv(netdev);
3739
3740         err = mlx5e_attach(mdev, priv);
3741         if (err) {
3742                 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
3743                 goto err_destroy_netdev;
3744         }
3745
3746         err = register_netdev(netdev);
3747         if (err) {
3748                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
3749                 goto err_detach;
3750         }
3751
3752         return priv;
3753
3754 err_detach:
3755         mlx5e_detach(mdev, priv);
3756
3757 err_destroy_netdev:
3758         mlx5e_destroy_netdev(mdev, priv);
3759
3760 err_unregister_reps:
3761         for (vport = 1; vport < total_vfs; vport++)
3762                 mlx5_eswitch_unregister_vport_rep(esw, vport);
3763
3764         return NULL;
3765 }
3766
3767 void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, struct mlx5e_priv *priv)
3768 {
3769         const struct mlx5e_profile *profile = priv->profile;
3770         struct net_device *netdev = priv->netdev;
3771
3772         unregister_netdev(netdev);
3773         destroy_workqueue(priv->wq);
3774         if (profile->cleanup)
3775                 profile->cleanup(priv);
3776         free_netdev(netdev);
3777 }
3778
3779 static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
3780 {
3781         struct mlx5_eswitch *esw = mdev->priv.eswitch;
3782         int total_vfs = MLX5_TOTAL_VPORTS(mdev);
3783         struct mlx5e_priv *priv = vpriv;
3784         int vport;
3785
3786         for (vport = 1; vport < total_vfs; vport++)
3787                 mlx5_eswitch_unregister_vport_rep(esw, vport);
3788
3789         mlx5e_detach(mdev, vpriv);
3790         mlx5e_destroy_netdev(mdev, priv);
3791 }
3792
3793 static void *mlx5e_get_netdev(void *vpriv)
3794 {
3795         struct mlx5e_priv *priv = vpriv;
3796
3797         return priv->netdev;
3798 }
3799
3800 static struct mlx5_interface mlx5e_interface = {
3801         .add       = mlx5e_add,
3802         .remove    = mlx5e_remove,
3803         .attach    = mlx5e_attach,
3804         .detach    = mlx5e_detach,
3805         .event     = mlx5e_async_event,
3806         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
3807         .get_dev   = mlx5e_get_netdev,
3808 };
3809
3810 void mlx5e_init(void)
3811 {
3812         mlx5e_build_ptys2ethtool_map();
3813         mlx5_register_interface(&mlx5e_interface);
3814 }
3815
3816 void mlx5e_cleanup(void)
3817 {
3818         mlx5_unregister_interface(&mlx5e_interface);
3819 }