drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include "en.h"
  38 #include "en_tc.h"
  39 #include "eswitch.h"
  40 #include "vxlan.h"
  41
  42 struct mlx5e_rq_param {
  43         u32                     rqc[MLX5_ST_SZ_DW(rqc)];
  44         struct mlx5_wq_param    wq;
  45         bool                    am_enabled;
  46 };
  47
  48 struct mlx5e_sq_param {
  49         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
  50         struct mlx5_wq_param       wq;
  51         u16                        max_inline;
  52         bool                       icosq;
  53 };
  54
  55 struct mlx5e_cq_param {
  56         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
  57         struct mlx5_wq_param       wq;
  58         u16                        eq_ix;
  59         u8                         cq_period_mode;
  60 };
  61
  62 struct mlx5e_channel_param {
  63         struct mlx5e_rq_param      rq;
  64         struct mlx5e_sq_param      sq;
  65         struct mlx5e_sq_param      icosq;
  66         struct mlx5e_cq_param      rx_cq;
  67         struct mlx5e_cq_param      tx_cq;
  68         struct mlx5e_cq_param      icosq_cq;
  69 };
  70
  71 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
  72 {
  73         struct mlx5_core_dev *mdev = priv->mdev;
  74         u8 port_state;
  75
  76         port_state = mlx5_query_vport_state(mdev,
  77                 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
  78
  79         if (port_state == VPORT_STATE_UP)
  80                 netif_carrier_on(priv->netdev);
  81         else
  82                 netif_carrier_off(priv->netdev);
  83 }
  84
  85 static void mlx5e_update_carrier_work(struct work_struct *work)
  86 {
  87         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
  88                                                update_carrier_work);
  89
  90         mutex_lock(&priv->state_lock);
  91         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
  92                 mlx5e_update_carrier(priv);
  93         mutex_unlock(&priv->state_lock);
  94 }
  95
  96 static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
  97 {
  98         struct mlx5e_sw_stats *s = &priv->stats.sw;
  99         struct mlx5e_rq_stats *rq_stats;
 100         struct mlx5e_sq_stats *sq_stats;
 101         u64 tx_offload_none = 0;
 102         int i, j;
 103
 104         memset(s, 0, sizeof(*s));
 105         for (i = 0; i < priv->params.num_channels; i++) {
 106                 rq_stats = &priv->channel[i]->rq.stats;
 107
 108                 s->rx_packets   += rq_stats->packets;
 109                 s->rx_bytes     += rq_stats->bytes;
 110                 s->lro_packets  += rq_stats->lro_packets;
 111                 s->lro_bytes    += rq_stats->lro_bytes;
 112                 s->rx_csum_none += rq_stats->csum_none;
 113                 s->rx_csum_sw   += rq_stats->csum_sw;
 114                 s->rx_csum_inner += rq_stats->csum_inner;
 115                 s->rx_wqe_err   += rq_stats->wqe_err;
 116                 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
 117                 s->rx_mpwqe_frag   += rq_stats->mpwqe_frag;
 118                 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
 119                 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
 120                 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
 121
 122                 for (j = 0; j < priv->params.num_tc; j++) {
 123                         sq_stats = &priv->channel[i]->sq[j].stats;
 124
 125                         s->tx_packets           += sq_stats->packets;
 126                         s->tx_bytes             += sq_stats->bytes;
 127                         s->tso_packets          += sq_stats->tso_packets;
 128                         s->tso_bytes            += sq_stats->tso_bytes;
 129                         s->tso_inner_packets    += sq_stats->tso_inner_packets;
 130                         s->tso_inner_bytes      += sq_stats->tso_inner_bytes;
 131                         s->tx_queue_stopped     += sq_stats->stopped;
 132                         s->tx_queue_wake        += sq_stats->wake;
 133                         s->tx_queue_dropped     += sq_stats->dropped;
 134                         s->tx_csum_inner        += sq_stats->csum_offload_inner;
 135                         tx_offload_none         += sq_stats->csum_offload_none;
 136                 }
 137         }
 138
 139         /* Update calculated offload counters */
 140         s->tx_csum_offload = s->tx_packets - tx_offload_none - s->tx_csum_inner;
 141         s->rx_csum_good    = s->rx_packets - s->rx_csum_none -
 142                              s->rx_csum_sw;
 143
 144         s->link_down_events = MLX5_GET(ppcnt_reg,
 145                                 priv->stats.pport.phy_counters,
 146                                 counter_set.phys_layer_cntrs.link_down_events);
 147 }
 148
 149 static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
 150 {
 151         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
 152         u32 *out = (u32 *)priv->stats.vport.query_vport_out;
 153         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
 154         struct mlx5_core_dev *mdev = priv->mdev;
 155
 156         memset(in, 0, sizeof(in));
 157
 158         MLX5_SET(query_vport_counter_in, in, opcode,
 159                  MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 160         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 161         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 162
 163         memset(out, 0, outlen);
 164
 165         mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
 166 }
 167
 168 static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
 169 {
 170         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
 171         struct mlx5_core_dev *mdev = priv->mdev;
 172         int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
 173         int prio;
 174         void *out;
 175         u32 *in;
 176
 177         in = mlx5_vzalloc(sz);
 178         if (!in)
 179                 goto free_out;
 180
 181         MLX5_SET(ppcnt_reg, in, local_port, 1);
 182
 183         out = pstats->IEEE_802_3_counters;
 184         MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
 185         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 186
 187         out = pstats->RFC_2863_counters;
 188         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
 189         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 190
 191         out = pstats->RFC_2819_counters;
 192         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
 193         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 194
 195         out = pstats->phy_counters;
 196         MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
 197         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 198
 199         MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
 200         for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
 201                 out = pstats->per_prio_counters[prio];
 202                 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
 203                 mlx5_core_access_reg(mdev, in, sz, out, sz,
 204                                      MLX5_REG_PPCNT, 0, 0);
 205         }
 206
 207 free_out:
 208         kvfree(in);
 209 }
 210
 211 static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
 212 {
 213         struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
 214
 215         if (!priv->q_counter)
 216                 return;
 217
 218         mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
 219                                       &qcnt->rx_out_of_buffer);
 220 }
 221
 222 void mlx5e_update_stats(struct mlx5e_priv *priv)
 223 {
 224         mlx5e_update_q_counter(priv);
 225         mlx5e_update_vport_counters(priv);
 226         mlx5e_update_pport_counters(priv);
 227         mlx5e_update_sw_counters(priv);
 228 }
 229
 230 static void mlx5e_update_stats_work(struct work_struct *work)
 231 {
 232         struct delayed_work *dwork = to_delayed_work(work);
 233         struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
 234                                                update_stats_work);
 235         mutex_lock(&priv->state_lock);
 236         if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
 237                 mlx5e_update_stats(priv);
 238                 queue_delayed_work(priv->wq, dwork,
 239                                    msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
 240         }
 241         mutex_unlock(&priv->state_lock);
 242 }
 243
 244 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 245                               enum mlx5_dev_event event, unsigned long param)
 246 {
 247         struct mlx5e_priv *priv = vpriv;
 248
 249         if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
 250                 return;
 251
 252         switch (event) {
 253         case MLX5_DEV_EVENT_PORT_UP:
 254         case MLX5_DEV_EVENT_PORT_DOWN:
 255                 queue_work(priv->wq, &priv->update_carrier_work);
 256                 break;
 257
 258         default:
 259                 break;
 260         }
 261 }
 262
 263 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 264 {
 265         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 266 }
 267
 268 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 269 {
 270         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 271         synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
 272 }
 273
 274 #define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 275 #define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 276
 277 static int mlx5e_create_rq(struct mlx5e_channel *c,
 278                            struct mlx5e_rq_param *param,
 279                            struct mlx5e_rq *rq)
 280 {
 281         struct mlx5e_priv *priv = c->priv;
 282         struct mlx5_core_dev *mdev = priv->mdev;
 283         void *rqc = param->rqc;
 284         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 285         u32 byte_count;
 286         int wq_sz;
 287         int err;
 288         int i;
 289
 290         param->wq.db_numa_node = cpu_to_node(c->cpu);
 291
 292         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
 293                                 &rq->wq_ctrl);
 294         if (err)
 295                 return err;
 296
 297         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
 298
 299         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 300
 301         switch (priv->params.rq_wq_type) {
 302         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 303                 rq->wqe_info = kzalloc_node(wq_sz * sizeof(*rq->wqe_info),
 304                                             GFP_KERNEL, cpu_to_node(c->cpu));
 305                 if (!rq->wqe_info) {
 306                         err = -ENOMEM;
 307                         goto err_rq_wq_destroy;
 308                 }
 309                 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_mpwrq;
 310                 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
 311
 312                 rq->mpwqe_stride_sz = BIT(priv->params.mpwqe_log_stride_sz);
 313                 rq->mpwqe_num_strides = BIT(priv->params.mpwqe_log_num_strides);
 314                 rq->wqe_sz = rq->mpwqe_stride_sz * rq->mpwqe_num_strides;
 315                 byte_count = rq->wqe_sz;
 316                 break;
 317         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 318                 rq->skb = kzalloc_node(wq_sz * sizeof(*rq->skb), GFP_KERNEL,
 319                                        cpu_to_node(c->cpu));
 320                 if (!rq->skb) {
 321                         err = -ENOMEM;
 322                         goto err_rq_wq_destroy;
 323                 }
 324                 rq->handle_rx_cqe = mlx5e_handle_rx_cqe;
 325                 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
 326
 327                 rq->wqe_sz = (priv->params.lro_en) ?
 328                                 priv->params.lro_wqe_sz :
 329                                 MLX5E_SW2HW_MTU(priv->netdev->mtu);
 330                 rq->wqe_sz = SKB_DATA_ALIGN(rq->wqe_sz);
 331                 byte_count = rq->wqe_sz;
 332                 byte_count |= MLX5_HW_START_PADDING;
 333         }
 334
 335         for (i = 0; i < wq_sz; i++) {
 336                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
 337
 338                 wqe->data.byte_count = cpu_to_be32(byte_count);
 339         }
 340
 341         INIT_WORK(&rq->am.work, mlx5e_rx_am_work);
 342         rq->am.mode = priv->params.rx_cq_period_mode;
 343
 344         rq->wq_type = priv->params.rq_wq_type;
 345         rq->pdev    = c->pdev;
 346         rq->netdev  = c->netdev;
 347         rq->tstamp  = &priv->tstamp;
 348         rq->channel = c;
 349         rq->ix      = c->ix;
 350         rq->priv    = c->priv;
 351         rq->mkey_be = c->mkey_be;
 352         rq->umr_mkey_be = cpu_to_be32(c->priv->umr_mkey.key);
 353
 354         return 0;
 355
 356 err_rq_wq_destroy:
 357         mlx5_wq_destroy(&rq->wq_ctrl);
 358
 359         return err;
 360 }
 361
 362 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 363 {
 364         switch (rq->wq_type) {
 365         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 366                 kfree(rq->wqe_info);
 367                 break;
 368         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 369                 kfree(rq->skb);
 370         }
 371
 372         mlx5_wq_destroy(&rq->wq_ctrl);
 373 }
 374
 375 static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 376 {
 377         struct mlx5e_priv *priv = rq->priv;
 378         struct mlx5_core_dev *mdev = priv->mdev;
 379
 380         void *in;
 381         void *rqc;
 382         void *wq;
 383         int inlen;
 384         int err;
 385
 386         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 387                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 388         in = mlx5_vzalloc(inlen);
 389         if (!in)
 390                 return -ENOMEM;
 391
 392         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 393         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 394
 395         memcpy(rqc, param->rqc, sizeof(param->rqc));
 396
 397         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 398         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 399         MLX5_SET(rqc,  rqc, flush_in_error_en,  1);
 400         MLX5_SET(rqc,  rqc, vsd, priv->params.vlan_strip_disable);
 401         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 402                                                 MLX5_ADAPTER_PAGE_SHIFT);
 403         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 404
 405         mlx5_fill_page_array(&rq->wq_ctrl.buf,
 406                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 407
 408         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 409
 410         kvfree(in);
 411
 412         return err;
 413 }
 414
 415 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
 416                                  int next_state)
 417 {
 418         struct mlx5e_channel *c = rq->channel;
 419         struct mlx5e_priv *priv = c->priv;
 420         struct mlx5_core_dev *mdev = priv->mdev;
 421
 422         void *in;
 423         void *rqc;
 424         int inlen;
 425         int err;
 426
 427         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 428         in = mlx5_vzalloc(inlen);
 429         if (!in)
 430                 return -ENOMEM;
 431
 432         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 433
 434         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 435         MLX5_SET(rqc, rqc, state, next_state);
 436
 437         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 438
 439         kvfree(in);
 440
 441         return err;
 442 }
 443
 444 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
 445 {
 446         struct mlx5e_channel *c = rq->channel;
 447         struct mlx5e_priv *priv = c->priv;
 448         struct mlx5_core_dev *mdev = priv->mdev;
 449
 450         void *in;
 451         void *rqc;
 452         int inlen;
 453         int err;
 454
 455         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 456         in = mlx5_vzalloc(inlen);
 457         if (!in)
 458                 return -ENOMEM;
 459
 460         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 461
 462         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 463         MLX5_SET64(modify_rq_in, in, modify_bitmask, MLX5_RQ_BITMASK_VSD);
 464         MLX5_SET(rqc, rqc, vsd, vsd);
 465         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 466
 467         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 468
 469         kvfree(in);
 470
 471         return err;
 472 }
 473
 474 static void mlx5e_disable_rq(struct mlx5e_rq *rq)
 475 {
 476         mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
 477 }
 478
 479 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
 480 {
 481         unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
 482         struct mlx5e_channel *c = rq->channel;
 483         struct mlx5e_priv *priv = c->priv;
 484         struct mlx5_wq_ll *wq = &rq->wq;
 485
 486         while (time_before(jiffies, exp_time)) {
 487                 if (wq->cur_sz >= priv->params.min_rx_wqes)
 488                         return 0;
 489
 490                 msleep(20);
 491         }
 492
 493         return -ETIMEDOUT;
 494 }
 495
 496 static int mlx5e_open_rq(struct mlx5e_channel *c,
 497                          struct mlx5e_rq_param *param,
 498                          struct mlx5e_rq *rq)
 499 {
 500         struct mlx5e_sq *sq = &c->icosq;
 501         u16 pi = sq->pc & sq->wq.sz_m1;
 502         int err;
 503
 504         err = mlx5e_create_rq(c, param, rq);
 505         if (err)
 506                 return err;
 507
 508         err = mlx5e_enable_rq(rq, param);
 509         if (err)
 510                 goto err_destroy_rq;
 511
 512         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 513         if (err)
 514                 goto err_disable_rq;
 515
 516         if (param->am_enabled)
 517                 set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);
 518
 519         set_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
 520
 521         sq->ico_wqe_info[pi].opcode     = MLX5_OPCODE_NOP;
 522         sq->ico_wqe_info[pi].num_wqebbs = 1;
 523         mlx5e_send_nop(sq, true); /* trigger mlx5e_post_rx_wqes() */
 524
 525         return 0;
 526
 527 err_disable_rq:
 528         mlx5e_disable_rq(rq);
 529 err_destroy_rq:
 530         mlx5e_destroy_rq(rq);
 531
 532         return err;
 533 }
 534
 535 static void mlx5e_close_rq(struct mlx5e_rq *rq)
 536 {
 537         clear_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
 538         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 539
 540         mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
 541         while (!mlx5_wq_ll_is_empty(&rq->wq))
 542                 msleep(20);
 543
 544         /* avoid destroying rq before mlx5e_poll_rx_cq() is done with it */
 545         napi_synchronize(&rq->channel->napi);
 546
 547         cancel_work_sync(&rq->am.work);
 548
 549         mlx5e_disable_rq(rq);
 550         mlx5e_destroy_rq(rq);
 551 }
 552
 553 static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
 554 {
 555         kfree(sq->wqe_info);
 556         kfree(sq->dma_fifo);
 557         kfree(sq->skb);
 558 }
 559
 560 static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
 561 {
 562         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 563         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
 564
 565         sq->skb = kzalloc_node(wq_sz * sizeof(*sq->skb), GFP_KERNEL, numa);
 566         sq->dma_fifo = kzalloc_node(df_sz * sizeof(*sq->dma_fifo), GFP_KERNEL,
 567                                     numa);
 568         sq->wqe_info = kzalloc_node(wq_sz * sizeof(*sq->wqe_info), GFP_KERNEL,
 569                                     numa);
 570
 571         if (!sq->skb || !sq->dma_fifo || !sq->wqe_info) {
 572                 mlx5e_free_sq_db(sq);
 573                 return -ENOMEM;
 574         }
 575
 576         sq->dma_fifo_mask = df_sz - 1;
 577
 578         return 0;
 579 }
 580
 581 static int mlx5e_create_sq(struct mlx5e_channel *c,
 582                            int tc,
 583                            struct mlx5e_sq_param *param,
 584                            struct mlx5e_sq *sq)
 585 {
 586         struct mlx5e_priv *priv = c->priv;
 587         struct mlx5_core_dev *mdev = priv->mdev;
 588
 589         void *sqc = param->sqc;
 590         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
 591         int err;
 592
 593         err = mlx5_alloc_map_uar(mdev, &sq->uar, true);
 594         if (err)
 595                 return err;
 596
 597         param->wq.db_numa_node = cpu_to_node(c->cpu);
 598
 599         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
 600                                  &sq->wq_ctrl);
 601         if (err)
 602                 goto err_unmap_free_uar;
 603
 604         sq->wq.db       = &sq->wq.db[MLX5_SND_DBR];
 605         if (sq->uar.bf_map) {
 606                 set_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state);
 607                 sq->uar_map = sq->uar.bf_map;
 608         } else {
 609                 sq->uar_map = sq->uar.map;
 610         }
 611         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
 612         sq->max_inline  = param->max_inline;
 613
 614         err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
 615         if (err)
 616                 goto err_sq_wq_destroy;
 617
 618         if (param->icosq) {
 619                 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 620
 621                 sq->ico_wqe_info = kzalloc_node(sizeof(*sq->ico_wqe_info) *
 622                                                 wq_sz,
 623                                                 GFP_KERNEL,
 624                                                 cpu_to_node(c->cpu));
 625                 if (!sq->ico_wqe_info) {
 626                         err = -ENOMEM;
 627                         goto err_free_sq_db;
 628                 }
 629         } else {
 630                 int txq_ix;
 631
 632                 txq_ix = c->ix + tc * priv->params.num_channels;
 633                 sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
 634                 priv->txq_to_sq_map[txq_ix] = sq;
 635         }
 636
 637         sq->pdev      = c->pdev;
 638         sq->tstamp    = &priv->tstamp;
 639         sq->mkey_be   = c->mkey_be;
 640         sq->channel   = c;
 641         sq->tc        = tc;
 642         sq->edge      = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
 643         sq->bf_budget = MLX5E_SQ_BF_BUDGET;
 644
 645         return 0;
 646
 647 err_free_sq_db:
 648         mlx5e_free_sq_db(sq);
 649
 650 err_sq_wq_destroy:
 651         mlx5_wq_destroy(&sq->wq_ctrl);
 652
 653 err_unmap_free_uar:
 654         mlx5_unmap_free_uar(mdev, &sq->uar);
 655
 656         return err;
 657 }
 658
 659 static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
 660 {
 661         struct mlx5e_channel *c = sq->channel;
 662         struct mlx5e_priv *priv = c->priv;
 663
 664         kfree(sq->ico_wqe_info);
 665         mlx5e_free_sq_db(sq);
 666         mlx5_wq_destroy(&sq->wq_ctrl);
 667         mlx5_unmap_free_uar(priv->mdev, &sq->uar);
 668 }
 669
 670 static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
 671 {
 672         struct mlx5e_channel *c = sq->channel;
 673         struct mlx5e_priv *priv = c->priv;
 674         struct mlx5_core_dev *mdev = priv->mdev;
 675
 676         void *in;
 677         void *sqc;
 678         void *wq;
 679         int inlen;
 680         int err;
 681
 682         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
 683                 sizeof(u64) * sq->wq_ctrl.buf.npages;
 684         in = mlx5_vzalloc(inlen);
 685         if (!in)
 686                 return -ENOMEM;
 687
 688         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
 689         wq = MLX5_ADDR_OF(sqc, sqc, wq);
 690
 691         memcpy(sqc, param->sqc, sizeof(param->sqc));
 692
 693         MLX5_SET(sqc,  sqc, tis_num_0, param->icosq ? 0 : priv->tisn[sq->tc]);
 694         MLX5_SET(sqc,  sqc, cqn,                sq->cq.mcq.cqn);
 695         MLX5_SET(sqc,  sqc, state,              MLX5_SQC_STATE_RST);
 696         MLX5_SET(sqc,  sqc, tis_lst_sz,         param->icosq ? 0 : 1);
 697         MLX5_SET(sqc,  sqc, flush_in_error_en,  1);
 698
 699         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
 700         MLX5_SET(wq,   wq, uar_page,      sq->uar.index);
 701         MLX5_SET(wq,   wq, log_wq_pg_sz,  sq->wq_ctrl.buf.page_shift -
 702                                           MLX5_ADAPTER_PAGE_SHIFT);
 703         MLX5_SET64(wq, wq, dbr_addr,      sq->wq_ctrl.db.dma);
 704
 705         mlx5_fill_page_array(&sq->wq_ctrl.buf,
 706                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 707
 708         err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
 709
 710         kvfree(in);
 711
 712         return err;
 713 }
 714
 715 static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state,
 716                            int next_state, bool update_rl, int rl_index)
 717 {
 718         struct mlx5e_channel *c = sq->channel;
 719         struct mlx5e_priv *priv = c->priv;
 720         struct mlx5_core_dev *mdev = priv->mdev;
 721
 722         void *in;
 723         void *sqc;
 724         int inlen;
 725         int err;
 726
 727         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
 728         in = mlx5_vzalloc(inlen);
 729         if (!in)
 730                 return -ENOMEM;
 731
 732         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
 733
 734         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
 735         MLX5_SET(sqc, sqc, state, next_state);
 736         if (update_rl && next_state == MLX5_SQC_STATE_RDY) {
 737                 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
 738                 MLX5_SET(sqc,  sqc, packet_pacing_rate_limit_index, rl_index);
 739         }
 740
 741         err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
 742
 743         kvfree(in);
 744
 745         return err;
 746 }
 747
 748 static void mlx5e_disable_sq(struct mlx5e_sq *sq)
 749 {
 750         struct mlx5e_channel *c = sq->channel;
 751         struct mlx5e_priv *priv = c->priv;
 752         struct mlx5_core_dev *mdev = priv->mdev;
 753
 754         mlx5_core_destroy_sq(mdev, sq->sqn);
 755         if (sq->rate_limit)
 756                 mlx5_rl_remove_rate(mdev, sq->rate_limit);
 757 }
 758
 759 static int mlx5e_open_sq(struct mlx5e_channel *c,
 760                          int tc,
 761                          struct mlx5e_sq_param *param,
 762                          struct mlx5e_sq *sq)
 763 {
 764         int err;
 765
 766         err = mlx5e_create_sq(c, tc, param, sq);
 767         if (err)
 768                 return err;
 769
 770         err = mlx5e_enable_sq(sq, param);
 771         if (err)
 772                 goto err_destroy_sq;
 773
 774         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY,
 775                               false, 0);
 776         if (err)
 777                 goto err_disable_sq;
 778
 779         if (sq->txq) {
 780                 set_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
 781                 netdev_tx_reset_queue(sq->txq);
 782                 netif_tx_start_queue(sq->txq);
 783         }
 784
 785         return 0;
 786
 787 err_disable_sq:
 788         mlx5e_disable_sq(sq);
 789 err_destroy_sq:
 790         mlx5e_destroy_sq(sq);
 791
 792         return err;
 793 }
 794
 795 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
 796 {
 797         __netif_tx_lock_bh(txq);
 798         netif_tx_stop_queue(txq);
 799         __netif_tx_unlock_bh(txq);
 800 }
 801
 802 static void mlx5e_close_sq(struct mlx5e_sq *sq)
 803 {
 804         if (sq->txq) {
 805                 clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
 806                 /* prevent netif_tx_wake_queue */
 807                 napi_synchronize(&sq->channel->napi);
 808                 netif_tx_disable_queue(sq->txq);
 809
 810                 /* ensure hw is notified of all pending wqes */
 811                 if (mlx5e_sq_has_room_for(sq, 1))
 812                         mlx5e_send_nop(sq, true);
 813
 814                 mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR,
 815                                 false, 0);
 816         }
 817
 818         while (sq->cc != sq->pc) /* wait till sq is empty */
 819                 msleep(20);
 820
 821         /* avoid destroying sq before mlx5e_poll_tx_cq() is done with it */
 822         napi_synchronize(&sq->channel->napi);
 823
 824         mlx5e_disable_sq(sq);
 825         mlx5e_destroy_sq(sq);
 826 }
 827
 828 static int mlx5e_create_cq(struct mlx5e_channel *c,
 829                            struct mlx5e_cq_param *param,
 830                            struct mlx5e_cq *cq)
 831 {
 832         struct mlx5e_priv *priv = c->priv;
 833         struct mlx5_core_dev *mdev = priv->mdev;
 834         struct mlx5_core_cq *mcq = &cq->mcq;
 835         int eqn_not_used;
 836         unsigned int irqn;
 837         int err;
 838         u32 i;
 839
 840         param->wq.buf_numa_node = cpu_to_node(c->cpu);
 841         param->wq.db_numa_node  = cpu_to_node(c->cpu);
 842         param->eq_ix   = c->ix;
 843
 844         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
 845                                &cq->wq_ctrl);
 846         if (err)
 847                 return err;
 848
 849         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
 850
 851         cq->napi        = &c->napi;
 852
 853         mcq->cqe_sz     = 64;
 854         mcq->set_ci_db  = cq->wq_ctrl.db.db;
 855         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
 856         *mcq->set_ci_db = 0;
 857         *mcq->arm_db    = 0;
 858         mcq->vector     = param->eq_ix;
 859         mcq->comp       = mlx5e_completion_event;
 860         mcq->event      = mlx5e_cq_error_event;
 861         mcq->irqn       = irqn;
 862         mcq->uar        = &priv->cq_uar;
 863
 864         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
 865                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
 866
 867                 cqe->op_own = 0xf1;
 868         }
 869
 870         cq->channel = c;
 871         cq->priv = priv;
 872
 873         return 0;
 874 }
 875
 876 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
 877 {
 878         mlx5_wq_destroy(&cq->wq_ctrl);
 879 }
 880
 881 static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
 882 {
 883         struct mlx5e_priv *priv = cq->priv;
 884         struct mlx5_core_dev *mdev = priv->mdev;
 885         struct mlx5_core_cq *mcq = &cq->mcq;
 886
 887         void *in;
 888         void *cqc;
 889         int inlen;
 890         unsigned int irqn_not_used;
 891         int eqn;
 892         int err;
 893
 894         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
 895                 sizeof(u64) * cq->wq_ctrl.buf.npages;
 896         in = mlx5_vzalloc(inlen);
 897         if (!in)
 898                 return -ENOMEM;
 899
 900         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
 901
 902         memcpy(cqc, param->cqc, sizeof(param->cqc));
 903
 904         mlx5_fill_page_array(&cq->wq_ctrl.buf,
 905                              (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
 906
 907         mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
 908
 909         MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);
 910         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
 911         MLX5_SET(cqc,   cqc, uar_page,      mcq->uar->index);
 912         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
 913                                             MLX5_ADAPTER_PAGE_SHIFT);
 914         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
 915
 916         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
 917
 918         kvfree(in);
 919
 920         if (err)
 921                 return err;
 922
 923         mlx5e_cq_arm(cq);
 924
 925         return 0;
 926 }
 927
 928 static void mlx5e_disable_cq(struct mlx5e_cq *cq)
 929 {
 930         struct mlx5e_priv *priv = cq->priv;
 931         struct mlx5_core_dev *mdev = priv->mdev;
 932
 933         mlx5_core_destroy_cq(mdev, &cq->mcq);
 934 }
 935
 936 static int mlx5e_open_cq(struct mlx5e_channel *c,
 937                          struct mlx5e_cq_param *param,
 938                          struct mlx5e_cq *cq,
 939                          struct mlx5e_cq_moder moderation)
 940 {
 941         int err;
 942         struct mlx5e_priv *priv = c->priv;
 943         struct mlx5_core_dev *mdev = priv->mdev;
 944
 945         err = mlx5e_create_cq(c, param, cq);
 946         if (err)
 947                 return err;
 948
 949         err = mlx5e_enable_cq(cq, param);
 950         if (err)
 951                 goto err_destroy_cq;
 952
 953         if (MLX5_CAP_GEN(mdev, cq_moderation))
 954                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
 955                                                moderation.usec,
 956                                                moderation.pkts);
 957         return 0;
 958
 959 err_destroy_cq:
 960         mlx5e_destroy_cq(cq);
 961
 962         return err;
 963 }
 964
 965 static void mlx5e_close_cq(struct mlx5e_cq *cq)
 966 {
 967         mlx5e_disable_cq(cq);
 968         mlx5e_destroy_cq(cq);
 969 }
 970
 971 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
 972 {
 973         return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
 974 }
 975
 976 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
 977                              struct mlx5e_channel_param *cparam)
 978 {
 979         struct mlx5e_priv *priv = c->priv;
 980         int err;
 981         int tc;
 982
 983         for (tc = 0; tc < c->num_tc; tc++) {
 984                 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
 985                                     priv->params.tx_cq_moderation);
 986                 if (err)
 987                         goto err_close_tx_cqs;
 988         }
 989
 990         return 0;
 991
 992 err_close_tx_cqs:
 993         for (tc--; tc >= 0; tc--)
 994                 mlx5e_close_cq(&c->sq[tc].cq);
 995
 996         return err;
 997 }
 998
 999 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1000 {
1001         int tc;
1002
1003         for (tc = 0; tc < c->num_tc; tc++)
1004                 mlx5e_close_cq(&c->sq[tc].cq);
1005 }
1006
1007 static int mlx5e_open_sqs(struct mlx5e_channel *c,
1008                           struct mlx5e_channel_param *cparam)
1009 {
1010         int err;
1011         int tc;
1012
1013         for (tc = 0; tc < c->num_tc; tc++) {
1014                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1015                 if (err)
1016                         goto err_close_sqs;
1017         }
1018
1019         return 0;
1020
1021 err_close_sqs:
1022         for (tc--; tc >= 0; tc--)
1023                 mlx5e_close_sq(&c->sq[tc]);
1024
1025         return err;
1026 }
1027
1028 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1029 {
1030         int tc;
1031
1032         for (tc = 0; tc < c->num_tc; tc++)
1033                 mlx5e_close_sq(&c->sq[tc]);
1034 }
1035
1036 static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
1037 {
1038         int i;
1039
1040         for (i = 0; i < MLX5E_MAX_NUM_TC; i++)
1041                 priv->channeltc_to_txq_map[ix][i] =
1042                         ix + i * priv->params.num_channels;
1043 }
1044
1045 static int mlx5e_set_sq_maxrate(struct net_device *dev,
1046                                 struct mlx5e_sq *sq, u32 rate)
1047 {
1048         struct mlx5e_priv *priv = netdev_priv(dev);
1049         struct mlx5_core_dev *mdev = priv->mdev;
1050         u16 rl_index = 0;
1051         int err;
1052
1053         if (rate == sq->rate_limit)
1054                 /* nothing to do */
1055                 return 0;
1056
1057         if (sq->rate_limit)
1058                 /* remove current rl index to free space to next ones */
1059                 mlx5_rl_remove_rate(mdev, sq->rate_limit);
1060
1061         sq->rate_limit = 0;
1062
1063         if (rate) {
1064                 err = mlx5_rl_add_rate(mdev, rate, &rl_index);
1065                 if (err) {
1066                         netdev_err(dev, "Failed configuring rate %u: %d\n",
1067                                    rate, err);
1068                         return err;
1069                 }
1070         }
1071
1072         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY,
1073                               MLX5_SQC_STATE_RDY, true, rl_index);
1074         if (err) {
1075                 netdev_err(dev, "Failed configuring rate %u: %d\n",
1076                            rate, err);
1077                 /* remove the rate from the table */
1078                 if (rate)
1079                         mlx5_rl_remove_rate(mdev, rate);
1080                 return err;
1081         }
1082
1083         sq->rate_limit = rate;
1084         return 0;
1085 }
1086
1087 static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1088 {
1089         struct mlx5e_priv *priv = netdev_priv(dev);
1090         struct mlx5_core_dev *mdev = priv->mdev;
1091         struct mlx5e_sq *sq = priv->txq_to_sq_map[index];
1092         int err = 0;
1093
1094         if (!mlx5_rl_is_supported(mdev)) {
1095                 netdev_err(dev, "Rate limiting is not supported on this device\n");
1096                 return -EINVAL;
1097         }
1098
1099         /* rate is given in Mb/sec, HW config is in Kb/sec */
1100         rate = rate << 10;
1101
1102         /* Check whether rate in valid range, 0 is always valid */
1103         if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1104                 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1105                 return -ERANGE;
1106         }
1107
1108         mutex_lock(&priv->state_lock);
1109         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1110                 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1111         if (!err)
1112                 priv->tx_rates[index] = rate;
1113         mutex_unlock(&priv->state_lock);
1114
1115         return err;
1116 }
1117
1118 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1119                               struct mlx5e_channel_param *cparam,
1120                               struct mlx5e_channel **cp)
1121 {
1122         struct mlx5e_cq_moder icosq_cq_moder = {0, 0};
1123         struct net_device *netdev = priv->netdev;
1124         struct mlx5e_cq_moder rx_cq_profile;
1125         int cpu = mlx5e_get_cpu(priv, ix);
1126         struct mlx5e_channel *c;
1127         struct mlx5e_sq *sq;
1128         int err;
1129         int i;
1130
1131         c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1132         if (!c)
1133                 return -ENOMEM;
1134
1135         c->priv     = priv;
1136         c->ix       = ix;
1137         c->cpu      = cpu;
1138         c->pdev     = &priv->mdev->pdev->dev;
1139         c->netdev   = priv->netdev;
1140         c->mkey_be  = cpu_to_be32(priv->mkey.key);
1141         c->num_tc   = priv->params.num_tc;
1142
1143         if (priv->params.rx_am_enabled)
1144                 rx_cq_profile = mlx5e_am_get_def_profile(priv->params.rx_cq_period_mode);
1145         else
1146                 rx_cq_profile = priv->params.rx_cq_moderation;
1147
1148         mlx5e_build_channeltc_to_txq_map(priv, ix);
1149
1150         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1151
1152         err = mlx5e_open_cq(c, &cparam->icosq_cq, &c->icosq.cq, icosq_cq_moder);
1153         if (err)
1154                 goto err_napi_del;
1155
1156         err = mlx5e_open_tx_cqs(c, cparam);
1157         if (err)
1158                 goto err_close_icosq_cq;
1159
1160         err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
1161                             rx_cq_profile);
1162         if (err)
1163                 goto err_close_tx_cqs;
1164
1165         napi_enable(&c->napi);
1166
1167         err = mlx5e_open_sq(c, 0, &cparam->icosq, &c->icosq);
1168         if (err)
1169                 goto err_disable_napi;
1170
1171         err = mlx5e_open_sqs(c, cparam);
1172         if (err)
1173                 goto err_close_icosq;
1174
1175         for (i = 0; i < priv->params.num_tc; i++) {
1176                 u32 txq_ix = priv->channeltc_to_txq_map[ix][i];
1177
1178                 if (priv->tx_rates[txq_ix]) {
1179                         sq = priv->txq_to_sq_map[txq_ix];
1180                         mlx5e_set_sq_maxrate(priv->netdev, sq,
1181                                              priv->tx_rates[txq_ix]);
1182                 }
1183         }
1184
1185         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1186         if (err)
1187                 goto err_close_sqs;
1188
1189         netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1190         *cp = c;
1191
1192         return 0;
1193
1194 err_close_sqs:
1195         mlx5e_close_sqs(c);
1196
1197 err_close_icosq:
1198         mlx5e_close_sq(&c->icosq);
1199
1200 err_disable_napi:
1201         napi_disable(&c->napi);
1202         mlx5e_close_cq(&c->rq.cq);
1203
1204 err_close_tx_cqs:
1205         mlx5e_close_tx_cqs(c);
1206
1207 err_close_icosq_cq:
1208         mlx5e_close_cq(&c->icosq.cq);
1209
1210 err_napi_del:
1211         netif_napi_del(&c->napi);
1212         napi_hash_del(&c->napi);
1213         kfree(c);
1214
1215         return err;
1216 }
1217
1218 static void mlx5e_close_channel(struct mlx5e_channel *c)
1219 {
1220         mlx5e_close_rq(&c->rq);
1221         mlx5e_close_sqs(c);
1222         mlx5e_close_sq(&c->icosq);
1223         napi_disable(&c->napi);
1224         mlx5e_close_cq(&c->rq.cq);
1225         mlx5e_close_tx_cqs(c);
1226         mlx5e_close_cq(&c->icosq.cq);
1227         netif_napi_del(&c->napi);
1228
1229         napi_hash_del(&c->napi);
1230         synchronize_rcu();
1231
1232         kfree(c);
1233 }
1234
1235 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1236                                  struct mlx5e_rq_param *param)
1237 {
1238         void *rqc = param->rqc;
1239         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1240
1241         switch (priv->params.rq_wq_type) {
1242         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1243                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
1244                          priv->params.mpwqe_log_num_strides - 9);
1245                 MLX5_SET(wq, wq, log_wqe_stride_size,
1246                          priv->params.mpwqe_log_stride_sz - 6);
1247                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1248                 break;
1249         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1250                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1251         }
1252
1253         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1254         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1255         MLX5_SET(wq, wq, log_wq_sz,        priv->params.log_rq_size);
1256         MLX5_SET(wq, wq, pd,               priv->pdn);
1257         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
1258
1259         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1260         param->wq.linear = 1;
1261
1262         param->am_enabled = priv->params.rx_am_enabled;
1263 }
1264
1265 static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1266 {
1267         void *rqc = param->rqc;
1268         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1269
1270         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1271         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1272 }
1273
1274 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1275                                         struct mlx5e_sq_param *param)
1276 {
1277         void *sqc = param->sqc;
1278         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1279
1280         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1281         MLX5_SET(wq, wq, pd,            priv->pdn);
1282
1283         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1284 }
1285
1286 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1287                                  struct mlx5e_sq_param *param)
1288 {
1289         void *sqc = param->sqc;
1290         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1291
1292         mlx5e_build_sq_param_common(priv, param);
1293         MLX5_SET(wq, wq, log_wq_sz,     priv->params.log_sq_size);
1294
1295         param->max_inline = priv->params.tx_max_inline;
1296 }
1297
1298 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1299                                         struct mlx5e_cq_param *param)
1300 {
1301         void *cqc = param->cqc;
1302
1303         MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1304 }
1305
1306 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1307                                     struct mlx5e_cq_param *param)
1308 {
1309         void *cqc = param->cqc;
1310         u8 log_cq_size;
1311
1312         switch (priv->params.rq_wq_type) {
1313         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1314                 log_cq_size = priv->params.log_rq_size +
1315                         priv->params.mpwqe_log_num_strides;
1316                 break;
1317         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1318                 log_cq_size = priv->params.log_rq_size;
1319         }
1320
1321         MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
1322         if (priv->params.rx_cqe_compress) {
1323                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1324                 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1325         }
1326
1327         mlx5e_build_common_cq_param(priv, param);
1328
1329         param->cq_period_mode = priv->params.rx_cq_period_mode;
1330 }
1331
1332 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1333                                     struct mlx5e_cq_param *param)
1334 {
1335         void *cqc = param->cqc;
1336
1337         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1338
1339         mlx5e_build_common_cq_param(priv, param);
1340
1341         param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1342 }
1343
1344 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1345                                      struct mlx5e_cq_param *param,
1346                                      u8 log_wq_size)
1347 {
1348         void *cqc = param->cqc;
1349
1350         MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1351
1352         mlx5e_build_common_cq_param(priv, param);
1353
1354         param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1355 }
1356
1357 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
1358                                     struct mlx5e_sq_param *param,
1359                                     u8 log_wq_size)
1360 {
1361         void *sqc = param->sqc;
1362         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1363
1364         mlx5e_build_sq_param_common(priv, param);
1365
1366         MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
1367         MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
1368
1369         param->icosq = true;
1370 }
1371
1372 static void mlx5e_build_channel_param(struct mlx5e_priv *priv, struct mlx5e_channel_param *cparam)
1373 {
1374         u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
1375
1376         mlx5e_build_rq_param(priv, &cparam->rq);
1377         mlx5e_build_sq_param(priv, &cparam->sq);
1378         mlx5e_build_icosq_param(priv, &cparam->icosq, icosq_log_wq_sz);
1379         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1380         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1381         mlx5e_build_ico_cq_param(priv, &cparam->icosq_cq, icosq_log_wq_sz);
1382 }
1383
1384 static int mlx5e_open_channels(struct mlx5e_priv *priv)
1385 {
1386         struct mlx5e_channel_param *cparam;
1387         int nch = priv->params.num_channels;
1388         int err = -ENOMEM;
1389         int i;
1390         int j;
1391
1392         priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1393                                 GFP_KERNEL);
1394
1395         priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
1396                                       sizeof(struct mlx5e_sq *), GFP_KERNEL);
1397
1398         cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
1399
1400         if (!priv->channel || !priv->txq_to_sq_map || !cparam)
1401                 goto err_free_txq_to_sq_map;
1402
1403         mlx5e_build_channel_param(priv, cparam);
1404
1405         for (i = 0; i < nch; i++) {
1406                 err = mlx5e_open_channel(priv, i, cparam, &priv->channel[i]);
1407                 if (err)
1408                         goto err_close_channels;
1409         }
1410
1411         for (j = 0; j < nch; j++) {
1412                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1413                 if (err)
1414                         goto err_close_channels;
1415         }
1416
1417         kfree(cparam);
1418         return 0;
1419
1420 err_close_channels:
1421         for (i--; i >= 0; i--)
1422                 mlx5e_close_channel(priv->channel[i]);
1423
1424 err_free_txq_to_sq_map:
1425         kfree(priv->txq_to_sq_map);
1426         kfree(priv->channel);
1427         kfree(cparam);
1428
1429         return err;
1430 }
1431
1432 static void mlx5e_close_channels(struct mlx5e_priv *priv)
1433 {
1434         int i;
1435
1436         for (i = 0; i < priv->params.num_channels; i++)
1437                 mlx5e_close_channel(priv->channel[i]);
1438
1439         kfree(priv->txq_to_sq_map);
1440         kfree(priv->channel);
1441 }
1442
1443 static int mlx5e_rx_hash_fn(int hfunc)
1444 {
1445         return (hfunc == ETH_RSS_HASH_TOP) ?
1446                MLX5_RX_HASH_FN_TOEPLITZ :
1447                MLX5_RX_HASH_FN_INVERTED_XOR8;
1448 }
1449
1450 static int mlx5e_bits_invert(unsigned long a, int size)
1451 {
1452         int inv = 0;
1453         int i;
1454
1455         for (i = 0; i < size; i++)
1456                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1457
1458         return inv;
1459 }
1460
1461 static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1462 {
1463         int i;
1464
1465         for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1466                 int ix = i;
1467                 u32 rqn;
1468
1469                 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1470                         ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1471
1472                 ix = priv->params.indirection_rqt[ix];
1473                 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1474                                 priv->channel[ix]->rq.rqn :
1475                                 priv->drop_rq.rqn;
1476                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
1477         }
1478 }
1479
1480 static void mlx5e_fill_direct_rqt_rqn(struct mlx5e_priv *priv, void *rqtc,
1481                                       int ix)
1482 {
1483         u32 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1484                         priv->channel[ix]->rq.rqn :
1485                         priv->drop_rq.rqn;
1486
1487         MLX5_SET(rqtc, rqtc, rq_num[0], rqn);
1488 }
1489
1490 static int mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, int ix, u32 *rqtn)
1491 {
1492         struct mlx5_core_dev *mdev = priv->mdev;
1493         void *rqtc;
1494         int inlen;
1495         int err;
1496         u32 *in;
1497
1498         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1499         in = mlx5_vzalloc(inlen);
1500         if (!in)
1501                 return -ENOMEM;
1502
1503         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1504
1505         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1506         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1507
1508         if (sz > 1) /* RSS */
1509                 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1510         else
1511                 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
1512
1513         err = mlx5_core_create_rqt(mdev, in, inlen, rqtn);
1514
1515         kvfree(in);
1516         return err;
1517 }
1518
1519 static void mlx5e_destroy_rqt(struct mlx5e_priv *priv, u32 rqtn)
1520 {
1521         mlx5_core_destroy_rqt(priv->mdev, rqtn);
1522 }
1523
1524 static int mlx5e_create_rqts(struct mlx5e_priv *priv)
1525 {
1526         int nch = mlx5e_get_max_num_channels(priv->mdev);
1527         u32 *rqtn;
1528         int err;
1529         int ix;
1530
1531         /* Indirect RQT */
1532         rqtn = &priv->indir_rqtn;
1533         err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, 0, rqtn);
1534         if (err)
1535                 return err;
1536
1537         /* Direct RQTs */
1538         for (ix = 0; ix < nch; ix++) {
1539                 rqtn = &priv->direct_tir[ix].rqtn;
1540                 err = mlx5e_create_rqt(priv, 1 /*size */, ix, rqtn);
1541                 if (err)
1542                         goto err_destroy_rqts;
1543         }
1544
1545         return 0;
1546
1547 err_destroy_rqts:
1548         for (ix--; ix >= 0; ix--)
1549                 mlx5e_destroy_rqt(priv, priv->direct_tir[ix].rqtn);
1550
1551         mlx5e_destroy_rqt(priv, priv->indir_rqtn);
1552
1553         return err;
1554 }
1555
1556 static void mlx5e_destroy_rqts(struct mlx5e_priv *priv)
1557 {
1558         int nch = mlx5e_get_max_num_channels(priv->mdev);
1559         int i;
1560
1561         for (i = 0; i < nch; i++)
1562                 mlx5e_destroy_rqt(priv, priv->direct_tir[i].rqtn);
1563
1564         mlx5e_destroy_rqt(priv, priv->indir_rqtn);
1565 }
1566
1567 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix)
1568 {
1569         struct mlx5_core_dev *mdev = priv->mdev;
1570         void *rqtc;
1571         int inlen;
1572         u32 *in;
1573         int err;
1574
1575         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1576         in = mlx5_vzalloc(inlen);
1577         if (!in)
1578                 return -ENOMEM;
1579
1580         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
1581
1582         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1583         if (sz > 1) /* RSS */
1584                 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1585         else
1586                 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
1587
1588         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
1589
1590         err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
1591
1592         kvfree(in);
1593
1594         return err;
1595 }
1596
1597 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
1598 {
1599         u32 rqtn;
1600         int ix;
1601
1602         rqtn = priv->indir_rqtn;
1603         mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, 0);
1604         for (ix = 0; ix < priv->params.num_channels; ix++) {
1605                 rqtn = priv->direct_tir[ix].rqtn;
1606                 mlx5e_redirect_rqt(priv, rqtn, 1, ix);
1607         }
1608 }
1609
1610 static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
1611 {
1612         if (!priv->params.lro_en)
1613                 return;
1614
1615 #define ROUGH_MAX_L2_L3_HDR_SZ 256
1616
1617         MLX5_SET(tirc, tirc, lro_enable_mask,
1618                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1619                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1620         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1621                  (priv->params.lro_wqe_sz -
1622                   ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1623         MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1624                  MLX5_CAP_ETH(priv->mdev,
1625                               lro_timer_supported_periods[2]));
1626 }
1627
1628 void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv)
1629 {
1630         MLX5_SET(tirc, tirc, rx_hash_fn,
1631                  mlx5e_rx_hash_fn(priv->params.rss_hfunc));
1632         if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
1633                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
1634                                              rx_hash_toeplitz_key);
1635                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
1636                                                rx_hash_toeplitz_key);
1637
1638                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1639                 memcpy(rss_key, priv->params.toeplitz_hash_key, len);
1640         }
1641 }
1642
1643 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
1644 {
1645         struct mlx5_core_dev *mdev = priv->mdev;
1646
1647         void *in;
1648         void *tirc;
1649         int inlen;
1650         int err;
1651         int tt;
1652         int ix;
1653
1654         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1655         in = mlx5_vzalloc(inlen);
1656         if (!in)
1657                 return -ENOMEM;
1658
1659         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
1660         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
1661
1662         mlx5e_build_tir_ctx_lro(tirc, priv);
1663
1664         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
1665                 err = mlx5_core_modify_tir(mdev, priv->indir_tirn[tt], in,
1666                                            inlen);
1667                 if (err)
1668                         goto free_in;
1669         }
1670
1671         for (ix = 0; ix < mlx5e_get_max_num_channels(mdev); ix++) {
1672                 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
1673                                            in, inlen);
1674                 if (err)
1675                         goto free_in;
1676         }
1677
1678 free_in:
1679         kvfree(in);
1680
1681         return err;
1682 }
1683
1684 static int mlx5e_refresh_tirs_self_loopback_enable(struct mlx5e_priv *priv)
1685 {
1686         void *in;
1687         int inlen;
1688         int err;
1689         int i;
1690
1691         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1692         in = mlx5_vzalloc(inlen);
1693         if (!in)
1694                 return -ENOMEM;
1695
1696         MLX5_SET(modify_tir_in, in, bitmask.self_lb_en, 1);
1697
1698         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
1699                 err = mlx5_core_modify_tir(priv->mdev, priv->indir_tirn[i], in,
1700                                            inlen);
1701                 if (err)
1702                         return err;
1703         }
1704
1705         for (i = 0; i < priv->params.num_channels; i++) {
1706                 err = mlx5_core_modify_tir(priv->mdev,
1707                                            priv->direct_tir[i].tirn, in,
1708                                            inlen);
1709                 if (err)
1710                         return err;
1711         }
1712
1713         kvfree(in);
1714
1715         return 0;
1716 }
1717
1718 static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
1719 {
1720         struct mlx5_core_dev *mdev = priv->mdev;
1721         u16 hw_mtu = MLX5E_SW2HW_MTU(mtu);
1722         int err;
1723
1724         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
1725         if (err)
1726                 return err;
1727
1728         /* Update vport context MTU */
1729         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
1730         return 0;
1731 }
1732
1733 static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
1734 {
1735         struct mlx5_core_dev *mdev = priv->mdev;
1736         u16 hw_mtu = 0;
1737         int err;
1738
1739         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
1740         if (err || !hw_mtu) /* fallback to port oper mtu */
1741                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
1742
1743         *mtu = MLX5E_HW2SW_MTU(hw_mtu);
1744 }
1745
1746 static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
1747 {
1748         struct mlx5e_priv *priv = netdev_priv(netdev);
1749         u16 mtu;
1750         int err;
1751
1752         err = mlx5e_set_mtu(priv, netdev->mtu);
1753         if (err)
1754                 return err;
1755
1756         mlx5e_query_mtu(priv, &mtu);
1757         if (mtu != netdev->mtu)
1758                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
1759                             __func__, mtu, netdev->mtu);
1760
1761         netdev->mtu = mtu;
1762         return 0;
1763 }
1764
1765 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
1766 {
1767         struct mlx5e_priv *priv = netdev_priv(netdev);
1768         int nch = priv->params.num_channels;
1769         int ntc = priv->params.num_tc;
1770         int tc;
1771
1772         netdev_reset_tc(netdev);
1773
1774         if (ntc == 1)
1775                 return;
1776
1777         netdev_set_num_tc(netdev, ntc);
1778
1779         for (tc = 0; tc < ntc; tc++)
1780                 netdev_set_tc_queue(netdev, tc, nch, tc * nch);
1781 }
1782
1783 int mlx5e_open_locked(struct net_device *netdev)
1784 {
1785         struct mlx5e_priv *priv = netdev_priv(netdev);
1786         int num_txqs;
1787         int err;
1788
1789         set_bit(MLX5E_STATE_OPENED, &priv->state);
1790
1791         mlx5e_netdev_set_tcs(netdev);
1792
1793         num_txqs = priv->params.num_channels * priv->params.num_tc;
1794         netif_set_real_num_tx_queues(netdev, num_txqs);
1795         netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
1796
1797         err = mlx5e_set_dev_port_mtu(netdev);
1798         if (err)
1799                 goto err_clear_state_opened_flag;
1800
1801         err = mlx5e_open_channels(priv);
1802         if (err) {
1803                 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
1804                            __func__, err);
1805                 goto err_clear_state_opened_flag;
1806         }
1807
1808         err = mlx5e_refresh_tirs_self_loopback_enable(priv);
1809         if (err) {
1810                 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
1811                            __func__, err);
1812                 goto err_close_channels;
1813         }
1814
1815         mlx5e_redirect_rqts(priv);
1816         mlx5e_update_carrier(priv);
1817         mlx5e_timestamp_init(priv);
1818 #ifdef CONFIG_RFS_ACCEL
1819         priv->netdev->rx_cpu_rmap = priv->mdev->rmap;
1820 #endif
1821
1822         queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
1823
1824         return 0;
1825
1826 err_close_channels:
1827         mlx5e_close_channels(priv);
1828 err_clear_state_opened_flag:
1829         clear_bit(MLX5E_STATE_OPENED, &priv->state);
1830         return err;
1831 }
1832
1833 static int mlx5e_open(struct net_device *netdev)
1834 {
1835         struct mlx5e_priv *priv = netdev_priv(netdev);
1836         int err;
1837
1838         mutex_lock(&priv->state_lock);
1839         err = mlx5e_open_locked(netdev);
1840         mutex_unlock(&priv->state_lock);
1841
1842         return err;
1843 }
1844
1845 int mlx5e_close_locked(struct net_device *netdev)
1846 {
1847         struct mlx5e_priv *priv = netdev_priv(netdev);
1848
1849         /* May already be CLOSED in case a previous configuration operation
1850          * (e.g RX/TX queue size change) that involves close&open failed.
1851          */
1852         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
1853                 return 0;
1854
1855         clear_bit(MLX5E_STATE_OPENED, &priv->state);
1856
1857         mlx5e_timestamp_cleanup(priv);
1858         netif_carrier_off(priv->netdev);
1859         mlx5e_redirect_rqts(priv);
1860         mlx5e_close_channels(priv);
1861
1862         return 0;
1863 }
1864
1865 static int mlx5e_close(struct net_device *netdev)
1866 {
1867         struct mlx5e_priv *priv = netdev_priv(netdev);
1868         int err;
1869
1870         mutex_lock(&priv->state_lock);
1871         err = mlx5e_close_locked(netdev);
1872         mutex_unlock(&priv->state_lock);
1873
1874         return err;
1875 }
1876
1877 static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
1878                                 struct mlx5e_rq *rq,
1879                                 struct mlx5e_rq_param *param)
1880 {
1881         struct mlx5_core_dev *mdev = priv->mdev;
1882         void *rqc = param->rqc;
1883         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1884         int err;
1885
1886         param->wq.db_numa_node = param->wq.buf_numa_node;
1887
1888         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
1889                                 &rq->wq_ctrl);
1890         if (err)
1891                 return err;
1892
1893         rq->priv = priv;
1894
1895         return 0;
1896 }
1897
1898 static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
1899                                 struct mlx5e_cq *cq,
1900                                 struct mlx5e_cq_param *param)
1901 {
1902         struct mlx5_core_dev *mdev = priv->mdev;
1903         struct mlx5_core_cq *mcq = &cq->mcq;
1904         int eqn_not_used;
1905         unsigned int irqn;
1906         int err;
1907
1908         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1909                                &cq->wq_ctrl);
1910         if (err)
1911                 return err;
1912
1913         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1914
1915         mcq->cqe_sz     = 64;
1916         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1917         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1918         *mcq->set_ci_db = 0;
1919         *mcq->arm_db    = 0;
1920         mcq->vector     = param->eq_ix;
1921         mcq->comp       = mlx5e_completion_event;
1922         mcq->event      = mlx5e_cq_error_event;
1923         mcq->irqn       = irqn;
1924         mcq->uar        = &priv->cq_uar;
1925
1926         cq->priv = priv;
1927
1928         return 0;
1929 }
1930
1931 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
1932 {
1933         struct mlx5e_cq_param cq_param;
1934         struct mlx5e_rq_param rq_param;
1935         struct mlx5e_rq *rq = &priv->drop_rq;
1936         struct mlx5e_cq *cq = &priv->drop_rq.cq;
1937         int err;
1938
1939         memset(&cq_param, 0, sizeof(cq_param));
1940         memset(&rq_param, 0, sizeof(rq_param));
1941         mlx5e_build_drop_rq_param(&rq_param);
1942
1943         err = mlx5e_create_drop_cq(priv, cq, &cq_param);
1944         if (err)
1945                 return err;
1946
1947         err = mlx5e_enable_cq(cq, &cq_param);
1948         if (err)
1949                 goto err_destroy_cq;
1950
1951         err = mlx5e_create_drop_rq(priv, rq, &rq_param);
1952         if (err)
1953                 goto err_disable_cq;
1954
1955         err = mlx5e_enable_rq(rq, &rq_param);
1956         if (err)
1957                 goto err_destroy_rq;
1958
1959         return 0;
1960
1961 err_destroy_rq:
1962         mlx5e_destroy_rq(&priv->drop_rq);
1963
1964 err_disable_cq:
1965         mlx5e_disable_cq(&priv->drop_rq.cq);
1966
1967 err_destroy_cq:
1968         mlx5e_destroy_cq(&priv->drop_rq.cq);
1969
1970         return err;
1971 }
1972
1973 static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
1974 {
1975         mlx5e_disable_rq(&priv->drop_rq);
1976         mlx5e_destroy_rq(&priv->drop_rq);
1977         mlx5e_disable_cq(&priv->drop_rq.cq);
1978         mlx5e_destroy_cq(&priv->drop_rq.cq);
1979 }
1980
1981 static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
1982 {
1983         struct mlx5_core_dev *mdev = priv->mdev;
1984         u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1985         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1986
1987         memset(in, 0, sizeof(in));
1988
1989         MLX5_SET(tisc, tisc, prio, tc << 1);
1990         MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
1991
1992         return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
1993 }
1994
1995 static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
1996 {
1997         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
1998 }
1999
2000 static int mlx5e_create_tises(struct mlx5e_priv *priv)
2001 {
2002         int err;
2003         int tc;
2004
2005         for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++) {
2006                 err = mlx5e_create_tis(priv, tc);
2007                 if (err)
2008                         goto err_close_tises;
2009         }
2010
2011         return 0;
2012
2013 err_close_tises:
2014         for (tc--; tc >= 0; tc--)
2015                 mlx5e_destroy_tis(priv, tc);
2016
2017         return err;
2018 }
2019
2020 static void mlx5e_destroy_tises(struct mlx5e_priv *priv)
2021 {
2022         int tc;
2023
2024         for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++)
2025                 mlx5e_destroy_tis(priv, tc);
2026 }
2027
2028 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2029                                       enum mlx5e_traffic_types tt)
2030 {
2031         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2032
2033         MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
2034
2035 #define MLX5_HASH_IP            (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2036                                  MLX5_HASH_FIELD_SEL_DST_IP)
2037
2038 #define MLX5_HASH_IP_L4PORTS    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2039                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2040                                  MLX5_HASH_FIELD_SEL_L4_SPORT |\
2041                                  MLX5_HASH_FIELD_SEL_L4_DPORT)
2042
2043 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2044                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2045                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2046
2047         mlx5e_build_tir_ctx_lro(tirc, priv);
2048
2049         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2050         MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqtn);
2051         mlx5e_build_tir_ctx_hash(tirc, priv);
2052
2053         switch (tt) {
2054         case MLX5E_TT_IPV4_TCP:
2055                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2056                          MLX5_L3_PROT_TYPE_IPV4);
2057                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2058                          MLX5_L4_PROT_TYPE_TCP);
2059                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2060                          MLX5_HASH_IP_L4PORTS);
2061                 break;
2062
2063         case MLX5E_TT_IPV6_TCP:
2064                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2065                          MLX5_L3_PROT_TYPE_IPV6);
2066                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2067                          MLX5_L4_PROT_TYPE_TCP);
2068                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2069                          MLX5_HASH_IP_L4PORTS);
2070                 break;
2071
2072         case MLX5E_TT_IPV4_UDP:
2073                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2074                          MLX5_L3_PROT_TYPE_IPV4);
2075                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2076                          MLX5_L4_PROT_TYPE_UDP);
2077                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2078                          MLX5_HASH_IP_L4PORTS);
2079                 break;
2080
2081         case MLX5E_TT_IPV6_UDP:
2082                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2083                          MLX5_L3_PROT_TYPE_IPV6);
2084                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2085                          MLX5_L4_PROT_TYPE_UDP);
2086                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2087                          MLX5_HASH_IP_L4PORTS);
2088                 break;
2089
2090         case MLX5E_TT_IPV4_IPSEC_AH:
2091                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2092                          MLX5_L3_PROT_TYPE_IPV4);
2093                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2094                          MLX5_HASH_IP_IPSEC_SPI);
2095                 break;
2096
2097         case MLX5E_TT_IPV6_IPSEC_AH:
2098                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2099                          MLX5_L3_PROT_TYPE_IPV6);
2100                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2101                          MLX5_HASH_IP_IPSEC_SPI);
2102                 break;
2103
2104         case MLX5E_TT_IPV4_IPSEC_ESP:
2105                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2106                          MLX5_L3_PROT_TYPE_IPV4);
2107                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2108                          MLX5_HASH_IP_IPSEC_SPI);
2109                 break;
2110
2111         case MLX5E_TT_IPV6_IPSEC_ESP:
2112                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2113                          MLX5_L3_PROT_TYPE_IPV6);
2114                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2115                          MLX5_HASH_IP_IPSEC_SPI);
2116                 break;
2117
2118         case MLX5E_TT_IPV4:
2119                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2120                          MLX5_L3_PROT_TYPE_IPV4);
2121                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2122                          MLX5_HASH_IP);
2123                 break;
2124
2125         case MLX5E_TT_IPV6:
2126                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2127                          MLX5_L3_PROT_TYPE_IPV6);
2128                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2129                          MLX5_HASH_IP);
2130                 break;
2131         default:
2132                 WARN_ONCE(true,
2133                           "mlx5e_build_indir_tir_ctx: bad traffic type!\n");
2134         }
2135 }
2136
2137 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2138                                        u32 rqtn)
2139 {
2140         MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
2141
2142         mlx5e_build_tir_ctx_lro(tirc, priv);
2143
2144         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2145         MLX5_SET(tirc, tirc, indirect_table, rqtn);
2146         MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2147 }
2148
2149 static int mlx5e_create_tirs(struct mlx5e_priv *priv)
2150 {
2151         int nch = mlx5e_get_max_num_channels(priv->mdev);
2152         void *tirc;
2153         int inlen;
2154         u32 *tirn;
2155         int err;
2156         u32 *in;
2157         int ix;
2158         int tt;
2159
2160         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2161         in = mlx5_vzalloc(inlen);
2162         if (!in)
2163                 return -ENOMEM;
2164
2165         /* indirect tirs */
2166         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2167                 memset(in, 0, inlen);
2168                 tirn = &priv->indir_tirn[tt];
2169                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2170                 mlx5e_build_indir_tir_ctx(priv, tirc, tt);
2171                 err = mlx5_core_create_tir(priv->mdev, in, inlen, tirn);
2172                 if (err)
2173                         goto err_destroy_tirs;
2174         }
2175
2176         /* direct tirs */
2177         for (ix = 0; ix < nch; ix++) {
2178                 memset(in, 0, inlen);
2179                 tirn = &priv->direct_tir[ix].tirn;
2180                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2181                 mlx5e_build_direct_tir_ctx(priv, tirc,
2182                                            priv->direct_tir[ix].rqtn);
2183                 err = mlx5_core_create_tir(priv->mdev, in, inlen, tirn);
2184                 if (err)
2185                         goto err_destroy_ch_tirs;
2186         }
2187
2188         kvfree(in);
2189
2190         return 0;
2191
2192 err_destroy_ch_tirs:
2193         for (ix--; ix >= 0; ix--)
2194                 mlx5_core_destroy_tir(priv->mdev, priv->direct_tir[ix].tirn);
2195
2196 err_destroy_tirs:
2197         for (tt--; tt >= 0; tt--)
2198                 mlx5_core_destroy_tir(priv->mdev, priv->indir_tirn[tt]);
2199
2200         kvfree(in);
2201
2202         return err;
2203 }
2204
2205 static void mlx5e_destroy_tirs(struct mlx5e_priv *priv)
2206 {
2207         int nch = mlx5e_get_max_num_channels(priv->mdev);
2208         int i;
2209
2210         for (i = 0; i < nch; i++)
2211                 mlx5_core_destroy_tir(priv->mdev, priv->direct_tir[i].tirn);
2212
2213         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
2214                 mlx5_core_destroy_tir(priv->mdev, priv->indir_tirn[i]);
2215 }
2216
2217 int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd)
2218 {
2219         int err = 0;
2220         int i;
2221
2222         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2223                 return 0;
2224
2225         for (i = 0; i < priv->params.num_channels; i++) {
2226                 err = mlx5e_modify_rq_vsd(&priv->channel[i]->rq, vsd);
2227                 if (err)
2228                         return err;
2229         }
2230
2231         return 0;
2232 }
2233
2234 static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
2235 {
2236         struct mlx5e_priv *priv = netdev_priv(netdev);
2237         bool was_opened;
2238         int err = 0;
2239
2240         if (tc && tc != MLX5E_MAX_NUM_TC)
2241                 return -EINVAL;
2242
2243         mutex_lock(&priv->state_lock);
2244
2245         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2246         if (was_opened)
2247                 mlx5e_close_locked(priv->netdev);
2248
2249         priv->params.num_tc = tc ? tc : 1;
2250
2251         if (was_opened)
2252                 err = mlx5e_open_locked(priv->netdev);
2253
2254         mutex_unlock(&priv->state_lock);
2255
2256         return err;
2257 }
2258
2259 static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
2260                               __be16 proto, struct tc_to_netdev *tc)
2261 {
2262         struct mlx5e_priv *priv = netdev_priv(dev);
2263
2264         if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
2265                 goto mqprio;
2266
2267         switch (tc->type) {
2268         case TC_SETUP_CLSFLOWER:
2269                 switch (tc->cls_flower->command) {
2270                 case TC_CLSFLOWER_REPLACE:
2271                         return mlx5e_configure_flower(priv, proto, tc->cls_flower);
2272                 case TC_CLSFLOWER_DESTROY:
2273                         return mlx5e_delete_flower(priv, tc->cls_flower);
2274                 case TC_CLSFLOWER_STATS:
2275                         return mlx5e_stats_flower(priv, tc->cls_flower);
2276                 }
2277         default:
2278                 return -EOPNOTSUPP;
2279         }
2280
2281 mqprio:
2282         if (tc->type != TC_SETUP_MQPRIO)
2283                 return -EINVAL;
2284
2285         return mlx5e_setup_tc(dev, tc->tc);
2286 }
2287
2288 static struct rtnl_link_stats64 *
2289 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
2290 {
2291         struct mlx5e_priv *priv = netdev_priv(dev);
2292         struct mlx5e_sw_stats *sstats = &priv->stats.sw;
2293         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
2294         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
2295
2296         stats->rx_packets = sstats->rx_packets;
2297         stats->rx_bytes   = sstats->rx_bytes;
2298         stats->tx_packets = sstats->tx_packets;
2299         stats->tx_bytes   = sstats->tx_bytes;
2300
2301         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
2302         stats->tx_dropped = sstats->tx_queue_dropped;
2303
2304         stats->rx_length_errors =
2305                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
2306                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
2307                 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
2308         stats->rx_crc_errors =
2309                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
2310         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
2311         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
2312         stats->tx_carrier_errors =
2313                 PPORT_802_3_GET(pstats, a_symbol_error_during_carrier);
2314         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
2315                            stats->rx_frame_errors;
2316         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
2317
2318         /* vport multicast also counts packets that are dropped due to steering
2319          * or rx out of buffer
2320          */
2321         stats->multicast =
2322                 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
2323
2324         return stats;
2325 }
2326
2327 static void mlx5e_set_rx_mode(struct net_device *dev)
2328 {
2329         struct mlx5e_priv *priv = netdev_priv(dev);
2330
2331         queue_work(priv->wq, &priv->set_rx_mode_work);
2332 }
2333
2334 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
2335 {
2336         struct mlx5e_priv *priv = netdev_priv(netdev);
2337         struct sockaddr *saddr = addr;
2338
2339         if (!is_valid_ether_addr(saddr->sa_data))
2340                 return -EADDRNOTAVAIL;
2341
2342         netif_addr_lock_bh(netdev);
2343         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
2344         netif_addr_unlock_bh(netdev);
2345
2346         queue_work(priv->wq, &priv->set_rx_mode_work);
2347
2348         return 0;
2349 }
2350
2351 #define MLX5E_SET_FEATURE(netdev, feature, enable)      \
2352         do {                                            \
2353                 if (enable)                             \
2354                         netdev->features |= feature;    \
2355                 else                                    \
2356                         netdev->features &= ~feature;   \
2357         } while (0)
2358
2359 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
2360
2361 static int set_feature_lro(struct net_device *netdev, bool enable)
2362 {
2363         struct mlx5e_priv *priv = netdev_priv(netdev);
2364         bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2365         int err;
2366
2367         mutex_lock(&priv->state_lock);
2368
2369         if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2370                 mlx5e_close_locked(priv->netdev);
2371
2372         priv->params.lro_en = enable;
2373         err = mlx5e_modify_tirs_lro(priv);
2374         if (err) {
2375                 netdev_err(netdev, "lro modify failed, %d\n", err);
2376                 priv->params.lro_en = !enable;
2377         }
2378
2379         if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2380                 mlx5e_open_locked(priv->netdev);
2381
2382         mutex_unlock(&priv->state_lock);
2383
2384         return err;
2385 }
2386
2387 static int set_feature_vlan_filter(struct net_device *netdev, bool enable)
2388 {
2389         struct mlx5e_priv *priv = netdev_priv(netdev);
2390
2391         if (enable)
2392                 mlx5e_enable_vlan_filter(priv);
2393         else
2394                 mlx5e_disable_vlan_filter(priv);
2395
2396         return 0;
2397 }
2398
2399 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
2400 {
2401         struct mlx5e_priv *priv = netdev_priv(netdev);
2402
2403         if (!enable && mlx5e_tc_num_filters(priv)) {
2404                 netdev_err(netdev,
2405                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
2406                 return -EINVAL;
2407         }
2408
2409         return 0;
2410 }
2411
2412 static int set_feature_rx_all(struct net_device *netdev, bool enable)
2413 {
2414         struct mlx5e_priv *priv = netdev_priv(netdev);
2415         struct mlx5_core_dev *mdev = priv->mdev;
2416
2417         return mlx5_set_port_fcs(mdev, !enable);
2418 }
2419
2420 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
2421 {
2422         struct mlx5e_priv *priv = netdev_priv(netdev);
2423         int err;
2424
2425         mutex_lock(&priv->state_lock);
2426
2427         priv->params.vlan_strip_disable = !enable;
2428         err = mlx5e_modify_rqs_vsd(priv, !enable);
2429         if (err)
2430                 priv->params.vlan_strip_disable = enable;
2431
2432         mutex_unlock(&priv->state_lock);
2433
2434         return err;
2435 }
2436
2437 #ifdef CONFIG_RFS_ACCEL
2438 static int set_feature_arfs(struct net_device *netdev, bool enable)
2439 {
2440         struct mlx5e_priv *priv = netdev_priv(netdev);
2441         int err;
2442
2443         if (enable)
2444                 err = mlx5e_arfs_enable(priv);
2445         else
2446                 err = mlx5e_arfs_disable(priv);
2447
2448         return err;
2449 }
2450 #endif
2451
2452 static int mlx5e_handle_feature(struct net_device *netdev,
2453                                 netdev_features_t wanted_features,
2454                                 netdev_features_t feature,
2455                                 mlx5e_feature_handler feature_handler)
2456 {
2457         netdev_features_t changes = wanted_features ^ netdev->features;
2458         bool enable = !!(wanted_features & feature);
2459         int err;
2460
2461         if (!(changes & feature))
2462                 return 0;
2463
2464         err = feature_handler(netdev, enable);
2465         if (err) {
2466                 netdev_err(netdev, "%s feature 0x%llx failed err %d\n",
2467                            enable ? "Enable" : "Disable", feature, err);
2468                 return err;
2469         }
2470
2471         MLX5E_SET_FEATURE(netdev, feature, enable);
2472         return 0;
2473 }
2474
2475 static int mlx5e_set_features(struct net_device *netdev,
2476                               netdev_features_t features)
2477 {
2478         int err;
2479
2480         err  = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
2481                                     set_feature_lro);
2482         err |= mlx5e_handle_feature(netdev, features,
2483                                     NETIF_F_HW_VLAN_CTAG_FILTER,
2484                                     set_feature_vlan_filter);
2485         err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
2486                                     set_feature_tc_num_filters);
2487         err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
2488                                     set_feature_rx_all);
2489         err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
2490                                     set_feature_rx_vlan);
2491 #ifdef CONFIG_RFS_ACCEL
2492         err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE,
2493                                     set_feature_arfs);
2494 #endif
2495
2496         return err ? -EINVAL : 0;
2497 }
2498
2499 #define MXL5_HW_MIN_MTU 64
2500 #define MXL5E_MIN_MTU (MXL5_HW_MIN_MTU + ETH_FCS_LEN)
2501
2502 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
2503 {
2504         struct mlx5e_priv *priv = netdev_priv(netdev);
2505         struct mlx5_core_dev *mdev = priv->mdev;
2506         bool was_opened;
2507         u16 max_mtu;
2508         u16 min_mtu;
2509         int err = 0;
2510
2511         mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2512
2513         max_mtu = MLX5E_HW2SW_MTU(max_mtu);
2514         min_mtu = MLX5E_HW2SW_MTU(MXL5E_MIN_MTU);
2515
2516         if (new_mtu > max_mtu || new_mtu < min_mtu) {
2517                 netdev_err(netdev,
2518                            "%s: Bad MTU (%d), valid range is: [%d..%d]\n",
2519                            __func__, new_mtu, min_mtu, max_mtu);
2520                 return -EINVAL;
2521         }
2522
2523         mutex_lock(&priv->state_lock);
2524
2525         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2526         if (was_opened)
2527                 mlx5e_close_locked(netdev);
2528
2529         netdev->mtu = new_mtu;
2530
2531         if (was_opened)
2532                 err = mlx5e_open_locked(netdev);
2533
2534         mutex_unlock(&priv->state_lock);
2535
2536         return err;
2537 }
2538
2539 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2540 {
2541         switch (cmd) {
2542         case SIOCSHWTSTAMP:
2543                 return mlx5e_hwstamp_set(dev, ifr);
2544         case SIOCGHWTSTAMP:
2545                 return mlx5e_hwstamp_get(dev, ifr);
2546         default:
2547                 return -EOPNOTSUPP;
2548         }
2549 }
2550
2551 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2552 {
2553         struct mlx5e_priv *priv = netdev_priv(dev);
2554         struct mlx5_core_dev *mdev = priv->mdev;
2555
2556         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
2557 }
2558
2559 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos)
2560 {
2561         struct mlx5e_priv *priv = netdev_priv(dev);
2562         struct mlx5_core_dev *mdev = priv->mdev;
2563
2564         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
2565                                            vlan, qos);
2566 }
2567
2568 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
2569 {
2570         struct mlx5e_priv *priv = netdev_priv(dev);
2571         struct mlx5_core_dev *mdev = priv->mdev;
2572
2573         return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
2574 }
2575
2576 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
2577 {
2578         struct mlx5e_priv *priv = netdev_priv(dev);
2579         struct mlx5_core_dev *mdev = priv->mdev;
2580
2581         return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
2582 }
2583 static int mlx5_vport_link2ifla(u8 esw_link)
2584 {
2585         switch (esw_link) {
2586         case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
2587                 return IFLA_VF_LINK_STATE_DISABLE;
2588         case MLX5_ESW_VPORT_ADMIN_STATE_UP:
2589                 return IFLA_VF_LINK_STATE_ENABLE;
2590         }
2591         return IFLA_VF_LINK_STATE_AUTO;
2592 }
2593
2594 static int mlx5_ifla_link2vport(u8 ifla_link)
2595 {
2596         switch (ifla_link) {
2597         case IFLA_VF_LINK_STATE_DISABLE:
2598                 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
2599         case IFLA_VF_LINK_STATE_ENABLE:
2600                 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
2601         }
2602         return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
2603 }
2604
2605 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
2606                                    int link_state)
2607 {
2608         struct mlx5e_priv *priv = netdev_priv(dev);
2609         struct mlx5_core_dev *mdev = priv->mdev;
2610
2611         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
2612                                             mlx5_ifla_link2vport(link_state));
2613 }
2614
2615 static int mlx5e_get_vf_config(struct net_device *dev,
2616                                int vf, struct ifla_vf_info *ivi)
2617 {
2618         struct mlx5e_priv *priv = netdev_priv(dev);
2619         struct mlx5_core_dev *mdev = priv->mdev;
2620         int err;
2621
2622         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
2623         if (err)
2624                 return err;
2625         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
2626         return 0;
2627 }
2628
2629 static int mlx5e_get_vf_stats(struct net_device *dev,
2630                               int vf, struct ifla_vf_stats *vf_stats)
2631 {
2632         struct mlx5e_priv *priv = netdev_priv(dev);
2633         struct mlx5_core_dev *mdev = priv->mdev;
2634
2635         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
2636                                             vf_stats);
2637 }
2638
2639 static void mlx5e_add_vxlan_port(struct net_device *netdev,
2640                                  struct udp_tunnel_info *ti)
2641 {
2642         struct mlx5e_priv *priv = netdev_priv(netdev);
2643
2644         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
2645                 return;
2646
2647         if (!mlx5e_vxlan_allowed(priv->mdev))
2648                 return;
2649
2650         mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);
2651 }
2652
2653 static void mlx5e_del_vxlan_port(struct net_device *netdev,
2654                                  struct udp_tunnel_info *ti)
2655 {
2656         struct mlx5e_priv *priv = netdev_priv(netdev);
2657
2658         if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
2659                 return;
2660
2661         if (!mlx5e_vxlan_allowed(priv->mdev))
2662                 return;
2663
2664         mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0);
2665 }
2666
2667 static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
2668                                                     struct sk_buff *skb,
2669                                                     netdev_features_t features)
2670 {
2671         struct udphdr *udph;
2672         u16 proto;
2673         u16 port = 0;
2674
2675         switch (vlan_get_protocol(skb)) {
2676         case htons(ETH_P_IP):
2677                 proto = ip_hdr(skb)->protocol;
2678                 break;
2679         case htons(ETH_P_IPV6):
2680                 proto = ipv6_hdr(skb)->nexthdr;
2681                 break;
2682         default:
2683                 goto out;
2684         }
2685
2686         if (proto == IPPROTO_UDP) {
2687                 udph = udp_hdr(skb);
2688                 port = be16_to_cpu(udph->dest);
2689         }
2690
2691         /* Verify if UDP port is being offloaded by HW */
2692         if (port && mlx5e_vxlan_lookup_port(priv, port))
2693                 return features;
2694
2695 out:
2696         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
2697         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2698 }
2699
2700 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
2701                                               struct net_device *netdev,
2702                                               netdev_features_t features)
2703 {
2704         struct mlx5e_priv *priv = netdev_priv(netdev);
2705
2706         features = vlan_features_check(skb, features);
2707         features = vxlan_features_check(skb, features);
2708
2709         /* Validate if the tunneled packet is being offloaded by HW */
2710         if (skb->encapsulation &&
2711             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
2712                 return mlx5e_vxlan_features_check(priv, skb, features);
2713
2714         return features;
2715 }
2716
2717 static const struct net_device_ops mlx5e_netdev_ops_basic = {
2718         .ndo_open                = mlx5e_open,
2719         .ndo_stop                = mlx5e_close,
2720         .ndo_start_xmit          = mlx5e_xmit,
2721         .ndo_setup_tc            = mlx5e_ndo_setup_tc,
2722         .ndo_select_queue        = mlx5e_select_queue,
2723         .ndo_get_stats64         = mlx5e_get_stats,
2724         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
2725         .ndo_set_mac_address     = mlx5e_set_mac,
2726         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
2727         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
2728         .ndo_set_features        = mlx5e_set_features,
2729         .ndo_change_mtu          = mlx5e_change_mtu,
2730         .ndo_do_ioctl            = mlx5e_ioctl,
2731         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
2732 #ifdef CONFIG_RFS_ACCEL
2733         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
2734 #endif
2735 };
2736
2737 static const struct net_device_ops mlx5e_netdev_ops_sriov = {
2738         .ndo_open                = mlx5e_open,
2739         .ndo_stop                = mlx5e_close,
2740         .ndo_start_xmit          = mlx5e_xmit,
2741         .ndo_setup_tc            = mlx5e_ndo_setup_tc,
2742         .ndo_select_queue        = mlx5e_select_queue,
2743         .ndo_get_stats64         = mlx5e_get_stats,
2744         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
2745         .ndo_set_mac_address     = mlx5e_set_mac,
2746         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
2747         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
2748         .ndo_set_features        = mlx5e_set_features,
2749         .ndo_change_mtu          = mlx5e_change_mtu,
2750         .ndo_do_ioctl            = mlx5e_ioctl,
2751         .ndo_udp_tunnel_add      = mlx5e_add_vxlan_port,
2752         .ndo_udp_tunnel_del      = mlx5e_del_vxlan_port,
2753         .ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,
2754         .ndo_features_check      = mlx5e_features_check,
2755 #ifdef CONFIG_RFS_ACCEL
2756         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
2757 #endif
2758         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
2759         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
2760         .ndo_set_vf_spoofchk     = mlx5e_set_vf_spoofchk,
2761         .ndo_set_vf_trust        = mlx5e_set_vf_trust,
2762         .ndo_get_vf_config       = mlx5e_get_vf_config,
2763         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
2764         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
2765 };
2766
2767 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2768 {
2769         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2770                 return -ENOTSUPP;
2771         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
2772             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
2773             !MLX5_CAP_ETH(mdev, csum_cap) ||
2774             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
2775             !MLX5_CAP_ETH(mdev, vlan_cap) ||
2776             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
2777             MLX5_CAP_FLOWTABLE(mdev,
2778                                flow_table_properties_nic_receive.max_ft_level)
2779                                < 3) {
2780                 mlx5_core_warn(mdev,
2781                                "Not creating net device, some required device capabilities are missing\n");
2782                 return -ENOTSUPP;
2783         }
2784         if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
2785                 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
2786         if (!MLX5_CAP_GEN(mdev, cq_moderation))
2787                 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
2788
2789         return 0;
2790 }
2791
2792 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
2793 {
2794         int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
2795
2796         return bf_buf_size -
2797                sizeof(struct mlx5e_tx_wqe) +
2798                2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
2799 }
2800
2801 #ifdef CONFIG_MLX5_CORE_EN_DCB
2802 static void mlx5e_ets_init(struct mlx5e_priv *priv)
2803 {
2804         int i;
2805
2806         priv->params.ets.ets_cap = mlx5_max_tc(priv->mdev) + 1;
2807         for (i = 0; i < priv->params.ets.ets_cap; i++) {
2808                 priv->params.ets.tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
2809                 priv->params.ets.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
2810                 priv->params.ets.prio_tc[i] = i;
2811         }
2812
2813         /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */
2814         priv->params.ets.prio_tc[0] = 1;
2815         priv->params.ets.prio_tc[1] = 0;
2816 }
2817 #endif
2818
2819 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
2820                                    u32 *indirection_rqt, int len,
2821                                    int num_channels)
2822 {
2823         int node = mdev->priv.numa_node;
2824         int node_num_of_cores;
2825         int i;
2826
2827         if (node == -1)
2828                 node = first_online_node;
2829
2830         node_num_of_cores = cpumask_weight(cpumask_of_node(node));
2831
2832         if (node_num_of_cores)
2833                 num_channels = min_t(int, num_channels, node_num_of_cores);
2834
2835         for (i = 0; i < len; i++)
2836                 indirection_rqt[i] = i % num_channels;
2837 }
2838
2839 static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
2840 {
2841         return MLX5_CAP_GEN(mdev, striding_rq) &&
2842                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
2843                 MLX5_CAP_ETH(mdev, reg_umr_sq);
2844 }
2845
2846 static int mlx5e_get_pci_bw(struct mlx5_core_dev *mdev, u32 *pci_bw)
2847 {
2848         enum pcie_link_width width;
2849         enum pci_bus_speed speed;
2850         int err = 0;
2851
2852         err = pcie_get_minimum_link(mdev->pdev, &speed, &width);
2853         if (err)
2854                 return err;
2855
2856         if (speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
2857                 return -EINVAL;
2858
2859         switch (speed) {
2860         case PCIE_SPEED_2_5GT:
2861                 *pci_bw = 2500 * width;
2862                 break;
2863         case PCIE_SPEED_5_0GT:
2864                 *pci_bw = 5000 * width;
2865                 break;
2866         case PCIE_SPEED_8_0GT:
2867                 *pci_bw = 8000 * width;
2868                 break;
2869         default:
2870                 return -EINVAL;
2871         }
2872
2873         return 0;
2874 }
2875
2876 static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw)
2877 {
2878         return (link_speed && pci_bw &&
2879                 (pci_bw < 40000) && (pci_bw < link_speed));
2880 }
2881
2882 void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
2883 {
2884         params->rx_cq_period_mode = cq_period_mode;
2885
2886         params->rx_cq_moderation.pkts =
2887                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
2888         params->rx_cq_moderation.usec =
2889                         MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
2890
2891         if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
2892                 params->rx_cq_moderation.usec =
2893                         MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
2894 }
2895
2896 static void mlx5e_build_netdev_priv(struct mlx5_core_dev *mdev,
2897                                     struct net_device *netdev,
2898                                     int num_channels)
2899 {
2900         struct mlx5e_priv *priv = netdev_priv(netdev);
2901         u32 link_speed = 0;
2902         u32 pci_bw = 0;
2903         u8 cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
2904                                          MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
2905                                          MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
2906
2907         priv->params.log_sq_size           =
2908                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
2909         priv->params.rq_wq_type = mlx5e_check_fragmented_striding_rq_cap(mdev) ?
2910                 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
2911                 MLX5_WQ_TYPE_LINKED_LIST;
2912
2913         /* set CQE compression */
2914         priv->params.rx_cqe_compress_admin = false;
2915         if (MLX5_CAP_GEN(mdev, cqe_compression) &&
2916             MLX5_CAP_GEN(mdev, vport_group_manager)) {
2917                 mlx5e_get_max_linkspeed(mdev, &link_speed);
2918                 mlx5e_get_pci_bw(mdev, &pci_bw);
2919                 mlx5_core_dbg(mdev, "Max link speed = %d, PCI BW = %d\n",
2920                               link_speed, pci_bw);
2921                 priv->params.rx_cqe_compress_admin =
2922                         cqe_compress_heuristic(link_speed, pci_bw);
2923         }
2924
2925         priv->params.rx_cqe_compress = priv->params.rx_cqe_compress_admin;
2926
2927         switch (priv->params.rq_wq_type) {
2928         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2929                 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
2930                 priv->params.mpwqe_log_stride_sz =
2931                         priv->params.rx_cqe_compress ?
2932                         MLX5_MPWRQ_LOG_STRIDE_SIZE_CQE_COMPRESS :
2933                         MLX5_MPWRQ_LOG_STRIDE_SIZE;
2934                 priv->params.mpwqe_log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ -
2935                         priv->params.mpwqe_log_stride_sz;
2936                 priv->params.lro_en = true;
2937                 break;
2938         default: /* MLX5_WQ_TYPE_LINKED_LIST */
2939                 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
2940         }
2941
2942         mlx5_core_info(mdev,
2943                        "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
2944                        priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
2945                        BIT(priv->params.log_rq_size),
2946                        BIT(priv->params.mpwqe_log_stride_sz),
2947                        priv->params.rx_cqe_compress_admin);
2948
2949         priv->params.min_rx_wqes = mlx5_min_rx_wqes(priv->params.rq_wq_type,
2950                                             BIT(priv->params.log_rq_size));
2951
2952         priv->params.rx_am_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
2953         mlx5e_set_rx_cq_mode_params(&priv->params, cq_period_mode);
2954
2955         priv->params.tx_cq_moderation.usec =
2956                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
2957         priv->params.tx_cq_moderation.pkts =
2958                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
2959         priv->params.tx_max_inline         = mlx5e_get_max_inline_cap(mdev);
2960         priv->params.num_tc                = 1;
2961         priv->params.rss_hfunc             = ETH_RSS_HASH_XOR;
2962
2963         netdev_rss_key_fill(priv->params.toeplitz_hash_key,
2964                             sizeof(priv->params.toeplitz_hash_key));
2965
2966         mlx5e_build_default_indir_rqt(mdev, priv->params.indirection_rqt,
2967                                       MLX5E_INDIR_RQT_SIZE, num_channels);
2968
2969         priv->params.lro_wqe_sz            =
2970                 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
2971
2972         /* Initialize pflags */
2973         MLX5E_SET_PRIV_FLAG(priv, MLX5E_PFLAG_RX_CQE_BASED_MODER,
2974                             priv->params.rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
2975
2976         priv->mdev                         = mdev;
2977         priv->netdev                       = netdev;
2978         priv->params.num_channels          = num_channels;
2979
2980 #ifdef CONFIG_MLX5_CORE_EN_DCB
2981         mlx5e_ets_init(priv);
2982 #endif
2983
2984         mutex_init(&priv->state_lock);
2985
2986         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
2987         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
2988         INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
2989 }
2990
2991 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
2992 {
2993         struct mlx5e_priv *priv = netdev_priv(netdev);
2994
2995         mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
2996         if (is_zero_ether_addr(netdev->dev_addr) &&
2997             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
2998                 eth_hw_addr_random(netdev);
2999                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
3000         }
3001 }
3002
3003 static void mlx5e_build_netdev(struct net_device *netdev)
3004 {
3005         struct mlx5e_priv *priv = netdev_priv(netdev);
3006         struct mlx5_core_dev *mdev = priv->mdev;
3007         bool fcs_supported;
3008         bool fcs_enabled;
3009
3010         SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
3011
3012         if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
3013                 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
3014 #ifdef CONFIG_MLX5_CORE_EN_DCB
3015                 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
3016 #endif
3017         } else {
3018                 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
3019         }
3020
3021         netdev->watchdog_timeo    = 15 * HZ;
3022
3023         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
3024
3025         netdev->vlan_features    |= NETIF_F_SG;
3026         netdev->vlan_features    |= NETIF_F_IP_CSUM;
3027         netdev->vlan_features    |= NETIF_F_IPV6_CSUM;
3028         netdev->vlan_features    |= NETIF_F_GRO;
3029         netdev->vlan_features    |= NETIF_F_TSO;
3030         netdev->vlan_features    |= NETIF_F_TSO6;
3031         netdev->vlan_features    |= NETIF_F_RXCSUM;
3032         netdev->vlan_features    |= NETIF_F_RXHASH;
3033
3034         if (!!MLX5_CAP_ETH(mdev, lro_cap))
3035                 netdev->vlan_features    |= NETIF_F_LRO;
3036
3037         netdev->hw_features       = netdev->vlan_features;
3038         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
3039         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
3040         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
3041
3042         if (mlx5e_vxlan_allowed(mdev)) {
3043                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL |
3044                                            NETIF_F_GSO_UDP_TUNNEL_CSUM |
3045                                            NETIF_F_GSO_PARTIAL;
3046                 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
3047                 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
3048                 netdev->hw_enc_features |= NETIF_F_TSO;
3049                 netdev->hw_enc_features |= NETIF_F_TSO6;
3050                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
3051                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM |
3052                                            NETIF_F_GSO_PARTIAL;
3053                 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
3054         }
3055
3056         mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
3057
3058         if (fcs_supported)
3059                 netdev->hw_features |= NETIF_F_RXALL;
3060
3061         netdev->features          = netdev->hw_features;
3062         if (!priv->params.lro_en)
3063                 netdev->features  &= ~NETIF_F_LRO;
3064
3065         if (fcs_enabled)
3066                 netdev->features  &= ~NETIF_F_RXALL;
3067
3068 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
3069         if (FT_CAP(flow_modify_en) &&
3070             FT_CAP(modify_root) &&
3071             FT_CAP(identified_miss_table_mode) &&
3072             FT_CAP(flow_table_modify)) {
3073                 netdev->hw_features      |= NETIF_F_HW_TC;
3074 #ifdef CONFIG_RFS_ACCEL
3075                 netdev->hw_features      |= NETIF_F_NTUPLE;
3076 #endif
3077         }
3078
3079         netdev->features         |= NETIF_F_HIGHDMA;
3080
3081         netdev->priv_flags       |= IFF_UNICAST_FLT;
3082
3083         mlx5e_set_netdev_dev_addr(netdev);
3084 }
3085
3086 static int mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
3087                              struct mlx5_core_mkey *mkey)
3088 {
3089         struct mlx5_core_dev *mdev = priv->mdev;
3090         struct mlx5_create_mkey_mbox_in *in;
3091         int err;
3092
3093         in = mlx5_vzalloc(sizeof(*in));
3094         if (!in)
3095                 return -ENOMEM;
3096
3097         in->seg.flags = MLX5_PERM_LOCAL_WRITE |
3098                         MLX5_PERM_LOCAL_READ  |
3099                         MLX5_ACCESS_MODE_PA;
3100         in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
3101         in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
3102
3103         err = mlx5_core_create_mkey(mdev, mkey, in, sizeof(*in), NULL, NULL,
3104                                     NULL);
3105
3106         kvfree(in);
3107
3108         return err;
3109 }
3110
3111 static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
3112 {
3113         struct mlx5_core_dev *mdev = priv->mdev;
3114         int err;
3115
3116         err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
3117         if (err) {
3118                 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
3119                 priv->q_counter = 0;
3120         }
3121 }
3122
3123 static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
3124 {
3125         if (!priv->q_counter)
3126                 return;
3127
3128         mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
3129 }
3130
3131 static int mlx5e_create_umr_mkey(struct mlx5e_priv *priv)
3132 {
3133         struct mlx5_core_dev *mdev = priv->mdev;
3134         struct mlx5_create_mkey_mbox_in *in;
3135         struct mlx5_mkey_seg *mkc;
3136         int inlen = sizeof(*in);
3137         u64 npages =
3138                 mlx5e_get_max_num_channels(mdev) * MLX5_CHANNEL_MAX_NUM_MTTS;
3139         int err;
3140
3141         in = mlx5_vzalloc(inlen);
3142         if (!in)
3143                 return -ENOMEM;
3144
3145         mkc = &in->seg;
3146         mkc->status = MLX5_MKEY_STATUS_FREE;
3147         mkc->flags = MLX5_PERM_UMR_EN |
3148                      MLX5_PERM_LOCAL_READ |
3149                      MLX5_PERM_LOCAL_WRITE |
3150                      MLX5_ACCESS_MODE_MTT;
3151
3152         mkc->qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
3153         mkc->flags_pd = cpu_to_be32(priv->pdn);
3154         mkc->len = cpu_to_be64(npages << PAGE_SHIFT);
3155         mkc->xlt_oct_size = cpu_to_be32(mlx5e_get_mtt_octw(npages));
3156         mkc->log2_page_size = PAGE_SHIFT;
3157
3158         err = mlx5_core_create_mkey(mdev, &priv->umr_mkey, in, inlen, NULL,
3159                                     NULL, NULL);
3160
3161         kvfree(in);
3162
3163         return err;
3164 }
3165
3166 static void *mlx5e_create_netdev(struct mlx5_core_dev *mdev)
3167 {
3168         struct net_device *netdev;
3169         struct mlx5e_priv *priv;
3170         int nch = mlx5e_get_max_num_channels(mdev);
3171         int err;
3172
3173         if (mlx5e_check_required_hca_cap(mdev))
3174                 return NULL;
3175
3176         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
3177                                     nch * MLX5E_MAX_NUM_TC,
3178                                     nch);
3179         if (!netdev) {
3180                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
3181                 return NULL;
3182         }
3183
3184         mlx5e_build_netdev_priv(mdev, netdev, nch);
3185         mlx5e_build_netdev(netdev);
3186
3187         netif_carrier_off(netdev);
3188
3189         priv = netdev_priv(netdev);
3190
3191         priv->wq = create_singlethread_workqueue("mlx5e");
3192         if (!priv->wq)
3193                 goto err_free_netdev;
3194
3195         err = mlx5_alloc_map_uar(mdev, &priv->cq_uar, false);
3196         if (err) {
3197                 mlx5_core_err(mdev, "alloc_map uar failed, %d\n", err);
3198                 goto err_destroy_wq;
3199         }
3200
3201         err = mlx5_core_alloc_pd(mdev, &priv->pdn);
3202         if (err) {
3203                 mlx5_core_err(mdev, "alloc pd failed, %d\n", err);
3204                 goto err_unmap_free_uar;
3205         }
3206
3207         err = mlx5_core_alloc_transport_domain(mdev, &priv->tdn);
3208         if (err) {
3209                 mlx5_core_err(mdev, "alloc td failed, %d\n", err);
3210                 goto err_dealloc_pd;
3211         }
3212
3213         err = mlx5e_create_mkey(priv, priv->pdn, &priv->mkey);
3214         if (err) {
3215                 mlx5_core_err(mdev, "create mkey failed, %d\n", err);
3216                 goto err_dealloc_transport_domain;
3217         }
3218
3219         err = mlx5e_create_umr_mkey(priv);
3220         if (err) {
3221                 mlx5_core_err(mdev, "create umr mkey failed, %d\n", err);
3222                 goto err_destroy_mkey;
3223         }
3224
3225         err = mlx5e_create_tises(priv);
3226         if (err) {
3227                 mlx5_core_warn(mdev, "create tises failed, %d\n", err);
3228                 goto err_destroy_umr_mkey;
3229         }
3230
3231         err = mlx5e_open_drop_rq(priv);
3232         if (err) {
3233                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
3234                 goto err_destroy_tises;
3235         }
3236
3237         err = mlx5e_create_rqts(priv);
3238         if (err) {
3239                 mlx5_core_warn(mdev, "create rqts failed, %d\n", err);
3240                 goto err_close_drop_rq;
3241         }
3242
3243         err = mlx5e_create_tirs(priv);
3244         if (err) {
3245                 mlx5_core_warn(mdev, "create tirs failed, %d\n", err);
3246                 goto err_destroy_rqts;
3247         }
3248
3249         err = mlx5e_create_flow_steering(priv);
3250         if (err) {
3251                 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
3252                 goto err_destroy_tirs;
3253         }
3254
3255         mlx5e_create_q_counter(priv);
3256
3257         mlx5e_init_l2_addr(priv);
3258
3259         mlx5e_vxlan_init(priv);
3260
3261         err = mlx5e_tc_init(priv);
3262         if (err)
3263                 goto err_dealloc_q_counters;
3264
3265 #ifdef CONFIG_MLX5_CORE_EN_DCB
3266         mlx5e_dcbnl_ieee_setets_core(priv, &priv->params.ets);
3267 #endif
3268
3269         err = register_netdev(netdev);
3270         if (err) {
3271                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
3272                 goto err_tc_cleanup;
3273         }
3274
3275         if (mlx5e_vxlan_allowed(mdev)) {
3276                 rtnl_lock();
3277                 udp_tunnel_get_rx_info(netdev);
3278                 rtnl_unlock();
3279         }
3280
3281         mlx5e_enable_async_events(priv);
3282         queue_work(priv->wq, &priv->set_rx_mode_work);
3283
3284         return priv;
3285
3286 err_tc_cleanup:
3287         mlx5e_tc_cleanup(priv);
3288
3289 err_dealloc_q_counters:
3290         mlx5e_destroy_q_counter(priv);
3291         mlx5e_destroy_flow_steering(priv);
3292
3293 err_destroy_tirs:
3294         mlx5e_destroy_tirs(priv);
3295
3296 err_destroy_rqts:
3297         mlx5e_destroy_rqts(priv);
3298
3299 err_close_drop_rq:
3300         mlx5e_close_drop_rq(priv);
3301
3302 err_destroy_tises:
3303         mlx5e_destroy_tises(priv);
3304
3305 err_destroy_umr_mkey:
3306         mlx5_core_destroy_mkey(mdev, &priv->umr_mkey);
3307
3308 err_destroy_mkey:
3309         mlx5_core_destroy_mkey(mdev, &priv->mkey);
3310
3311 err_dealloc_transport_domain:
3312         mlx5_core_dealloc_transport_domain(mdev, priv->tdn);
3313
3314 err_dealloc_pd:
3315         mlx5_core_dealloc_pd(mdev, priv->pdn);
3316
3317 err_unmap_free_uar:
3318         mlx5_unmap_free_uar(mdev, &priv->cq_uar);
3319
3320 err_destroy_wq:
3321         destroy_workqueue(priv->wq);
3322
3323 err_free_netdev:
3324         free_netdev(netdev);
3325
3326         return NULL;
3327 }
3328
3329 static void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, void *vpriv)
3330 {
3331         struct mlx5e_priv *priv = vpriv;
3332         struct net_device *netdev = priv->netdev;
3333
3334         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
3335
3336         queue_work(priv->wq, &priv->set_rx_mode_work);
3337         mlx5e_disable_async_events(priv);
3338         flush_workqueue(priv->wq);
3339         if (test_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &mdev->intf_state)) {
3340                 netif_device_detach(netdev);
3341                 mlx5e_close(netdev);
3342         } else {
3343                 unregister_netdev(netdev);
3344         }
3345
3346         mlx5e_tc_cleanup(priv);
3347         mlx5e_vxlan_cleanup(priv);
3348         mlx5e_destroy_q_counter(priv);
3349         mlx5e_destroy_flow_steering(priv);
3350         mlx5e_destroy_tirs(priv);
3351         mlx5e_destroy_rqts(priv);
3352         mlx5e_close_drop_rq(priv);
3353         mlx5e_destroy_tises(priv);
3354         mlx5_core_destroy_mkey(priv->mdev, &priv->umr_mkey);
3355         mlx5_core_destroy_mkey(priv->mdev, &priv->mkey);
3356         mlx5_core_dealloc_transport_domain(priv->mdev, priv->tdn);
3357         mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
3358         mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
3359         cancel_delayed_work_sync(&priv->update_stats_work);
3360         destroy_workqueue(priv->wq);
3361
3362         if (!test_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &mdev->intf_state))
3363                 free_netdev(netdev);
3364 }
3365
3366 static void *mlx5e_get_netdev(void *vpriv)
3367 {
3368         struct mlx5e_priv *priv = vpriv;
3369
3370         return priv->netdev;
3371 }
3372
3373 static struct mlx5_interface mlx5e_interface = {
3374         .add       = mlx5e_create_netdev,
3375         .remove    = mlx5e_destroy_netdev,
3376         .event     = mlx5e_async_event,
3377         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
3378         .get_dev   = mlx5e_get_netdev,
3379 };
3380
3381 void mlx5e_init(void)
3382 {
3383         mlx5e_build_ptys2ethtool_map();
3384         mlx5_register_interface(&mlx5e_interface);
3385 }
3386
3387 void mlx5e_cleanup(void)
3388 {
3389         mlx5_unregister_interface(&mlx5e_interface);
3390 }