drivers/net/ethernet/mellanox/mlx5/core/en_main.c

   1 /*
   2  * Copyright (c) 2015-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <net/tc_act/tc_gact.h>
  34 #include <net/pkt_cls.h>
  35 #include <linux/mlx5/fs.h>
  36 #include <net/vxlan.h>
  37 #include "en.h"
  38 #include "en_tc.h"
  39 #include "eswitch.h"
  40 #include "vxlan.h"
  41
  42 struct mlx5e_rq_param {
  43         u32                        rqc[MLX5_ST_SZ_DW(rqc)];
  44         struct mlx5_wq_param       wq;
  45 };
  46
  47 struct mlx5e_sq_param {
  48         u32                        sqc[MLX5_ST_SZ_DW(sqc)];
  49         struct mlx5_wq_param       wq;
  50         u16                        max_inline;
  51         bool                       icosq;
  52 };
  53
  54 struct mlx5e_cq_param {
  55         u32                        cqc[MLX5_ST_SZ_DW(cqc)];
  56         struct mlx5_wq_param       wq;
  57         u16                        eq_ix;
  58 };
  59
  60 struct mlx5e_channel_param {
  61         struct mlx5e_rq_param      rq;
  62         struct mlx5e_sq_param      sq;
  63         struct mlx5e_sq_param      icosq;
  64         struct mlx5e_cq_param      rx_cq;
  65         struct mlx5e_cq_param      tx_cq;
  66         struct mlx5e_cq_param      icosq_cq;
  67 };
  68
  69 static void mlx5e_update_carrier(struct mlx5e_priv *priv)
  70 {
  71         struct mlx5_core_dev *mdev = priv->mdev;
  72         u8 port_state;
  73
  74         port_state = mlx5_query_vport_state(mdev,
  75                 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
  76
  77         if (port_state == VPORT_STATE_UP)
  78                 netif_carrier_on(priv->netdev);
  79         else
  80                 netif_carrier_off(priv->netdev);
  81 }
  82
  83 static void mlx5e_update_carrier_work(struct work_struct *work)
  84 {
  85         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
  86                                                update_carrier_work);
  87
  88         mutex_lock(&priv->state_lock);
  89         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
  90                 mlx5e_update_carrier(priv);
  91         mutex_unlock(&priv->state_lock);
  92 }
  93
  94 static void mlx5e_update_sw_counters(struct mlx5e_priv *priv)
  95 {
  96         struct mlx5e_sw_stats *s = &priv->stats.sw;
  97         struct mlx5e_rq_stats *rq_stats;
  98         struct mlx5e_sq_stats *sq_stats;
  99         u64 tx_offload_none = 0;
 100         int i, j;
 101
 102         memset(s, 0, sizeof(*s));
 103         for (i = 0; i < priv->params.num_channels; i++) {
 104                 rq_stats = &priv->channel[i]->rq.stats;
 105
 106                 s->rx_packets   += rq_stats->packets;
 107                 s->rx_bytes     += rq_stats->bytes;
 108                 s->lro_packets  += rq_stats->lro_packets;
 109                 s->lro_bytes    += rq_stats->lro_bytes;
 110                 s->rx_csum_none += rq_stats->csum_none;
 111                 s->rx_csum_sw   += rq_stats->csum_sw;
 112                 s->rx_csum_inner += rq_stats->csum_inner;
 113                 s->rx_wqe_err   += rq_stats->wqe_err;
 114                 s->rx_mpwqe_filler += rq_stats->mpwqe_filler;
 115                 s->rx_mpwqe_frag   += rq_stats->mpwqe_frag;
 116                 s->rx_buff_alloc_err += rq_stats->buff_alloc_err;
 117                 s->rx_cqe_compress_blks += rq_stats->cqe_compress_blks;
 118                 s->rx_cqe_compress_pkts += rq_stats->cqe_compress_pkts;
 119
 120                 for (j = 0; j < priv->params.num_tc; j++) {
 121                         sq_stats = &priv->channel[i]->sq[j].stats;
 122
 123                         s->tx_packets           += sq_stats->packets;
 124                         s->tx_bytes             += sq_stats->bytes;
 125                         s->tso_packets          += sq_stats->tso_packets;
 126                         s->tso_bytes            += sq_stats->tso_bytes;
 127                         s->tso_inner_packets    += sq_stats->tso_inner_packets;
 128                         s->tso_inner_bytes      += sq_stats->tso_inner_bytes;
 129                         s->tx_queue_stopped     += sq_stats->stopped;
 130                         s->tx_queue_wake        += sq_stats->wake;
 131                         s->tx_queue_dropped     += sq_stats->dropped;
 132                         s->tx_csum_inner        += sq_stats->csum_offload_inner;
 133                         tx_offload_none         += sq_stats->csum_offload_none;
 134                 }
 135         }
 136
 137         /* Update calculated offload counters */
 138         s->tx_csum_offload = s->tx_packets - tx_offload_none - s->tx_csum_inner;
 139         s->rx_csum_good    = s->rx_packets - s->rx_csum_none -
 140                              s->rx_csum_sw;
 141
 142         s->link_down_events = MLX5_GET(ppcnt_reg,
 143                                 priv->stats.pport.phy_counters,
 144                                 counter_set.phys_layer_cntrs.link_down_events);
 145 }
 146
 147 static void mlx5e_update_vport_counters(struct mlx5e_priv *priv)
 148 {
 149         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
 150         u32 *out = (u32 *)priv->stats.vport.query_vport_out;
 151         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
 152         struct mlx5_core_dev *mdev = priv->mdev;
 153
 154         memset(in, 0, sizeof(in));
 155
 156         MLX5_SET(query_vport_counter_in, in, opcode,
 157                  MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 158         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 159         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 160
 161         memset(out, 0, outlen);
 162
 163         mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen);
 164 }
 165
 166 static void mlx5e_update_pport_counters(struct mlx5e_priv *priv)
 167 {
 168         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
 169         struct mlx5_core_dev *mdev = priv->mdev;
 170         int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
 171         int prio;
 172         void *out;
 173         u32 *in;
 174
 175         in = mlx5_vzalloc(sz);
 176         if (!in)
 177                 goto free_out;
 178
 179         MLX5_SET(ppcnt_reg, in, local_port, 1);
 180
 181         out = pstats->IEEE_802_3_counters;
 182         MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
 183         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 184
 185         out = pstats->RFC_2863_counters;
 186         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
 187         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 188
 189         out = pstats->RFC_2819_counters;
 190         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
 191         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 192
 193         out = pstats->phy_counters;
 194         MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
 195         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 196
 197         MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
 198         for (prio = 0; prio < NUM_PPORT_PRIO; prio++) {
 199                 out = pstats->per_prio_counters[prio];
 200                 MLX5_SET(ppcnt_reg, in, prio_tc, prio);
 201                 mlx5_core_access_reg(mdev, in, sz, out, sz,
 202                                      MLX5_REG_PPCNT, 0, 0);
 203         }
 204
 205 free_out:
 206         kvfree(in);
 207 }
 208
 209 static void mlx5e_update_q_counter(struct mlx5e_priv *priv)
 210 {
 211         struct mlx5e_qcounter_stats *qcnt = &priv->stats.qcnt;
 212
 213         if (!priv->q_counter)
 214                 return;
 215
 216         mlx5_core_query_out_of_buffer(priv->mdev, priv->q_counter,
 217                                       &qcnt->rx_out_of_buffer);
 218 }
 219
 220 void mlx5e_update_stats(struct mlx5e_priv *priv)
 221 {
 222         mlx5e_update_q_counter(priv);
 223         mlx5e_update_vport_counters(priv);
 224         mlx5e_update_pport_counters(priv);
 225         mlx5e_update_sw_counters(priv);
 226 }
 227
 228 static void mlx5e_update_stats_work(struct work_struct *work)
 229 {
 230         struct delayed_work *dwork = to_delayed_work(work);
 231         struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
 232                                                update_stats_work);
 233         mutex_lock(&priv->state_lock);
 234         if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
 235                 mlx5e_update_stats(priv);
 236                 queue_delayed_work(priv->wq, dwork,
 237                                    msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
 238         }
 239         mutex_unlock(&priv->state_lock);
 240 }
 241
 242 static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 243                               enum mlx5_dev_event event, unsigned long param)
 244 {
 245         struct mlx5e_priv *priv = vpriv;
 246
 247         if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
 248                 return;
 249
 250         switch (event) {
 251         case MLX5_DEV_EVENT_PORT_UP:
 252         case MLX5_DEV_EVENT_PORT_DOWN:
 253                 queue_work(priv->wq, &priv->update_carrier_work);
 254                 break;
 255
 256         default:
 257                 break;
 258         }
 259 }
 260
 261 static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
 262 {
 263         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 264 }
 265
 266 static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
 267 {
 268         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 269         synchronize_irq(mlx5_get_msix_vec(priv->mdev, MLX5_EQ_VEC_ASYNC));
 270 }
 271
 272 #define MLX5E_HW2SW_MTU(hwmtu) (hwmtu - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 273 #define MLX5E_SW2HW_MTU(swmtu) (swmtu + (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN))
 274
 275 static int mlx5e_create_rq(struct mlx5e_channel *c,
 276                            struct mlx5e_rq_param *param,
 277                            struct mlx5e_rq *rq)
 278 {
 279         struct mlx5e_priv *priv = c->priv;
 280         struct mlx5_core_dev *mdev = priv->mdev;
 281         void *rqc = param->rqc;
 282         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 283         u32 byte_count;
 284         int wq_sz;
 285         int err;
 286         int i;
 287
 288         param->wq.db_numa_node = cpu_to_node(c->cpu);
 289
 290         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
 291                                 &rq->wq_ctrl);
 292         if (err)
 293                 return err;
 294
 295         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
 296
 297         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 298
 299         switch (priv->params.rq_wq_type) {
 300         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 301                 rq->wqe_info = kzalloc_node(wq_sz * sizeof(*rq->wqe_info),
 302                                             GFP_KERNEL, cpu_to_node(c->cpu));
 303                 if (!rq->wqe_info) {
 304                         err = -ENOMEM;
 305                         goto err_rq_wq_destroy;
 306                 }
 307                 rq->handle_rx_cqe = mlx5e_handle_rx_cqe_mpwrq;
 308                 rq->alloc_wqe = mlx5e_alloc_rx_mpwqe;
 309
 310                 rq->wqe_sz = MLX5_MPWRQ_NUM_STRIDES * MLX5_MPWRQ_STRIDE_SIZE;
 311                 byte_count = rq->wqe_sz;
 312                 break;
 313         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 314                 rq->skb = kzalloc_node(wq_sz * sizeof(*rq->skb), GFP_KERNEL,
 315                                        cpu_to_node(c->cpu));
 316                 if (!rq->skb) {
 317                         err = -ENOMEM;
 318                         goto err_rq_wq_destroy;
 319                 }
 320                 rq->handle_rx_cqe = mlx5e_handle_rx_cqe;
 321                 rq->alloc_wqe = mlx5e_alloc_rx_wqe;
 322
 323                 rq->wqe_sz = (priv->params.lro_en) ?
 324                                 priv->params.lro_wqe_sz :
 325                                 MLX5E_SW2HW_MTU(priv->netdev->mtu);
 326                 rq->wqe_sz = SKB_DATA_ALIGN(rq->wqe_sz);
 327                 byte_count = rq->wqe_sz;
 328                 byte_count |= MLX5_HW_START_PADDING;
 329         }
 330
 331         for (i = 0; i < wq_sz; i++) {
 332                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
 333
 334                 wqe->data.byte_count = cpu_to_be32(byte_count);
 335         }
 336
 337         rq->wq_type = priv->params.rq_wq_type;
 338         rq->pdev    = c->pdev;
 339         rq->netdev  = c->netdev;
 340         rq->tstamp  = &priv->tstamp;
 341         rq->channel = c;
 342         rq->ix      = c->ix;
 343         rq->priv    = c->priv;
 344         rq->mkey_be = c->mkey_be;
 345         rq->umr_mkey_be = cpu_to_be32(c->priv->umr_mkey.key);
 346
 347         return 0;
 348
 349 err_rq_wq_destroy:
 350         mlx5_wq_destroy(&rq->wq_ctrl);
 351
 352         return err;
 353 }
 354
 355 static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
 356 {
 357         switch (rq->wq_type) {
 358         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
 359                 kfree(rq->wqe_info);
 360                 break;
 361         default: /* MLX5_WQ_TYPE_LINKED_LIST */
 362                 kfree(rq->skb);
 363         }
 364
 365         mlx5_wq_destroy(&rq->wq_ctrl);
 366 }
 367
 368 static int mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 369 {
 370         struct mlx5e_priv *priv = rq->priv;
 371         struct mlx5_core_dev *mdev = priv->mdev;
 372
 373         void *in;
 374         void *rqc;
 375         void *wq;
 376         int inlen;
 377         int err;
 378
 379         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 380                 sizeof(u64) * rq->wq_ctrl.buf.npages;
 381         in = mlx5_vzalloc(inlen);
 382         if (!in)
 383                 return -ENOMEM;
 384
 385         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 386         wq  = MLX5_ADDR_OF(rqc, rqc, wq);
 387
 388         memcpy(rqc, param->rqc, sizeof(param->rqc));
 389
 390         MLX5_SET(rqc,  rqc, cqn,                rq->cq.mcq.cqn);
 391         MLX5_SET(rqc,  rqc, state,              MLX5_RQC_STATE_RST);
 392         MLX5_SET(rqc,  rqc, flush_in_error_en,  1);
 393         MLX5_SET(rqc,  rqc, vsd, priv->params.vlan_strip_disable);
 394         MLX5_SET(wq,   wq,  log_wq_pg_sz,       rq->wq_ctrl.buf.page_shift -
 395                                                 MLX5_ADAPTER_PAGE_SHIFT);
 396         MLX5_SET64(wq, wq,  dbr_addr,           rq->wq_ctrl.db.dma);
 397
 398         mlx5_fill_page_array(&rq->wq_ctrl.buf,
 399                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 400
 401         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 402
 403         kvfree(in);
 404
 405         return err;
 406 }
 407
 408 static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
 409                                  int next_state)
 410 {
 411         struct mlx5e_channel *c = rq->channel;
 412         struct mlx5e_priv *priv = c->priv;
 413         struct mlx5_core_dev *mdev = priv->mdev;
 414
 415         void *in;
 416         void *rqc;
 417         int inlen;
 418         int err;
 419
 420         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 421         in = mlx5_vzalloc(inlen);
 422         if (!in)
 423                 return -ENOMEM;
 424
 425         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 426
 427         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 428         MLX5_SET(rqc, rqc, state, next_state);
 429
 430         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 431
 432         kvfree(in);
 433
 434         return err;
 435 }
 436
 437 static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
 438 {
 439         struct mlx5e_channel *c = rq->channel;
 440         struct mlx5e_priv *priv = c->priv;
 441         struct mlx5_core_dev *mdev = priv->mdev;
 442
 443         void *in;
 444         void *rqc;
 445         int inlen;
 446         int err;
 447
 448         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 449         in = mlx5_vzalloc(inlen);
 450         if (!in)
 451                 return -ENOMEM;
 452
 453         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 454
 455         MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
 456         MLX5_SET64(modify_rq_in, in, modify_bitmask, MLX5_RQ_BITMASK_VSD);
 457         MLX5_SET(rqc, rqc, vsd, vsd);
 458         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
 459
 460         err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
 461
 462         kvfree(in);
 463
 464         return err;
 465 }
 466
 467 static void mlx5e_disable_rq(struct mlx5e_rq *rq)
 468 {
 469         mlx5_core_destroy_rq(rq->priv->mdev, rq->rqn);
 470 }
 471
 472 static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
 473 {
 474         unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
 475         struct mlx5e_channel *c = rq->channel;
 476         struct mlx5e_priv *priv = c->priv;
 477         struct mlx5_wq_ll *wq = &rq->wq;
 478
 479         while (time_before(jiffies, exp_time)) {
 480                 if (wq->cur_sz >= priv->params.min_rx_wqes)
 481                         return 0;
 482
 483                 msleep(20);
 484         }
 485
 486         return -ETIMEDOUT;
 487 }
 488
 489 static int mlx5e_open_rq(struct mlx5e_channel *c,
 490                          struct mlx5e_rq_param *param,
 491                          struct mlx5e_rq *rq)
 492 {
 493         struct mlx5e_sq *sq = &c->icosq;
 494         u16 pi = sq->pc & sq->wq.sz_m1;
 495         int err;
 496
 497         err = mlx5e_create_rq(c, param, rq);
 498         if (err)
 499                 return err;
 500
 501         err = mlx5e_enable_rq(rq, param);
 502         if (err)
 503                 goto err_destroy_rq;
 504
 505         err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 506         if (err)
 507                 goto err_disable_rq;
 508
 509         set_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
 510
 511         sq->ico_wqe_info[pi].opcode     = MLX5_OPCODE_NOP;
 512         sq->ico_wqe_info[pi].num_wqebbs = 1;
 513         mlx5e_send_nop(sq, true); /* trigger mlx5e_post_rx_wqes() */
 514
 515         return 0;
 516
 517 err_disable_rq:
 518         mlx5e_disable_rq(rq);
 519 err_destroy_rq:
 520         mlx5e_destroy_rq(rq);
 521
 522         return err;
 523 }
 524
 525 static void mlx5e_close_rq(struct mlx5e_rq *rq)
 526 {
 527         clear_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);
 528         napi_synchronize(&rq->channel->napi); /* prevent mlx5e_post_rx_wqes */
 529
 530         mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
 531         while (!mlx5_wq_ll_is_empty(&rq->wq))
 532                 msleep(20);
 533
 534         /* avoid destroying rq before mlx5e_poll_rx_cq() is done with it */
 535         napi_synchronize(&rq->channel->napi);
 536
 537         mlx5e_disable_rq(rq);
 538         mlx5e_destroy_rq(rq);
 539 }
 540
 541 static void mlx5e_free_sq_db(struct mlx5e_sq *sq)
 542 {
 543         kfree(sq->wqe_info);
 544         kfree(sq->dma_fifo);
 545         kfree(sq->skb);
 546 }
 547
 548 static int mlx5e_alloc_sq_db(struct mlx5e_sq *sq, int numa)
 549 {
 550         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 551         int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
 552
 553         sq->skb = kzalloc_node(wq_sz * sizeof(*sq->skb), GFP_KERNEL, numa);
 554         sq->dma_fifo = kzalloc_node(df_sz * sizeof(*sq->dma_fifo), GFP_KERNEL,
 555                                     numa);
 556         sq->wqe_info = kzalloc_node(wq_sz * sizeof(*sq->wqe_info), GFP_KERNEL,
 557                                     numa);
 558
 559         if (!sq->skb || !sq->dma_fifo || !sq->wqe_info) {
 560                 mlx5e_free_sq_db(sq);
 561                 return -ENOMEM;
 562         }
 563
 564         sq->dma_fifo_mask = df_sz - 1;
 565
 566         return 0;
 567 }
 568
 569 static int mlx5e_create_sq(struct mlx5e_channel *c,
 570                            int tc,
 571                            struct mlx5e_sq_param *param,
 572                            struct mlx5e_sq *sq)
 573 {
 574         struct mlx5e_priv *priv = c->priv;
 575         struct mlx5_core_dev *mdev = priv->mdev;
 576
 577         void *sqc = param->sqc;
 578         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
 579         int err;
 580
 581         err = mlx5_alloc_map_uar(mdev, &sq->uar, true);
 582         if (err)
 583                 return err;
 584
 585         param->wq.db_numa_node = cpu_to_node(c->cpu);
 586
 587         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
 588                                  &sq->wq_ctrl);
 589         if (err)
 590                 goto err_unmap_free_uar;
 591
 592         sq->wq.db       = &sq->wq.db[MLX5_SND_DBR];
 593         if (sq->uar.bf_map) {
 594                 set_bit(MLX5E_SQ_STATE_BF_ENABLE, &sq->state);
 595                 sq->uar_map = sq->uar.bf_map;
 596         } else {
 597                 sq->uar_map = sq->uar.map;
 598         }
 599         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
 600         sq->max_inline  = param->max_inline;
 601
 602         err = mlx5e_alloc_sq_db(sq, cpu_to_node(c->cpu));
 603         if (err)
 604                 goto err_sq_wq_destroy;
 605
 606         if (param->icosq) {
 607                 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 608
 609                 sq->ico_wqe_info = kzalloc_node(sizeof(*sq->ico_wqe_info) *
 610                                                 wq_sz,
 611                                                 GFP_KERNEL,
 612                                                 cpu_to_node(c->cpu));
 613                 if (!sq->ico_wqe_info) {
 614                         err = -ENOMEM;
 615                         goto err_free_sq_db;
 616                 }
 617         } else {
 618                 int txq_ix;
 619
 620                 txq_ix = c->ix + tc * priv->params.num_channels;
 621                 sq->txq = netdev_get_tx_queue(priv->netdev, txq_ix);
 622                 priv->txq_to_sq_map[txq_ix] = sq;
 623         }
 624
 625         sq->pdev      = c->pdev;
 626         sq->tstamp    = &priv->tstamp;
 627         sq->mkey_be   = c->mkey_be;
 628         sq->channel   = c;
 629         sq->tc        = tc;
 630         sq->edge      = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
 631         sq->bf_budget = MLX5E_SQ_BF_BUDGET;
 632
 633         return 0;
 634
 635 err_free_sq_db:
 636         mlx5e_free_sq_db(sq);
 637
 638 err_sq_wq_destroy:
 639         mlx5_wq_destroy(&sq->wq_ctrl);
 640
 641 err_unmap_free_uar:
 642         mlx5_unmap_free_uar(mdev, &sq->uar);
 643
 644         return err;
 645 }
 646
 647 static void mlx5e_destroy_sq(struct mlx5e_sq *sq)
 648 {
 649         struct mlx5e_channel *c = sq->channel;
 650         struct mlx5e_priv *priv = c->priv;
 651
 652         kfree(sq->ico_wqe_info);
 653         mlx5e_free_sq_db(sq);
 654         mlx5_wq_destroy(&sq->wq_ctrl);
 655         mlx5_unmap_free_uar(priv->mdev, &sq->uar);
 656 }
 657
 658 static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
 659 {
 660         struct mlx5e_channel *c = sq->channel;
 661         struct mlx5e_priv *priv = c->priv;
 662         struct mlx5_core_dev *mdev = priv->mdev;
 663
 664         void *in;
 665         void *sqc;
 666         void *wq;
 667         int inlen;
 668         int err;
 669
 670         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
 671                 sizeof(u64) * sq->wq_ctrl.buf.npages;
 672         in = mlx5_vzalloc(inlen);
 673         if (!in)
 674                 return -ENOMEM;
 675
 676         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
 677         wq = MLX5_ADDR_OF(sqc, sqc, wq);
 678
 679         memcpy(sqc, param->sqc, sizeof(param->sqc));
 680
 681         MLX5_SET(sqc,  sqc, tis_num_0, param->icosq ? 0 : priv->tisn[sq->tc]);
 682         MLX5_SET(sqc,  sqc, cqn,                sq->cq.mcq.cqn);
 683         MLX5_SET(sqc,  sqc, state,              MLX5_SQC_STATE_RST);
 684         MLX5_SET(sqc,  sqc, tis_lst_sz,         param->icosq ? 0 : 1);
 685         MLX5_SET(sqc,  sqc, flush_in_error_en,  1);
 686
 687         MLX5_SET(wq,   wq, wq_type,       MLX5_WQ_TYPE_CYCLIC);
 688         MLX5_SET(wq,   wq, uar_page,      sq->uar.index);
 689         MLX5_SET(wq,   wq, log_wq_pg_sz,  sq->wq_ctrl.buf.page_shift -
 690                                           MLX5_ADAPTER_PAGE_SHIFT);
 691         MLX5_SET64(wq, wq, dbr_addr,      sq->wq_ctrl.db.dma);
 692
 693         mlx5_fill_page_array(&sq->wq_ctrl.buf,
 694                              (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
 695
 696         err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
 697
 698         kvfree(in);
 699
 700         return err;
 701 }
 702
 703 static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
 704 {
 705         struct mlx5e_channel *c = sq->channel;
 706         struct mlx5e_priv *priv = c->priv;
 707         struct mlx5_core_dev *mdev = priv->mdev;
 708
 709         void *in;
 710         void *sqc;
 711         int inlen;
 712         int err;
 713
 714         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
 715         in = mlx5_vzalloc(inlen);
 716         if (!in)
 717                 return -ENOMEM;
 718
 719         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
 720
 721         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
 722         MLX5_SET(sqc, sqc, state, next_state);
 723
 724         err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
 725
 726         kvfree(in);
 727
 728         return err;
 729 }
 730
 731 static void mlx5e_disable_sq(struct mlx5e_sq *sq)
 732 {
 733         struct mlx5e_channel *c = sq->channel;
 734         struct mlx5e_priv *priv = c->priv;
 735         struct mlx5_core_dev *mdev = priv->mdev;
 736
 737         mlx5_core_destroy_sq(mdev, sq->sqn);
 738 }
 739
 740 static int mlx5e_open_sq(struct mlx5e_channel *c,
 741                          int tc,
 742                          struct mlx5e_sq_param *param,
 743                          struct mlx5e_sq *sq)
 744 {
 745         int err;
 746
 747         err = mlx5e_create_sq(c, tc, param, sq);
 748         if (err)
 749                 return err;
 750
 751         err = mlx5e_enable_sq(sq, param);
 752         if (err)
 753                 goto err_destroy_sq;
 754
 755         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
 756         if (err)
 757                 goto err_disable_sq;
 758
 759         if (sq->txq) {
 760                 set_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
 761                 netdev_tx_reset_queue(sq->txq);
 762                 netif_tx_start_queue(sq->txq);
 763         }
 764
 765         return 0;
 766
 767 err_disable_sq:
 768         mlx5e_disable_sq(sq);
 769 err_destroy_sq:
 770         mlx5e_destroy_sq(sq);
 771
 772         return err;
 773 }
 774
 775 static inline void netif_tx_disable_queue(struct netdev_queue *txq)
 776 {
 777         __netif_tx_lock_bh(txq);
 778         netif_tx_stop_queue(txq);
 779         __netif_tx_unlock_bh(txq);
 780 }
 781
 782 static void mlx5e_close_sq(struct mlx5e_sq *sq)
 783 {
 784         if (sq->txq) {
 785                 clear_bit(MLX5E_SQ_STATE_WAKE_TXQ_ENABLE, &sq->state);
 786                 /* prevent netif_tx_wake_queue */
 787                 napi_synchronize(&sq->channel->napi);
 788                 netif_tx_disable_queue(sq->txq);
 789
 790                 /* ensure hw is notified of all pending wqes */
 791                 if (mlx5e_sq_has_room_for(sq, 1))
 792                         mlx5e_send_nop(sq, true);
 793
 794                 mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
 795         }
 796
 797         while (sq->cc != sq->pc) /* wait till sq is empty */
 798                 msleep(20);
 799
 800         /* avoid destroying sq before mlx5e_poll_tx_cq() is done with it */
 801         napi_synchronize(&sq->channel->napi);
 802
 803         mlx5e_disable_sq(sq);
 804         mlx5e_destroy_sq(sq);
 805 }
 806
 807 static int mlx5e_create_cq(struct mlx5e_channel *c,
 808                            struct mlx5e_cq_param *param,
 809                            struct mlx5e_cq *cq)
 810 {
 811         struct mlx5e_priv *priv = c->priv;
 812         struct mlx5_core_dev *mdev = priv->mdev;
 813         struct mlx5_core_cq *mcq = &cq->mcq;
 814         int eqn_not_used;
 815         unsigned int irqn;
 816         int err;
 817         u32 i;
 818
 819         param->wq.buf_numa_node = cpu_to_node(c->cpu);
 820         param->wq.db_numa_node  = cpu_to_node(c->cpu);
 821         param->eq_ix   = c->ix;
 822
 823         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
 824                                &cq->wq_ctrl);
 825         if (err)
 826                 return err;
 827
 828         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
 829
 830         cq->napi        = &c->napi;
 831
 832         mcq->cqe_sz     = 64;
 833         mcq->set_ci_db  = cq->wq_ctrl.db.db;
 834         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
 835         *mcq->set_ci_db = 0;
 836         *mcq->arm_db    = 0;
 837         mcq->vector     = param->eq_ix;
 838         mcq->comp       = mlx5e_completion_event;
 839         mcq->event      = mlx5e_cq_error_event;
 840         mcq->irqn       = irqn;
 841         mcq->uar        = &priv->cq_uar;
 842
 843         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
 844                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
 845
 846                 cqe->op_own = 0xf1;
 847         }
 848
 849         cq->channel = c;
 850         cq->priv = priv;
 851
 852         return 0;
 853 }
 854
 855 static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
 856 {
 857         mlx5_wq_destroy(&cq->wq_ctrl);
 858 }
 859
 860 static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
 861 {
 862         struct mlx5e_priv *priv = cq->priv;
 863         struct mlx5_core_dev *mdev = priv->mdev;
 864         struct mlx5_core_cq *mcq = &cq->mcq;
 865
 866         void *in;
 867         void *cqc;
 868         int inlen;
 869         unsigned int irqn_not_used;
 870         int eqn;
 871         int err;
 872
 873         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
 874                 sizeof(u64) * cq->wq_ctrl.buf.npages;
 875         in = mlx5_vzalloc(inlen);
 876         if (!in)
 877                 return -ENOMEM;
 878
 879         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
 880
 881         memcpy(cqc, param->cqc, sizeof(param->cqc));
 882
 883         mlx5_fill_page_array(&cq->wq_ctrl.buf,
 884                              (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
 885
 886         mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
 887
 888         MLX5_SET(cqc,   cqc, c_eqn,         eqn);
 889         MLX5_SET(cqc,   cqc, uar_page,      mcq->uar->index);
 890         MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
 891                                             MLX5_ADAPTER_PAGE_SHIFT);
 892         MLX5_SET64(cqc, cqc, dbr_addr,      cq->wq_ctrl.db.dma);
 893
 894         err = mlx5_core_create_cq(mdev, mcq, in, inlen);
 895
 896         kvfree(in);
 897
 898         if (err)
 899                 return err;
 900
 901         mlx5e_cq_arm(cq);
 902
 903         return 0;
 904 }
 905
 906 static void mlx5e_disable_cq(struct mlx5e_cq *cq)
 907 {
 908         struct mlx5e_priv *priv = cq->priv;
 909         struct mlx5_core_dev *mdev = priv->mdev;
 910
 911         mlx5_core_destroy_cq(mdev, &cq->mcq);
 912 }
 913
 914 static int mlx5e_open_cq(struct mlx5e_channel *c,
 915                          struct mlx5e_cq_param *param,
 916                          struct mlx5e_cq *cq,
 917                          u16 moderation_usecs,
 918                          u16 moderation_frames)
 919 {
 920         int err;
 921         struct mlx5e_priv *priv = c->priv;
 922         struct mlx5_core_dev *mdev = priv->mdev;
 923
 924         err = mlx5e_create_cq(c, param, cq);
 925         if (err)
 926                 return err;
 927
 928         err = mlx5e_enable_cq(cq, param);
 929         if (err)
 930                 goto err_destroy_cq;
 931
 932         if (MLX5_CAP_GEN(mdev, cq_moderation))
 933                 mlx5_core_modify_cq_moderation(mdev, &cq->mcq,
 934                                                moderation_usecs,
 935                                                moderation_frames);
 936         return 0;
 937
 938 err_destroy_cq:
 939         mlx5e_destroy_cq(cq);
 940
 941         return err;
 942 }
 943
 944 static void mlx5e_close_cq(struct mlx5e_cq *cq)
 945 {
 946         mlx5e_disable_cq(cq);
 947         mlx5e_destroy_cq(cq);
 948 }
 949
 950 static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
 951 {
 952         return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
 953 }
 954
 955 static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
 956                              struct mlx5e_channel_param *cparam)
 957 {
 958         struct mlx5e_priv *priv = c->priv;
 959         int err;
 960         int tc;
 961
 962         for (tc = 0; tc < c->num_tc; tc++) {
 963                 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
 964                                     priv->params.tx_cq_moderation_usec,
 965                                     priv->params.tx_cq_moderation_pkts);
 966                 if (err)
 967                         goto err_close_tx_cqs;
 968         }
 969
 970         return 0;
 971
 972 err_close_tx_cqs:
 973         for (tc--; tc >= 0; tc--)
 974                 mlx5e_close_cq(&c->sq[tc].cq);
 975
 976         return err;
 977 }
 978
 979 static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
 980 {
 981         int tc;
 982
 983         for (tc = 0; tc < c->num_tc; tc++)
 984                 mlx5e_close_cq(&c->sq[tc].cq);
 985 }
 986
 987 static int mlx5e_open_sqs(struct mlx5e_channel *c,
 988                           struct mlx5e_channel_param *cparam)
 989 {
 990         int err;
 991         int tc;
 992
 993         for (tc = 0; tc < c->num_tc; tc++) {
 994                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
 995                 if (err)
 996                         goto err_close_sqs;
 997         }
 998
 999         return 0;
1000
1001 err_close_sqs:
1002         for (tc--; tc >= 0; tc--)
1003                 mlx5e_close_sq(&c->sq[tc]);
1004
1005         return err;
1006 }
1007
1008 static void mlx5e_close_sqs(struct mlx5e_channel *c)
1009 {
1010         int tc;
1011
1012         for (tc = 0; tc < c->num_tc; tc++)
1013                 mlx5e_close_sq(&c->sq[tc]);
1014 }
1015
1016 static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix)
1017 {
1018         int i;
1019
1020         for (i = 0; i < MLX5E_MAX_NUM_TC; i++)
1021                 priv->channeltc_to_txq_map[ix][i] =
1022                         ix + i * priv->params.num_channels;
1023 }
1024
1025 static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1026                               struct mlx5e_channel_param *cparam,
1027                               struct mlx5e_channel **cp)
1028 {
1029         struct net_device *netdev = priv->netdev;
1030         int cpu = mlx5e_get_cpu(priv, ix);
1031         struct mlx5e_channel *c;
1032         int err;
1033
1034         c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1035         if (!c)
1036                 return -ENOMEM;
1037
1038         c->priv     = priv;
1039         c->ix       = ix;
1040         c->cpu      = cpu;
1041         c->pdev     = &priv->mdev->pdev->dev;
1042         c->netdev   = priv->netdev;
1043         c->mkey_be  = cpu_to_be32(priv->mkey.key);
1044         c->num_tc   = priv->params.num_tc;
1045
1046         mlx5e_build_channeltc_to_txq_map(priv, ix);
1047
1048         netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1049
1050         err = mlx5e_open_cq(c, &cparam->icosq_cq, &c->icosq.cq, 0, 0);
1051         if (err)
1052                 goto err_napi_del;
1053
1054         err = mlx5e_open_tx_cqs(c, cparam);
1055         if (err)
1056                 goto err_close_icosq_cq;
1057
1058         err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
1059                             priv->params.rx_cq_moderation_usec,
1060                             priv->params.rx_cq_moderation_pkts);
1061         if (err)
1062                 goto err_close_tx_cqs;
1063
1064         napi_enable(&c->napi);
1065
1066         err = mlx5e_open_sq(c, 0, &cparam->icosq, &c->icosq);
1067         if (err)
1068                 goto err_disable_napi;
1069
1070         err = mlx5e_open_sqs(c, cparam);
1071         if (err)
1072                 goto err_close_icosq;
1073
1074         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1075         if (err)
1076                 goto err_close_sqs;
1077
1078         netif_set_xps_queue(netdev, get_cpu_mask(c->cpu), ix);
1079         *cp = c;
1080
1081         return 0;
1082
1083 err_close_sqs:
1084         mlx5e_close_sqs(c);
1085
1086 err_close_icosq:
1087         mlx5e_close_sq(&c->icosq);
1088
1089 err_disable_napi:
1090         napi_disable(&c->napi);
1091         mlx5e_close_cq(&c->rq.cq);
1092
1093 err_close_tx_cqs:
1094         mlx5e_close_tx_cqs(c);
1095
1096 err_close_icosq_cq:
1097         mlx5e_close_cq(&c->icosq.cq);
1098
1099 err_napi_del:
1100         netif_napi_del(&c->napi);
1101         napi_hash_del(&c->napi);
1102         kfree(c);
1103
1104         return err;
1105 }
1106
1107 static void mlx5e_close_channel(struct mlx5e_channel *c)
1108 {
1109         mlx5e_close_rq(&c->rq);
1110         mlx5e_close_sqs(c);
1111         mlx5e_close_sq(&c->icosq);
1112         napi_disable(&c->napi);
1113         mlx5e_close_cq(&c->rq.cq);
1114         mlx5e_close_tx_cqs(c);
1115         mlx5e_close_cq(&c->icosq.cq);
1116         netif_napi_del(&c->napi);
1117
1118         napi_hash_del(&c->napi);
1119         synchronize_rcu();
1120
1121         kfree(c);
1122 }
1123
1124 static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1125                                  struct mlx5e_rq_param *param)
1126 {
1127         void *rqc = param->rqc;
1128         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1129
1130         switch (priv->params.rq_wq_type) {
1131         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1132                 MLX5_SET(wq, wq, log_wqe_num_of_strides,
1133                          MLX5_MPWRQ_LOG_NUM_STRIDES - 9);
1134                 MLX5_SET(wq, wq, log_wqe_stride_size,
1135                          MLX5_MPWRQ_LOG_STRIDE_SIZE - 6);
1136                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1137                 break;
1138         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1139                 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1140         }
1141
1142         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1143         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1144         MLX5_SET(wq, wq, log_wq_sz,        priv->params.log_rq_size);
1145         MLX5_SET(wq, wq, pd,               priv->pdn);
1146         MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
1147
1148         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1149         param->wq.linear = 1;
1150 }
1151
1152 static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
1153 {
1154         void *rqc = param->rqc;
1155         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1156
1157         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1158         MLX5_SET(wq, wq, log_wq_stride,    ilog2(sizeof(struct mlx5e_rx_wqe)));
1159 }
1160
1161 static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1162                                         struct mlx5e_sq_param *param)
1163 {
1164         void *sqc = param->sqc;
1165         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1166
1167         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1168         MLX5_SET(wq, wq, pd,            priv->pdn);
1169
1170         param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1171 }
1172
1173 static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1174                                  struct mlx5e_sq_param *param)
1175 {
1176         void *sqc = param->sqc;
1177         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1178
1179         mlx5e_build_sq_param_common(priv, param);
1180         MLX5_SET(wq, wq, log_wq_sz,     priv->params.log_sq_size);
1181
1182         param->max_inline = priv->params.tx_max_inline;
1183 }
1184
1185 static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1186                                         struct mlx5e_cq_param *param)
1187 {
1188         void *cqc = param->cqc;
1189
1190         MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1191 }
1192
1193 static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1194                                     struct mlx5e_cq_param *param)
1195 {
1196         void *cqc = param->cqc;
1197         u8 log_cq_size;
1198
1199         switch (priv->params.rq_wq_type) {
1200         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1201                 log_cq_size = priv->params.log_rq_size +
1202                         MLX5_MPWRQ_LOG_NUM_STRIDES;
1203                 break;
1204         default: /* MLX5_WQ_TYPE_LINKED_LIST */
1205                 log_cq_size = priv->params.log_rq_size;
1206         }
1207
1208         MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
1209         if (priv->params.rx_cqe_compress) {
1210                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1211                 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1212         }
1213
1214         mlx5e_build_common_cq_param(priv, param);
1215 }
1216
1217 static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1218                                     struct mlx5e_cq_param *param)
1219 {
1220         void *cqc = param->cqc;
1221
1222         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1223
1224         mlx5e_build_common_cq_param(priv, param);
1225 }
1226
1227 static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1228                                      struct mlx5e_cq_param *param,
1229                                      u8 log_wq_size)
1230 {
1231         void *cqc = param->cqc;
1232
1233         MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1234
1235         mlx5e_build_common_cq_param(priv, param);
1236 }
1237
1238 static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
1239                                     struct mlx5e_sq_param *param,
1240                                     u8 log_wq_size)
1241 {
1242         void *sqc = param->sqc;
1243         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1244
1245         mlx5e_build_sq_param_common(priv, param);
1246
1247         MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
1248         MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
1249
1250         param->icosq = true;
1251 }
1252
1253 static void mlx5e_build_channel_param(struct mlx5e_priv *priv, struct mlx5e_channel_param *cparam)
1254 {
1255         u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
1256
1257         mlx5e_build_rq_param(priv, &cparam->rq);
1258         mlx5e_build_sq_param(priv, &cparam->sq);
1259         mlx5e_build_icosq_param(priv, &cparam->icosq, icosq_log_wq_sz);
1260         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1261         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1262         mlx5e_build_ico_cq_param(priv, &cparam->icosq_cq, icosq_log_wq_sz);
1263 }
1264
1265 static int mlx5e_open_channels(struct mlx5e_priv *priv)
1266 {
1267         struct mlx5e_channel_param *cparam;
1268         int nch = priv->params.num_channels;
1269         int err = -ENOMEM;
1270         int i;
1271         int j;
1272
1273         priv->channel = kcalloc(nch, sizeof(struct mlx5e_channel *),
1274                                 GFP_KERNEL);
1275
1276         priv->txq_to_sq_map = kcalloc(nch * priv->params.num_tc,
1277                                       sizeof(struct mlx5e_sq *), GFP_KERNEL);
1278
1279         cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
1280
1281         if (!priv->channel || !priv->txq_to_sq_map || !cparam)
1282                 goto err_free_txq_to_sq_map;
1283
1284         mlx5e_build_channel_param(priv, cparam);
1285
1286         for (i = 0; i < nch; i++) {
1287                 err = mlx5e_open_channel(priv, i, cparam, &priv->channel[i]);
1288                 if (err)
1289                         goto err_close_channels;
1290         }
1291
1292         for (j = 0; j < nch; j++) {
1293                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1294                 if (err)
1295                         goto err_close_channels;
1296         }
1297
1298         kfree(cparam);
1299         return 0;
1300
1301 err_close_channels:
1302         for (i--; i >= 0; i--)
1303                 mlx5e_close_channel(priv->channel[i]);
1304
1305 err_free_txq_to_sq_map:
1306         kfree(priv->txq_to_sq_map);
1307         kfree(priv->channel);
1308         kfree(cparam);
1309
1310         return err;
1311 }
1312
1313 static void mlx5e_close_channels(struct mlx5e_priv *priv)
1314 {
1315         int i;
1316
1317         for (i = 0; i < priv->params.num_channels; i++)
1318                 mlx5e_close_channel(priv->channel[i]);
1319
1320         kfree(priv->txq_to_sq_map);
1321         kfree(priv->channel);
1322 }
1323
1324 static int mlx5e_rx_hash_fn(int hfunc)
1325 {
1326         return (hfunc == ETH_RSS_HASH_TOP) ?
1327                MLX5_RX_HASH_FN_TOEPLITZ :
1328                MLX5_RX_HASH_FN_INVERTED_XOR8;
1329 }
1330
1331 static int mlx5e_bits_invert(unsigned long a, int size)
1332 {
1333         int inv = 0;
1334         int i;
1335
1336         for (i = 0; i < size; i++)
1337                 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
1338
1339         return inv;
1340 }
1341
1342 static void mlx5e_fill_indir_rqt_rqns(struct mlx5e_priv *priv, void *rqtc)
1343 {
1344         int i;
1345
1346         for (i = 0; i < MLX5E_INDIR_RQT_SIZE; i++) {
1347                 int ix = i;
1348                 u32 rqn;
1349
1350                 if (priv->params.rss_hfunc == ETH_RSS_HASH_XOR)
1351                         ix = mlx5e_bits_invert(i, MLX5E_LOG_INDIR_RQT_SIZE);
1352
1353                 ix = priv->params.indirection_rqt[ix];
1354                 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1355                                 priv->channel[ix]->rq.rqn :
1356                                 priv->drop_rq.rqn;
1357                 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
1358         }
1359 }
1360
1361 static void mlx5e_fill_direct_rqt_rqn(struct mlx5e_priv *priv, void *rqtc,
1362                                       int ix)
1363 {
1364         u32 rqn = test_bit(MLX5E_STATE_OPENED, &priv->state) ?
1365                         priv->channel[ix]->rq.rqn :
1366                         priv->drop_rq.rqn;
1367
1368         MLX5_SET(rqtc, rqtc, rq_num[0], rqn);
1369 }
1370
1371 static int mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, int ix, u32 *rqtn)
1372 {
1373         struct mlx5_core_dev *mdev = priv->mdev;
1374         void *rqtc;
1375         int inlen;
1376         int err;
1377         u32 *in;
1378
1379         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1380         in = mlx5_vzalloc(inlen);
1381         if (!in)
1382                 return -ENOMEM;
1383
1384         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1385
1386         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1387         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1388
1389         if (sz > 1) /* RSS */
1390                 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1391         else
1392                 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
1393
1394         err = mlx5_core_create_rqt(mdev, in, inlen, rqtn);
1395
1396         kvfree(in);
1397         return err;
1398 }
1399
1400 static void mlx5e_destroy_rqt(struct mlx5e_priv *priv, u32 rqtn)
1401 {
1402         mlx5_core_destroy_rqt(priv->mdev, rqtn);
1403 }
1404
1405 static int mlx5e_create_rqts(struct mlx5e_priv *priv)
1406 {
1407         int nch = mlx5e_get_max_num_channels(priv->mdev);
1408         u32 *rqtn;
1409         int err;
1410         int ix;
1411
1412         /* Indirect RQT */
1413         rqtn = &priv->indir_rqtn;
1414         err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, 0, rqtn);
1415         if (err)
1416                 return err;
1417
1418         /* Direct RQTs */
1419         for (ix = 0; ix < nch; ix++) {
1420                 rqtn = &priv->direct_tir[ix].rqtn;
1421                 err = mlx5e_create_rqt(priv, 1 /*size */, ix, rqtn);
1422                 if (err)
1423                         goto err_destroy_rqts;
1424         }
1425
1426         return 0;
1427
1428 err_destroy_rqts:
1429         for (ix--; ix >= 0; ix--)
1430                 mlx5e_destroy_rqt(priv, priv->direct_tir[ix].rqtn);
1431
1432         mlx5e_destroy_rqt(priv, priv->indir_rqtn);
1433
1434         return err;
1435 }
1436
1437 static void mlx5e_destroy_rqts(struct mlx5e_priv *priv)
1438 {
1439         int nch = mlx5e_get_max_num_channels(priv->mdev);
1440         int i;
1441
1442         for (i = 0; i < nch; i++)
1443                 mlx5e_destroy_rqt(priv, priv->direct_tir[i].rqtn);
1444
1445         mlx5e_destroy_rqt(priv, priv->indir_rqtn);
1446 }
1447
1448 int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz, int ix)
1449 {
1450         struct mlx5_core_dev *mdev = priv->mdev;
1451         void *rqtc;
1452         int inlen;
1453         u32 *in;
1454         int err;
1455
1456         inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
1457         in = mlx5_vzalloc(inlen);
1458         if (!in)
1459                 return -ENOMEM;
1460
1461         rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
1462
1463         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1464         if (sz > 1) /* RSS */
1465                 mlx5e_fill_indir_rqt_rqns(priv, rqtc);
1466         else
1467                 mlx5e_fill_direct_rqt_rqn(priv, rqtc, ix);
1468
1469         MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
1470
1471         err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
1472
1473         kvfree(in);
1474
1475         return err;
1476 }
1477
1478 static void mlx5e_redirect_rqts(struct mlx5e_priv *priv)
1479 {
1480         u32 rqtn;
1481         int ix;
1482
1483         rqtn = priv->indir_rqtn;
1484         mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, 0);
1485         for (ix = 0; ix < priv->params.num_channels; ix++) {
1486                 rqtn = priv->direct_tir[ix].rqtn;
1487                 mlx5e_redirect_rqt(priv, rqtn, 1, ix);
1488         }
1489 }
1490
1491 static void mlx5e_build_tir_ctx_lro(void *tirc, struct mlx5e_priv *priv)
1492 {
1493         if (!priv->params.lro_en)
1494                 return;
1495
1496 #define ROUGH_MAX_L2_L3_HDR_SZ 256
1497
1498         MLX5_SET(tirc, tirc, lro_enable_mask,
1499                  MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1500                  MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1501         MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
1502                  (priv->params.lro_wqe_sz -
1503                   ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1504         MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1505                  MLX5_CAP_ETH(priv->mdev,
1506                               lro_timer_supported_periods[2]));
1507 }
1508
1509 void mlx5e_build_tir_ctx_hash(void *tirc, struct mlx5e_priv *priv)
1510 {
1511         MLX5_SET(tirc, tirc, rx_hash_fn,
1512                  mlx5e_rx_hash_fn(priv->params.rss_hfunc));
1513         if (priv->params.rss_hfunc == ETH_RSS_HASH_TOP) {
1514                 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
1515                                              rx_hash_toeplitz_key);
1516                 size_t len = MLX5_FLD_SZ_BYTES(tirc,
1517                                                rx_hash_toeplitz_key);
1518
1519                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1520                 memcpy(rss_key, priv->params.toeplitz_hash_key, len);
1521         }
1522 }
1523
1524 static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
1525 {
1526         struct mlx5_core_dev *mdev = priv->mdev;
1527
1528         void *in;
1529         void *tirc;
1530         int inlen;
1531         int err;
1532         int tt;
1533         int ix;
1534
1535         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1536         in = mlx5_vzalloc(inlen);
1537         if (!in)
1538                 return -ENOMEM;
1539
1540         MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
1541         tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
1542
1543         mlx5e_build_tir_ctx_lro(tirc, priv);
1544
1545         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
1546                 err = mlx5_core_modify_tir(mdev, priv->indir_tirn[tt], in,
1547                                            inlen);
1548                 if (err)
1549                         goto free_in;
1550         }
1551
1552         for (ix = 0; ix < mlx5e_get_max_num_channels(mdev); ix++) {
1553                 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
1554                                            in, inlen);
1555                 if (err)
1556                         goto free_in;
1557         }
1558
1559 free_in:
1560         kvfree(in);
1561
1562         return err;
1563 }
1564
1565 static int mlx5e_refresh_tirs_self_loopback_enable(struct mlx5e_priv *priv)
1566 {
1567         void *in;
1568         int inlen;
1569         int err;
1570         int i;
1571
1572         inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
1573         in = mlx5_vzalloc(inlen);
1574         if (!in)
1575                 return -ENOMEM;
1576
1577         MLX5_SET(modify_tir_in, in, bitmask.self_lb_en, 1);
1578
1579         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
1580                 err = mlx5_core_modify_tir(priv->mdev, priv->indir_tirn[i], in,
1581                                            inlen);
1582                 if (err)
1583                         return err;
1584         }
1585
1586         for (i = 0; i < priv->params.num_channels; i++) {
1587                 err = mlx5_core_modify_tir(priv->mdev,
1588                                            priv->direct_tir[i].tirn, in,
1589                                            inlen);
1590                 if (err)
1591                         return err;
1592         }
1593
1594         kvfree(in);
1595
1596         return 0;
1597 }
1598
1599 static int mlx5e_set_mtu(struct mlx5e_priv *priv, u16 mtu)
1600 {
1601         struct mlx5_core_dev *mdev = priv->mdev;
1602         u16 hw_mtu = MLX5E_SW2HW_MTU(mtu);
1603         int err;
1604
1605         err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
1606         if (err)
1607                 return err;
1608
1609         /* Update vport context MTU */
1610         mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
1611         return 0;
1612 }
1613
1614 static void mlx5e_query_mtu(struct mlx5e_priv *priv, u16 *mtu)
1615 {
1616         struct mlx5_core_dev *mdev = priv->mdev;
1617         u16 hw_mtu = 0;
1618         int err;
1619
1620         err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
1621         if (err || !hw_mtu) /* fallback to port oper mtu */
1622                 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
1623
1624         *mtu = MLX5E_HW2SW_MTU(hw_mtu);
1625 }
1626
1627 static int mlx5e_set_dev_port_mtu(struct net_device *netdev)
1628 {
1629         struct mlx5e_priv *priv = netdev_priv(netdev);
1630         u16 mtu;
1631         int err;
1632
1633         err = mlx5e_set_mtu(priv, netdev->mtu);
1634         if (err)
1635                 return err;
1636
1637         mlx5e_query_mtu(priv, &mtu);
1638         if (mtu != netdev->mtu)
1639                 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
1640                             __func__, mtu, netdev->mtu);
1641
1642         netdev->mtu = mtu;
1643         return 0;
1644 }
1645
1646 static void mlx5e_netdev_set_tcs(struct net_device *netdev)
1647 {
1648         struct mlx5e_priv *priv = netdev_priv(netdev);
1649         int nch = priv->params.num_channels;
1650         int ntc = priv->params.num_tc;
1651         int tc;
1652
1653         netdev_reset_tc(netdev);
1654
1655         if (ntc == 1)
1656                 return;
1657
1658         netdev_set_num_tc(netdev, ntc);
1659
1660         for (tc = 0; tc < ntc; tc++)
1661                 netdev_set_tc_queue(netdev, tc, nch, tc * nch);
1662 }
1663
1664 int mlx5e_open_locked(struct net_device *netdev)
1665 {
1666         struct mlx5e_priv *priv = netdev_priv(netdev);
1667         int num_txqs;
1668         int err;
1669
1670         set_bit(MLX5E_STATE_OPENED, &priv->state);
1671
1672         mlx5e_netdev_set_tcs(netdev);
1673
1674         num_txqs = priv->params.num_channels * priv->params.num_tc;
1675         netif_set_real_num_tx_queues(netdev, num_txqs);
1676         netif_set_real_num_rx_queues(netdev, priv->params.num_channels);
1677
1678         err = mlx5e_set_dev_port_mtu(netdev);
1679         if (err)
1680                 goto err_clear_state_opened_flag;
1681
1682         err = mlx5e_open_channels(priv);
1683         if (err) {
1684                 netdev_err(netdev, "%s: mlx5e_open_channels failed, %d\n",
1685                            __func__, err);
1686                 goto err_clear_state_opened_flag;
1687         }
1688
1689         err = mlx5e_refresh_tirs_self_loopback_enable(priv);
1690         if (err) {
1691                 netdev_err(netdev, "%s: mlx5e_refresh_tirs_self_loopback_enable failed, %d\n",
1692                            __func__, err);
1693                 goto err_close_channels;
1694         }
1695
1696         mlx5e_redirect_rqts(priv);
1697         mlx5e_update_carrier(priv);
1698         mlx5e_timestamp_init(priv);
1699 #ifdef CONFIG_RFS_ACCEL
1700         priv->netdev->rx_cpu_rmap = priv->mdev->rmap;
1701 #endif
1702
1703         queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
1704
1705         return 0;
1706
1707 err_close_channels:
1708         mlx5e_close_channels(priv);
1709 err_clear_state_opened_flag:
1710         clear_bit(MLX5E_STATE_OPENED, &priv->state);
1711         return err;
1712 }
1713
1714 static int mlx5e_open(struct net_device *netdev)
1715 {
1716         struct mlx5e_priv *priv = netdev_priv(netdev);
1717         int err;
1718
1719         mutex_lock(&priv->state_lock);
1720         err = mlx5e_open_locked(netdev);
1721         mutex_unlock(&priv->state_lock);
1722
1723         return err;
1724 }
1725
1726 int mlx5e_close_locked(struct net_device *netdev)
1727 {
1728         struct mlx5e_priv *priv = netdev_priv(netdev);
1729
1730         /* May already be CLOSED in case a previous configuration operation
1731          * (e.g RX/TX queue size change) that involves close&open failed.
1732          */
1733         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
1734                 return 0;
1735
1736         clear_bit(MLX5E_STATE_OPENED, &priv->state);
1737
1738         mlx5e_timestamp_cleanup(priv);
1739         netif_carrier_off(priv->netdev);
1740         mlx5e_redirect_rqts(priv);
1741         mlx5e_close_channels(priv);
1742
1743         return 0;
1744 }
1745
1746 static int mlx5e_close(struct net_device *netdev)
1747 {
1748         struct mlx5e_priv *priv = netdev_priv(netdev);
1749         int err;
1750
1751         mutex_lock(&priv->state_lock);
1752         err = mlx5e_close_locked(netdev);
1753         mutex_unlock(&priv->state_lock);
1754
1755         return err;
1756 }
1757
1758 static int mlx5e_create_drop_rq(struct mlx5e_priv *priv,
1759                                 struct mlx5e_rq *rq,
1760                                 struct mlx5e_rq_param *param)
1761 {
1762         struct mlx5_core_dev *mdev = priv->mdev;
1763         void *rqc = param->rqc;
1764         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1765         int err;
1766
1767         param->wq.db_numa_node = param->wq.buf_numa_node;
1768
1769         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
1770                                 &rq->wq_ctrl);
1771         if (err)
1772                 return err;
1773
1774         rq->priv = priv;
1775
1776         return 0;
1777 }
1778
1779 static int mlx5e_create_drop_cq(struct mlx5e_priv *priv,
1780                                 struct mlx5e_cq *cq,
1781                                 struct mlx5e_cq_param *param)
1782 {
1783         struct mlx5_core_dev *mdev = priv->mdev;
1784         struct mlx5_core_cq *mcq = &cq->mcq;
1785         int eqn_not_used;
1786         unsigned int irqn;
1787         int err;
1788
1789         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1790                                &cq->wq_ctrl);
1791         if (err)
1792                 return err;
1793
1794         mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1795
1796         mcq->cqe_sz     = 64;
1797         mcq->set_ci_db  = cq->wq_ctrl.db.db;
1798         mcq->arm_db     = cq->wq_ctrl.db.db + 1;
1799         *mcq->set_ci_db = 0;
1800         *mcq->arm_db    = 0;
1801         mcq->vector     = param->eq_ix;
1802         mcq->comp       = mlx5e_completion_event;
1803         mcq->event      = mlx5e_cq_error_event;
1804         mcq->irqn       = irqn;
1805         mcq->uar        = &priv->cq_uar;
1806
1807         cq->priv = priv;
1808
1809         return 0;
1810 }
1811
1812 static int mlx5e_open_drop_rq(struct mlx5e_priv *priv)
1813 {
1814         struct mlx5e_cq_param cq_param;
1815         struct mlx5e_rq_param rq_param;
1816         struct mlx5e_rq *rq = &priv->drop_rq;
1817         struct mlx5e_cq *cq = &priv->drop_rq.cq;
1818         int err;
1819
1820         memset(&cq_param, 0, sizeof(cq_param));
1821         memset(&rq_param, 0, sizeof(rq_param));
1822         mlx5e_build_drop_rq_param(&rq_param);
1823
1824         err = mlx5e_create_drop_cq(priv, cq, &cq_param);
1825         if (err)
1826                 return err;
1827
1828         err = mlx5e_enable_cq(cq, &cq_param);
1829         if (err)
1830                 goto err_destroy_cq;
1831
1832         err = mlx5e_create_drop_rq(priv, rq, &rq_param);
1833         if (err)
1834                 goto err_disable_cq;
1835
1836         err = mlx5e_enable_rq(rq, &rq_param);
1837         if (err)
1838                 goto err_destroy_rq;
1839
1840         return 0;
1841
1842 err_destroy_rq:
1843         mlx5e_destroy_rq(&priv->drop_rq);
1844
1845 err_disable_cq:
1846         mlx5e_disable_cq(&priv->drop_rq.cq);
1847
1848 err_destroy_cq:
1849         mlx5e_destroy_cq(&priv->drop_rq.cq);
1850
1851         return err;
1852 }
1853
1854 static void mlx5e_close_drop_rq(struct mlx5e_priv *priv)
1855 {
1856         mlx5e_disable_rq(&priv->drop_rq);
1857         mlx5e_destroy_rq(&priv->drop_rq);
1858         mlx5e_disable_cq(&priv->drop_rq.cq);
1859         mlx5e_destroy_cq(&priv->drop_rq.cq);
1860 }
1861
1862 static int mlx5e_create_tis(struct mlx5e_priv *priv, int tc)
1863 {
1864         struct mlx5_core_dev *mdev = priv->mdev;
1865         u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1866         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1867
1868         memset(in, 0, sizeof(in));
1869
1870         MLX5_SET(tisc, tisc, prio, tc << 1);
1871         MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
1872
1873         return mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]);
1874 }
1875
1876 static void mlx5e_destroy_tis(struct mlx5e_priv *priv, int tc)
1877 {
1878         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
1879 }
1880
1881 static int mlx5e_create_tises(struct mlx5e_priv *priv)
1882 {
1883         int err;
1884         int tc;
1885
1886         for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++) {
1887                 err = mlx5e_create_tis(priv, tc);
1888                 if (err)
1889                         goto err_close_tises;
1890         }
1891
1892         return 0;
1893
1894 err_close_tises:
1895         for (tc--; tc >= 0; tc--)
1896                 mlx5e_destroy_tis(priv, tc);
1897
1898         return err;
1899 }
1900
1901 static void mlx5e_destroy_tises(struct mlx5e_priv *priv)
1902 {
1903         int tc;
1904
1905         for (tc = 0; tc < MLX5E_MAX_NUM_TC; tc++)
1906                 mlx5e_destroy_tis(priv, tc);
1907 }
1908
1909 static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
1910                                       enum mlx5e_traffic_types tt)
1911 {
1912         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1913
1914         MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
1915
1916 #define MLX5_HASH_IP            (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1917                                  MLX5_HASH_FIELD_SEL_DST_IP)
1918
1919 #define MLX5_HASH_IP_L4PORTS    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1920                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
1921                                  MLX5_HASH_FIELD_SEL_L4_SPORT |\
1922                                  MLX5_HASH_FIELD_SEL_L4_DPORT)
1923
1924 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1925                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
1926                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
1927
1928         mlx5e_build_tir_ctx_lro(tirc, priv);
1929
1930         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
1931         MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqtn);
1932         mlx5e_build_tir_ctx_hash(tirc, priv);
1933
1934         switch (tt) {
1935         case MLX5E_TT_IPV4_TCP:
1936                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1937                          MLX5_L3_PROT_TYPE_IPV4);
1938                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1939                          MLX5_L4_PROT_TYPE_TCP);
1940                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1941                          MLX5_HASH_IP_L4PORTS);
1942                 break;
1943
1944         case MLX5E_TT_IPV6_TCP:
1945                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1946                          MLX5_L3_PROT_TYPE_IPV6);
1947                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1948                          MLX5_L4_PROT_TYPE_TCP);
1949                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1950                          MLX5_HASH_IP_L4PORTS);
1951                 break;
1952
1953         case MLX5E_TT_IPV4_UDP:
1954                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1955                          MLX5_L3_PROT_TYPE_IPV4);
1956                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1957                          MLX5_L4_PROT_TYPE_UDP);
1958                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1959                          MLX5_HASH_IP_L4PORTS);
1960                 break;
1961
1962         case MLX5E_TT_IPV6_UDP:
1963                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1964                          MLX5_L3_PROT_TYPE_IPV6);
1965                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1966                          MLX5_L4_PROT_TYPE_UDP);
1967                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1968                          MLX5_HASH_IP_L4PORTS);
1969                 break;
1970
1971         case MLX5E_TT_IPV4_IPSEC_AH:
1972                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1973                          MLX5_L3_PROT_TYPE_IPV4);
1974                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1975                          MLX5_HASH_IP_IPSEC_SPI);
1976                 break;
1977
1978         case MLX5E_TT_IPV6_IPSEC_AH:
1979                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1980                          MLX5_L3_PROT_TYPE_IPV6);
1981                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1982                          MLX5_HASH_IP_IPSEC_SPI);
1983                 break;
1984
1985         case MLX5E_TT_IPV4_IPSEC_ESP:
1986                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1987                          MLX5_L3_PROT_TYPE_IPV4);
1988                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1989                          MLX5_HASH_IP_IPSEC_SPI);
1990                 break;
1991
1992         case MLX5E_TT_IPV6_IPSEC_ESP:
1993                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1994                          MLX5_L3_PROT_TYPE_IPV6);
1995                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
1996                          MLX5_HASH_IP_IPSEC_SPI);
1997                 break;
1998
1999         case MLX5E_TT_IPV4:
2000                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2001                          MLX5_L3_PROT_TYPE_IPV4);
2002                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2003                          MLX5_HASH_IP);
2004                 break;
2005
2006         case MLX5E_TT_IPV6:
2007                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2008                          MLX5_L3_PROT_TYPE_IPV6);
2009                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2010                          MLX5_HASH_IP);
2011                 break;
2012         default:
2013                 WARN_ONCE(true,
2014                           "mlx5e_build_indir_tir_ctx: bad traffic type!\n");
2015         }
2016 }
2017
2018 static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 *tirc,
2019                                        u32 rqtn)
2020 {
2021         MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
2022
2023         mlx5e_build_tir_ctx_lro(tirc, priv);
2024
2025         MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2026         MLX5_SET(tirc, tirc, indirect_table, rqtn);
2027         MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2028 }
2029
2030 static int mlx5e_create_tirs(struct mlx5e_priv *priv)
2031 {
2032         int nch = mlx5e_get_max_num_channels(priv->mdev);
2033         void *tirc;
2034         int inlen;
2035         u32 *tirn;
2036         int err;
2037         u32 *in;
2038         int ix;
2039         int tt;
2040
2041         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2042         in = mlx5_vzalloc(inlen);
2043         if (!in)
2044                 return -ENOMEM;
2045
2046         /* indirect tirs */
2047         for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2048                 memset(in, 0, inlen);
2049                 tirn = &priv->indir_tirn[tt];
2050                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2051                 mlx5e_build_indir_tir_ctx(priv, tirc, tt);
2052                 err = mlx5_core_create_tir(priv->mdev, in, inlen, tirn);
2053                 if (err)
2054                         goto err_destroy_tirs;
2055         }
2056
2057         /* direct tirs */
2058         for (ix = 0; ix < nch; ix++) {
2059                 memset(in, 0, inlen);
2060                 tirn = &priv->direct_tir[ix].tirn;
2061                 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2062                 mlx5e_build_direct_tir_ctx(priv, tirc,
2063                                            priv->direct_tir[ix].rqtn);
2064                 err = mlx5_core_create_tir(priv->mdev, in, inlen, tirn);
2065                 if (err)
2066                         goto err_destroy_ch_tirs;
2067         }
2068
2069         kvfree(in);
2070
2071         return 0;
2072
2073 err_destroy_ch_tirs:
2074         for (ix--; ix >= 0; ix--)
2075                 mlx5_core_destroy_tir(priv->mdev, priv->direct_tir[ix].tirn);
2076
2077 err_destroy_tirs:
2078         for (tt--; tt >= 0; tt--)
2079                 mlx5_core_destroy_tir(priv->mdev, priv->indir_tirn[tt]);
2080
2081         kvfree(in);
2082
2083         return err;
2084 }
2085
2086 static void mlx5e_destroy_tirs(struct mlx5e_priv *priv)
2087 {
2088         int nch = mlx5e_get_max_num_channels(priv->mdev);
2089         int i;
2090
2091         for (i = 0; i < nch; i++)
2092                 mlx5_core_destroy_tir(priv->mdev, priv->direct_tir[i].tirn);
2093
2094         for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
2095                 mlx5_core_destroy_tir(priv->mdev, priv->indir_tirn[i]);
2096 }
2097
2098 int mlx5e_modify_rqs_vsd(struct mlx5e_priv *priv, bool vsd)
2099 {
2100         int err = 0;
2101         int i;
2102
2103         if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2104                 return 0;
2105
2106         for (i = 0; i < priv->params.num_channels; i++) {
2107                 err = mlx5e_modify_rq_vsd(&priv->channel[i]->rq, vsd);
2108                 if (err)
2109                         return err;
2110         }
2111
2112         return 0;
2113 }
2114
2115 static int mlx5e_setup_tc(struct net_device *netdev, u8 tc)
2116 {
2117         struct mlx5e_priv *priv = netdev_priv(netdev);
2118         bool was_opened;
2119         int err = 0;
2120
2121         if (tc && tc != MLX5E_MAX_NUM_TC)
2122                 return -EINVAL;
2123
2124         mutex_lock(&priv->state_lock);
2125
2126         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2127         if (was_opened)
2128                 mlx5e_close_locked(priv->netdev);
2129
2130         priv->params.num_tc = tc ? tc : 1;
2131
2132         if (was_opened)
2133                 err = mlx5e_open_locked(priv->netdev);
2134
2135         mutex_unlock(&priv->state_lock);
2136
2137         return err;
2138 }
2139
2140 static int mlx5e_ndo_setup_tc(struct net_device *dev, u32 handle,
2141                               __be16 proto, struct tc_to_netdev *tc)
2142 {
2143         struct mlx5e_priv *priv = netdev_priv(dev);
2144
2145         if (TC_H_MAJ(handle) != TC_H_MAJ(TC_H_INGRESS))
2146                 goto mqprio;
2147
2148         switch (tc->type) {
2149         case TC_SETUP_CLSFLOWER:
2150                 switch (tc->cls_flower->command) {
2151                 case TC_CLSFLOWER_REPLACE:
2152                         return mlx5e_configure_flower(priv, proto, tc->cls_flower);
2153                 case TC_CLSFLOWER_DESTROY:
2154                         return mlx5e_delete_flower(priv, tc->cls_flower);
2155                 }
2156         default:
2157                 return -EOPNOTSUPP;
2158         }
2159
2160 mqprio:
2161         if (tc->type != TC_SETUP_MQPRIO)
2162                 return -EINVAL;
2163
2164         return mlx5e_setup_tc(dev, tc->tc);
2165 }
2166
2167 static struct rtnl_link_stats64 *
2168 mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
2169 {
2170         struct mlx5e_priv *priv = netdev_priv(dev);
2171         struct mlx5e_sw_stats *sstats = &priv->stats.sw;
2172         struct mlx5e_vport_stats *vstats = &priv->stats.vport;
2173         struct mlx5e_pport_stats *pstats = &priv->stats.pport;
2174
2175         stats->rx_packets = sstats->rx_packets;
2176         stats->rx_bytes   = sstats->rx_bytes;
2177         stats->tx_packets = sstats->tx_packets;
2178         stats->tx_bytes   = sstats->tx_bytes;
2179
2180         stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
2181         stats->tx_dropped = sstats->tx_queue_dropped;
2182
2183         stats->rx_length_errors =
2184                 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
2185                 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
2186                 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
2187         stats->rx_crc_errors =
2188                 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
2189         stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
2190         stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
2191         stats->tx_carrier_errors =
2192                 PPORT_802_3_GET(pstats, a_symbol_error_during_carrier);
2193         stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
2194                            stats->rx_frame_errors;
2195         stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
2196
2197         /* vport multicast also counts packets that are dropped due to steering
2198          * or rx out of buffer
2199          */
2200         stats->multicast =
2201                 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
2202
2203         return stats;
2204 }
2205
2206 static void mlx5e_set_rx_mode(struct net_device *dev)
2207 {
2208         struct mlx5e_priv *priv = netdev_priv(dev);
2209
2210         queue_work(priv->wq, &priv->set_rx_mode_work);
2211 }
2212
2213 static int mlx5e_set_mac(struct net_device *netdev, void *addr)
2214 {
2215         struct mlx5e_priv *priv = netdev_priv(netdev);
2216         struct sockaddr *saddr = addr;
2217
2218         if (!is_valid_ether_addr(saddr->sa_data))
2219                 return -EADDRNOTAVAIL;
2220
2221         netif_addr_lock_bh(netdev);
2222         ether_addr_copy(netdev->dev_addr, saddr->sa_data);
2223         netif_addr_unlock_bh(netdev);
2224
2225         queue_work(priv->wq, &priv->set_rx_mode_work);
2226
2227         return 0;
2228 }
2229
2230 #define MLX5E_SET_FEATURE(netdev, feature, enable)      \
2231         do {                                            \
2232                 if (enable)                             \
2233                         netdev->features |= feature;    \
2234                 else                                    \
2235                         netdev->features &= ~feature;   \
2236         } while (0)
2237
2238 typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
2239
2240 static int set_feature_lro(struct net_device *netdev, bool enable)
2241 {
2242         struct mlx5e_priv *priv = netdev_priv(netdev);
2243         bool was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2244         int err;
2245
2246         mutex_lock(&priv->state_lock);
2247
2248         if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2249                 mlx5e_close_locked(priv->netdev);
2250
2251         priv->params.lro_en = enable;
2252         err = mlx5e_modify_tirs_lro(priv);
2253         if (err) {
2254                 netdev_err(netdev, "lro modify failed, %d\n", err);
2255                 priv->params.lro_en = !enable;
2256         }
2257
2258         if (was_opened && (priv->params.rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST))
2259                 mlx5e_open_locked(priv->netdev);
2260
2261         mutex_unlock(&priv->state_lock);
2262
2263         return err;
2264 }
2265
2266 static int set_feature_vlan_filter(struct net_device *netdev, bool enable)
2267 {
2268         struct mlx5e_priv *priv = netdev_priv(netdev);
2269
2270         if (enable)
2271                 mlx5e_enable_vlan_filter(priv);
2272         else
2273                 mlx5e_disable_vlan_filter(priv);
2274
2275         return 0;
2276 }
2277
2278 static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
2279 {
2280         struct mlx5e_priv *priv = netdev_priv(netdev);
2281
2282         if (!enable && mlx5e_tc_num_filters(priv)) {
2283                 netdev_err(netdev,
2284                            "Active offloaded tc filters, can't turn hw_tc_offload off\n");
2285                 return -EINVAL;
2286         }
2287
2288         return 0;
2289 }
2290
2291 static int set_feature_rx_all(struct net_device *netdev, bool enable)
2292 {
2293         struct mlx5e_priv *priv = netdev_priv(netdev);
2294         struct mlx5_core_dev *mdev = priv->mdev;
2295
2296         return mlx5_set_port_fcs(mdev, !enable);
2297 }
2298
2299 static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
2300 {
2301         struct mlx5e_priv *priv = netdev_priv(netdev);
2302         int err;
2303
2304         mutex_lock(&priv->state_lock);
2305
2306         priv->params.vlan_strip_disable = !enable;
2307         err = mlx5e_modify_rqs_vsd(priv, !enable);
2308         if (err)
2309                 priv->params.vlan_strip_disable = enable;
2310
2311         mutex_unlock(&priv->state_lock);
2312
2313         return err;
2314 }
2315
2316 #ifdef CONFIG_RFS_ACCEL
2317 static int set_feature_arfs(struct net_device *netdev, bool enable)
2318 {
2319         struct mlx5e_priv *priv = netdev_priv(netdev);
2320         int err;
2321
2322         if (enable)
2323                 err = mlx5e_arfs_enable(priv);
2324         else
2325                 err = mlx5e_arfs_disable(priv);
2326
2327         return err;
2328 }
2329 #endif
2330
2331 static int mlx5e_handle_feature(struct net_device *netdev,
2332                                 netdev_features_t wanted_features,
2333                                 netdev_features_t feature,
2334                                 mlx5e_feature_handler feature_handler)
2335 {
2336         netdev_features_t changes = wanted_features ^ netdev->features;
2337         bool enable = !!(wanted_features & feature);
2338         int err;
2339
2340         if (!(changes & feature))
2341                 return 0;
2342
2343         err = feature_handler(netdev, enable);
2344         if (err) {
2345                 netdev_err(netdev, "%s feature 0x%llx failed err %d\n",
2346                            enable ? "Enable" : "Disable", feature, err);
2347                 return err;
2348         }
2349
2350         MLX5E_SET_FEATURE(netdev, feature, enable);
2351         return 0;
2352 }
2353
2354 static int mlx5e_set_features(struct net_device *netdev,
2355                               netdev_features_t features)
2356 {
2357         int err;
2358
2359         err  = mlx5e_handle_feature(netdev, features, NETIF_F_LRO,
2360                                     set_feature_lro);
2361         err |= mlx5e_handle_feature(netdev, features,
2362                                     NETIF_F_HW_VLAN_CTAG_FILTER,
2363                                     set_feature_vlan_filter);
2364         err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_TC,
2365                                     set_feature_tc_num_filters);
2366         err |= mlx5e_handle_feature(netdev, features, NETIF_F_RXALL,
2367                                     set_feature_rx_all);
2368         err |= mlx5e_handle_feature(netdev, features, NETIF_F_HW_VLAN_CTAG_RX,
2369                                     set_feature_rx_vlan);
2370 #ifdef CONFIG_RFS_ACCEL
2371         err |= mlx5e_handle_feature(netdev, features, NETIF_F_NTUPLE,
2372                                     set_feature_arfs);
2373 #endif
2374
2375         return err ? -EINVAL : 0;
2376 }
2377
2378 #define MXL5_HW_MIN_MTU 64
2379 #define MXL5E_MIN_MTU (MXL5_HW_MIN_MTU + ETH_FCS_LEN)
2380
2381 static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
2382 {
2383         struct mlx5e_priv *priv = netdev_priv(netdev);
2384         struct mlx5_core_dev *mdev = priv->mdev;
2385         bool was_opened;
2386         u16 max_mtu;
2387         u16 min_mtu;
2388         int err = 0;
2389
2390         mlx5_query_port_max_mtu(mdev, &max_mtu, 1);
2391
2392         max_mtu = MLX5E_HW2SW_MTU(max_mtu);
2393         min_mtu = MLX5E_HW2SW_MTU(MXL5E_MIN_MTU);
2394
2395         if (new_mtu > max_mtu || new_mtu < min_mtu) {
2396                 netdev_err(netdev,
2397                            "%s: Bad MTU (%d), valid range is: [%d..%d]\n",
2398                            __func__, new_mtu, min_mtu, max_mtu);
2399                 return -EINVAL;
2400         }
2401
2402         mutex_lock(&priv->state_lock);
2403
2404         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2405         if (was_opened)
2406                 mlx5e_close_locked(netdev);
2407
2408         netdev->mtu = new_mtu;
2409
2410         if (was_opened)
2411                 err = mlx5e_open_locked(netdev);
2412
2413         mutex_unlock(&priv->state_lock);
2414
2415         return err;
2416 }
2417
2418 static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2419 {
2420         switch (cmd) {
2421         case SIOCSHWTSTAMP:
2422                 return mlx5e_hwstamp_set(dev, ifr);
2423         case SIOCGHWTSTAMP:
2424                 return mlx5e_hwstamp_get(dev, ifr);
2425         default:
2426                 return -EOPNOTSUPP;
2427         }
2428 }
2429
2430 static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
2431 {
2432         struct mlx5e_priv *priv = netdev_priv(dev);
2433         struct mlx5_core_dev *mdev = priv->mdev;
2434
2435         return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
2436 }
2437
2438 static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos)
2439 {
2440         struct mlx5e_priv *priv = netdev_priv(dev);
2441         struct mlx5_core_dev *mdev = priv->mdev;
2442
2443         return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
2444                                            vlan, qos);
2445 }
2446
2447 static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
2448 {
2449         struct mlx5e_priv *priv = netdev_priv(dev);
2450         struct mlx5_core_dev *mdev = priv->mdev;
2451
2452         return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
2453 }
2454
2455 static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
2456 {
2457         struct mlx5e_priv *priv = netdev_priv(dev);
2458         struct mlx5_core_dev *mdev = priv->mdev;
2459
2460         return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
2461 }
2462 static int mlx5_vport_link2ifla(u8 esw_link)
2463 {
2464         switch (esw_link) {
2465         case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
2466                 return IFLA_VF_LINK_STATE_DISABLE;
2467         case MLX5_ESW_VPORT_ADMIN_STATE_UP:
2468                 return IFLA_VF_LINK_STATE_ENABLE;
2469         }
2470         return IFLA_VF_LINK_STATE_AUTO;
2471 }
2472
2473 static int mlx5_ifla_link2vport(u8 ifla_link)
2474 {
2475         switch (ifla_link) {
2476         case IFLA_VF_LINK_STATE_DISABLE:
2477                 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
2478         case IFLA_VF_LINK_STATE_ENABLE:
2479                 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
2480         }
2481         return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
2482 }
2483
2484 static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
2485                                    int link_state)
2486 {
2487         struct mlx5e_priv *priv = netdev_priv(dev);
2488         struct mlx5_core_dev *mdev = priv->mdev;
2489
2490         return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
2491                                             mlx5_ifla_link2vport(link_state));
2492 }
2493
2494 static int mlx5e_get_vf_config(struct net_device *dev,
2495                                int vf, struct ifla_vf_info *ivi)
2496 {
2497         struct mlx5e_priv *priv = netdev_priv(dev);
2498         struct mlx5_core_dev *mdev = priv->mdev;
2499         int err;
2500
2501         err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
2502         if (err)
2503                 return err;
2504         ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
2505         return 0;
2506 }
2507
2508 static int mlx5e_get_vf_stats(struct net_device *dev,
2509                               int vf, struct ifla_vf_stats *vf_stats)
2510 {
2511         struct mlx5e_priv *priv = netdev_priv(dev);
2512         struct mlx5_core_dev *mdev = priv->mdev;
2513
2514         return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
2515                                             vf_stats);
2516 }
2517
2518 static void mlx5e_add_vxlan_port(struct net_device *netdev,
2519                                  sa_family_t sa_family, __be16 port)
2520 {
2521         struct mlx5e_priv *priv = netdev_priv(netdev);
2522
2523         if (!mlx5e_vxlan_allowed(priv->mdev))
2524                 return;
2525
2526         mlx5e_vxlan_queue_work(priv, sa_family, be16_to_cpu(port), 1);
2527 }
2528
2529 static void mlx5e_del_vxlan_port(struct net_device *netdev,
2530                                  sa_family_t sa_family, __be16 port)
2531 {
2532         struct mlx5e_priv *priv = netdev_priv(netdev);
2533
2534         if (!mlx5e_vxlan_allowed(priv->mdev))
2535                 return;
2536
2537         mlx5e_vxlan_queue_work(priv, sa_family, be16_to_cpu(port), 0);
2538 }
2539
2540 static netdev_features_t mlx5e_vxlan_features_check(struct mlx5e_priv *priv,
2541                                                     struct sk_buff *skb,
2542                                                     netdev_features_t features)
2543 {
2544         struct udphdr *udph;
2545         u16 proto;
2546         u16 port = 0;
2547
2548         switch (vlan_get_protocol(skb)) {
2549         case htons(ETH_P_IP):
2550                 proto = ip_hdr(skb)->protocol;
2551                 break;
2552         case htons(ETH_P_IPV6):
2553                 proto = ipv6_hdr(skb)->nexthdr;
2554                 break;
2555         default:
2556                 goto out;
2557         }
2558
2559         if (proto == IPPROTO_UDP) {
2560                 udph = udp_hdr(skb);
2561                 port = be16_to_cpu(udph->dest);
2562         }
2563
2564         /* Verify if UDP port is being offloaded by HW */
2565         if (port && mlx5e_vxlan_lookup_port(priv, port))
2566                 return features;
2567
2568 out:
2569         /* Disable CSUM and GSO if the udp dport is not offloaded by HW */
2570         return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2571 }
2572
2573 static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
2574                                               struct net_device *netdev,
2575                                               netdev_features_t features)
2576 {
2577         struct mlx5e_priv *priv = netdev_priv(netdev);
2578
2579         features = vlan_features_check(skb, features);
2580         features = vxlan_features_check(skb, features);
2581
2582         /* Validate if the tunneled packet is being offloaded by HW */
2583         if (skb->encapsulation &&
2584             (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
2585                 return mlx5e_vxlan_features_check(priv, skb, features);
2586
2587         return features;
2588 }
2589
2590 static const struct net_device_ops mlx5e_netdev_ops_basic = {
2591         .ndo_open                = mlx5e_open,
2592         .ndo_stop                = mlx5e_close,
2593         .ndo_start_xmit          = mlx5e_xmit,
2594         .ndo_setup_tc            = mlx5e_ndo_setup_tc,
2595         .ndo_select_queue        = mlx5e_select_queue,
2596         .ndo_get_stats64         = mlx5e_get_stats,
2597         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
2598         .ndo_set_mac_address     = mlx5e_set_mac,
2599         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
2600         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
2601         .ndo_set_features        = mlx5e_set_features,
2602         .ndo_change_mtu          = mlx5e_change_mtu,
2603         .ndo_do_ioctl            = mlx5e_ioctl,
2604 #ifdef CONFIG_RFS_ACCEL
2605         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
2606 #endif
2607 };
2608
2609 static const struct net_device_ops mlx5e_netdev_ops_sriov = {
2610         .ndo_open                = mlx5e_open,
2611         .ndo_stop                = mlx5e_close,
2612         .ndo_start_xmit          = mlx5e_xmit,
2613         .ndo_setup_tc            = mlx5e_ndo_setup_tc,
2614         .ndo_select_queue        = mlx5e_select_queue,
2615         .ndo_get_stats64         = mlx5e_get_stats,
2616         .ndo_set_rx_mode         = mlx5e_set_rx_mode,
2617         .ndo_set_mac_address     = mlx5e_set_mac,
2618         .ndo_vlan_rx_add_vid     = mlx5e_vlan_rx_add_vid,
2619         .ndo_vlan_rx_kill_vid    = mlx5e_vlan_rx_kill_vid,
2620         .ndo_set_features        = mlx5e_set_features,
2621         .ndo_change_mtu          = mlx5e_change_mtu,
2622         .ndo_do_ioctl            = mlx5e_ioctl,
2623         .ndo_add_vxlan_port      = mlx5e_add_vxlan_port,
2624         .ndo_del_vxlan_port      = mlx5e_del_vxlan_port,
2625         .ndo_features_check      = mlx5e_features_check,
2626 #ifdef CONFIG_RFS_ACCEL
2627         .ndo_rx_flow_steer       = mlx5e_rx_flow_steer,
2628 #endif
2629         .ndo_set_vf_mac          = mlx5e_set_vf_mac,
2630         .ndo_set_vf_vlan         = mlx5e_set_vf_vlan,
2631         .ndo_set_vf_spoofchk     = mlx5e_set_vf_spoofchk,
2632         .ndo_set_vf_trust        = mlx5e_set_vf_trust,
2633         .ndo_get_vf_config       = mlx5e_get_vf_config,
2634         .ndo_set_vf_link_state   = mlx5e_set_vf_link_state,
2635         .ndo_get_vf_stats        = mlx5e_get_vf_stats,
2636 };
2637
2638 static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2639 {
2640         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2641                 return -ENOTSUPP;
2642         if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
2643             !MLX5_CAP_GEN(mdev, nic_flow_table) ||
2644             !MLX5_CAP_ETH(mdev, csum_cap) ||
2645             !MLX5_CAP_ETH(mdev, max_lso_cap) ||
2646             !MLX5_CAP_ETH(mdev, vlan_cap) ||
2647             !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
2648             MLX5_CAP_FLOWTABLE(mdev,
2649                                flow_table_properties_nic_receive.max_ft_level)
2650                                < 3) {
2651                 mlx5_core_warn(mdev,
2652                                "Not creating net device, some required device capabilities are missing\n");
2653                 return -ENOTSUPP;
2654         }
2655         if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
2656                 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
2657         if (!MLX5_CAP_GEN(mdev, cq_moderation))
2658                 mlx5_core_warn(mdev, "CQ modiration is not supported\n");
2659
2660         return 0;
2661 }
2662
2663 u16 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
2664 {
2665         int bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
2666
2667         return bf_buf_size -
2668                sizeof(struct mlx5e_tx_wqe) +
2669                2 /*sizeof(mlx5e_tx_wqe.inline_hdr_start)*/;
2670 }
2671
2672 #ifdef CONFIG_MLX5_CORE_EN_DCB
2673 static void mlx5e_ets_init(struct mlx5e_priv *priv)
2674 {
2675         int i;
2676
2677         priv->params.ets.ets_cap = mlx5_max_tc(priv->mdev) + 1;
2678         for (i = 0; i < priv->params.ets.ets_cap; i++) {
2679                 priv->params.ets.tc_tx_bw[i] = MLX5E_MAX_BW_ALLOC;
2680                 priv->params.ets.tc_tsa[i] = IEEE_8021QAZ_TSA_VENDOR;
2681                 priv->params.ets.prio_tc[i] = i;
2682         }
2683
2684         /* tclass[prio=0]=1, tclass[prio=1]=0, tclass[prio=i]=i (for i>1) */
2685         priv->params.ets.prio_tc[0] = 1;
2686         priv->params.ets.prio_tc[1] = 0;
2687 }
2688 #endif
2689
2690 void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev,
2691                                    u32 *indirection_rqt, int len,
2692                                    int num_channels)
2693 {
2694         int node = mdev->priv.numa_node;
2695         int node_num_of_cores;
2696         int i;
2697
2698         if (node == -1)
2699                 node = first_online_node;
2700
2701         node_num_of_cores = cpumask_weight(cpumask_of_node(node));
2702
2703         if (node_num_of_cores)
2704                 num_channels = min_t(int, num_channels, node_num_of_cores);
2705
2706         for (i = 0; i < len; i++)
2707                 indirection_rqt[i] = i % num_channels;
2708 }
2709
2710 static bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
2711 {
2712         return MLX5_CAP_GEN(mdev, striding_rq) &&
2713                 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
2714                 MLX5_CAP_ETH(mdev, reg_umr_sq);
2715 }
2716
2717 static void mlx5e_build_netdev_priv(struct mlx5_core_dev *mdev,
2718                                     struct net_device *netdev,
2719                                     int num_channels)
2720 {
2721         struct mlx5e_priv *priv = netdev_priv(netdev);
2722
2723         priv->params.log_sq_size           =
2724                 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
2725         priv->params.rq_wq_type = mlx5e_check_fragmented_striding_rq_cap(mdev) ?
2726                 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
2727                 MLX5_WQ_TYPE_LINKED_LIST;
2728
2729         switch (priv->params.rq_wq_type) {
2730         case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
2731                 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE_MPW;
2732                 priv->params.lro_en = true;
2733                 break;
2734         default: /* MLX5_WQ_TYPE_LINKED_LIST */
2735                 priv->params.log_rq_size = MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
2736         }
2737
2738         priv->params.min_rx_wqes = mlx5_min_rx_wqes(priv->params.rq_wq_type,
2739                                             BIT(priv->params.log_rq_size));
2740         priv->params.rx_cq_moderation_usec =
2741                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
2742         priv->params.rx_cq_moderation_pkts =
2743                 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
2744         priv->params.tx_cq_moderation_usec =
2745                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
2746         priv->params.tx_cq_moderation_pkts =
2747                 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
2748         priv->params.tx_max_inline         = mlx5e_get_max_inline_cap(mdev);
2749         priv->params.num_tc                = 1;
2750         priv->params.rss_hfunc             = ETH_RSS_HASH_XOR;
2751
2752         netdev_rss_key_fill(priv->params.toeplitz_hash_key,
2753                             sizeof(priv->params.toeplitz_hash_key));
2754
2755         mlx5e_build_default_indir_rqt(mdev, priv->params.indirection_rqt,
2756                                       MLX5E_INDIR_RQT_SIZE, num_channels);
2757
2758         priv->params.lro_wqe_sz            =
2759                 MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
2760
2761         priv->mdev                         = mdev;
2762         priv->netdev                       = netdev;
2763         priv->params.num_channels          = num_channels;
2764
2765 #ifdef CONFIG_MLX5_CORE_EN_DCB
2766         mlx5e_ets_init(priv);
2767 #endif
2768
2769         mutex_init(&priv->state_lock);
2770
2771         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
2772         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
2773         INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
2774 }
2775
2776 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
2777 {
2778         struct mlx5e_priv *priv = netdev_priv(netdev);
2779
2780         mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
2781         if (is_zero_ether_addr(netdev->dev_addr) &&
2782             !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
2783                 eth_hw_addr_random(netdev);
2784                 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
2785         }
2786 }
2787
2788 static void mlx5e_build_netdev(struct net_device *netdev)
2789 {
2790         struct mlx5e_priv *priv = netdev_priv(netdev);
2791         struct mlx5_core_dev *mdev = priv->mdev;
2792         bool fcs_supported;
2793         bool fcs_enabled;
2794
2795         SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
2796
2797         if (MLX5_CAP_GEN(mdev, vport_group_manager)) {
2798                 netdev->netdev_ops = &mlx5e_netdev_ops_sriov;
2799 #ifdef CONFIG_MLX5_CORE_EN_DCB
2800                 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
2801 #endif
2802         } else {
2803                 netdev->netdev_ops = &mlx5e_netdev_ops_basic;
2804         }
2805
2806         netdev->watchdog_timeo    = 15 * HZ;
2807
2808         netdev->ethtool_ops       = &mlx5e_ethtool_ops;
2809
2810         netdev->vlan_features    |= NETIF_F_SG;
2811         netdev->vlan_features    |= NETIF_F_IP_CSUM;
2812         netdev->vlan_features    |= NETIF_F_IPV6_CSUM;
2813         netdev->vlan_features    |= NETIF_F_GRO;
2814         netdev->vlan_features    |= NETIF_F_TSO;
2815         netdev->vlan_features    |= NETIF_F_TSO6;
2816         netdev->vlan_features    |= NETIF_F_RXCSUM;
2817         netdev->vlan_features    |= NETIF_F_RXHASH;
2818
2819         if (!!MLX5_CAP_ETH(mdev, lro_cap))
2820                 netdev->vlan_features    |= NETIF_F_LRO;
2821
2822         netdev->hw_features       = netdev->vlan_features;
2823         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_TX;
2824         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_RX;
2825         netdev->hw_features      |= NETIF_F_HW_VLAN_CTAG_FILTER;
2826
2827         if (mlx5e_vxlan_allowed(mdev)) {
2828                 netdev->hw_features     |= NETIF_F_GSO_UDP_TUNNEL |
2829                                            NETIF_F_GSO_UDP_TUNNEL_CSUM |
2830                                            NETIF_F_GSO_PARTIAL;
2831                 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
2832                 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
2833                 netdev->hw_enc_features |= NETIF_F_TSO;
2834                 netdev->hw_enc_features |= NETIF_F_TSO6;
2835                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
2836                 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM |
2837                                            NETIF_F_GSO_PARTIAL;
2838                 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
2839         }
2840
2841         mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
2842
2843         if (fcs_supported)
2844                 netdev->hw_features |= NETIF_F_RXALL;
2845
2846         netdev->features          = netdev->hw_features;
2847         if (!priv->params.lro_en)
2848                 netdev->features  &= ~NETIF_F_LRO;
2849
2850         if (fcs_enabled)
2851                 netdev->features  &= ~NETIF_F_RXALL;
2852
2853 #define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
2854         if (FT_CAP(flow_modify_en) &&
2855             FT_CAP(modify_root) &&
2856             FT_CAP(identified_miss_table_mode) &&
2857             FT_CAP(flow_table_modify)) {
2858                 netdev->hw_features      |= NETIF_F_HW_TC;
2859 #ifdef CONFIG_RFS_ACCEL
2860                 netdev->hw_features      |= NETIF_F_NTUPLE;
2861 #endif
2862         }
2863
2864         netdev->features         |= NETIF_F_HIGHDMA;
2865
2866         netdev->priv_flags       |= IFF_UNICAST_FLT;
2867
2868         mlx5e_set_netdev_dev_addr(netdev);
2869 }
2870
2871 static int mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
2872                              struct mlx5_core_mkey *mkey)
2873 {
2874         struct mlx5_core_dev *mdev = priv->mdev;
2875         struct mlx5_create_mkey_mbox_in *in;
2876         int err;
2877
2878         in = mlx5_vzalloc(sizeof(*in));
2879         if (!in)
2880                 return -ENOMEM;
2881
2882         in->seg.flags = MLX5_PERM_LOCAL_WRITE |
2883                         MLX5_PERM_LOCAL_READ  |
2884                         MLX5_ACCESS_MODE_PA;
2885         in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
2886         in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
2887
2888         err = mlx5_core_create_mkey(mdev, mkey, in, sizeof(*in), NULL, NULL,
2889                                     NULL);
2890
2891         kvfree(in);
2892
2893         return err;
2894 }
2895
2896 static void mlx5e_create_q_counter(struct mlx5e_priv *priv)
2897 {
2898         struct mlx5_core_dev *mdev = priv->mdev;
2899         int err;
2900
2901         err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
2902         if (err) {
2903                 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
2904                 priv->q_counter = 0;
2905         }
2906 }
2907
2908 static void mlx5e_destroy_q_counter(struct mlx5e_priv *priv)
2909 {
2910         if (!priv->q_counter)
2911                 return;
2912
2913         mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
2914 }
2915
2916 static int mlx5e_create_umr_mkey(struct mlx5e_priv *priv)
2917 {
2918         struct mlx5_core_dev *mdev = priv->mdev;
2919         struct mlx5_create_mkey_mbox_in *in;
2920         struct mlx5_mkey_seg *mkc;
2921         int inlen = sizeof(*in);
2922         u64 npages =
2923                 mlx5e_get_max_num_channels(mdev) * MLX5_CHANNEL_MAX_NUM_MTTS;
2924         int err;
2925
2926         in = mlx5_vzalloc(inlen);
2927         if (!in)
2928                 return -ENOMEM;
2929
2930         mkc = &in->seg;
2931         mkc->status = MLX5_MKEY_STATUS_FREE;
2932         mkc->flags = MLX5_PERM_UMR_EN |
2933                      MLX5_PERM_LOCAL_READ |
2934                      MLX5_PERM_LOCAL_WRITE |
2935                      MLX5_ACCESS_MODE_MTT;
2936
2937         mkc->qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
2938         mkc->flags_pd = cpu_to_be32(priv->pdn);
2939         mkc->len = cpu_to_be64(npages << PAGE_SHIFT);
2940         mkc->xlt_oct_size = cpu_to_be32(mlx5e_get_mtt_octw(npages));
2941         mkc->log2_page_size = PAGE_SHIFT;
2942
2943         err = mlx5_core_create_mkey(mdev, &priv->umr_mkey, in, inlen, NULL,
2944                                     NULL, NULL);
2945
2946         kvfree(in);
2947
2948         return err;
2949 }
2950
2951 static void *mlx5e_create_netdev(struct mlx5_core_dev *mdev)
2952 {
2953         struct net_device *netdev;
2954         struct mlx5e_priv *priv;
2955         int nch = mlx5e_get_max_num_channels(mdev);
2956         int err;
2957
2958         if (mlx5e_check_required_hca_cap(mdev))
2959                 return NULL;
2960
2961         netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
2962                                     nch * MLX5E_MAX_NUM_TC,
2963                                     nch);
2964         if (!netdev) {
2965                 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
2966                 return NULL;
2967         }
2968
2969         mlx5e_build_netdev_priv(mdev, netdev, nch);
2970         mlx5e_build_netdev(netdev);
2971
2972         netif_carrier_off(netdev);
2973
2974         priv = netdev_priv(netdev);
2975
2976         priv->wq = create_singlethread_workqueue("mlx5e");
2977         if (!priv->wq)
2978                 goto err_free_netdev;
2979
2980         err = mlx5_alloc_map_uar(mdev, &priv->cq_uar, false);
2981         if (err) {
2982                 mlx5_core_err(mdev, "alloc_map uar failed, %d\n", err);
2983                 goto err_destroy_wq;
2984         }
2985
2986         err = mlx5_core_alloc_pd(mdev, &priv->pdn);
2987         if (err) {
2988                 mlx5_core_err(mdev, "alloc pd failed, %d\n", err);
2989                 goto err_unmap_free_uar;
2990         }
2991
2992         err = mlx5_core_alloc_transport_domain(mdev, &priv->tdn);
2993         if (err) {
2994                 mlx5_core_err(mdev, "alloc td failed, %d\n", err);
2995                 goto err_dealloc_pd;
2996         }
2997
2998         err = mlx5e_create_mkey(priv, priv->pdn, &priv->mkey);
2999         if (err) {
3000                 mlx5_core_err(mdev, "create mkey failed, %d\n", err);
3001                 goto err_dealloc_transport_domain;
3002         }
3003
3004         err = mlx5e_create_umr_mkey(priv);
3005         if (err) {
3006                 mlx5_core_err(mdev, "create umr mkey failed, %d\n", err);
3007                 goto err_destroy_mkey;
3008         }
3009
3010         err = mlx5e_create_tises(priv);
3011         if (err) {
3012                 mlx5_core_warn(mdev, "create tises failed, %d\n", err);
3013                 goto err_destroy_umr_mkey;
3014         }
3015
3016         err = mlx5e_open_drop_rq(priv);
3017         if (err) {
3018                 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
3019                 goto err_destroy_tises;
3020         }
3021
3022         err = mlx5e_create_rqts(priv);
3023         if (err) {
3024                 mlx5_core_warn(mdev, "create rqts failed, %d\n", err);
3025                 goto err_close_drop_rq;
3026         }
3027
3028         err = mlx5e_create_tirs(priv);
3029         if (err) {
3030                 mlx5_core_warn(mdev, "create tirs failed, %d\n", err);
3031                 goto err_destroy_rqts;
3032         }
3033
3034         err = mlx5e_create_flow_steering(priv);
3035         if (err) {
3036                 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
3037                 goto err_destroy_tirs;
3038         }
3039
3040         mlx5e_create_q_counter(priv);
3041
3042         mlx5e_init_l2_addr(priv);
3043
3044         mlx5e_vxlan_init(priv);
3045
3046         err = mlx5e_tc_init(priv);
3047         if (err)
3048                 goto err_dealloc_q_counters;
3049
3050 #ifdef CONFIG_MLX5_CORE_EN_DCB
3051         mlx5e_dcbnl_ieee_setets_core(priv, &priv->params.ets);
3052 #endif
3053
3054         err = register_netdev(netdev);
3055         if (err) {
3056                 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
3057                 goto err_tc_cleanup;
3058         }
3059
3060         if (mlx5e_vxlan_allowed(mdev)) {
3061                 rtnl_lock();
3062                 vxlan_get_rx_port(netdev);
3063                 rtnl_unlock();
3064         }
3065
3066         mlx5e_enable_async_events(priv);
3067         queue_work(priv->wq, &priv->set_rx_mode_work);
3068
3069         return priv;
3070
3071 err_tc_cleanup:
3072         mlx5e_tc_cleanup(priv);
3073
3074 err_dealloc_q_counters:
3075         mlx5e_destroy_q_counter(priv);
3076         mlx5e_destroy_flow_steering(priv);
3077
3078 err_destroy_tirs:
3079         mlx5e_destroy_tirs(priv);
3080
3081 err_destroy_rqts:
3082         mlx5e_destroy_rqts(priv);
3083
3084 err_close_drop_rq:
3085         mlx5e_close_drop_rq(priv);
3086
3087 err_destroy_tises:
3088         mlx5e_destroy_tises(priv);
3089
3090 err_destroy_umr_mkey:
3091         mlx5_core_destroy_mkey(mdev, &priv->umr_mkey);
3092
3093 err_destroy_mkey:
3094         mlx5_core_destroy_mkey(mdev, &priv->mkey);
3095
3096 err_dealloc_transport_domain:
3097         mlx5_core_dealloc_transport_domain(mdev, priv->tdn);
3098
3099 err_dealloc_pd:
3100         mlx5_core_dealloc_pd(mdev, priv->pdn);
3101
3102 err_unmap_free_uar:
3103         mlx5_unmap_free_uar(mdev, &priv->cq_uar);
3104
3105 err_destroy_wq:
3106         destroy_workqueue(priv->wq);
3107
3108 err_free_netdev:
3109         free_netdev(netdev);
3110
3111         return NULL;
3112 }
3113
3114 static void mlx5e_destroy_netdev(struct mlx5_core_dev *mdev, void *vpriv)
3115 {
3116         struct mlx5e_priv *priv = vpriv;
3117         struct net_device *netdev = priv->netdev;
3118
3119         set_bit(MLX5E_STATE_DESTROYING, &priv->state);
3120
3121         queue_work(priv->wq, &priv->set_rx_mode_work);
3122         mlx5e_disable_async_events(priv);
3123         flush_workqueue(priv->wq);
3124         if (test_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &mdev->intf_state)) {
3125                 netif_device_detach(netdev);
3126                 mutex_lock(&priv->state_lock);
3127                 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
3128                         mlx5e_close_locked(netdev);
3129                 mutex_unlock(&priv->state_lock);
3130         } else {
3131                 unregister_netdev(netdev);
3132         }
3133
3134         mlx5e_tc_cleanup(priv);
3135         mlx5e_vxlan_cleanup(priv);
3136         mlx5e_destroy_q_counter(priv);
3137         mlx5e_destroy_flow_steering(priv);
3138         mlx5e_destroy_tirs(priv);
3139         mlx5e_destroy_rqts(priv);
3140         mlx5e_close_drop_rq(priv);
3141         mlx5e_destroy_tises(priv);
3142         mlx5_core_destroy_mkey(priv->mdev, &priv->umr_mkey);
3143         mlx5_core_destroy_mkey(priv->mdev, &priv->mkey);
3144         mlx5_core_dealloc_transport_domain(priv->mdev, priv->tdn);
3145         mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
3146         mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
3147         cancel_delayed_work_sync(&priv->update_stats_work);
3148         destroy_workqueue(priv->wq);
3149
3150         if (!test_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &mdev->intf_state))
3151                 free_netdev(netdev);
3152 }
3153
3154 static void *mlx5e_get_netdev(void *vpriv)
3155 {
3156         struct mlx5e_priv *priv = vpriv;
3157
3158         return priv->netdev;
3159 }
3160
3161 static struct mlx5_interface mlx5e_interface = {
3162         .add       = mlx5e_create_netdev,
3163         .remove    = mlx5e_destroy_netdev,
3164         .event     = mlx5e_async_event,
3165         .protocol  = MLX5_INTERFACE_PROTOCOL_ETH,
3166         .get_dev   = mlx5e_get_netdev,
3167 };
3168
3169 void mlx5e_init(void)
3170 {
3171         mlx5_register_interface(&mlx5e_interface);
3172 }
3173
3174 void mlx5e_cleanup(void)
3175 {
3176         mlx5_unregister_interface(&mlx5e_interface);
3177 }