2 * drivers/net/ethernet/mellanox/mlxsw/reg.h
3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015-2016 Ido Schimmel <idosch@mellanox.com>
5 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
6 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
40 #include <linux/string.h>
41 #include <linux/bitops.h>
42 #include <linux/if_vlan.h>
47 struct mlxsw_reg_info {
52 #define MLXSW_REG(type) (&mlxsw_reg_##type)
53 #define MLXSW_REG_LEN(type) MLXSW_REG(type)->len
54 #define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len)
56 /* SGCR - Switch General Configuration Register
57 * --------------------------------------------
58 * This register is used for configuration of the switch capabilities.
60 #define MLXSW_REG_SGCR_ID 0x2000
61 #define MLXSW_REG_SGCR_LEN 0x10
63 static const struct mlxsw_reg_info mlxsw_reg_sgcr = {
64 .id = MLXSW_REG_SGCR_ID,
65 .len = MLXSW_REG_SGCR_LEN,
69 * Link Local Broadcast (Default=0)
70 * When set, all Link Local packets (224.0.0.X) will be treated as broadcast
71 * packets and ignore the IGMP snooping entries.
74 MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1);
76 static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb)
78 MLXSW_REG_ZERO(sgcr, payload);
79 mlxsw_reg_sgcr_llb_set(payload, !!llb);
82 /* SPAD - Switch Physical Address Register
83 * ---------------------------------------
84 * The SPAD register configures the switch physical MAC address.
86 #define MLXSW_REG_SPAD_ID 0x2002
87 #define MLXSW_REG_SPAD_LEN 0x10
89 static const struct mlxsw_reg_info mlxsw_reg_spad = {
90 .id = MLXSW_REG_SPAD_ID,
91 .len = MLXSW_REG_SPAD_LEN,
95 * Base MAC address for the switch partitions.
96 * Per switch partition MAC address is equal to:
100 MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6);
102 /* SMID - Switch Multicast ID
103 * --------------------------
104 * The MID record maps from a MID (Multicast ID), which is a unique identifier
105 * of the multicast group within the stacking domain, into a list of local
106 * ports into which the packet is replicated.
108 #define MLXSW_REG_SMID_ID 0x2007
109 #define MLXSW_REG_SMID_LEN 0x240
111 static const struct mlxsw_reg_info mlxsw_reg_smid = {
112 .id = MLXSW_REG_SMID_ID,
113 .len = MLXSW_REG_SMID_LEN,
117 * Switch partition ID.
120 MLXSW_ITEM32(reg, smid, swid, 0x00, 24, 8);
123 * Multicast identifier - global identifier that represents the multicast group
124 * across all devices.
127 MLXSW_ITEM32(reg, smid, mid, 0x00, 0, 16);
130 * Local port memebership (1 bit per port).
133 MLXSW_ITEM_BIT_ARRAY(reg, smid, port, 0x20, 0x20, 1);
135 /* reg_smid_port_mask
136 * Local port mask (1 bit per port).
139 MLXSW_ITEM_BIT_ARRAY(reg, smid, port_mask, 0x220, 0x20, 1);
141 static inline void mlxsw_reg_smid_pack(char *payload, u16 mid,
144 MLXSW_REG_ZERO(smid, payload);
145 mlxsw_reg_smid_swid_set(payload, 0);
146 mlxsw_reg_smid_mid_set(payload, mid);
147 mlxsw_reg_smid_port_set(payload, port, set);
148 mlxsw_reg_smid_port_mask_set(payload, port, 1);
151 /* SSPR - Switch System Port Record Register
152 * -----------------------------------------
153 * Configures the system port to local port mapping.
155 #define MLXSW_REG_SSPR_ID 0x2008
156 #define MLXSW_REG_SSPR_LEN 0x8
158 static const struct mlxsw_reg_info mlxsw_reg_sspr = {
159 .id = MLXSW_REG_SSPR_ID,
160 .len = MLXSW_REG_SSPR_LEN,
164 * Master - if set, then the record describes the master system port.
165 * This is needed in case a local port is mapped into several system ports
166 * (for multipathing). That number will be reported as the source system
167 * port when packets are forwarded to the CPU. Only one master port is allowed
170 * Note: Must be set for Spectrum.
173 MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1);
175 /* reg_sspr_local_port
180 MLXSW_ITEM32(reg, sspr, local_port, 0x00, 16, 8);
183 * Virtual port within the physical port.
184 * Should be set to 0 when virtual ports are not enabled on the port.
188 MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8);
190 /* reg_sspr_system_port
191 * Unique identifier within the stacking domain that represents all the ports
192 * that are available in the system (external ports).
194 * Currently, only single-ASIC configurations are supported, so we default to
195 * 1:1 mapping between system ports and local ports.
198 MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16);
200 static inline void mlxsw_reg_sspr_pack(char *payload, u8 local_port)
202 MLXSW_REG_ZERO(sspr, payload);
203 mlxsw_reg_sspr_m_set(payload, 1);
204 mlxsw_reg_sspr_local_port_set(payload, local_port);
205 mlxsw_reg_sspr_sub_port_set(payload, 0);
206 mlxsw_reg_sspr_system_port_set(payload, local_port);
209 /* SFDAT - Switch Filtering Database Aging Time
210 * --------------------------------------------
211 * Controls the Switch aging time. Aging time is able to be set per Switch
214 #define MLXSW_REG_SFDAT_ID 0x2009
215 #define MLXSW_REG_SFDAT_LEN 0x8
217 static const struct mlxsw_reg_info mlxsw_reg_sfdat = {
218 .id = MLXSW_REG_SFDAT_ID,
219 .len = MLXSW_REG_SFDAT_LEN,
223 * Switch partition ID.
226 MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8);
228 /* reg_sfdat_age_time
229 * Aging time in seconds
231 * Max - 1,000,000 seconds
232 * Default is 300 seconds.
235 MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20);
237 static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time)
239 MLXSW_REG_ZERO(sfdat, payload);
240 mlxsw_reg_sfdat_swid_set(payload, 0);
241 mlxsw_reg_sfdat_age_time_set(payload, age_time);
244 /* SFD - Switch Filtering Database
245 * -------------------------------
246 * The following register defines the access to the filtering database.
247 * The register supports querying, adding, removing and modifying the database.
248 * The access is optimized for bulk updates in which case more than one
249 * FDB record is present in the same command.
251 #define MLXSW_REG_SFD_ID 0x200A
252 #define MLXSW_REG_SFD_BASE_LEN 0x10 /* base length, without records */
253 #define MLXSW_REG_SFD_REC_LEN 0x10 /* record length */
254 #define MLXSW_REG_SFD_REC_MAX_COUNT 64
255 #define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN + \
256 MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT)
258 static const struct mlxsw_reg_info mlxsw_reg_sfd = {
259 .id = MLXSW_REG_SFD_ID,
260 .len = MLXSW_REG_SFD_LEN,
264 * Switch partition ID for queries. Reserved on Write.
267 MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8);
269 enum mlxsw_reg_sfd_op {
270 /* Dump entire FDB a (process according to record_locator) */
271 MLXSW_REG_SFD_OP_QUERY_DUMP = 0,
272 /* Query records by {MAC, VID/FID} value */
273 MLXSW_REG_SFD_OP_QUERY_QUERY = 1,
274 /* Query and clear activity. Query records by {MAC, VID/FID} value */
275 MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2,
276 /* Test. Response indicates if each of the records could be
279 MLXSW_REG_SFD_OP_WRITE_TEST = 0,
280 /* Add/modify. Aged-out records cannot be added. This command removes
281 * the learning notification of the {MAC, VID/FID}. Response includes
282 * the entries that were added to the FDB.
284 MLXSW_REG_SFD_OP_WRITE_EDIT = 1,
285 /* Remove record by {MAC, VID/FID}. This command also removes
286 * the learning notification and aged-out notifications
287 * of the {MAC, VID/FID}. The response provides current (pre-removal)
288 * entries as non-aged-out.
290 MLXSW_REG_SFD_OP_WRITE_REMOVE = 2,
291 /* Remove learned notification by {MAC, VID/FID}. The response provides
292 * the removed learning notification.
294 MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2,
301 MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2);
303 /* reg_sfd_record_locator
304 * Used for querying the FDB. Use record_locator=0 to initiate the
305 * query. When a record is returned, a new record_locator is
306 * returned to be used in the subsequent query.
307 * Reserved for database update.
310 MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30);
313 * Request: Number of records to read/add/modify/remove
314 * Response: Number of records read/added/replaced/removed
315 * See above description for more details.
319 MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8);
321 static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op,
324 MLXSW_REG_ZERO(sfd, payload);
325 mlxsw_reg_sfd_op_set(payload, op);
326 mlxsw_reg_sfd_record_locator_set(payload, record_locator);
330 * Switch partition ID.
333 MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8,
334 MLXSW_REG_SFD_REC_LEN, 0x00, false);
336 enum mlxsw_reg_sfd_rec_type {
337 MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0,
338 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1,
339 MLXSW_REG_SFD_REC_TYPE_MULTICAST = 0x2,
346 MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4,
347 MLXSW_REG_SFD_REC_LEN, 0x00, false);
349 enum mlxsw_reg_sfd_rec_policy {
350 /* Replacement disabled, aging disabled. */
351 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0,
352 /* (mlag remote): Replacement enabled, aging disabled,
353 * learning notification enabled on this port.
355 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1,
356 /* (ingress device): Replacement enabled, aging enabled. */
357 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3,
360 /* reg_sfd_rec_policy
364 MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2,
365 MLXSW_REG_SFD_REC_LEN, 0x00, false);
368 * Activity. Set for new static entries. Set for static entries if a frame SMAC
369 * lookup hits on the entry.
370 * To clear the a bit, use "query and clear activity" op.
373 MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1,
374 MLXSW_REG_SFD_REC_LEN, 0x00, false);
380 MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6,
381 MLXSW_REG_SFD_REC_LEN, 0x02);
383 enum mlxsw_reg_sfd_rec_action {
385 MLXSW_REG_SFD_REC_ACTION_NOP = 0,
386 /* forward and trap, trap_id is FDB_TRAP */
387 MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1,
388 /* trap and do not forward, trap_id is FDB_TRAP */
389 MLXSW_REG_SFD_REC_ACTION_TRAP = 2,
390 /* forward to IP router */
391 MLXSW_REG_SFD_REC_ACTION_FORWARD_IP_ROUTER = 3,
392 MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15,
395 /* reg_sfd_rec_action
396 * Action to apply on the packet.
397 * Note: Dynamic entries can only be configured with NOP action.
400 MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4,
401 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
403 /* reg_sfd_uc_sub_port
404 * VEPA channel on local port.
405 * Valid only if local port is a non-stacking port. Must be 0 if multichannel
406 * VEPA is not enabled.
409 MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8,
410 MLXSW_REG_SFD_REC_LEN, 0x08, false);
412 /* reg_sfd_uc_fid_vid
413 * Filtering ID or VLAN ID
414 * For SwitchX and SwitchX-2:
415 * - Dynamic entries (policy 2,3) use FID
416 * - Static entries (policy 0) use VID
417 * - When independent learning is configured, VID=FID
418 * For Spectrum: use FID for both Dynamic and Static entries.
419 * VID should not be used.
422 MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
423 MLXSW_REG_SFD_REC_LEN, 0x08, false);
425 /* reg_sfd_uc_system_port
426 * Unique port identifier for the final destination of the packet.
429 MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16,
430 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
432 static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index,
433 enum mlxsw_reg_sfd_rec_type rec_type,
435 enum mlxsw_reg_sfd_rec_action action)
437 u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload);
439 if (rec_index >= num_rec)
440 mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1);
441 mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0);
442 mlxsw_reg_sfd_rec_type_set(payload, rec_index, rec_type);
443 mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac);
444 mlxsw_reg_sfd_rec_action_set(payload, rec_index, action);
447 static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index,
448 enum mlxsw_reg_sfd_rec_policy policy,
449 const char *mac, u16 fid_vid,
450 enum mlxsw_reg_sfd_rec_action action,
453 mlxsw_reg_sfd_rec_pack(payload, rec_index,
454 MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action);
455 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
456 mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0);
457 mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid);
458 mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port);
461 static inline void mlxsw_reg_sfd_uc_unpack(char *payload, int rec_index,
462 char *mac, u16 *p_fid_vid,
465 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac);
466 *p_fid_vid = mlxsw_reg_sfd_uc_fid_vid_get(payload, rec_index);
467 *p_local_port = mlxsw_reg_sfd_uc_system_port_get(payload, rec_index);
470 /* reg_sfd_uc_lag_sub_port
472 * Must be 0 if multichannel VEPA is not enabled.
475 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8,
476 MLXSW_REG_SFD_REC_LEN, 0x08, false);
478 /* reg_sfd_uc_lag_fid_vid
479 * Filtering ID or VLAN ID
480 * For SwitchX and SwitchX-2:
481 * - Dynamic entries (policy 2,3) use FID
482 * - Static entries (policy 0) use VID
483 * - When independent learning is configured, VID=FID
484 * For Spectrum: use FID for both Dynamic and Static entries.
485 * VID should not be used.
488 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
489 MLXSW_REG_SFD_REC_LEN, 0x08, false);
491 /* reg_sfd_uc_lag_lag_vid
492 * Indicates VID in case of vFIDs. Reserved for FIDs.
495 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12,
496 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
498 /* reg_sfd_uc_lag_lag_id
499 * LAG Identifier - pointer into the LAG descriptor table.
502 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10,
503 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
506 mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index,
507 enum mlxsw_reg_sfd_rec_policy policy,
508 const char *mac, u16 fid_vid,
509 enum mlxsw_reg_sfd_rec_action action, u16 lag_vid,
512 mlxsw_reg_sfd_rec_pack(payload, rec_index,
513 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG,
515 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
516 mlxsw_reg_sfd_uc_lag_sub_port_set(payload, rec_index, 0);
517 mlxsw_reg_sfd_uc_lag_fid_vid_set(payload, rec_index, fid_vid);
518 mlxsw_reg_sfd_uc_lag_lag_vid_set(payload, rec_index, lag_vid);
519 mlxsw_reg_sfd_uc_lag_lag_id_set(payload, rec_index, lag_id);
522 static inline void mlxsw_reg_sfd_uc_lag_unpack(char *payload, int rec_index,
523 char *mac, u16 *p_vid,
526 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac);
527 *p_vid = mlxsw_reg_sfd_uc_lag_fid_vid_get(payload, rec_index);
528 *p_lag_id = mlxsw_reg_sfd_uc_lag_lag_id_get(payload, rec_index);
533 * Multicast port group index - index into the port group table.
534 * Value 0x1FFF indicates the pgi should point to the MID entry.
535 * For Spectrum this value must be set to 0x1FFF
538 MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13,
539 MLXSW_REG_SFD_REC_LEN, 0x08, false);
541 /* reg_sfd_mc_fid_vid
543 * Filtering ID or VLAN ID
546 MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
547 MLXSW_REG_SFD_REC_LEN, 0x08, false);
551 * Multicast identifier - global identifier that represents the multicast
552 * group across all devices.
555 MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
556 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
559 mlxsw_reg_sfd_mc_pack(char *payload, int rec_index,
560 const char *mac, u16 fid_vid,
561 enum mlxsw_reg_sfd_rec_action action, u16 mid)
563 mlxsw_reg_sfd_rec_pack(payload, rec_index,
564 MLXSW_REG_SFD_REC_TYPE_MULTICAST, mac, action);
565 mlxsw_reg_sfd_mc_pgi_set(payload, rec_index, 0x1FFF);
566 mlxsw_reg_sfd_mc_fid_vid_set(payload, rec_index, fid_vid);
567 mlxsw_reg_sfd_mc_mid_set(payload, rec_index, mid);
570 /* SFN - Switch FDB Notification Register
571 * -------------------------------------------
572 * The switch provides notifications on newly learned FDB entries and
573 * aged out entries. The notifications can be polled by software.
575 #define MLXSW_REG_SFN_ID 0x200B
576 #define MLXSW_REG_SFN_BASE_LEN 0x10 /* base length, without records */
577 #define MLXSW_REG_SFN_REC_LEN 0x10 /* record length */
578 #define MLXSW_REG_SFN_REC_MAX_COUNT 64
579 #define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN + \
580 MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT)
582 static const struct mlxsw_reg_info mlxsw_reg_sfn = {
583 .id = MLXSW_REG_SFN_ID,
584 .len = MLXSW_REG_SFN_LEN,
588 * Switch partition ID.
591 MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8);
594 * Request: Number of learned notifications and aged-out notification
596 * Response: Number of notification records returned (must be smaller
597 * than or equal to the value requested)
601 MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8);
603 static inline void mlxsw_reg_sfn_pack(char *payload)
605 MLXSW_REG_ZERO(sfn, payload);
606 mlxsw_reg_sfn_swid_set(payload, 0);
607 mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT);
611 * Switch partition ID.
614 MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8,
615 MLXSW_REG_SFN_REC_LEN, 0x00, false);
617 enum mlxsw_reg_sfn_rec_type {
618 /* MAC addresses learned on a regular port. */
619 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5,
620 /* MAC addresses learned on a LAG port. */
621 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6,
622 /* Aged-out MAC address on a regular port. */
623 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7,
624 /* Aged-out MAC address on a LAG port. */
625 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8,
629 * Notification record type.
632 MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4,
633 MLXSW_REG_SFN_REC_LEN, 0x00, false);
639 MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6,
640 MLXSW_REG_SFN_REC_LEN, 0x02);
642 /* reg_sfn_mac_sub_port
643 * VEPA channel on the local port.
644 * 0 if multichannel VEPA is not enabled.
647 MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8,
648 MLXSW_REG_SFN_REC_LEN, 0x08, false);
651 * Filtering identifier.
654 MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16,
655 MLXSW_REG_SFN_REC_LEN, 0x08, false);
657 /* reg_sfn_mac_system_port
658 * Unique port identifier for the final destination of the packet.
661 MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16,
662 MLXSW_REG_SFN_REC_LEN, 0x0C, false);
664 static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index,
665 char *mac, u16 *p_vid,
668 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
669 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
670 *p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index);
673 /* reg_sfn_mac_lag_lag_id
674 * LAG ID (pointer into the LAG descriptor table).
677 MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10,
678 MLXSW_REG_SFN_REC_LEN, 0x0C, false);
680 static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload, int rec_index,
681 char *mac, u16 *p_vid,
684 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
685 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
686 *p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(payload, rec_index);
689 /* SPMS - Switch Port MSTP/RSTP State Register
690 * -------------------------------------------
691 * Configures the spanning tree state of a physical port.
693 #define MLXSW_REG_SPMS_ID 0x200D
694 #define MLXSW_REG_SPMS_LEN 0x404
696 static const struct mlxsw_reg_info mlxsw_reg_spms = {
697 .id = MLXSW_REG_SPMS_ID,
698 .len = MLXSW_REG_SPMS_LEN,
701 /* reg_spms_local_port
705 MLXSW_ITEM32(reg, spms, local_port, 0x00, 16, 8);
707 enum mlxsw_reg_spms_state {
708 MLXSW_REG_SPMS_STATE_NO_CHANGE,
709 MLXSW_REG_SPMS_STATE_DISCARDING,
710 MLXSW_REG_SPMS_STATE_LEARNING,
711 MLXSW_REG_SPMS_STATE_FORWARDING,
715 * Spanning tree state of each VLAN ID (VID) of the local port.
716 * 0 - Do not change spanning tree state (used only when writing).
717 * 1 - Discarding. No learning or forwarding to/from this port (default).
718 * 2 - Learning. Port is learning, but not forwarding.
719 * 3 - Forwarding. Port is learning and forwarding.
722 MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2);
724 static inline void mlxsw_reg_spms_pack(char *payload, u8 local_port)
726 MLXSW_REG_ZERO(spms, payload);
727 mlxsw_reg_spms_local_port_set(payload, local_port);
730 static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid,
731 enum mlxsw_reg_spms_state state)
733 mlxsw_reg_spms_state_set(payload, vid, state);
736 /* SPVID - Switch Port VID
737 * -----------------------
738 * The switch port VID configures the default VID for a port.
740 #define MLXSW_REG_SPVID_ID 0x200E
741 #define MLXSW_REG_SPVID_LEN 0x08
743 static const struct mlxsw_reg_info mlxsw_reg_spvid = {
744 .id = MLXSW_REG_SPVID_ID,
745 .len = MLXSW_REG_SPVID_LEN,
748 /* reg_spvid_local_port
752 MLXSW_ITEM32(reg, spvid, local_port, 0x00, 16, 8);
754 /* reg_spvid_sub_port
755 * Virtual port within the physical port.
756 * Should be set to 0 when virtual ports are not enabled on the port.
759 MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8);
765 MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12);
767 static inline void mlxsw_reg_spvid_pack(char *payload, u8 local_port, u16 pvid)
769 MLXSW_REG_ZERO(spvid, payload);
770 mlxsw_reg_spvid_local_port_set(payload, local_port);
771 mlxsw_reg_spvid_pvid_set(payload, pvid);
774 /* SPVM - Switch Port VLAN Membership
775 * ----------------------------------
776 * The Switch Port VLAN Membership register configures the VLAN membership
777 * of a port in a VLAN denoted by VID. VLAN membership is managed per
778 * virtual port. The register can be used to add and remove VID(s) from a port.
780 #define MLXSW_REG_SPVM_ID 0x200F
781 #define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */
782 #define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */
783 #define MLXSW_REG_SPVM_REC_MAX_COUNT 256
784 #define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN + \
785 MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT)
787 static const struct mlxsw_reg_info mlxsw_reg_spvm = {
788 .id = MLXSW_REG_SPVM_ID,
789 .len = MLXSW_REG_SPVM_LEN,
793 * Priority tagged. If this bit is set, packets forwarded to the port with
794 * untagged VLAN membership (u bit is set) will be tagged with priority tag
798 MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1);
801 * Priority Tagged Update Enable. On Write operations, if this bit is cleared,
802 * the pt bit will NOT be updated. To update the pt bit, pte must be set.
805 MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1);
807 /* reg_spvm_local_port
811 MLXSW_ITEM32(reg, spvm, local_port, 0x00, 16, 8);
814 * Virtual port within the physical port.
815 * Should be set to 0 when virtual ports are not enabled on the port.
818 MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8);
821 * Number of records to update. Each record contains: i, e, u, vid.
824 MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8);
827 * Ingress membership in VLAN ID.
830 MLXSW_ITEM32_INDEXED(reg, spvm, rec_i,
831 MLXSW_REG_SPVM_BASE_LEN, 14, 1,
832 MLXSW_REG_SPVM_REC_LEN, 0, false);
835 * Egress membership in VLAN ID.
838 MLXSW_ITEM32_INDEXED(reg, spvm, rec_e,
839 MLXSW_REG_SPVM_BASE_LEN, 13, 1,
840 MLXSW_REG_SPVM_REC_LEN, 0, false);
843 * Untagged - port is an untagged member - egress transmission uses untagged
847 MLXSW_ITEM32_INDEXED(reg, spvm, rec_u,
848 MLXSW_REG_SPVM_BASE_LEN, 12, 1,
849 MLXSW_REG_SPVM_REC_LEN, 0, false);
852 * Egress membership in VLAN ID.
855 MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid,
856 MLXSW_REG_SPVM_BASE_LEN, 0, 12,
857 MLXSW_REG_SPVM_REC_LEN, 0, false);
859 static inline void mlxsw_reg_spvm_pack(char *payload, u8 local_port,
860 u16 vid_begin, u16 vid_end,
861 bool is_member, bool untagged)
863 int size = vid_end - vid_begin + 1;
866 MLXSW_REG_ZERO(spvm, payload);
867 mlxsw_reg_spvm_local_port_set(payload, local_port);
868 mlxsw_reg_spvm_num_rec_set(payload, size);
870 for (i = 0; i < size; i++) {
871 mlxsw_reg_spvm_rec_i_set(payload, i, is_member);
872 mlxsw_reg_spvm_rec_e_set(payload, i, is_member);
873 mlxsw_reg_spvm_rec_u_set(payload, i, untagged);
874 mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i);
878 /* SPAFT - Switch Port Acceptable Frame Types
879 * ------------------------------------------
880 * The Switch Port Acceptable Frame Types register configures the frame
881 * admittance of the port.
883 #define MLXSW_REG_SPAFT_ID 0x2010
884 #define MLXSW_REG_SPAFT_LEN 0x08
886 static const struct mlxsw_reg_info mlxsw_reg_spaft = {
887 .id = MLXSW_REG_SPAFT_ID,
888 .len = MLXSW_REG_SPAFT_LEN,
891 /* reg_spaft_local_port
895 * Note: CPU port is not supported (all tag types are allowed).
897 MLXSW_ITEM32(reg, spaft, local_port, 0x00, 16, 8);
899 /* reg_spaft_sub_port
900 * Virtual port within the physical port.
901 * Should be set to 0 when virtual ports are not enabled on the port.
904 MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8);
906 /* reg_spaft_allow_untagged
907 * When set, untagged frames on the ingress are allowed (default).
910 MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1);
912 /* reg_spaft_allow_prio_tagged
913 * When set, priority tagged frames on the ingress are allowed (default).
916 MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1);
918 /* reg_spaft_allow_tagged
919 * When set, tagged frames on the ingress are allowed (default).
922 MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1);
924 static inline void mlxsw_reg_spaft_pack(char *payload, u8 local_port,
927 MLXSW_REG_ZERO(spaft, payload);
928 mlxsw_reg_spaft_local_port_set(payload, local_port);
929 mlxsw_reg_spaft_allow_untagged_set(payload, allow_untagged);
930 mlxsw_reg_spaft_allow_prio_tagged_set(payload, true);
931 mlxsw_reg_spaft_allow_tagged_set(payload, true);
934 /* SFGC - Switch Flooding Group Configuration
935 * ------------------------------------------
936 * The following register controls the association of flooding tables and MIDs
937 * to packet types used for flooding.
939 #define MLXSW_REG_SFGC_ID 0x2011
940 #define MLXSW_REG_SFGC_LEN 0x10
942 static const struct mlxsw_reg_info mlxsw_reg_sfgc = {
943 .id = MLXSW_REG_SFGC_ID,
944 .len = MLXSW_REG_SFGC_LEN,
947 enum mlxsw_reg_sfgc_type {
948 MLXSW_REG_SFGC_TYPE_BROADCAST,
949 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST,
950 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4,
951 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6,
952 MLXSW_REG_SFGC_TYPE_RESERVED,
953 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP,
954 MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL,
955 MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST,
956 MLXSW_REG_SFGC_TYPE_MAX,
960 * The traffic type to reach the flooding table.
963 MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4);
965 enum mlxsw_reg_sfgc_bridge_type {
966 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID = 0,
967 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID = 1,
970 /* reg_sfgc_bridge_type
973 * Note: SwitchX-2 only supports 802.1Q mode.
975 MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3);
977 enum mlxsw_flood_table_type {
978 MLXSW_REG_SFGC_TABLE_TYPE_VID = 1,
979 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2,
980 MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0,
981 MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFEST = 3,
982 MLXSW_REG_SFGC_TABLE_TYPE_FID = 4,
985 /* reg_sfgc_table_type
986 * See mlxsw_flood_table_type
989 * Note: FID offset and FID types are not supported in SwitchX-2.
991 MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3);
993 /* reg_sfgc_flood_table
994 * Flooding table index to associate with the specific type on the specific
998 MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6);
1001 * The multicast ID for the swid. Not supported for Spectrum
1004 MLXSW_ITEM32(reg, sfgc, mid, 0x08, 0, 16);
1006 /* reg_sfgc_counter_set_type
1007 * Counter Set Type for flow counters.
1010 MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8);
1012 /* reg_sfgc_counter_index
1013 * Counter Index for flow counters.
1016 MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24);
1019 mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type,
1020 enum mlxsw_reg_sfgc_bridge_type bridge_type,
1021 enum mlxsw_flood_table_type table_type,
1022 unsigned int flood_table)
1024 MLXSW_REG_ZERO(sfgc, payload);
1025 mlxsw_reg_sfgc_type_set(payload, type);
1026 mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type);
1027 mlxsw_reg_sfgc_table_type_set(payload, table_type);
1028 mlxsw_reg_sfgc_flood_table_set(payload, flood_table);
1029 mlxsw_reg_sfgc_mid_set(payload, MLXSW_PORT_MID);
1032 /* SFTR - Switch Flooding Table Register
1033 * -------------------------------------
1034 * The switch flooding table is used for flooding packet replication. The table
1035 * defines a bit mask of ports for packet replication.
1037 #define MLXSW_REG_SFTR_ID 0x2012
1038 #define MLXSW_REG_SFTR_LEN 0x420
1040 static const struct mlxsw_reg_info mlxsw_reg_sftr = {
1041 .id = MLXSW_REG_SFTR_ID,
1042 .len = MLXSW_REG_SFTR_LEN,
1046 * Switch partition ID with which to associate the port.
1049 MLXSW_ITEM32(reg, sftr, swid, 0x00, 24, 8);
1051 /* reg_sftr_flood_table
1052 * Flooding table index to associate with the specific type on the specific
1056 MLXSW_ITEM32(reg, sftr, flood_table, 0x00, 16, 6);
1059 * Index. Used as an index into the Flooding Table in case the table is
1060 * configured to use VID / FID or FID Offset.
1063 MLXSW_ITEM32(reg, sftr, index, 0x00, 0, 16);
1065 /* reg_sftr_table_type
1066 * See mlxsw_flood_table_type
1069 MLXSW_ITEM32(reg, sftr, table_type, 0x04, 16, 3);
1072 * Range of entries to update
1075 MLXSW_ITEM32(reg, sftr, range, 0x04, 0, 16);
1078 * Local port membership (1 bit per port).
1081 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port, 0x20, 0x20, 1);
1083 /* reg_sftr_cpu_port_mask
1084 * CPU port mask (1 bit per port).
1087 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port_mask, 0x220, 0x20, 1);
1089 static inline void mlxsw_reg_sftr_pack(char *payload,
1090 unsigned int flood_table,
1092 enum mlxsw_flood_table_type table_type,
1093 unsigned int range, u8 port, bool set)
1095 MLXSW_REG_ZERO(sftr, payload);
1096 mlxsw_reg_sftr_swid_set(payload, 0);
1097 mlxsw_reg_sftr_flood_table_set(payload, flood_table);
1098 mlxsw_reg_sftr_index_set(payload, index);
1099 mlxsw_reg_sftr_table_type_set(payload, table_type);
1100 mlxsw_reg_sftr_range_set(payload, range);
1101 mlxsw_reg_sftr_port_set(payload, port, set);
1102 mlxsw_reg_sftr_port_mask_set(payload, port, 1);
1105 /* SFDF - Switch Filtering DB Flush
1106 * --------------------------------
1107 * The switch filtering DB flush register is used to flush the FDB.
1108 * Note that FDB notifications are flushed as well.
1110 #define MLXSW_REG_SFDF_ID 0x2013
1111 #define MLXSW_REG_SFDF_LEN 0x14
1113 static const struct mlxsw_reg_info mlxsw_reg_sfdf = {
1114 .id = MLXSW_REG_SFDF_ID,
1115 .len = MLXSW_REG_SFDF_LEN,
1119 * Switch partition ID.
1122 MLXSW_ITEM32(reg, sfdf, swid, 0x00, 24, 8);
1124 enum mlxsw_reg_sfdf_flush_type {
1125 MLXSW_REG_SFDF_FLUSH_PER_SWID,
1126 MLXSW_REG_SFDF_FLUSH_PER_FID,
1127 MLXSW_REG_SFDF_FLUSH_PER_PORT,
1128 MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID,
1129 MLXSW_REG_SFDF_FLUSH_PER_LAG,
1130 MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID,
1133 /* reg_sfdf_flush_type
1135 * 0 - All SWID dynamic entries are flushed.
1136 * 1 - All FID dynamic entries are flushed.
1137 * 2 - All dynamic entries pointing to port are flushed.
1138 * 3 - All FID dynamic entries pointing to port are flushed.
1139 * 4 - All dynamic entries pointing to LAG are flushed.
1140 * 5 - All FID dynamic entries pointing to LAG are flushed.
1143 MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4);
1145 /* reg_sfdf_flush_static
1147 * 0 - Flush only dynamic entries.
1148 * 1 - Flush both dynamic and static entries.
1151 MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1);
1153 static inline void mlxsw_reg_sfdf_pack(char *payload,
1154 enum mlxsw_reg_sfdf_flush_type type)
1156 MLXSW_REG_ZERO(sfdf, payload);
1157 mlxsw_reg_sfdf_flush_type_set(payload, type);
1158 mlxsw_reg_sfdf_flush_static_set(payload, true);
1165 MLXSW_ITEM32(reg, sfdf, fid, 0x0C, 0, 16);
1167 /* reg_sfdf_system_port
1171 MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16);
1173 /* reg_sfdf_port_fid_system_port
1174 * Port to flush, pointed to by FID.
1177 MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16);
1183 MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10);
1185 /* reg_sfdf_lag_fid_lag_id
1186 * LAG ID to flush, pointed to by FID.
1189 MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10);
1191 /* SLDR - Switch LAG Descriptor Register
1192 * -----------------------------------------
1193 * The switch LAG descriptor register is populated by LAG descriptors.
1194 * Each LAG descriptor is indexed by lag_id. The LAG ID runs from 0 to
1197 #define MLXSW_REG_SLDR_ID 0x2014
1198 #define MLXSW_REG_SLDR_LEN 0x0C /* counting in only one port in list */
1200 static const struct mlxsw_reg_info mlxsw_reg_sldr = {
1201 .id = MLXSW_REG_SLDR_ID,
1202 .len = MLXSW_REG_SLDR_LEN,
1205 enum mlxsw_reg_sldr_op {
1206 /* Indicates a creation of a new LAG-ID, lag_id must be valid */
1207 MLXSW_REG_SLDR_OP_LAG_CREATE,
1208 MLXSW_REG_SLDR_OP_LAG_DESTROY,
1209 /* Ports that appear in the list have the Distributor enabled */
1210 MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST,
1211 /* Removes ports from the disributor list */
1212 MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST,
1219 MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3);
1222 * LAG identifier. The lag_id is the index into the LAG descriptor table.
1225 MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10);
1227 static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id)
1229 MLXSW_REG_ZERO(sldr, payload);
1230 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_CREATE);
1231 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1234 static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id)
1236 MLXSW_REG_ZERO(sldr, payload);
1237 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_DESTROY);
1238 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1241 /* reg_sldr_num_ports
1242 * The number of member ports of the LAG.
1243 * Reserved for Create / Destroy operations
1244 * For Add / Remove operations - indicates the number of ports in the list.
1247 MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8);
1249 /* reg_sldr_system_port
1253 MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false);
1255 static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id,
1258 MLXSW_REG_ZERO(sldr, payload);
1259 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST);
1260 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1261 mlxsw_reg_sldr_num_ports_set(payload, 1);
1262 mlxsw_reg_sldr_system_port_set(payload, 0, local_port);
1265 static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id,
1268 MLXSW_REG_ZERO(sldr, payload);
1269 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST);
1270 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1271 mlxsw_reg_sldr_num_ports_set(payload, 1);
1272 mlxsw_reg_sldr_system_port_set(payload, 0, local_port);
1275 /* SLCR - Switch LAG Configuration 2 Register
1276 * -------------------------------------------
1277 * The Switch LAG Configuration register is used for configuring the
1278 * LAG properties of the switch.
1280 #define MLXSW_REG_SLCR_ID 0x2015
1281 #define MLXSW_REG_SLCR_LEN 0x10
1283 static const struct mlxsw_reg_info mlxsw_reg_slcr = {
1284 .id = MLXSW_REG_SLCR_ID,
1285 .len = MLXSW_REG_SLCR_LEN,
1288 enum mlxsw_reg_slcr_pp {
1289 /* Global Configuration (for all ports) */
1290 MLXSW_REG_SLCR_PP_GLOBAL,
1291 /* Per port configuration, based on local_port field */
1292 MLXSW_REG_SLCR_PP_PER_PORT,
1296 * Per Port Configuration
1297 * Note: Reading at Global mode results in reading port 1 configuration.
1300 MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1);
1302 /* reg_slcr_local_port
1304 * Supported from CPU port
1305 * Not supported from router port
1306 * Reserved when pp = Global Configuration
1309 MLXSW_ITEM32(reg, slcr, local_port, 0x00, 16, 8);
1311 enum mlxsw_reg_slcr_type {
1312 MLXSW_REG_SLCR_TYPE_CRC, /* default */
1313 MLXSW_REG_SLCR_TYPE_XOR,
1314 MLXSW_REG_SLCR_TYPE_RANDOM,
1321 MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4);
1324 #define MLXSW_REG_SLCR_LAG_HASH_IN_PORT BIT(0)
1325 /* SMAC - for IPv4 and IPv6 packets */
1326 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP BIT(1)
1327 /* SMAC - for non-IP packets */
1328 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP BIT(2)
1329 #define MLXSW_REG_SLCR_LAG_HASH_SMAC \
1330 (MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \
1331 MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP)
1332 /* DMAC - for IPv4 and IPv6 packets */
1333 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP BIT(3)
1334 /* DMAC - for non-IP packets */
1335 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP BIT(4)
1336 #define MLXSW_REG_SLCR_LAG_HASH_DMAC \
1337 (MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \
1338 MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP)
1339 /* Ethertype - for IPv4 and IPv6 packets */
1340 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP BIT(5)
1341 /* Ethertype - for non-IP packets */
1342 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP BIT(6)
1343 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \
1344 (MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \
1345 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP)
1346 /* VLAN ID - for IPv4 and IPv6 packets */
1347 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP BIT(7)
1348 /* VLAN ID - for non-IP packets */
1349 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP BIT(8)
1350 #define MLXSW_REG_SLCR_LAG_HASH_VLANID \
1351 (MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \
1352 MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP)
1353 /* Source IP address (can be IPv4 or IPv6) */
1354 #define MLXSW_REG_SLCR_LAG_HASH_SIP BIT(9)
1355 /* Destination IP address (can be IPv4 or IPv6) */
1356 #define MLXSW_REG_SLCR_LAG_HASH_DIP BIT(10)
1357 /* TCP/UDP source port */
1358 #define MLXSW_REG_SLCR_LAG_HASH_SPORT BIT(11)
1359 /* TCP/UDP destination port*/
1360 #define MLXSW_REG_SLCR_LAG_HASH_DPORT BIT(12)
1361 /* IPv4 Protocol/IPv6 Next Header */
1362 #define MLXSW_REG_SLCR_LAG_HASH_IPPROTO BIT(13)
1363 /* IPv6 Flow label */
1364 #define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL BIT(14)
1365 /* SID - FCoE source ID */
1366 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID BIT(15)
1367 /* DID - FCoE destination ID */
1368 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID BIT(16)
1369 /* OXID - FCoE originator exchange ID */
1370 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID BIT(17)
1371 /* Destination QP number - for RoCE packets */
1372 #define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP BIT(19)
1374 /* reg_slcr_lag_hash
1375 * LAG hashing configuration. This is a bitmask, in which each set
1376 * bit includes the corresponding item in the LAG hash calculation.
1377 * The default lag_hash contains SMAC, DMAC, VLANID and
1378 * Ethertype (for all packet types).
1381 MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20);
1383 static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash)
1385 MLXSW_REG_ZERO(slcr, payload);
1386 mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL);
1387 mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_XOR);
1388 mlxsw_reg_slcr_lag_hash_set(payload, lag_hash);
1391 /* SLCOR - Switch LAG Collector Register
1392 * -------------------------------------
1393 * The Switch LAG Collector register controls the Local Port membership
1394 * in a LAG and enablement of the collector.
1396 #define MLXSW_REG_SLCOR_ID 0x2016
1397 #define MLXSW_REG_SLCOR_LEN 0x10
1399 static const struct mlxsw_reg_info mlxsw_reg_slcor = {
1400 .id = MLXSW_REG_SLCOR_ID,
1401 .len = MLXSW_REG_SLCOR_LEN,
1404 enum mlxsw_reg_slcor_col {
1405 /* Port is added with collector disabled */
1406 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT,
1407 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED,
1408 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED,
1409 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT,
1413 * Collector configuration
1416 MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2);
1418 /* reg_slcor_local_port
1420 * Not supported for CPU port
1423 MLXSW_ITEM32(reg, slcor, local_port, 0x00, 16, 8);
1426 * LAG Identifier. Index into the LAG descriptor table.
1429 MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10);
1431 /* reg_slcor_port_index
1432 * Port index in the LAG list. Only valid on Add Port to LAG col.
1433 * Valid range is from 0 to cap_max_lag_members-1
1436 MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10);
1438 static inline void mlxsw_reg_slcor_pack(char *payload,
1439 u8 local_port, u16 lag_id,
1440 enum mlxsw_reg_slcor_col col)
1442 MLXSW_REG_ZERO(slcor, payload);
1443 mlxsw_reg_slcor_col_set(payload, col);
1444 mlxsw_reg_slcor_local_port_set(payload, local_port);
1445 mlxsw_reg_slcor_lag_id_set(payload, lag_id);
1448 static inline void mlxsw_reg_slcor_port_add_pack(char *payload,
1449 u8 local_port, u16 lag_id,
1452 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1453 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT);
1454 mlxsw_reg_slcor_port_index_set(payload, port_index);
1457 static inline void mlxsw_reg_slcor_port_remove_pack(char *payload,
1458 u8 local_port, u16 lag_id)
1460 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1461 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT);
1464 static inline void mlxsw_reg_slcor_col_enable_pack(char *payload,
1465 u8 local_port, u16 lag_id)
1467 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1468 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED);
1471 static inline void mlxsw_reg_slcor_col_disable_pack(char *payload,
1472 u8 local_port, u16 lag_id)
1474 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1475 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED);
1478 /* SPMLR - Switch Port MAC Learning Register
1479 * -----------------------------------------
1480 * Controls the Switch MAC learning policy per port.
1482 #define MLXSW_REG_SPMLR_ID 0x2018
1483 #define MLXSW_REG_SPMLR_LEN 0x8
1485 static const struct mlxsw_reg_info mlxsw_reg_spmlr = {
1486 .id = MLXSW_REG_SPMLR_ID,
1487 .len = MLXSW_REG_SPMLR_LEN,
1490 /* reg_spmlr_local_port
1491 * Local port number.
1494 MLXSW_ITEM32(reg, spmlr, local_port, 0x00, 16, 8);
1496 /* reg_spmlr_sub_port
1497 * Virtual port within the physical port.
1498 * Should be set to 0 when virtual ports are not enabled on the port.
1501 MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8);
1503 enum mlxsw_reg_spmlr_learn_mode {
1504 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0,
1505 MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2,
1506 MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3,
1509 /* reg_spmlr_learn_mode
1510 * Learning mode on the port.
1511 * 0 - Learning disabled.
1512 * 2 - Learning enabled.
1513 * 3 - Security mode.
1515 * In security mode the switch does not learn MACs on the port, but uses the
1516 * SMAC to see if it exists on another ingress port. If so, the packet is
1517 * classified as a bad packet and is discarded unless the software registers
1518 * to receive port security error packets usign HPKT.
1520 MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2);
1522 static inline void mlxsw_reg_spmlr_pack(char *payload, u8 local_port,
1523 enum mlxsw_reg_spmlr_learn_mode mode)
1525 MLXSW_REG_ZERO(spmlr, payload);
1526 mlxsw_reg_spmlr_local_port_set(payload, local_port);
1527 mlxsw_reg_spmlr_sub_port_set(payload, 0);
1528 mlxsw_reg_spmlr_learn_mode_set(payload, mode);
1531 /* SVFA - Switch VID to FID Allocation Register
1532 * --------------------------------------------
1533 * Controls the VID to FID mapping and {Port, VID} to FID mapping for
1534 * virtualized ports.
1536 #define MLXSW_REG_SVFA_ID 0x201C
1537 #define MLXSW_REG_SVFA_LEN 0x10
1539 static const struct mlxsw_reg_info mlxsw_reg_svfa = {
1540 .id = MLXSW_REG_SVFA_ID,
1541 .len = MLXSW_REG_SVFA_LEN,
1545 * Switch partition ID.
1548 MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8);
1550 /* reg_svfa_local_port
1551 * Local port number.
1554 * Note: Reserved for 802.1Q FIDs.
1556 MLXSW_ITEM32(reg, svfa, local_port, 0x00, 16, 8);
1558 enum mlxsw_reg_svfa_mt {
1559 MLXSW_REG_SVFA_MT_VID_TO_FID,
1560 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID,
1563 /* reg_svfa_mapping_table
1566 * 1 - {Port, VID} to FID
1569 * Note: Reserved for SwitchX-2.
1571 MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3);
1578 * Note: Reserved for SwitchX-2.
1580 MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1);
1586 MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16);
1592 MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12);
1594 /* reg_svfa_counter_set_type
1595 * Counter set type for flow counters.
1598 * Note: Reserved for SwitchX-2.
1600 MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8);
1602 /* reg_svfa_counter_index
1603 * Counter index for flow counters.
1606 * Note: Reserved for SwitchX-2.
1608 MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24);
1610 static inline void mlxsw_reg_svfa_pack(char *payload, u8 local_port,
1611 enum mlxsw_reg_svfa_mt mt, bool valid,
1614 MLXSW_REG_ZERO(svfa, payload);
1615 local_port = mt == MLXSW_REG_SVFA_MT_VID_TO_FID ? 0 : local_port;
1616 mlxsw_reg_svfa_swid_set(payload, 0);
1617 mlxsw_reg_svfa_local_port_set(payload, local_port);
1618 mlxsw_reg_svfa_mapping_table_set(payload, mt);
1619 mlxsw_reg_svfa_v_set(payload, valid);
1620 mlxsw_reg_svfa_fid_set(payload, fid);
1621 mlxsw_reg_svfa_vid_set(payload, vid);
1624 /* SVPE - Switch Virtual-Port Enabling Register
1625 * --------------------------------------------
1626 * Enables port virtualization.
1628 #define MLXSW_REG_SVPE_ID 0x201E
1629 #define MLXSW_REG_SVPE_LEN 0x4
1631 static const struct mlxsw_reg_info mlxsw_reg_svpe = {
1632 .id = MLXSW_REG_SVPE_ID,
1633 .len = MLXSW_REG_SVPE_LEN,
1636 /* reg_svpe_local_port
1640 * Note: CPU port is not supported (uses VLAN mode only).
1642 MLXSW_ITEM32(reg, svpe, local_port, 0x00, 16, 8);
1645 * Virtual port enable.
1646 * 0 - Disable, VLAN mode (VID to FID).
1647 * 1 - Enable, Virtual port mode ({Port, VID} to FID).
1650 MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1);
1652 static inline void mlxsw_reg_svpe_pack(char *payload, u8 local_port,
1655 MLXSW_REG_ZERO(svpe, payload);
1656 mlxsw_reg_svpe_local_port_set(payload, local_port);
1657 mlxsw_reg_svpe_vp_en_set(payload, enable);
1660 /* SFMR - Switch FID Management Register
1661 * -------------------------------------
1662 * Creates and configures FIDs.
1664 #define MLXSW_REG_SFMR_ID 0x201F
1665 #define MLXSW_REG_SFMR_LEN 0x18
1667 static const struct mlxsw_reg_info mlxsw_reg_sfmr = {
1668 .id = MLXSW_REG_SFMR_ID,
1669 .len = MLXSW_REG_SFMR_LEN,
1672 enum mlxsw_reg_sfmr_op {
1673 MLXSW_REG_SFMR_OP_CREATE_FID,
1674 MLXSW_REG_SFMR_OP_DESTROY_FID,
1679 * 0 - Create or edit FID.
1683 MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4);
1689 MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16);
1691 /* reg_sfmr_fid_offset
1693 * Used to point into the flooding table selected by SFGC register if
1694 * the table is of type FID-Offset. Otherwise, this field is reserved.
1697 MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16);
1700 * Valid Tunnel Flood Pointer.
1701 * If not set, then nve_tunnel_flood_ptr is reserved and considered NULL.
1704 * Note: Reserved for 802.1Q FIDs.
1706 MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1);
1708 /* reg_sfmr_nve_tunnel_flood_ptr
1709 * Underlay Flooding and BC Pointer.
1710 * Used as a pointer to the first entry of the group based link lists of
1711 * flooding or BC entries (for NVE tunnels).
1714 MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24);
1718 * If not set, then vni is reserved.
1721 * Note: Reserved for 802.1Q FIDs.
1723 MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1);
1726 * Virtual Network Identifier.
1729 * Note: A given VNI can only be assigned to one FID.
1731 MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24);
1733 static inline void mlxsw_reg_sfmr_pack(char *payload,
1734 enum mlxsw_reg_sfmr_op op, u16 fid,
1737 MLXSW_REG_ZERO(sfmr, payload);
1738 mlxsw_reg_sfmr_op_set(payload, op);
1739 mlxsw_reg_sfmr_fid_set(payload, fid);
1740 mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset);
1741 mlxsw_reg_sfmr_vtfp_set(payload, false);
1742 mlxsw_reg_sfmr_vv_set(payload, false);
1745 /* SPVMLR - Switch Port VLAN MAC Learning Register
1746 * -----------------------------------------------
1747 * Controls the switch MAC learning policy per {Port, VID}.
1749 #define MLXSW_REG_SPVMLR_ID 0x2020
1750 #define MLXSW_REG_SPVMLR_BASE_LEN 0x04 /* base length, without records */
1751 #define MLXSW_REG_SPVMLR_REC_LEN 0x04 /* record length */
1752 #define MLXSW_REG_SPVMLR_REC_MAX_COUNT 256
1753 #define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \
1754 MLXSW_REG_SPVMLR_REC_LEN * \
1755 MLXSW_REG_SPVMLR_REC_MAX_COUNT)
1757 static const struct mlxsw_reg_info mlxsw_reg_spvmlr = {
1758 .id = MLXSW_REG_SPVMLR_ID,
1759 .len = MLXSW_REG_SPVMLR_LEN,
1762 /* reg_spvmlr_local_port
1763 * Local ingress port.
1766 * Note: CPU port is not supported.
1768 MLXSW_ITEM32(reg, spvmlr, local_port, 0x00, 16, 8);
1770 /* reg_spvmlr_num_rec
1771 * Number of records to update.
1774 MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8);
1776 /* reg_spvmlr_rec_learn_enable
1777 * 0 - Disable learning for {Port, VID}.
1778 * 1 - Enable learning for {Port, VID}.
1781 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN,
1782 31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false);
1784 /* reg_spvmlr_rec_vid
1785 * VLAN ID to be added/removed from port or for querying.
1788 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12,
1789 MLXSW_REG_SPVMLR_REC_LEN, 0x00, false);
1791 static inline void mlxsw_reg_spvmlr_pack(char *payload, u8 local_port,
1792 u16 vid_begin, u16 vid_end,
1795 int num_rec = vid_end - vid_begin + 1;
1798 WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT);
1800 MLXSW_REG_ZERO(spvmlr, payload);
1801 mlxsw_reg_spvmlr_local_port_set(payload, local_port);
1802 mlxsw_reg_spvmlr_num_rec_set(payload, num_rec);
1804 for (i = 0; i < num_rec; i++) {
1805 mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable);
1806 mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i);
1810 /* QTCT - QoS Switch Traffic Class Table
1811 * -------------------------------------
1812 * Configures the mapping between the packet switch priority and the
1813 * traffic class on the transmit port.
1815 #define MLXSW_REG_QTCT_ID 0x400A
1816 #define MLXSW_REG_QTCT_LEN 0x08
1818 static const struct mlxsw_reg_info mlxsw_reg_qtct = {
1819 .id = MLXSW_REG_QTCT_ID,
1820 .len = MLXSW_REG_QTCT_LEN,
1823 /* reg_qtct_local_port
1824 * Local port number.
1827 * Note: CPU port is not supported.
1829 MLXSW_ITEM32(reg, qtct, local_port, 0x00, 16, 8);
1831 /* reg_qtct_sub_port
1832 * Virtual port within the physical port.
1833 * Should be set to 0 when virtual ports are not enabled on the port.
1836 MLXSW_ITEM32(reg, qtct, sub_port, 0x00, 8, 8);
1838 /* reg_qtct_switch_prio
1842 MLXSW_ITEM32(reg, qtct, switch_prio, 0x00, 0, 4);
1847 * switch_prio 0 : tclass 1
1848 * switch_prio 1 : tclass 0
1849 * switch_prio i : tclass i, for i > 1
1852 MLXSW_ITEM32(reg, qtct, tclass, 0x04, 0, 4);
1854 static inline void mlxsw_reg_qtct_pack(char *payload, u8 local_port,
1855 u8 switch_prio, u8 tclass)
1857 MLXSW_REG_ZERO(qtct, payload);
1858 mlxsw_reg_qtct_local_port_set(payload, local_port);
1859 mlxsw_reg_qtct_switch_prio_set(payload, switch_prio);
1860 mlxsw_reg_qtct_tclass_set(payload, tclass);
1863 /* QEEC - QoS ETS Element Configuration Register
1864 * ---------------------------------------------
1865 * Configures the ETS elements.
1867 #define MLXSW_REG_QEEC_ID 0x400D
1868 #define MLXSW_REG_QEEC_LEN 0x1C
1870 static const struct mlxsw_reg_info mlxsw_reg_qeec = {
1871 .id = MLXSW_REG_QEEC_ID,
1872 .len = MLXSW_REG_QEEC_LEN,
1875 /* reg_qeec_local_port
1876 * Local port number.
1879 * Note: CPU port is supported.
1881 MLXSW_ITEM32(reg, qeec, local_port, 0x00, 16, 8);
1883 enum mlxsw_reg_qeec_hr {
1884 MLXSW_REG_QEEC_HIERARCY_PORT,
1885 MLXSW_REG_QEEC_HIERARCY_GROUP,
1886 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
1887 MLXSW_REG_QEEC_HIERARCY_TC,
1890 /* reg_qeec_element_hierarchy
1897 MLXSW_ITEM32(reg, qeec, element_hierarchy, 0x04, 16, 4);
1899 /* reg_qeec_element_index
1900 * The index of the element in the hierarchy.
1903 MLXSW_ITEM32(reg, qeec, element_index, 0x04, 0, 8);
1905 /* reg_qeec_next_element_index
1906 * The index of the next (lower) element in the hierarchy.
1909 * Note: Reserved for element_hierarchy 0.
1911 MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8);
1914 MLXSW_REG_QEEC_BYTES_MODE,
1915 MLXSW_REG_QEEC_PACKETS_MODE,
1919 * Packets or bytes mode.
1924 * Note: Used for max shaper configuration. For Spectrum, packets mode
1925 * is supported only for traffic classes of CPU port.
1927 MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1);
1930 * Max shaper configuration enable. Enables configuration of the max
1931 * shaper on this ETS element.
1936 MLXSW_ITEM32(reg, qeec, mase, 0x10, 31, 1);
1938 /* A large max rate will disable the max shaper. */
1939 #define MLXSW_REG_QEEC_MAS_DIS 200000000 /* Kbps */
1941 /* reg_qeec_max_shaper_rate
1942 * Max shaper information rate.
1943 * For CPU port, can only be configured for port hierarchy.
1944 * When in bytes mode, value is specified in units of 1000bps.
1947 MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 28);
1950 * DWRR configuration enable. Enables configuration of the dwrr and
1956 MLXSW_ITEM32(reg, qeec, de, 0x18, 31, 1);
1959 * Transmission selection algorithm to use on the link going down from
1961 * 0 - Strict priority
1965 MLXSW_ITEM32(reg, qeec, dwrr, 0x18, 15, 1);
1967 /* reg_qeec_dwrr_weight
1968 * DWRR weight on the link going down from the ETS element. The
1969 * percentage of bandwidth guaranteed to an ETS element within
1970 * its hierarchy. The sum of all weights across all ETS elements
1971 * within one hierarchy should be equal to 100. Reserved when
1972 * transmission selection algorithm is strict priority.
1975 MLXSW_ITEM32(reg, qeec, dwrr_weight, 0x18, 0, 8);
1977 static inline void mlxsw_reg_qeec_pack(char *payload, u8 local_port,
1978 enum mlxsw_reg_qeec_hr hr, u8 index,
1981 MLXSW_REG_ZERO(qeec, payload);
1982 mlxsw_reg_qeec_local_port_set(payload, local_port);
1983 mlxsw_reg_qeec_element_hierarchy_set(payload, hr);
1984 mlxsw_reg_qeec_element_index_set(payload, index);
1985 mlxsw_reg_qeec_next_element_index_set(payload, next_index);
1988 /* PMLP - Ports Module to Local Port Register
1989 * ------------------------------------------
1990 * Configures the assignment of modules to local ports.
1992 #define MLXSW_REG_PMLP_ID 0x5002
1993 #define MLXSW_REG_PMLP_LEN 0x40
1995 static const struct mlxsw_reg_info mlxsw_reg_pmlp = {
1996 .id = MLXSW_REG_PMLP_ID,
1997 .len = MLXSW_REG_PMLP_LEN,
2001 * 0 - Tx value is used for both Tx and Rx.
2002 * 1 - Rx value is taken from a separte field.
2005 MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1);
2007 /* reg_pmlp_local_port
2008 * Local port number.
2011 MLXSW_ITEM32(reg, pmlp, local_port, 0x00, 16, 8);
2014 * 0 - Unmap local port.
2015 * 1 - Lane 0 is used.
2016 * 2 - Lanes 0 and 1 are used.
2017 * 4 - Lanes 0, 1, 2 and 3 are used.
2020 MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8);
2026 MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false);
2029 * Tx Lane. When rxtx field is cleared, this field is used for Rx as well.
2032 MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 2, 0x04, 0x00, false);
2035 * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is
2039 MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 2, 0x04, 0x00, false);
2041 static inline void mlxsw_reg_pmlp_pack(char *payload, u8 local_port)
2043 MLXSW_REG_ZERO(pmlp, payload);
2044 mlxsw_reg_pmlp_local_port_set(payload, local_port);
2047 /* PMTU - Port MTU Register
2048 * ------------------------
2049 * Configures and reports the port MTU.
2051 #define MLXSW_REG_PMTU_ID 0x5003
2052 #define MLXSW_REG_PMTU_LEN 0x10
2054 static const struct mlxsw_reg_info mlxsw_reg_pmtu = {
2055 .id = MLXSW_REG_PMTU_ID,
2056 .len = MLXSW_REG_PMTU_LEN,
2059 /* reg_pmtu_local_port
2060 * Local port number.
2063 MLXSW_ITEM32(reg, pmtu, local_port, 0x00, 16, 8);
2067 * When port type (e.g. Ethernet) is configured, the relevant MTU is
2068 * reported, otherwise the minimum between the max_mtu of the different
2069 * types is reported.
2072 MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16);
2074 /* reg_pmtu_admin_mtu
2075 * MTU value to set port to. Must be smaller or equal to max_mtu.
2076 * Note: If port type is Infiniband, then port must be disabled, when its
2080 MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16);
2082 /* reg_pmtu_oper_mtu
2083 * The actual MTU configured on the port. Packets exceeding this size
2085 * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband
2086 * oper_mtu might be smaller than admin_mtu.
2089 MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16);
2091 static inline void mlxsw_reg_pmtu_pack(char *payload, u8 local_port,
2094 MLXSW_REG_ZERO(pmtu, payload);
2095 mlxsw_reg_pmtu_local_port_set(payload, local_port);
2096 mlxsw_reg_pmtu_max_mtu_set(payload, 0);
2097 mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu);
2098 mlxsw_reg_pmtu_oper_mtu_set(payload, 0);
2101 /* PTYS - Port Type and Speed Register
2102 * -----------------------------------
2103 * Configures and reports the port speed type.
2105 * Note: When set while the link is up, the changes will not take effect
2106 * until the port transitions from down to up state.
2108 #define MLXSW_REG_PTYS_ID 0x5004
2109 #define MLXSW_REG_PTYS_LEN 0x40
2111 static const struct mlxsw_reg_info mlxsw_reg_ptys = {
2112 .id = MLXSW_REG_PTYS_ID,
2113 .len = MLXSW_REG_PTYS_LEN,
2116 /* reg_ptys_local_port
2117 * Local port number.
2120 MLXSW_ITEM32(reg, ptys, local_port, 0x00, 16, 8);
2122 #define MLXSW_REG_PTYS_PROTO_MASK_ETH BIT(2)
2124 /* reg_ptys_proto_mask
2125 * Protocol mask. Indicates which protocol is used.
2127 * 1 - Fibre Channel.
2131 MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3);
2133 #define MLXSW_REG_PTYS_ETH_SPEED_SGMII BIT(0)
2134 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX BIT(1)
2135 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 BIT(2)
2136 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 BIT(3)
2137 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR BIT(4)
2138 #define MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2 BIT(5)
2139 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 BIT(6)
2140 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 BIT(7)
2141 #define MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4 BIT(8)
2142 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR BIT(12)
2143 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR BIT(13)
2144 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR BIT(14)
2145 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 BIT(15)
2146 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4 BIT(16)
2147 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 BIT(19)
2148 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 BIT(20)
2149 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 BIT(21)
2150 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 BIT(22)
2151 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4 BIT(23)
2152 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX BIT(24)
2153 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T BIT(25)
2154 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T BIT(26)
2155 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR BIT(27)
2156 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR BIT(28)
2157 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR BIT(29)
2158 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 BIT(30)
2159 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2 BIT(31)
2161 /* reg_ptys_eth_proto_cap
2162 * Ethernet port supported speeds and protocols.
2165 MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32);
2167 /* reg_ptys_eth_proto_admin
2168 * Speed and protocol to set port to.
2171 MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32);
2173 /* reg_ptys_eth_proto_oper
2174 * The current speed and protocol configured for the port.
2177 MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32);
2179 static inline void mlxsw_reg_ptys_pack(char *payload, u8 local_port,
2182 MLXSW_REG_ZERO(ptys, payload);
2183 mlxsw_reg_ptys_local_port_set(payload, local_port);
2184 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH);
2185 mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin);
2188 static inline void mlxsw_reg_ptys_unpack(char *payload, u32 *p_eth_proto_cap,
2189 u32 *p_eth_proto_adm,
2190 u32 *p_eth_proto_oper)
2192 if (p_eth_proto_cap)
2193 *p_eth_proto_cap = mlxsw_reg_ptys_eth_proto_cap_get(payload);
2194 if (p_eth_proto_adm)
2195 *p_eth_proto_adm = mlxsw_reg_ptys_eth_proto_admin_get(payload);
2196 if (p_eth_proto_oper)
2197 *p_eth_proto_oper = mlxsw_reg_ptys_eth_proto_oper_get(payload);
2200 /* PPAD - Port Physical Address Register
2201 * -------------------------------------
2202 * The PPAD register configures the per port physical MAC address.
2204 #define MLXSW_REG_PPAD_ID 0x5005
2205 #define MLXSW_REG_PPAD_LEN 0x10
2207 static const struct mlxsw_reg_info mlxsw_reg_ppad = {
2208 .id = MLXSW_REG_PPAD_ID,
2209 .len = MLXSW_REG_PPAD_LEN,
2212 /* reg_ppad_single_base_mac
2213 * 0: base_mac, local port should be 0 and mac[7:0] is
2214 * reserved. HW will set incremental
2215 * 1: single_mac - mac of the local_port
2218 MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1);
2220 /* reg_ppad_local_port
2221 * port number, if single_base_mac = 0 then local_port is reserved
2224 MLXSW_ITEM32(reg, ppad, local_port, 0x00, 16, 8);
2227 * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved.
2228 * If single_base_mac = 1 - the per port MAC address
2231 MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6);
2233 static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac,
2236 MLXSW_REG_ZERO(ppad, payload);
2237 mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac);
2238 mlxsw_reg_ppad_local_port_set(payload, local_port);
2241 /* PAOS - Ports Administrative and Operational Status Register
2242 * -----------------------------------------------------------
2243 * Configures and retrieves per port administrative and operational status.
2245 #define MLXSW_REG_PAOS_ID 0x5006
2246 #define MLXSW_REG_PAOS_LEN 0x10
2248 static const struct mlxsw_reg_info mlxsw_reg_paos = {
2249 .id = MLXSW_REG_PAOS_ID,
2250 .len = MLXSW_REG_PAOS_LEN,
2254 * Switch partition ID with which to associate the port.
2255 * Note: while external ports uses unique local port numbers (and thus swid is
2256 * redundant), router ports use the same local port number where swid is the
2257 * only indication for the relevant port.
2260 MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8);
2262 /* reg_paos_local_port
2263 * Local port number.
2266 MLXSW_ITEM32(reg, paos, local_port, 0x00, 16, 8);
2268 /* reg_paos_admin_status
2269 * Port administrative state (the desired state of the port):
2272 * 3 - Up once. This means that in case of link failure, the port won't go
2273 * into polling mode, but will wait to be re-enabled by software.
2274 * 4 - Disabled by system. Can only be set by hardware.
2277 MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4);
2279 /* reg_paos_oper_status
2280 * Port operational state (the current state):
2283 * 3 - Down by port failure. This means that the device will not let the
2284 * port up again until explicitly specified by software.
2287 MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4);
2290 * Admin state update enabled.
2293 MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1);
2296 * Event update enable. If this bit is set, event generation will be
2297 * updated based on the e field.
2300 MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1);
2303 * Event generation on operational state change:
2304 * 0 - Do not generate event.
2305 * 1 - Generate Event.
2306 * 2 - Generate Single Event.
2309 MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2);
2311 static inline void mlxsw_reg_paos_pack(char *payload, u8 local_port,
2312 enum mlxsw_port_admin_status status)
2314 MLXSW_REG_ZERO(paos, payload);
2315 mlxsw_reg_paos_swid_set(payload, 0);
2316 mlxsw_reg_paos_local_port_set(payload, local_port);
2317 mlxsw_reg_paos_admin_status_set(payload, status);
2318 mlxsw_reg_paos_oper_status_set(payload, 0);
2319 mlxsw_reg_paos_ase_set(payload, 1);
2320 mlxsw_reg_paos_ee_set(payload, 1);
2321 mlxsw_reg_paos_e_set(payload, 1);
2324 /* PFCC - Ports Flow Control Configuration Register
2325 * ------------------------------------------------
2326 * Configures and retrieves the per port flow control configuration.
2328 #define MLXSW_REG_PFCC_ID 0x5007
2329 #define MLXSW_REG_PFCC_LEN 0x20
2331 static const struct mlxsw_reg_info mlxsw_reg_pfcc = {
2332 .id = MLXSW_REG_PFCC_ID,
2333 .len = MLXSW_REG_PFCC_LEN,
2336 /* reg_pfcc_local_port
2337 * Local port number.
2340 MLXSW_ITEM32(reg, pfcc, local_port, 0x00, 16, 8);
2343 * Port number access type. Determines the way local_port is interpreted:
2344 * 0 - Local port number.
2345 * 1 - IB / label port number.
2348 MLXSW_ITEM32(reg, pfcc, pnat, 0x00, 14, 2);
2351 * Send to higher layers capabilities:
2352 * 0 - No capability of sending Pause and PFC frames to higher layers.
2353 * 1 - Device has capability of sending Pause and PFC frames to higher
2357 MLXSW_ITEM32(reg, pfcc, shl_cap, 0x00, 1, 1);
2360 * Send to higher layers operation:
2361 * 0 - Pause and PFC frames are handled by the port (default).
2362 * 1 - Pause and PFC frames are handled by the port and also sent to
2363 * higher layers. Only valid if shl_cap = 1.
2366 MLXSW_ITEM32(reg, pfcc, shl_opr, 0x00, 0, 1);
2369 * Pause policy auto negotiation.
2370 * 0 - Disabled. Generate / ignore Pause frames based on pptx / pprtx.
2371 * 1 - Enabled. When auto-negotiation is performed, set the Pause policy
2372 * based on the auto-negotiation resolution.
2375 * Note: The auto-negotiation advertisement is set according to pptx and
2376 * pprtx. When PFC is set on Tx / Rx, ppan must be set to 0.
2378 MLXSW_ITEM32(reg, pfcc, ppan, 0x04, 28, 4);
2380 /* reg_pfcc_prio_mask_tx
2381 * Bit per priority indicating if Tx flow control policy should be
2382 * updated based on bit pfctx.
2385 MLXSW_ITEM32(reg, pfcc, prio_mask_tx, 0x04, 16, 8);
2387 /* reg_pfcc_prio_mask_rx
2388 * Bit per priority indicating if Rx flow control policy should be
2389 * updated based on bit pfcrx.
2392 MLXSW_ITEM32(reg, pfcc, prio_mask_rx, 0x04, 0, 8);
2395 * Admin Pause policy on Tx.
2396 * 0 - Never generate Pause frames (default).
2397 * 1 - Generate Pause frames according to Rx buffer threshold.
2400 MLXSW_ITEM32(reg, pfcc, pptx, 0x08, 31, 1);
2403 * Active (operational) Pause policy on Tx.
2404 * 0 - Never generate Pause frames.
2405 * 1 - Generate Pause frames according to Rx buffer threshold.
2408 MLXSW_ITEM32(reg, pfcc, aptx, 0x08, 30, 1);
2411 * Priority based flow control policy on Tx[7:0]. Per-priority bit mask:
2412 * 0 - Never generate priority Pause frames on the specified priority
2414 * 1 - Generate priority Pause frames according to Rx buffer threshold on
2415 * the specified priority.
2418 * Note: pfctx and pptx must be mutually exclusive.
2420 MLXSW_ITEM32(reg, pfcc, pfctx, 0x08, 16, 8);
2423 * Admin Pause policy on Rx.
2424 * 0 - Ignore received Pause frames (default).
2425 * 1 - Respect received Pause frames.
2428 MLXSW_ITEM32(reg, pfcc, pprx, 0x0C, 31, 1);
2431 * Active (operational) Pause policy on Rx.
2432 * 0 - Ignore received Pause frames.
2433 * 1 - Respect received Pause frames.
2436 MLXSW_ITEM32(reg, pfcc, aprx, 0x0C, 30, 1);
2439 * Priority based flow control policy on Rx[7:0]. Per-priority bit mask:
2440 * 0 - Ignore incoming priority Pause frames on the specified priority
2442 * 1 - Respect incoming priority Pause frames on the specified priority.
2445 MLXSW_ITEM32(reg, pfcc, pfcrx, 0x0C, 16, 8);
2447 #define MLXSW_REG_PFCC_ALL_PRIO 0xFF
2449 static inline void mlxsw_reg_pfcc_prio_pack(char *payload, u8 pfc_en)
2451 mlxsw_reg_pfcc_prio_mask_tx_set(payload, MLXSW_REG_PFCC_ALL_PRIO);
2452 mlxsw_reg_pfcc_prio_mask_rx_set(payload, MLXSW_REG_PFCC_ALL_PRIO);
2453 mlxsw_reg_pfcc_pfctx_set(payload, pfc_en);
2454 mlxsw_reg_pfcc_pfcrx_set(payload, pfc_en);
2457 static inline void mlxsw_reg_pfcc_pack(char *payload, u8 local_port)
2459 MLXSW_REG_ZERO(pfcc, payload);
2460 mlxsw_reg_pfcc_local_port_set(payload, local_port);
2463 /* PPCNT - Ports Performance Counters Register
2464 * -------------------------------------------
2465 * The PPCNT register retrieves per port performance counters.
2467 #define MLXSW_REG_PPCNT_ID 0x5008
2468 #define MLXSW_REG_PPCNT_LEN 0x100
2470 static const struct mlxsw_reg_info mlxsw_reg_ppcnt = {
2471 .id = MLXSW_REG_PPCNT_ID,
2472 .len = MLXSW_REG_PPCNT_LEN,
2476 * For HCA: must be always 0.
2477 * Switch partition ID to associate port with.
2478 * Switch partitions are numbered from 0 to 7 inclusively.
2479 * Switch partition 254 indicates stacking ports.
2480 * Switch partition 255 indicates all switch partitions.
2481 * Only valid on Set() operation with local_port=255.
2484 MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8);
2486 /* reg_ppcnt_local_port
2487 * Local port number.
2488 * 255 indicates all ports on the device, and is only allowed
2489 * for Set() operation.
2492 MLXSW_ITEM32(reg, ppcnt, local_port, 0x00, 16, 8);
2495 * Port number access type:
2496 * 0 - Local port number
2497 * 1 - IB port number
2500 MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2);
2502 enum mlxsw_reg_ppcnt_grp {
2503 MLXSW_REG_PPCNT_IEEE_8023_CNT = 0x0,
2504 MLXSW_REG_PPCNT_PRIO_CNT = 0x10,
2508 * Performance counter group.
2509 * Group 63 indicates all groups. Only valid on Set() operation with
2511 * 0x0: IEEE 802.3 Counters
2512 * 0x1: RFC 2863 Counters
2513 * 0x2: RFC 2819 Counters
2514 * 0x3: RFC 3635 Counters
2515 * 0x5: Ethernet Extended Counters
2516 * 0x8: Link Level Retransmission Counters
2517 * 0x10: Per Priority Counters
2518 * 0x11: Per Traffic Class Counters
2519 * 0x12: Physical Layer Counters
2522 MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6);
2525 * Clear counters. Setting the clr bit will reset the counter value
2526 * for all counters in the counter group. This bit can be set
2527 * for both Set() and Get() operation.
2530 MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1);
2532 /* reg_ppcnt_prio_tc
2533 * Priority for counter set that support per priority, valid values: 0-7.
2534 * Traffic class for counter set that support per traffic class,
2535 * valid values: 0- cap_max_tclass-1 .
2536 * For HCA: cap_max_tclass is always 8.
2537 * Otherwise must be 0.
2540 MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5);
2542 /* Ethernet IEEE 802.3 Counter Group */
2544 /* reg_ppcnt_a_frames_transmitted_ok
2547 MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok,
2548 0x08 + 0x00, 0, 64);
2550 /* reg_ppcnt_a_frames_received_ok
2553 MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok,
2554 0x08 + 0x08, 0, 64);
2556 /* reg_ppcnt_a_frame_check_sequence_errors
2559 MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors,
2560 0x08 + 0x10, 0, 64);
2562 /* reg_ppcnt_a_alignment_errors
2565 MLXSW_ITEM64(reg, ppcnt, a_alignment_errors,
2566 0x08 + 0x18, 0, 64);
2568 /* reg_ppcnt_a_octets_transmitted_ok
2571 MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok,
2572 0x08 + 0x20, 0, 64);
2574 /* reg_ppcnt_a_octets_received_ok
2577 MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok,
2578 0x08 + 0x28, 0, 64);
2580 /* reg_ppcnt_a_multicast_frames_xmitted_ok
2583 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok,
2584 0x08 + 0x30, 0, 64);
2586 /* reg_ppcnt_a_broadcast_frames_xmitted_ok
2589 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok,
2590 0x08 + 0x38, 0, 64);
2592 /* reg_ppcnt_a_multicast_frames_received_ok
2595 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok,
2596 0x08 + 0x40, 0, 64);
2598 /* reg_ppcnt_a_broadcast_frames_received_ok
2601 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok,
2602 0x08 + 0x48, 0, 64);
2604 /* reg_ppcnt_a_in_range_length_errors
2607 MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors,
2608 0x08 + 0x50, 0, 64);
2610 /* reg_ppcnt_a_out_of_range_length_field
2613 MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field,
2614 0x08 + 0x58, 0, 64);
2616 /* reg_ppcnt_a_frame_too_long_errors
2619 MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors,
2620 0x08 + 0x60, 0, 64);
2622 /* reg_ppcnt_a_symbol_error_during_carrier
2625 MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier,
2626 0x08 + 0x68, 0, 64);
2628 /* reg_ppcnt_a_mac_control_frames_transmitted
2631 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted,
2632 0x08 + 0x70, 0, 64);
2634 /* reg_ppcnt_a_mac_control_frames_received
2637 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received,
2638 0x08 + 0x78, 0, 64);
2640 /* reg_ppcnt_a_unsupported_opcodes_received
2643 MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received,
2644 0x08 + 0x80, 0, 64);
2646 /* reg_ppcnt_a_pause_mac_ctrl_frames_received
2649 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received,
2650 0x08 + 0x88, 0, 64);
2652 /* reg_ppcnt_a_pause_mac_ctrl_frames_transmitted
2655 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted,
2656 0x08 + 0x90, 0, 64);
2658 /* Ethernet Per Priority Group Counters */
2660 /* reg_ppcnt_rx_octets
2663 MLXSW_ITEM64(reg, ppcnt, rx_octets, 0x08 + 0x00, 0, 64);
2665 /* reg_ppcnt_rx_frames
2668 MLXSW_ITEM64(reg, ppcnt, rx_frames, 0x08 + 0x20, 0, 64);
2670 /* reg_ppcnt_tx_octets
2673 MLXSW_ITEM64(reg, ppcnt, tx_octets, 0x08 + 0x28, 0, 64);
2675 /* reg_ppcnt_tx_frames
2678 MLXSW_ITEM64(reg, ppcnt, tx_frames, 0x08 + 0x48, 0, 64);
2680 /* reg_ppcnt_rx_pause
2683 MLXSW_ITEM64(reg, ppcnt, rx_pause, 0x08 + 0x50, 0, 64);
2685 /* reg_ppcnt_rx_pause_duration
2688 MLXSW_ITEM64(reg, ppcnt, rx_pause_duration, 0x08 + 0x58, 0, 64);
2690 /* reg_ppcnt_tx_pause
2693 MLXSW_ITEM64(reg, ppcnt, tx_pause, 0x08 + 0x60, 0, 64);
2695 /* reg_ppcnt_tx_pause_duration
2698 MLXSW_ITEM64(reg, ppcnt, tx_pause_duration, 0x08 + 0x68, 0, 64);
2700 /* reg_ppcnt_rx_pause_transition
2703 MLXSW_ITEM64(reg, ppcnt, tx_pause_transition, 0x08 + 0x70, 0, 64);
2705 static inline void mlxsw_reg_ppcnt_pack(char *payload, u8 local_port,
2706 enum mlxsw_reg_ppcnt_grp grp,
2709 MLXSW_REG_ZERO(ppcnt, payload);
2710 mlxsw_reg_ppcnt_swid_set(payload, 0);
2711 mlxsw_reg_ppcnt_local_port_set(payload, local_port);
2712 mlxsw_reg_ppcnt_pnat_set(payload, 0);
2713 mlxsw_reg_ppcnt_grp_set(payload, grp);
2714 mlxsw_reg_ppcnt_clr_set(payload, 0);
2715 mlxsw_reg_ppcnt_prio_tc_set(payload, prio_tc);
2718 /* PPTB - Port Prio To Buffer Register
2719 * -----------------------------------
2720 * Configures the switch priority to buffer table.
2722 #define MLXSW_REG_PPTB_ID 0x500B
2723 #define MLXSW_REG_PPTB_LEN 0x0C
2725 static const struct mlxsw_reg_info mlxsw_reg_pptb = {
2726 .id = MLXSW_REG_PPTB_ID,
2727 .len = MLXSW_REG_PPTB_LEN,
2731 MLXSW_REG_PPTB_MM_UM,
2732 MLXSW_REG_PPTB_MM_UNICAST,
2733 MLXSW_REG_PPTB_MM_MULTICAST,
2738 * 0 - Map both unicast and multicast packets to the same buffer.
2739 * 1 - Map only unicast packets.
2740 * 2 - Map only multicast packets.
2743 * Note: SwitchX-2 only supports the first option.
2745 MLXSW_ITEM32(reg, pptb, mm, 0x00, 28, 2);
2747 /* reg_pptb_local_port
2748 * Local port number.
2751 MLXSW_ITEM32(reg, pptb, local_port, 0x00, 16, 8);
2754 * Enables the update of the untagged_buf field.
2757 MLXSW_ITEM32(reg, pptb, um, 0x00, 8, 1);
2760 * Enables the update of the prio_to_buff field.
2761 * Bit <i> is a flag for updating the mapping for switch priority <i>.
2764 MLXSW_ITEM32(reg, pptb, pm, 0x00, 0, 8);
2766 /* reg_pptb_prio_to_buff
2767 * Mapping of switch priority <i> to one of the allocated receive port
2771 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff, 0x04, 0x04, 4);
2774 * Enables the update of the prio_to_buff field.
2775 * Bit <i> is a flag for updating the mapping for switch priority <i+8>.
2778 MLXSW_ITEM32(reg, pptb, pm_msb, 0x08, 24, 8);
2780 /* reg_pptb_untagged_buff
2781 * Mapping of untagged frames to one of the allocated receive port buffers.
2784 * Note: In SwitchX-2 this field must be mapped to buffer 8. Reserved for
2785 * Spectrum, as it maps untagged packets based on the default switch priority.
2787 MLXSW_ITEM32(reg, pptb, untagged_buff, 0x08, 0, 4);
2789 #define MLXSW_REG_PPTB_ALL_PRIO 0xFF
2791 static inline void mlxsw_reg_pptb_pack(char *payload, u8 local_port)
2793 MLXSW_REG_ZERO(pptb, payload);
2794 mlxsw_reg_pptb_mm_set(payload, MLXSW_REG_PPTB_MM_UM);
2795 mlxsw_reg_pptb_local_port_set(payload, local_port);
2796 mlxsw_reg_pptb_pm_set(payload, MLXSW_REG_PPTB_ALL_PRIO);
2799 /* PBMC - Port Buffer Management Control Register
2800 * ----------------------------------------------
2801 * The PBMC register configures and retrieves the port packet buffer
2802 * allocation for different Prios, and the Pause threshold management.
2804 #define MLXSW_REG_PBMC_ID 0x500C
2805 #define MLXSW_REG_PBMC_LEN 0x6C
2807 static const struct mlxsw_reg_info mlxsw_reg_pbmc = {
2808 .id = MLXSW_REG_PBMC_ID,
2809 .len = MLXSW_REG_PBMC_LEN,
2812 /* reg_pbmc_local_port
2813 * Local port number.
2816 MLXSW_ITEM32(reg, pbmc, local_port, 0x00, 16, 8);
2818 /* reg_pbmc_xoff_timer_value
2819 * When device generates a pause frame, it uses this value as the pause
2820 * timer (time for the peer port to pause in quota-512 bit time).
2823 MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16);
2825 /* reg_pbmc_xoff_refresh
2826 * The time before a new pause frame should be sent to refresh the pause RW
2827 * state. Using the same units as xoff_timer_value above (in quota-512 bit
2831 MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16);
2833 #define MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX 11
2835 /* reg_pbmc_buf_lossy
2836 * The field indicates if the buffer is lossy.
2841 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false);
2843 /* reg_pbmc_buf_epsb
2844 * Eligible for Port Shared buffer.
2845 * If epsb is set, packets assigned to buffer are allowed to insert the port
2847 * When buf_lossy is MLXSW_REG_PBMC_LOSSY_LOSSY this field is reserved.
2850 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false);
2852 /* reg_pbmc_buf_size
2853 * The part of the packet buffer array is allocated for the specific buffer.
2854 * Units are represented in cells.
2857 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false);
2859 /* reg_pbmc_buf_xoff_threshold
2860 * Once the amount of data in the buffer goes above this value, device
2861 * starts sending PFC frames for all priorities associated with the
2862 * buffer. Units are represented in cells. Reserved in case of lossy
2866 * Note: In Spectrum, reserved for buffer[9].
2868 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xoff_threshold, 0x0C, 16, 16,
2871 /* reg_pbmc_buf_xon_threshold
2872 * When the amount of data in the buffer goes below this value, device
2873 * stops sending PFC frames for the priorities associated with the
2874 * buffer. Units are represented in cells. Reserved in case of lossy
2878 * Note: In Spectrum, reserved for buffer[9].
2880 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xon_threshold, 0x0C, 0, 16,
2883 static inline void mlxsw_reg_pbmc_pack(char *payload, u8 local_port,
2884 u16 xoff_timer_value, u16 xoff_refresh)
2886 MLXSW_REG_ZERO(pbmc, payload);
2887 mlxsw_reg_pbmc_local_port_set(payload, local_port);
2888 mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value);
2889 mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh);
2892 static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload,
2896 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1);
2897 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0);
2898 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size);
2901 static inline void mlxsw_reg_pbmc_lossless_buffer_pack(char *payload,
2902 int buf_index, u16 size,
2905 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 0);
2906 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0);
2907 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size);
2908 mlxsw_reg_pbmc_buf_xoff_threshold_set(payload, buf_index, threshold);
2909 mlxsw_reg_pbmc_buf_xon_threshold_set(payload, buf_index, threshold);
2912 /* PSPA - Port Switch Partition Allocation
2913 * ---------------------------------------
2914 * Controls the association of a port with a switch partition and enables
2915 * configuring ports as stacking ports.
2917 #define MLXSW_REG_PSPA_ID 0x500D
2918 #define MLXSW_REG_PSPA_LEN 0x8
2920 static const struct mlxsw_reg_info mlxsw_reg_pspa = {
2921 .id = MLXSW_REG_PSPA_ID,
2922 .len = MLXSW_REG_PSPA_LEN,
2926 * Switch partition ID.
2929 MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8);
2931 /* reg_pspa_local_port
2932 * Local port number.
2935 MLXSW_ITEM32(reg, pspa, local_port, 0x00, 16, 8);
2937 /* reg_pspa_sub_port
2938 * Virtual port within the local port. Set to 0 when virtual ports are
2939 * disabled on the local port.
2942 MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8);
2944 static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u8 local_port)
2946 MLXSW_REG_ZERO(pspa, payload);
2947 mlxsw_reg_pspa_swid_set(payload, swid);
2948 mlxsw_reg_pspa_local_port_set(payload, local_port);
2949 mlxsw_reg_pspa_sub_port_set(payload, 0);
2952 /* HTGT - Host Trap Group Table
2953 * ----------------------------
2954 * Configures the properties for forwarding to CPU.
2956 #define MLXSW_REG_HTGT_ID 0x7002
2957 #define MLXSW_REG_HTGT_LEN 0x100
2959 static const struct mlxsw_reg_info mlxsw_reg_htgt = {
2960 .id = MLXSW_REG_HTGT_ID,
2961 .len = MLXSW_REG_HTGT_LEN,
2965 * Switch partition ID.
2968 MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8);
2970 #define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0 /* For locally attached CPU */
2976 MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4);
2978 enum mlxsw_reg_htgt_trap_group {
2979 MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
2980 MLXSW_REG_HTGT_TRAP_GROUP_RX,
2981 MLXSW_REG_HTGT_TRAP_GROUP_CTRL,
2984 /* reg_htgt_trap_group
2985 * Trap group number. User defined number specifying which trap groups
2986 * should be forwarded to the CPU. The mapping between trap IDs and trap
2987 * groups is configured using HPKT register.
2990 MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8);
2993 MLXSW_REG_HTGT_POLICER_DISABLE,
2994 MLXSW_REG_HTGT_POLICER_ENABLE,
2998 * Enable policer ID specified using 'pid' field.
3001 MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1);
3004 * Policer ID for the trap group.
3007 MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8);
3009 #define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0
3011 /* reg_htgt_mirror_action
3012 * Mirror action to use.
3014 * 1 - Trap to CPU and mirror to a mirroring agent.
3015 * 2 - Mirror to a mirroring agent and do not trap to CPU.
3018 * Note: Mirroring to a mirroring agent is only supported in Spectrum.
3020 MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2);
3022 /* reg_htgt_mirroring_agent
3026 MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3);
3028 /* reg_htgt_priority
3029 * Trap group priority.
3030 * In case a packet matches multiple classification rules, the packet will
3031 * only be trapped once, based on the trap ID associated with the group (via
3032 * register HPKT) with the highest priority.
3033 * Supported values are 0-7, with 7 represnting the highest priority.
3036 * Note: In SwitchX-2 this field is ignored and the priority value is replaced
3037 * by the 'trap_group' field.
3039 MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4);
3041 /* reg_htgt_local_path_cpu_tclass
3042 * CPU ingress traffic class for the trap group.
3045 MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6);
3047 #define MLXSW_REG_HTGT_LOCAL_PATH_RDQ_EMAD 0x15
3048 #define MLXSW_REG_HTGT_LOCAL_PATH_RDQ_RX 0x14
3049 #define MLXSW_REG_HTGT_LOCAL_PATH_RDQ_CTRL 0x13
3051 /* reg_htgt_local_path_rdq
3052 * Receive descriptor queue (RDQ) to use for the trap group.
3055 MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6);
3057 static inline void mlxsw_reg_htgt_pack(char *payload,
3058 enum mlxsw_reg_htgt_trap_group group)
3062 MLXSW_REG_ZERO(htgt, payload);
3064 case MLXSW_REG_HTGT_TRAP_GROUP_EMAD:
3065 swid = MLXSW_PORT_SWID_ALL_SWIDS;
3066 rdq = MLXSW_REG_HTGT_LOCAL_PATH_RDQ_EMAD;
3068 case MLXSW_REG_HTGT_TRAP_GROUP_RX:
3070 rdq = MLXSW_REG_HTGT_LOCAL_PATH_RDQ_RX;
3072 case MLXSW_REG_HTGT_TRAP_GROUP_CTRL:
3074 rdq = MLXSW_REG_HTGT_LOCAL_PATH_RDQ_CTRL;
3077 mlxsw_reg_htgt_swid_set(payload, swid);
3078 mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL);
3079 mlxsw_reg_htgt_trap_group_set(payload, group);
3080 mlxsw_reg_htgt_pide_set(payload, MLXSW_REG_HTGT_POLICER_DISABLE);
3081 mlxsw_reg_htgt_pid_set(payload, 0);
3082 mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU);
3083 mlxsw_reg_htgt_mirroring_agent_set(payload, 0);
3084 mlxsw_reg_htgt_priority_set(payload, 0);
3085 mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, 7);
3086 mlxsw_reg_htgt_local_path_rdq_set(payload, rdq);
3089 /* HPKT - Host Packet Trap
3090 * -----------------------
3091 * Configures trap IDs inside trap groups.
3093 #define MLXSW_REG_HPKT_ID 0x7003
3094 #define MLXSW_REG_HPKT_LEN 0x10
3096 static const struct mlxsw_reg_info mlxsw_reg_hpkt = {
3097 .id = MLXSW_REG_HPKT_ID,
3098 .len = MLXSW_REG_HPKT_LEN,
3102 MLXSW_REG_HPKT_ACK_NOT_REQUIRED,
3103 MLXSW_REG_HPKT_ACK_REQUIRED,
3107 * Require acknowledgements from the host for events.
3108 * If set, then the device will wait for the event it sent to be acknowledged
3109 * by the host. This option is only relevant for event trap IDs.
3112 * Note: Currently not supported by firmware.
3114 MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1);
3116 enum mlxsw_reg_hpkt_action {
3117 MLXSW_REG_HPKT_ACTION_FORWARD,
3118 MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU,
3119 MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU,
3120 MLXSW_REG_HPKT_ACTION_DISCARD,
3121 MLXSW_REG_HPKT_ACTION_SOFT_DISCARD,
3122 MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD,
3126 * Action to perform on packet when trapped.
3127 * 0 - No action. Forward to CPU based on switching rules.
3128 * 1 - Trap to CPU (CPU receives sole copy).
3129 * 2 - Mirror to CPU (CPU receives a replica of the packet).
3131 * 4 - Soft discard (allow other traps to act on the packet).
3132 * 5 - Trap and soft discard (allow other traps to overwrite this trap).
3135 * Note: Must be set to 0 (forward) for event trap IDs, as they are already
3136 * addressed to the CPU.
3138 MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3);
3140 /* reg_hpkt_trap_group
3141 * Trap group to associate the trap with.
3144 MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6);
3150 * Note: A trap ID can only be associated with a single trap group. The device
3151 * will associate the trap ID with the last trap group configured.
3153 MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 9);
3156 MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT,
3157 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER,
3158 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER,
3162 * Configure dedicated buffer resources for control packets.
3163 * 0 - Keep factory defaults.
3164 * 1 - Do not use control buffer for this trap ID.
3165 * 2 - Use control buffer for this trap ID.
3168 MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2);
3170 static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id)
3172 enum mlxsw_reg_htgt_trap_group trap_group;
3174 MLXSW_REG_ZERO(hpkt, payload);
3175 mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED);
3176 mlxsw_reg_hpkt_action_set(payload, action);
3178 case MLXSW_TRAP_ID_ETHEMAD:
3179 case MLXSW_TRAP_ID_PUDE:
3180 trap_group = MLXSW_REG_HTGT_TRAP_GROUP_EMAD;
3183 trap_group = MLXSW_REG_HTGT_TRAP_GROUP_RX;
3186 mlxsw_reg_hpkt_trap_group_set(payload, trap_group);
3187 mlxsw_reg_hpkt_trap_id_set(payload, trap_id);
3188 mlxsw_reg_hpkt_ctrl_set(payload, MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT);
3191 /* RGCR - Router General Configuration Register
3192 * --------------------------------------------
3193 * The register is used for setting up the router configuration.
3195 #define MLXSW_REG_RGCR_ID 0x8001
3196 #define MLXSW_REG_RGCR_LEN 0x28
3198 static const struct mlxsw_reg_info mlxsw_reg_rgcr = {
3199 .id = MLXSW_REG_RGCR_ID,
3200 .len = MLXSW_REG_RGCR_LEN,
3204 * IPv4 router enable.
3207 MLXSW_ITEM32(reg, rgcr, ipv4_en, 0x00, 31, 1);
3210 * IPv6 router enable.
3213 MLXSW_ITEM32(reg, rgcr, ipv6_en, 0x00, 30, 1);
3215 /* reg_rgcr_max_router_interfaces
3216 * Defines the maximum number of active router interfaces for all virtual
3220 MLXSW_ITEM32(reg, rgcr, max_router_interfaces, 0x10, 0, 16);
3223 * Update switch priority and packet color.
3224 * 0 - Preserve the value of Switch Priority and packet color.
3225 * 1 - Recalculate the value of Switch Priority and packet color.
3228 * Note: Not supported by SwitchX and SwitchX-2.
3230 MLXSW_ITEM32(reg, rgcr, usp, 0x18, 20, 1);
3233 * Indicates how to handle the pcp_rewrite_en value:
3234 * 0 - Preserve the value of pcp_rewrite_en.
3235 * 2 - Disable PCP rewrite.
3236 * 3 - Enable PCP rewrite.
3239 * Note: Not supported by SwitchX and SwitchX-2.
3241 MLXSW_ITEM32(reg, rgcr, pcp_rw, 0x18, 16, 2);
3243 /* reg_rgcr_activity_dis
3245 * 0 - Activity will be set when an entry is hit (default).
3246 * 1 - Activity will not be set when an entry is hit.
3248 * Bit 0 - Disable activity bit in Router Algorithmic LPM Unicast Entry
3250 * Bit 1 - Disable activity bit in Router Algorithmic LPM Unicast Host
3252 * Bits 2:7 are reserved.
3255 * Note: Not supported by SwitchX, SwitchX-2 and Switch-IB.
3257 MLXSW_ITEM32(reg, rgcr, activity_dis, 0x20, 0, 8);
3259 static inline void mlxsw_reg_rgcr_pack(char *payload, bool ipv4_en)
3261 MLXSW_REG_ZERO(rgcr, payload);
3262 mlxsw_reg_rgcr_ipv4_en_set(payload, ipv4_en);
3265 /* RITR - Router Interface Table Register
3266 * --------------------------------------
3267 * The register is used to configure the router interface table.
3269 #define MLXSW_REG_RITR_ID 0x8002
3270 #define MLXSW_REG_RITR_LEN 0x40
3272 static const struct mlxsw_reg_info mlxsw_reg_ritr = {
3273 .id = MLXSW_REG_RITR_ID,
3274 .len = MLXSW_REG_RITR_LEN,
3278 * Enables routing on the router interface.
3281 MLXSW_ITEM32(reg, ritr, enable, 0x00, 31, 1);
3284 * IPv4 routing enable. Enables routing of IPv4 traffic on the router
3288 MLXSW_ITEM32(reg, ritr, ipv4, 0x00, 29, 1);
3291 * IPv6 routing enable. Enables routing of IPv6 traffic on the router
3295 MLXSW_ITEM32(reg, ritr, ipv6, 0x00, 28, 1);
3297 enum mlxsw_reg_ritr_if_type {
3298 MLXSW_REG_RITR_VLAN_IF,
3299 MLXSW_REG_RITR_FID_IF,
3300 MLXSW_REG_RITR_SP_IF,
3304 * Router interface type.
3305 * 0 - VLAN interface.
3306 * 1 - FID interface.
3307 * 2 - Sub-port interface.
3310 MLXSW_ITEM32(reg, ritr, type, 0x00, 23, 3);
3313 MLXSW_REG_RITR_RIF_CREATE,
3314 MLXSW_REG_RITR_RIF_DEL,
3319 * 0 - Create or edit RIF.
3321 * Reserved for SwitchX-2. For Spectrum, editing of interface properties
3322 * is not supported. An interface must be deleted and re-created in order
3323 * to update properties.
3326 MLXSW_ITEM32(reg, ritr, op, 0x00, 20, 2);
3329 * Router interface index. A pointer to the Router Interface Table.
3332 MLXSW_ITEM32(reg, ritr, rif, 0x00, 0, 16);
3335 * IPv4 Forwarding Enable.
3336 * Enables routing of IPv4 traffic on the router interface. When disabled,
3337 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled.
3338 * Not supported in SwitchX-2.
3341 MLXSW_ITEM32(reg, ritr, ipv4_fe, 0x04, 29, 1);
3344 * IPv6 Forwarding Enable.
3345 * Enables routing of IPv6 traffic on the router interface. When disabled,
3346 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled.
3347 * Not supported in SwitchX-2.
3350 MLXSW_ITEM32(reg, ritr, ipv6_fe, 0x04, 28, 1);
3352 /* reg_ritr_virtual_router
3353 * Virtual router ID associated with the router interface.
3356 MLXSW_ITEM32(reg, ritr, virtual_router, 0x04, 0, 16);
3359 * Router interface MTU.
3362 MLXSW_ITEM32(reg, ritr, mtu, 0x34, 0, 16);
3365 * Switch partition ID.
3368 MLXSW_ITEM32(reg, ritr, if_swid, 0x08, 24, 8);
3371 * Router interface MAC address.
3372 * In Spectrum, all MAC addresses must have the same 38 MSBits.
3375 MLXSW_ITEM_BUF(reg, ritr, if_mac, 0x12, 6);
3377 /* VLAN Interface */
3379 /* reg_ritr_vlan_if_vid
3383 MLXSW_ITEM32(reg, ritr, vlan_if_vid, 0x08, 0, 12);
3387 /* reg_ritr_fid_if_fid
3388 * Filtering ID. Used to connect a bridge to the router. Only FIDs from
3389 * the vFID range are supported.
3392 MLXSW_ITEM32(reg, ritr, fid_if_fid, 0x08, 0, 16);
3394 static inline void mlxsw_reg_ritr_fid_set(char *payload,
3395 enum mlxsw_reg_ritr_if_type rif_type,
3398 if (rif_type == MLXSW_REG_RITR_FID_IF)
3399 mlxsw_reg_ritr_fid_if_fid_set(payload, fid);
3401 mlxsw_reg_ritr_vlan_if_vid_set(payload, fid);
3404 /* Sub-port Interface */
3406 /* reg_ritr_sp_if_lag
3407 * LAG indication. When this bit is set the system_port field holds the
3411 MLXSW_ITEM32(reg, ritr, sp_if_lag, 0x08, 24, 1);
3413 /* reg_ritr_sp_system_port
3414 * Port unique indentifier. When lag bit is set, this field holds the
3415 * lag_id in bits 0:9.
3418 MLXSW_ITEM32(reg, ritr, sp_if_system_port, 0x08, 0, 16);
3420 /* reg_ritr_sp_if_vid
3424 MLXSW_ITEM32(reg, ritr, sp_if_vid, 0x18, 0, 12);
3426 static inline void mlxsw_reg_ritr_rif_pack(char *payload, u16 rif)
3428 MLXSW_REG_ZERO(ritr, payload);
3429 mlxsw_reg_ritr_rif_set(payload, rif);
3432 static inline void mlxsw_reg_ritr_sp_if_pack(char *payload, bool lag,
3433 u16 system_port, u16 vid)
3435 mlxsw_reg_ritr_sp_if_lag_set(payload, lag);
3436 mlxsw_reg_ritr_sp_if_system_port_set(payload, system_port);
3437 mlxsw_reg_ritr_sp_if_vid_set(payload, vid);
3440 static inline void mlxsw_reg_ritr_pack(char *payload, bool enable,
3441 enum mlxsw_reg_ritr_if_type type,
3442 u16 rif, u16 mtu, const char *mac)
3444 bool op = enable ? MLXSW_REG_RITR_RIF_CREATE : MLXSW_REG_RITR_RIF_DEL;
3446 MLXSW_REG_ZERO(ritr, payload);
3447 mlxsw_reg_ritr_enable_set(payload, enable);
3448 mlxsw_reg_ritr_ipv4_set(payload, 1);
3449 mlxsw_reg_ritr_type_set(payload, type);
3450 mlxsw_reg_ritr_op_set(payload, op);
3451 mlxsw_reg_ritr_rif_set(payload, rif);
3452 mlxsw_reg_ritr_ipv4_fe_set(payload, 1);
3453 mlxsw_reg_ritr_mtu_set(payload, mtu);
3454 mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac);
3457 /* MFCR - Management Fan Control Register
3458 * --------------------------------------
3459 * This register controls the settings of the Fan Speed PWM mechanism.
3461 #define MLXSW_REG_MFCR_ID 0x9001
3462 #define MLXSW_REG_MFCR_LEN 0x08
3464 static const struct mlxsw_reg_info mlxsw_reg_mfcr = {
3465 .id = MLXSW_REG_MFCR_ID,
3466 .len = MLXSW_REG_MFCR_LEN,
3469 enum mlxsw_reg_mfcr_pwm_frequency {
3470 MLXSW_REG_MFCR_PWM_FEQ_11HZ = 0x00,
3471 MLXSW_REG_MFCR_PWM_FEQ_14_7HZ = 0x01,
3472 MLXSW_REG_MFCR_PWM_FEQ_22_1HZ = 0x02,
3473 MLXSW_REG_MFCR_PWM_FEQ_1_4KHZ = 0x40,
3474 MLXSW_REG_MFCR_PWM_FEQ_5KHZ = 0x41,
3475 MLXSW_REG_MFCR_PWM_FEQ_20KHZ = 0x42,
3476 MLXSW_REG_MFCR_PWM_FEQ_22_5KHZ = 0x43,
3477 MLXSW_REG_MFCR_PWM_FEQ_25KHZ = 0x44,
3480 /* reg_mfcr_pwm_frequency
3481 * Controls the frequency of the PWM signal.
3484 MLXSW_ITEM32(reg, mfcr, pwm_frequency, 0x00, 0, 6);
3486 #define MLXSW_MFCR_TACHOS_MAX 10
3488 /* reg_mfcr_tacho_active
3489 * Indicates which of the tachometer is active (bit per tachometer).
3492 MLXSW_ITEM32(reg, mfcr, tacho_active, 0x04, 16, MLXSW_MFCR_TACHOS_MAX);
3494 #define MLXSW_MFCR_PWMS_MAX 5
3496 /* reg_mfcr_pwm_active
3497 * Indicates which of the PWM control is active (bit per PWM).
3500 MLXSW_ITEM32(reg, mfcr, pwm_active, 0x04, 0, MLXSW_MFCR_PWMS_MAX);
3503 mlxsw_reg_mfcr_pack(char *payload,
3504 enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency)
3506 MLXSW_REG_ZERO(mfcr, payload);
3507 mlxsw_reg_mfcr_pwm_frequency_set(payload, pwm_frequency);
3511 mlxsw_reg_mfcr_unpack(char *payload,
3512 enum mlxsw_reg_mfcr_pwm_frequency *p_pwm_frequency,
3513 u16 *p_tacho_active, u8 *p_pwm_active)
3515 *p_pwm_frequency = mlxsw_reg_mfcr_pwm_frequency_get(payload);
3516 *p_tacho_active = mlxsw_reg_mfcr_tacho_active_get(payload);
3517 *p_pwm_active = mlxsw_reg_mfcr_pwm_active_get(payload);
3520 /* MFSC - Management Fan Speed Control Register
3521 * --------------------------------------------
3522 * This register controls the settings of the Fan Speed PWM mechanism.
3524 #define MLXSW_REG_MFSC_ID 0x9002
3525 #define MLXSW_REG_MFSC_LEN 0x08
3527 static const struct mlxsw_reg_info mlxsw_reg_mfsc = {
3528 .id = MLXSW_REG_MFSC_ID,
3529 .len = MLXSW_REG_MFSC_LEN,
3533 * Fan pwm to control / monitor.
3536 MLXSW_ITEM32(reg, mfsc, pwm, 0x00, 24, 3);
3538 /* reg_mfsc_pwm_duty_cycle
3539 * Controls the duty cycle of the PWM. Value range from 0..255 to
3540 * represent duty cycle of 0%...100%.
3543 MLXSW_ITEM32(reg, mfsc, pwm_duty_cycle, 0x04, 0, 8);
3545 static inline void mlxsw_reg_mfsc_pack(char *payload, u8 pwm,
3548 MLXSW_REG_ZERO(mfsc, payload);
3549 mlxsw_reg_mfsc_pwm_set(payload, pwm);
3550 mlxsw_reg_mfsc_pwm_duty_cycle_set(payload, pwm_duty_cycle);
3553 /* MFSM - Management Fan Speed Measurement
3554 * ---------------------------------------
3555 * This register controls the settings of the Tacho measurements and
3556 * enables reading the Tachometer measurements.
3558 #define MLXSW_REG_MFSM_ID 0x9003
3559 #define MLXSW_REG_MFSM_LEN 0x08
3561 static const struct mlxsw_reg_info mlxsw_reg_mfsm = {
3562 .id = MLXSW_REG_MFSM_ID,
3563 .len = MLXSW_REG_MFSM_LEN,
3567 * Fan tachometer index.
3570 MLXSW_ITEM32(reg, mfsm, tacho, 0x00, 24, 4);
3573 * Fan speed (round per minute).
3576 MLXSW_ITEM32(reg, mfsm, rpm, 0x04, 0, 16);
3578 static inline void mlxsw_reg_mfsm_pack(char *payload, u8 tacho)
3580 MLXSW_REG_ZERO(mfsm, payload);
3581 mlxsw_reg_mfsm_tacho_set(payload, tacho);
3584 /* MTCAP - Management Temperature Capabilities
3585 * -------------------------------------------
3586 * This register exposes the capabilities of the device and
3587 * system temperature sensing.
3589 #define MLXSW_REG_MTCAP_ID 0x9009
3590 #define MLXSW_REG_MTCAP_LEN 0x08
3592 static const struct mlxsw_reg_info mlxsw_reg_mtcap = {
3593 .id = MLXSW_REG_MTCAP_ID,
3594 .len = MLXSW_REG_MTCAP_LEN,
3597 /* reg_mtcap_sensor_count
3598 * Number of sensors supported by the device.
3599 * This includes the QSFP module sensors (if exists in the QSFP module).
3602 MLXSW_ITEM32(reg, mtcap, sensor_count, 0x00, 0, 7);
3604 /* MTMP - Management Temperature
3605 * -----------------------------
3606 * This register controls the settings of the temperature measurements
3607 * and enables reading the temperature measurements. Note that temperature
3608 * is in 0.125 degrees Celsius.
3610 #define MLXSW_REG_MTMP_ID 0x900A
3611 #define MLXSW_REG_MTMP_LEN 0x20
3613 static const struct mlxsw_reg_info mlxsw_reg_mtmp = {
3614 .id = MLXSW_REG_MTMP_ID,
3615 .len = MLXSW_REG_MTMP_LEN,
3618 /* reg_mtmp_sensor_index
3619 * Sensors index to access.
3620 * 64-127 of sensor_index are mapped to the SFP+/QSFP modules sequentially
3621 * (module 0 is mapped to sensor_index 64).
3624 MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 7);
3626 /* Convert to milli degrees Celsius */
3627 #define MLXSW_REG_MTMP_TEMP_TO_MC(val) (val * 125)
3629 /* reg_mtmp_temperature
3630 * Temperature reading from the sensor. Reading is in 0.125 Celsius
3634 MLXSW_ITEM32(reg, mtmp, temperature, 0x04, 0, 16);
3637 * Max Temperature Enable - enables measuring the max temperature on a sensor.
3640 MLXSW_ITEM32(reg, mtmp, mte, 0x08, 31, 1);
3643 * Max Temperature Reset - clears the value of the max temperature register.
3646 MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1);
3648 /* reg_mtmp_max_temperature
3649 * The highest measured temperature from the sensor.
3650 * When the bit mte is cleared, the field max_temperature is reserved.
3653 MLXSW_ITEM32(reg, mtmp, max_temperature, 0x08, 0, 16);
3655 #define MLXSW_REG_MTMP_SENSOR_NAME_SIZE 8
3657 /* reg_mtmp_sensor_name
3661 MLXSW_ITEM_BUF(reg, mtmp, sensor_name, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE);
3663 static inline void mlxsw_reg_mtmp_pack(char *payload, u8 sensor_index,
3664 bool max_temp_enable,
3665 bool max_temp_reset)
3667 MLXSW_REG_ZERO(mtmp, payload);
3668 mlxsw_reg_mtmp_sensor_index_set(payload, sensor_index);
3669 mlxsw_reg_mtmp_mte_set(payload, max_temp_enable);
3670 mlxsw_reg_mtmp_mtr_set(payload, max_temp_reset);
3673 static inline void mlxsw_reg_mtmp_unpack(char *payload, unsigned int *p_temp,
3674 unsigned int *p_max_temp,
3680 temp = mlxsw_reg_mtmp_temperature_get(payload);
3681 *p_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp);
3684 temp = mlxsw_reg_mtmp_max_temperature_get(payload);
3685 *p_max_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp);
3688 mlxsw_reg_mtmp_sensor_name_memcpy_from(payload, sensor_name);
3691 /* MLCR - Management LED Control Register
3692 * --------------------------------------
3693 * Controls the system LEDs.
3695 #define MLXSW_REG_MLCR_ID 0x902B
3696 #define MLXSW_REG_MLCR_LEN 0x0C
3698 static const struct mlxsw_reg_info mlxsw_reg_mlcr = {
3699 .id = MLXSW_REG_MLCR_ID,
3700 .len = MLXSW_REG_MLCR_LEN,
3703 /* reg_mlcr_local_port
3704 * Local port number.
3707 MLXSW_ITEM32(reg, mlcr, local_port, 0x00, 16, 8);
3709 #define MLXSW_REG_MLCR_DURATION_MAX 0xFFFF
3711 /* reg_mlcr_beacon_duration
3712 * Duration of the beacon to be active, in seconds.
3713 * 0x0 - Will turn off the beacon.
3714 * 0xFFFF - Will turn on the beacon until explicitly turned off.
3717 MLXSW_ITEM32(reg, mlcr, beacon_duration, 0x04, 0, 16);
3719 /* reg_mlcr_beacon_remain
3720 * Remaining duration of the beacon, in seconds.
3721 * 0xFFFF indicates an infinite amount of time.
3724 MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16);
3726 static inline void mlxsw_reg_mlcr_pack(char *payload, u8 local_port,
3729 MLXSW_REG_ZERO(mlcr, payload);
3730 mlxsw_reg_mlcr_local_port_set(payload, local_port);
3731 mlxsw_reg_mlcr_beacon_duration_set(payload, active ?
3732 MLXSW_REG_MLCR_DURATION_MAX : 0);
3735 /* SBPR - Shared Buffer Pools Register
3736 * -----------------------------------
3737 * The SBPR configures and retrieves the shared buffer pools and configuration.
3739 #define MLXSW_REG_SBPR_ID 0xB001
3740 #define MLXSW_REG_SBPR_LEN 0x14
3742 static const struct mlxsw_reg_info mlxsw_reg_sbpr = {
3743 .id = MLXSW_REG_SBPR_ID,
3744 .len = MLXSW_REG_SBPR_LEN,
3747 /* shared direstion enum for SBPR, SBCM, SBPM */
3748 enum mlxsw_reg_sbxx_dir {
3749 MLXSW_REG_SBXX_DIR_INGRESS,
3750 MLXSW_REG_SBXX_DIR_EGRESS,
3757 MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2);
3763 MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4);
3766 * Pool size in buffer cells.
3769 MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24);
3771 enum mlxsw_reg_sbpr_mode {
3772 MLXSW_REG_SBPR_MODE_STATIC,
3773 MLXSW_REG_SBPR_MODE_DYNAMIC,
3777 * Pool quota calculation mode.
3780 MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4);
3782 static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool,
3783 enum mlxsw_reg_sbxx_dir dir,
3784 enum mlxsw_reg_sbpr_mode mode, u32 size)
3786 MLXSW_REG_ZERO(sbpr, payload);
3787 mlxsw_reg_sbpr_pool_set(payload, pool);
3788 mlxsw_reg_sbpr_dir_set(payload, dir);
3789 mlxsw_reg_sbpr_mode_set(payload, mode);
3790 mlxsw_reg_sbpr_size_set(payload, size);
3793 /* SBCM - Shared Buffer Class Management Register
3794 * ----------------------------------------------
3795 * The SBCM register configures and retrieves the shared buffer allocation
3796 * and configuration according to Port-PG, including the binding to pool
3797 * and definition of the associated quota.
3799 #define MLXSW_REG_SBCM_ID 0xB002
3800 #define MLXSW_REG_SBCM_LEN 0x28
3802 static const struct mlxsw_reg_info mlxsw_reg_sbcm = {
3803 .id = MLXSW_REG_SBCM_ID,
3804 .len = MLXSW_REG_SBCM_LEN,
3807 /* reg_sbcm_local_port
3808 * Local port number.
3809 * For Ingress: excludes CPU port and Router port
3810 * For Egress: excludes IP Router
3813 MLXSW_ITEM32(reg, sbcm, local_port, 0x00, 16, 8);
3816 * PG buffer - Port PG (dir=ingress) / traffic class (dir=egress)
3817 * For PG buffer: range is 0..cap_max_pg_buffers - 1
3818 * For traffic class: range is 0..cap_max_tclass - 1
3819 * Note that when traffic class is in MC aware mode then the traffic
3820 * classes which are MC aware cannot be configured.
3823 MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6);
3829 MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2);
3831 /* reg_sbcm_min_buff
3832 * Minimum buffer size for the limiter, in cells.
3835 MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24);
3837 /* shared max_buff limits for dynamic threshold for SBCM, SBPM */
3838 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN 1
3839 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX 14
3841 /* reg_sbcm_max_buff
3842 * When the pool associated to the port-pg/tclass is configured to
3843 * static, Maximum buffer size for the limiter configured in cells.
3844 * When the pool associated to the port-pg/tclass is configured to
3845 * dynamic, the max_buff holds the "alpha" parameter, supporting
3846 * the following values:
3848 * i: (1/128)*2^(i-1), for i=1..14
3852 MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24);
3855 * Association of the port-priority to a pool.
3858 MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4);
3860 static inline void mlxsw_reg_sbcm_pack(char *payload, u8 local_port, u8 pg_buff,
3861 enum mlxsw_reg_sbxx_dir dir,
3862 u32 min_buff, u32 max_buff, u8 pool)
3864 MLXSW_REG_ZERO(sbcm, payload);
3865 mlxsw_reg_sbcm_local_port_set(payload, local_port);
3866 mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff);
3867 mlxsw_reg_sbcm_dir_set(payload, dir);
3868 mlxsw_reg_sbcm_min_buff_set(payload, min_buff);
3869 mlxsw_reg_sbcm_max_buff_set(payload, max_buff);
3870 mlxsw_reg_sbcm_pool_set(payload, pool);
3873 /* SBPM - Shared Buffer Port Management Register
3874 * ---------------------------------------------
3875 * The SBPM register configures and retrieves the shared buffer allocation
3876 * and configuration according to Port-Pool, including the definition
3877 * of the associated quota.
3879 #define MLXSW_REG_SBPM_ID 0xB003
3880 #define MLXSW_REG_SBPM_LEN 0x28
3882 static const struct mlxsw_reg_info mlxsw_reg_sbpm = {
3883 .id = MLXSW_REG_SBPM_ID,
3884 .len = MLXSW_REG_SBPM_LEN,
3887 /* reg_sbpm_local_port
3888 * Local port number.
3889 * For Ingress: excludes CPU port and Router port
3890 * For Egress: excludes IP Router
3893 MLXSW_ITEM32(reg, sbpm, local_port, 0x00, 16, 8);
3896 * The pool associated to quota counting on the local_port.
3899 MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4);
3905 MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2);
3907 /* reg_sbpm_buff_occupancy
3908 * Current buffer occupancy in cells.
3911 MLXSW_ITEM32(reg, sbpm, buff_occupancy, 0x10, 0, 24);
3914 * Clear Max Buffer Occupancy
3915 * When this bit is set, max_buff_occupancy field is cleared (and a
3916 * new max value is tracked from the time the clear was performed).
3919 MLXSW_ITEM32(reg, sbpm, clr, 0x14, 31, 1);
3921 /* reg_sbpm_max_buff_occupancy
3922 * Maximum value of buffer occupancy in cells monitored. Cleared by
3923 * writing to the clr field.
3926 MLXSW_ITEM32(reg, sbpm, max_buff_occupancy, 0x14, 0, 24);
3928 /* reg_sbpm_min_buff
3929 * Minimum buffer size for the limiter, in cells.
3932 MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24);
3934 /* reg_sbpm_max_buff
3935 * When the pool associated to the port-pg/tclass is configured to
3936 * static, Maximum buffer size for the limiter configured in cells.
3937 * When the pool associated to the port-pg/tclass is configured to
3938 * dynamic, the max_buff holds the "alpha" parameter, supporting
3939 * the following values:
3941 * i: (1/128)*2^(i-1), for i=1..14
3945 MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24);
3947 static inline void mlxsw_reg_sbpm_pack(char *payload, u8 local_port, u8 pool,
3948 enum mlxsw_reg_sbxx_dir dir, bool clr,
3949 u32 min_buff, u32 max_buff)
3951 MLXSW_REG_ZERO(sbpm, payload);
3952 mlxsw_reg_sbpm_local_port_set(payload, local_port);
3953 mlxsw_reg_sbpm_pool_set(payload, pool);
3954 mlxsw_reg_sbpm_dir_set(payload, dir);
3955 mlxsw_reg_sbpm_clr_set(payload, clr);
3956 mlxsw_reg_sbpm_min_buff_set(payload, min_buff);
3957 mlxsw_reg_sbpm_max_buff_set(payload, max_buff);
3960 static inline void mlxsw_reg_sbpm_unpack(char *payload, u32 *p_buff_occupancy,
3961 u32 *p_max_buff_occupancy)
3963 *p_buff_occupancy = mlxsw_reg_sbpm_buff_occupancy_get(payload);
3964 *p_max_buff_occupancy = mlxsw_reg_sbpm_max_buff_occupancy_get(payload);
3967 /* SBMM - Shared Buffer Multicast Management Register
3968 * --------------------------------------------------
3969 * The SBMM register configures and retrieves the shared buffer allocation
3970 * and configuration for MC packets according to Switch-Priority, including
3971 * the binding to pool and definition of the associated quota.
3973 #define MLXSW_REG_SBMM_ID 0xB004
3974 #define MLXSW_REG_SBMM_LEN 0x28
3976 static const struct mlxsw_reg_info mlxsw_reg_sbmm = {
3977 .id = MLXSW_REG_SBMM_ID,
3978 .len = MLXSW_REG_SBMM_LEN,
3985 MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4);
3987 /* reg_sbmm_min_buff
3988 * Minimum buffer size for the limiter, in cells.
3991 MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24);
3993 /* reg_sbmm_max_buff
3994 * When the pool associated to the port-pg/tclass is configured to
3995 * static, Maximum buffer size for the limiter configured in cells.
3996 * When the pool associated to the port-pg/tclass is configured to
3997 * dynamic, the max_buff holds the "alpha" parameter, supporting
3998 * the following values:
4000 * i: (1/128)*2^(i-1), for i=1..14
4004 MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24);
4007 * Association of the port-priority to a pool.
4010 MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4);
4012 static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff,
4013 u32 max_buff, u8 pool)
4015 MLXSW_REG_ZERO(sbmm, payload);
4016 mlxsw_reg_sbmm_prio_set(payload, prio);
4017 mlxsw_reg_sbmm_min_buff_set(payload, min_buff);
4018 mlxsw_reg_sbmm_max_buff_set(payload, max_buff);
4019 mlxsw_reg_sbmm_pool_set(payload, pool);
4022 /* SBSR - Shared Buffer Status Register
4023 * ------------------------------------
4024 * The SBSR register retrieves the shared buffer occupancy according to
4025 * Port-Pool. Note that this register enables reading a large amount of data.
4026 * It is the user's responsibility to limit the amount of data to ensure the
4027 * response can match the maximum transfer unit. In case the response exceeds
4028 * the maximum transport unit, it will be truncated with no special notice.
4030 #define MLXSW_REG_SBSR_ID 0xB005
4031 #define MLXSW_REG_SBSR_BASE_LEN 0x5C /* base length, without records */
4032 #define MLXSW_REG_SBSR_REC_LEN 0x8 /* record length */
4033 #define MLXSW_REG_SBSR_REC_MAX_COUNT 120
4034 #define MLXSW_REG_SBSR_LEN (MLXSW_REG_SBSR_BASE_LEN + \
4035 MLXSW_REG_SBSR_REC_LEN * \
4036 MLXSW_REG_SBSR_REC_MAX_COUNT)
4038 static const struct mlxsw_reg_info mlxsw_reg_sbsr = {
4039 .id = MLXSW_REG_SBSR_ID,
4040 .len = MLXSW_REG_SBSR_LEN,
4044 * Clear Max Buffer Occupancy. When this bit is set, the max_buff_occupancy
4045 * field is cleared (and a new max value is tracked from the time the clear
4049 MLXSW_ITEM32(reg, sbsr, clr, 0x00, 31, 1);
4051 /* reg_sbsr_ingress_port_mask
4052 * Bit vector for all ingress network ports.
4053 * Indicates which of the ports (for which the relevant bit is set)
4054 * are affected by the set operation. Configuration of any other port
4058 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, ingress_port_mask, 0x10, 0x20, 1);
4060 /* reg_sbsr_pg_buff_mask
4061 * Bit vector for all switch priority groups.
4062 * Indicates which of the priorities (for which the relevant bit is set)
4063 * are affected by the set operation. Configuration of any other priority
4065 * Range is 0..cap_max_pg_buffers - 1
4068 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, pg_buff_mask, 0x30, 0x4, 1);
4070 /* reg_sbsr_egress_port_mask
4071 * Bit vector for all egress network ports.
4072 * Indicates which of the ports (for which the relevant bit is set)
4073 * are affected by the set operation. Configuration of any other port
4077 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, egress_port_mask, 0x34, 0x20, 1);
4079 /* reg_sbsr_tclass_mask
4080 * Bit vector for all traffic classes.
4081 * Indicates which of the traffic classes (for which the relevant bit is
4082 * set) are affected by the set operation. Configuration of any other
4083 * traffic class does not change.
4084 * Range is 0..cap_max_tclass - 1
4087 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, tclass_mask, 0x54, 0x8, 1);
4089 static inline void mlxsw_reg_sbsr_pack(char *payload, bool clr)
4091 MLXSW_REG_ZERO(sbsr, payload);
4092 mlxsw_reg_sbsr_clr_set(payload, clr);
4095 /* reg_sbsr_rec_buff_occupancy
4096 * Current buffer occupancy in cells.
4099 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN,
4100 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x00, false);
4102 /* reg_sbsr_rec_max_buff_occupancy
4103 * Maximum value of buffer occupancy in cells monitored. Cleared by
4104 * writing to the clr field.
4107 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_max_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN,
4108 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x04, false);
4110 static inline void mlxsw_reg_sbsr_rec_unpack(char *payload, int rec_index,
4111 u32 *p_buff_occupancy,
4112 u32 *p_max_buff_occupancy)
4115 mlxsw_reg_sbsr_rec_buff_occupancy_get(payload, rec_index);
4116 *p_max_buff_occupancy =
4117 mlxsw_reg_sbsr_rec_max_buff_occupancy_get(payload, rec_index);
4120 static inline const char *mlxsw_reg_id_str(u16 reg_id)
4123 case MLXSW_REG_SGCR_ID:
4125 case MLXSW_REG_SPAD_ID:
4127 case MLXSW_REG_SMID_ID:
4129 case MLXSW_REG_SSPR_ID:
4131 case MLXSW_REG_SFDAT_ID:
4133 case MLXSW_REG_SFD_ID:
4135 case MLXSW_REG_SFN_ID:
4137 case MLXSW_REG_SPMS_ID:
4139 case MLXSW_REG_SPVID_ID:
4141 case MLXSW_REG_SPVM_ID:
4143 case MLXSW_REG_SPAFT_ID:
4145 case MLXSW_REG_SFGC_ID:
4147 case MLXSW_REG_SFTR_ID:
4149 case MLXSW_REG_SFDF_ID:
4151 case MLXSW_REG_SLDR_ID:
4153 case MLXSW_REG_SLCR_ID:
4155 case MLXSW_REG_SLCOR_ID:
4157 case MLXSW_REG_SPMLR_ID:
4159 case MLXSW_REG_SVFA_ID:
4161 case MLXSW_REG_SVPE_ID:
4163 case MLXSW_REG_SFMR_ID:
4165 case MLXSW_REG_SPVMLR_ID:
4167 case MLXSW_REG_QTCT_ID:
4169 case MLXSW_REG_QEEC_ID:
4171 case MLXSW_REG_PMLP_ID:
4173 case MLXSW_REG_PMTU_ID:
4175 case MLXSW_REG_PTYS_ID:
4177 case MLXSW_REG_PPAD_ID:
4179 case MLXSW_REG_PAOS_ID:
4181 case MLXSW_REG_PFCC_ID:
4183 case MLXSW_REG_PPCNT_ID:
4185 case MLXSW_REG_PPTB_ID:
4187 case MLXSW_REG_PBMC_ID:
4189 case MLXSW_REG_PSPA_ID:
4191 case MLXSW_REG_HTGT_ID:
4193 case MLXSW_REG_HPKT_ID:
4195 case MLXSW_REG_RGCR_ID:
4197 case MLXSW_REG_RITR_ID:
4199 case MLXSW_REG_MFCR_ID:
4201 case MLXSW_REG_MFSC_ID:
4203 case MLXSW_REG_MFSM_ID:
4205 case MLXSW_REG_MTCAP_ID:
4207 case MLXSW_REG_MTMP_ID:
4209 case MLXSW_REG_MLCR_ID:
4211 case MLXSW_REG_SBPR_ID:
4213 case MLXSW_REG_SBCM_ID:
4215 case MLXSW_REG_SBPM_ID:
4217 case MLXSW_REG_SBMM_ID:
4219 case MLXSW_REG_SBSR_ID:
4226 /* PUDE - Port Up / Down Event
4227 * ---------------------------
4228 * Reports the operational state change of a port.
4230 #define MLXSW_REG_PUDE_LEN 0x10
4233 * Switch partition ID with which to associate the port.
4236 MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8);
4238 /* reg_pude_local_port
4239 * Local port number.
4242 MLXSW_ITEM32(reg, pude, local_port, 0x00, 16, 8);
4244 /* reg_pude_admin_status
4245 * Port administrative state (the desired state).
4248 * 3 - Up once. This means that in case of link failure, the port won't go
4249 * into polling mode, but will wait to be re-enabled by software.
4250 * 4 - Disabled by system. Can only be set by hardware.
4253 MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4);
4255 /* reg_pude_oper_status
4256 * Port operatioanl state.
4259 * 3 - Down by port failure. This means that the device will not let the
4260 * port up again until explicitly specified by software.
4263 MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4);