2 * drivers/net/ethernet/mellanox/mlxsw/spectrum.h
3 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2015 Jiri Pirko <jiri@mellanox.com>
5 * Copyright (c) 2015 Ido Schimmel <idosch@mellanox.com>
6 * Copyright (c) 2015 Elad Raz <eladr@mellanox.com>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the names of the copyright holders nor the names of its
17 * contributors may be used to endorse or promote products derived from
18 * this software without specific prior written permission.
20 * Alternatively, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") version 2 as published by the Free
22 * Software Foundation.
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
37 #ifndef _MLXSW_SPECTRUM_H
38 #define _MLXSW_SPECTRUM_H
40 #include <linux/types.h>
41 #include <linux/netdevice.h>
42 #include <linux/bitops.h>
43 #include <linux/if_vlan.h>
44 #include <linux/list.h>
45 #include <linux/dcbnl.h>
46 #include <linux/in6.h>
47 #include <net/switchdev.h>
52 #define MLXSW_SP_VFID_BASE VLAN_N_VID
53 #define MLXSW_SP_VFID_PORT_MAX 512 /* Non-bridged VLAN interfaces */
54 #define MLXSW_SP_VFID_BR_MAX 6144 /* Bridged VLAN interfaces */
55 #define MLXSW_SP_VFID_MAX (MLXSW_SP_VFID_PORT_MAX + MLXSW_SP_VFID_BR_MAX)
57 #define MLXSW_SP_LAG_MAX 64
58 #define MLXSW_SP_PORT_PER_LAG_MAX 16
60 #define MLXSW_SP_MID_MAX 7000
62 #define MLXSW_SP_PORTS_PER_CLUSTER_MAX 4
64 #define MLXSW_SP_PORT_BASE_SPEED 25000 /* Mb/s */
66 #define MLXSW_SP_BYTES_PER_CELL 96
68 #define MLXSW_SP_BYTES_TO_CELLS(b) DIV_ROUND_UP(b, MLXSW_SP_BYTES_PER_CELL)
69 #define MLXSW_SP_CELLS_TO_BYTES(c) (c * MLXSW_SP_BYTES_PER_CELL)
71 /* Maximum delay buffer needed in case of PAUSE frames, in cells.
72 * Assumes 100m cable and maximum MTU.
74 #define MLXSW_SP_PAUSE_DELAY 612
76 #define MLXSW_SP_CELL_FACTOR 2 /* 2 * cell_size / (IPG + cell_size + 1) */
78 #define MLXSW_SP_RIF_MAX 800
80 static inline u16 mlxsw_sp_pfc_delay_get(int mtu, u16 delay)
82 delay = MLXSW_SP_BYTES_TO_CELLS(DIV_ROUND_UP(delay, BITS_PER_BYTE));
83 return MLXSW_SP_CELL_FACTOR * delay + MLXSW_SP_BYTES_TO_CELLS(mtu);
88 struct mlxsw_sp_upper {
89 struct net_device *dev;
90 unsigned int ref_count;
94 void (*leave)(struct mlxsw_sp_port *mlxsw_sp_vport);
95 struct list_head list;
96 unsigned int ref_count;
97 struct net_device *dev;
102 struct mlxsw_sp_rif {
103 struct net_device *dev;
107 struct mlxsw_sp_mid {
108 struct list_head list;
109 unsigned char addr[ETH_ALEN];
112 unsigned int ref_count;
115 static inline u16 mlxsw_sp_vfid_to_fid(u16 vfid)
117 return MLXSW_SP_VFID_BASE + vfid;
120 static inline u16 mlxsw_sp_fid_to_vfid(u16 fid)
122 return fid - MLXSW_SP_VFID_BASE;
125 static inline bool mlxsw_sp_fid_is_vfid(u16 fid)
127 return fid >= MLXSW_SP_VFID_BASE;
130 struct mlxsw_sp_sb_pr {
131 enum mlxsw_reg_sbpr_mode mode;
135 struct mlxsw_cp_sb_occ {
140 struct mlxsw_sp_sb_cm {
144 struct mlxsw_cp_sb_occ occ;
147 struct mlxsw_sp_sb_pm {
150 struct mlxsw_cp_sb_occ occ;
153 #define MLXSW_SP_SB_POOL_COUNT 4
154 #define MLXSW_SP_SB_TC_COUNT 8
157 struct mlxsw_sp_sb_pr prs[2][MLXSW_SP_SB_POOL_COUNT];
159 struct mlxsw_sp_sb_cm cms[2][MLXSW_SP_SB_TC_COUNT];
160 struct mlxsw_sp_sb_pm pms[2][MLXSW_SP_SB_POOL_COUNT];
161 } ports[MLXSW_PORT_MAX_PORTS];
164 #define MLXSW_SP_PREFIX_COUNT (sizeof(struct in6_addr) * BITS_PER_BYTE)
166 struct mlxsw_sp_prefix_usage {
167 DECLARE_BITMAP(b, MLXSW_SP_PREFIX_COUNT);
172 struct list_head list;
173 DECLARE_BITMAP(mapped, MLXSW_SP_VFID_PORT_MAX);
176 struct list_head list;
177 DECLARE_BITMAP(mapped, MLXSW_SP_VFID_BR_MAX);
180 struct list_head list;
181 DECLARE_BITMAP(mapped, MLXSW_SP_MID_MAX);
183 struct list_head fids; /* VLAN-aware bridge FIDs */
184 struct mlxsw_sp_rif *rifs[MLXSW_SP_RIF_MAX];
185 struct mlxsw_sp_port **ports;
186 struct mlxsw_core *core;
187 const struct mlxsw_bus_info *bus_info;
188 unsigned char base_mac[ETH_ALEN];
190 struct delayed_work dw;
191 #define MLXSW_SP_DEFAULT_LEARNING_INTERVAL 100
192 unsigned int interval; /* ms */
194 #define MLXSW_SP_MIN_AGEING_TIME 10
195 #define MLXSW_SP_MAX_AGEING_TIME 1000000
196 #define MLXSW_SP_DEFAULT_AGEING_TIME 300
198 struct mlxsw_sp_upper master_bridge;
199 struct mlxsw_sp_upper lags[MLXSW_SP_LAG_MAX];
200 u8 port_to_module[MLXSW_PORT_MAX_PORTS];
201 struct mlxsw_sp_sb sb;
204 static inline struct mlxsw_sp_upper *
205 mlxsw_sp_lag_get(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
207 return &mlxsw_sp->lags[lag_id];
210 struct mlxsw_sp_port_pcpu_stats {
215 struct u64_stats_sync syncp;
219 struct mlxsw_sp_port {
220 struct mlxsw_core_port core_port; /* must be first */
221 struct net_device *dev;
222 struct mlxsw_sp_port_pcpu_stats __percpu *pcpu_stats;
223 struct mlxsw_sp *mlxsw_sp;
235 struct list_head list;
236 struct mlxsw_sp_fid *f;
244 struct ieee_ets *ets;
245 struct ieee_maxrate *maxrate;
246 struct ieee_pfc *pfc;
253 /* 802.1Q bridge VLANs */
254 unsigned long *active_vlans;
255 unsigned long *untagged_vlans;
256 /* VLAN interfaces */
257 struct list_head vports_list;
261 mlxsw_sp_port_is_pause_en(const struct mlxsw_sp_port *mlxsw_sp_port)
263 return mlxsw_sp_port->link.tx_pause || mlxsw_sp_port->link.rx_pause;
266 static inline struct mlxsw_sp_port *
267 mlxsw_sp_port_lagged_get(struct mlxsw_sp *mlxsw_sp, u16 lag_id, u8 port_index)
269 struct mlxsw_sp_port *mlxsw_sp_port;
272 local_port = mlxsw_core_lag_mapping_get(mlxsw_sp->core,
274 mlxsw_sp_port = mlxsw_sp->ports[local_port];
275 return mlxsw_sp_port && mlxsw_sp_port->lagged ? mlxsw_sp_port : NULL;
279 mlxsw_sp_vport_vid_get(const struct mlxsw_sp_port *mlxsw_sp_vport)
281 return mlxsw_sp_vport->vport.vid;
285 mlxsw_sp_port_is_vport(const struct mlxsw_sp_port *mlxsw_sp_port)
287 u16 vid = mlxsw_sp_vport_vid_get(mlxsw_sp_port);
292 static inline void mlxsw_sp_vport_fid_set(struct mlxsw_sp_port *mlxsw_sp_vport,
293 struct mlxsw_sp_fid *f)
295 mlxsw_sp_vport->vport.f = f;
298 static inline struct mlxsw_sp_fid *
299 mlxsw_sp_vport_fid_get(const struct mlxsw_sp_port *mlxsw_sp_vport)
301 return mlxsw_sp_vport->vport.f;
304 static inline struct net_device *
305 mlxsw_sp_vport_br_get(const struct mlxsw_sp_port *mlxsw_sp_vport)
307 struct mlxsw_sp_fid *f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
309 return f ? f->dev : NULL;
312 static inline struct mlxsw_sp_port *
313 mlxsw_sp_port_vport_find(const struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
315 struct mlxsw_sp_port *mlxsw_sp_vport;
317 list_for_each_entry(mlxsw_sp_vport, &mlxsw_sp_port->vports_list,
319 if (mlxsw_sp_vport_vid_get(mlxsw_sp_vport) == vid)
320 return mlxsw_sp_vport;
326 static inline struct mlxsw_sp_port *
327 mlxsw_sp_port_vport_find_by_fid(const struct mlxsw_sp_port *mlxsw_sp_port,
330 struct mlxsw_sp_port *mlxsw_sp_vport;
332 list_for_each_entry(mlxsw_sp_vport, &mlxsw_sp_port->vports_list,
334 struct mlxsw_sp_fid *f = mlxsw_sp_vport_fid_get(mlxsw_sp_vport);
336 if (f && f->fid == fid)
337 return mlxsw_sp_vport;
343 static inline struct mlxsw_sp_rif *
344 mlxsw_sp_rif_find_by_dev(const struct mlxsw_sp *mlxsw_sp,
345 const struct net_device *dev)
349 for (i = 0; i < MLXSW_SP_RIF_MAX; i++)
350 if (mlxsw_sp->rifs[i] && mlxsw_sp->rifs[i]->dev == dev)
351 return mlxsw_sp->rifs[i];
356 enum mlxsw_sp_flood_table {
357 MLXSW_SP_FLOOD_TABLE_UC,
358 MLXSW_SP_FLOOD_TABLE_BM,
361 int mlxsw_sp_buffers_init(struct mlxsw_sp *mlxsw_sp);
362 void mlxsw_sp_buffers_fini(struct mlxsw_sp *mlxsw_sp);
363 int mlxsw_sp_port_buffers_init(struct mlxsw_sp_port *mlxsw_sp_port);
364 int mlxsw_sp_sb_pool_get(struct mlxsw_core *mlxsw_core,
365 unsigned int sb_index, u16 pool_index,
366 struct devlink_sb_pool_info *pool_info);
367 int mlxsw_sp_sb_pool_set(struct mlxsw_core *mlxsw_core,
368 unsigned int sb_index, u16 pool_index, u32 size,
369 enum devlink_sb_threshold_type threshold_type);
370 int mlxsw_sp_sb_port_pool_get(struct mlxsw_core_port *mlxsw_core_port,
371 unsigned int sb_index, u16 pool_index,
373 int mlxsw_sp_sb_port_pool_set(struct mlxsw_core_port *mlxsw_core_port,
374 unsigned int sb_index, u16 pool_index,
376 int mlxsw_sp_sb_tc_pool_bind_get(struct mlxsw_core_port *mlxsw_core_port,
377 unsigned int sb_index, u16 tc_index,
378 enum devlink_sb_pool_type pool_type,
379 u16 *p_pool_index, u32 *p_threshold);
380 int mlxsw_sp_sb_tc_pool_bind_set(struct mlxsw_core_port *mlxsw_core_port,
381 unsigned int sb_index, u16 tc_index,
382 enum devlink_sb_pool_type pool_type,
383 u16 pool_index, u32 threshold);
384 int mlxsw_sp_sb_occ_snapshot(struct mlxsw_core *mlxsw_core,
385 unsigned int sb_index);
386 int mlxsw_sp_sb_occ_max_clear(struct mlxsw_core *mlxsw_core,
387 unsigned int sb_index);
388 int mlxsw_sp_sb_occ_port_pool_get(struct mlxsw_core_port *mlxsw_core_port,
389 unsigned int sb_index, u16 pool_index,
390 u32 *p_cur, u32 *p_max);
391 int mlxsw_sp_sb_occ_tc_port_bind_get(struct mlxsw_core_port *mlxsw_core_port,
392 unsigned int sb_index, u16 tc_index,
393 enum devlink_sb_pool_type pool_type,
394 u32 *p_cur, u32 *p_max);
396 int mlxsw_sp_switchdev_init(struct mlxsw_sp *mlxsw_sp);
397 void mlxsw_sp_switchdev_fini(struct mlxsw_sp *mlxsw_sp);
398 int mlxsw_sp_port_vlan_init(struct mlxsw_sp_port *mlxsw_sp_port);
399 void mlxsw_sp_port_switchdev_init(struct mlxsw_sp_port *mlxsw_sp_port);
400 void mlxsw_sp_port_switchdev_fini(struct mlxsw_sp_port *mlxsw_sp_port);
401 int mlxsw_sp_port_vid_to_fid_set(struct mlxsw_sp_port *mlxsw_sp_port,
402 enum mlxsw_reg_svfa_mt mt, bool valid, u16 fid,
404 int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
405 u16 vid_end, bool is_member, bool untagged);
406 int mlxsw_sp_port_add_vid(struct net_device *dev, __be16 __always_unused proto,
408 int mlxsw_sp_vport_flood_set(struct mlxsw_sp_port *mlxsw_sp_vport, u16 fid,
410 void mlxsw_sp_port_active_vlans_del(struct mlxsw_sp_port *mlxsw_sp_port);
411 int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid);
412 int mlxsw_sp_port_fdb_flush(struct mlxsw_sp_port *mlxsw_sp_port, u16 fid);
413 int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
414 enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
415 bool dwrr, u8 dwrr_weight);
416 int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
417 u8 switch_prio, u8 tclass);
418 int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
419 u8 *prio_tc, bool pause_en,
420 struct ieee_pfc *my_pfc);
421 int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
422 enum mlxsw_reg_qeec_hr hr, u8 index,
423 u8 next_index, u32 maxrate);
425 #ifdef CONFIG_MLXSW_SPECTRUM_DCB
427 int mlxsw_sp_port_dcb_init(struct mlxsw_sp_port *mlxsw_sp_port);
428 void mlxsw_sp_port_dcb_fini(struct mlxsw_sp_port *mlxsw_sp_port);
432 static inline int mlxsw_sp_port_dcb_init(struct mlxsw_sp_port *mlxsw_sp_port)
437 static inline void mlxsw_sp_port_dcb_fini(struct mlxsw_sp_port *mlxsw_sp_port)
442 int mlxsw_sp_router_init(struct mlxsw_sp *mlxsw_sp);
443 void mlxsw_sp_router_fini(struct mlxsw_sp *mlxsw_sp);