drivers/net/ethernet/neterion/s2io.c

   1 /************************************************************************
   2  * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
   3  * Copyright(c) 2002-2010 Exar Corp.
   4  *
   5  * This software may be used and distributed according to the terms of
   6  * the GNU General Public License (GPL), incorporated herein by reference.
   7  * Drivers based on or derived from this code fall under the GPL and must
   8  * retain the authorship, copyright and license notice.  This file is not
   9  * a complete program and may only be used when the entire operating
  10  * system is licensed under the GPL.
  11  * See the file COPYING in this distribution for more information.
  12  *
  13  * Credits:
  14  * Jeff Garzik          : For pointing out the improper error condition
  15  *                        check in the s2io_xmit routine and also some
  16  *                        issues in the Tx watch dog function. Also for
  17  *                        patiently answering all those innumerable
  18  *                        questions regaring the 2.6 porting issues.
  19  * Stephen Hemminger    : Providing proper 2.6 porting mechanism for some
  20  *                        macros available only in 2.6 Kernel.
  21  * Francois Romieu      : For pointing out all code part that were
  22  *                        deprecated and also styling related comments.
  23  * Grant Grundler       : For helping me get rid of some Architecture
  24  *                        dependent code.
  25  * Christopher Hellwig  : Some more 2.6 specific issues in the driver.
  26  *
  27  * The module loadable parameters that are supported by the driver and a brief
  28  * explanation of all the variables.
  29  *
  30  * rx_ring_num : This can be used to program the number of receive rings used
  31  * in the driver.
  32  * rx_ring_sz: This defines the number of receive blocks each ring can have.
  33  *     This is also an array of size 8.
  34  * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
  35  *              values are 1, 2.
  36  * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
  37  * tx_fifo_len: This too is an array of 8. Each element defines the number of
  38  * Tx descriptors that can be associated with each corresponding FIFO.
  39  * intr_type: This defines the type of interrupt. The values can be 0(INTA),
  40  *     2(MSI_X). Default value is '2(MSI_X)'
  41  * lro_max_pkts: This parameter defines maximum number of packets can be
  42  *     aggregated as a single large packet
  43  * napi: This parameter used to enable/disable NAPI (polling Rx)
  44  *     Possible values '1' for enable and '0' for disable. Default is '1'
  45  * ufo: This parameter used to enable/disable UDP Fragmentation Offload(UFO)
  46  *      Possible values '1' for enable and '0' for disable. Default is '0'
  47  * vlan_tag_strip: This can be used to enable or disable vlan stripping.
  48  *                 Possible values '1' for enable , '0' for disable.
  49  *                 Default is '2' - which means disable in promisc mode
  50  *                 and enable in non-promiscuous mode.
  51  * multiq: This parameter used to enable/disable MULTIQUEUE support.
  52  *      Possible values '1' for enable and '0' for disable. Default is '0'
  53  ************************************************************************/
  54
  55 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  56
  57 #include <linux/module.h>
  58 #include <linux/types.h>
  59 #include <linux/errno.h>
  60 #include <linux/ioport.h>
  61 #include <linux/pci.h>
  62 #include <linux/dma-mapping.h>
  63 #include <linux/kernel.h>
  64 #include <linux/netdevice.h>
  65 #include <linux/etherdevice.h>
  66 #include <linux/mdio.h>
  67 #include <linux/skbuff.h>
  68 #include <linux/init.h>
  69 #include <linux/delay.h>
  70 #include <linux/stddef.h>
  71 #include <linux/ioctl.h>
  72 #include <linux/timex.h>
  73 #include <linux/ethtool.h>
  74 #include <linux/workqueue.h>
  75 #include <linux/if_vlan.h>
  76 #include <linux/ip.h>
  77 #include <linux/tcp.h>
  78 #include <linux/uaccess.h>
  79 #include <linux/io.h>
  80 #include <linux/slab.h>
  81 #include <linux/prefetch.h>
  82 #include <net/tcp.h>
  83 #include <net/checksum.h>
  84
  85 #include <asm/div64.h>
  86 #include <asm/irq.h>
  87
  88 /* local include */
  89 #include "s2io.h"
  90 #include "s2io-regs.h"
  91
  92 #define DRV_VERSION "2.0.26.28"
  93
  94 /* S2io Driver name & version. */
  95 static const char s2io_driver_name[] = "Neterion";
  96 static const char s2io_driver_version[] = DRV_VERSION;
  97
  98 static const int rxd_size[2] = {32, 48};
  99 static const int rxd_count[2] = {127, 85};
 100
 101 static inline int RXD_IS_UP2DT(struct RxD_t *rxdp)
 102 {
 103         int ret;
 104
 105         ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
 106                (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
 107
 108         return ret;
 109 }
 110
 111 /*
 112  * Cards with following subsystem_id have a link state indication
 113  * problem, 600B, 600C, 600D, 640B, 640C and 640D.
 114  * macro below identifies these cards given the subsystem_id.
 115  */
 116 #define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid)              \
 117         (dev_type == XFRAME_I_DEVICE) ?                                 \
 118         ((((subid >= 0x600B) && (subid <= 0x600D)) ||                   \
 119           ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
 120
 121 #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
 122                                       ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
 123
 124 static inline int is_s2io_card_up(const struct s2io_nic *sp)
 125 {
 126         return test_bit(__S2IO_STATE_CARD_UP, &sp->state);
 127 }
 128
 129 /* Ethtool related variables and Macros. */
 130 static const char s2io_gstrings[][ETH_GSTRING_LEN] = {
 131         "Register test\t(offline)",
 132         "Eeprom test\t(offline)",
 133         "Link test\t(online)",
 134         "RLDRAM test\t(offline)",
 135         "BIST Test\t(offline)"
 136 };
 137
 138 static const char ethtool_xena_stats_keys[][ETH_GSTRING_LEN] = {
 139         {"tmac_frms"},
 140         {"tmac_data_octets"},
 141         {"tmac_drop_frms"},
 142         {"tmac_mcst_frms"},
 143         {"tmac_bcst_frms"},
 144         {"tmac_pause_ctrl_frms"},
 145         {"tmac_ttl_octets"},
 146         {"tmac_ucst_frms"},
 147         {"tmac_nucst_frms"},
 148         {"tmac_any_err_frms"},
 149         {"tmac_ttl_less_fb_octets"},
 150         {"tmac_vld_ip_octets"},
 151         {"tmac_vld_ip"},
 152         {"tmac_drop_ip"},
 153         {"tmac_icmp"},
 154         {"tmac_rst_tcp"},
 155         {"tmac_tcp"},
 156         {"tmac_udp"},
 157         {"rmac_vld_frms"},
 158         {"rmac_data_octets"},
 159         {"rmac_fcs_err_frms"},
 160         {"rmac_drop_frms"},
 161         {"rmac_vld_mcst_frms"},
 162         {"rmac_vld_bcst_frms"},
 163         {"rmac_in_rng_len_err_frms"},
 164         {"rmac_out_rng_len_err_frms"},
 165         {"rmac_long_frms"},
 166         {"rmac_pause_ctrl_frms"},
 167         {"rmac_unsup_ctrl_frms"},
 168         {"rmac_ttl_octets"},
 169         {"rmac_accepted_ucst_frms"},
 170         {"rmac_accepted_nucst_frms"},
 171         {"rmac_discarded_frms"},
 172         {"rmac_drop_events"},
 173         {"rmac_ttl_less_fb_octets"},
 174         {"rmac_ttl_frms"},
 175         {"rmac_usized_frms"},
 176         {"rmac_osized_frms"},
 177         {"rmac_frag_frms"},
 178         {"rmac_jabber_frms"},
 179         {"rmac_ttl_64_frms"},
 180         {"rmac_ttl_65_127_frms"},
 181         {"rmac_ttl_128_255_frms"},
 182         {"rmac_ttl_256_511_frms"},
 183         {"rmac_ttl_512_1023_frms"},
 184         {"rmac_ttl_1024_1518_frms"},
 185         {"rmac_ip"},
 186         {"rmac_ip_octets"},
 187         {"rmac_hdr_err_ip"},
 188         {"rmac_drop_ip"},
 189         {"rmac_icmp"},
 190         {"rmac_tcp"},
 191         {"rmac_udp"},
 192         {"rmac_err_drp_udp"},
 193         {"rmac_xgmii_err_sym"},
 194         {"rmac_frms_q0"},
 195         {"rmac_frms_q1"},
 196         {"rmac_frms_q2"},
 197         {"rmac_frms_q3"},
 198         {"rmac_frms_q4"},
 199         {"rmac_frms_q5"},
 200         {"rmac_frms_q6"},
 201         {"rmac_frms_q7"},
 202         {"rmac_full_q0"},
 203         {"rmac_full_q1"},
 204         {"rmac_full_q2"},
 205         {"rmac_full_q3"},
 206         {"rmac_full_q4"},
 207         {"rmac_full_q5"},
 208         {"rmac_full_q6"},
 209         {"rmac_full_q7"},
 210         {"rmac_pause_cnt"},
 211         {"rmac_xgmii_data_err_cnt"},
 212         {"rmac_xgmii_ctrl_err_cnt"},
 213         {"rmac_accepted_ip"},
 214         {"rmac_err_tcp"},
 215         {"rd_req_cnt"},
 216         {"new_rd_req_cnt"},
 217         {"new_rd_req_rtry_cnt"},
 218         {"rd_rtry_cnt"},
 219         {"wr_rtry_rd_ack_cnt"},
 220         {"wr_req_cnt"},
 221         {"new_wr_req_cnt"},
 222         {"new_wr_req_rtry_cnt"},
 223         {"wr_rtry_cnt"},
 224         {"wr_disc_cnt"},
 225         {"rd_rtry_wr_ack_cnt"},
 226         {"txp_wr_cnt"},
 227         {"txd_rd_cnt"},
 228         {"txd_wr_cnt"},
 229         {"rxd_rd_cnt"},
 230         {"rxd_wr_cnt"},
 231         {"txf_rd_cnt"},
 232         {"rxf_wr_cnt"}
 233 };
 234
 235 static const char ethtool_enhanced_stats_keys[][ETH_GSTRING_LEN] = {
 236         {"rmac_ttl_1519_4095_frms"},
 237         {"rmac_ttl_4096_8191_frms"},
 238         {"rmac_ttl_8192_max_frms"},
 239         {"rmac_ttl_gt_max_frms"},
 240         {"rmac_osized_alt_frms"},
 241         {"rmac_jabber_alt_frms"},
 242         {"rmac_gt_max_alt_frms"},
 243         {"rmac_vlan_frms"},
 244         {"rmac_len_discard"},
 245         {"rmac_fcs_discard"},
 246         {"rmac_pf_discard"},
 247         {"rmac_da_discard"},
 248         {"rmac_red_discard"},
 249         {"rmac_rts_discard"},
 250         {"rmac_ingm_full_discard"},
 251         {"link_fault_cnt"}
 252 };
 253
 254 static const char ethtool_driver_stats_keys[][ETH_GSTRING_LEN] = {
 255         {"\n DRIVER STATISTICS"},
 256         {"single_bit_ecc_errs"},
 257         {"double_bit_ecc_errs"},
 258         {"parity_err_cnt"},
 259         {"serious_err_cnt"},
 260         {"soft_reset_cnt"},
 261         {"fifo_full_cnt"},
 262         {"ring_0_full_cnt"},
 263         {"ring_1_full_cnt"},
 264         {"ring_2_full_cnt"},
 265         {"ring_3_full_cnt"},
 266         {"ring_4_full_cnt"},
 267         {"ring_5_full_cnt"},
 268         {"ring_6_full_cnt"},
 269         {"ring_7_full_cnt"},
 270         {"alarm_transceiver_temp_high"},
 271         {"alarm_transceiver_temp_low"},
 272         {"alarm_laser_bias_current_high"},
 273         {"alarm_laser_bias_current_low"},
 274         {"alarm_laser_output_power_high"},
 275         {"alarm_laser_output_power_low"},
 276         {"warn_transceiver_temp_high"},
 277         {"warn_transceiver_temp_low"},
 278         {"warn_laser_bias_current_high"},
 279         {"warn_laser_bias_current_low"},
 280         {"warn_laser_output_power_high"},
 281         {"warn_laser_output_power_low"},
 282         {"lro_aggregated_pkts"},
 283         {"lro_flush_both_count"},
 284         {"lro_out_of_sequence_pkts"},
 285         {"lro_flush_due_to_max_pkts"},
 286         {"lro_avg_aggr_pkts"},
 287         {"mem_alloc_fail_cnt"},
 288         {"pci_map_fail_cnt"},
 289         {"watchdog_timer_cnt"},
 290         {"mem_allocated"},
 291         {"mem_freed"},
 292         {"link_up_cnt"},
 293         {"link_down_cnt"},
 294         {"link_up_time"},
 295         {"link_down_time"},
 296         {"tx_tcode_buf_abort_cnt"},
 297         {"tx_tcode_desc_abort_cnt"},
 298         {"tx_tcode_parity_err_cnt"},
 299         {"tx_tcode_link_loss_cnt"},
 300         {"tx_tcode_list_proc_err_cnt"},
 301         {"rx_tcode_parity_err_cnt"},
 302         {"rx_tcode_abort_cnt"},
 303         {"rx_tcode_parity_abort_cnt"},
 304         {"rx_tcode_rda_fail_cnt"},
 305         {"rx_tcode_unkn_prot_cnt"},
 306         {"rx_tcode_fcs_err_cnt"},
 307         {"rx_tcode_buf_size_err_cnt"},
 308         {"rx_tcode_rxd_corrupt_cnt"},
 309         {"rx_tcode_unkn_err_cnt"},
 310         {"tda_err_cnt"},
 311         {"pfc_err_cnt"},
 312         {"pcc_err_cnt"},
 313         {"tti_err_cnt"},
 314         {"tpa_err_cnt"},
 315         {"sm_err_cnt"},
 316         {"lso_err_cnt"},
 317         {"mac_tmac_err_cnt"},
 318         {"mac_rmac_err_cnt"},
 319         {"xgxs_txgxs_err_cnt"},
 320         {"xgxs_rxgxs_err_cnt"},
 321         {"rc_err_cnt"},
 322         {"prc_pcix_err_cnt"},
 323         {"rpa_err_cnt"},
 324         {"rda_err_cnt"},
 325         {"rti_err_cnt"},
 326         {"mc_err_cnt"}
 327 };
 328
 329 #define S2IO_XENA_STAT_LEN      ARRAY_SIZE(ethtool_xena_stats_keys)
 330 #define S2IO_ENHANCED_STAT_LEN  ARRAY_SIZE(ethtool_enhanced_stats_keys)
 331 #define S2IO_DRIVER_STAT_LEN    ARRAY_SIZE(ethtool_driver_stats_keys)
 332
 333 #define XFRAME_I_STAT_LEN (S2IO_XENA_STAT_LEN + S2IO_DRIVER_STAT_LEN)
 334 #define XFRAME_II_STAT_LEN (XFRAME_I_STAT_LEN + S2IO_ENHANCED_STAT_LEN)
 335
 336 #define XFRAME_I_STAT_STRINGS_LEN (XFRAME_I_STAT_LEN * ETH_GSTRING_LEN)
 337 #define XFRAME_II_STAT_STRINGS_LEN (XFRAME_II_STAT_LEN * ETH_GSTRING_LEN)
 338
 339 #define S2IO_TEST_LEN   ARRAY_SIZE(s2io_gstrings)
 340 #define S2IO_STRINGS_LEN        (S2IO_TEST_LEN * ETH_GSTRING_LEN)
 341
 342 #define S2IO_TIMER_CONF(timer, handle, arg, exp)        \
 343         init_timer(&timer);                             \
 344         timer.function = handle;                        \
 345         timer.data = (unsigned long)arg;                \
 346         mod_timer(&timer, (jiffies + exp))              \
 347
 348 /* copy mac addr to def_mac_addr array */
 349 static void do_s2io_copy_mac_addr(struct s2io_nic *sp, int offset, u64 mac_addr)
 350 {
 351         sp->def_mac_addr[offset].mac_addr[5] = (u8) (mac_addr);
 352         sp->def_mac_addr[offset].mac_addr[4] = (u8) (mac_addr >> 8);
 353         sp->def_mac_addr[offset].mac_addr[3] = (u8) (mac_addr >> 16);
 354         sp->def_mac_addr[offset].mac_addr[2] = (u8) (mac_addr >> 24);
 355         sp->def_mac_addr[offset].mac_addr[1] = (u8) (mac_addr >> 32);
 356         sp->def_mac_addr[offset].mac_addr[0] = (u8) (mac_addr >> 40);
 357 }
 358
 359 /*
 360  * Constants to be programmed into the Xena's registers, to configure
 361  * the XAUI.
 362  */
 363
 364 #define END_SIGN        0x0
 365 static const u64 herc_act_dtx_cfg[] = {
 366         /* Set address */
 367         0x8000051536750000ULL, 0x80000515367500E0ULL,
 368         /* Write data */
 369         0x8000051536750004ULL, 0x80000515367500E4ULL,
 370         /* Set address */
 371         0x80010515003F0000ULL, 0x80010515003F00E0ULL,
 372         /* Write data */
 373         0x80010515003F0004ULL, 0x80010515003F00E4ULL,
 374         /* Set address */
 375         0x801205150D440000ULL, 0x801205150D4400E0ULL,
 376         /* Write data */
 377         0x801205150D440004ULL, 0x801205150D4400E4ULL,
 378         /* Set address */
 379         0x80020515F2100000ULL, 0x80020515F21000E0ULL,
 380         /* Write data */
 381         0x80020515F2100004ULL, 0x80020515F21000E4ULL,
 382         /* Done */
 383         END_SIGN
 384 };
 385
 386 static const u64 xena_dtx_cfg[] = {
 387         /* Set address */
 388         0x8000051500000000ULL, 0x80000515000000E0ULL,
 389         /* Write data */
 390         0x80000515D9350004ULL, 0x80000515D93500E4ULL,
 391         /* Set address */
 392         0x8001051500000000ULL, 0x80010515000000E0ULL,
 393         /* Write data */
 394         0x80010515001E0004ULL, 0x80010515001E00E4ULL,
 395         /* Set address */
 396         0x8002051500000000ULL, 0x80020515000000E0ULL,
 397         /* Write data */
 398         0x80020515F2100004ULL, 0x80020515F21000E4ULL,
 399         END_SIGN
 400 };
 401
 402 /*
 403  * Constants for Fixing the MacAddress problem seen mostly on
 404  * Alpha machines.
 405  */
 406 static const u64 fix_mac[] = {
 407         0x0060000000000000ULL, 0x0060600000000000ULL,
 408         0x0040600000000000ULL, 0x0000600000000000ULL,
 409         0x0020600000000000ULL, 0x0060600000000000ULL,
 410         0x0020600000000000ULL, 0x0060600000000000ULL,
 411         0x0020600000000000ULL, 0x0060600000000000ULL,
 412         0x0020600000000000ULL, 0x0060600000000000ULL,
 413         0x0020600000000000ULL, 0x0060600000000000ULL,
 414         0x0020600000000000ULL, 0x0060600000000000ULL,
 415         0x0020600000000000ULL, 0x0060600000000000ULL,
 416         0x0020600000000000ULL, 0x0060600000000000ULL,
 417         0x0020600000000000ULL, 0x0060600000000000ULL,
 418         0x0020600000000000ULL, 0x0060600000000000ULL,
 419         0x0020600000000000ULL, 0x0000600000000000ULL,
 420         0x0040600000000000ULL, 0x0060600000000000ULL,
 421         END_SIGN
 422 };
 423
 424 MODULE_LICENSE("GPL");
 425 MODULE_VERSION(DRV_VERSION);
 426
 427
 428 /* Module Loadable parameters. */
 429 S2IO_PARM_INT(tx_fifo_num, FIFO_DEFAULT_NUM);
 430 S2IO_PARM_INT(rx_ring_num, 1);
 431 S2IO_PARM_INT(multiq, 0);
 432 S2IO_PARM_INT(rx_ring_mode, 1);
 433 S2IO_PARM_INT(use_continuous_tx_intrs, 1);
 434 S2IO_PARM_INT(rmac_pause_time, 0x100);
 435 S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
 436 S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
 437 S2IO_PARM_INT(shared_splits, 0);
 438 S2IO_PARM_INT(tmac_util_period, 5);
 439 S2IO_PARM_INT(rmac_util_period, 5);
 440 S2IO_PARM_INT(l3l4hdr_size, 128);
 441 /* 0 is no steering, 1 is Priority steering, 2 is Default steering */
 442 S2IO_PARM_INT(tx_steering_type, TX_DEFAULT_STEERING);
 443 /* Frequency of Rx desc syncs expressed as power of 2 */
 444 S2IO_PARM_INT(rxsync_frequency, 3);
 445 /* Interrupt type. Values can be 0(INTA), 2(MSI_X) */
 446 S2IO_PARM_INT(intr_type, 2);
 447 /* Large receive offload feature */
 448
 449 /* Max pkts to be aggregated by LRO at one time. If not specified,
 450  * aggregation happens until we hit max IP pkt size(64K)
 451  */
 452 S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
 453 S2IO_PARM_INT(indicate_max_pkts, 0);
 454
 455 S2IO_PARM_INT(napi, 1);
 456 S2IO_PARM_INT(ufo, 0);
 457 S2IO_PARM_INT(vlan_tag_strip, NO_STRIP_IN_PROMISC);
 458
 459 static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
 460 {DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
 461 static unsigned int rx_ring_sz[MAX_RX_RINGS] =
 462 {[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
 463 static unsigned int rts_frm_len[MAX_RX_RINGS] =
 464 {[0 ...(MAX_RX_RINGS - 1)] = 0 };
 465
 466 module_param_array(tx_fifo_len, uint, NULL, 0);
 467 module_param_array(rx_ring_sz, uint, NULL, 0);
 468 module_param_array(rts_frm_len, uint, NULL, 0);
 469
 470 /*
 471  * S2IO device table.
 472  * This table lists all the devices that this driver supports.
 473  */
 474 static const struct pci_device_id s2io_tbl[] = {
 475         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
 476          PCI_ANY_ID, PCI_ANY_ID},
 477         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
 478          PCI_ANY_ID, PCI_ANY_ID},
 479         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
 480          PCI_ANY_ID, PCI_ANY_ID},
 481         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
 482          PCI_ANY_ID, PCI_ANY_ID},
 483         {0,}
 484 };
 485
 486 MODULE_DEVICE_TABLE(pci, s2io_tbl);
 487
 488 static const struct pci_error_handlers s2io_err_handler = {
 489         .error_detected = s2io_io_error_detected,
 490         .slot_reset = s2io_io_slot_reset,
 491         .resume = s2io_io_resume,
 492 };
 493
 494 static struct pci_driver s2io_driver = {
 495         .name = "S2IO",
 496         .id_table = s2io_tbl,
 497         .probe = s2io_init_nic,
 498         .remove = s2io_rem_nic,
 499         .err_handler = &s2io_err_handler,
 500 };
 501
 502 /* A simplifier macro used both by init and free shared_mem Fns(). */
 503 #define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
 504
 505 /* netqueue manipulation helper functions */
 506 static inline void s2io_stop_all_tx_queue(struct s2io_nic *sp)
 507 {
 508         if (!sp->config.multiq) {
 509                 int i;
 510
 511                 for (i = 0; i < sp->config.tx_fifo_num; i++)
 512                         sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_STOP;
 513         }
 514         netif_tx_stop_all_queues(sp->dev);
 515 }
 516
 517 static inline void s2io_stop_tx_queue(struct s2io_nic *sp, int fifo_no)
 518 {
 519         if (!sp->config.multiq)
 520                 sp->mac_control.fifos[fifo_no].queue_state =
 521                         FIFO_QUEUE_STOP;
 522
 523         netif_tx_stop_all_queues(sp->dev);
 524 }
 525
 526 static inline void s2io_start_all_tx_queue(struct s2io_nic *sp)
 527 {
 528         if (!sp->config.multiq) {
 529                 int i;
 530
 531                 for (i = 0; i < sp->config.tx_fifo_num; i++)
 532                         sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
 533         }
 534         netif_tx_start_all_queues(sp->dev);
 535 }
 536
 537 static inline void s2io_wake_all_tx_queue(struct s2io_nic *sp)
 538 {
 539         if (!sp->config.multiq) {
 540                 int i;
 541
 542                 for (i = 0; i < sp->config.tx_fifo_num; i++)
 543                         sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
 544         }
 545         netif_tx_wake_all_queues(sp->dev);
 546 }
 547
 548 static inline void s2io_wake_tx_queue(
 549         struct fifo_info *fifo, int cnt, u8 multiq)
 550 {
 551
 552         if (multiq) {
 553                 if (cnt && __netif_subqueue_stopped(fifo->dev, fifo->fifo_no))
 554                         netif_wake_subqueue(fifo->dev, fifo->fifo_no);
 555         } else if (cnt && (fifo->queue_state == FIFO_QUEUE_STOP)) {
 556                 if (netif_queue_stopped(fifo->dev)) {
 557                         fifo->queue_state = FIFO_QUEUE_START;
 558                         netif_wake_queue(fifo->dev);
 559                 }
 560         }
 561 }
 562
 563 /**
 564  * init_shared_mem - Allocation and Initialization of Memory
 565  * @nic: Device private variable.
 566  * Description: The function allocates all the memory areas shared
 567  * between the NIC and the driver. This includes Tx descriptors,
 568  * Rx descriptors and the statistics block.
 569  */
 570
 571 static int init_shared_mem(struct s2io_nic *nic)
 572 {
 573         u32 size;
 574         void *tmp_v_addr, *tmp_v_addr_next;
 575         dma_addr_t tmp_p_addr, tmp_p_addr_next;
 576         struct RxD_block *pre_rxd_blk = NULL;
 577         int i, j, blk_cnt;
 578         int lst_size, lst_per_page;
 579         struct net_device *dev = nic->dev;
 580         unsigned long tmp;
 581         struct buffAdd *ba;
 582         struct config_param *config = &nic->config;
 583         struct mac_info *mac_control = &nic->mac_control;
 584         unsigned long long mem_allocated = 0;
 585
 586         /* Allocation and initialization of TXDLs in FIFOs */
 587         size = 0;
 588         for (i = 0; i < config->tx_fifo_num; i++) {
 589                 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
 590
 591                 size += tx_cfg->fifo_len;
 592         }
 593         if (size > MAX_AVAILABLE_TXDS) {
 594                 DBG_PRINT(ERR_DBG,
 595                           "Too many TxDs requested: %d, max supported: %d\n",
 596                           size, MAX_AVAILABLE_TXDS);
 597                 return -EINVAL;
 598         }
 599
 600         size = 0;
 601         for (i = 0; i < config->tx_fifo_num; i++) {
 602                 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
 603
 604                 size = tx_cfg->fifo_len;
 605                 /*
 606                  * Legal values are from 2 to 8192
 607                  */
 608                 if (size < 2) {
 609                         DBG_PRINT(ERR_DBG, "Fifo %d: Invalid length (%d) - "
 610                                   "Valid lengths are 2 through 8192\n",
 611                                   i, size);
 612                         return -EINVAL;
 613                 }
 614         }
 615
 616         lst_size = (sizeof(struct TxD) * config->max_txds);
 617         lst_per_page = PAGE_SIZE / lst_size;
 618
 619         for (i = 0; i < config->tx_fifo_num; i++) {
 620                 struct fifo_info *fifo = &mac_control->fifos[i];
 621                 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
 622                 int fifo_len = tx_cfg->fifo_len;
 623                 int list_holder_size = fifo_len * sizeof(struct list_info_hold);
 624
 625                 fifo->list_info = kzalloc(list_holder_size, GFP_KERNEL);
 626                 if (!fifo->list_info) {
 627                         DBG_PRINT(INFO_DBG, "Malloc failed for list_info\n");
 628                         return -ENOMEM;
 629                 }
 630                 mem_allocated += list_holder_size;
 631         }
 632         for (i = 0; i < config->tx_fifo_num; i++) {
 633                 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
 634                                                 lst_per_page);
 635                 struct fifo_info *fifo = &mac_control->fifos[i];
 636                 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
 637
 638                 fifo->tx_curr_put_info.offset = 0;
 639                 fifo->tx_curr_put_info.fifo_len = tx_cfg->fifo_len - 1;
 640                 fifo->tx_curr_get_info.offset = 0;
 641                 fifo->tx_curr_get_info.fifo_len = tx_cfg->fifo_len - 1;
 642                 fifo->fifo_no = i;
 643                 fifo->nic = nic;
 644                 fifo->max_txds = MAX_SKB_FRAGS + 2;
 645                 fifo->dev = dev;
 646
 647                 for (j = 0; j < page_num; j++) {
 648                         int k = 0;
 649                         dma_addr_t tmp_p;
 650                         void *tmp_v;
 651                         tmp_v = pci_alloc_consistent(nic->pdev,
 652                                                      PAGE_SIZE, &tmp_p);
 653                         if (!tmp_v) {
 654                                 DBG_PRINT(INFO_DBG,
 655                                           "pci_alloc_consistent failed for TxDL\n");
 656                                 return -ENOMEM;
 657                         }
 658                         /* If we got a zero DMA address(can happen on
 659                          * certain platforms like PPC), reallocate.
 660                          * Store virtual address of page we don't want,
 661                          * to be freed later.
 662                          */
 663                         if (!tmp_p) {
 664                                 mac_control->zerodma_virt_addr = tmp_v;
 665                                 DBG_PRINT(INIT_DBG,
 666                                           "%s: Zero DMA address for TxDL. "
 667                                           "Virtual address %p\n",
 668                                           dev->name, tmp_v);
 669                                 tmp_v = pci_alloc_consistent(nic->pdev,
 670                                                              PAGE_SIZE, &tmp_p);
 671                                 if (!tmp_v) {
 672                                         DBG_PRINT(INFO_DBG,
 673                                                   "pci_alloc_consistent failed for TxDL\n");
 674                                         return -ENOMEM;
 675                                 }
 676                                 mem_allocated += PAGE_SIZE;
 677                         }
 678                         while (k < lst_per_page) {
 679                                 int l = (j * lst_per_page) + k;
 680                                 if (l == tx_cfg->fifo_len)
 681                                         break;
 682                                 fifo->list_info[l].list_virt_addr =
 683                                         tmp_v + (k * lst_size);
 684                                 fifo->list_info[l].list_phy_addr =
 685                                         tmp_p + (k * lst_size);
 686                                 k++;
 687                         }
 688                 }
 689         }
 690
 691         for (i = 0; i < config->tx_fifo_num; i++) {
 692                 struct fifo_info *fifo = &mac_control->fifos[i];
 693                 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
 694
 695                 size = tx_cfg->fifo_len;
 696                 fifo->ufo_in_band_v = kcalloc(size, sizeof(u64), GFP_KERNEL);
 697                 if (!fifo->ufo_in_band_v)
 698                         return -ENOMEM;
 699                 mem_allocated += (size * sizeof(u64));
 700         }
 701
 702         /* Allocation and initialization of RXDs in Rings */
 703         size = 0;
 704         for (i = 0; i < config->rx_ring_num; i++) {
 705                 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
 706                 struct ring_info *ring = &mac_control->rings[i];
 707
 708                 if (rx_cfg->num_rxd % (rxd_count[nic->rxd_mode] + 1)) {
 709                         DBG_PRINT(ERR_DBG, "%s: Ring%d RxD count is not a "
 710                                   "multiple of RxDs per Block\n",
 711                                   dev->name, i);
 712                         return FAILURE;
 713                 }
 714                 size += rx_cfg->num_rxd;
 715                 ring->block_count = rx_cfg->num_rxd /
 716                         (rxd_count[nic->rxd_mode] + 1);
 717                 ring->pkt_cnt = rx_cfg->num_rxd - ring->block_count;
 718         }
 719         if (nic->rxd_mode == RXD_MODE_1)
 720                 size = (size * (sizeof(struct RxD1)));
 721         else
 722                 size = (size * (sizeof(struct RxD3)));
 723
 724         for (i = 0; i < config->rx_ring_num; i++) {
 725                 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
 726                 struct ring_info *ring = &mac_control->rings[i];
 727
 728                 ring->rx_curr_get_info.block_index = 0;
 729                 ring->rx_curr_get_info.offset = 0;
 730                 ring->rx_curr_get_info.ring_len = rx_cfg->num_rxd - 1;
 731                 ring->rx_curr_put_info.block_index = 0;
 732                 ring->rx_curr_put_info.offset = 0;
 733                 ring->rx_curr_put_info.ring_len = rx_cfg->num_rxd - 1;
 734                 ring->nic = nic;
 735                 ring->ring_no = i;
 736
 737                 blk_cnt = rx_cfg->num_rxd / (rxd_count[nic->rxd_mode] + 1);
 738                 /*  Allocating all the Rx blocks */
 739                 for (j = 0; j < blk_cnt; j++) {
 740                         struct rx_block_info *rx_blocks;
 741                         int l;
 742
 743                         rx_blocks = &ring->rx_blocks[j];
 744                         size = SIZE_OF_BLOCK;   /* size is always page size */
 745                         tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
 746                                                           &tmp_p_addr);
 747                         if (tmp_v_addr == NULL) {
 748                                 /*
 749                                  * In case of failure, free_shared_mem()
 750                                  * is called, which should free any
 751                                  * memory that was alloced till the
 752                                  * failure happened.
 753                                  */
 754                                 rx_blocks->block_virt_addr = tmp_v_addr;
 755                                 return -ENOMEM;
 756                         }
 757                         mem_allocated += size;
 758                         memset(tmp_v_addr, 0, size);
 759
 760                         size = sizeof(struct rxd_info) *
 761                                 rxd_count[nic->rxd_mode];
 762                         rx_blocks->block_virt_addr = tmp_v_addr;
 763                         rx_blocks->block_dma_addr = tmp_p_addr;
 764                         rx_blocks->rxds = kmalloc(size,  GFP_KERNEL);
 765                         if (!rx_blocks->rxds)
 766                                 return -ENOMEM;
 767                         mem_allocated += size;
 768                         for (l = 0; l < rxd_count[nic->rxd_mode]; l++) {
 769                                 rx_blocks->rxds[l].virt_addr =
 770                                         rx_blocks->block_virt_addr +
 771                                         (rxd_size[nic->rxd_mode] * l);
 772                                 rx_blocks->rxds[l].dma_addr =
 773                                         rx_blocks->block_dma_addr +
 774                                         (rxd_size[nic->rxd_mode] * l);
 775                         }
 776                 }
 777                 /* Interlinking all Rx Blocks */
 778                 for (j = 0; j < blk_cnt; j++) {
 779                         int next = (j + 1) % blk_cnt;
 780                         tmp_v_addr = ring->rx_blocks[j].block_virt_addr;
 781                         tmp_v_addr_next = ring->rx_blocks[next].block_virt_addr;
 782                         tmp_p_addr = ring->rx_blocks[j].block_dma_addr;
 783                         tmp_p_addr_next = ring->rx_blocks[next].block_dma_addr;
 784
 785                         pre_rxd_blk = tmp_v_addr;
 786                         pre_rxd_blk->reserved_2_pNext_RxD_block =
 787                                 (unsigned long)tmp_v_addr_next;
 788                         pre_rxd_blk->pNext_RxD_Blk_physical =
 789                                 (u64)tmp_p_addr_next;
 790                 }
 791         }
 792         if (nic->rxd_mode == RXD_MODE_3B) {
 793                 /*
 794                  * Allocation of Storages for buffer addresses in 2BUFF mode
 795                  * and the buffers as well.
 796                  */
 797                 for (i = 0; i < config->rx_ring_num; i++) {
 798                         struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
 799                         struct ring_info *ring = &mac_control->rings[i];
 800
 801                         blk_cnt = rx_cfg->num_rxd /
 802                                 (rxd_count[nic->rxd_mode] + 1);
 803                         size = sizeof(struct buffAdd *) * blk_cnt;
 804                         ring->ba = kmalloc(size, GFP_KERNEL);
 805                         if (!ring->ba)
 806                                 return -ENOMEM;
 807                         mem_allocated += size;
 808                         for (j = 0; j < blk_cnt; j++) {
 809                                 int k = 0;
 810
 811                                 size = sizeof(struct buffAdd) *
 812                                         (rxd_count[nic->rxd_mode] + 1);
 813                                 ring->ba[j] = kmalloc(size, GFP_KERNEL);
 814                                 if (!ring->ba[j])
 815                                         return -ENOMEM;
 816                                 mem_allocated += size;
 817                                 while (k != rxd_count[nic->rxd_mode]) {
 818                                         ba = &ring->ba[j][k];
 819                                         size = BUF0_LEN + ALIGN_SIZE;
 820                                         ba->ba_0_org = kmalloc(size, GFP_KERNEL);
 821                                         if (!ba->ba_0_org)
 822                                                 return -ENOMEM;
 823                                         mem_allocated += size;
 824                                         tmp = (unsigned long)ba->ba_0_org;
 825                                         tmp += ALIGN_SIZE;
 826                                         tmp &= ~((unsigned long)ALIGN_SIZE);
 827                                         ba->ba_0 = (void *)tmp;
 828
 829                                         size = BUF1_LEN + ALIGN_SIZE;
 830                                         ba->ba_1_org = kmalloc(size, GFP_KERNEL);
 831                                         if (!ba->ba_1_org)
 832                                                 return -ENOMEM;
 833                                         mem_allocated += size;
 834                                         tmp = (unsigned long)ba->ba_1_org;
 835                                         tmp += ALIGN_SIZE;
 836                                         tmp &= ~((unsigned long)ALIGN_SIZE);
 837                                         ba->ba_1 = (void *)tmp;
 838                                         k++;
 839                                 }
 840                         }
 841                 }
 842         }
 843
 844         /* Allocation and initialization of Statistics block */
 845         size = sizeof(struct stat_block);
 846         mac_control->stats_mem =
 847                 pci_alloc_consistent(nic->pdev, size,
 848                                      &mac_control->stats_mem_phy);
 849
 850         if (!mac_control->stats_mem) {
 851                 /*
 852                  * In case of failure, free_shared_mem() is called, which
 853                  * should free any memory that was alloced till the
 854                  * failure happened.
 855                  */
 856                 return -ENOMEM;
 857         }
 858         mem_allocated += size;
 859         mac_control->stats_mem_sz = size;
 860
 861         tmp_v_addr = mac_control->stats_mem;
 862         mac_control->stats_info = tmp_v_addr;
 863         memset(tmp_v_addr, 0, size);
 864         DBG_PRINT(INIT_DBG, "%s: Ring Mem PHY: 0x%llx\n",
 865                 dev_name(&nic->pdev->dev), (unsigned long long)tmp_p_addr);
 866         mac_control->stats_info->sw_stat.mem_allocated += mem_allocated;
 867         return SUCCESS;
 868 }
 869
 870 /**
 871  * free_shared_mem - Free the allocated Memory
 872  * @nic:  Device private variable.
 873  * Description: This function is to free all memory locations allocated by
 874  * the init_shared_mem() function and return it to the kernel.
 875  */
 876
 877 static void free_shared_mem(struct s2io_nic *nic)
 878 {
 879         int i, j, blk_cnt, size;
 880         void *tmp_v_addr;
 881         dma_addr_t tmp_p_addr;
 882         int lst_size, lst_per_page;
 883         struct net_device *dev;
 884         int page_num = 0;
 885         struct config_param *config;
 886         struct mac_info *mac_control;
 887         struct stat_block *stats;
 888         struct swStat *swstats;
 889
 890         if (!nic)
 891                 return;
 892
 893         dev = nic->dev;
 894
 895         config = &nic->config;
 896         mac_control = &nic->mac_control;
 897         stats = mac_control->stats_info;
 898         swstats = &stats->sw_stat;
 899
 900         lst_size = sizeof(struct TxD) * config->max_txds;
 901         lst_per_page = PAGE_SIZE / lst_size;
 902
 903         for (i = 0; i < config->tx_fifo_num; i++) {
 904                 struct fifo_info *fifo = &mac_control->fifos[i];
 905                 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
 906
 907                 page_num = TXD_MEM_PAGE_CNT(tx_cfg->fifo_len, lst_per_page);
 908                 for (j = 0; j < page_num; j++) {
 909                         int mem_blks = (j * lst_per_page);
 910                         struct list_info_hold *fli;
 911
 912                         if (!fifo->list_info)
 913                                 return;
 914
 915                         fli = &fifo->list_info[mem_blks];
 916                         if (!fli->list_virt_addr)
 917                                 break;
 918                         pci_free_consistent(nic->pdev, PAGE_SIZE,
 919                                             fli->list_virt_addr,
 920                                             fli->list_phy_addr);
 921                         swstats->mem_freed += PAGE_SIZE;
 922                 }
 923                 /* If we got a zero DMA address during allocation,
 924                  * free the page now
 925                  */
 926                 if (mac_control->zerodma_virt_addr) {
 927                         pci_free_consistent(nic->pdev, PAGE_SIZE,
 928                                             mac_control->zerodma_virt_addr,
 929                                             (dma_addr_t)0);
 930                         DBG_PRINT(INIT_DBG,
 931                                   "%s: Freeing TxDL with zero DMA address. "
 932                                   "Virtual address %p\n",
 933                                   dev->name, mac_control->zerodma_virt_addr);
 934                         swstats->mem_freed += PAGE_SIZE;
 935                 }
 936                 kfree(fifo->list_info);
 937                 swstats->mem_freed += tx_cfg->fifo_len *
 938                         sizeof(struct list_info_hold);
 939         }
 940
 941         size = SIZE_OF_BLOCK;
 942         for (i = 0; i < config->rx_ring_num; i++) {
 943                 struct ring_info *ring = &mac_control->rings[i];
 944
 945                 blk_cnt = ring->block_count;
 946                 for (j = 0; j < blk_cnt; j++) {
 947                         tmp_v_addr = ring->rx_blocks[j].block_virt_addr;
 948                         tmp_p_addr = ring->rx_blocks[j].block_dma_addr;
 949                         if (tmp_v_addr == NULL)
 950                                 break;
 951                         pci_free_consistent(nic->pdev, size,
 952                                             tmp_v_addr, tmp_p_addr);
 953                         swstats->mem_freed += size;
 954                         kfree(ring->rx_blocks[j].rxds);
 955                         swstats->mem_freed += sizeof(struct rxd_info) *
 956                                 rxd_count[nic->rxd_mode];
 957                 }
 958         }
 959
 960         if (nic->rxd_mode == RXD_MODE_3B) {
 961                 /* Freeing buffer storage addresses in 2BUFF mode. */
 962                 for (i = 0; i < config->rx_ring_num; i++) {
 963                         struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
 964                         struct ring_info *ring = &mac_control->rings[i];
 965
 966                         blk_cnt = rx_cfg->num_rxd /
 967                                 (rxd_count[nic->rxd_mode] + 1);
 968                         for (j = 0; j < blk_cnt; j++) {
 969                                 int k = 0;
 970                                 if (!ring->ba[j])
 971                                         continue;
 972                                 while (k != rxd_count[nic->rxd_mode]) {
 973                                         struct buffAdd *ba = &ring->ba[j][k];
 974                                         kfree(ba->ba_0_org);
 975                                         swstats->mem_freed +=
 976                                                 BUF0_LEN + ALIGN_SIZE;
 977                                         kfree(ba->ba_1_org);
 978                                         swstats->mem_freed +=
 979                                                 BUF1_LEN + ALIGN_SIZE;
 980                                         k++;
 981                                 }
 982                                 kfree(ring->ba[j]);
 983                                 swstats->mem_freed += sizeof(struct buffAdd) *
 984                                         (rxd_count[nic->rxd_mode] + 1);
 985                         }
 986                         kfree(ring->ba);
 987                         swstats->mem_freed += sizeof(struct buffAdd *) *
 988                                 blk_cnt;
 989                 }
 990         }
 991
 992         for (i = 0; i < nic->config.tx_fifo_num; i++) {
 993                 struct fifo_info *fifo = &mac_control->fifos[i];
 994                 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
 995
 996                 if (fifo->ufo_in_band_v) {
 997                         swstats->mem_freed += tx_cfg->fifo_len *
 998                                 sizeof(u64);
 999                         kfree(fifo->ufo_in_band_v);
1000                 }
1001         }
1002
1003         if (mac_control->stats_mem) {
1004                 swstats->mem_freed += mac_control->stats_mem_sz;
1005                 pci_free_consistent(nic->pdev,
1006                                     mac_control->stats_mem_sz,
1007                                     mac_control->stats_mem,
1008                                     mac_control->stats_mem_phy);
1009         }
1010 }
1011
1012 /**
1013  * s2io_verify_pci_mode -
1014  */
1015
1016 static int s2io_verify_pci_mode(struct s2io_nic *nic)
1017 {
1018         struct XENA_dev_config __iomem *bar0 = nic->bar0;
1019         register u64 val64 = 0;
1020         int     mode;
1021
1022         val64 = readq(&bar0->pci_mode);
1023         mode = (u8)GET_PCI_MODE(val64);
1024
1025         if (val64 & PCI_MODE_UNKNOWN_MODE)
1026                 return -1;      /* Unknown PCI mode */
1027         return mode;
1028 }
1029
1030 #define NEC_VENID   0x1033
1031 #define NEC_DEVID   0x0125
1032 static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
1033 {
1034         struct pci_dev *tdev = NULL;
1035         for_each_pci_dev(tdev) {
1036                 if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) {
1037                         if (tdev->bus == s2io_pdev->bus->parent) {
1038                                 pci_dev_put(tdev);
1039                                 return 1;
1040                         }
1041                 }
1042         }
1043         return 0;
1044 }
1045
1046 static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
1047 /**
1048  * s2io_print_pci_mode -
1049  */
1050 static int s2io_print_pci_mode(struct s2io_nic *nic)
1051 {
1052         struct XENA_dev_config __iomem *bar0 = nic->bar0;
1053         register u64 val64 = 0;
1054         int     mode;
1055         struct config_param *config = &nic->config;
1056         const char *pcimode;
1057
1058         val64 = readq(&bar0->pci_mode);
1059         mode = (u8)GET_PCI_MODE(val64);
1060
1061         if (val64 & PCI_MODE_UNKNOWN_MODE)
1062                 return -1;      /* Unknown PCI mode */
1063
1064         config->bus_speed = bus_speed[mode];
1065
1066         if (s2io_on_nec_bridge(nic->pdev)) {
1067                 DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
1068                           nic->dev->name);
1069                 return mode;
1070         }
1071
1072         switch (mode) {
1073         case PCI_MODE_PCI_33:
1074                 pcimode = "33MHz PCI bus";
1075                 break;
1076         case PCI_MODE_PCI_66:
1077                 pcimode = "66MHz PCI bus";
1078                 break;
1079         case PCI_MODE_PCIX_M1_66:
1080                 pcimode = "66MHz PCIX(M1) bus";
1081                 break;
1082         case PCI_MODE_PCIX_M1_100:
1083                 pcimode = "100MHz PCIX(M1) bus";
1084                 break;
1085         case PCI_MODE_PCIX_M1_133:
1086                 pcimode = "133MHz PCIX(M1) bus";
1087                 break;
1088         case PCI_MODE_PCIX_M2_66:
1089                 pcimode = "133MHz PCIX(M2) bus";
1090                 break;
1091         case PCI_MODE_PCIX_M2_100:
1092                 pcimode = "200MHz PCIX(M2) bus";
1093                 break;
1094         case PCI_MODE_PCIX_M2_133:
1095                 pcimode = "266MHz PCIX(M2) bus";
1096                 break;
1097         default:
1098                 pcimode = "unsupported bus!";
1099                 mode = -1;
1100         }
1101
1102         DBG_PRINT(ERR_DBG, "%s: Device is on %d bit %s\n",
1103                   nic->dev->name, val64 & PCI_MODE_32_BITS ? 32 : 64, pcimode);
1104
1105         return mode;
1106 }
1107
1108 /**
1109  *  init_tti - Initialization transmit traffic interrupt scheme
1110  *  @nic: device private variable
1111  *  @link: link status (UP/DOWN) used to enable/disable continuous
1112  *  transmit interrupts
1113  *  Description: The function configures transmit traffic interrupts
1114  *  Return Value:  SUCCESS on success and
1115  *  '-1' on failure
1116  */
1117
1118 static int init_tti(struct s2io_nic *nic, int link)
1119 {
1120         struct XENA_dev_config __iomem *bar0 = nic->bar0;
1121         register u64 val64 = 0;
1122         int i;
1123         struct config_param *config = &nic->config;
1124
1125         for (i = 0; i < config->tx_fifo_num; i++) {
1126                 /*
1127                  * TTI Initialization. Default Tx timer gets us about
1128                  * 250 interrupts per sec. Continuous interrupts are enabled
1129                  * by default.
1130                  */
1131                 if (nic->device_type == XFRAME_II_DEVICE) {
1132                         int count = (nic->config.bus_speed * 125)/2;
1133                         val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1134                 } else
1135                         val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1136
1137                 val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1138                         TTI_DATA1_MEM_TX_URNG_B(0x10) |
1139                         TTI_DATA1_MEM_TX_URNG_C(0x30) |
1140                         TTI_DATA1_MEM_TX_TIMER_AC_EN;
1141                 if (i == 0)
1142                         if (use_continuous_tx_intrs && (link == LINK_UP))
1143                                 val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
1144                 writeq(val64, &bar0->tti_data1_mem);
1145
1146                 if (nic->config.intr_type == MSI_X) {
1147                         val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1148                                 TTI_DATA2_MEM_TX_UFC_B(0x100) |
1149                                 TTI_DATA2_MEM_TX_UFC_C(0x200) |
1150                                 TTI_DATA2_MEM_TX_UFC_D(0x300);
1151                 } else {
1152                         if ((nic->config.tx_steering_type ==
1153                              TX_DEFAULT_STEERING) &&
1154                             (config->tx_fifo_num > 1) &&
1155                             (i >= nic->udp_fifo_idx) &&
1156                             (i < (nic->udp_fifo_idx +
1157                                   nic->total_udp_fifos)))
1158                                 val64 = TTI_DATA2_MEM_TX_UFC_A(0x50) |
1159                                         TTI_DATA2_MEM_TX_UFC_B(0x80) |
1160                                         TTI_DATA2_MEM_TX_UFC_C(0x100) |
1161                                         TTI_DATA2_MEM_TX_UFC_D(0x120);
1162                         else
1163                                 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1164                                         TTI_DATA2_MEM_TX_UFC_B(0x20) |
1165                                         TTI_DATA2_MEM_TX_UFC_C(0x40) |
1166                                         TTI_DATA2_MEM_TX_UFC_D(0x80);
1167                 }
1168
1169                 writeq(val64, &bar0->tti_data2_mem);
1170
1171                 val64 = TTI_CMD_MEM_WE |
1172                         TTI_CMD_MEM_STROBE_NEW_CMD |
1173                         TTI_CMD_MEM_OFFSET(i);
1174                 writeq(val64, &bar0->tti_command_mem);
1175
1176                 if (wait_for_cmd_complete(&bar0->tti_command_mem,
1177                                           TTI_CMD_MEM_STROBE_NEW_CMD,
1178                                           S2IO_BIT_RESET) != SUCCESS)
1179                         return FAILURE;
1180         }
1181
1182         return SUCCESS;
1183 }
1184
1185 /**
1186  *  init_nic - Initialization of hardware
1187  *  @nic: device private variable
1188  *  Description: The function sequentially configures every block
1189  *  of the H/W from their reset values.
1190  *  Return Value:  SUCCESS on success and
1191  *  '-1' on failure (endian settings incorrect).
1192  */
1193
1194 static int init_nic(struct s2io_nic *nic)
1195 {
1196         struct XENA_dev_config __iomem *bar0 = nic->bar0;
1197         struct net_device *dev = nic->dev;
1198         register u64 val64 = 0;
1199         void __iomem *add;
1200         u32 time;
1201         int i, j;
1202         int dtx_cnt = 0;
1203         unsigned long long mem_share;
1204         int mem_size;
1205         struct config_param *config = &nic->config;
1206         struct mac_info *mac_control = &nic->mac_control;
1207
1208         /* to set the swapper controle on the card */
1209         if (s2io_set_swapper(nic)) {
1210                 DBG_PRINT(ERR_DBG, "ERROR: Setting Swapper failed\n");
1211                 return -EIO;
1212         }
1213
1214         /*
1215          * Herc requires EOI to be removed from reset before XGXS, so..
1216          */
1217         if (nic->device_type & XFRAME_II_DEVICE) {
1218                 val64 = 0xA500000000ULL;
1219                 writeq(val64, &bar0->sw_reset);
1220                 msleep(500);
1221                 val64 = readq(&bar0->sw_reset);
1222         }
1223
1224         /* Remove XGXS from reset state */
1225         val64 = 0;
1226         writeq(val64, &bar0->sw_reset);
1227         msleep(500);
1228         val64 = readq(&bar0->sw_reset);
1229
1230         /* Ensure that it's safe to access registers by checking
1231          * RIC_RUNNING bit is reset. Check is valid only for XframeII.
1232          */
1233         if (nic->device_type == XFRAME_II_DEVICE) {
1234                 for (i = 0; i < 50; i++) {
1235                         val64 = readq(&bar0->adapter_status);
1236                         if (!(val64 & ADAPTER_STATUS_RIC_RUNNING))
1237                                 break;
1238                         msleep(10);
1239                 }
1240                 if (i == 50)
1241                         return -ENODEV;
1242         }
1243
1244         /*  Enable Receiving broadcasts */
1245         add = &bar0->mac_cfg;
1246         val64 = readq(&bar0->mac_cfg);
1247         val64 |= MAC_RMAC_BCAST_ENABLE;
1248         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1249         writel((u32)val64, add);
1250         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1251         writel((u32) (val64 >> 32), (add + 4));
1252
1253         /* Read registers in all blocks */
1254         val64 = readq(&bar0->mac_int_mask);
1255         val64 = readq(&bar0->mc_int_mask);
1256         val64 = readq(&bar0->xgxs_int_mask);
1257
1258         /*  Set MTU */
1259         val64 = dev->mtu;
1260         writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
1261
1262         if (nic->device_type & XFRAME_II_DEVICE) {
1263                 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
1264                         SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
1265                                           &bar0->dtx_control, UF);
1266                         if (dtx_cnt & 0x1)
1267                                 msleep(1); /* Necessary!! */
1268                         dtx_cnt++;
1269                 }
1270         } else {
1271                 while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
1272                         SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
1273                                           &bar0->dtx_control, UF);
1274                         val64 = readq(&bar0->dtx_control);
1275                         dtx_cnt++;
1276                 }
1277         }
1278
1279         /*  Tx DMA Initialization */
1280         val64 = 0;
1281         writeq(val64, &bar0->tx_fifo_partition_0);
1282         writeq(val64, &bar0->tx_fifo_partition_1);
1283         writeq(val64, &bar0->tx_fifo_partition_2);
1284         writeq(val64, &bar0->tx_fifo_partition_3);
1285
1286         for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
1287                 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
1288
1289                 val64 |= vBIT(tx_cfg->fifo_len - 1, ((j * 32) + 19), 13) |
1290                         vBIT(tx_cfg->fifo_priority, ((j * 32) + 5), 3);
1291
1292                 if (i == (config->tx_fifo_num - 1)) {
1293                         if (i % 2 == 0)
1294                                 i++;
1295                 }
1296
1297                 switch (i) {
1298                 case 1:
1299                         writeq(val64, &bar0->tx_fifo_partition_0);
1300                         val64 = 0;
1301                         j = 0;
1302                         break;
1303                 case 3:
1304                         writeq(val64, &bar0->tx_fifo_partition_1);
1305                         val64 = 0;
1306                         j = 0;
1307                         break;
1308                 case 5:
1309                         writeq(val64, &bar0->tx_fifo_partition_2);
1310                         val64 = 0;
1311                         j = 0;
1312                         break;
1313                 case 7:
1314                         writeq(val64, &bar0->tx_fifo_partition_3);
1315                         val64 = 0;
1316                         j = 0;
1317                         break;
1318                 default:
1319                         j++;
1320                         break;
1321                 }
1322         }
1323
1324         /*
1325          * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1326          * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1327          */
1328         if ((nic->device_type == XFRAME_I_DEVICE) && (nic->pdev->revision < 4))
1329                 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1330
1331         val64 = readq(&bar0->tx_fifo_partition_0);
1332         DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
1333                   &bar0->tx_fifo_partition_0, (unsigned long long)val64);
1334
1335         /*
1336          * Initialization of Tx_PA_CONFIG register to ignore packet
1337          * integrity checking.
1338          */
1339         val64 = readq(&bar0->tx_pa_cfg);
1340         val64 |= TX_PA_CFG_IGNORE_FRM_ERR |
1341                 TX_PA_CFG_IGNORE_SNAP_OUI |
1342                 TX_PA_CFG_IGNORE_LLC_CTRL |
1343                 TX_PA_CFG_IGNORE_L2_ERR;
1344         writeq(val64, &bar0->tx_pa_cfg);
1345
1346         /* Rx DMA initialization. */
1347         val64 = 0;
1348         for (i = 0; i < config->rx_ring_num; i++) {
1349                 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
1350
1351                 val64 |= vBIT(rx_cfg->ring_priority, (5 + (i * 8)), 3);
1352         }
1353         writeq(val64, &bar0->rx_queue_priority);
1354
1355         /*
1356          * Allocating equal share of memory to all the
1357          * configured Rings.
1358          */
1359         val64 = 0;
1360         if (nic->device_type & XFRAME_II_DEVICE)
1361                 mem_size = 32;
1362         else
1363                 mem_size = 64;
1364
1365         for (i = 0; i < config->rx_ring_num; i++) {
1366                 switch (i) {
1367                 case 0:
1368                         mem_share = (mem_size / config->rx_ring_num +
1369                                      mem_size % config->rx_ring_num);
1370                         val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1371                         continue;
1372                 case 1:
1373                         mem_share = (mem_size / config->rx_ring_num);
1374                         val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1375                         continue;
1376                 case 2:
1377                         mem_share = (mem_size / config->rx_ring_num);
1378                         val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1379                         continue;
1380                 case 3:
1381                         mem_share = (mem_size / config->rx_ring_num);
1382                         val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1383                         continue;
1384                 case 4:
1385                         mem_share = (mem_size / config->rx_ring_num);
1386                         val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1387                         continue;
1388                 case 5:
1389                         mem_share = (mem_size / config->rx_ring_num);
1390                         val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1391                         continue;
1392                 case 6:
1393                         mem_share = (mem_size / config->rx_ring_num);
1394                         val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1395                         continue;
1396                 case 7:
1397                         mem_share = (mem_size / config->rx_ring_num);
1398                         val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1399                         continue;
1400                 }
1401         }
1402         writeq(val64, &bar0->rx_queue_cfg);
1403
1404         /*
1405          * Filling Tx round robin registers
1406          * as per the number of FIFOs for equal scheduling priority
1407          */
1408         switch (config->tx_fifo_num) {
1409         case 1:
1410                 val64 = 0x0;
1411                 writeq(val64, &bar0->tx_w_round_robin_0);
1412                 writeq(val64, &bar0->tx_w_round_robin_1);
1413                 writeq(val64, &bar0->tx_w_round_robin_2);
1414                 writeq(val64, &bar0->tx_w_round_robin_3);
1415                 writeq(val64, &bar0->tx_w_round_robin_4);
1416                 break;
1417         case 2:
1418                 val64 = 0x0001000100010001ULL;
1419                 writeq(val64, &bar0->tx_w_round_robin_0);
1420                 writeq(val64, &bar0->tx_w_round_robin_1);
1421                 writeq(val64, &bar0->tx_w_round_robin_2);
1422                 writeq(val64, &bar0->tx_w_round_robin_3);
1423                 val64 = 0x0001000100000000ULL;
1424                 writeq(val64, &bar0->tx_w_round_robin_4);
1425                 break;
1426         case 3:
1427                 val64 = 0x0001020001020001ULL;
1428                 writeq(val64, &bar0->tx_w_round_robin_0);
1429                 val64 = 0x0200010200010200ULL;
1430                 writeq(val64, &bar0->tx_w_round_robin_1);
1431                 val64 = 0x0102000102000102ULL;
1432                 writeq(val64, &bar0->tx_w_round_robin_2);
1433                 val64 = 0x0001020001020001ULL;
1434                 writeq(val64, &bar0->tx_w_round_robin_3);
1435                 val64 = 0x0200010200000000ULL;
1436                 writeq(val64, &bar0->tx_w_round_robin_4);
1437                 break;
1438         case 4:
1439                 val64 = 0x0001020300010203ULL;
1440                 writeq(val64, &bar0->tx_w_round_robin_0);
1441                 writeq(val64, &bar0->tx_w_round_robin_1);
1442                 writeq(val64, &bar0->tx_w_round_robin_2);
1443                 writeq(val64, &bar0->tx_w_round_robin_3);
1444                 val64 = 0x0001020300000000ULL;
1445                 writeq(val64, &bar0->tx_w_round_robin_4);
1446                 break;
1447         case 5:
1448                 val64 = 0x0001020304000102ULL;
1449                 writeq(val64, &bar0->tx_w_round_robin_0);
1450                 val64 = 0x0304000102030400ULL;
1451                 writeq(val64, &bar0->tx_w_round_robin_1);
1452                 val64 = 0x0102030400010203ULL;
1453                 writeq(val64, &bar0->tx_w_round_robin_2);
1454                 val64 = 0x0400010203040001ULL;
1455                 writeq(val64, &bar0->tx_w_round_robin_3);
1456                 val64 = 0x0203040000000000ULL;
1457                 writeq(val64, &bar0->tx_w_round_robin_4);
1458                 break;
1459         case 6:
1460                 val64 = 0x0001020304050001ULL;
1461                 writeq(val64, &bar0->tx_w_round_robin_0);
1462                 val64 = 0x0203040500010203ULL;
1463                 writeq(val64, &bar0->tx_w_round_robin_1);
1464                 val64 = 0x0405000102030405ULL;
1465                 writeq(val64, &bar0->tx_w_round_robin_2);
1466                 val64 = 0x0001020304050001ULL;
1467                 writeq(val64, &bar0->tx_w_round_robin_3);
1468                 val64 = 0x0203040500000000ULL;
1469                 writeq(val64, &bar0->tx_w_round_robin_4);
1470                 break;
1471         case 7:
1472                 val64 = 0x0001020304050600ULL;
1473                 writeq(val64, &bar0->tx_w_round_robin_0);
1474                 val64 = 0x0102030405060001ULL;
1475                 writeq(val64, &bar0->tx_w_round_robin_1);
1476                 val64 = 0x0203040506000102ULL;
1477                 writeq(val64, &bar0->tx_w_round_robin_2);
1478                 val64 = 0x0304050600010203ULL;
1479                 writeq(val64, &bar0->tx_w_round_robin_3);
1480                 val64 = 0x0405060000000000ULL;
1481                 writeq(val64, &bar0->tx_w_round_robin_4);
1482                 break;
1483         case 8:
1484                 val64 = 0x0001020304050607ULL;
1485                 writeq(val64, &bar0->tx_w_round_robin_0);
1486                 writeq(val64, &bar0->tx_w_round_robin_1);
1487                 writeq(val64, &bar0->tx_w_round_robin_2);
1488                 writeq(val64, &bar0->tx_w_round_robin_3);
1489                 val64 = 0x0001020300000000ULL;
1490                 writeq(val64, &bar0->tx_w_round_robin_4);
1491                 break;
1492         }
1493
1494         /* Enable all configured Tx FIFO partitions */
1495         val64 = readq(&bar0->tx_fifo_partition_0);
1496         val64 |= (TX_FIFO_PARTITION_EN);
1497         writeq(val64, &bar0->tx_fifo_partition_0);
1498
1499         /* Filling the Rx round robin registers as per the
1500          * number of Rings and steering based on QoS with
1501          * equal priority.
1502          */
1503         switch (config->rx_ring_num) {
1504         case 1:
1505                 val64 = 0x0;
1506                 writeq(val64, &bar0->rx_w_round_robin_0);
1507                 writeq(val64, &bar0->rx_w_round_robin_1);
1508                 writeq(val64, &bar0->rx_w_round_robin_2);
1509                 writeq(val64, &bar0->rx_w_round_robin_3);
1510                 writeq(val64, &bar0->rx_w_round_robin_4);
1511
1512                 val64 = 0x8080808080808080ULL;
1513                 writeq(val64, &bar0->rts_qos_steering);
1514                 break;
1515         case 2:
1516                 val64 = 0x0001000100010001ULL;
1517                 writeq(val64, &bar0->rx_w_round_robin_0);
1518                 writeq(val64, &bar0->rx_w_round_robin_1);
1519                 writeq(val64, &bar0->rx_w_round_robin_2);
1520                 writeq(val64, &bar0->rx_w_round_robin_3);
1521                 val64 = 0x0001000100000000ULL;
1522                 writeq(val64, &bar0->rx_w_round_robin_4);
1523
1524                 val64 = 0x8080808040404040ULL;
1525                 writeq(val64, &bar0->rts_qos_steering);
1526                 break;
1527         case 3:
1528                 val64 = 0x0001020001020001ULL;
1529                 writeq(val64, &bar0->rx_w_round_robin_0);
1530                 val64 = 0x0200010200010200ULL;
1531                 writeq(val64, &bar0->rx_w_round_robin_1);
1532                 val64 = 0x0102000102000102ULL;
1533                 writeq(val64, &bar0->rx_w_round_robin_2);
1534                 val64 = 0x0001020001020001ULL;
1535                 writeq(val64, &bar0->rx_w_round_robin_3);
1536                 val64 = 0x0200010200000000ULL;
1537                 writeq(val64, &bar0->rx_w_round_robin_4);
1538
1539                 val64 = 0x8080804040402020ULL;
1540                 writeq(val64, &bar0->rts_qos_steering);
1541                 break;
1542         case 4:
1543                 val64 = 0x0001020300010203ULL;
1544                 writeq(val64, &bar0->rx_w_round_robin_0);
1545                 writeq(val64, &bar0->rx_w_round_robin_1);
1546                 writeq(val64, &bar0->rx_w_round_robin_2);
1547                 writeq(val64, &bar0->rx_w_round_robin_3);
1548                 val64 = 0x0001020300000000ULL;
1549                 writeq(val64, &bar0->rx_w_round_robin_4);
1550
1551                 val64 = 0x8080404020201010ULL;
1552                 writeq(val64, &bar0->rts_qos_steering);
1553                 break;
1554         case 5:
1555                 val64 = 0x0001020304000102ULL;
1556                 writeq(val64, &bar0->rx_w_round_robin_0);
1557                 val64 = 0x0304000102030400ULL;
1558                 writeq(val64, &bar0->rx_w_round_robin_1);
1559                 val64 = 0x0102030400010203ULL;
1560                 writeq(val64, &bar0->rx_w_round_robin_2);
1561                 val64 = 0x0400010203040001ULL;
1562                 writeq(val64, &bar0->rx_w_round_robin_3);
1563                 val64 = 0x0203040000000000ULL;
1564                 writeq(val64, &bar0->rx_w_round_robin_4);
1565
1566                 val64 = 0x8080404020201008ULL;
1567                 writeq(val64, &bar0->rts_qos_steering);
1568                 break;
1569         case 6:
1570                 val64 = 0x0001020304050001ULL;
1571                 writeq(val64, &bar0->rx_w_round_robin_0);
1572                 val64 = 0x0203040500010203ULL;
1573                 writeq(val64, &bar0->rx_w_round_robin_1);
1574                 val64 = 0x0405000102030405ULL;
1575                 writeq(val64, &bar0->rx_w_round_robin_2);
1576                 val64 = 0x0001020304050001ULL;
1577                 writeq(val64, &bar0->rx_w_round_robin_3);
1578                 val64 = 0x0203040500000000ULL;
1579                 writeq(val64, &bar0->rx_w_round_robin_4);
1580
1581                 val64 = 0x8080404020100804ULL;
1582                 writeq(val64, &bar0->rts_qos_steering);
1583                 break;
1584         case 7:
1585                 val64 = 0x0001020304050600ULL;
1586                 writeq(val64, &bar0->rx_w_round_robin_0);
1587                 val64 = 0x0102030405060001ULL;
1588                 writeq(val64, &bar0->rx_w_round_robin_1);
1589                 val64 = 0x0203040506000102ULL;
1590                 writeq(val64, &bar0->rx_w_round_robin_2);
1591                 val64 = 0x0304050600010203ULL;
1592                 writeq(val64, &bar0->rx_w_round_robin_3);
1593                 val64 = 0x0405060000000000ULL;
1594                 writeq(val64, &bar0->rx_w_round_robin_4);
1595
1596                 val64 = 0x8080402010080402ULL;
1597                 writeq(val64, &bar0->rts_qos_steering);
1598                 break;
1599         case 8:
1600                 val64 = 0x0001020304050607ULL;
1601                 writeq(val64, &bar0->rx_w_round_robin_0);
1602                 writeq(val64, &bar0->rx_w_round_robin_1);
1603                 writeq(val64, &bar0->rx_w_round_robin_2);
1604                 writeq(val64, &bar0->rx_w_round_robin_3);
1605                 val64 = 0x0001020300000000ULL;
1606                 writeq(val64, &bar0->rx_w_round_robin_4);
1607
1608                 val64 = 0x8040201008040201ULL;
1609                 writeq(val64, &bar0->rts_qos_steering);
1610                 break;
1611         }
1612
1613         /* UDP Fix */
1614         val64 = 0;
1615         for (i = 0; i < 8; i++)
1616                 writeq(val64, &bar0->rts_frm_len_n[i]);
1617
1618         /* Set the default rts frame length for the rings configured */
1619         val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1620         for (i = 0 ; i < config->rx_ring_num ; i++)
1621                 writeq(val64, &bar0->rts_frm_len_n[i]);
1622
1623         /* Set the frame length for the configured rings
1624          * desired by the user
1625          */
1626         for (i = 0; i < config->rx_ring_num; i++) {
1627                 /* If rts_frm_len[i] == 0 then it is assumed that user not
1628                  * specified frame length steering.
1629                  * If the user provides the frame length then program
1630                  * the rts_frm_len register for those values or else
1631                  * leave it as it is.
1632                  */
1633                 if (rts_frm_len[i] != 0) {
1634                         writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
1635                                &bar0->rts_frm_len_n[i]);
1636                 }
1637         }
1638
1639         /* Disable differentiated services steering logic */
1640         for (i = 0; i < 64; i++) {
1641                 if (rts_ds_steer(nic, i, 0) == FAILURE) {
1642                         DBG_PRINT(ERR_DBG,
1643                                   "%s: rts_ds_steer failed on codepoint %d\n",
1644                                   dev->name, i);
1645                         return -ENODEV;
1646                 }
1647         }
1648
1649         /* Program statistics memory */
1650         writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1651
1652         if (nic->device_type == XFRAME_II_DEVICE) {
1653                 val64 = STAT_BC(0x320);
1654                 writeq(val64, &bar0->stat_byte_cnt);
1655         }
1656
1657         /*
1658          * Initializing the sampling rate for the device to calculate the
1659          * bandwidth utilization.
1660          */
1661         val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
1662                 MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1663         writeq(val64, &bar0->mac_link_util);
1664
1665         /*
1666          * Initializing the Transmit and Receive Traffic Interrupt
1667          * Scheme.
1668          */
1669
1670         /* Initialize TTI */
1671         if (SUCCESS != init_tti(nic, nic->last_link_state))
1672                 return -ENODEV;
1673
1674         /* RTI Initialization */
1675         if (nic->device_type == XFRAME_II_DEVICE) {
1676                 /*
1677                  * Programmed to generate Apprx 500 Intrs per
1678                  * second
1679                  */
1680                 int count = (nic->config.bus_speed * 125)/4;
1681                 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1682         } else
1683                 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1684         val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1685                 RTI_DATA1_MEM_RX_URNG_B(0x10) |
1686                 RTI_DATA1_MEM_RX_URNG_C(0x30) |
1687                 RTI_DATA1_MEM_RX_TIMER_AC_EN;
1688
1689         writeq(val64, &bar0->rti_data1_mem);
1690
1691         val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
1692                 RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1693         if (nic->config.intr_type == MSI_X)
1694                 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) |
1695                           RTI_DATA2_MEM_RX_UFC_D(0x40));
1696         else
1697                 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) |
1698                           RTI_DATA2_MEM_RX_UFC_D(0x80));
1699         writeq(val64, &bar0->rti_data2_mem);
1700
1701         for (i = 0; i < config->rx_ring_num; i++) {
1702                 val64 = RTI_CMD_MEM_WE |
1703                         RTI_CMD_MEM_STROBE_NEW_CMD |
1704                         RTI_CMD_MEM_OFFSET(i);
1705                 writeq(val64, &bar0->rti_command_mem);
1706
1707                 /*
1708                  * Once the operation completes, the Strobe bit of the
1709                  * command register will be reset. We poll for this
1710                  * particular condition. We wait for a maximum of 500ms
1711                  * for the operation to complete, if it's not complete
1712                  * by then we return error.
1713                  */
1714                 time = 0;
1715                 while (true) {
1716                         val64 = readq(&bar0->rti_command_mem);
1717                         if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD))
1718                                 break;
1719
1720                         if (time > 10) {
1721                                 DBG_PRINT(ERR_DBG, "%s: RTI init failed\n",
1722                                           dev->name);
1723                                 return -ENODEV;
1724                         }
1725                         time++;
1726                         msleep(50);
1727                 }
1728         }
1729
1730         /*
1731          * Initializing proper values as Pause threshold into all
1732          * the 8 Queues on Rx side.
1733          */
1734         writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1735         writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1736
1737         /* Disable RMAC PAD STRIPPING */
1738         add = &bar0->mac_cfg;
1739         val64 = readq(&bar0->mac_cfg);
1740         val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1741         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1742         writel((u32) (val64), add);
1743         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1744         writel((u32) (val64 >> 32), (add + 4));
1745         val64 = readq(&bar0->mac_cfg);
1746
1747         /* Enable FCS stripping by adapter */
1748         add = &bar0->mac_cfg;
1749         val64 = readq(&bar0->mac_cfg);
1750         val64 |= MAC_CFG_RMAC_STRIP_FCS;
1751         if (nic->device_type == XFRAME_II_DEVICE)
1752                 writeq(val64, &bar0->mac_cfg);
1753         else {
1754                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1755                 writel((u32) (val64), add);
1756                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1757                 writel((u32) (val64 >> 32), (add + 4));
1758         }
1759
1760         /*
1761          * Set the time value to be inserted in the pause frame
1762          * generated by xena.
1763          */
1764         val64 = readq(&bar0->rmac_pause_cfg);
1765         val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1766         val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1767         writeq(val64, &bar0->rmac_pause_cfg);
1768
1769         /*
1770          * Set the Threshold Limit for Generating the pause frame
1771          * If the amount of data in any Queue exceeds ratio of
1772          * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1773          * pause frame is generated
1774          */
1775         val64 = 0;
1776         for (i = 0; i < 4; i++) {
1777                 val64 |= (((u64)0xFF00 |
1778                            nic->mac_control.mc_pause_threshold_q0q3)
1779                           << (i * 2 * 8));
1780         }
1781         writeq(val64, &bar0->mc_pause_thresh_q0q3);
1782
1783         val64 = 0;
1784         for (i = 0; i < 4; i++) {
1785                 val64 |= (((u64)0xFF00 |
1786                            nic->mac_control.mc_pause_threshold_q4q7)
1787                           << (i * 2 * 8));
1788         }
1789         writeq(val64, &bar0->mc_pause_thresh_q4q7);
1790
1791         /*
1792          * TxDMA will stop Read request if the number of read split has
1793          * exceeded the limit pointed by shared_splits
1794          */
1795         val64 = readq(&bar0->pic_control);
1796         val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1797         writeq(val64, &bar0->pic_control);
1798
1799         if (nic->config.bus_speed == 266) {
1800                 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1801                 writeq(0x0, &bar0->read_retry_delay);
1802                 writeq(0x0, &bar0->write_retry_delay);
1803         }
1804
1805         /*
1806          * Programming the Herc to split every write transaction
1807          * that does not start on an ADB to reduce disconnects.
1808          */
1809         if (nic->device_type == XFRAME_II_DEVICE) {
1810                 val64 = FAULT_BEHAVIOUR | EXT_REQ_EN |
1811                         MISC_LINK_STABILITY_PRD(3);
1812                 writeq(val64, &bar0->misc_control);
1813                 val64 = readq(&bar0->pic_control2);
1814                 val64 &= ~(s2BIT(13)|s2BIT(14)|s2BIT(15));
1815                 writeq(val64, &bar0->pic_control2);
1816         }
1817         if (strstr(nic->product_name, "CX4")) {
1818                 val64 = TMAC_AVG_IPG(0x17);
1819                 writeq(val64, &bar0->tmac_avg_ipg);
1820         }
1821
1822         return SUCCESS;
1823 }
1824 #define LINK_UP_DOWN_INTERRUPT          1
1825 #define MAC_RMAC_ERR_TIMER              2
1826
1827 static int s2io_link_fault_indication(struct s2io_nic *nic)
1828 {
1829         if (nic->device_type == XFRAME_II_DEVICE)
1830                 return LINK_UP_DOWN_INTERRUPT;
1831         else
1832                 return MAC_RMAC_ERR_TIMER;
1833 }
1834
1835 /**
1836  *  do_s2io_write_bits -  update alarm bits in alarm register
1837  *  @value: alarm bits
1838  *  @flag: interrupt status
1839  *  @addr: address value
1840  *  Description: update alarm bits in alarm register
1841  *  Return Value:
1842  *  NONE.
1843  */
1844 static void do_s2io_write_bits(u64 value, int flag, void __iomem *addr)
1845 {
1846         u64 temp64;
1847
1848         temp64 = readq(addr);
1849
1850         if (flag == ENABLE_INTRS)
1851                 temp64 &= ~((u64)value);
1852         else
1853                 temp64 |= ((u64)value);
1854         writeq(temp64, addr);
1855 }
1856
1857 static void en_dis_err_alarms(struct s2io_nic *nic, u16 mask, int flag)
1858 {
1859         struct XENA_dev_config __iomem *bar0 = nic->bar0;
1860         register u64 gen_int_mask = 0;
1861         u64 interruptible;
1862
1863         writeq(DISABLE_ALL_INTRS, &bar0->general_int_mask);
1864         if (mask & TX_DMA_INTR) {
1865                 gen_int_mask |= TXDMA_INT_M;
1866
1867                 do_s2io_write_bits(TXDMA_TDA_INT | TXDMA_PFC_INT |
1868                                    TXDMA_PCC_INT | TXDMA_TTI_INT |
1869                                    TXDMA_LSO_INT | TXDMA_TPA_INT |
1870                                    TXDMA_SM_INT, flag, &bar0->txdma_int_mask);
1871
1872                 do_s2io_write_bits(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
1873                                    PFC_MISC_0_ERR | PFC_MISC_1_ERR |
1874                                    PFC_PCIX_ERR | PFC_ECC_SG_ERR, flag,
1875                                    &bar0->pfc_err_mask);
1876
1877                 do_s2io_write_bits(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |
1878                                    TDA_SM1_ERR_ALARM | TDA_Fn_ECC_SG_ERR |
1879                                    TDA_PCIX_ERR, flag, &bar0->tda_err_mask);
1880
1881                 do_s2io_write_bits(PCC_FB_ECC_DB_ERR | PCC_TXB_ECC_DB_ERR |
1882                                    PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
1883                                    PCC_N_SERR | PCC_6_COF_OV_ERR |
1884                                    PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
1885                                    PCC_7_LSO_OV_ERR | PCC_FB_ECC_SG_ERR |
1886                                    PCC_TXB_ECC_SG_ERR,
1887                                    flag, &bar0->pcc_err_mask);
1888
1889                 do_s2io_write_bits(TTI_SM_ERR_ALARM | TTI_ECC_SG_ERR |
1890                                    TTI_ECC_DB_ERR, flag, &bar0->tti_err_mask);
1891
1892                 do_s2io_write_bits(LSO6_ABORT | LSO7_ABORT |
1893                                    LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM |
1894                                    LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
1895                                    flag, &bar0->lso_err_mask);
1896
1897                 do_s2io_write_bits(TPA_SM_ERR_ALARM | TPA_TX_FRM_DROP,
1898                                    flag, &bar0->tpa_err_mask);
1899
1900                 do_s2io_write_bits(SM_SM_ERR_ALARM, flag, &bar0->sm_err_mask);
1901         }
1902
1903         if (mask & TX_MAC_INTR) {
1904                 gen_int_mask |= TXMAC_INT_M;
1905                 do_s2io_write_bits(MAC_INT_STATUS_TMAC_INT, flag,
1906                                    &bar0->mac_int_mask);
1907                 do_s2io_write_bits(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR |
1908                                    TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
1909                                    TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,
1910                                    flag, &bar0->mac_tmac_err_mask);
1911         }
1912
1913         if (mask & TX_XGXS_INTR) {
1914                 gen_int_mask |= TXXGXS_INT_M;
1915                 do_s2io_write_bits(XGXS_INT_STATUS_TXGXS, flag,
1916                                    &bar0->xgxs_int_mask);
1917                 do_s2io_write_bits(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR |
1918                                    TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
1919                                    flag, &bar0->xgxs_txgxs_err_mask);
1920         }
1921
1922         if (mask & RX_DMA_INTR) {
1923                 gen_int_mask |= RXDMA_INT_M;
1924                 do_s2io_write_bits(RXDMA_INT_RC_INT_M | RXDMA_INT_RPA_INT_M |
1925                                    RXDMA_INT_RDA_INT_M | RXDMA_INT_RTI_INT_M,
1926                                    flag, &bar0->rxdma_int_mask);
1927                 do_s2io_write_bits(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR |
1928                                    RC_PRCn_SM_ERR_ALARM | RC_FTC_SM_ERR_ALARM |
1929                                    RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR |
1930                                    RC_RDA_FAIL_WR_Rn, flag, &bar0->rc_err_mask);
1931                 do_s2io_write_bits(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn |
1932                                    PRC_PCI_AB_F_WR_Rn | PRC_PCI_DP_RD_Rn |
1933                                    PRC_PCI_DP_WR_Rn | PRC_PCI_DP_F_WR_Rn, flag,
1934                                    &bar0->prc_pcix_err_mask);
1935                 do_s2io_write_bits(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR |
1936                                    RPA_ECC_SG_ERR | RPA_ECC_DB_ERR, flag,
1937                                    &bar0->rpa_err_mask);
1938                 do_s2io_write_bits(RDA_RXDn_ECC_DB_ERR | RDA_FRM_ECC_DB_N_AERR |
1939                                    RDA_SM1_ERR_ALARM | RDA_SM0_ERR_ALARM |
1940                                    RDA_RXD_ECC_DB_SERR | RDA_RXDn_ECC_SG_ERR |
1941                                    RDA_FRM_ECC_SG_ERR |
1942                                    RDA_MISC_ERR|RDA_PCIX_ERR,
1943                                    flag, &bar0->rda_err_mask);
1944                 do_s2io_write_bits(RTI_SM_ERR_ALARM |
1945                                    RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
1946                                    flag, &bar0->rti_err_mask);
1947         }
1948
1949         if (mask & RX_MAC_INTR) {
1950                 gen_int_mask |= RXMAC_INT_M;
1951                 do_s2io_write_bits(MAC_INT_STATUS_RMAC_INT, flag,
1952                                    &bar0->mac_int_mask);
1953                 interruptible = (RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR |
1954                                  RMAC_UNUSED_INT | RMAC_SINGLE_ECC_ERR |
1955                                  RMAC_DOUBLE_ECC_ERR);
1956                 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER)
1957                         interruptible |= RMAC_LINK_STATE_CHANGE_INT;
1958                 do_s2io_write_bits(interruptible,
1959                                    flag, &bar0->mac_rmac_err_mask);
1960         }
1961
1962         if (mask & RX_XGXS_INTR) {
1963                 gen_int_mask |= RXXGXS_INT_M;
1964                 do_s2io_write_bits(XGXS_INT_STATUS_RXGXS, flag,
1965                                    &bar0->xgxs_int_mask);
1966                 do_s2io_write_bits(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR, flag,
1967                                    &bar0->xgxs_rxgxs_err_mask);
1968         }
1969
1970         if (mask & MC_INTR) {
1971                 gen_int_mask |= MC_INT_M;
1972                 do_s2io_write_bits(MC_INT_MASK_MC_INT,
1973                                    flag, &bar0->mc_int_mask);
1974                 do_s2io_write_bits(MC_ERR_REG_SM_ERR | MC_ERR_REG_ECC_ALL_SNG |
1975                                    MC_ERR_REG_ECC_ALL_DBL | PLL_LOCK_N, flag,
1976                                    &bar0->mc_err_mask);
1977         }
1978         nic->general_int_mask = gen_int_mask;
1979
1980         /* Remove this line when alarm interrupts are enabled */
1981         nic->general_int_mask = 0;
1982 }
1983
1984 /**
1985  *  en_dis_able_nic_intrs - Enable or Disable the interrupts
1986  *  @nic: device private variable,
1987  *  @mask: A mask indicating which Intr block must be modified and,
1988  *  @flag: A flag indicating whether to enable or disable the Intrs.
1989  *  Description: This function will either disable or enable the interrupts
1990  *  depending on the flag argument. The mask argument can be used to
1991  *  enable/disable any Intr block.
1992  *  Return Value: NONE.
1993  */
1994
1995 static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
1996 {
1997         struct XENA_dev_config __iomem *bar0 = nic->bar0;
1998         register u64 temp64 = 0, intr_mask = 0;
1999
2000         intr_mask = nic->general_int_mask;
2001
2002         /*  Top level interrupt classification */
2003         /*  PIC Interrupts */
2004         if (mask & TX_PIC_INTR) {
2005                 /*  Enable PIC Intrs in the general intr mask register */
2006                 intr_mask |= TXPIC_INT_M;
2007                 if (flag == ENABLE_INTRS) {
2008                         /*
2009                          * If Hercules adapter enable GPIO otherwise
2010                          * disable all PCIX, Flash, MDIO, IIC and GPIO
2011                          * interrupts for now.
2012                          * TODO
2013                          */
2014                         if (s2io_link_fault_indication(nic) ==
2015                             LINK_UP_DOWN_INTERRUPT) {
2016                                 do_s2io_write_bits(PIC_INT_GPIO, flag,
2017                                                    &bar0->pic_int_mask);
2018                                 do_s2io_write_bits(GPIO_INT_MASK_LINK_UP, flag,
2019                                                    &bar0->gpio_int_mask);
2020                         } else
2021                                 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
2022                 } else if (flag == DISABLE_INTRS) {
2023                         /*
2024                          * Disable PIC Intrs in the general
2025                          * intr mask register
2026                          */
2027                         writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
2028                 }
2029         }
2030
2031         /*  Tx traffic interrupts */
2032         if (mask & TX_TRAFFIC_INTR) {
2033                 intr_mask |= TXTRAFFIC_INT_M;
2034                 if (flag == ENABLE_INTRS) {
2035                         /*
2036                          * Enable all the Tx side interrupts
2037                          * writing 0 Enables all 64 TX interrupt levels
2038                          */
2039                         writeq(0x0, &bar0->tx_traffic_mask);
2040                 } else if (flag == DISABLE_INTRS) {
2041                         /*
2042                          * Disable Tx Traffic Intrs in the general intr mask
2043                          * register.
2044                          */
2045                         writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
2046                 }
2047         }
2048
2049         /*  Rx traffic interrupts */
2050         if (mask & RX_TRAFFIC_INTR) {
2051                 intr_mask |= RXTRAFFIC_INT_M;
2052                 if (flag == ENABLE_INTRS) {
2053                         /* writing 0 Enables all 8 RX interrupt levels */
2054                         writeq(0x0, &bar0->rx_traffic_mask);
2055                 } else if (flag == DISABLE_INTRS) {
2056                         /*
2057                          * Disable Rx Traffic Intrs in the general intr mask
2058                          * register.
2059                          */
2060                         writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
2061                 }
2062         }
2063
2064         temp64 = readq(&bar0->general_int_mask);
2065         if (flag == ENABLE_INTRS)
2066                 temp64 &= ~((u64)intr_mask);
2067         else
2068                 temp64 = DISABLE_ALL_INTRS;
2069         writeq(temp64, &bar0->general_int_mask);
2070
2071         nic->general_int_mask = readq(&bar0->general_int_mask);
2072 }
2073
2074 /**
2075  *  verify_pcc_quiescent- Checks for PCC quiescent state
2076  *  Return: 1 If PCC is quiescence
2077  *          0 If PCC is not quiescence
2078  */
2079 static int verify_pcc_quiescent(struct s2io_nic *sp, int flag)
2080 {
2081         int ret = 0, herc;
2082         struct XENA_dev_config __iomem *bar0 = sp->bar0;
2083         u64 val64 = readq(&bar0->adapter_status);
2084
2085         herc = (sp->device_type == XFRAME_II_DEVICE);
2086
2087         if (flag == false) {
2088                 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
2089                         if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE))
2090                                 ret = 1;
2091                 } else {
2092                         if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
2093                                 ret = 1;
2094                 }
2095         } else {
2096                 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
2097                         if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
2098                              ADAPTER_STATUS_RMAC_PCC_IDLE))
2099                                 ret = 1;
2100                 } else {
2101                         if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
2102                              ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
2103                                 ret = 1;
2104                 }
2105         }
2106
2107         return ret;
2108 }
2109 /**
2110  *  verify_xena_quiescence - Checks whether the H/W is ready
2111  *  Description: Returns whether the H/W is ready to go or not. Depending
2112  *  on whether adapter enable bit was written or not the comparison
2113  *  differs and the calling function passes the input argument flag to
2114  *  indicate this.
2115  *  Return: 1 If xena is quiescence
2116  *          0 If Xena is not quiescence
2117  */
2118
2119 static int verify_xena_quiescence(struct s2io_nic *sp)
2120 {
2121         int  mode;
2122         struct XENA_dev_config __iomem *bar0 = sp->bar0;
2123         u64 val64 = readq(&bar0->adapter_status);
2124         mode = s2io_verify_pci_mode(sp);
2125
2126         if (!(val64 & ADAPTER_STATUS_TDMA_READY)) {
2127                 DBG_PRINT(ERR_DBG, "TDMA is not ready!\n");
2128                 return 0;
2129         }
2130         if (!(val64 & ADAPTER_STATUS_RDMA_READY)) {
2131                 DBG_PRINT(ERR_DBG, "RDMA is not ready!\n");
2132                 return 0;
2133         }
2134         if (!(val64 & ADAPTER_STATUS_PFC_READY)) {
2135                 DBG_PRINT(ERR_DBG, "PFC is not ready!\n");
2136                 return 0;
2137         }
2138         if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) {
2139                 DBG_PRINT(ERR_DBG, "TMAC BUF is not empty!\n");
2140                 return 0;
2141         }
2142         if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) {
2143                 DBG_PRINT(ERR_DBG, "PIC is not QUIESCENT!\n");
2144                 return 0;
2145         }
2146         if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) {
2147                 DBG_PRINT(ERR_DBG, "MC_DRAM is not ready!\n");
2148                 return 0;
2149         }
2150         if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) {
2151                 DBG_PRINT(ERR_DBG, "MC_QUEUES is not ready!\n");
2152                 return 0;
2153         }
2154         if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) {
2155                 DBG_PRINT(ERR_DBG, "M_PLL is not locked!\n");
2156                 return 0;
2157         }
2158
2159         /*
2160          * In PCI 33 mode, the P_PLL is not used, and therefore,
2161          * the the P_PLL_LOCK bit in the adapter_status register will
2162          * not be asserted.
2163          */
2164         if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) &&
2165             sp->device_type == XFRAME_II_DEVICE &&
2166             mode != PCI_MODE_PCI_33) {
2167                 DBG_PRINT(ERR_DBG, "P_PLL is not locked!\n");
2168                 return 0;
2169         }
2170         if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
2171               ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
2172                 DBG_PRINT(ERR_DBG, "RC_PRC is not QUIESCENT!\n");
2173                 return 0;
2174         }
2175         return 1;
2176 }
2177
2178 /**
2179  * fix_mac_address -  Fix for Mac addr problem on Alpha platforms
2180  * @sp: Pointer to device specifc structure
2181  * Description :
2182  * New procedure to clear mac address reading  problems on Alpha platforms
2183  *
2184  */
2185
2186 static void fix_mac_address(struct s2io_nic *sp)
2187 {
2188         struct XENA_dev_config __iomem *bar0 = sp->bar0;
2189         int i = 0;
2190
2191         while (fix_mac[i] != END_SIGN) {
2192                 writeq(fix_mac[i++], &bar0->gpio_control);
2193                 udelay(10);
2194                 (void) readq(&bar0->gpio_control);
2195         }
2196 }
2197
2198 /**
2199  *  start_nic - Turns the device on
2200  *  @nic : device private variable.
2201  *  Description:
2202  *  This function actually turns the device on. Before this  function is
2203  *  called,all Registers are configured from their reset states
2204  *  and shared memory is allocated but the NIC is still quiescent. On
2205  *  calling this function, the device interrupts are cleared and the NIC is
2206  *  literally switched on by writing into the adapter control register.
2207  *  Return Value:
2208  *  SUCCESS on success and -1 on failure.
2209  */
2210
2211 static int start_nic(struct s2io_nic *nic)
2212 {
2213         struct XENA_dev_config __iomem *bar0 = nic->bar0;
2214         struct net_device *dev = nic->dev;
2215         register u64 val64 = 0;
2216         u16 subid, i;
2217         struct config_param *config = &nic->config;
2218         struct mac_info *mac_control = &nic->mac_control;
2219
2220         /*  PRC Initialization and configuration */
2221         for (i = 0; i < config->rx_ring_num; i++) {
2222                 struct ring_info *ring = &mac_control->rings[i];
2223
2224                 writeq((u64)ring->rx_blocks[0].block_dma_addr,
2225                        &bar0->prc_rxd0_n[i]);
2226
2227                 val64 = readq(&bar0->prc_ctrl_n[i]);
2228                 if (nic->rxd_mode == RXD_MODE_1)
2229                         val64 |= PRC_CTRL_RC_ENABLED;
2230                 else
2231                         val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
2232                 if (nic->device_type == XFRAME_II_DEVICE)
2233                         val64 |= PRC_CTRL_GROUP_READS;
2234                 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2235                 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
2236                 writeq(val64, &bar0->prc_ctrl_n[i]);
2237         }
2238
2239         if (nic->rxd_mode == RXD_MODE_3B) {
2240                 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2241                 val64 = readq(&bar0->rx_pa_cfg);
2242                 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
2243                 writeq(val64, &bar0->rx_pa_cfg);
2244         }
2245
2246         if (vlan_tag_strip == 0) {
2247                 val64 = readq(&bar0->rx_pa_cfg);
2248                 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
2249                 writeq(val64, &bar0->rx_pa_cfg);
2250                 nic->vlan_strip_flag = 0;
2251         }
2252
2253         /*
2254          * Enabling MC-RLDRAM. After enabling the device, we timeout
2255          * for around 100ms, which is approximately the time required
2256          * for the device to be ready for operation.
2257          */
2258         val64 = readq(&bar0->mc_rldram_mrs);
2259         val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
2260         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
2261         val64 = readq(&bar0->mc_rldram_mrs);
2262
2263         msleep(100);    /* Delay by around 100 ms. */
2264
2265         /* Enabling ECC Protection. */
2266         val64 = readq(&bar0->adapter_control);
2267         val64 &= ~ADAPTER_ECC_EN;
2268         writeq(val64, &bar0->adapter_control);
2269
2270         /*
2271          * Verify if the device is ready to be enabled, if so enable
2272          * it.
2273          */
2274         val64 = readq(&bar0->adapter_status);
2275         if (!verify_xena_quiescence(nic)) {
2276                 DBG_PRINT(ERR_DBG, "%s: device is not ready, "
2277                           "Adapter status reads: 0x%llx\n",
2278                           dev->name, (unsigned long long)val64);
2279                 return FAILURE;
2280         }
2281
2282         /*
2283          * With some switches, link might be already up at this point.
2284          * Because of this weird behavior, when we enable laser,
2285          * we may not get link. We need to handle this. We cannot
2286          * figure out which switch is misbehaving. So we are forced to
2287          * make a global change.
2288          */
2289
2290         /* Enabling Laser. */
2291         val64 = readq(&bar0->adapter_control);
2292         val64 |= ADAPTER_EOI_TX_ON;
2293         writeq(val64, &bar0->adapter_control);
2294
2295         if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2296                 /*
2297                  * Dont see link state interrupts initially on some switches,
2298                  * so directly scheduling the link state task here.
2299                  */
2300                 schedule_work(&nic->set_link_task);
2301         }
2302         /* SXE-002: Initialize link and activity LED */
2303         subid = nic->pdev->subsystem_device;
2304         if (((subid & 0xFF) >= 0x07) &&
2305             (nic->device_type == XFRAME_I_DEVICE)) {
2306                 val64 = readq(&bar0->gpio_control);
2307                 val64 |= 0x0000800000000000ULL;
2308                 writeq(val64, &bar0->gpio_control);
2309                 val64 = 0x0411040400000000ULL;
2310                 writeq(val64, (void __iomem *)bar0 + 0x2700);
2311         }
2312
2313         return SUCCESS;
2314 }
2315 /**
2316  * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2317  */
2318 static struct sk_buff *s2io_txdl_getskb(struct fifo_info *fifo_data,
2319                                         struct TxD *txdlp, int get_off)
2320 {
2321         struct s2io_nic *nic = fifo_data->nic;
2322         struct sk_buff *skb;
2323         struct TxD *txds;
2324         u16 j, frg_cnt;
2325
2326         txds = txdlp;
2327         if (txds->Host_Control == (u64)(long)fifo_data->ufo_in_band_v) {
2328                 pci_unmap_single(nic->pdev, (dma_addr_t)txds->Buffer_Pointer,
2329                                  sizeof(u64), PCI_DMA_TODEVICE);
2330                 txds++;
2331         }
2332
2333         skb = (struct sk_buff *)((unsigned long)txds->Host_Control);
2334         if (!skb) {
2335                 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
2336                 return NULL;
2337         }
2338         pci_unmap_single(nic->pdev, (dma_addr_t)txds->Buffer_Pointer,
2339                          skb_headlen(skb), PCI_DMA_TODEVICE);
2340         frg_cnt = skb_shinfo(skb)->nr_frags;
2341         if (frg_cnt) {
2342                 txds++;
2343                 for (j = 0; j < frg_cnt; j++, txds++) {
2344                         const skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2345                         if (!txds->Buffer_Pointer)
2346                                 break;
2347                         pci_unmap_page(nic->pdev,
2348                                        (dma_addr_t)txds->Buffer_Pointer,
2349                                        skb_frag_size(frag), PCI_DMA_TODEVICE);
2350                 }
2351         }
2352         memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
2353         return skb;
2354 }
2355
2356 /**
2357  *  free_tx_buffers - Free all queued Tx buffers
2358  *  @nic : device private variable.
2359  *  Description:
2360  *  Free all queued Tx buffers.
2361  *  Return Value: void
2362  */
2363
2364 static void free_tx_buffers(struct s2io_nic *nic)
2365 {
2366         struct net_device *dev = nic->dev;
2367         struct sk_buff *skb;
2368         struct TxD *txdp;
2369         int i, j;
2370         int cnt = 0;
2371         struct config_param *config = &nic->config;
2372         struct mac_info *mac_control = &nic->mac_control;
2373         struct stat_block *stats = mac_control->stats_info;
2374         struct swStat *swstats = &stats->sw_stat;
2375
2376         for (i = 0; i < config->tx_fifo_num; i++) {
2377                 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
2378                 struct fifo_info *fifo = &mac_control->fifos[i];
2379                 unsigned long flags;
2380
2381                 spin_lock_irqsave(&fifo->tx_lock, flags);
2382                 for (j = 0; j < tx_cfg->fifo_len; j++) {
2383                         txdp = fifo->list_info[j].list_virt_addr;
2384                         skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2385                         if (skb) {
2386                                 swstats->mem_freed += skb->truesize;
2387                                 dev_kfree_skb(skb);
2388                                 cnt++;
2389                         }
2390                 }
2391                 DBG_PRINT(INTR_DBG,
2392                           "%s: forcibly freeing %d skbs on FIFO%d\n",
2393                           dev->name, cnt, i);
2394                 fifo->tx_curr_get_info.offset = 0;
2395                 fifo->tx_curr_put_info.offset = 0;
2396                 spin_unlock_irqrestore(&fifo->tx_lock, flags);
2397         }
2398 }
2399
2400 /**
2401  *   stop_nic -  To stop the nic
2402  *   @nic ; device private variable.
2403  *   Description:
2404  *   This function does exactly the opposite of what the start_nic()
2405  *   function does. This function is called to stop the device.
2406  *   Return Value:
2407  *   void.
2408  */
2409
2410 static void stop_nic(struct s2io_nic *nic)
2411 {
2412         struct XENA_dev_config __iomem *bar0 = nic->bar0;
2413         register u64 val64 = 0;
2414         u16 interruptible;
2415
2416         /*  Disable all interrupts */
2417         en_dis_err_alarms(nic, ENA_ALL_INTRS, DISABLE_INTRS);
2418         interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
2419         interruptible |= TX_PIC_INTR;
2420         en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2421
2422         /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2423         val64 = readq(&bar0->adapter_control);
2424         val64 &= ~(ADAPTER_CNTL_EN);
2425         writeq(val64, &bar0->adapter_control);
2426 }
2427
2428 /**
2429  *  fill_rx_buffers - Allocates the Rx side skbs
2430  *  @ring_info: per ring structure
2431  *  @from_card_up: If this is true, we will map the buffer to get
2432  *     the dma address for buf0 and buf1 to give it to the card.
2433  *     Else we will sync the already mapped buffer to give it to the card.
2434  *  Description:
2435  *  The function allocates Rx side skbs and puts the physical
2436  *  address of these buffers into the RxD buffer pointers, so that the NIC
2437  *  can DMA the received frame into these locations.
2438  *  The NIC supports 3 receive modes, viz
2439  *  1. single buffer,
2440  *  2. three buffer and
2441  *  3. Five buffer modes.
2442  *  Each mode defines how many fragments the received frame will be split
2443  *  up into by the NIC. The frame is split into L3 header, L4 Header,
2444  *  L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2445  *  is split into 3 fragments. As of now only single buffer mode is
2446  *  supported.
2447  *   Return Value:
2448  *  SUCCESS on success or an appropriate -ve value on failure.
2449  */
2450 static int fill_rx_buffers(struct s2io_nic *nic, struct ring_info *ring,
2451                            int from_card_up)
2452 {
2453         struct sk_buff *skb;
2454         struct RxD_t *rxdp;
2455         int off, size, block_no, block_no1;
2456         u32 alloc_tab = 0;
2457         u32 alloc_cnt;
2458         u64 tmp;
2459         struct buffAdd *ba;
2460         struct RxD_t *first_rxdp = NULL;
2461         u64 Buffer0_ptr = 0, Buffer1_ptr = 0;
2462         int rxd_index = 0;
2463         struct RxD1 *rxdp1;
2464         struct RxD3 *rxdp3;
2465         struct swStat *swstats = &ring->nic->mac_control.stats_info->sw_stat;
2466
2467         alloc_cnt = ring->pkt_cnt - ring->rx_bufs_left;
2468
2469         block_no1 = ring->rx_curr_get_info.block_index;
2470         while (alloc_tab < alloc_cnt) {
2471                 block_no = ring->rx_curr_put_info.block_index;
2472
2473                 off = ring->rx_curr_put_info.offset;
2474
2475                 rxdp = ring->rx_blocks[block_no].rxds[off].virt_addr;
2476
2477                 rxd_index = off + 1;
2478                 if (block_no)
2479                         rxd_index += (block_no * ring->rxd_count);
2480
2481                 if ((block_no == block_no1) &&
2482                     (off == ring->rx_curr_get_info.offset) &&
2483                     (rxdp->Host_Control)) {
2484                         DBG_PRINT(INTR_DBG, "%s: Get and Put info equated\n",
2485                                   ring->dev->name);
2486                         goto end;
2487                 }
2488                 if (off && (off == ring->rxd_count)) {
2489                         ring->rx_curr_put_info.block_index++;
2490                         if (ring->rx_curr_put_info.block_index ==
2491                             ring->block_count)
2492                                 ring->rx_curr_put_info.block_index = 0;
2493                         block_no = ring->rx_curr_put_info.block_index;
2494                         off = 0;
2495                         ring->rx_curr_put_info.offset = off;
2496                         rxdp = ring->rx_blocks[block_no].block_virt_addr;
2497                         DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
2498                                   ring->dev->name, rxdp);
2499
2500                 }
2501
2502                 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
2503                     ((ring->rxd_mode == RXD_MODE_3B) &&
2504                      (rxdp->Control_2 & s2BIT(0)))) {
2505                         ring->rx_curr_put_info.offset = off;
2506                         goto end;
2507                 }
2508                 /* calculate size of skb based on ring mode */
2509                 size = ring->mtu +
2510                         HEADER_ETHERNET_II_802_3_SIZE +
2511                         HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
2512                 if (ring->rxd_mode == RXD_MODE_1)
2513                         size += NET_IP_ALIGN;
2514                 else
2515                         size = ring->mtu + ALIGN_SIZE + BUF0_LEN + 4;
2516
2517                 /* allocate skb */
2518                 skb = netdev_alloc_skb(nic->dev, size);
2519                 if (!skb) {
2520                         DBG_PRINT(INFO_DBG, "%s: Could not allocate skb\n",
2521                                   ring->dev->name);
2522                         if (first_rxdp) {
2523                                 dma_wmb();
2524                                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2525                         }
2526                         swstats->mem_alloc_fail_cnt++;
2527
2528                         return -ENOMEM ;
2529                 }
2530                 swstats->mem_allocated += skb->truesize;
2531
2532                 if (ring->rxd_mode == RXD_MODE_1) {
2533                         /* 1 buffer mode - normal operation mode */
2534                         rxdp1 = (struct RxD1 *)rxdp;
2535                         memset(rxdp, 0, sizeof(struct RxD1));
2536                         skb_reserve(skb, NET_IP_ALIGN);
2537                         rxdp1->Buffer0_ptr =
2538                                 pci_map_single(ring->pdev, skb->data,
2539                                                size - NET_IP_ALIGN,
2540                                                PCI_DMA_FROMDEVICE);
2541                         if (pci_dma_mapping_error(nic->pdev,
2542                                                   rxdp1->Buffer0_ptr))
2543                                 goto pci_map_failed;
2544
2545                         rxdp->Control_2 =
2546                                 SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
2547                         rxdp->Host_Control = (unsigned long)skb;
2548                 } else if (ring->rxd_mode == RXD_MODE_3B) {
2549                         /*
2550                          * 2 buffer mode -
2551                          * 2 buffer mode provides 128
2552                          * byte aligned receive buffers.
2553                          */
2554
2555                         rxdp3 = (struct RxD3 *)rxdp;
2556                         /* save buffer pointers to avoid frequent dma mapping */
2557                         Buffer0_ptr = rxdp3->Buffer0_ptr;
2558                         Buffer1_ptr = rxdp3->Buffer1_ptr;
2559                         memset(rxdp, 0, sizeof(struct RxD3));
2560                         /* restore the buffer pointers for dma sync*/
2561                         rxdp3->Buffer0_ptr = Buffer0_ptr;
2562                         rxdp3->Buffer1_ptr = Buffer1_ptr;
2563
2564                         ba = &ring->ba[block_no][off];
2565                         skb_reserve(skb, BUF0_LEN);
2566                         tmp = (u64)(unsigned long)skb->data;
2567                         tmp += ALIGN_SIZE;
2568                         tmp &= ~ALIGN_SIZE;
2569                         skb->data = (void *) (unsigned long)tmp;
2570                         skb_reset_tail_pointer(skb);
2571
2572                         if (from_card_up) {
2573                                 rxdp3->Buffer0_ptr =
2574                                         pci_map_single(ring->pdev, ba->ba_0,
2575                                                        BUF0_LEN,
2576                                                        PCI_DMA_FROMDEVICE);
2577                                 if (pci_dma_mapping_error(nic->pdev,
2578                                                           rxdp3->Buffer0_ptr))
2579                                         goto pci_map_failed;
2580                         } else
2581                                 pci_dma_sync_single_for_device(ring->pdev,
2582                                                                (dma_addr_t)rxdp3->Buffer0_ptr,
2583                                                                BUF0_LEN,
2584                                                                PCI_DMA_FROMDEVICE);
2585
2586                         rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
2587                         if (ring->rxd_mode == RXD_MODE_3B) {
2588                                 /* Two buffer mode */
2589
2590                                 /*
2591                                  * Buffer2 will have L3/L4 header plus
2592                                  * L4 payload
2593                                  */
2594                                 rxdp3->Buffer2_ptr = pci_map_single(ring->pdev,
2595                                                                     skb->data,
2596                                                                     ring->mtu + 4,
2597                                                                     PCI_DMA_FROMDEVICE);
2598
2599                                 if (pci_dma_mapping_error(nic->pdev,
2600                                                           rxdp3->Buffer2_ptr))
2601                                         goto pci_map_failed;
2602
2603                                 if (from_card_up) {
2604                                         rxdp3->Buffer1_ptr =
2605                                                 pci_map_single(ring->pdev,
2606                                                                ba->ba_1,
2607                                                                BUF1_LEN,
2608                                                                PCI_DMA_FROMDEVICE);
2609
2610                                         if (pci_dma_mapping_error(nic->pdev,
2611                                                                   rxdp3->Buffer1_ptr)) {
2612                                                 pci_unmap_single(ring->pdev,
2613                                                                  (dma_addr_t)(unsigned long)
2614                                                                  skb->data,
2615                                                                  ring->mtu + 4,
2616                                                                  PCI_DMA_FROMDEVICE);
2617                                                 goto pci_map_failed;
2618                                         }
2619                                 }
2620                                 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2621                                 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
2622                                         (ring->mtu + 4);
2623                         }
2624                         rxdp->Control_2 |= s2BIT(0);
2625                         rxdp->Host_Control = (unsigned long) (skb);
2626                 }
2627                 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2628                         rxdp->Control_1 |= RXD_OWN_XENA;
2629                 off++;
2630                 if (off == (ring->rxd_count + 1))
2631                         off = 0;
2632                 ring->rx_curr_put_info.offset = off;
2633
2634                 rxdp->Control_2 |= SET_RXD_MARKER;
2635                 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2636                         if (first_rxdp) {
2637                                 dma_wmb();
2638                                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2639                         }
2640                         first_rxdp = rxdp;
2641                 }
2642                 ring->rx_bufs_left += 1;
2643                 alloc_tab++;
2644         }
2645
2646 end:
2647         /* Transfer ownership of first descriptor to adapter just before
2648          * exiting. Before that, use memory barrier so that ownership
2649          * and other fields are seen by adapter correctly.
2650          */
2651         if (first_rxdp) {
2652                 dma_wmb();
2653                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2654         }
2655
2656         return SUCCESS;
2657
2658 pci_map_failed:
2659         swstats->pci_map_fail_cnt++;
2660         swstats->mem_freed += skb->truesize;
2661         dev_kfree_skb_irq(skb);
2662         return -ENOMEM;
2663 }
2664
2665 static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2666 {
2667         struct net_device *dev = sp->dev;
2668         int j;
2669         struct sk_buff *skb;
2670         struct RxD_t *rxdp;
2671         struct RxD1 *rxdp1;
2672         struct RxD3 *rxdp3;
2673         struct mac_info *mac_control = &sp->mac_control;
2674         struct stat_block *stats = mac_control->stats_info;
2675         struct swStat *swstats = &stats->sw_stat;
2676
2677         for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2678                 rxdp = mac_control->rings[ring_no].
2679                         rx_blocks[blk].rxds[j].virt_addr;
2680                 skb = (struct sk_buff *)((unsigned long)rxdp->Host_Control);
2681                 if (!skb)
2682                         continue;
2683                 if (sp->rxd_mode == RXD_MODE_1) {
2684                         rxdp1 = (struct RxD1 *)rxdp;
2685                         pci_unmap_single(sp->pdev,
2686                                          (dma_addr_t)rxdp1->Buffer0_ptr,
2687                                          dev->mtu +
2688                                          HEADER_ETHERNET_II_802_3_SIZE +
2689                                          HEADER_802_2_SIZE + HEADER_SNAP_SIZE,
2690                                          PCI_DMA_FROMDEVICE);
2691                         memset(rxdp, 0, sizeof(struct RxD1));
2692                 } else if (sp->rxd_mode == RXD_MODE_3B) {
2693                         rxdp3 = (struct RxD3 *)rxdp;
2694                         pci_unmap_single(sp->pdev,
2695                                          (dma_addr_t)rxdp3->Buffer0_ptr,
2696                                          BUF0_LEN,
2697                                          PCI_DMA_FROMDEVICE);
2698                         pci_unmap_single(sp->pdev,
2699                                          (dma_addr_t)rxdp3->Buffer1_ptr,
2700                                          BUF1_LEN,
2701                                          PCI_DMA_FROMDEVICE);
2702                         pci_unmap_single(sp->pdev,
2703                                          (dma_addr_t)rxdp3->Buffer2_ptr,
2704                                          dev->mtu + 4,
2705                                          PCI_DMA_FROMDEVICE);
2706                         memset(rxdp, 0, sizeof(struct RxD3));
2707                 }
2708                 swstats->mem_freed += skb->truesize;
2709                 dev_kfree_skb(skb);
2710                 mac_control->rings[ring_no].rx_bufs_left -= 1;
2711         }
2712 }
2713
2714 /**
2715  *  free_rx_buffers - Frees all Rx buffers
2716  *  @sp: device private variable.
2717  *  Description:
2718  *  This function will free all Rx buffers allocated by host.
2719  *  Return Value:
2720  *  NONE.
2721  */
2722
2723 static void free_rx_buffers(struct s2io_nic *sp)
2724 {
2725         struct net_device *dev = sp->dev;
2726         int i, blk = 0, buf_cnt = 0;
2727         struct config_param *config = &sp->config;
2728         struct mac_info *mac_control = &sp->mac_control;
2729
2730         for (i = 0; i < config->rx_ring_num; i++) {
2731                 struct ring_info *ring = &mac_control->rings[i];
2732
2733                 for (blk = 0; blk < rx_ring_sz[i]; blk++)
2734                         free_rxd_blk(sp, i, blk);
2735
2736                 ring->rx_curr_put_info.block_index = 0;
2737                 ring->rx_curr_get_info.block_index = 0;
2738                 ring->rx_curr_put_info.offset = 0;
2739                 ring->rx_curr_get_info.offset = 0;
2740                 ring->rx_bufs_left = 0;
2741                 DBG_PRINT(INIT_DBG, "%s: Freed 0x%x Rx Buffers on ring%d\n",
2742                           dev->name, buf_cnt, i);
2743         }
2744 }
2745
2746 static int s2io_chk_rx_buffers(struct s2io_nic *nic, struct ring_info *ring)
2747 {
2748         if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) {
2749                 DBG_PRINT(INFO_DBG, "%s: Out of memory in Rx Intr!!\n",
2750                           ring->dev->name);
2751         }
2752         return 0;
2753 }
2754
2755 /**
2756  * s2io_poll - Rx interrupt handler for NAPI support
2757  * @napi : pointer to the napi structure.
2758  * @budget : The number of packets that were budgeted to be processed
2759  * during  one pass through the 'Poll" function.
2760  * Description:
2761  * Comes into picture only if NAPI support has been incorporated. It does
2762  * the same thing that rx_intr_handler does, but not in a interrupt context
2763  * also It will process only a given number of packets.
2764  * Return value:
2765  * 0 on success and 1 if there are No Rx packets to be processed.
2766  */
2767
2768 static int s2io_poll_msix(struct napi_struct *napi, int budget)
2769 {
2770         struct ring_info *ring = container_of(napi, struct ring_info, napi);
2771         struct net_device *dev = ring->dev;
2772         int pkts_processed = 0;
2773         u8 __iomem *addr = NULL;
2774         u8 val8 = 0;
2775         struct s2io_nic *nic = netdev_priv(dev);
2776         struct XENA_dev_config __iomem *bar0 = nic->bar0;
2777         int budget_org = budget;
2778
2779         if (unlikely(!is_s2io_card_up(nic)))
2780                 return 0;
2781
2782         pkts_processed = rx_intr_handler(ring, budget);
2783         s2io_chk_rx_buffers(nic, ring);
2784
2785         if (pkts_processed < budget_org) {
2786                 napi_complete(napi);
2787                 /*Re Enable MSI-Rx Vector*/
2788                 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
2789                 addr += 7 - ring->ring_no;
2790                 val8 = (ring->ring_no == 0) ? 0x3f : 0xbf;
2791                 writeb(val8, addr);
2792                 val8 = readb(addr);
2793         }
2794         return pkts_processed;
2795 }
2796
2797 static int s2io_poll_inta(struct napi_struct *napi, int budget)
2798 {
2799         struct s2io_nic *nic = container_of(napi, struct s2io_nic, napi);
2800         int pkts_processed = 0;
2801         int ring_pkts_processed, i;
2802         struct XENA_dev_config __iomem *bar0 = nic->bar0;
2803         int budget_org = budget;
2804         struct config_param *config = &nic->config;
2805         struct mac_info *mac_control = &nic->mac_control;
2806
2807         if (unlikely(!is_s2io_card_up(nic)))
2808                 return 0;
2809
2810         for (i = 0; i < config->rx_ring_num; i++) {
2811                 struct ring_info *ring = &mac_control->rings[i];
2812                 ring_pkts_processed = rx_intr_handler(ring, budget);
2813                 s2io_chk_rx_buffers(nic, ring);
2814                 pkts_processed += ring_pkts_processed;
2815                 budget -= ring_pkts_processed;
2816                 if (budget <= 0)
2817                         break;
2818         }
2819         if (pkts_processed < budget_org) {
2820                 napi_complete(napi);
2821                 /* Re enable the Rx interrupts for the ring */
2822                 writeq(0, &bar0->rx_traffic_mask);
2823                 readl(&bar0->rx_traffic_mask);
2824         }
2825         return pkts_processed;
2826 }
2827
2828 #ifdef CONFIG_NET_POLL_CONTROLLER
2829 /**
2830  * s2io_netpoll - netpoll event handler entry point
2831  * @dev : pointer to the device structure.
2832  * Description:
2833  *      This function will be called by upper layer to check for events on the
2834  * interface in situations where interrupts are disabled. It is used for
2835  * specific in-kernel networking tasks, such as remote consoles and kernel
2836  * debugging over the network (example netdump in RedHat).
2837  */
2838 static void s2io_netpoll(struct net_device *dev)
2839 {
2840         struct s2io_nic *nic = netdev_priv(dev);
2841         const int irq = nic->pdev->irq;
2842         struct XENA_dev_config __iomem *bar0 = nic->bar0;
2843         u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
2844         int i;
2845         struct config_param *config = &nic->config;
2846         struct mac_info *mac_control = &nic->mac_control;
2847
2848         if (pci_channel_offline(nic->pdev))
2849                 return;
2850
2851         disable_irq(irq);
2852
2853         writeq(val64, &bar0->rx_traffic_int);
2854         writeq(val64, &bar0->tx_traffic_int);
2855
2856         /* we need to free up the transmitted skbufs or else netpoll will
2857          * run out of skbs and will fail and eventually netpoll application such
2858          * as netdump will fail.
2859          */
2860         for (i = 0; i < config->tx_fifo_num; i++)
2861                 tx_intr_handler(&mac_control->fifos[i]);
2862
2863         /* check for received packet and indicate up to network */
2864         for (i = 0; i < config->rx_ring_num; i++) {
2865                 struct ring_info *ring = &mac_control->rings[i];
2866
2867                 rx_intr_handler(ring, 0);
2868         }
2869
2870         for (i = 0; i < config->rx_ring_num; i++) {
2871                 struct ring_info *ring = &mac_control->rings[i];
2872
2873                 if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) {
2874                         DBG_PRINT(INFO_DBG,
2875                                   "%s: Out of memory in Rx Netpoll!!\n",
2876                                   dev->name);
2877                         break;
2878                 }
2879         }
2880         enable_irq(irq);
2881 }
2882 #endif
2883
2884 /**
2885  *  rx_intr_handler - Rx interrupt handler
2886  *  @ring_info: per ring structure.
2887  *  @budget: budget for napi processing.
2888  *  Description:
2889  *  If the interrupt is because of a received frame or if the
2890  *  receive ring contains fresh as yet un-processed frames,this function is
2891  *  called. It picks out the RxD at which place the last Rx processing had
2892  *  stopped and sends the skb to the OSM's Rx handler and then increments
2893  *  the offset.
2894  *  Return Value:
2895  *  No. of napi packets processed.
2896  */
2897 static int rx_intr_handler(struct ring_info *ring_data, int budget)
2898 {
2899         int get_block, put_block;
2900         struct rx_curr_get_info get_info, put_info;
2901         struct RxD_t *rxdp;
2902         struct sk_buff *skb;
2903         int pkt_cnt = 0, napi_pkts = 0;
2904         int i;
2905         struct RxD1 *rxdp1;
2906         struct RxD3 *rxdp3;
2907
2908         if (budget <= 0)
2909                 return napi_pkts;
2910
2911         get_info = ring_data->rx_curr_get_info;
2912         get_block = get_info.block_index;
2913         memcpy(&put_info, &ring_data->rx_curr_put_info, sizeof(put_info));
2914         put_block = put_info.block_index;
2915         rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
2916
2917         while (RXD_IS_UP2DT(rxdp)) {
2918                 /*
2919                  * If your are next to put index then it's
2920                  * FIFO full condition
2921                  */
2922                 if ((get_block == put_block) &&
2923                     (get_info.offset + 1) == put_info.offset) {
2924                         DBG_PRINT(INTR_DBG, "%s: Ring Full\n",
2925                                   ring_data->dev->name);
2926                         break;
2927                 }
2928                 skb = (struct sk_buff *)((unsigned long)rxdp->Host_Control);
2929                 if (skb == NULL) {
2930                         DBG_PRINT(ERR_DBG, "%s: NULL skb in Rx Intr\n",
2931                                   ring_data->dev->name);
2932                         return 0;
2933                 }
2934                 if (ring_data->rxd_mode == RXD_MODE_1) {
2935                         rxdp1 = (struct RxD1 *)rxdp;
2936                         pci_unmap_single(ring_data->pdev, (dma_addr_t)
2937                                          rxdp1->Buffer0_ptr,
2938                                          ring_data->mtu +
2939                                          HEADER_ETHERNET_II_802_3_SIZE +
2940                                          HEADER_802_2_SIZE +
2941                                          HEADER_SNAP_SIZE,
2942                                          PCI_DMA_FROMDEVICE);
2943                 } else if (ring_data->rxd_mode == RXD_MODE_3B) {
2944                         rxdp3 = (struct RxD3 *)rxdp;
2945                         pci_dma_sync_single_for_cpu(ring_data->pdev,
2946                                                     (dma_addr_t)rxdp3->Buffer0_ptr,
2947                                                     BUF0_LEN,
2948                                                     PCI_DMA_FROMDEVICE);
2949                         pci_unmap_single(ring_data->pdev,
2950                                          (dma_addr_t)rxdp3->Buffer2_ptr,
2951                                          ring_data->mtu + 4,
2952                                          PCI_DMA_FROMDEVICE);
2953                 }
2954                 prefetch(skb->data);
2955                 rx_osm_handler(ring_data, rxdp);
2956                 get_info.offset++;
2957                 ring_data->rx_curr_get_info.offset = get_info.offset;
2958                 rxdp = ring_data->rx_blocks[get_block].
2959                         rxds[get_info.offset].virt_addr;
2960                 if (get_info.offset == rxd_count[ring_data->rxd_mode]) {
2961                         get_info.offset = 0;
2962                         ring_data->rx_curr_get_info.offset = get_info.offset;
2963                         get_block++;
2964                         if (get_block == ring_data->block_count)
2965                                 get_block = 0;
2966                         ring_data->rx_curr_get_info.block_index = get_block;
2967                         rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
2968                 }
2969
2970                 if (ring_data->nic->config.napi) {
2971                         budget--;
2972                         napi_pkts++;
2973                         if (!budget)
2974                                 break;
2975                 }
2976                 pkt_cnt++;
2977                 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
2978                         break;
2979         }
2980         if (ring_data->lro) {
2981                 /* Clear all LRO sessions before exiting */
2982                 for (i = 0; i < MAX_LRO_SESSIONS; i++) {
2983                         struct lro *lro = &ring_data->lro0_n[i];
2984                         if (lro->in_use) {
2985                                 update_L3L4_header(ring_data->nic, lro);
2986                                 queue_rx_frame(lro->parent, lro->vlan_tag);
2987                                 clear_lro_session(lro);
2988                         }
2989                 }
2990         }
2991         return napi_pkts;
2992 }
2993
2994 /**
2995  *  tx_intr_handler - Transmit interrupt handler
2996  *  @nic : device private variable
2997  *  Description:
2998  *  If an interrupt was raised to indicate DMA complete of the
2999  *  Tx packet, this function is called. It identifies the last TxD
3000  *  whose buffer was freed and frees all skbs whose data have already
3001  *  DMA'ed into the NICs internal memory.
3002  *  Return Value:
3003  *  NONE
3004  */
3005
3006 static void tx_intr_handler(struct fifo_info *fifo_data)
3007 {
3008         struct s2io_nic *nic = fifo_data->nic;
3009         struct tx_curr_get_info get_info, put_info;
3010         struct sk_buff *skb = NULL;
3011         struct TxD *txdlp;
3012         int pkt_cnt = 0;
3013         unsigned long flags = 0;
3014         u8 err_mask;
3015         struct stat_block *stats = nic->mac_control.stats_info;
3016         struct swStat *swstats = &stats->sw_stat;
3017
3018         if (!spin_trylock_irqsave(&fifo_data->tx_lock, flags))
3019                 return;
3020
3021         get_info = fifo_data->tx_curr_get_info;
3022         memcpy(&put_info, &fifo_data->tx_curr_put_info, sizeof(put_info));
3023         txdlp = fifo_data->list_info[get_info.offset].list_virt_addr;
3024         while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
3025                (get_info.offset != put_info.offset) &&
3026                (txdlp->Host_Control)) {
3027                 /* Check for TxD errors */
3028                 if (txdlp->Control_1 & TXD_T_CODE) {
3029                         unsigned long long err;
3030                         err = txdlp->Control_1 & TXD_T_CODE;
3031                         if (err & 0x1) {
3032                                 swstats->parity_err_cnt++;
3033                         }
3034
3035                         /* update t_code statistics */
3036                         err_mask = err >> 48;
3037                         switch (err_mask) {
3038                         case 2:
3039                                 swstats->tx_buf_abort_cnt++;
3040                                 break;
3041
3042                         case 3:
3043                                 swstats->tx_desc_abort_cnt++;
3044                                 break;
3045
3046                         case 7:
3047                                 swstats->tx_parity_err_cnt++;
3048                                 break;
3049
3050                         case 10:
3051                                 swstats->tx_link_loss_cnt++;
3052                                 break;
3053
3054                         case 15:
3055                                 swstats->tx_list_proc_err_cnt++;
3056                                 break;
3057                         }
3058                 }
3059
3060                 skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
3061                 if (skb == NULL) {
3062                         spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
3063                         DBG_PRINT(ERR_DBG, "%s: NULL skb in Tx Free Intr\n",
3064                                   __func__);
3065                         return;
3066                 }
3067                 pkt_cnt++;
3068
3069                 /* Updating the statistics block */
3070                 swstats->mem_freed += skb->truesize;
3071                 dev_kfree_skb_irq(skb);
3072
3073                 get_info.offset++;
3074                 if (get_info.offset == get_info.fifo_len + 1)
3075                         get_info.offset = 0;
3076                 txdlp = fifo_data->list_info[get_info.offset].list_virt_addr;
3077                 fifo_data->tx_curr_get_info.offset = get_info.offset;
3078         }
3079
3080         s2io_wake_tx_queue(fifo_data, pkt_cnt, nic->config.multiq);
3081
3082         spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
3083 }
3084
3085 /**
3086  *  s2io_mdio_write - Function to write in to MDIO registers
3087  *  @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3088  *  @addr     : address value
3089  *  @value    : data value
3090  *  @dev      : pointer to net_device structure
3091  *  Description:
3092  *  This function is used to write values to the MDIO registers
3093  *  NONE
3094  */
3095 static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value,
3096                             struct net_device *dev)
3097 {
3098         u64 val64;
3099         struct s2io_nic *sp = netdev_priv(dev);
3100         struct XENA_dev_config __iomem *bar0 = sp->bar0;
3101
3102         /* address transaction */
3103         val64 = MDIO_MMD_INDX_ADDR(addr) |
3104                 MDIO_MMD_DEV_ADDR(mmd_type) |
3105                 MDIO_MMS_PRT_ADDR(0x0);
3106         writeq(val64, &bar0->mdio_control);
3107         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3108         writeq(val64, &bar0->mdio_control);
3109         udelay(100);
3110
3111         /* Data transaction */
3112         val64 = MDIO_MMD_INDX_ADDR(addr) |
3113                 MDIO_MMD_DEV_ADDR(mmd_type) |
3114                 MDIO_MMS_PRT_ADDR(0x0) |
3115                 MDIO_MDIO_DATA(value) |
3116                 MDIO_OP(MDIO_OP_WRITE_TRANS);
3117         writeq(val64, &bar0->mdio_control);
3118         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3119         writeq(val64, &bar0->mdio_control);
3120         udelay(100);
3121
3122         val64 = MDIO_MMD_INDX_ADDR(addr) |
3123                 MDIO_MMD_DEV_ADDR(mmd_type) |
3124                 MDIO_MMS_PRT_ADDR(0x0) |
3125                 MDIO_OP(MDIO_OP_READ_TRANS);
3126         writeq(val64, &bar0->mdio_control);
3127         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3128         writeq(val64, &bar0->mdio_control);
3129         udelay(100);
3130 }
3131
3132 /**
3133  *  s2io_mdio_read - Function to write in to MDIO registers
3134  *  @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3135  *  @addr     : address value
3136  *  @dev      : pointer to net_device structure
3137  *  Description:
3138  *  This function is used to read values to the MDIO registers
3139  *  NONE
3140  */
3141 static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
3142 {
3143         u64 val64 = 0x0;
3144         u64 rval64 = 0x0;
3145         struct s2io_nic *sp = netdev_priv(dev);
3146         struct XENA_dev_config __iomem *bar0 = sp->bar0;
3147
3148         /* address transaction */
3149         val64 = val64 | (MDIO_MMD_INDX_ADDR(addr)
3150                          | MDIO_MMD_DEV_ADDR(mmd_type)
3151                          | MDIO_MMS_PRT_ADDR(0x0));
3152         writeq(val64, &bar0->mdio_control);
3153         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3154         writeq(val64, &bar0->mdio_control);
3155         udelay(100);
3156
3157         /* Data transaction */
3158         val64 = MDIO_MMD_INDX_ADDR(addr) |
3159                 MDIO_MMD_DEV_ADDR(mmd_type) |
3160                 MDIO_MMS_PRT_ADDR(0x0) |
3161                 MDIO_OP(MDIO_OP_READ_TRANS);
3162         writeq(val64, &bar0->mdio_control);
3163         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3164         writeq(val64, &bar0->mdio_control);
3165         udelay(100);
3166
3167         /* Read the value from regs */
3168         rval64 = readq(&bar0->mdio_control);
3169         rval64 = rval64 & 0xFFFF0000;
3170         rval64 = rval64 >> 16;
3171         return rval64;
3172 }
3173
3174 /**
3175  *  s2io_chk_xpak_counter - Function to check the status of the xpak counters
3176  *  @counter      : counter value to be updated
3177  *  @flag         : flag to indicate the status
3178  *  @type         : counter type
3179  *  Description:
3180  *  This function is to check the status of the xpak counters value
3181  *  NONE
3182  */
3183
3184 static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index,
3185                                   u16 flag, u16 type)
3186 {
3187         u64 mask = 0x3;
3188         u64 val64;
3189         int i;
3190         for (i = 0; i < index; i++)
3191                 mask = mask << 0x2;
3192
3193         if (flag > 0) {
3194                 *counter = *counter + 1;
3195                 val64 = *regs_stat & mask;
3196                 val64 = val64 >> (index * 0x2);
3197                 val64 = val64 + 1;
3198                 if (val64 == 3) {
3199                         switch (type) {
3200                         case 1:
3201                                 DBG_PRINT(ERR_DBG,
3202                                           "Take Xframe NIC out of service.\n");
3203                                 DBG_PRINT(ERR_DBG,
3204 "Excessive temperatures may result in premature transceiver failure.\n");
3205                                 break;
3206                         case 2:
3207                                 DBG_PRINT(ERR_DBG,
3208                                           "Take Xframe NIC out of service.\n");
3209                                 DBG_PRINT(ERR_DBG,
3210 "Excessive bias currents may indicate imminent laser diode failure.\n");
3211                                 break;
3212                         case 3:
3213                                 DBG_PRINT(ERR_DBG,
3214                                           "Take Xframe NIC out of service.\n");
3215                                 DBG_PRINT(ERR_DBG,
3216 "Excessive laser output power may saturate far-end receiver.\n");
3217                                 break;
3218                         default:
3219                                 DBG_PRINT(ERR_DBG,
3220                                           "Incorrect XPAK Alarm type\n");
3221                         }
3222                         val64 = 0x0;
3223                 }
3224                 val64 = val64 << (index * 0x2);
3225                 *regs_stat = (*regs_stat & (~mask)) | (val64);
3226
3227         } else {
3228                 *regs_stat = *regs_stat & (~mask);
3229         }
3230 }
3231
3232 /**
3233  *  s2io_updt_xpak_counter - Function to update the xpak counters
3234  *  @dev         : pointer to net_device struct
3235  *  Description:
3236  *  This function is to upate the status of the xpak counters value
3237  *  NONE
3238  */
3239 static void s2io_updt_xpak_counter(struct net_device *dev)
3240 {
3241         u16 flag  = 0x0;
3242         u16 type  = 0x0;
3243         u16 val16 = 0x0;
3244         u64 val64 = 0x0;
3245         u64 addr  = 0x0;
3246
3247         struct s2io_nic *sp = netdev_priv(dev);
3248         struct stat_block *stats = sp->mac_control.stats_info;
3249         struct xpakStat *xstats = &stats->xpak_stat;
3250
3251         /* Check the communication with the MDIO slave */
3252         addr = MDIO_CTRL1;
3253         val64 = 0x0;
3254         val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3255         if ((val64 == 0xFFFF) || (val64 == 0x0000)) {
3256                 DBG_PRINT(ERR_DBG,
3257                           "ERR: MDIO slave access failed - Returned %llx\n",
3258                           (unsigned long long)val64);
3259                 return;
3260         }
3261
3262         /* Check for the expected value of control reg 1 */
3263         if (val64 != MDIO_CTRL1_SPEED10G) {
3264                 DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - "
3265                           "Returned: %llx- Expected: 0x%x\n",
3266                           (unsigned long long)val64, MDIO_CTRL1_SPEED10G);
3267                 return;
3268         }
3269
3270         /* Loading the DOM register to MDIO register */
3271         addr = 0xA100;
3272         s2io_mdio_write(MDIO_MMD_PMAPMD, addr, val16, dev);
3273         val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3274
3275         /* Reading the Alarm flags */
3276         addr = 0xA070;
3277         val64 = 0x0;
3278         val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3279
3280         flag = CHECKBIT(val64, 0x7);
3281         type = 1;
3282         s2io_chk_xpak_counter(&xstats->alarm_transceiver_temp_high,
3283                               &xstats->xpak_regs_stat,
3284                               0x0, flag, type);
3285
3286         if (CHECKBIT(val64, 0x6))
3287                 xstats->alarm_transceiver_temp_low++;
3288
3289         flag = CHECKBIT(val64, 0x3);
3290         type = 2;
3291         s2io_chk_xpak_counter(&xstats->alarm_laser_bias_current_high,
3292                               &xstats->xpak_regs_stat,
3293                               0x2, flag, type);
3294
3295         if (CHECKBIT(val64, 0x2))
3296                 xstats->alarm_laser_bias_current_low++;
3297
3298         flag = CHECKBIT(val64, 0x1);
3299         type = 3;
3300         s2io_chk_xpak_counter(&xstats->alarm_laser_output_power_high,
3301                               &xstats->xpak_regs_stat,
3302                               0x4, flag, type);
3303
3304         if (CHECKBIT(val64, 0x0))
3305                 xstats->alarm_laser_output_power_low++;
3306
3307         /* Reading the Warning flags */
3308         addr = 0xA074;
3309         val64 = 0x0;
3310         val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3311
3312         if (CHECKBIT(val64, 0x7))
3313                 xstats->warn_transceiver_temp_high++;
3314
3315         if (CHECKBIT(val64, 0x6))
3316                 xstats->warn_transceiver_temp_low++;
3317
3318         if (CHECKBIT(val64, 0x3))
3319                 xstats->warn_laser_bias_current_high++;
3320
3321         if (CHECKBIT(val64, 0x2))
3322                 xstats->warn_laser_bias_current_low++;
3323
3324         if (CHECKBIT(val64, 0x1))
3325                 xstats->warn_laser_output_power_high++;
3326
3327         if (CHECKBIT(val64, 0x0))
3328                 xstats->warn_laser_output_power_low++;
3329 }
3330
3331 /**
3332  *  wait_for_cmd_complete - waits for a command to complete.
3333  *  @sp : private member of the device structure, which is a pointer to the
3334  *  s2io_nic structure.
3335  *  Description: Function that waits for a command to Write into RMAC
3336  *  ADDR DATA registers to be completed and returns either success or
3337  *  error depending on whether the command was complete or not.
3338  *  Return value:
3339  *   SUCCESS on success and FAILURE on failure.
3340  */
3341
3342 static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
3343                                  int bit_state)
3344 {
3345         int ret = FAILURE, cnt = 0, delay = 1;
3346         u64 val64;
3347
3348         if ((bit_state != S2IO_BIT_RESET) && (bit_state != S2IO_BIT_SET))
3349                 return FAILURE;
3350
3351         do {
3352                 val64 = readq(addr);
3353                 if (bit_state == S2IO_BIT_RESET) {
3354                         if (!(val64 & busy_bit)) {
3355                                 ret = SUCCESS;
3356                                 break;
3357                         }
3358                 } else {
3359                         if (val64 & busy_bit) {
3360                                 ret = SUCCESS;
3361                                 break;
3362                         }
3363                 }
3364
3365                 if (in_interrupt())
3366                         mdelay(delay);
3367                 else
3368                         msleep(delay);
3369
3370                 if (++cnt >= 10)
3371                         delay = 50;
3372         } while (cnt < 20);
3373         return ret;
3374 }
3375 /**
3376  * check_pci_device_id - Checks if the device id is supported
3377  * @id : device id
3378  * Description: Function to check if the pci device id is supported by driver.
3379  * Return value: Actual device id if supported else PCI_ANY_ID
3380  */
3381 static u16 check_pci_device_id(u16 id)
3382 {
3383         switch (id) {
3384         case PCI_DEVICE_ID_HERC_WIN:
3385         case PCI_DEVICE_ID_HERC_UNI:
3386                 return XFRAME_II_DEVICE;
3387         case PCI_DEVICE_ID_S2IO_UNI:
3388         case PCI_DEVICE_ID_S2IO_WIN:
3389                 return XFRAME_I_DEVICE;
3390         default:
3391                 return PCI_ANY_ID;
3392         }
3393 }
3394
3395 /**
3396  *  s2io_reset - Resets the card.
3397  *  @sp : private member of the device structure.
3398  *  Description: Function to Reset the card. This function then also
3399  *  restores the previously saved PCI configuration space registers as
3400  *  the card reset also resets the configuration space.
3401  *  Return value:
3402  *  void.
3403  */
3404
3405 static void s2io_reset(struct s2io_nic *sp)
3406 {
3407         struct XENA_dev_config __iomem *bar0 = sp->bar0;
3408         u64 val64;
3409         u16 subid, pci_cmd;
3410         int i;
3411         u16 val16;
3412         unsigned long long up_cnt, down_cnt, up_time, down_time, reset_cnt;
3413         unsigned long long mem_alloc_cnt, mem_free_cnt, watchdog_cnt;
3414         struct stat_block *stats;
3415         struct swStat *swstats;
3416
3417         DBG_PRINT(INIT_DBG, "%s: Resetting XFrame card %s\n",
3418                   __func__, pci_name(sp->pdev));
3419
3420         /* Back up  the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
3421         pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
3422
3423         val64 = SW_RESET_ALL;
3424         writeq(val64, &bar0->sw_reset);
3425         if (strstr(sp->product_name, "CX4"))
3426                 msleep(750);
3427         msleep(250);
3428         for (i = 0; i < S2IO_MAX_PCI_CONFIG_SPACE_REINIT; i++) {
3429
3430                 /* Restore the PCI state saved during initialization. */
3431                 pci_restore_state(sp->pdev);
3432                 pci_save_state(sp->pdev);
3433                 pci_read_config_word(sp->pdev, 0x2, &val16);
3434                 if (check_pci_device_id(val16) != (u16)PCI_ANY_ID)
3435                         break;
3436                 msleep(200);
3437         }
3438
3439         if (check_pci_device_id(val16) == (u16)PCI_ANY_ID)
3440                 DBG_PRINT(ERR_DBG, "%s SW_Reset failed!\n", __func__);
3441
3442         pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, pci_cmd);
3443
3444         s2io_init_pci(sp);
3445
3446         /* Set swapper to enable I/O register access */
3447         s2io_set_swapper(sp);
3448
3449         /* restore mac_addr entries */
3450         do_s2io_restore_unicast_mc(sp);
3451
3452         /* Restore the MSIX table entries from local variables */
3453         restore_xmsi_data(sp);
3454
3455         /* Clear certain PCI/PCI-X fields after reset */
3456         if (sp->device_type == XFRAME_II_DEVICE) {
3457                 /* Clear "detected parity error" bit */
3458                 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
3459
3460                 /* Clearing PCIX Ecc status register */
3461                 pci_write_config_dword(sp->pdev, 0x68, 0x7C);
3462
3463                 /* Clearing PCI_STATUS error reflected here */
3464                 writeq(s2BIT(62), &bar0->txpic_int_reg);
3465         }
3466
3467         /* Reset device statistics maintained by OS */
3468         memset(&sp->stats, 0, sizeof(struct net_device_stats));
3469
3470         stats = sp->mac_control.stats_info;
3471         swstats = &stats->sw_stat;
3472
3473         /* save link up/down time/cnt, reset/memory/watchdog cnt */
3474         up_cnt = swstats->link_up_cnt;
3475         down_cnt = swstats->link_down_cnt;
3476         up_time = swstats->link_up_time;
3477         down_time = swstats->link_down_time;
3478         reset_cnt = swstats->soft_reset_cnt;
3479         mem_alloc_cnt = swstats->mem_allocated;
3480         mem_free_cnt = swstats->mem_freed;
3481         watchdog_cnt = swstats->watchdog_timer_cnt;
3482
3483         memset(stats, 0, sizeof(struct stat_block));
3484
3485         /* restore link up/down time/cnt, reset/memory/watchdog cnt */
3486         swstats->link_up_cnt = up_cnt;
3487         swstats->link_down_cnt = down_cnt;
3488         swstats->link_up_time = up_time;
3489         swstats->link_down_time = down_time;
3490         swstats->soft_reset_cnt = reset_cnt;
3491         swstats->mem_allocated = mem_alloc_cnt;
3492         swstats->mem_freed = mem_free_cnt;
3493         swstats->watchdog_timer_cnt = watchdog_cnt;
3494
3495         /* SXE-002: Configure link and activity LED to turn it off */
3496         subid = sp->pdev->subsystem_device;
3497         if (((subid & 0xFF) >= 0x07) &&
3498             (sp->device_type == XFRAME_I_DEVICE)) {
3499                 val64 = readq(&bar0->gpio_control);
3500                 val64 |= 0x0000800000000000ULL;
3501                 writeq(val64, &bar0->gpio_control);
3502                 val64 = 0x0411040400000000ULL;
3503                 writeq(val64, (void __iomem *)bar0 + 0x2700);
3504         }
3505
3506         /*
3507          * Clear spurious ECC interrupts that would have occurred on
3508          * XFRAME II cards after reset.
3509          */
3510         if (sp->device_type == XFRAME_II_DEVICE) {
3511                 val64 = readq(&bar0->pcc_err_reg);
3512                 writeq(val64, &bar0->pcc_err_reg);
3513         }
3514
3515         sp->device_enabled_once = false;
3516 }
3517
3518 /**
3519  *  s2io_set_swapper - to set the swapper controle on the card
3520  *  @sp : private member of the device structure,
3521  *  pointer to the s2io_nic structure.
3522  *  Description: Function to set the swapper control on the card
3523  *  correctly depending on the 'endianness' of the system.
3524  *  Return value:
3525  *  SUCCESS on success and FAILURE on failure.
3526  */
3527
3528 static int s2io_set_swapper(struct s2io_nic *sp)
3529 {
3530         struct net_device *dev = sp->dev;
3531         struct XENA_dev_config __iomem *bar0 = sp->bar0;
3532         u64 val64, valt, valr;
3533
3534         /*
3535          * Set proper endian settings and verify the same by reading
3536          * the PIF Feed-back register.
3537          */
3538
3539         val64 = readq(&bar0->pif_rd_swapper_fb);
3540         if (val64 != 0x0123456789ABCDEFULL) {
3541                 int i = 0;
3542                 static const u64 value[] = {
3543                         0xC30000C3C30000C3ULL,  /* FE=1, SE=1 */
3544                         0x8100008181000081ULL,  /* FE=1, SE=0 */
3545                         0x4200004242000042ULL,  /* FE=0, SE=1 */
3546                         0                       /* FE=0, SE=0 */
3547                 };
3548
3549                 while (i < 4) {
3550                         writeq(value[i], &bar0->swapper_ctrl);
3551                         val64 = readq(&bar0->pif_rd_swapper_fb);
3552                         if (val64 == 0x0123456789ABCDEFULL)
3553                                 break;
3554                         i++;
3555                 }
3556                 if (i == 4) {
3557                         DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, "
3558                                   "feedback read %llx\n",
3559                                   dev->name, (unsigned long long)val64);
3560                         return FAILURE;
3561                 }
3562                 valr = value[i];
3563         } else {
3564                 valr = readq(&bar0->swapper_ctrl);
3565         }
3566
3567         valt = 0x0123456789ABCDEFULL;
3568         writeq(valt, &bar0->xmsi_address);
3569         val64 = readq(&bar0->xmsi_address);
3570
3571         if (val64 != valt) {
3572                 int i = 0;
3573                 static const u64 value[] = {
3574                         0x00C3C30000C3C300ULL,  /* FE=1, SE=1 */
3575                         0x0081810000818100ULL,  /* FE=1, SE=0 */
3576                         0x0042420000424200ULL,  /* FE=0, SE=1 */
3577                         0                       /* FE=0, SE=0 */
3578                 };
3579
3580                 while (i < 4) {
3581                         writeq((value[i] | valr), &bar0->swapper_ctrl);
3582                         writeq(valt, &bar0->xmsi_address);
3583                         val64 = readq(&bar0->xmsi_address);
3584                         if (val64 == valt)
3585                                 break;
3586                         i++;
3587                 }
3588                 if (i == 4) {
3589                         unsigned long long x = val64;
3590                         DBG_PRINT(ERR_DBG,
3591                                   "Write failed, Xmsi_addr reads:0x%llx\n", x);
3592                         return FAILURE;
3593                 }
3594         }
3595         val64 = readq(&bar0->swapper_ctrl);
3596         val64 &= 0xFFFF000000000000ULL;
3597
3598 #ifdef __BIG_ENDIAN
3599         /*
3600          * The device by default set to a big endian format, so a
3601          * big endian driver need not set anything.
3602          */
3603         val64 |= (SWAPPER_CTRL_TXP_FE |
3604                   SWAPPER_CTRL_TXP_SE |
3605                   SWAPPER_CTRL_TXD_R_FE |
3606                   SWAPPER_CTRL_TXD_W_FE |
3607                   SWAPPER_CTRL_TXF_R_FE |
3608                   SWAPPER_CTRL_RXD_R_FE |
3609                   SWAPPER_CTRL_RXD_W_FE |
3610                   SWAPPER_CTRL_RXF_W_FE |
3611                   SWAPPER_CTRL_XMSI_FE |
3612                   SWAPPER_CTRL_STATS_FE |
3613                   SWAPPER_CTRL_STATS_SE);
3614         if (sp->config.intr_type == INTA)
3615                 val64 |= SWAPPER_CTRL_XMSI_SE;
3616         writeq(val64, &bar0->swapper_ctrl);
3617 #else
3618         /*
3619          * Initially we enable all bits to make it accessible by the
3620          * driver, then we selectively enable only those bits that
3621          * we want to set.
3622          */
3623         val64 |= (SWAPPER_CTRL_TXP_FE |
3624                   SWAPPER_CTRL_TXP_SE |
3625                   SWAPPER_CTRL_TXD_R_FE |
3626                   SWAPPER_CTRL_TXD_R_SE |
3627                   SWAPPER_CTRL_TXD_W_FE |
3628                   SWAPPER_CTRL_TXD_W_SE |
3629                   SWAPPER_CTRL_TXF_R_FE |
3630                   SWAPPER_CTRL_RXD_R_FE |
3631                   SWAPPER_CTRL_RXD_R_SE |
3632                   SWAPPER_CTRL_RXD_W_FE |
3633                   SWAPPER_CTRL_RXD_W_SE |
3634                   SWAPPER_CTRL_RXF_W_FE |
3635                   SWAPPER_CTRL_XMSI_FE |
3636                   SWAPPER_CTRL_STATS_FE |
3637                   SWAPPER_CTRL_STATS_SE);
3638         if (sp->config.intr_type == INTA)
3639                 val64 |= SWAPPER_CTRL_XMSI_SE;
3640         writeq(val64, &bar0->swapper_ctrl);
3641 #endif
3642         val64 = readq(&bar0->swapper_ctrl);
3643
3644         /*
3645          * Verifying if endian settings are accurate by reading a
3646          * feedback register.
3647          */
3648         val64 = readq(&bar0->pif_rd_swapper_fb);
3649         if (val64 != 0x0123456789ABCDEFULL) {
3650                 /* Endian settings are incorrect, calls for another dekko. */
3651                 DBG_PRINT(ERR_DBG,
3652                           "%s: Endian settings are wrong, feedback read %llx\n",
3653                           dev->name, (unsigned long long)val64);
3654                 return FAILURE;
3655         }
3656
3657         return SUCCESS;
3658 }
3659
3660 static int wait_for_msix_trans(struct s2io_nic *nic, int i)
3661 {
3662         struct XENA_dev_config __iomem *bar0 = nic->bar0;
3663         u64 val64;
3664         int ret = 0, cnt = 0;
3665
3666         do {
3667                 val64 = readq(&bar0->xmsi_access);
3668                 if (!(val64 & s2BIT(15)))
3669                         break;
3670                 mdelay(1);
3671                 cnt++;
3672         } while (cnt < 5);
3673         if (cnt == 5) {
3674                 DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
3675                 ret = 1;
3676         }
3677
3678         return ret;
3679 }
3680
3681 static void restore_xmsi_data(struct s2io_nic *nic)
3682 {
3683         struct XENA_dev_config __iomem *bar0 = nic->bar0;
3684         u64 val64;
3685         int i, msix_index;
3686
3687         if (nic->device_type == XFRAME_I_DEVICE)
3688                 return;
3689
3690         for (i = 0; i < MAX_REQUESTED_MSI_X; i++) {
3691                 msix_index = (i) ? ((i-1) * 8 + 1) : 0;
3692                 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3693                 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
3694                 val64 = (s2BIT(7) | s2BIT(15) | vBIT(msix_index, 26, 6));
3695                 writeq(val64, &bar0->xmsi_access);
3696                 if (wait_for_msix_trans(nic, msix_index)) {
3697                         DBG_PRINT(ERR_DBG, "%s: index: %d failed\n",
3698                                   __func__, msix_index);
3699                         continue;
3700                 }
3701         }
3702 }
3703
3704 static void store_xmsi_data(struct s2io_nic *nic)
3705 {
3706         struct XENA_dev_config __iomem *bar0 = nic->bar0;
3707         u64 val64, addr, data;
3708         int i, msix_index;
3709
3710         if (nic->device_type == XFRAME_I_DEVICE)
3711                 return;
3712
3713         /* Store and display */
3714         for (i = 0; i < MAX_REQUESTED_MSI_X; i++) {
3715                 msix_index = (i) ? ((i-1) * 8 + 1) : 0;
3716                 val64 = (s2BIT(15) | vBIT(msix_index, 26, 6));
3717                 writeq(val64, &bar0->xmsi_access);
3718                 if (wait_for_msix_trans(nic, msix_index)) {
3719                         DBG_PRINT(ERR_DBG, "%s: index: %d failed\n",
3720                                   __func__, msix_index);
3721                         continue;
3722                 }
3723                 addr = readq(&bar0->xmsi_address);
3724                 data = readq(&bar0->xmsi_data);
3725                 if (addr && data) {
3726                         nic->msix_info[i].addr = addr;
3727                         nic->msix_info[i].data = data;
3728                 }
3729         }
3730 }
3731
3732 static int s2io_enable_msi_x(struct s2io_nic *nic)
3733 {
3734         struct XENA_dev_config __iomem *bar0 = nic->bar0;
3735         u64 rx_mat;
3736         u16 msi_control; /* Temp variable */
3737         int ret, i, j, msix_indx = 1;
3738         int size;
3739         struct stat_block *stats = nic->mac_control.stats_info;
3740         struct swStat *swstats = &stats->sw_stat;
3741
3742         size = nic->num_entries * sizeof(struct msix_entry);
3743         nic->entries = kzalloc(size, GFP_KERNEL);
3744         if (!nic->entries) {
3745                 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
3746                           __func__);
3747                 swstats->mem_alloc_fail_cnt++;
3748                 return -ENOMEM;
3749         }
3750         swstats->mem_allocated += size;
3751
3752         size = nic->num_entries * sizeof(struct s2io_msix_entry);
3753         nic->s2io_entries = kzalloc(size, GFP_KERNEL);
3754         if (!nic->s2io_entries) {
3755                 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
3756                           __func__);
3757                 swstats->mem_alloc_fail_cnt++;
3758                 kfree(nic->entries);
3759                 swstats->mem_freed
3760                         += (nic->num_entries * sizeof(struct msix_entry));
3761                 return -ENOMEM;
3762         }
3763         swstats->mem_allocated += size;
3764
3765         nic->entries[0].entry = 0;
3766         nic->s2io_entries[0].entry = 0;
3767         nic->s2io_entries[0].in_use = MSIX_FLG;
3768         nic->s2io_entries[0].type = MSIX_ALARM_TYPE;
3769         nic->s2io_entries[0].arg = &nic->mac_control.fifos;
3770
3771         for (i = 1; i < nic->num_entries; i++) {
3772                 nic->entries[i].entry = ((i - 1) * 8) + 1;
3773                 nic->s2io_entries[i].entry = ((i - 1) * 8) + 1;
3774                 nic->s2io_entries[i].arg = NULL;
3775                 nic->s2io_entries[i].in_use = 0;
3776         }
3777
3778         rx_mat = readq(&bar0->rx_mat);
3779         for (j = 0; j < nic->config.rx_ring_num; j++) {
3780                 rx_mat |= RX_MAT_SET(j, msix_indx);
3781                 nic->s2io_entries[j+1].arg = &nic->mac_control.rings[j];
3782                 nic->s2io_entries[j+1].type = MSIX_RING_TYPE;
3783                 nic->s2io_entries[j+1].in_use = MSIX_FLG;
3784                 msix_indx += 8;
3785         }
3786         writeq(rx_mat, &bar0->rx_mat);
3787         readq(&bar0->rx_mat);
3788
3789         ret = pci_enable_msix_range(nic->pdev, nic->entries,
3790                                     nic->num_entries, nic->num_entries);
3791         /* We fail init if error or we get less vectors than min required */
3792         if (ret < 0) {
3793                 DBG_PRINT(ERR_DBG, "Enabling MSI-X failed\n");
3794                 kfree(nic->entries);
3795                 swstats->mem_freed += nic->num_entries *
3796                         sizeof(struct msix_entry);
3797                 kfree(nic->s2io_entries);
3798                 swstats->mem_freed += nic->num_entries *
3799                         sizeof(struct s2io_msix_entry);
3800                 nic->entries = NULL;
3801                 nic->s2io_entries = NULL;
3802                 return -ENOMEM;
3803         }
3804
3805         /*
3806          * To enable MSI-X, MSI also needs to be enabled, due to a bug
3807          * in the herc NIC. (Temp change, needs to be removed later)
3808          */
3809         pci_read_config_word(nic->pdev, 0x42, &msi_control);
3810         msi_control |= 0x1; /* Enable MSI */
3811         pci_write_config_word(nic->pdev, 0x42, msi_control);
3812
3813         return 0;
3814 }
3815
3816 /* Handle software interrupt used during MSI(X) test */
3817 static irqreturn_t s2io_test_intr(int irq, void *dev_id)
3818 {
3819         struct s2io_nic *sp = dev_id;
3820
3821         sp->msi_detected = 1;
3822         wake_up(&sp->msi_wait);
3823
3824         return IRQ_HANDLED;
3825 }
3826
3827 /* Test interrupt path by forcing a a software IRQ */
3828 static int s2io_test_msi(struct s2io_nic *sp)
3829 {
3830         struct pci_dev *pdev = sp->pdev;
3831         struct XENA_dev_config __iomem *bar0 = sp->bar0;
3832         int err;
3833         u64 val64, saved64;
3834
3835         err = request_irq(sp->entries[1].vector, s2io_test_intr, 0,
3836                           sp->name, sp);
3837         if (err) {
3838                 DBG_PRINT(ERR_DBG, "%s: PCI %s: cannot assign irq %d\n",
3839                           sp->dev->name, pci_name(pdev), pdev->irq);
3840                 return err;
3841         }
3842
3843         init_waitqueue_head(&sp->msi_wait);
3844         sp->msi_detected = 0;
3845
3846         saved64 = val64 = readq(&bar0->scheduled_int_ctrl);
3847         val64 |= SCHED_INT_CTRL_ONE_SHOT;
3848         val64 |= SCHED_INT_CTRL_TIMER_EN;
3849         val64 |= SCHED_INT_CTRL_INT2MSI(1);
3850         writeq(val64, &bar0->scheduled_int_ctrl);
3851
3852         wait_event_timeout(sp->msi_wait, sp->msi_detected, HZ/10);
3853
3854         if (!sp->msi_detected) {
3855                 /* MSI(X) test failed, go back to INTx mode */
3856                 DBG_PRINT(ERR_DBG, "%s: PCI %s: No interrupt was generated "
3857                           "using MSI(X) during test\n",
3858                           sp->dev->name, pci_name(pdev));
3859
3860                 err = -EOPNOTSUPP;
3861         }
3862
3863         free_irq(sp->entries[1].vector, sp);
3864
3865         writeq(saved64, &bar0->scheduled_int_ctrl);
3866
3867         return err;
3868 }
3869
3870 static void remove_msix_isr(struct s2io_nic *sp)
3871 {
3872         int i;
3873         u16 msi_control;
3874
3875         for (i = 0; i < sp->num_entries; i++) {
3876                 if (sp->s2io_entries[i].in_use == MSIX_REGISTERED_SUCCESS) {
3877                         int vector = sp->entries[i].vector;
3878                         void *arg = sp->s2io_entries[i].arg;
3879                         free_irq(vector, arg);
3880                 }
3881         }
3882
3883         kfree(sp->entries);
3884         kfree(sp->s2io_entries);
3885         sp->entries = NULL;
3886         sp->s2io_entries = NULL;
3887
3888         pci_read_config_word(sp->pdev, 0x42, &msi_control);
3889         msi_control &= 0xFFFE; /* Disable MSI */
3890         pci_write_config_word(sp->pdev, 0x42, msi_control);
3891
3892         pci_disable_msix(sp->pdev);
3893 }
3894
3895 static void remove_inta_isr(struct s2io_nic *sp)
3896 {
3897         free_irq(sp->pdev->irq, sp->dev);
3898 }
3899
3900 /* ********************************************************* *
3901  * Functions defined below concern the OS part of the driver *
3902  * ********************************************************* */
3903
3904 /**
3905  *  s2io_open - open entry point of the driver
3906  *  @dev : pointer to the device structure.
3907  *  Description:
3908  *  This function is the open entry point of the driver. It mainly calls a
3909  *  function to allocate Rx buffers and inserts them into the buffer
3910  *  descriptors and then enables the Rx part of the NIC.
3911  *  Return value:
3912  *  0 on success and an appropriate (-)ve integer as defined in errno.h
3913  *   file on failure.
3914  */
3915
3916 static int s2io_open(struct net_device *dev)
3917 {
3918         struct s2io_nic *sp = netdev_priv(dev);
3919         struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
3920         int err = 0;
3921
3922         /*
3923          * Make sure you have link off by default every time
3924          * Nic is initialized
3925          */
3926         netif_carrier_off(dev);
3927         sp->last_link_state = 0;
3928
3929         /* Initialize H/W and enable interrupts */
3930         err = s2io_card_up(sp);
3931         if (err) {
3932                 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
3933                           dev->name);
3934                 goto hw_init_failed;
3935         }
3936
3937         if (do_s2io_prog_unicast(dev, dev->dev_addr) == FAILURE) {
3938                 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
3939                 s2io_card_down(sp);
3940                 err = -ENODEV;
3941                 goto hw_init_failed;
3942         }
3943         s2io_start_all_tx_queue(sp);
3944         return 0;
3945
3946 hw_init_failed:
3947         if (sp->config.intr_type == MSI_X) {
3948                 if (sp->entries) {
3949                         kfree(sp->entries);
3950                         swstats->mem_freed += sp->num_entries *
3951                                 sizeof(struct msix_entry);
3952                 }
3953                 if (sp->s2io_entries) {
3954                         kfree(sp->s2io_entries);
3955                         swstats->mem_freed += sp->num_entries *
3956                                 sizeof(struct s2io_msix_entry);
3957                 }
3958         }
3959         return err;
3960 }
3961
3962 /**
3963  *  s2io_close -close entry point of the driver
3964  *  @dev : device pointer.
3965  *  Description:
3966  *  This is the stop entry point of the driver. It needs to undo exactly
3967  *  whatever was done by the open entry point,thus it's usually referred to
3968  *  as the close function.Among other things this function mainly stops the
3969  *  Rx side of the NIC and frees all the Rx buffers in the Rx rings.
3970  *  Return value:
3971  *  0 on success and an appropriate (-)ve integer as defined in errno.h
3972  *  file on failure.
3973  */
3974
3975 static int s2io_close(struct net_device *dev)
3976 {
3977         struct s2io_nic *sp = netdev_priv(dev);
3978         struct config_param *config = &sp->config;
3979         u64 tmp64;
3980         int offset;
3981
3982         /* Return if the device is already closed               *
3983          *  Can happen when s2io_card_up failed in change_mtu    *
3984          */
3985         if (!is_s2io_card_up(sp))
3986                 return 0;
3987
3988         s2io_stop_all_tx_queue(sp);
3989         /* delete all populated mac entries */
3990         for (offset = 1; offset < config->max_mc_addr; offset++) {
3991                 tmp64 = do_s2io_read_unicast_mc(sp, offset);
3992                 if (tmp64 != S2IO_DISABLE_MAC_ENTRY)
3993                         do_s2io_delete_unicast_mc(sp, tmp64);
3994         }
3995
3996         s2io_card_down(sp);
3997
3998         return 0;
3999 }
4000
4001 /**
4002  *  s2io_xmit - Tx entry point of te driver
4003  *  @skb : the socket buffer containing the Tx data.
4004  *  @dev : device pointer.
4005  *  Description :
4006  *  This function is the Tx entry point of the driver. S2IO NIC supports
4007  *  certain protocol assist features on Tx side, namely  CSO, S/G, LSO.
4008  *  NOTE: when device can't queue the pkt,just the trans_start variable will
4009  *  not be upadted.
4010  *  Return value:
4011  *  0 on success & 1 on failure.
4012  */
4013
4014 static netdev_tx_t s2io_xmit(struct sk_buff *skb, struct net_device *dev)
4015 {
4016         struct s2io_nic *sp = netdev_priv(dev);
4017         u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
4018         register u64 val64;
4019         struct TxD *txdp;
4020         struct TxFIFO_element __iomem *tx_fifo;
4021         unsigned long flags = 0;
4022         u16 vlan_tag = 0;
4023         struct fifo_info *fifo = NULL;
4024         int offload_type;
4025         int enable_per_list_interrupt = 0;
4026         struct config_param *config = &sp->config;
4027         struct mac_info *mac_control = &sp->mac_control;
4028         struct stat_block *stats = mac_control->stats_info;
4029         struct swStat *swstats = &stats->sw_stat;
4030
4031         DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
4032
4033         if (unlikely(skb->len <= 0)) {
4034                 DBG_PRINT(TX_DBG, "%s: Buffer has no data..\n", dev->name);
4035                 dev_kfree_skb_any(skb);
4036                 return NETDEV_TX_OK;
4037         }
4038
4039         if (!is_s2io_card_up(sp)) {
4040                 DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
4041                           dev->name);
4042                 dev_kfree_skb_any(skb);
4043                 return NETDEV_TX_OK;
4044         }
4045
4046         queue = 0;
4047         if (skb_vlan_tag_present(skb))
4048                 vlan_tag = skb_vlan_tag_get(skb);
4049         if (sp->config.tx_steering_type == TX_DEFAULT_STEERING) {
4050                 if (skb->protocol == htons(ETH_P_IP)) {
4051                         struct iphdr *ip;
4052                         struct tcphdr *th;
4053                         ip = ip_hdr(skb);
4054
4055                         if (!ip_is_fragment(ip)) {
4056                                 th = (struct tcphdr *)(((unsigned char *)ip) +
4057                                                        ip->ihl*4);
4058
4059                                 if (ip->protocol == IPPROTO_TCP) {
4060                                         queue_len = sp->total_tcp_fifos;
4061                                         queue = (ntohs(th->source) +
4062                                                  ntohs(th->dest)) &
4063                                                 sp->fifo_selector[queue_len - 1];
4064                                         if (queue >= queue_len)
4065                                                 queue = queue_len - 1;
4066                                 } else if (ip->protocol == IPPROTO_UDP) {
4067                                         queue_len = sp->total_udp_fifos;
4068                                         queue = (ntohs(th->source) +
4069                                                  ntohs(th->dest)) &
4070                                                 sp->fifo_selector[queue_len - 1];
4071                                         if (queue >= queue_len)
4072                                                 queue = queue_len - 1;
4073                                         queue += sp->udp_fifo_idx;
4074                                         if (skb->len > 1024)
4075                                                 enable_per_list_interrupt = 1;
4076                                 }
4077                         }
4078                 }
4079         } else if (sp->config.tx_steering_type == TX_PRIORITY_STEERING)
4080                 /* get fifo number based on skb->priority value */
4081                 queue = config->fifo_mapping
4082                         [skb->priority & (MAX_TX_FIFOS - 1)];
4083         fifo = &mac_control->fifos[queue];
4084
4085         spin_lock_irqsave(&fifo->tx_lock, flags);
4086
4087         if (sp->config.multiq) {
4088                 if (__netif_subqueue_stopped(dev, fifo->fifo_no)) {
4089                         spin_unlock_irqrestore(&fifo->tx_lock, flags);
4090                         return NETDEV_TX_BUSY;
4091                 }
4092         } else if (unlikely(fifo->queue_state == FIFO_QUEUE_STOP)) {
4093                 if (netif_queue_stopped(dev)) {
4094                         spin_unlock_irqrestore(&fifo->tx_lock, flags);
4095                         return NETDEV_TX_BUSY;
4096                 }
4097         }
4098
4099         put_off = (u16)fifo->tx_curr_put_info.offset;
4100         get_off = (u16)fifo->tx_curr_get_info.offset;
4101         txdp = fifo->list_info[put_off].list_virt_addr;
4102
4103         queue_len = fifo->tx_curr_put_info.fifo_len + 1;
4104         /* Avoid "put" pointer going beyond "get" pointer */
4105         if (txdp->Host_Control ||
4106             ((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
4107                 DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
4108                 s2io_stop_tx_queue(sp, fifo->fifo_no);
4109                 dev_kfree_skb_any(skb);
4110                 spin_unlock_irqrestore(&fifo->tx_lock, flags);
4111                 return NETDEV_TX_OK;
4112         }
4113
4114         offload_type = s2io_offload_type(skb);
4115         if (offload_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
4116                 txdp->Control_1 |= TXD_TCP_LSO_EN;
4117                 txdp->Control_1 |= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb));
4118         }
4119         if (skb->ip_summed == CHECKSUM_PARTIAL) {
4120                 txdp->Control_2 |= (TXD_TX_CKO_IPV4_EN |
4121                                     TXD_TX_CKO_TCP_EN |
4122                                     TXD_TX_CKO_UDP_EN);
4123         }
4124         txdp->Control_1 |= TXD_GATHER_CODE_FIRST;
4125         txdp->Control_1 |= TXD_LIST_OWN_XENA;
4126         txdp->Control_2 |= TXD_INT_NUMBER(fifo->fifo_no);
4127         if (enable_per_list_interrupt)
4128                 if (put_off & (queue_len >> 5))
4129                         txdp->Control_2 |= TXD_INT_TYPE_PER_LIST;
4130         if (vlan_tag) {
4131                 txdp->Control_2 |= TXD_VLAN_ENABLE;
4132                 txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
4133         }
4134
4135         frg_len = skb_headlen(skb);
4136         if (offload_type == SKB_GSO_UDP) {
4137                 int ufo_size;
4138
4139                 ufo_size = s2io_udp_mss(skb);
4140                 ufo_size &= ~7;
4141                 txdp->Control_1 |= TXD_UFO_EN;
4142                 txdp->Control_1 |= TXD_UFO_MSS(ufo_size);
4143                 txdp->Control_1 |= TXD_BUFFER0_SIZE(8);
4144 #ifdef __BIG_ENDIAN
4145                 /* both variants do cpu_to_be64(be32_to_cpu(...)) */
4146                 fifo->ufo_in_band_v[put_off] =
4147                         (__force u64)skb_shinfo(skb)->ip6_frag_id;
4148 #else
4149                 fifo->ufo_in_band_v[put_off] =
4150                         (__force u64)skb_shinfo(skb)->ip6_frag_id << 32;
4151 #endif
4152                 txdp->Host_Control = (unsigned long)fifo->ufo_in_band_v;
4153                 txdp->Buffer_Pointer = pci_map_single(sp->pdev,
4154                                                       fifo->ufo_in_band_v,
4155                                                       sizeof(u64),
4156                                                       PCI_DMA_TODEVICE);
4157                 if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer))
4158                         goto pci_map_failed;
4159                 txdp++;
4160         }
4161
4162         txdp->Buffer_Pointer = pci_map_single(sp->pdev, skb->data,
4163                                               frg_len, PCI_DMA_TODEVICE);
4164         if (pci_dma_mapping_error(sp->pdev, txdp->Buffer_Pointer))
4165                 goto pci_map_failed;
4166
4167         txdp->Host_Control = (unsigned long)skb;
4168         txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len);
4169         if (offload_type == SKB_GSO_UDP)
4170                 txdp->Control_1 |= TXD_UFO_EN;
4171
4172         frg_cnt = skb_shinfo(skb)->nr_frags;
4173         /* For fragmented SKB. */
4174         for (i = 0; i < frg_cnt; i++) {
4175                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4176                 /* A '0' length fragment will be ignored */
4177                 if (!skb_frag_size(frag))
4178                         continue;
4179                 txdp++;
4180                 txdp->Buffer_Pointer = (u64)skb_frag_dma_map(&sp->pdev->dev,
4181                                                              frag, 0,
4182                                                              skb_frag_size(frag),
4183                                                              DMA_TO_DEVICE);
4184                 txdp->Control_1 = TXD_BUFFER0_SIZE(skb_frag_size(frag));
4185                 if (offload_type == SKB_GSO_UDP)
4186                         txdp->Control_1 |= TXD_UFO_EN;
4187         }
4188         txdp->Control_1 |= TXD_GATHER_CODE_LAST;
4189
4190         if (offload_type == SKB_GSO_UDP)
4191                 frg_cnt++; /* as Txd0 was used for inband header */
4192
4193         tx_fifo = mac_control->tx_FIFO_start[queue];
4194         val64 = fifo->list_info[put_off].list_phy_addr;
4195         writeq(val64, &tx_fifo->TxDL_Pointer);
4196
4197         val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
4198                  TX_FIFO_LAST_LIST);
4199         if (offload_type)
4200                 val64 |= TX_FIFO_SPECIAL_FUNC;
4201
4202         writeq(val64, &tx_fifo->List_Control);
4203
4204         mmiowb();
4205
4206         put_off++;
4207         if (put_off == fifo->tx_curr_put_info.fifo_len + 1)
4208                 put_off = 0;
4209         fifo->tx_curr_put_info.offset = put_off;
4210
4211         /* Avoid "put" pointer going beyond "get" pointer */
4212         if (((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
4213                 swstats->fifo_full_cnt++;
4214                 DBG_PRINT(TX_DBG,
4215                           "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
4216                           put_off, get_off);
4217                 s2io_stop_tx_queue(sp, fifo->fifo_no);
4218         }
4219         swstats->mem_allocated += skb->truesize;
4220         spin_unlock_irqrestore(&fifo->tx_lock, flags);
4221
4222         if (sp->config.intr_type == MSI_X)
4223                 tx_intr_handler(fifo);
4224
4225         return NETDEV_TX_OK;
4226
4227 pci_map_failed:
4228         swstats->pci_map_fail_cnt++;
4229         s2io_stop_tx_queue(sp, fifo->fifo_no);
4230         swstats->mem_freed += skb->truesize;
4231         dev_kfree_skb_any(skb);
4232         spin_unlock_irqrestore(&fifo->tx_lock, flags);
4233         return NETDEV_TX_OK;
4234 }
4235
4236 static void
4237 s2io_alarm_handle(unsigned long data)
4238 {
4239         struct s2io_nic *sp = (struct s2io_nic *)data;
4240         struct net_device *dev = sp->dev;
4241
4242         s2io_handle_errors(dev);
4243         mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
4244 }
4245
4246 static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id)
4247 {
4248         struct ring_info *ring = (struct ring_info *)dev_id;
4249         struct s2io_nic *sp = ring->nic;
4250         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4251
4252         if (unlikely(!is_s2io_card_up(sp)))
4253                 return IRQ_HANDLED;
4254
4255         if (sp->config.napi) {
4256                 u8 __iomem *addr = NULL;
4257                 u8 val8 = 0;
4258
4259                 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
4260                 addr += (7 - ring->ring_no);
4261                 val8 = (ring->ring_no == 0) ? 0x7f : 0xff;
4262                 writeb(val8, addr);
4263                 val8 = readb(addr);
4264                 napi_schedule(&ring->napi);
4265         } else {
4266                 rx_intr_handler(ring, 0);
4267                 s2io_chk_rx_buffers(sp, ring);
4268         }
4269
4270         return IRQ_HANDLED;
4271 }
4272
4273 static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id)
4274 {
4275         int i;
4276         struct fifo_info *fifos = (struct fifo_info *)dev_id;
4277         struct s2io_nic *sp = fifos->nic;
4278         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4279         struct config_param *config  = &sp->config;
4280         u64 reason;
4281
4282         if (unlikely(!is_s2io_card_up(sp)))
4283                 return IRQ_NONE;
4284
4285         reason = readq(&bar0->general_int_status);
4286         if (unlikely(reason == S2IO_MINUS_ONE))
4287                 /* Nothing much can be done. Get out */
4288                 return IRQ_HANDLED;
4289
4290         if (reason & (GEN_INTR_TXPIC | GEN_INTR_TXTRAFFIC)) {
4291                 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4292
4293                 if (reason & GEN_INTR_TXPIC)
4294                         s2io_txpic_intr_handle(sp);
4295
4296                 if (reason & GEN_INTR_TXTRAFFIC)
4297                         writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
4298
4299                 for (i = 0; i < config->tx_fifo_num; i++)
4300                         tx_intr_handler(&fifos[i]);
4301
4302                 writeq(sp->general_int_mask, &bar0->general_int_mask);
4303                 readl(&bar0->general_int_status);
4304                 return IRQ_HANDLED;
4305         }
4306         /* The interrupt was not raised by us */
4307         return IRQ_NONE;
4308 }
4309
4310 static void s2io_txpic_intr_handle(struct s2io_nic *sp)
4311 {
4312         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4313         u64 val64;
4314
4315         val64 = readq(&bar0->pic_int_status);
4316         if (val64 & PIC_INT_GPIO) {
4317                 val64 = readq(&bar0->gpio_int_reg);
4318                 if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
4319                     (val64 & GPIO_INT_REG_LINK_UP)) {
4320                         /*
4321                          * This is unstable state so clear both up/down
4322                          * interrupt and adapter to re-evaluate the link state.
4323                          */
4324                         val64 |= GPIO_INT_REG_LINK_DOWN;
4325                         val64 |= GPIO_INT_REG_LINK_UP;
4326                         writeq(val64, &bar0->gpio_int_reg);
4327                         val64 = readq(&bar0->gpio_int_mask);
4328                         val64 &= ~(GPIO_INT_MASK_LINK_UP |
4329                                    GPIO_INT_MASK_LINK_DOWN);
4330                         writeq(val64, &bar0->gpio_int_mask);
4331                 } else if (val64 & GPIO_INT_REG_LINK_UP) {
4332                         val64 = readq(&bar0->adapter_status);
4333                         /* Enable Adapter */
4334                         val64 = readq(&bar0->adapter_control);
4335                         val64 |= ADAPTER_CNTL_EN;
4336                         writeq(val64, &bar0->adapter_control);
4337                         val64 |= ADAPTER_LED_ON;
4338                         writeq(val64, &bar0->adapter_control);
4339                         if (!sp->device_enabled_once)
4340                                 sp->device_enabled_once = 1;
4341
4342                         s2io_link(sp, LINK_UP);
4343                         /*
4344                          * unmask link down interrupt and mask link-up
4345                          * intr
4346                          */
4347                         val64 = readq(&bar0->gpio_int_mask);
4348                         val64 &= ~GPIO_INT_MASK_LINK_DOWN;
4349                         val64 |= GPIO_INT_MASK_LINK_UP;
4350                         writeq(val64, &bar0->gpio_int_mask);
4351
4352                 } else if (val64 & GPIO_INT_REG_LINK_DOWN) {
4353                         val64 = readq(&bar0->adapter_status);
4354                         s2io_link(sp, LINK_DOWN);
4355                         /* Link is down so unmaks link up interrupt */
4356                         val64 = readq(&bar0->gpio_int_mask);
4357                         val64 &= ~GPIO_INT_MASK_LINK_UP;
4358                         val64 |= GPIO_INT_MASK_LINK_DOWN;
4359                         writeq(val64, &bar0->gpio_int_mask);
4360
4361                         /* turn off LED */
4362                         val64 = readq(&bar0->adapter_control);
4363                         val64 = val64 & (~ADAPTER_LED_ON);
4364                         writeq(val64, &bar0->adapter_control);
4365                 }
4366         }
4367         val64 = readq(&bar0->gpio_int_mask);
4368 }
4369
4370 /**
4371  *  do_s2io_chk_alarm_bit - Check for alarm and incrment the counter
4372  *  @value: alarm bits
4373  *  @addr: address value
4374  *  @cnt: counter variable
4375  *  Description: Check for alarm and increment the counter
4376  *  Return Value:
4377  *  1 - if alarm bit set
4378  *  0 - if alarm bit is not set
4379  */
4380 static int do_s2io_chk_alarm_bit(u64 value, void __iomem *addr,
4381                                  unsigned long long *cnt)
4382 {
4383         u64 val64;
4384         val64 = readq(addr);
4385         if (val64 & value) {
4386                 writeq(val64, addr);
4387                 (*cnt)++;
4388                 return 1;
4389         }
4390         return 0;
4391
4392 }
4393
4394 /**
4395  *  s2io_handle_errors - Xframe error indication handler
4396  *  @nic: device private variable
4397  *  Description: Handle alarms such as loss of link, single or
4398  *  double ECC errors, critical and serious errors.
4399  *  Return Value:
4400  *  NONE
4401  */
4402 static void s2io_handle_errors(void *dev_id)
4403 {
4404         struct net_device *dev = (struct net_device *)dev_id;
4405         struct s2io_nic *sp = netdev_priv(dev);
4406         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4407         u64 temp64 = 0, val64 = 0;
4408         int i = 0;
4409
4410         struct swStat *sw_stat = &sp->mac_control.stats_info->sw_stat;
4411         struct xpakStat *stats = &sp->mac_control.stats_info->xpak_stat;
4412
4413         if (!is_s2io_card_up(sp))
4414                 return;
4415
4416         if (pci_channel_offline(sp->pdev))
4417                 return;
4418
4419         memset(&sw_stat->ring_full_cnt, 0,
4420                sizeof(sw_stat->ring_full_cnt));
4421
4422         /* Handling the XPAK counters update */
4423         if (stats->xpak_timer_count < 72000) {
4424                 /* waiting for an hour */
4425                 stats->xpak_timer_count++;
4426         } else {
4427                 s2io_updt_xpak_counter(dev);
4428                 /* reset the count to zero */
4429                 stats->xpak_timer_count = 0;
4430         }
4431
4432         /* Handling link status change error Intr */
4433         if (s2io_link_fault_indication(sp) == MAC_RMAC_ERR_TIMER) {
4434                 val64 = readq(&bar0->mac_rmac_err_reg);
4435                 writeq(val64, &bar0->mac_rmac_err_reg);
4436                 if (val64 & RMAC_LINK_STATE_CHANGE_INT)
4437                         schedule_work(&sp->set_link_task);
4438         }
4439
4440         /* In case of a serious error, the device will be Reset. */
4441         if (do_s2io_chk_alarm_bit(SERR_SOURCE_ANY, &bar0->serr_source,
4442                                   &sw_stat->serious_err_cnt))
4443                 goto reset;
4444
4445         /* Check for data parity error */
4446         if (do_s2io_chk_alarm_bit(GPIO_INT_REG_DP_ERR_INT, &bar0->gpio_int_reg,
4447                                   &sw_stat->parity_err_cnt))
4448                 goto reset;
4449
4450         /* Check for ring full counter */
4451         if (sp->device_type == XFRAME_II_DEVICE) {
4452                 val64 = readq(&bar0->ring_bump_counter1);
4453                 for (i = 0; i < 4; i++) {
4454                         temp64 = (val64 & vBIT(0xFFFF, (i*16), 16));
4455                         temp64 >>= 64 - ((i+1)*16);
4456                         sw_stat->ring_full_cnt[i] += temp64;
4457                 }
4458
4459                 val64 = readq(&bar0->ring_bump_counter2);
4460                 for (i = 0; i < 4; i++) {
4461                         temp64 = (val64 & vBIT(0xFFFF, (i*16), 16));
4462                         temp64 >>= 64 - ((i+1)*16);
4463                         sw_stat->ring_full_cnt[i+4] += temp64;
4464                 }
4465         }
4466
4467         val64 = readq(&bar0->txdma_int_status);
4468         /*check for pfc_err*/
4469         if (val64 & TXDMA_PFC_INT) {
4470                 if (do_s2io_chk_alarm_bit(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
4471                                           PFC_MISC_0_ERR | PFC_MISC_1_ERR |
4472                                           PFC_PCIX_ERR,
4473                                           &bar0->pfc_err_reg,
4474                                           &sw_stat->pfc_err_cnt))
4475                         goto reset;
4476                 do_s2io_chk_alarm_bit(PFC_ECC_SG_ERR,
4477                                       &bar0->pfc_err_reg,
4478                                       &sw_stat->pfc_err_cnt);
4479         }
4480
4481         /*check for tda_err*/
4482         if (val64 & TXDMA_TDA_INT) {
4483                 if (do_s2io_chk_alarm_bit(TDA_Fn_ECC_DB_ERR |
4484                                           TDA_SM0_ERR_ALARM |
4485                                           TDA_SM1_ERR_ALARM,
4486                                           &bar0->tda_err_reg,
4487                                           &sw_stat->tda_err_cnt))
4488                         goto reset;
4489                 do_s2io_chk_alarm_bit(TDA_Fn_ECC_SG_ERR | TDA_PCIX_ERR,
4490                                       &bar0->tda_err_reg,
4491                                       &sw_stat->tda_err_cnt);
4492         }
4493         /*check for pcc_err*/
4494         if (val64 & TXDMA_PCC_INT) {
4495                 if (do_s2io_chk_alarm_bit(PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
4496                                           PCC_N_SERR | PCC_6_COF_OV_ERR |
4497                                           PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
4498                                           PCC_7_LSO_OV_ERR | PCC_FB_ECC_DB_ERR |
4499                                           PCC_TXB_ECC_DB_ERR,
4500                                           &bar0->pcc_err_reg,
4501                                           &sw_stat->pcc_err_cnt))
4502                         goto reset;
4503                 do_s2io_chk_alarm_bit(PCC_FB_ECC_SG_ERR | PCC_TXB_ECC_SG_ERR,
4504                                       &bar0->pcc_err_reg,
4505                                       &sw_stat->pcc_err_cnt);
4506         }
4507
4508         /*check for tti_err*/
4509         if (val64 & TXDMA_TTI_INT) {
4510                 if (do_s2io_chk_alarm_bit(TTI_SM_ERR_ALARM,
4511                                           &bar0->tti_err_reg,
4512                                           &sw_stat->tti_err_cnt))
4513                         goto reset;
4514                 do_s2io_chk_alarm_bit(TTI_ECC_SG_ERR | TTI_ECC_DB_ERR,
4515                                       &bar0->tti_err_reg,
4516                                       &sw_stat->tti_err_cnt);
4517         }
4518
4519         /*check for lso_err*/
4520         if (val64 & TXDMA_LSO_INT) {
4521                 if (do_s2io_chk_alarm_bit(LSO6_ABORT | LSO7_ABORT |
4522                                           LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM,
4523                                           &bar0->lso_err_reg,
4524                                           &sw_stat->lso_err_cnt))
4525                         goto reset;
4526                 do_s2io_chk_alarm_bit(LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
4527                                       &bar0->lso_err_reg,
4528                                       &sw_stat->lso_err_cnt);
4529         }
4530
4531         /*check for tpa_err*/
4532         if (val64 & TXDMA_TPA_INT) {
4533                 if (do_s2io_chk_alarm_bit(TPA_SM_ERR_ALARM,
4534                                           &bar0->tpa_err_reg,
4535                                           &sw_stat->tpa_err_cnt))
4536                         goto reset;
4537                 do_s2io_chk_alarm_bit(TPA_TX_FRM_DROP,
4538                                       &bar0->tpa_err_reg,
4539                                       &sw_stat->tpa_err_cnt);
4540         }
4541
4542         /*check for sm_err*/
4543         if (val64 & TXDMA_SM_INT) {
4544                 if (do_s2io_chk_alarm_bit(SM_SM_ERR_ALARM,
4545                                           &bar0->sm_err_reg,
4546                                           &sw_stat->sm_err_cnt))
4547                         goto reset;
4548         }
4549
4550         val64 = readq(&bar0->mac_int_status);
4551         if (val64 & MAC_INT_STATUS_TMAC_INT) {
4552                 if (do_s2io_chk_alarm_bit(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR,
4553                                           &bar0->mac_tmac_err_reg,
4554                                           &sw_stat->mac_tmac_err_cnt))
4555                         goto reset;
4556                 do_s2io_chk_alarm_bit(TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
4557                                       TMAC_DESC_ECC_SG_ERR |
4558                                       TMAC_DESC_ECC_DB_ERR,
4559                                       &bar0->mac_tmac_err_reg,
4560                                       &sw_stat->mac_tmac_err_cnt);
4561         }
4562
4563         val64 = readq(&bar0->xgxs_int_status);
4564         if (val64 & XGXS_INT_STATUS_TXGXS) {
4565                 if (do_s2io_chk_alarm_bit(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR,
4566                                           &bar0->xgxs_txgxs_err_reg,
4567                                           &sw_stat->xgxs_txgxs_err_cnt))
4568                         goto reset;
4569                 do_s2io_chk_alarm_bit(TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
4570                                       &bar0->xgxs_txgxs_err_reg,
4571                                       &sw_stat->xgxs_txgxs_err_cnt);
4572         }
4573
4574         val64 = readq(&bar0->rxdma_int_status);
4575         if (val64 & RXDMA_INT_RC_INT_M) {
4576                 if (do_s2io_chk_alarm_bit(RC_PRCn_ECC_DB_ERR |
4577                                           RC_FTC_ECC_DB_ERR |
4578                                           RC_PRCn_SM_ERR_ALARM |
4579                                           RC_FTC_SM_ERR_ALARM,
4580                                           &bar0->rc_err_reg,
4581                                           &sw_stat->rc_err_cnt))
4582                         goto reset;
4583                 do_s2io_chk_alarm_bit(RC_PRCn_ECC_SG_ERR |
4584                                       RC_FTC_ECC_SG_ERR |
4585                                       RC_RDA_FAIL_WR_Rn, &bar0->rc_err_reg,
4586                                       &sw_stat->rc_err_cnt);
4587                 if (do_s2io_chk_alarm_bit(PRC_PCI_AB_RD_Rn |
4588                                           PRC_PCI_AB_WR_Rn |
4589                                           PRC_PCI_AB_F_WR_Rn,
4590                                           &bar0->prc_pcix_err_reg,
4591                                           &sw_stat->prc_pcix_err_cnt))
4592                         goto reset;
4593                 do_s2io_chk_alarm_bit(PRC_PCI_DP_RD_Rn |
4594                                       PRC_PCI_DP_WR_Rn |
4595                                       PRC_PCI_DP_F_WR_Rn,
4596                                       &bar0->prc_pcix_err_reg,
4597                                       &sw_stat->prc_pcix_err_cnt);
4598         }
4599
4600         if (val64 & RXDMA_INT_RPA_INT_M) {
4601                 if (do_s2io_chk_alarm_bit(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR,
4602                                           &bar0->rpa_err_reg,
4603                                           &sw_stat->rpa_err_cnt))
4604                         goto reset;
4605                 do_s2io_chk_alarm_bit(RPA_ECC_SG_ERR | RPA_ECC_DB_ERR,
4606                                       &bar0->rpa_err_reg,
4607                                       &sw_stat->rpa_err_cnt);
4608         }
4609
4610         if (val64 & RXDMA_INT_RDA_INT_M) {
4611                 if (do_s2io_chk_alarm_bit(RDA_RXDn_ECC_DB_ERR |
4612                                           RDA_FRM_ECC_DB_N_AERR |
4613                                           RDA_SM1_ERR_ALARM |
4614                                           RDA_SM0_ERR_ALARM |
4615                                           RDA_RXD_ECC_DB_SERR,
4616                                           &bar0->rda_err_reg,
4617                                           &sw_stat->rda_err_cnt))
4618                         goto reset;
4619                 do_s2io_chk_alarm_bit(RDA_RXDn_ECC_SG_ERR |
4620                                       RDA_FRM_ECC_SG_ERR |
4621                                       RDA_MISC_ERR |
4622                                       RDA_PCIX_ERR,
4623                                       &bar0->rda_err_reg,
4624                                       &sw_stat->rda_err_cnt);
4625         }
4626
4627         if (val64 & RXDMA_INT_RTI_INT_M) {
4628                 if (do_s2io_chk_alarm_bit(RTI_SM_ERR_ALARM,
4629                                           &bar0->rti_err_reg,
4630                                           &sw_stat->rti_err_cnt))
4631                         goto reset;
4632                 do_s2io_chk_alarm_bit(RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
4633                                       &bar0->rti_err_reg,
4634                                       &sw_stat->rti_err_cnt);
4635         }
4636
4637         val64 = readq(&bar0->mac_int_status);
4638         if (val64 & MAC_INT_STATUS_RMAC_INT) {
4639                 if (do_s2io_chk_alarm_bit(RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR,
4640                                           &bar0->mac_rmac_err_reg,
4641                                           &sw_stat->mac_rmac_err_cnt))
4642                         goto reset;
4643                 do_s2io_chk_alarm_bit(RMAC_UNUSED_INT |
4644                                       RMAC_SINGLE_ECC_ERR |
4645                                       RMAC_DOUBLE_ECC_ERR,
4646                                       &bar0->mac_rmac_err_reg,
4647                                       &sw_stat->mac_rmac_err_cnt);
4648         }
4649
4650         val64 = readq(&bar0->xgxs_int_status);
4651         if (val64 & XGXS_INT_STATUS_RXGXS) {
4652                 if (do_s2io_chk_alarm_bit(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR,
4653                                           &bar0->xgxs_rxgxs_err_reg,
4654                                           &sw_stat->xgxs_rxgxs_err_cnt))
4655                         goto reset;
4656         }
4657
4658         val64 = readq(&bar0->mc_int_status);
4659         if (val64 & MC_INT_STATUS_MC_INT) {
4660                 if (do_s2io_chk_alarm_bit(MC_ERR_REG_SM_ERR,
4661                                           &bar0->mc_err_reg,
4662                                           &sw_stat->mc_err_cnt))
4663                         goto reset;
4664
4665                 /* Handling Ecc errors */
4666                 if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
4667                         writeq(val64, &bar0->mc_err_reg);
4668                         if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
4669                                 sw_stat->double_ecc_errs++;
4670                                 if (sp->device_type != XFRAME_II_DEVICE) {
4671                                         /*
4672                                          * Reset XframeI only if critical error
4673                                          */
4674                                         if (val64 &
4675                                             (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
4676                                              MC_ERR_REG_MIRI_ECC_DB_ERR_1))
4677                                                 goto reset;
4678                                 }
4679                         } else
4680                                 sw_stat->single_ecc_errs++;
4681                 }
4682         }
4683         return;
4684
4685 reset:
4686         s2io_stop_all_tx_queue(sp);
4687         schedule_work(&sp->rst_timer_task);
4688         sw_stat->soft_reset_cnt++;
4689 }
4690
4691 /**
4692  *  s2io_isr - ISR handler of the device .
4693  *  @irq: the irq of the device.
4694  *  @dev_id: a void pointer to the dev structure of the NIC.
4695  *  Description:  This function is the ISR handler of the device. It
4696  *  identifies the reason for the interrupt and calls the relevant
4697  *  service routines. As a contongency measure, this ISR allocates the
4698  *  recv buffers, if their numbers are below the panic value which is
4699  *  presently set to 25% of the original number of rcv buffers allocated.
4700  *  Return value:
4701  *   IRQ_HANDLED: will be returned if IRQ was handled by this routine
4702  *   IRQ_NONE: will be returned if interrupt is not from our device
4703  */
4704 static irqreturn_t s2io_isr(int irq, void *dev_id)
4705 {
4706         struct net_device *dev = (struct net_device *)dev_id;
4707         struct s2io_nic *sp = netdev_priv(dev);
4708         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4709         int i;
4710         u64 reason = 0;
4711         struct mac_info *mac_control;
4712         struct config_param *config;
4713
4714         /* Pretend we handled any irq's from a disconnected card */
4715         if (pci_channel_offline(sp->pdev))
4716                 return IRQ_NONE;
4717
4718         if (!is_s2io_card_up(sp))
4719                 return IRQ_NONE;
4720
4721         config = &sp->config;
4722         mac_control = &sp->mac_control;
4723
4724         /*
4725          * Identify the cause for interrupt and call the appropriate
4726          * interrupt handler. Causes for the interrupt could be;
4727          * 1. Rx of packet.
4728          * 2. Tx complete.
4729          * 3. Link down.
4730          */
4731         reason = readq(&bar0->general_int_status);
4732
4733         if (unlikely(reason == S2IO_MINUS_ONE))
4734                 return IRQ_HANDLED;     /* Nothing much can be done. Get out */
4735
4736         if (reason &
4737             (GEN_INTR_RXTRAFFIC | GEN_INTR_TXTRAFFIC | GEN_INTR_TXPIC)) {
4738                 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4739
4740                 if (config->napi) {
4741                         if (reason & GEN_INTR_RXTRAFFIC) {
4742                                 napi_schedule(&sp->napi);
4743                                 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_mask);
4744                                 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4745                                 readl(&bar0->rx_traffic_int);
4746                         }
4747                 } else {
4748                         /*
4749                          * rx_traffic_int reg is an R1 register, writing all 1's
4750                          * will ensure that the actual interrupt causing bit
4751                          * get's cleared and hence a read can be avoided.
4752                          */
4753                         if (reason & GEN_INTR_RXTRAFFIC)
4754                                 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4755
4756                         for (i = 0; i < config->rx_ring_num; i++) {
4757                                 struct ring_info *ring = &mac_control->rings[i];
4758
4759                                 rx_intr_handler(ring, 0);
4760                         }
4761                 }
4762
4763                 /*
4764                  * tx_traffic_int reg is an R1 register, writing all 1's
4765                  * will ensure that the actual interrupt causing bit get's
4766                  * cleared and hence a read can be avoided.
4767                  */
4768                 if (reason & GEN_INTR_TXTRAFFIC)
4769                         writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
4770
4771                 for (i = 0; i < config->tx_fifo_num; i++)
4772                         tx_intr_handler(&mac_control->fifos[i]);
4773
4774                 if (reason & GEN_INTR_TXPIC)
4775                         s2io_txpic_intr_handle(sp);
4776
4777                 /*
4778                  * Reallocate the buffers from the interrupt handler itself.
4779                  */
4780                 if (!config->napi) {
4781                         for (i = 0; i < config->rx_ring_num; i++) {
4782                                 struct ring_info *ring = &mac_control->rings[i];
4783
4784                                 s2io_chk_rx_buffers(sp, ring);
4785                         }
4786                 }
4787                 writeq(sp->general_int_mask, &bar0->general_int_mask);
4788                 readl(&bar0->general_int_status);
4789
4790                 return IRQ_HANDLED;
4791
4792         } else if (!reason) {
4793                 /* The interrupt was not raised by us */
4794                 return IRQ_NONE;
4795         }
4796
4797         return IRQ_HANDLED;
4798 }
4799
4800 /**
4801  * s2io_updt_stats -
4802  */
4803 static void s2io_updt_stats(struct s2io_nic *sp)
4804 {
4805         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4806         u64 val64;
4807         int cnt = 0;
4808
4809         if (is_s2io_card_up(sp)) {
4810                 /* Apprx 30us on a 133 MHz bus */
4811                 val64 = SET_UPDT_CLICKS(10) |
4812                         STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
4813                 writeq(val64, &bar0->stat_cfg);
4814                 do {
4815                         udelay(100);
4816                         val64 = readq(&bar0->stat_cfg);
4817                         if (!(val64 & s2BIT(0)))
4818                                 break;
4819                         cnt++;
4820                         if (cnt == 5)
4821                                 break; /* Updt failed */
4822                 } while (1);
4823         }
4824 }
4825
4826 /**
4827  *  s2io_get_stats - Updates the device statistics structure.
4828  *  @dev : pointer to the device structure.
4829  *  Description:
4830  *  This function updates the device statistics structure in the s2io_nic
4831  *  structure and returns a pointer to the same.
4832  *  Return value:
4833  *  pointer to the updated net_device_stats structure.
4834  */
4835 static struct net_device_stats *s2io_get_stats(struct net_device *dev)
4836 {
4837         struct s2io_nic *sp = netdev_priv(dev);
4838         struct mac_info *mac_control = &sp->mac_control;
4839         struct stat_block *stats = mac_control->stats_info;
4840         u64 delta;
4841
4842         /* Configure Stats for immediate updt */
4843         s2io_updt_stats(sp);
4844
4845         /* A device reset will cause the on-adapter statistics to be zero'ed.
4846          * This can be done while running by changing the MTU.  To prevent the
4847          * system from having the stats zero'ed, the driver keeps a copy of the
4848          * last update to the system (which is also zero'ed on reset).  This
4849          * enables the driver to accurately know the delta between the last
4850          * update and the current update.
4851          */
4852         delta = ((u64) le32_to_cpu(stats->rmac_vld_frms_oflow) << 32 |
4853                 le32_to_cpu(stats->rmac_vld_frms)) - sp->stats.rx_packets;
4854         sp->stats.rx_packets += delta;
4855         dev->stats.rx_packets += delta;
4856
4857         delta = ((u64) le32_to_cpu(stats->tmac_frms_oflow) << 32 |
4858                 le32_to_cpu(stats->tmac_frms)) - sp->stats.tx_packets;
4859         sp->stats.tx_packets += delta;
4860         dev->stats.tx_packets += delta;
4861
4862         delta = ((u64) le32_to_cpu(stats->rmac_data_octets_oflow) << 32 |
4863                 le32_to_cpu(stats->rmac_data_octets)) - sp->stats.rx_bytes;
4864         sp->stats.rx_bytes += delta;
4865         dev->stats.rx_bytes += delta;
4866
4867         delta = ((u64) le32_to_cpu(stats->tmac_data_octets_oflow) << 32 |
4868                 le32_to_cpu(stats->tmac_data_octets)) - sp->stats.tx_bytes;
4869         sp->stats.tx_bytes += delta;
4870         dev->stats.tx_bytes += delta;
4871
4872         delta = le64_to_cpu(stats->rmac_drop_frms) - sp->stats.rx_errors;
4873         sp->stats.rx_errors += delta;
4874         dev->stats.rx_errors += delta;
4875
4876         delta = ((u64) le32_to_cpu(stats->tmac_any_err_frms_oflow) << 32 |
4877                 le32_to_cpu(stats->tmac_any_err_frms)) - sp->stats.tx_errors;
4878         sp->stats.tx_errors += delta;
4879         dev->stats.tx_errors += delta;
4880
4881         delta = le64_to_cpu(stats->rmac_drop_frms) - sp->stats.rx_dropped;
4882         sp->stats.rx_dropped += delta;
4883         dev->stats.rx_dropped += delta;
4884
4885         delta = le64_to_cpu(stats->tmac_drop_frms) - sp->stats.tx_dropped;
4886         sp->stats.tx_dropped += delta;
4887         dev->stats.tx_dropped += delta;
4888
4889         /* The adapter MAC interprets pause frames as multicast packets, but
4890          * does not pass them up.  This erroneously increases the multicast
4891          * packet count and needs to be deducted when the multicast frame count
4892          * is queried.
4893          */
4894         delta = (u64) le32_to_cpu(stats->rmac_vld_mcst_frms_oflow) << 32 |
4895                 le32_to_cpu(stats->rmac_vld_mcst_frms);
4896         delta -= le64_to_cpu(stats->rmac_pause_ctrl_frms);
4897         delta -= sp->stats.multicast;
4898         sp->stats.multicast += delta;
4899         dev->stats.multicast += delta;
4900
4901         delta = ((u64) le32_to_cpu(stats->rmac_usized_frms_oflow) << 32 |
4902                 le32_to_cpu(stats->rmac_usized_frms)) +
4903                 le64_to_cpu(stats->rmac_long_frms) - sp->stats.rx_length_errors;
4904         sp->stats.rx_length_errors += delta;
4905         dev->stats.rx_length_errors += delta;
4906
4907         delta = le64_to_cpu(stats->rmac_fcs_err_frms) - sp->stats.rx_crc_errors;
4908         sp->stats.rx_crc_errors += delta;
4909         dev->stats.rx_crc_errors += delta;
4910
4911         return &dev->stats;
4912 }
4913
4914 /**
4915  *  s2io_set_multicast - entry point for multicast address enable/disable.
4916  *  @dev : pointer to the device structure
4917  *  Description:
4918  *  This function is a driver entry point which gets called by the kernel
4919  *  whenever multicast addresses must be enabled/disabled. This also gets
4920  *  called to set/reset promiscuous mode. Depending on the deivce flag, we
4921  *  determine, if multicast address must be enabled or if promiscuous mode
4922  *  is to be disabled etc.
4923  *  Return value:
4924  *  void.
4925  */
4926
4927 static void s2io_set_multicast(struct net_device *dev)
4928 {
4929         int i, j, prev_cnt;
4930         struct netdev_hw_addr *ha;
4931         struct s2io_nic *sp = netdev_priv(dev);
4932         struct XENA_dev_config __iomem *bar0 = sp->bar0;
4933         u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
4934                 0xfeffffffffffULL;
4935         u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, mac_addr = 0;
4936         void __iomem *add;
4937         struct config_param *config = &sp->config;
4938
4939         if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
4940                 /*  Enable all Multicast addresses */
4941                 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
4942                        &bar0->rmac_addr_data0_mem);
4943                 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
4944                        &bar0->rmac_addr_data1_mem);
4945                 val64 = RMAC_ADDR_CMD_MEM_WE |
4946                         RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4947                         RMAC_ADDR_CMD_MEM_OFFSET(config->max_mc_addr - 1);
4948                 writeq(val64, &bar0->rmac_addr_cmd_mem);
4949                 /* Wait till command completes */
4950                 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4951                                       RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4952                                       S2IO_BIT_RESET);
4953
4954                 sp->m_cast_flg = 1;
4955                 sp->all_multi_pos = config->max_mc_addr - 1;
4956         } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
4957                 /*  Disable all Multicast addresses */
4958                 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4959                        &bar0->rmac_addr_data0_mem);
4960                 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
4961                        &bar0->rmac_addr_data1_mem);
4962                 val64 = RMAC_ADDR_CMD_MEM_WE |
4963                         RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4964                         RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
4965                 writeq(val64, &bar0->rmac_addr_cmd_mem);
4966                 /* Wait till command completes */
4967                 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4968                                       RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4969                                       S2IO_BIT_RESET);
4970
4971                 sp->m_cast_flg = 0;
4972                 sp->all_multi_pos = 0;
4973         }
4974
4975         if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
4976                 /*  Put the NIC into promiscuous mode */
4977                 add = &bar0->mac_cfg;
4978                 val64 = readq(&bar0->mac_cfg);
4979                 val64 |= MAC_CFG_RMAC_PROM_ENABLE;
4980
4981                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4982                 writel((u32)val64, add);
4983                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4984                 writel((u32) (val64 >> 32), (add + 4));
4985
4986                 if (vlan_tag_strip != 1) {
4987                         val64 = readq(&bar0->rx_pa_cfg);
4988                         val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
4989                         writeq(val64, &bar0->rx_pa_cfg);
4990                         sp->vlan_strip_flag = 0;
4991                 }
4992
4993                 val64 = readq(&bar0->mac_cfg);
4994                 sp->promisc_flg = 1;
4995                 DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
4996                           dev->name);
4997         } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
4998                 /*  Remove the NIC from promiscuous mode */
4999                 add = &bar0->mac_cfg;
5000                 val64 = readq(&bar0->mac_cfg);
5001                 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
5002
5003                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5004                 writel((u32)val64, add);
5005                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
5006                 writel((u32) (val64 >> 32), (add + 4));
5007
5008                 if (vlan_tag_strip != 0) {
5009                         val64 = readq(&bar0->rx_pa_cfg);
5010                         val64 |= RX_PA_CFG_STRIP_VLAN_TAG;
5011                         writeq(val64, &bar0->rx_pa_cfg);
5012                         sp->vlan_strip_flag = 1;
5013                 }
5014
5015                 val64 = readq(&bar0->mac_cfg);
5016                 sp->promisc_flg = 0;
5017                 DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n", dev->name);
5018         }
5019
5020         /*  Update individual M_CAST address list */
5021         if ((!sp->m_cast_flg) && netdev_mc_count(dev)) {
5022                 if (netdev_mc_count(dev) >
5023                     (config->max_mc_addr - config->max_mac_addr)) {
5024                         DBG_PRINT(ERR_DBG,
5025                                   "%s: No more Rx filters can be added - "
5026                                   "please enable ALL_MULTI instead\n",
5027                                   dev->name);
5028                         return;
5029                 }
5030
5031                 prev_cnt = sp->mc_addr_count;
5032                 sp->mc_addr_count = netdev_mc_count(dev);
5033
5034                 /* Clear out the previous list of Mc in the H/W. */
5035                 for (i = 0; i < prev_cnt; i++) {
5036                         writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
5037                                &bar0->rmac_addr_data0_mem);
5038                         writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
5039                                &bar0->rmac_addr_data1_mem);
5040                         val64 = RMAC_ADDR_CMD_MEM_WE |
5041                                 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5042                                 RMAC_ADDR_CMD_MEM_OFFSET
5043                                 (config->mc_start_offset + i);
5044                         writeq(val64, &bar0->rmac_addr_cmd_mem);
5045
5046                         /* Wait for command completes */
5047                         if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5048                                                   RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5049                                                   S2IO_BIT_RESET)) {
5050                                 DBG_PRINT(ERR_DBG,
5051                                           "%s: Adding Multicasts failed\n",
5052                                           dev->name);
5053                                 return;
5054                         }
5055                 }
5056
5057                 /* Create the new Rx filter list and update the same in H/W. */
5058                 i = 0;
5059                 netdev_for_each_mc_addr(ha, dev) {
5060                         mac_addr = 0;
5061                         for (j = 0; j < ETH_ALEN; j++) {
5062                                 mac_addr |= ha->addr[j];
5063                                 mac_addr <<= 8;
5064                         }
5065                         mac_addr >>= 8;
5066                         writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
5067                                &bar0->rmac_addr_data0_mem);
5068                         writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
5069                                &bar0->rmac_addr_data1_mem);
5070                         val64 = RMAC_ADDR_CMD_MEM_WE |
5071                                 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5072                                 RMAC_ADDR_CMD_MEM_OFFSET
5073                                 (i + config->mc_start_offset);
5074                         writeq(val64, &bar0->rmac_addr_cmd_mem);
5075
5076                         /* Wait for command completes */
5077                         if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5078                                                   RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5079                                                   S2IO_BIT_RESET)) {
5080                                 DBG_PRINT(ERR_DBG,
5081                                           "%s: Adding Multicasts failed\n",
5082                                           dev->name);
5083                                 return;
5084                         }
5085                         i++;
5086                 }
5087         }
5088 }
5089
5090 /* read from CAM unicast & multicast addresses and store it in
5091  * def_mac_addr structure
5092  */
5093 static void do_s2io_store_unicast_mc(struct s2io_nic *sp)
5094 {
5095         int offset;
5096         u64 mac_addr = 0x0;
5097         struct config_param *config = &sp->config;
5098
5099         /* store unicast & multicast mac addresses */
5100         for (offset = 0; offset < config->max_mc_addr; offset++) {
5101                 mac_addr = do_s2io_read_unicast_mc(sp, offset);
5102                 /* if read fails disable the entry */
5103                 if (mac_addr == FAILURE)
5104                         mac_addr = S2IO_DISABLE_MAC_ENTRY;
5105                 do_s2io_copy_mac_addr(sp, offset, mac_addr);
5106         }
5107 }
5108
5109 /* restore unicast & multicast MAC to CAM from def_mac_addr structure */
5110 static void do_s2io_restore_unicast_mc(struct s2io_nic *sp)
5111 {
5112         int offset;
5113         struct config_param *config = &sp->config;
5114         /* restore unicast mac address */
5115         for (offset = 0; offset < config->max_mac_addr; offset++)
5116                 do_s2io_prog_unicast(sp->dev,
5117                                      sp->def_mac_addr[offset].mac_addr);
5118
5119         /* restore multicast mac address */
5120         for (offset = config->mc_start_offset;
5121              offset < config->max_mc_addr; offset++)
5122                 do_s2io_add_mc(sp, sp->def_mac_addr[offset].mac_addr);
5123 }
5124
5125 /* add a multicast MAC address to CAM */
5126 static int do_s2io_add_mc(struct s2io_nic *sp, u8 *addr)
5127 {
5128         int i;
5129         u64 mac_addr = 0;
5130         struct config_param *config = &sp->config;
5131
5132         for (i = 0; i < ETH_ALEN; i++) {
5133                 mac_addr <<= 8;
5134                 mac_addr |= addr[i];
5135         }
5136         if ((0ULL == mac_addr) || (mac_addr == S2IO_DISABLE_MAC_ENTRY))
5137                 return SUCCESS;
5138
5139         /* check if the multicast mac already preset in CAM */
5140         for (i = config->mc_start_offset; i < config->max_mc_addr; i++) {
5141                 u64 tmp64;
5142                 tmp64 = do_s2io_read_unicast_mc(sp, i);
5143                 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5144                         break;
5145
5146                 if (tmp64 == mac_addr)
5147                         return SUCCESS;
5148         }
5149         if (i == config->max_mc_addr) {
5150                 DBG_PRINT(ERR_DBG,
5151                           "CAM full no space left for multicast MAC\n");
5152                 return FAILURE;
5153         }
5154         /* Update the internal structure with this new mac address */
5155         do_s2io_copy_mac_addr(sp, i, mac_addr);
5156
5157         return do_s2io_add_mac(sp, mac_addr, i);
5158 }
5159
5160 /* add MAC address to CAM */
5161 static int do_s2io_add_mac(struct s2io_nic *sp, u64 addr, int off)
5162 {
5163         u64 val64;
5164         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5165
5166         writeq(RMAC_ADDR_DATA0_MEM_ADDR(addr),
5167                &bar0->rmac_addr_data0_mem);
5168
5169         val64 = RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5170                 RMAC_ADDR_CMD_MEM_OFFSET(off);
5171         writeq(val64, &bar0->rmac_addr_cmd_mem);
5172
5173         /* Wait till command completes */
5174         if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5175                                   RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5176                                   S2IO_BIT_RESET)) {
5177                 DBG_PRINT(INFO_DBG, "do_s2io_add_mac failed\n");
5178                 return FAILURE;
5179         }
5180         return SUCCESS;
5181 }
5182 /* deletes a specified unicast/multicast mac entry from CAM */
5183 static int do_s2io_delete_unicast_mc(struct s2io_nic *sp, u64 addr)
5184 {
5185         int offset;
5186         u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, tmp64;
5187         struct config_param *config = &sp->config;
5188
5189         for (offset = 1;
5190              offset < config->max_mc_addr; offset++) {
5191                 tmp64 = do_s2io_read_unicast_mc(sp, offset);
5192                 if (tmp64 == addr) {
5193                         /* disable the entry by writing  0xffffffffffffULL */
5194                         if (do_s2io_add_mac(sp, dis_addr, offset) ==  FAILURE)
5195                                 return FAILURE;
5196                         /* store the new mac list from CAM */
5197                         do_s2io_store_unicast_mc(sp);
5198                         return SUCCESS;
5199                 }
5200         }
5201         DBG_PRINT(ERR_DBG, "MAC address 0x%llx not found in CAM\n",
5202                   (unsigned long long)addr);
5203         return FAILURE;
5204 }
5205
5206 /* read mac entries from CAM */
5207 static u64 do_s2io_read_unicast_mc(struct s2io_nic *sp, int offset)
5208 {
5209         u64 tmp64 = 0xffffffffffff0000ULL, val64;
5210         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5211
5212         /* read mac addr */
5213         val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5214                 RMAC_ADDR_CMD_MEM_OFFSET(offset);
5215         writeq(val64, &bar0->rmac_addr_cmd_mem);
5216
5217         /* Wait till command completes */
5218         if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5219                                   RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5220                                   S2IO_BIT_RESET)) {
5221                 DBG_PRINT(INFO_DBG, "do_s2io_read_unicast_mc failed\n");
5222                 return FAILURE;
5223         }
5224         tmp64 = readq(&bar0->rmac_addr_data0_mem);
5225
5226         return tmp64 >> 16;
5227 }
5228
5229 /**
5230  * s2io_set_mac_addr - driver entry point
5231  */
5232
5233 static int s2io_set_mac_addr(struct net_device *dev, void *p)
5234 {
5235         struct sockaddr *addr = p;
5236
5237         if (!is_valid_ether_addr(addr->sa_data))
5238                 return -EADDRNOTAVAIL;
5239
5240         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5241
5242         /* store the MAC address in CAM */
5243         return do_s2io_prog_unicast(dev, dev->dev_addr);
5244 }
5245 /**
5246  *  do_s2io_prog_unicast - Programs the Xframe mac address
5247  *  @dev : pointer to the device structure.
5248  *  @addr: a uchar pointer to the new mac address which is to be set.
5249  *  Description : This procedure will program the Xframe to receive
5250  *  frames with new Mac Address
5251  *  Return value: SUCCESS on success and an appropriate (-)ve integer
5252  *  as defined in errno.h file on failure.
5253  */
5254
5255 static int do_s2io_prog_unicast(struct net_device *dev, u8 *addr)
5256 {
5257         struct s2io_nic *sp = netdev_priv(dev);
5258         register u64 mac_addr = 0, perm_addr = 0;
5259         int i;
5260         u64 tmp64;
5261         struct config_param *config = &sp->config;
5262
5263         /*
5264          * Set the new MAC address as the new unicast filter and reflect this
5265          * change on the device address registered with the OS. It will be
5266          * at offset 0.
5267          */
5268         for (i = 0; i < ETH_ALEN; i++) {
5269                 mac_addr <<= 8;
5270                 mac_addr |= addr[i];
5271                 perm_addr <<= 8;
5272                 perm_addr |= sp->def_mac_addr[0].mac_addr[i];
5273         }
5274
5275         /* check if the dev_addr is different than perm_addr */
5276         if (mac_addr == perm_addr)
5277                 return SUCCESS;
5278
5279         /* check if the mac already preset in CAM */
5280         for (i = 1; i < config->max_mac_addr; i++) {
5281                 tmp64 = do_s2io_read_unicast_mc(sp, i);
5282                 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5283                         break;
5284
5285                 if (tmp64 == mac_addr) {
5286                         DBG_PRINT(INFO_DBG,
5287                                   "MAC addr:0x%llx already present in CAM\n",
5288                                   (unsigned long long)mac_addr);
5289                         return SUCCESS;
5290                 }
5291         }
5292         if (i == config->max_mac_addr) {
5293                 DBG_PRINT(ERR_DBG, "CAM full no space left for Unicast MAC\n");
5294                 return FAILURE;
5295         }
5296         /* Update the internal structure with this new mac address */
5297         do_s2io_copy_mac_addr(sp, i, mac_addr);
5298
5299         return do_s2io_add_mac(sp, mac_addr, i);
5300 }
5301
5302 /**
5303  * s2io_ethtool_sset - Sets different link parameters.
5304  * @sp : private member of the device structure, which is a pointer to the
5305  * s2io_nic structure.
5306  * @info: pointer to the structure with parameters given by ethtool to set
5307  * link information.
5308  * Description:
5309  * The function sets different link parameters provided by the user onto
5310  * the NIC.
5311  * Return value:
5312  * 0 on success.
5313  */
5314
5315 static int s2io_ethtool_sset(struct net_device *dev,
5316                              struct ethtool_cmd *info)
5317 {
5318         struct s2io_nic *sp = netdev_priv(dev);
5319         if ((info->autoneg == AUTONEG_ENABLE) ||
5320             (ethtool_cmd_speed(info) != SPEED_10000) ||
5321             (info->duplex != DUPLEX_FULL))
5322                 return -EINVAL;
5323         else {
5324                 s2io_close(sp->dev);
5325                 s2io_open(sp->dev);
5326         }
5327
5328         return 0;
5329 }
5330
5331 /**
5332  * s2io_ethtol_gset - Return link specific information.
5333  * @sp : private member of the device structure, pointer to the
5334  *      s2io_nic structure.
5335  * @info : pointer to the structure with parameters given by ethtool
5336  * to return link information.
5337  * Description:
5338  * Returns link specific information like speed, duplex etc.. to ethtool.
5339  * Return value :
5340  * return 0 on success.
5341  */
5342
5343 static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
5344 {
5345         struct s2io_nic *sp = netdev_priv(dev);
5346         info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5347         info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5348         info->port = PORT_FIBRE;
5349
5350         /* info->transceiver */
5351         info->transceiver = XCVR_EXTERNAL;
5352
5353         if (netif_carrier_ok(sp->dev)) {
5354                 ethtool_cmd_speed_set(info, SPEED_10000);
5355                 info->duplex = DUPLEX_FULL;
5356         } else {
5357                 ethtool_cmd_speed_set(info, SPEED_UNKNOWN);
5358                 info->duplex = DUPLEX_UNKNOWN;
5359         }
5360
5361         info->autoneg = AUTONEG_DISABLE;
5362         return 0;
5363 }
5364
5365 /**
5366  * s2io_ethtool_gdrvinfo - Returns driver specific information.
5367  * @sp : private member of the device structure, which is a pointer to the
5368  * s2io_nic structure.
5369  * @info : pointer to the structure with parameters given by ethtool to
5370  * return driver information.
5371  * Description:
5372  * Returns driver specefic information like name, version etc.. to ethtool.
5373  * Return value:
5374  *  void
5375  */
5376
5377 static void s2io_ethtool_gdrvinfo(struct net_device *dev,
5378                                   struct ethtool_drvinfo *info)
5379 {
5380         struct s2io_nic *sp = netdev_priv(dev);
5381
5382         strlcpy(info->driver, s2io_driver_name, sizeof(info->driver));
5383         strlcpy(info->version, s2io_driver_version, sizeof(info->version));
5384         strlcpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info));
5385 }
5386
5387 /**
5388  *  s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
5389  *  @sp: private member of the device structure, which is a pointer to the
5390  *  s2io_nic structure.
5391  *  @regs : pointer to the structure with parameters given by ethtool for
5392  *  dumping the registers.
5393  *  @reg_space: The input argumnet into which all the registers are dumped.
5394  *  Description:
5395  *  Dumps the entire register space of xFrame NIC into the user given
5396  *  buffer area.
5397  * Return value :
5398  * void .
5399  */
5400
5401 static void s2io_ethtool_gregs(struct net_device *dev,
5402                                struct ethtool_regs *regs, void *space)
5403 {
5404         int i;
5405         u64 reg;
5406         u8 *reg_space = (u8 *)space;
5407         struct s2io_nic *sp = netdev_priv(dev);
5408
5409         regs->len = XENA_REG_SPACE;
5410         regs->version = sp->pdev->subsystem_device;
5411
5412         for (i = 0; i < regs->len; i += 8) {
5413                 reg = readq(sp->bar0 + i);
5414                 memcpy((reg_space + i), &reg, 8);
5415         }
5416 }
5417
5418 /*
5419  *  s2io_set_led - control NIC led
5420  */
5421 static void s2io_set_led(struct s2io_nic *sp, bool on)
5422 {
5423         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5424         u16 subid = sp->pdev->subsystem_device;
5425         u64 val64;
5426
5427         if ((sp->device_type == XFRAME_II_DEVICE) ||
5428             ((subid & 0xFF) >= 0x07)) {
5429                 val64 = readq(&bar0->gpio_control);
5430                 if (on)
5431                         val64 |= GPIO_CTRL_GPIO_0;
5432                 else
5433                         val64 &= ~GPIO_CTRL_GPIO_0;
5434
5435                 writeq(val64, &bar0->gpio_control);
5436         } else {
5437                 val64 = readq(&bar0->adapter_control);
5438                 if (on)
5439                         val64 |= ADAPTER_LED_ON;
5440                 else
5441                         val64 &= ~ADAPTER_LED_ON;
5442
5443                 writeq(val64, &bar0->adapter_control);
5444         }
5445
5446 }
5447
5448 /**
5449  * s2io_ethtool_set_led - To physically identify the nic on the system.
5450  * @dev : network device
5451  * @state: led setting
5452  *
5453  * Description: Used to physically identify the NIC on the system.
5454  * The Link LED will blink for a time specified by the user for
5455  * identification.
5456  * NOTE: The Link has to be Up to be able to blink the LED. Hence
5457  * identification is possible only if it's link is up.
5458  */
5459
5460 static int s2io_ethtool_set_led(struct net_device *dev,
5461                                 enum ethtool_phys_id_state state)
5462 {
5463         struct s2io_nic *sp = netdev_priv(dev);
5464         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5465         u16 subid = sp->pdev->subsystem_device;
5466
5467         if ((sp->device_type == XFRAME_I_DEVICE) && ((subid & 0xFF) < 0x07)) {
5468                 u64 val64 = readq(&bar0->adapter_control);
5469                 if (!(val64 & ADAPTER_CNTL_EN)) {
5470                         pr_err("Adapter Link down, cannot blink LED\n");
5471                         return -EAGAIN;
5472                 }
5473         }
5474
5475         switch (state) {
5476         case ETHTOOL_ID_ACTIVE:
5477                 sp->adapt_ctrl_org = readq(&bar0->gpio_control);
5478                 return 1;       /* cycle on/off once per second */
5479
5480         case ETHTOOL_ID_ON:
5481                 s2io_set_led(sp, true);
5482                 break;
5483
5484         case ETHTOOL_ID_OFF:
5485                 s2io_set_led(sp, false);
5486                 break;
5487
5488         case ETHTOOL_ID_INACTIVE:
5489                 if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid))
5490                         writeq(sp->adapt_ctrl_org, &bar0->gpio_control);
5491         }
5492
5493         return 0;
5494 }
5495
5496 static void s2io_ethtool_gringparam(struct net_device *dev,
5497                                     struct ethtool_ringparam *ering)
5498 {
5499         struct s2io_nic *sp = netdev_priv(dev);
5500         int i, tx_desc_count = 0, rx_desc_count = 0;
5501
5502         if (sp->rxd_mode == RXD_MODE_1) {
5503                 ering->rx_max_pending = MAX_RX_DESC_1;
5504                 ering->rx_jumbo_max_pending = MAX_RX_DESC_1;
5505         } else {
5506                 ering->rx_max_pending = MAX_RX_DESC_2;
5507                 ering->rx_jumbo_max_pending = MAX_RX_DESC_2;
5508         }
5509
5510         ering->tx_max_pending = MAX_TX_DESC;
5511
5512         for (i = 0; i < sp->config.rx_ring_num; i++)
5513                 rx_desc_count += sp->config.rx_cfg[i].num_rxd;
5514         ering->rx_pending = rx_desc_count;
5515         ering->rx_jumbo_pending = rx_desc_count;
5516
5517         for (i = 0; i < sp->config.tx_fifo_num; i++)
5518                 tx_desc_count += sp->config.tx_cfg[i].fifo_len;
5519         ering->tx_pending = tx_desc_count;
5520         DBG_PRINT(INFO_DBG, "max txds: %d\n", sp->config.max_txds);
5521 }
5522
5523 /**
5524  * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
5525  * @sp : private member of the device structure, which is a pointer to the
5526  *      s2io_nic structure.
5527  * @ep : pointer to the structure with pause parameters given by ethtool.
5528  * Description:
5529  * Returns the Pause frame generation and reception capability of the NIC.
5530  * Return value:
5531  *  void
5532  */
5533 static void s2io_ethtool_getpause_data(struct net_device *dev,
5534                                        struct ethtool_pauseparam *ep)
5535 {
5536         u64 val64;
5537         struct s2io_nic *sp = netdev_priv(dev);
5538         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5539
5540         val64 = readq(&bar0->rmac_pause_cfg);
5541         if (val64 & RMAC_PAUSE_GEN_ENABLE)
5542                 ep->tx_pause = true;
5543         if (val64 & RMAC_PAUSE_RX_ENABLE)
5544                 ep->rx_pause = true;
5545         ep->autoneg = false;
5546 }
5547
5548 /**
5549  * s2io_ethtool_setpause_data -  set/reset pause frame generation.
5550  * @sp : private member of the device structure, which is a pointer to the
5551  *      s2io_nic structure.
5552  * @ep : pointer to the structure with pause parameters given by ethtool.
5553  * Description:
5554  * It can be used to set or reset Pause frame generation or reception
5555  * support of the NIC.
5556  * Return value:
5557  * int, returns 0 on Success
5558  */
5559
5560 static int s2io_ethtool_setpause_data(struct net_device *dev,
5561                                       struct ethtool_pauseparam *ep)
5562 {
5563         u64 val64;
5564         struct s2io_nic *sp = netdev_priv(dev);
5565         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5566
5567         val64 = readq(&bar0->rmac_pause_cfg);
5568         if (ep->tx_pause)
5569                 val64 |= RMAC_PAUSE_GEN_ENABLE;
5570         else
5571                 val64 &= ~RMAC_PAUSE_GEN_ENABLE;
5572         if (ep->rx_pause)
5573                 val64 |= RMAC_PAUSE_RX_ENABLE;
5574         else
5575                 val64 &= ~RMAC_PAUSE_RX_ENABLE;
5576         writeq(val64, &bar0->rmac_pause_cfg);
5577         return 0;
5578 }
5579
5580 /**
5581  * read_eeprom - reads 4 bytes of data from user given offset.
5582  * @sp : private member of the device structure, which is a pointer to the
5583  *      s2io_nic structure.
5584  * @off : offset at which the data must be written
5585  * @data : Its an output parameter where the data read at the given
5586  *      offset is stored.
5587  * Description:
5588  * Will read 4 bytes of data from the user given offset and return the
5589  * read data.
5590  * NOTE: Will allow to read only part of the EEPROM visible through the
5591  *   I2C bus.
5592  * Return value:
5593  *  -1 on failure and 0 on success.
5594  */
5595
5596 #define S2IO_DEV_ID             5
5597 static int read_eeprom(struct s2io_nic *sp, int off, u64 *data)
5598 {
5599         int ret = -1;
5600         u32 exit_cnt = 0;
5601         u64 val64;
5602         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5603
5604         if (sp->device_type == XFRAME_I_DEVICE) {
5605                 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) |
5606                         I2C_CONTROL_ADDR(off) |
5607                         I2C_CONTROL_BYTE_CNT(0x3) |
5608                         I2C_CONTROL_READ |
5609                         I2C_CONTROL_CNTL_START;
5610                 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5611
5612                 while (exit_cnt < 5) {
5613                         val64 = readq(&bar0->i2c_control);
5614                         if (I2C_CONTROL_CNTL_END(val64)) {
5615                                 *data = I2C_CONTROL_GET_DATA(val64);
5616                                 ret = 0;
5617                                 break;
5618                         }
5619                         msleep(50);
5620                         exit_cnt++;
5621                 }
5622         }
5623
5624         if (sp->device_type == XFRAME_II_DEVICE) {
5625                 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
5626                         SPI_CONTROL_BYTECNT(0x3) |
5627                         SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off);
5628                 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5629                 val64 |= SPI_CONTROL_REQ;
5630                 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5631                 while (exit_cnt < 5) {
5632                         val64 = readq(&bar0->spi_control);
5633                         if (val64 & SPI_CONTROL_NACK) {
5634                                 ret = 1;
5635                                 break;
5636                         } else if (val64 & SPI_CONTROL_DONE) {
5637                                 *data = readq(&bar0->spi_data);
5638                                 *data &= 0xffffff;
5639                                 ret = 0;
5640                                 break;
5641                         }
5642                         msleep(50);
5643                         exit_cnt++;
5644                 }
5645         }
5646         return ret;
5647 }
5648
5649 /**
5650  *  write_eeprom - actually writes the relevant part of the data value.
5651  *  @sp : private member of the device structure, which is a pointer to the
5652  *       s2io_nic structure.
5653  *  @off : offset at which the data must be written
5654  *  @data : The data that is to be written
5655  *  @cnt : Number of bytes of the data that are actually to be written into
5656  *  the Eeprom. (max of 3)
5657  * Description:
5658  *  Actually writes the relevant part of the data value into the Eeprom
5659  *  through the I2C bus.
5660  * Return value:
5661  *  0 on success, -1 on failure.
5662  */
5663
5664 static int write_eeprom(struct s2io_nic *sp, int off, u64 data, int cnt)
5665 {
5666         int exit_cnt = 0, ret = -1;
5667         u64 val64;
5668         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5669
5670         if (sp->device_type == XFRAME_I_DEVICE) {
5671                 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) |
5672                         I2C_CONTROL_ADDR(off) |
5673                         I2C_CONTROL_BYTE_CNT(cnt) |
5674                         I2C_CONTROL_SET_DATA((u32)data) |
5675                         I2C_CONTROL_CNTL_START;
5676                 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5677
5678                 while (exit_cnt < 5) {
5679                         val64 = readq(&bar0->i2c_control);
5680                         if (I2C_CONTROL_CNTL_END(val64)) {
5681                                 if (!(val64 & I2C_CONTROL_NACK))
5682                                         ret = 0;
5683                                 break;
5684                         }
5685                         msleep(50);
5686                         exit_cnt++;
5687                 }
5688         }
5689
5690         if (sp->device_type == XFRAME_II_DEVICE) {
5691                 int write_cnt = (cnt == 8) ? 0 : cnt;
5692                 writeq(SPI_DATA_WRITE(data, (cnt << 3)), &bar0->spi_data);
5693
5694                 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
5695                         SPI_CONTROL_BYTECNT(write_cnt) |
5696                         SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off);
5697                 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5698                 val64 |= SPI_CONTROL_REQ;
5699                 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5700                 while (exit_cnt < 5) {
5701                         val64 = readq(&bar0->spi_control);
5702                         if (val64 & SPI_CONTROL_NACK) {
5703                                 ret = 1;
5704                                 break;
5705                         } else if (val64 & SPI_CONTROL_DONE) {
5706                                 ret = 0;
5707                                 break;
5708                         }
5709                         msleep(50);
5710                         exit_cnt++;
5711                 }
5712         }
5713         return ret;
5714 }
5715 static void s2io_vpd_read(struct s2io_nic *nic)
5716 {
5717         u8 *vpd_data;
5718         u8 data;
5719         int i = 0, cnt, len, fail = 0;
5720         int vpd_addr = 0x80;
5721         struct swStat *swstats = &nic->mac_control.stats_info->sw_stat;
5722
5723         if (nic->device_type == XFRAME_II_DEVICE) {
5724                 strcpy(nic->product_name, "Xframe II 10GbE network adapter");
5725                 vpd_addr = 0x80;
5726         } else {
5727                 strcpy(nic->product_name, "Xframe I 10GbE network adapter");
5728                 vpd_addr = 0x50;
5729         }
5730         strcpy(nic->serial_num, "NOT AVAILABLE");
5731
5732         vpd_data = kmalloc(256, GFP_KERNEL);
5733         if (!vpd_data) {
5734                 swstats->mem_alloc_fail_cnt++;
5735                 return;
5736         }
5737         swstats->mem_allocated += 256;
5738
5739         for (i = 0; i < 256; i += 4) {
5740                 pci_write_config_byte(nic->pdev, (vpd_addr + 2), i);
5741                 pci_read_config_byte(nic->pdev,  (vpd_addr + 2), &data);
5742                 pci_write_config_byte(nic->pdev, (vpd_addr + 3), 0);
5743                 for (cnt = 0; cnt < 5; cnt++) {
5744                         msleep(2);
5745                         pci_read_config_byte(nic->pdev, (vpd_addr + 3), &data);
5746                         if (data == 0x80)
5747                                 break;
5748                 }
5749                 if (cnt >= 5) {
5750                         DBG_PRINT(ERR_DBG, "Read of VPD data failed\n");
5751                         fail = 1;
5752                         break;
5753                 }
5754                 pci_read_config_dword(nic->pdev,  (vpd_addr + 4),
5755                                       (u32 *)&vpd_data[i]);
5756         }
5757
5758         if (!fail) {
5759                 /* read serial number of adapter */
5760                 for (cnt = 0; cnt < 252; cnt++) {
5761                         if ((vpd_data[cnt] == 'S') &&
5762                             (vpd_data[cnt+1] == 'N')) {
5763                                 len = vpd_data[cnt+2];
5764                                 if (len < min(VPD_STRING_LEN, 256-cnt-2)) {
5765                                         memcpy(nic->serial_num,
5766                                                &vpd_data[cnt + 3],
5767                                                len);
5768                                         memset(nic->serial_num+len,
5769                                                0,
5770                                                VPD_STRING_LEN-len);
5771                                         break;
5772                                 }
5773                         }
5774                 }
5775         }
5776
5777         if ((!fail) && (vpd_data[1] < VPD_STRING_LEN)) {
5778                 len = vpd_data[1];
5779                 memcpy(nic->product_name, &vpd_data[3], len);
5780                 nic->product_name[len] = 0;
5781         }
5782         kfree(vpd_data);
5783         swstats->mem_freed += 256;
5784 }
5785
5786 /**
5787  *  s2io_ethtool_geeprom  - reads the value stored in the Eeprom.
5788  *  @sp : private member of the device structure, which is a pointer to the
5789  *  s2io_nic structure.
5790  *  @eeprom : pointer to the user level structure provided by ethtool,
5791  *  containing all relevant information.
5792  *  @data_buf : user defined value to be written into Eeprom.
5793  *  Description: Reads the values stored in the Eeprom at given offset
5794  *  for a given length. Stores these values int the input argument data
5795  *  buffer 'data_buf' and returns these to the caller (ethtool.)
5796  *  Return value:
5797  *  int  0 on success
5798  */
5799
5800 static int s2io_ethtool_geeprom(struct net_device *dev,
5801                                 struct ethtool_eeprom *eeprom, u8 * data_buf)
5802 {
5803         u32 i, valid;
5804         u64 data;
5805         struct s2io_nic *sp = netdev_priv(dev);
5806
5807         eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
5808
5809         if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE))
5810                 eeprom->len = XENA_EEPROM_SPACE - eeprom->offset;
5811
5812         for (i = 0; i < eeprom->len; i += 4) {
5813                 if (read_eeprom(sp, (eeprom->offset + i), &data)) {
5814                         DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n");
5815                         return -EFAULT;
5816                 }
5817                 valid = INV(data);
5818                 memcpy((data_buf + i), &valid, 4);
5819         }
5820         return 0;
5821 }
5822
5823 /**
5824  *  s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
5825  *  @sp : private member of the device structure, which is a pointer to the
5826  *  s2io_nic structure.
5827  *  @eeprom : pointer to the user level structure provided by ethtool,
5828  *  containing all relevant information.
5829  *  @data_buf ; user defined value to be written into Eeprom.
5830  *  Description:
5831  *  Tries to write the user provided value in the Eeprom, at the offset
5832  *  given by the user.
5833  *  Return value:
5834  *  0 on success, -EFAULT on failure.
5835  */
5836
5837 static int s2io_ethtool_seeprom(struct net_device *dev,
5838                                 struct ethtool_eeprom *eeprom,
5839                                 u8 *data_buf)
5840 {
5841         int len = eeprom->len, cnt = 0;
5842         u64 valid = 0, data;
5843         struct s2io_nic *sp = netdev_priv(dev);
5844
5845         if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
5846                 DBG_PRINT(ERR_DBG,
5847                           "ETHTOOL_WRITE_EEPROM Err: "
5848                           "Magic value is wrong, it is 0x%x should be 0x%x\n",
5849                           (sp->pdev->vendor | (sp->pdev->device << 16)),
5850                           eeprom->magic);
5851                 return -EFAULT;
5852         }
5853
5854         while (len) {
5855                 data = (u32)data_buf[cnt] & 0x000000FF;
5856                 if (data)
5857                         valid = (u32)(data << 24);
5858                 else
5859                         valid = data;
5860
5861                 if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) {
5862                         DBG_PRINT(ERR_DBG,
5863                                   "ETHTOOL_WRITE_EEPROM Err: "
5864                                   "Cannot write into the specified offset\n");
5865                         return -EFAULT;
5866                 }
5867                 cnt++;
5868                 len--;
5869         }
5870
5871         return 0;
5872 }
5873
5874 /**
5875  * s2io_register_test - reads and writes into all clock domains.
5876  * @sp : private member of the device structure, which is a pointer to the
5877  * s2io_nic structure.
5878  * @data : variable that returns the result of each of the test conducted b
5879  * by the driver.
5880  * Description:
5881  * Read and write into all clock domains. The NIC has 3 clock domains,
5882  * see that registers in all the three regions are accessible.
5883  * Return value:
5884  * 0 on success.
5885  */
5886
5887 static int s2io_register_test(struct s2io_nic *sp, uint64_t *data)
5888 {
5889         struct XENA_dev_config __iomem *bar0 = sp->bar0;
5890         u64 val64 = 0, exp_val;
5891         int fail = 0;
5892
5893         val64 = readq(&bar0->pif_rd_swapper_fb);
5894         if (val64 != 0x123456789abcdefULL) {
5895                 fail = 1;
5896                 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 1);
5897         }
5898
5899         val64 = readq(&bar0->rmac_pause_cfg);
5900         if (val64 != 0xc000ffff00000000ULL) {
5901                 fail = 1;
5902                 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 2);
5903         }
5904
5905         val64 = readq(&bar0->rx_queue_cfg);
5906         if (sp->device_type == XFRAME_II_DEVICE)
5907                 exp_val = 0x0404040404040404ULL;
5908         else
5909                 exp_val = 0x0808080808080808ULL;
5910         if (val64 != exp_val) {
5911                 fail = 1;
5912                 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 3);
5913         }
5914
5915         val64 = readq(&bar0->xgxs_efifo_cfg);
5916         if (val64 != 0x000000001923141EULL) {
5917                 fail = 1;
5918                 DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 4);
5919         }
5920
5921         val64 = 0x5A5A5A5A5A5A5A5AULL;
5922         writeq(val64, &bar0->xmsi_data);
5923         val64 = readq(&bar0->xmsi_data);
5924         if (val64 != 0x5A5A5A5A5A5A5A5AULL) {
5925                 fail = 1;
5926                 DBG_PRINT(ERR_DBG, "Write Test level %d fails\n", 1);
5927         }
5928
5929         val64 = 0xA5A5A5A5A5A5A5A5ULL;
5930         writeq(val64, &bar0->xmsi_data);
5931         val64 = readq(&bar0->xmsi_data);
5932         if (val64 != 0xA5A5A5A5A5A5A5A5ULL) {
5933                 fail = 1;
5934                 DBG_PRINT(ERR_DBG, "Write Test level %d fails\n", 2);
5935         }
5936
5937         *data = fail;
5938         return fail;
5939 }
5940
5941 /**
5942  * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
5943  * @sp : private member of the device structure, which is a pointer to the
5944  * s2io_nic structure.
5945  * @data:variable that returns the result of each of the test conducted by
5946  * the driver.
5947  * Description:
5948  * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
5949  * register.
5950  * Return value:
5951  * 0 on success.
5952  */
5953
5954 static int s2io_eeprom_test(struct s2io_nic *sp, uint64_t *data)
5955 {
5956         int fail = 0;
5957         u64 ret_data, org_4F0, org_7F0;
5958         u8 saved_4F0 = 0, saved_7F0 = 0;
5959         struct net_device *dev = sp->dev;
5960
5961         /* Test Write Error at offset 0 */
5962         /* Note that SPI interface allows write access to all areas
5963          * of EEPROM. Hence doing all negative testing only for Xframe I.
5964          */
5965         if (sp->device_type == XFRAME_I_DEVICE)
5966                 if (!write_eeprom(sp, 0, 0, 3))
5967                         fail = 1;
5968
5969         /* Save current values at offsets 0x4F0 and 0x7F0 */
5970         if (!read_eeprom(sp, 0x4F0, &org_4F0))
5971                 saved_4F0 = 1;
5972         if (!read_eeprom(sp, 0x7F0, &org_7F0))
5973                 saved_7F0 = 1;
5974
5975         /* Test Write at offset 4f0 */
5976         if (write_eeprom(sp, 0x4F0, 0x012345, 3))
5977                 fail = 1;
5978         if (read_eeprom(sp, 0x4F0, &ret_data))
5979                 fail = 1;
5980
5981         if (ret_data != 0x012345) {
5982                 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x4F0. "
5983                           "Data written %llx Data read %llx\n",
5984                           dev->name, (unsigned long long)0x12345,
5985                           (unsigned long long)ret_data);
5986                 fail = 1;
5987         }
5988
5989         /* Reset the EEPROM data go FFFF */
5990         write_eeprom(sp, 0x4F0, 0xFFFFFF, 3);
5991
5992         /* Test Write Request Error at offset 0x7c */
5993         if (sp->device_type == XFRAME_I_DEVICE)
5994                 if (!write_eeprom(sp, 0x07C, 0, 3))
5995                         fail = 1;
5996
5997         /* Test Write Request at offset 0x7f0 */
5998         if (write_eeprom(sp, 0x7F0, 0x012345, 3))
5999                 fail = 1;
6000         if (read_eeprom(sp, 0x7F0, &ret_data))
6001                 fail = 1;
6002
6003         if (ret_data != 0x012345) {
6004                 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x7F0. "
6005                           "Data written %llx Data read %llx\n",
6006                           dev->name, (unsigned long long)0x12345,
6007                           (unsigned long long)ret_data);
6008                 fail = 1;
6009         }
6010
6011         /* Reset the EEPROM data go FFFF */
6012         write_eeprom(sp, 0x7F0, 0xFFFFFF, 3);
6013
6014         if (sp->device_type == XFRAME_I_DEVICE) {
6015                 /* Test Write Error at offset 0x80 */
6016                 if (!write_eeprom(sp, 0x080, 0, 3))
6017                         fail = 1;
6018
6019                 /* Test Write Error at offset 0xfc */
6020                 if (!write_eeprom(sp, 0x0FC, 0, 3))
6021                         fail = 1;
6022
6023                 /* Test Write Error at offset 0x100 */
6024                 if (!write_eeprom(sp, 0x100, 0, 3))
6025                         fail = 1;
6026
6027                 /* Test Write Error at offset 4ec */
6028                 if (!write_eeprom(sp, 0x4EC, 0, 3))
6029                         fail = 1;
6030         }
6031
6032         /* Restore values at offsets 0x4F0 and 0x7F0 */
6033         if (saved_4F0)
6034                 write_eeprom(sp, 0x4F0, org_4F0, 3);
6035         if (saved_7F0)
6036                 write_eeprom(sp, 0x7F0, org_7F0, 3);
6037
6038         *data = fail;
6039         return fail;
6040 }
6041
6042 /**
6043  * s2io_bist_test - invokes the MemBist test of the card .
6044  * @sp : private member of the device structure, which is a pointer to the
6045  * s2io_nic structure.
6046  * @data:variable that returns the result of each of the test conducted by
6047  * the driver.
6048  * Description:
6049  * This invokes the MemBist test of the card. We give around
6050  * 2 secs time for the Test to complete. If it's still not complete
6051  * within this peiod, we consider that the test failed.
6052  * Return value:
6053  * 0 on success and -1 on failure.
6054  */
6055
6056 static int s2io_bist_test(struct s2io_nic *sp, uint64_t *data)
6057 {
6058         u8 bist = 0;
6059         int cnt = 0, ret = -1;
6060
6061         pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6062         bist |= PCI_BIST_START;
6063         pci_write_config_word(sp->pdev, PCI_BIST, bist);
6064
6065         while (cnt < 20) {
6066                 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6067                 if (!(bist & PCI_BIST_START)) {
6068                         *data = (bist & PCI_BIST_CODE_MASK);
6069                         ret = 0;
6070                         break;
6071                 }
6072                 msleep(100);
6073                 cnt++;
6074         }
6075
6076         return ret;
6077 }
6078
6079 /**
6080  * s2io_link_test - verifies the link state of the nic
6081  * @sp ; private member of the device structure, which is a pointer to the
6082  * s2io_nic structure.
6083  * @data: variable that returns the result of each of the test conducted by
6084  * the driver.
6085  * Description:
6086  * The function verifies the link state of the NIC and updates the input
6087  * argument 'data' appropriately.
6088  * Return value:
6089  * 0 on success.
6090  */
6091
6092 static int s2io_link_test(struct s2io_nic *sp, uint64_t *data)
6093 {
6094         struct XENA_dev_config __iomem *bar0 = sp->bar0;
6095         u64 val64;
6096
6097         val64 = readq(&bar0->adapter_status);
6098         if (!(LINK_IS_UP(val64)))
6099                 *data = 1;
6100         else
6101                 *data = 0;
6102
6103         return *data;
6104 }
6105
6106 /**
6107  * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
6108  * @sp: private member of the device structure, which is a pointer to the
6109  * s2io_nic structure.
6110  * @data: variable that returns the result of each of the test
6111  * conducted by the driver.
6112  * Description:
6113  *  This is one of the offline test that tests the read and write
6114  *  access to the RldRam chip on the NIC.
6115  * Return value:
6116  *  0 on success.
6117  */
6118
6119 static int s2io_rldram_test(struct s2io_nic *sp, uint64_t *data)
6120 {
6121         struct XENA_dev_config __iomem *bar0 = sp->bar0;
6122         u64 val64;
6123         int cnt, iteration = 0, test_fail = 0;
6124
6125         val64 = readq(&bar0->adapter_control);
6126         val64 &= ~ADAPTER_ECC_EN;
6127         writeq(val64, &bar0->adapter_control);
6128
6129         val64 = readq(&bar0->mc_rldram_test_ctrl);
6130         val64 |= MC_RLDRAM_TEST_MODE;
6131         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6132
6133         val64 = readq(&bar0->mc_rldram_mrs);
6134         val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
6135         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6136
6137         val64 |= MC_RLDRAM_MRS_ENABLE;
6138         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6139
6140         while (iteration < 2) {
6141                 val64 = 0x55555555aaaa0000ULL;
6142                 if (iteration == 1)
6143                         val64 ^= 0xFFFFFFFFFFFF0000ULL;
6144                 writeq(val64, &bar0->mc_rldram_test_d0);
6145
6146                 val64 = 0xaaaa5a5555550000ULL;
6147                 if (iteration == 1)
6148                         val64 ^= 0xFFFFFFFFFFFF0000ULL;
6149                 writeq(val64, &bar0->mc_rldram_test_d1);
6150
6151                 val64 = 0x55aaaaaaaa5a0000ULL;
6152                 if (iteration == 1)
6153                         val64 ^= 0xFFFFFFFFFFFF0000ULL;
6154                 writeq(val64, &bar0->mc_rldram_test_d2);
6155
6156                 val64 = (u64) (0x0000003ffffe0100ULL);
6157                 writeq(val64, &bar0->mc_rldram_test_add);
6158
6159                 val64 = MC_RLDRAM_TEST_MODE |
6160                         MC_RLDRAM_TEST_WRITE |
6161                         MC_RLDRAM_TEST_GO;
6162                 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6163
6164                 for (cnt = 0; cnt < 5; cnt++) {
6165                         val64 = readq(&bar0->mc_rldram_test_ctrl);
6166                         if (val64 & MC_RLDRAM_TEST_DONE)
6167                                 break;
6168                         msleep(200);
6169                 }
6170
6171                 if (cnt == 5)
6172                         break;
6173
6174                 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
6175                 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6176
6177                 for (cnt = 0; cnt < 5; cnt++) {
6178                         val64 = readq(&bar0->mc_rldram_test_ctrl);
6179                         if (val64 & MC_RLDRAM_TEST_DONE)
6180                                 break;
6181                         msleep(500);
6182                 }
6183
6184                 if (cnt == 5)
6185                         break;
6186
6187                 val64 = readq(&bar0->mc_rldram_test_ctrl);
6188                 if (!(val64 & MC_RLDRAM_TEST_PASS))
6189                         test_fail = 1;
6190
6191                 iteration++;
6192         }
6193
6194         *data = test_fail;
6195
6196         /* Bring the adapter out of test mode */
6197         SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF);
6198
6199         return test_fail;
6200 }
6201
6202 /**
6203  *  s2io_ethtool_test - conducts 6 tsets to determine the health of card.
6204  *  @sp : private member of the device structure, which is a pointer to the
6205  *  s2io_nic structure.
6206  *  @ethtest : pointer to a ethtool command specific structure that will be
6207  *  returned to the user.
6208  *  @data : variable that returns the result of each of the test
6209  * conducted by the driver.
6210  * Description:
6211  *  This function conducts 6 tests ( 4 offline and 2 online) to determine
6212  *  the health of the card.
6213  * Return value:
6214  *  void
6215  */
6216
6217 static void s2io_ethtool_test(struct net_device *dev,
6218                               struct ethtool_test *ethtest,
6219                               uint64_t *data)
6220 {
6221         struct s2io_nic *sp = netdev_priv(dev);
6222         int orig_state = netif_running(sp->dev);
6223
6224         if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
6225                 /* Offline Tests. */
6226                 if (orig_state)
6227                         s2io_close(sp->dev);
6228
6229                 if (s2io_register_test(sp, &data[0]))
6230                         ethtest->flags |= ETH_TEST_FL_FAILED;
6231
6232                 s2io_reset(sp);
6233
6234                 if (s2io_rldram_test(sp, &data[3]))
6235                         ethtest->flags |= ETH_TEST_FL_FAILED;
6236
6237                 s2io_reset(sp);
6238
6239                 if (s2io_eeprom_test(sp, &data[1]))
6240                         ethtest->flags |= ETH_TEST_FL_FAILED;
6241
6242                 if (s2io_bist_test(sp, &data[4]))
6243                         ethtest->flags |= ETH_TEST_FL_FAILED;
6244
6245                 if (orig_state)
6246                         s2io_open(sp->dev);
6247
6248                 data[2] = 0;
6249         } else {
6250                 /* Online Tests. */
6251                 if (!orig_state) {
6252                         DBG_PRINT(ERR_DBG, "%s: is not up, cannot run test\n",
6253                                   dev->name);
6254                         data[0] = -1;
6255                         data[1] = -1;
6256                         data[2] = -1;
6257                         data[3] = -1;
6258                         data[4] = -1;
6259                 }
6260
6261                 if (s2io_link_test(sp, &data[2]))
6262                         ethtest->flags |= ETH_TEST_FL_FAILED;
6263
6264                 data[0] = 0;
6265                 data[1] = 0;
6266                 data[3] = 0;
6267                 data[4] = 0;
6268         }
6269 }
6270
6271 static void s2io_get_ethtool_stats(struct net_device *dev,
6272                                    struct ethtool_stats *estats,
6273                                    u64 *tmp_stats)
6274 {
6275         int i = 0, k;
6276         struct s2io_nic *sp = netdev_priv(dev);
6277         struct stat_block *stats = sp->mac_control.stats_info;
6278         struct swStat *swstats = &stats->sw_stat;
6279         struct xpakStat *xstats = &stats->xpak_stat;
6280
6281         s2io_updt_stats(sp);
6282         tmp_stats[i++] =
6283                 (u64)le32_to_cpu(stats->tmac_frms_oflow) << 32  |
6284                 le32_to_cpu(stats->tmac_frms);
6285         tmp_stats[i++] =
6286                 (u64)le32_to_cpu(stats->tmac_data_octets_oflow) << 32 |
6287                 le32_to_cpu(stats->tmac_data_octets);
6288         tmp_stats[i++] = le64_to_cpu(stats->tmac_drop_frms);
6289         tmp_stats[i++] =
6290                 (u64)le32_to_cpu(stats->tmac_mcst_frms_oflow) << 32 |
6291                 le32_to_cpu(stats->tmac_mcst_frms);
6292         tmp_stats[i++] =
6293                 (u64)le32_to_cpu(stats->tmac_bcst_frms_oflow) << 32 |
6294                 le32_to_cpu(stats->tmac_bcst_frms);
6295         tmp_stats[i++] = le64_to_cpu(stats->tmac_pause_ctrl_frms);
6296         tmp_stats[i++] =
6297                 (u64)le32_to_cpu(stats->tmac_ttl_octets_oflow) << 32 |
6298                 le32_to_cpu(stats->tmac_ttl_octets);
6299         tmp_stats[i++] =
6300                 (u64)le32_to_cpu(stats->tmac_ucst_frms_oflow) << 32 |
6301                 le32_to_cpu(stats->tmac_ucst_frms);
6302         tmp_stats[i++] =
6303                 (u64)le32_to_cpu(stats->tmac_nucst_frms_oflow) << 32 |
6304                 le32_to_cpu(stats->tmac_nucst_frms);
6305         tmp_stats[i++] =
6306                 (u64)le32_to_cpu(stats->tmac_any_err_frms_oflow) << 32 |
6307                 le32_to_cpu(stats->tmac_any_err_frms);
6308         tmp_stats[i++] = le64_to_cpu(stats->tmac_ttl_less_fb_octets);
6309         tmp_stats[i++] = le64_to_cpu(stats->tmac_vld_ip_octets);
6310         tmp_stats[i++] =
6311                 (u64)le32_to_cpu(stats->tmac_vld_ip_oflow) << 32 |
6312                 le32_to_cpu(stats->tmac_vld_ip);
6313         tmp_stats[i++] =
6314                 (u64)le32_to_cpu(stats->tmac_drop_ip_oflow) << 32 |
6315                 le32_to_cpu(stats->tmac_drop_ip);
6316         tmp_stats[i++] =
6317                 (u64)le32_to_cpu(stats->tmac_icmp_oflow) << 32 |
6318                 le32_to_cpu(stats->tmac_icmp);
6319         tmp_stats[i++] =
6320                 (u64)le32_to_cpu(stats->tmac_rst_tcp_oflow) << 32 |
6321                 le32_to_cpu(stats->tmac_rst_tcp);
6322         tmp_stats[i++] = le64_to_cpu(stats->tmac_tcp);
6323         tmp_stats[i++] = (u64)le32_to_cpu(stats->tmac_udp_oflow) << 32 |
6324                 le32_to_cpu(stats->tmac_udp);
6325         tmp_stats[i++] =
6326                 (u64)le32_to_cpu(stats->rmac_vld_frms_oflow) << 32 |
6327                 le32_to_cpu(stats->rmac_vld_frms);
6328         tmp_stats[i++] =
6329                 (u64)le32_to_cpu(stats->rmac_data_octets_oflow) << 32 |
6330                 le32_to_cpu(stats->rmac_data_octets);
6331         tmp_stats[i++] = le64_to_cpu(stats->rmac_fcs_err_frms);
6332         tmp_stats[i++] = le64_to_cpu(stats->rmac_drop_frms);
6333         tmp_stats[i++] =
6334                 (u64)le32_to_cpu(stats->rmac_vld_mcst_frms_oflow) << 32 |
6335                 le32_to_cpu(stats->rmac_vld_mcst_frms);
6336         tmp_stats[i++] =
6337                 (u64)le32_to_cpu(stats->rmac_vld_bcst_frms_oflow) << 32 |
6338                 le32_to_cpu(stats->rmac_vld_bcst_frms);
6339         tmp_stats[i++] = le32_to_cpu(stats->rmac_in_rng_len_err_frms);
6340         tmp_stats[i++] = le32_to_cpu(stats->rmac_out_rng_len_err_frms);
6341         tmp_stats[i++] = le64_to_cpu(stats->rmac_long_frms);
6342         tmp_stats[i++] = le64_to_cpu(stats->rmac_pause_ctrl_frms);
6343         tmp_stats[i++] = le64_to_cpu(stats->rmac_unsup_ctrl_frms);
6344         tmp_stats[i++] =
6345                 (u64)le32_to_cpu(stats->rmac_ttl_octets_oflow) << 32 |
6346                 le32_to_cpu(stats->rmac_ttl_octets);
6347         tmp_stats[i++] =
6348                 (u64)le32_to_cpu(stats->rmac_accepted_ucst_frms_oflow) << 32
6349                 | le32_to_cpu(stats->rmac_accepted_ucst_frms);
6350         tmp_stats[i++] =
6351                 (u64)le32_to_cpu(stats->rmac_accepted_nucst_frms_oflow)
6352                 << 32 | le32_to_cpu(stats->rmac_accepted_nucst_frms);
6353         tmp_stats[i++] =
6354                 (u64)le32_to_cpu(stats->rmac_discarded_frms_oflow) << 32 |
6355                 le32_to_cpu(stats->rmac_discarded_frms);
6356         tmp_stats[i++] =
6357                 (u64)le32_to_cpu(stats->rmac_drop_events_oflow)
6358                 << 32 | le32_to_cpu(stats->rmac_drop_events);
6359         tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_less_fb_octets);
6360         tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_frms);
6361         tmp_stats[i++] =
6362                 (u64)le32_to_cpu(stats->rmac_usized_frms_oflow) << 32 |
6363                 le32_to_cpu(stats->rmac_usized_frms);
6364         tmp_stats[i++] =
6365                 (u64)le32_to_cpu(stats->rmac_osized_frms_oflow) << 32 |
6366                 le32_to_cpu(stats->rmac_osized_frms);
6367         tmp_stats[i++] =
6368                 (u64)le32_to_cpu(stats->rmac_frag_frms_oflow) << 32 |
6369                 le32_to_cpu(stats->rmac_frag_frms);
6370         tmp_stats[i++] =
6371                 (u64)le32_to_cpu(stats->rmac_jabber_frms_oflow) << 32 |
6372                 le32_to_cpu(stats->rmac_jabber_frms);
6373         tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_64_frms);
6374         tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_65_127_frms);
6375         tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_128_255_frms);
6376         tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_256_511_frms);
6377         tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_512_1023_frms);
6378         tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_1024_1518_frms);
6379         tmp_stats[i++] =
6380                 (u64)le32_to_cpu(stats->rmac_ip_oflow) << 32 |
6381                 le32_to_cpu(stats->rmac_ip);
6382         tmp_stats[i++] = le64_to_cpu(stats->rmac_ip_octets);
6383         tmp_stats[i++] = le32_to_cpu(stats->rmac_hdr_err_ip);
6384         tmp_stats[i++] =
6385                 (u64)le32_to_cpu(stats->rmac_drop_ip_oflow) << 32 |
6386                 le32_to_cpu(stats->rmac_drop_ip);
6387         tmp_stats[i++] =
6388                 (u64)le32_to_cpu(stats->rmac_icmp_oflow) << 32 |
6389                 le32_to_cpu(stats->rmac_icmp);
6390         tmp_stats[i++] = le64_to_cpu(stats->rmac_tcp);
6391         tmp_stats[i++] =
6392                 (u64)le32_to_cpu(stats->rmac_udp_oflow) << 32 |
6393                 le32_to_cpu(stats->rmac_udp);
6394         tmp_stats[i++] =
6395                 (u64)le32_to_cpu(stats->rmac_err_drp_udp_oflow) << 32 |
6396                 le32_to_cpu(stats->rmac_err_drp_udp);
6397         tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_err_sym);
6398         tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q0);
6399         tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q1);
6400         tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q2);
6401         tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q3);
6402         tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q4);
6403         tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q5);
6404         tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q6);
6405         tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q7);
6406         tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q0);
6407         tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q1);
6408         tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q2);
6409         tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q3);
6410         tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q4);
6411         tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q5);
6412         tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q6);
6413         tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q7);
6414         tmp_stats[i++] =
6415                 (u64)le32_to_cpu(stats->rmac_pause_cnt_oflow) << 32 |
6416                 le32_to_cpu(stats->rmac_pause_cnt);
6417         tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_data_err_cnt);
6418         tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_ctrl_err_cnt);
6419         tmp_stats[i++] =
6420                 (u64)le32_to_cpu(stats->rmac_accepted_ip_oflow) << 32 |
6421                 le32_to_cpu(stats->rmac_accepted_ip);
6422         tmp_stats[i++] = le32_to_cpu(stats->rmac_err_tcp);
6423         tmp_stats[i++] = le32_to_cpu(stats->rd_req_cnt);
6424         tmp_stats[i++] = le32_to_cpu(stats->new_rd_req_cnt);
6425         tmp_stats[i++] = le32_to_cpu(stats->new_rd_req_rtry_cnt);
6426         tmp_stats[i++] = le32_to_cpu(stats->rd_rtry_cnt);
6427         tmp_stats[i++] = le32_to_cpu(stats->wr_rtry_rd_ack_cnt);
6428         tmp_stats[i++] = le32_to_cpu(stats->wr_req_cnt);
6429         tmp_stats[i++] = le32_to_cpu(stats->new_wr_req_cnt);
6430         tmp_stats[i++] = le32_to_cpu(stats->new_wr_req_rtry_cnt);
6431         tmp_stats[i++] = le32_to_cpu(stats->wr_rtry_cnt);
6432         tmp_stats[i++] = le32_to_cpu(stats->wr_disc_cnt);
6433         tmp_stats[i++] = le32_to_cpu(stats->rd_rtry_wr_ack_cnt);
6434         tmp_stats[i++] = le32_to_cpu(stats->txp_wr_cnt);
6435         tmp_stats[i++] = le32_to_cpu(stats->txd_rd_cnt);
6436         tmp_stats[i++] = le32_to_cpu(stats->txd_wr_cnt);
6437         tmp_stats[i++] = le32_to_cpu(stats->rxd_rd_cnt);
6438         tmp_stats[i++] = le32_to_cpu(stats->rxd_wr_cnt);
6439         tmp_stats[i++] = le32_to_cpu(stats->txf_rd_cnt);
6440         tmp_stats[i++] = le32_to_cpu(stats->rxf_wr_cnt);
6441
6442         /* Enhanced statistics exist only for Hercules */
6443         if (sp->device_type == XFRAME_II_DEVICE) {
6444                 tmp_stats[i++] =
6445                         le64_to_cpu(stats->rmac_ttl_1519_4095_frms);
6446                 tmp_stats[i++] =
6447                         le64_to_cpu(stats->rmac_ttl_4096_8191_frms);
6448                 tmp_stats[i++] =
6449                         le64_to_cpu(stats->rmac_ttl_8192_max_frms);
6450                 tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_gt_max_frms);
6451                 tmp_stats[i++] = le64_to_cpu(stats->rmac_osized_alt_frms);
6452                 tmp_stats[i++] = le64_to_cpu(stats->rmac_jabber_alt_frms);
6453                 tmp_stats[i++] = le64_to_cpu(stats->rmac_gt_max_alt_frms);
6454                 tmp_stats[i++] = le64_to_cpu(stats->rmac_vlan_frms);
6455                 tmp_stats[i++] = le32_to_cpu(stats->rmac_len_discard);
6456                 tmp_stats[i++] = le32_to_cpu(stats->rmac_fcs_discard);
6457                 tmp_stats[i++] = le32_to_cpu(stats->rmac_pf_discard);
6458                 tmp_stats[i++] = le32_to_cpu(stats->rmac_da_discard);
6459                 tmp_stats[i++] = le32_to_cpu(stats->rmac_red_discard);
6460                 tmp_stats[i++] = le32_to_cpu(stats->rmac_rts_discard);
6461                 tmp_stats[i++] = le32_to_cpu(stats->rmac_ingm_full_discard);
6462                 tmp_stats[i++] = le32_to_cpu(stats->link_fault_cnt);
6463         }
6464
6465         tmp_stats[i++] = 0;
6466         tmp_stats[i++] = swstats->single_ecc_errs;
6467         tmp_stats[i++] = swstats->double_ecc_errs;
6468         tmp_stats[i++] = swstats->parity_err_cnt;
6469         tmp_stats[i++] = swstats->serious_err_cnt;
6470         tmp_stats[i++] = swstats->soft_reset_cnt;
6471         tmp_stats[i++] = swstats->fifo_full_cnt;
6472         for (k = 0; k < MAX_RX_RINGS; k++)
6473                 tmp_stats[i++] = swstats->ring_full_cnt[k];
6474         tmp_stats[i++] = xstats->alarm_transceiver_temp_high;
6475         tmp_stats[i++] = xstats->alarm_transceiver_temp_low;
6476         tmp_stats[i++] = xstats->alarm_laser_bias_current_high;
6477         tmp_stats[i++] = xstats->alarm_laser_bias_current_low;
6478         tmp_stats[i++] = xstats->alarm_laser_output_power_high;
6479         tmp_stats[i++] = xstats->alarm_laser_output_power_low;
6480         tmp_stats[i++] = xstats->warn_transceiver_temp_high;
6481         tmp_stats[i++] = xstats->warn_transceiver_temp_low;
6482         tmp_stats[i++] = xstats->warn_laser_bias_current_high;
6483         tmp_stats[i++] = xstats->warn_laser_bias_current_low;
6484         tmp_stats[i++] = xstats->warn_laser_output_power_high;
6485         tmp_stats[i++] = xstats->warn_laser_output_power_low;
6486         tmp_stats[i++] = swstats->clubbed_frms_cnt;
6487         tmp_stats[i++] = swstats->sending_both;
6488         tmp_stats[i++] = swstats->outof_sequence_pkts;
6489         tmp_stats[i++] = swstats->flush_max_pkts;
6490         if (swstats->num_aggregations) {
6491                 u64 tmp = swstats->sum_avg_pkts_aggregated;
6492                 int count = 0;
6493                 /*
6494                  * Since 64-bit divide does not work on all platforms,
6495                  * do repeated subtraction.
6496                  */
6497                 while (tmp >= swstats->num_aggregations) {
6498                         tmp -= swstats->num_aggregations;
6499                         count++;
6500                 }
6501                 tmp_stats[i++] = count;
6502         } else
6503                 tmp_stats[i++] = 0;
6504         tmp_stats[i++] = swstats->mem_alloc_fail_cnt;
6505         tmp_stats[i++] = swstats->pci_map_fail_cnt;
6506         tmp_stats[i++] = swstats->watchdog_timer_cnt;
6507         tmp_stats[i++] = swstats->mem_allocated;
6508         tmp_stats[i++] = swstats->mem_freed;
6509         tmp_stats[i++] = swstats->link_up_cnt;
6510         tmp_stats[i++] = swstats->link_down_cnt;
6511         tmp_stats[i++] = swstats->link_up_time;
6512         tmp_stats[i++] = swstats->link_down_time;
6513
6514         tmp_stats[i++] = swstats->tx_buf_abort_cnt;
6515         tmp_stats[i++] = swstats->tx_desc_abort_cnt;
6516         tmp_stats[i++] = swstats->tx_parity_err_cnt;
6517         tmp_stats[i++] = swstats->tx_link_loss_cnt;
6518         tmp_stats[i++] = swstats->tx_list_proc_err_cnt;
6519
6520         tmp_stats[i++] = swstats->rx_parity_err_cnt;
6521         tmp_stats[i++] = swstats->rx_abort_cnt;
6522         tmp_stats[i++] = swstats->rx_parity_abort_cnt;
6523         tmp_stats[i++] = swstats->rx_rda_fail_cnt;
6524         tmp_stats[i++] = swstats->rx_unkn_prot_cnt;
6525         tmp_stats[i++] = swstats->rx_fcs_err_cnt;
6526         tmp_stats[i++] = swstats->rx_buf_size_err_cnt;
6527         tmp_stats[i++] = swstats->rx_rxd_corrupt_cnt;
6528         tmp_stats[i++] = swstats->rx_unkn_err_cnt;
6529         tmp_stats[i++] = swstats->tda_err_cnt;
6530         tmp_stats[i++] = swstats->pfc_err_cnt;
6531         tmp_stats[i++] = swstats->pcc_err_cnt;
6532         tmp_stats[i++] = swstats->tti_err_cnt;
6533         tmp_stats[i++] = swstats->tpa_err_cnt;
6534         tmp_stats[i++] = swstats->sm_err_cnt;
6535         tmp_stats[i++] = swstats->lso_err_cnt;
6536         tmp_stats[i++] = swstats->mac_tmac_err_cnt;
6537         tmp_stats[i++] = swstats->mac_rmac_err_cnt;
6538         tmp_stats[i++] = swstats->xgxs_txgxs_err_cnt;
6539         tmp_stats[i++] = swstats->xgxs_rxgxs_err_cnt;
6540         tmp_stats[i++] = swstats->rc_err_cnt;
6541         tmp_stats[i++] = swstats->prc_pcix_err_cnt;
6542         tmp_stats[i++] = swstats->rpa_err_cnt;
6543         tmp_stats[i++] = swstats->rda_err_cnt;
6544         tmp_stats[i++] = swstats->rti_err_cnt;
6545         tmp_stats[i++] = swstats->mc_err_cnt;
6546 }
6547
6548 static int s2io_ethtool_get_regs_len(struct net_device *dev)
6549 {
6550         return XENA_REG_SPACE;
6551 }
6552
6553
6554 static int s2io_get_eeprom_len(struct net_device *dev)
6555 {
6556         return XENA_EEPROM_SPACE;
6557 }
6558
6559 static int s2io_get_sset_count(struct net_device *dev, int sset)
6560 {
6561         struct s2io_nic *sp = netdev_priv(dev);
6562
6563         switch (sset) {
6564         case ETH_SS_TEST:
6565                 return S2IO_TEST_LEN;
6566         case ETH_SS_STATS:
6567                 switch (sp->device_type) {
6568                 case XFRAME_I_DEVICE:
6569                         return XFRAME_I_STAT_LEN;
6570                 case XFRAME_II_DEVICE:
6571                         return XFRAME_II_STAT_LEN;
6572                 default:
6573                         return 0;
6574                 }
6575         default:
6576                 return -EOPNOTSUPP;
6577         }
6578 }
6579
6580 static void s2io_ethtool_get_strings(struct net_device *dev,
6581                                      u32 stringset, u8 *data)
6582 {
6583         int stat_size = 0;
6584         struct s2io_nic *sp = netdev_priv(dev);
6585
6586         switch (stringset) {
6587         case ETH_SS_TEST:
6588                 memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN);
6589                 break;
6590         case ETH_SS_STATS:
6591                 stat_size = sizeof(ethtool_xena_stats_keys);
6592                 memcpy(data, &ethtool_xena_stats_keys, stat_size);
6593                 if (sp->device_type == XFRAME_II_DEVICE) {
6594                         memcpy(data + stat_size,
6595                                &ethtool_enhanced_stats_keys,
6596                                sizeof(ethtool_enhanced_stats_keys));
6597                         stat_size += sizeof(ethtool_enhanced_stats_keys);
6598                 }
6599
6600                 memcpy(data + stat_size, &ethtool_driver_stats_keys,
6601                        sizeof(ethtool_driver_stats_keys));
6602         }
6603 }
6604
6605 static int s2io_set_features(struct net_device *dev, netdev_features_t features)
6606 {
6607         struct s2io_nic *sp = netdev_priv(dev);
6608         netdev_features_t changed = (features ^ dev->features) & NETIF_F_LRO;
6609
6610         if (changed && netif_running(dev)) {
6611                 int rc;
6612
6613                 s2io_stop_all_tx_queue(sp);
6614                 s2io_card_down(sp);
6615                 dev->features = features;
6616                 rc = s2io_card_up(sp);
6617                 if (rc)
6618                         s2io_reset(sp);
6619                 else
6620                         s2io_start_all_tx_queue(sp);
6621
6622                 return rc ? rc : 1;
6623         }
6624
6625         return 0;
6626 }
6627
6628 static const struct ethtool_ops netdev_ethtool_ops = {
6629         .get_settings = s2io_ethtool_gset,
6630         .set_settings = s2io_ethtool_sset,
6631         .get_drvinfo = s2io_ethtool_gdrvinfo,
6632         .get_regs_len = s2io_ethtool_get_regs_len,
6633         .get_regs = s2io_ethtool_gregs,
6634         .get_link = ethtool_op_get_link,
6635         .get_eeprom_len = s2io_get_eeprom_len,
6636         .get_eeprom = s2io_ethtool_geeprom,
6637         .set_eeprom = s2io_ethtool_seeprom,
6638         .get_ringparam = s2io_ethtool_gringparam,
6639         .get_pauseparam = s2io_ethtool_getpause_data,
6640         .set_pauseparam = s2io_ethtool_setpause_data,
6641         .self_test = s2io_ethtool_test,
6642         .get_strings = s2io_ethtool_get_strings,
6643         .set_phys_id = s2io_ethtool_set_led,
6644         .get_ethtool_stats = s2io_get_ethtool_stats,
6645         .get_sset_count = s2io_get_sset_count,
6646 };
6647
6648 /**
6649  *  s2io_ioctl - Entry point for the Ioctl
6650  *  @dev :  Device pointer.
6651  *  @ifr :  An IOCTL specefic structure, that can contain a pointer to
6652  *  a proprietary structure used to pass information to the driver.
6653  *  @cmd :  This is used to distinguish between the different commands that
6654  *  can be passed to the IOCTL functions.
6655  *  Description:
6656  *  Currently there are no special functionality supported in IOCTL, hence
6657  *  function always return EOPNOTSUPPORTED
6658  */
6659
6660 static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
6661 {
6662         return -EOPNOTSUPP;
6663 }
6664
6665 /**
6666  *  s2io_change_mtu - entry point to change MTU size for the device.
6667  *   @dev : device pointer.
6668  *   @new_mtu : the new MTU size for the device.
6669  *   Description: A driver entry point to change MTU size for the device.
6670  *   Before changing the MTU the device must be stopped.
6671  *  Return value:
6672  *   0 on success and an appropriate (-)ve integer as defined in errno.h
6673  *   file on failure.
6674  */
6675
6676 static int s2io_change_mtu(struct net_device *dev, int new_mtu)
6677 {
6678         struct s2io_nic *sp = netdev_priv(dev);
6679         int ret = 0;
6680
6681         if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) {
6682                 DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n", dev->name);
6683                 return -EPERM;
6684         }
6685
6686         dev->mtu = new_mtu;
6687         if (netif_running(dev)) {
6688                 s2io_stop_all_tx_queue(sp);
6689                 s2io_card_down(sp);
6690                 ret = s2io_card_up(sp);
6691                 if (ret) {
6692                         DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
6693                                   __func__);
6694                         return ret;
6695                 }
6696                 s2io_wake_all_tx_queue(sp);
6697         } else { /* Device is down */
6698                 struct XENA_dev_config __iomem *bar0 = sp->bar0;
6699                 u64 val64 = new_mtu;
6700
6701                 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
6702         }
6703
6704         return ret;
6705 }
6706
6707 /**
6708  * s2io_set_link - Set the LInk status
6709  * @data: long pointer to device private structue
6710  * Description: Sets the link status for the adapter
6711  */
6712
6713 static void s2io_set_link(struct work_struct *work)
6714 {
6715         struct s2io_nic *nic = container_of(work, struct s2io_nic,
6716                                             set_link_task);
6717         struct net_device *dev = nic->dev;
6718         struct XENA_dev_config __iomem *bar0 = nic->bar0;
6719         register u64 val64;
6720         u16 subid;
6721
6722         rtnl_lock();
6723
6724         if (!netif_running(dev))
6725                 goto out_unlock;
6726
6727         if (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(nic->state))) {
6728                 /* The card is being reset, no point doing anything */
6729                 goto out_unlock;
6730         }
6731
6732         subid = nic->pdev->subsystem_device;
6733         if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
6734                 /*
6735                  * Allow a small delay for the NICs self initiated
6736                  * cleanup to complete.
6737                  */
6738                 msleep(100);
6739         }
6740
6741         val64 = readq(&bar0->adapter_status);
6742         if (LINK_IS_UP(val64)) {
6743                 if (!(readq(&bar0->adapter_control) & ADAPTER_CNTL_EN)) {
6744                         if (verify_xena_quiescence(nic)) {
6745                                 val64 = readq(&bar0->adapter_control);
6746                                 val64 |= ADAPTER_CNTL_EN;
6747                                 writeq(val64, &bar0->adapter_control);
6748                                 if (CARDS_WITH_FAULTY_LINK_INDICATORS(
6749                                             nic->device_type, subid)) {
6750                                         val64 = readq(&bar0->gpio_control);
6751                                         val64 |= GPIO_CTRL_GPIO_0;
6752                                         writeq(val64, &bar0->gpio_control);
6753                                         val64 = readq(&bar0->gpio_control);
6754                                 } else {
6755                                         val64 |= ADAPTER_LED_ON;
6756                                         writeq(val64, &bar0->adapter_control);
6757                                 }
6758                                 nic->device_enabled_once = true;
6759                         } else {
6760                                 DBG_PRINT(ERR_DBG,
6761                                           "%s: Error: device is not Quiescent\n",
6762                                           dev->name);
6763                                 s2io_stop_all_tx_queue(nic);
6764                         }
6765                 }
6766                 val64 = readq(&bar0->adapter_control);
6767                 val64 |= ADAPTER_LED_ON;
6768                 writeq(val64, &bar0->adapter_control);
6769                 s2io_link(nic, LINK_UP);
6770         } else {
6771                 if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
6772                                                       subid)) {
6773                         val64 = readq(&bar0->gpio_control);
6774                         val64 &= ~GPIO_CTRL_GPIO_0;
6775                         writeq(val64, &bar0->gpio_control);
6776                         val64 = readq(&bar0->gpio_control);
6777                 }
6778                 /* turn off LED */
6779                 val64 = readq(&bar0->adapter_control);
6780                 val64 = val64 & (~ADAPTER_LED_ON);
6781                 writeq(val64, &bar0->adapter_control);
6782                 s2io_link(nic, LINK_DOWN);
6783         }
6784         clear_bit(__S2IO_STATE_LINK_TASK, &(nic->state));
6785
6786 out_unlock:
6787         rtnl_unlock();
6788 }
6789
6790 static int set_rxd_buffer_pointer(struct s2io_nic *sp, struct RxD_t *rxdp,
6791                                   struct buffAdd *ba,
6792                                   struct sk_buff **skb, u64 *temp0, u64 *temp1,
6793                                   u64 *temp2, int size)
6794 {
6795         struct net_device *dev = sp->dev;
6796         struct swStat *stats = &sp->mac_control.stats_info->sw_stat;
6797
6798         if ((sp->rxd_mode == RXD_MODE_1) && (rxdp->Host_Control == 0)) {
6799                 struct RxD1 *rxdp1 = (struct RxD1 *)rxdp;
6800                 /* allocate skb */
6801                 if (*skb) {
6802                         DBG_PRINT(INFO_DBG, "SKB is not NULL\n");
6803                         /*
6804                          * As Rx frame are not going to be processed,
6805                          * using same mapped address for the Rxd
6806                          * buffer pointer
6807                          */
6808                         rxdp1->Buffer0_ptr = *temp0;
6809                 } else {
6810                         *skb = netdev_alloc_skb(dev, size);
6811                         if (!(*skb)) {
6812                                 DBG_PRINT(INFO_DBG,
6813                                           "%s: Out of memory to allocate %s\n",
6814                                           dev->name, "1 buf mode SKBs");
6815                                 stats->mem_alloc_fail_cnt++;
6816                                 return -ENOMEM ;
6817                         }
6818                         stats->mem_allocated += (*skb)->truesize;
6819                         /* storing the mapped addr in a temp variable
6820                          * such it will be used for next rxd whose
6821                          * Host Control is NULL
6822                          */
6823                         rxdp1->Buffer0_ptr = *temp0 =
6824                                 pci_map_single(sp->pdev, (*skb)->data,
6825                                                size - NET_IP_ALIGN,
6826                                                PCI_DMA_FROMDEVICE);
6827                         if (pci_dma_mapping_error(sp->pdev, rxdp1->Buffer0_ptr))
6828                                 goto memalloc_failed;
6829                         rxdp->Host_Control = (unsigned long) (*skb);
6830                 }
6831         } else if ((sp->rxd_mode == RXD_MODE_3B) && (rxdp->Host_Control == 0)) {
6832                 struct RxD3 *rxdp3 = (struct RxD3 *)rxdp;
6833                 /* Two buffer Mode */
6834                 if (*skb) {
6835                         rxdp3->Buffer2_ptr = *temp2;
6836                         rxdp3->Buffer0_ptr = *temp0;
6837                         rxdp3->Buffer1_ptr = *temp1;
6838                 } else {
6839                         *skb = netdev_alloc_skb(dev, size);
6840                         if (!(*skb)) {
6841                                 DBG_PRINT(INFO_DBG,
6842                                           "%s: Out of memory to allocate %s\n",
6843                                           dev->name,
6844                                           "2 buf mode SKBs");
6845                                 stats->mem_alloc_fail_cnt++;
6846                                 return -ENOMEM;
6847                         }
6848                         stats->mem_allocated += (*skb)->truesize;
6849                         rxdp3->Buffer2_ptr = *temp2 =
6850                                 pci_map_single(sp->pdev, (*skb)->data,
6851                                                dev->mtu + 4,
6852                                                PCI_DMA_FROMDEVICE);
6853                         if (pci_dma_mapping_error(sp->pdev, rxdp3->Buffer2_ptr))
6854                                 goto memalloc_failed;
6855                         rxdp3->Buffer0_ptr = *temp0 =
6856                                 pci_map_single(sp->pdev, ba->ba_0, BUF0_LEN,
6857                                                PCI_DMA_FROMDEVICE);
6858                         if (pci_dma_mapping_error(sp->pdev,
6859                                                   rxdp3->Buffer0_ptr)) {
6860                                 pci_unmap_single(sp->pdev,
6861                                                  (dma_addr_t)rxdp3->Buffer2_ptr,
6862                                                  dev->mtu + 4,
6863                                                  PCI_DMA_FROMDEVICE);
6864                                 goto memalloc_failed;
6865                         }
6866                         rxdp->Host_Control = (unsigned long) (*skb);
6867
6868                         /* Buffer-1 will be dummy buffer not used */
6869                         rxdp3->Buffer1_ptr = *temp1 =
6870                                 pci_map_single(sp->pdev, ba->ba_1, BUF1_LEN,
6871                                                PCI_DMA_FROMDEVICE);
6872                         if (pci_dma_mapping_error(sp->pdev,
6873                                                   rxdp3->Buffer1_ptr)) {
6874                                 pci_unmap_single(sp->pdev,
6875                                                  (dma_addr_t)rxdp3->Buffer0_ptr,
6876                                                  BUF0_LEN, PCI_DMA_FROMDEVICE);
6877                                 pci_unmap_single(sp->pdev,
6878                                                  (dma_addr_t)rxdp3->Buffer2_ptr,
6879                                                  dev->mtu + 4,
6880                                                  PCI_DMA_FROMDEVICE);
6881                                 goto memalloc_failed;
6882                         }
6883                 }
6884         }
6885         return 0;
6886
6887 memalloc_failed:
6888         stats->pci_map_fail_cnt++;
6889         stats->mem_freed += (*skb)->truesize;
6890         dev_kfree_skb(*skb);
6891         return -ENOMEM;
6892 }
6893
6894 static void set_rxd_buffer_size(struct s2io_nic *sp, struct RxD_t *rxdp,
6895                                 int size)
6896 {
6897         struct net_device *dev = sp->dev;
6898         if (sp->rxd_mode == RXD_MODE_1) {
6899                 rxdp->Control_2 = SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
6900         } else if (sp->rxd_mode == RXD_MODE_3B) {
6901                 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
6902                 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
6903                 rxdp->Control_2 |= SET_BUFFER2_SIZE_3(dev->mtu + 4);
6904         }
6905 }
6906
6907 static  int rxd_owner_bit_reset(struct s2io_nic *sp)
6908 {
6909         int i, j, k, blk_cnt = 0, size;
6910         struct config_param *config = &sp->config;
6911         struct mac_info *mac_control = &sp->mac_control;
6912         struct net_device *dev = sp->dev;
6913         struct RxD_t *rxdp = NULL;
6914         struct sk_buff *skb = NULL;
6915         struct buffAdd *ba = NULL;
6916         u64 temp0_64 = 0, temp1_64 = 0, temp2_64 = 0;
6917
6918         /* Calculate the size based on ring mode */
6919         size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
6920                 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
6921         if (sp->rxd_mode == RXD_MODE_1)
6922                 size += NET_IP_ALIGN;
6923         else if (sp->rxd_mode == RXD_MODE_3B)
6924                 size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
6925
6926         for (i = 0; i < config->rx_ring_num; i++) {
6927                 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
6928                 struct ring_info *ring = &mac_control->rings[i];
6929
6930                 blk_cnt = rx_cfg->num_rxd / (rxd_count[sp->rxd_mode] + 1);
6931
6932                 for (j = 0; j < blk_cnt; j++) {
6933                         for (k = 0; k < rxd_count[sp->rxd_mode]; k++) {
6934                                 rxdp = ring->rx_blocks[j].rxds[k].virt_addr;
6935                                 if (sp->rxd_mode == RXD_MODE_3B)
6936                                         ba = &ring->ba[j][k];
6937                                 if (set_rxd_buffer_pointer(sp, rxdp, ba, &skb,
6938                                                            &temp0_64,
6939                                                            &temp1_64,
6940                                                            &temp2_64,
6941                                                            size) == -ENOMEM) {
6942                                         return 0;
6943                                 }
6944
6945                                 set_rxd_buffer_size(sp, rxdp, size);
6946                                 dma_wmb();
6947                                 /* flip the Ownership bit to Hardware */
6948                                 rxdp->Control_1 |= RXD_OWN_XENA;
6949                         }
6950                 }
6951         }
6952         return 0;
6953
6954 }
6955
6956 static int s2io_add_isr(struct s2io_nic *sp)
6957 {
6958         int ret = 0;
6959         struct net_device *dev = sp->dev;
6960         int err = 0;
6961
6962         if (sp->config.intr_type == MSI_X)
6963                 ret = s2io_enable_msi_x(sp);
6964         if (ret) {
6965                 DBG_PRINT(ERR_DBG, "%s: Defaulting to INTA\n", dev->name);
6966                 sp->config.intr_type = INTA;
6967         }
6968
6969         /*
6970          * Store the values of the MSIX table in
6971          * the struct s2io_nic structure
6972          */
6973         store_xmsi_data(sp);
6974
6975         /* After proper initialization of H/W, register ISR */
6976         if (sp->config.intr_type == MSI_X) {
6977                 int i, msix_rx_cnt = 0;
6978
6979                 for (i = 0; i < sp->num_entries; i++) {
6980                         if (sp->s2io_entries[i].in_use == MSIX_FLG) {
6981                                 if (sp->s2io_entries[i].type ==
6982                                     MSIX_RING_TYPE) {
6983                                         snprintf(sp->desc[i],
6984                                                 sizeof(sp->desc[i]),
6985                                                 "%s:MSI-X-%d-RX",
6986                                                 dev->name, i);
6987                                         err = request_irq(sp->entries[i].vector,
6988                                                           s2io_msix_ring_handle,
6989                                                           0,
6990                                                           sp->desc[i],
6991                                                           sp->s2io_entries[i].arg);
6992                                 } else if (sp->s2io_entries[i].type ==
6993                                            MSIX_ALARM_TYPE) {
6994                                         snprintf(sp->desc[i],
6995                                                 sizeof(sp->desc[i]),
6996                                                 "%s:MSI-X-%d-TX",
6997                                                 dev->name, i);
6998                                         err = request_irq(sp->entries[i].vector,
6999                                                           s2io_msix_fifo_handle,
7000                                                           0,
7001                                                           sp->desc[i],
7002                                                           sp->s2io_entries[i].arg);
7003
7004                                 }
7005                                 /* if either data or addr is zero print it. */
7006                                 if (!(sp->msix_info[i].addr &&
7007                                       sp->msix_info[i].data)) {
7008                                         DBG_PRINT(ERR_DBG,
7009                                                   "%s @Addr:0x%llx Data:0x%llx\n",
7010                                                   sp->desc[i],
7011                                                   (unsigned long long)
7012                                                   sp->msix_info[i].addr,
7013                                                   (unsigned long long)
7014                                                   ntohl(sp->msix_info[i].data));
7015                                 } else
7016                                         msix_rx_cnt++;
7017                                 if (err) {
7018                                         remove_msix_isr(sp);
7019
7020                                         DBG_PRINT(ERR_DBG,
7021                                                   "%s:MSI-X-%d registration "
7022                                                   "failed\n", dev->name, i);
7023
7024                                         DBG_PRINT(ERR_DBG,
7025                                                   "%s: Defaulting to INTA\n",
7026                                                   dev->name);
7027                                         sp->config.intr_type = INTA;
7028                                         break;
7029                                 }
7030                                 sp->s2io_entries[i].in_use =
7031                                         MSIX_REGISTERED_SUCCESS;
7032                         }
7033                 }
7034                 if (!err) {
7035                         pr_info("MSI-X-RX %d entries enabled\n", --msix_rx_cnt);
7036                         DBG_PRINT(INFO_DBG,
7037                                   "MSI-X-TX entries enabled through alarm vector\n");
7038                 }
7039         }
7040         if (sp->config.intr_type == INTA) {
7041                 err = request_irq(sp->pdev->irq, s2io_isr, IRQF_SHARED,
7042                                   sp->name, dev);
7043                 if (err) {
7044                         DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
7045                                   dev->name);
7046                         return -1;
7047                 }
7048         }
7049         return 0;
7050 }
7051
7052 static void s2io_rem_isr(struct s2io_nic *sp)
7053 {
7054         if (sp->config.intr_type == MSI_X)
7055                 remove_msix_isr(sp);
7056         else
7057                 remove_inta_isr(sp);
7058 }
7059
7060 static void do_s2io_card_down(struct s2io_nic *sp, int do_io)
7061 {
7062         int cnt = 0;
7063         struct XENA_dev_config __iomem *bar0 = sp->bar0;
7064         register u64 val64 = 0;
7065         struct config_param *config;
7066         config = &sp->config;
7067
7068         if (!is_s2io_card_up(sp))
7069                 return;
7070
7071         del_timer_sync(&sp->alarm_timer);
7072         /* If s2io_set_link task is executing, wait till it completes. */
7073         while (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(sp->state)))
7074                 msleep(50);
7075         clear_bit(__S2IO_STATE_CARD_UP, &sp->state);
7076
7077         /* Disable napi */
7078         if (sp->config.napi) {
7079                 int off = 0;
7080                 if (config->intr_type ==  MSI_X) {
7081                         for (; off < sp->config.rx_ring_num; off++)
7082                                 napi_disable(&sp->mac_control.rings[off].napi);
7083                 }
7084                 else
7085                         napi_disable(&sp->napi);
7086         }
7087
7088         /* disable Tx and Rx traffic on the NIC */
7089         if (do_io)
7090                 stop_nic(sp);
7091
7092         s2io_rem_isr(sp);
7093
7094         /* stop the tx queue, indicate link down */
7095         s2io_link(sp, LINK_DOWN);
7096
7097         /* Check if the device is Quiescent and then Reset the NIC */
7098         while (do_io) {
7099                 /* As per the HW requirement we need to replenish the
7100                  * receive buffer to avoid the ring bump. Since there is
7101                  * no intention of processing the Rx frame at this pointwe are
7102                  * just setting the ownership bit of rxd in Each Rx
7103                  * ring to HW and set the appropriate buffer size
7104                  * based on the ring mode
7105                  */
7106                 rxd_owner_bit_reset(sp);
7107
7108                 val64 = readq(&bar0->adapter_status);
7109                 if (verify_xena_quiescence(sp)) {
7110                         if (verify_pcc_quiescent(sp, sp->device_enabled_once))
7111                                 break;
7112                 }
7113
7114                 msleep(50);
7115                 cnt++;
7116                 if (cnt == 10) {
7117                         DBG_PRINT(ERR_DBG, "Device not Quiescent - "
7118                                   "adapter status reads 0x%llx\n",
7119                                   (unsigned long long)val64);
7120                         break;
7121                 }
7122         }
7123         if (do_io)
7124                 s2io_reset(sp);
7125
7126         /* Free all Tx buffers */
7127         free_tx_buffers(sp);
7128
7129         /* Free all Rx buffers */
7130         free_rx_buffers(sp);
7131
7132         clear_bit(__S2IO_STATE_LINK_TASK, &(sp->state));
7133 }
7134
7135 static void s2io_card_down(struct s2io_nic *sp)
7136 {
7137         do_s2io_card_down(sp, 1);
7138 }
7139
7140 static int s2io_card_up(struct s2io_nic *sp)
7141 {
7142         int i, ret = 0;
7143         struct config_param *config;
7144         struct mac_info *mac_control;
7145         struct net_device *dev = sp->dev;
7146         u16 interruptible;
7147
7148         /* Initialize the H/W I/O registers */
7149         ret = init_nic(sp);
7150         if (ret != 0) {
7151                 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
7152                           dev->name);
7153                 if (ret != -EIO)
7154                         s2io_reset(sp);
7155                 return ret;
7156         }
7157
7158         /*
7159          * Initializing the Rx buffers. For now we are considering only 1
7160          * Rx ring and initializing buffers into 30 Rx blocks
7161          */
7162         config = &sp->config;
7163         mac_control = &sp->mac_control;
7164
7165         for (i = 0; i < config->rx_ring_num; i++) {
7166                 struct ring_info *ring = &mac_control->rings[i];
7167
7168                 ring->mtu = dev->mtu;
7169                 ring->lro = !!(dev->features & NETIF_F_LRO);
7170                 ret = fill_rx_buffers(sp, ring, 1);
7171                 if (ret) {
7172                         DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
7173                                   dev->name);
7174                         s2io_reset(sp);
7175                         free_rx_buffers(sp);
7176                         return -ENOMEM;
7177                 }
7178                 DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
7179                           ring->rx_bufs_left);
7180         }
7181
7182         /* Initialise napi */
7183         if (config->napi) {
7184                 if (config->intr_type ==  MSI_X) {
7185                         for (i = 0; i < sp->config.rx_ring_num; i++)
7186                                 napi_enable(&sp->mac_control.rings[i].napi);
7187                 } else {
7188                         napi_enable(&sp->napi);
7189                 }
7190         }
7191
7192         /* Maintain the state prior to the open */
7193         if (sp->promisc_flg)
7194                 sp->promisc_flg = 0;
7195         if (sp->m_cast_flg) {
7196                 sp->m_cast_flg = 0;
7197                 sp->all_multi_pos = 0;
7198         }
7199
7200         /* Setting its receive mode */
7201         s2io_set_multicast(dev);
7202
7203         if (dev->features & NETIF_F_LRO) {
7204                 /* Initialize max aggregatable pkts per session based on MTU */
7205                 sp->lro_max_aggr_per_sess = ((1<<16) - 1) / dev->mtu;
7206                 /* Check if we can use (if specified) user provided value */
7207                 if (lro_max_pkts < sp->lro_max_aggr_per_sess)
7208                         sp->lro_max_aggr_per_sess = lro_max_pkts;
7209         }
7210
7211         /* Enable Rx Traffic and interrupts on the NIC */
7212         if (start_nic(sp)) {
7213                 DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
7214                 s2io_reset(sp);
7215                 free_rx_buffers(sp);
7216                 return -ENODEV;
7217         }
7218
7219         /* Add interrupt service routine */
7220         if (s2io_add_isr(sp) != 0) {
7221                 if (sp->config.intr_type == MSI_X)
7222                         s2io_rem_isr(sp);
7223                 s2io_reset(sp);
7224                 free_rx_buffers(sp);
7225                 return -ENODEV;
7226         }
7227
7228         S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2));
7229
7230         set_bit(__S2IO_STATE_CARD_UP, &sp->state);
7231
7232         /*  Enable select interrupts */
7233         en_dis_err_alarms(sp, ENA_ALL_INTRS, ENABLE_INTRS);
7234         if (sp->config.intr_type != INTA) {
7235                 interruptible = TX_TRAFFIC_INTR | TX_PIC_INTR;
7236                 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
7237         } else {
7238                 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
7239                 interruptible |= TX_PIC_INTR;
7240                 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
7241         }
7242
7243         return 0;
7244 }
7245
7246 /**
7247  * s2io_restart_nic - Resets the NIC.
7248  * @data : long pointer to the device private structure
7249  * Description:
7250  * This function is scheduled to be run by the s2io_tx_watchdog
7251  * function after 0.5 secs to reset the NIC. The idea is to reduce
7252  * the run time of the watch dog routine which is run holding a
7253  * spin lock.
7254  */
7255
7256 static void s2io_restart_nic(struct work_struct *work)
7257 {
7258         struct s2io_nic *sp = container_of(work, struct s2io_nic, rst_timer_task);
7259         struct net_device *dev = sp->dev;
7260
7261         rtnl_lock();
7262
7263         if (!netif_running(dev))
7264                 goto out_unlock;
7265
7266         s2io_card_down(sp);
7267         if (s2io_card_up(sp)) {
7268                 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n", dev->name);
7269         }
7270         s2io_wake_all_tx_queue(sp);
7271         DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n", dev->name);
7272 out_unlock:
7273         rtnl_unlock();
7274 }
7275
7276 /**
7277  *  s2io_tx_watchdog - Watchdog for transmit side.
7278  *  @dev : Pointer to net device structure
7279  *  Description:
7280  *  This function is triggered if the Tx Queue is stopped
7281  *  for a pre-defined amount of time when the Interface is still up.
7282  *  If the Interface is jammed in such a situation, the hardware is
7283  *  reset (by s2io_close) and restarted again (by s2io_open) to
7284  *  overcome any problem that might have been caused in the hardware.
7285  *  Return value:
7286  *  void
7287  */
7288
7289 static void s2io_tx_watchdog(struct net_device *dev)
7290 {
7291         struct s2io_nic *sp = netdev_priv(dev);
7292         struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
7293
7294         if (netif_carrier_ok(dev)) {
7295                 swstats->watchdog_timer_cnt++;
7296                 schedule_work(&sp->rst_timer_task);
7297                 swstats->soft_reset_cnt++;
7298         }
7299 }
7300
7301 /**
7302  *   rx_osm_handler - To perform some OS related operations on SKB.
7303  *   @sp: private member of the device structure,pointer to s2io_nic structure.
7304  *   @skb : the socket buffer pointer.
7305  *   @len : length of the packet
7306  *   @cksum : FCS checksum of the frame.
7307  *   @ring_no : the ring from which this RxD was extracted.
7308  *   Description:
7309  *   This function is called by the Rx interrupt serivce routine to perform
7310  *   some OS related operations on the SKB before passing it to the upper
7311  *   layers. It mainly checks if the checksum is OK, if so adds it to the
7312  *   SKBs cksum variable, increments the Rx packet count and passes the SKB
7313  *   to the upper layer. If the checksum is wrong, it increments the Rx
7314  *   packet error count, frees the SKB and returns error.
7315  *   Return value:
7316  *   SUCCESS on success and -1 on failure.
7317  */
7318 static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp)
7319 {
7320         struct s2io_nic *sp = ring_data->nic;
7321         struct net_device *dev = ring_data->dev;
7322         struct sk_buff *skb = (struct sk_buff *)
7323                 ((unsigned long)rxdp->Host_Control);
7324         int ring_no = ring_data->ring_no;
7325         u16 l3_csum, l4_csum;
7326         unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
7327         struct lro *uninitialized_var(lro);
7328         u8 err_mask;
7329         struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
7330
7331         skb->dev = dev;
7332
7333         if (err) {
7334                 /* Check for parity error */
7335                 if (err & 0x1)
7336                         swstats->parity_err_cnt++;
7337
7338                 err_mask = err >> 48;
7339                 switch (err_mask) {
7340                 case 1:
7341                         swstats->rx_parity_err_cnt++;
7342                         break;
7343
7344                 case 2:
7345                         swstats->rx_abort_cnt++;
7346                         break;
7347
7348                 case 3:
7349                         swstats->rx_parity_abort_cnt++;
7350                         break;
7351
7352                 case 4:
7353                         swstats->rx_rda_fail_cnt++;
7354                         break;
7355
7356                 case 5:
7357                         swstats->rx_unkn_prot_cnt++;
7358                         break;
7359
7360                 case 6:
7361                         swstats->rx_fcs_err_cnt++;
7362                         break;
7363
7364                 case 7:
7365                         swstats->rx_buf_size_err_cnt++;
7366                         break;
7367
7368                 case 8:
7369                         swstats->rx_rxd_corrupt_cnt++;
7370                         break;
7371
7372                 case 15:
7373                         swstats->rx_unkn_err_cnt++;
7374                         break;
7375                 }
7376                 /*
7377                  * Drop the packet if bad transfer code. Exception being
7378                  * 0x5, which could be due to unsupported IPv6 extension header.
7379                  * In this case, we let stack handle the packet.
7380                  * Note that in this case, since checksum will be incorrect,
7381                  * stack will validate the same.
7382                  */
7383                 if (err_mask != 0x5) {
7384                         DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%x\n",
7385                                   dev->name, err_mask);
7386                         dev->stats.rx_crc_errors++;
7387                         swstats->mem_freed
7388                                 += skb->truesize;
7389                         dev_kfree_skb(skb);
7390                         ring_data->rx_bufs_left -= 1;
7391                         rxdp->Host_Control = 0;
7392                         return 0;
7393                 }
7394         }
7395
7396         rxdp->Host_Control = 0;
7397         if (sp->rxd_mode == RXD_MODE_1) {
7398                 int len = RXD_GET_BUFFER0_SIZE_1(rxdp->Control_2);
7399
7400                 skb_put(skb, len);
7401         } else if (sp->rxd_mode == RXD_MODE_3B) {
7402                 int get_block = ring_data->rx_curr_get_info.block_index;
7403                 int get_off = ring_data->rx_curr_get_info.offset;
7404                 int buf0_len = RXD_GET_BUFFER0_SIZE_3(rxdp->Control_2);
7405                 int buf2_len = RXD_GET_BUFFER2_SIZE_3(rxdp->Control_2);
7406                 unsigned char *buff = skb_push(skb, buf0_len);
7407
7408                 struct buffAdd *ba = &ring_data->ba[get_block][get_off];
7409                 memcpy(buff, ba->ba_0, buf0_len);
7410                 skb_put(skb, buf2_len);
7411         }
7412
7413         if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) &&
7414             ((!ring_data->lro) ||
7415              (!(rxdp->Control_1 & RXD_FRAME_IP_FRAG))) &&
7416             (dev->features & NETIF_F_RXCSUM)) {
7417                 l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
7418                 l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
7419                 if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
7420                         /*
7421                          * NIC verifies if the Checksum of the received
7422                          * frame is Ok or not and accordingly returns
7423                          * a flag in the RxD.
7424                          */
7425                         skb->ip_summed = CHECKSUM_UNNECESSARY;
7426                         if (ring_data->lro) {
7427                                 u32 tcp_len = 0;
7428                                 u8 *tcp;
7429                                 int ret = 0;
7430
7431                                 ret = s2io_club_tcp_session(ring_data,
7432                                                             skb->data, &tcp,
7433                                                             &tcp_len, &lro,
7434                                                             rxdp, sp);
7435                                 switch (ret) {
7436                                 case 3: /* Begin anew */
7437                                         lro->parent = skb;
7438                                         goto aggregate;
7439                                 case 1: /* Aggregate */
7440                                         lro_append_pkt(sp, lro, skb, tcp_len);
7441                                         goto aggregate;
7442                                 case 4: /* Flush session */
7443                                         lro_append_pkt(sp, lro, skb, tcp_len);
7444                                         queue_rx_frame(lro->parent,
7445                                                        lro->vlan_tag);
7446                                         clear_lro_session(lro);
7447                                         swstats->flush_max_pkts++;
7448                                         goto aggregate;
7449                                 case 2: /* Flush both */
7450                                         lro->parent->data_len = lro->frags_len;
7451                                         swstats->sending_both++;
7452                                         queue_rx_frame(lro->parent,
7453                                                        lro->vlan_tag);
7454                                         clear_lro_session(lro);
7455                                         goto send_up;
7456                                 case 0: /* sessions exceeded */
7457                                 case -1: /* non-TCP or not L2 aggregatable */
7458                                 case 5: /*
7459                                          * First pkt in session not
7460                                          * L3/L4 aggregatable
7461                                          */
7462                                         break;
7463                                 default:
7464                                         DBG_PRINT(ERR_DBG,
7465                                                   "%s: Samadhana!!\n",
7466                                                   __func__);
7467                                         BUG();
7468                                 }
7469                         }
7470                 } else {
7471                         /*
7472                          * Packet with erroneous checksum, let the
7473                          * upper layers deal with it.
7474                          */
7475                         skb_checksum_none_assert(skb);
7476                 }
7477         } else
7478                 skb_checksum_none_assert(skb);
7479
7480         swstats->mem_freed += skb->truesize;
7481 send_up:
7482         skb_record_rx_queue(skb, ring_no);
7483         queue_rx_frame(skb, RXD_GET_VLAN_TAG(rxdp->Control_2));
7484 aggregate:
7485         sp->mac_control.rings[ring_no].rx_bufs_left -= 1;
7486         return SUCCESS;
7487 }
7488
7489 /**
7490  *  s2io_link - stops/starts the Tx queue.
7491  *  @sp : private member of the device structure, which is a pointer to the
7492  *  s2io_nic structure.
7493  *  @link : inidicates whether link is UP/DOWN.
7494  *  Description:
7495  *  This function stops/starts the Tx queue depending on whether the link
7496  *  status of the NIC is is down or up. This is called by the Alarm
7497  *  interrupt handler whenever a link change interrupt comes up.
7498  *  Return value:
7499  *  void.
7500  */
7501
7502 static void s2io_link(struct s2io_nic *sp, int link)
7503 {
7504         struct net_device *dev = sp->dev;
7505         struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
7506
7507         if (link != sp->last_link_state) {
7508                 init_tti(sp, link);
7509                 if (link == LINK_DOWN) {
7510                         DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name);
7511                         s2io_stop_all_tx_queue(sp);
7512                         netif_carrier_off(dev);
7513                         if (swstats->link_up_cnt)
7514                                 swstats->link_up_time =
7515                                         jiffies - sp->start_time;
7516                         swstats->link_down_cnt++;
7517                 } else {
7518                         DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name);
7519                         if (swstats->link_down_cnt)
7520                                 swstats->link_down_time =
7521                                         jiffies - sp->start_time;
7522                         swstats->link_up_cnt++;
7523                         netif_carrier_on(dev);
7524                         s2io_wake_all_tx_queue(sp);
7525                 }
7526         }
7527         sp->last_link_state = link;
7528         sp->start_time = jiffies;
7529 }
7530
7531 /**
7532  *  s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
7533  *  @sp : private member of the device structure, which is a pointer to the
7534  *  s2io_nic structure.
7535  *  Description:
7536  *  This function initializes a few of the PCI and PCI-X configuration registers
7537  *  with recommended values.
7538  *  Return value:
7539  *  void
7540  */
7541
7542 static void s2io_init_pci(struct s2io_nic *sp)
7543 {
7544         u16 pci_cmd = 0, pcix_cmd = 0;
7545
7546         /* Enable Data Parity Error Recovery in PCI-X command register. */
7547         pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7548                              &(pcix_cmd));
7549         pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7550                               (pcix_cmd | 1));
7551         pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7552                              &(pcix_cmd));
7553
7554         /* Set the PErr Response bit in PCI command register. */
7555         pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
7556         pci_write_config_word(sp->pdev, PCI_COMMAND,
7557                               (pci_cmd | PCI_COMMAND_PARITY));
7558         pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
7559 }
7560
7561 static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type,
7562                             u8 *dev_multiq)
7563 {
7564         int i;
7565
7566         if ((tx_fifo_num > MAX_TX_FIFOS) || (tx_fifo_num < 1)) {
7567                 DBG_PRINT(ERR_DBG, "Requested number of tx fifos "
7568                           "(%d) not supported\n", tx_fifo_num);
7569
7570                 if (tx_fifo_num < 1)
7571                         tx_fifo_num = 1;
7572                 else
7573                         tx_fifo_num = MAX_TX_FIFOS;
7574
7575                 DBG_PRINT(ERR_DBG, "Default to %d tx fifos\n", tx_fifo_num);
7576         }
7577
7578         if (multiq)
7579                 *dev_multiq = multiq;
7580
7581         if (tx_steering_type && (1 == tx_fifo_num)) {
7582                 if (tx_steering_type != TX_DEFAULT_STEERING)
7583                         DBG_PRINT(ERR_DBG,
7584                                   "Tx steering is not supported with "
7585                                   "one fifo. Disabling Tx steering.\n");
7586                 tx_steering_type = NO_STEERING;
7587         }
7588
7589         if ((tx_steering_type < NO_STEERING) ||
7590             (tx_steering_type > TX_DEFAULT_STEERING)) {
7591                 DBG_PRINT(ERR_DBG,
7592                           "Requested transmit steering not supported\n");
7593                 DBG_PRINT(ERR_DBG, "Disabling transmit steering\n");
7594                 tx_steering_type = NO_STEERING;
7595         }
7596
7597         if (rx_ring_num > MAX_RX_RINGS) {
7598                 DBG_PRINT(ERR_DBG,
7599                           "Requested number of rx rings not supported\n");
7600                 DBG_PRINT(ERR_DBG, "Default to %d rx rings\n",
7601                           MAX_RX_RINGS);
7602                 rx_ring_num = MAX_RX_RINGS;
7603         }
7604
7605         if ((*dev_intr_type != INTA) && (*dev_intr_type != MSI_X)) {
7606                 DBG_PRINT(ERR_DBG, "Wrong intr_type requested. "
7607                           "Defaulting to INTA\n");
7608                 *dev_intr_type = INTA;
7609         }
7610
7611         if ((*dev_intr_type == MSI_X) &&
7612             ((pdev->device != PCI_DEVICE_ID_HERC_WIN) &&
7613              (pdev->device != PCI_DEVICE_ID_HERC_UNI))) {
7614                 DBG_PRINT(ERR_DBG, "Xframe I does not support MSI_X. "
7615                           "Defaulting to INTA\n");
7616                 *dev_intr_type = INTA;
7617         }
7618
7619         if ((rx_ring_mode != 1) && (rx_ring_mode != 2)) {
7620                 DBG_PRINT(ERR_DBG, "Requested ring mode not supported\n");
7621                 DBG_PRINT(ERR_DBG, "Defaulting to 1-buffer mode\n");
7622                 rx_ring_mode = 1;
7623         }
7624
7625         for (i = 0; i < MAX_RX_RINGS; i++)
7626                 if (rx_ring_sz[i] > MAX_RX_BLOCKS_PER_RING) {
7627                         DBG_PRINT(ERR_DBG, "Requested rx ring size not "
7628                                   "supported\nDefaulting to %d\n",
7629                                   MAX_RX_BLOCKS_PER_RING);
7630                         rx_ring_sz[i] = MAX_RX_BLOCKS_PER_RING;
7631                 }
7632
7633         return SUCCESS;
7634 }
7635
7636 /**
7637  * rts_ds_steer - Receive traffic steering based on IPv4 or IPv6 TOS
7638  * or Traffic class respectively.
7639  * @nic: device private variable
7640  * Description: The function configures the receive steering to
7641  * desired receive ring.
7642  * Return Value:  SUCCESS on success and
7643  * '-1' on failure (endian settings incorrect).
7644  */
7645 static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring)
7646 {
7647         struct XENA_dev_config __iomem *bar0 = nic->bar0;
7648         register u64 val64 = 0;
7649
7650         if (ds_codepoint > 63)
7651                 return FAILURE;
7652
7653         val64 = RTS_DS_MEM_DATA(ring);
7654         writeq(val64, &bar0->rts_ds_mem_data);
7655
7656         val64 = RTS_DS_MEM_CTRL_WE |
7657                 RTS_DS_MEM_CTRL_STROBE_NEW_CMD |
7658                 RTS_DS_MEM_CTRL_OFFSET(ds_codepoint);
7659
7660         writeq(val64, &bar0->rts_ds_mem_ctrl);
7661
7662         return wait_for_cmd_complete(&bar0->rts_ds_mem_ctrl,
7663                                      RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED,
7664                                      S2IO_BIT_RESET);
7665 }
7666
7667 static const struct net_device_ops s2io_netdev_ops = {
7668         .ndo_open               = s2io_open,
7669         .ndo_stop               = s2io_close,
7670         .ndo_get_stats          = s2io_get_stats,
7671         .ndo_start_xmit         = s2io_xmit,
7672         .ndo_validate_addr      = eth_validate_addr,
7673         .ndo_set_rx_mode        = s2io_set_multicast,
7674         .ndo_do_ioctl           = s2io_ioctl,
7675         .ndo_set_mac_address    = s2io_set_mac_addr,
7676         .ndo_change_mtu         = s2io_change_mtu,
7677         .ndo_set_features       = s2io_set_features,
7678         .ndo_tx_timeout         = s2io_tx_watchdog,
7679 #ifdef CONFIG_NET_POLL_CONTROLLER
7680         .ndo_poll_controller    = s2io_netpoll,
7681 #endif
7682 };
7683
7684 /**
7685  *  s2io_init_nic - Initialization of the adapter .
7686  *  @pdev : structure containing the PCI related information of the device.
7687  *  @pre: List of PCI devices supported by the driver listed in s2io_tbl.
7688  *  Description:
7689  *  The function initializes an adapter identified by the pci_dec structure.
7690  *  All OS related initialization including memory and device structure and
7691  *  initlaization of the device private variable is done. Also the swapper
7692  *  control register is initialized to enable read and write into the I/O
7693  *  registers of the device.
7694  *  Return value:
7695  *  returns 0 on success and negative on failure.
7696  */
7697
7698 static int
7699 s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
7700 {
7701         struct s2io_nic *sp;
7702         struct net_device *dev;
7703         int i, j, ret;
7704         int dma_flag = false;
7705         u32 mac_up, mac_down;
7706         u64 val64 = 0, tmp64 = 0;
7707         struct XENA_dev_config __iomem *bar0 = NULL;
7708         u16 subid;
7709         struct config_param *config;
7710         struct mac_info *mac_control;
7711         int mode;
7712         u8 dev_intr_type = intr_type;
7713         u8 dev_multiq = 0;
7714
7715         ret = s2io_verify_parm(pdev, &dev_intr_type, &dev_multiq);
7716         if (ret)
7717                 return ret;
7718
7719         ret = pci_enable_device(pdev);
7720         if (ret) {
7721                 DBG_PRINT(ERR_DBG,
7722                           "%s: pci_enable_device failed\n", __func__);
7723                 return ret;
7724         }
7725
7726         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
7727                 DBG_PRINT(INIT_DBG, "%s: Using 64bit DMA\n", __func__);
7728                 dma_flag = true;
7729                 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
7730                         DBG_PRINT(ERR_DBG,
7731                                   "Unable to obtain 64bit DMA "
7732                                   "for consistent allocations\n");
7733                         pci_disable_device(pdev);
7734                         return -ENOMEM;
7735                 }
7736         } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
7737                 DBG_PRINT(INIT_DBG, "%s: Using 32bit DMA\n", __func__);
7738         } else {
7739                 pci_disable_device(pdev);
7740                 return -ENOMEM;
7741         }
7742         ret = pci_request_regions(pdev, s2io_driver_name);
7743         if (ret) {
7744                 DBG_PRINT(ERR_DBG, "%s: Request Regions failed - %x\n",
7745                           __func__, ret);
7746                 pci_disable_device(pdev);
7747                 return -ENODEV;
7748         }
7749         if (dev_multiq)
7750                 dev = alloc_etherdev_mq(sizeof(struct s2io_nic), tx_fifo_num);
7751         else
7752                 dev = alloc_etherdev(sizeof(struct s2io_nic));
7753         if (dev == NULL) {
7754                 pci_disable_device(pdev);
7755                 pci_release_regions(pdev);
7756                 return -ENODEV;
7757         }
7758
7759         pci_set_master(pdev);
7760         pci_set_drvdata(pdev, dev);
7761         SET_NETDEV_DEV(dev, &pdev->dev);
7762
7763         /*  Private member variable initialized to s2io NIC structure */
7764         sp = netdev_priv(dev);
7765         sp->dev = dev;
7766         sp->pdev = pdev;
7767         sp->high_dma_flag = dma_flag;
7768         sp->device_enabled_once = false;
7769         if (rx_ring_mode == 1)
7770                 sp->rxd_mode = RXD_MODE_1;
7771         if (rx_ring_mode == 2)
7772                 sp->rxd_mode = RXD_MODE_3B;
7773
7774         sp->config.intr_type = dev_intr_type;
7775
7776         if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) ||
7777             (pdev->device == PCI_DEVICE_ID_HERC_UNI))
7778                 sp->device_type = XFRAME_II_DEVICE;
7779         else
7780                 sp->device_type = XFRAME_I_DEVICE;
7781
7782
7783         /* Initialize some PCI/PCI-X fields of the NIC. */
7784         s2io_init_pci(sp);
7785
7786         /*
7787          * Setting the device configuration parameters.
7788          * Most of these parameters can be specified by the user during
7789          * module insertion as they are module loadable parameters. If
7790          * these parameters are not not specified during load time, they
7791          * are initialized with default values.
7792          */
7793         config = &sp->config;
7794         mac_control = &sp->mac_control;
7795
7796         config->napi = napi;
7797         config->tx_steering_type = tx_steering_type;
7798
7799         /* Tx side parameters. */
7800         if (config->tx_steering_type == TX_PRIORITY_STEERING)
7801                 config->tx_fifo_num = MAX_TX_FIFOS;
7802         else
7803                 config->tx_fifo_num = tx_fifo_num;
7804
7805         /* Initialize the fifos used for tx steering */
7806         if (config->tx_fifo_num < 5) {
7807                 if (config->tx_fifo_num  == 1)
7808                         sp->total_tcp_fifos = 1;
7809                 else
7810                         sp->total_tcp_fifos = config->tx_fifo_num - 1;
7811                 sp->udp_fifo_idx = config->tx_fifo_num - 1;
7812                 sp->total_udp_fifos = 1;
7813                 sp->other_fifo_idx = sp->total_tcp_fifos - 1;
7814         } else {
7815                 sp->total_tcp_fifos = (tx_fifo_num - FIFO_UDP_MAX_NUM -
7816                                        FIFO_OTHER_MAX_NUM);
7817                 sp->udp_fifo_idx = sp->total_tcp_fifos;
7818                 sp->total_udp_fifos = FIFO_UDP_MAX_NUM;
7819                 sp->other_fifo_idx = sp->udp_fifo_idx + FIFO_UDP_MAX_NUM;
7820         }
7821
7822         config->multiq = dev_multiq;
7823         for (i = 0; i < config->tx_fifo_num; i++) {
7824                 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
7825
7826                 tx_cfg->fifo_len = tx_fifo_len[i];
7827                 tx_cfg->fifo_priority = i;
7828         }
7829
7830         /* mapping the QoS priority to the configured fifos */
7831         for (i = 0; i < MAX_TX_FIFOS; i++)
7832                 config->fifo_mapping[i] = fifo_map[config->tx_fifo_num - 1][i];
7833
7834         /* map the hashing selector table to the configured fifos */
7835         for (i = 0; i < config->tx_fifo_num; i++)
7836                 sp->fifo_selector[i] = fifo_selector[i];
7837
7838
7839         config->tx_intr_type = TXD_INT_TYPE_UTILZ;
7840         for (i = 0; i < config->tx_fifo_num; i++) {
7841                 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
7842
7843                 tx_cfg->f_no_snoop = (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
7844                 if (tx_cfg->fifo_len < 65) {
7845                         config->tx_intr_type = TXD_INT_TYPE_PER_LIST;
7846                         break;
7847                 }
7848         }
7849         /* + 2 because one Txd for skb->data and one Txd for UFO */
7850         config->max_txds = MAX_SKB_FRAGS + 2;
7851
7852         /* Rx side parameters. */
7853         config->rx_ring_num = rx_ring_num;
7854         for (i = 0; i < config->rx_ring_num; i++) {
7855                 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
7856                 struct ring_info *ring = &mac_control->rings[i];
7857
7858                 rx_cfg->num_rxd = rx_ring_sz[i] * (rxd_count[sp->rxd_mode] + 1);
7859                 rx_cfg->ring_priority = i;
7860                 ring->rx_bufs_left = 0;
7861                 ring->rxd_mode = sp->rxd_mode;
7862                 ring->rxd_count = rxd_count[sp->rxd_mode];
7863                 ring->pdev = sp->pdev;
7864                 ring->dev = sp->dev;
7865         }
7866
7867         for (i = 0; i < rx_ring_num; i++) {
7868                 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
7869
7870                 rx_cfg->ring_org = RING_ORG_BUFF1;
7871                 rx_cfg->f_no_snoop = (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
7872         }
7873
7874         /*  Setting Mac Control parameters */
7875         mac_control->rmac_pause_time = rmac_pause_time;
7876         mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3;
7877         mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7;
7878
7879
7880         /*  initialize the shared memory used by the NIC and the host */
7881         if (init_shared_mem(sp)) {
7882                 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n", dev->name);
7883                 ret = -ENOMEM;
7884                 goto mem_alloc_failed;
7885         }
7886
7887         sp->bar0 = pci_ioremap_bar(pdev, 0);
7888         if (!sp->bar0) {
7889                 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem1\n",
7890                           dev->name);
7891                 ret = -ENOMEM;
7892                 goto bar0_remap_failed;
7893         }
7894
7895         sp->bar1 = pci_ioremap_bar(pdev, 2);
7896         if (!sp->bar1) {
7897                 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem2\n",
7898                           dev->name);
7899                 ret = -ENOMEM;
7900                 goto bar1_remap_failed;
7901         }
7902
7903         /* Initializing the BAR1 address as the start of the FIFO pointer. */
7904         for (j = 0; j < MAX_TX_FIFOS; j++) {
7905                 mac_control->tx_FIFO_start[j] = sp->bar1 + (j * 0x00020000);
7906         }
7907
7908         /*  Driver entry points */
7909         dev->netdev_ops = &s2io_netdev_ops;
7910         dev->ethtool_ops = &netdev_ethtool_ops;
7911         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM |
7912                 NETIF_F_TSO | NETIF_F_TSO6 |
7913                 NETIF_F_RXCSUM | NETIF_F_LRO;
7914         dev->features |= dev->hw_features |
7915                 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
7916         if (sp->device_type & XFRAME_II_DEVICE) {
7917                 dev->hw_features |= NETIF_F_UFO;
7918                 if (ufo)
7919                         dev->features |= NETIF_F_UFO;
7920         }
7921         if (sp->high_dma_flag == true)
7922                 dev->features |= NETIF_F_HIGHDMA;
7923         dev->watchdog_timeo = WATCH_DOG_TIMEOUT;
7924         INIT_WORK(&sp->rst_timer_task, s2io_restart_nic);
7925         INIT_WORK(&sp->set_link_task, s2io_set_link);
7926
7927         pci_save_state(sp->pdev);
7928
7929         /* Setting swapper control on the NIC, for proper reset operation */
7930         if (s2io_set_swapper(sp)) {
7931                 DBG_PRINT(ERR_DBG, "%s: swapper settings are wrong\n",
7932                           dev->name);
7933                 ret = -EAGAIN;
7934                 goto set_swap_failed;
7935         }
7936
7937         /* Verify if the Herc works on the slot its placed into */
7938         if (sp->device_type & XFRAME_II_DEVICE) {
7939                 mode = s2io_verify_pci_mode(sp);
7940                 if (mode < 0) {
7941                         DBG_PRINT(ERR_DBG, "%s: Unsupported PCI bus mode\n",
7942                                   __func__);
7943                         ret = -EBADSLT;
7944                         goto set_swap_failed;
7945                 }
7946         }
7947
7948         if (sp->config.intr_type == MSI_X) {
7949                 sp->num_entries = config->rx_ring_num + 1;
7950                 ret = s2io_enable_msi_x(sp);
7951
7952                 if (!ret) {
7953                         ret = s2io_test_msi(sp);
7954                         /* rollback MSI-X, will re-enable during add_isr() */
7955                         remove_msix_isr(sp);
7956                 }
7957                 if (ret) {
7958
7959                         DBG_PRINT(ERR_DBG,
7960                                   "MSI-X requested but failed to enable\n");
7961                         sp->config.intr_type = INTA;
7962                 }
7963         }
7964
7965         if (config->intr_type ==  MSI_X) {
7966                 for (i = 0; i < config->rx_ring_num ; i++) {
7967                         struct ring_info *ring = &mac_control->rings[i];
7968
7969                         netif_napi_add(dev, &ring->napi, s2io_poll_msix, 64);
7970                 }
7971         } else {
7972                 netif_napi_add(dev, &sp->napi, s2io_poll_inta, 64);
7973         }
7974
7975         /* Not needed for Herc */
7976         if (sp->device_type & XFRAME_I_DEVICE) {
7977                 /*
7978                  * Fix for all "FFs" MAC address problems observed on
7979                  * Alpha platforms
7980                  */
7981                 fix_mac_address(sp);
7982                 s2io_reset(sp);
7983         }
7984
7985         /*
7986          * MAC address initialization.
7987          * For now only one mac address will be read and used.
7988          */
7989         bar0 = sp->bar0;
7990         val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
7991                 RMAC_ADDR_CMD_MEM_OFFSET(0 + S2IO_MAC_ADDR_START_OFFSET);
7992         writeq(val64, &bar0->rmac_addr_cmd_mem);
7993         wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
7994                               RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
7995                               S2IO_BIT_RESET);
7996         tmp64 = readq(&bar0->rmac_addr_data0_mem);
7997         mac_down = (u32)tmp64;
7998         mac_up = (u32) (tmp64 >> 32);
7999
8000         sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_up);
8001         sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_up >> 8);
8002         sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_up >> 16);
8003         sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_up >> 24);
8004         sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16);
8005         sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24);
8006
8007         /*  Set the factory defined MAC address initially   */
8008         dev->addr_len = ETH_ALEN;
8009         memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN);
8010
8011         /* initialize number of multicast & unicast MAC entries variables */
8012         if (sp->device_type == XFRAME_I_DEVICE) {
8013                 config->max_mc_addr = S2IO_XENA_MAX_MC_ADDRESSES;
8014                 config->max_mac_addr = S2IO_XENA_MAX_MAC_ADDRESSES;
8015                 config->mc_start_offset = S2IO_XENA_MC_ADDR_START_OFFSET;
8016         } else if (sp->device_type == XFRAME_II_DEVICE) {
8017                 config->max_mc_addr = S2IO_HERC_MAX_MC_ADDRESSES;
8018                 config->max_mac_addr = S2IO_HERC_MAX_MAC_ADDRESSES;
8019                 config->mc_start_offset = S2IO_HERC_MC_ADDR_START_OFFSET;
8020         }
8021
8022         /* store mac addresses from CAM to s2io_nic structure */
8023         do_s2io_store_unicast_mc(sp);
8024
8025         /* Configure MSIX vector for number of rings configured plus one */
8026         if ((sp->device_type == XFRAME_II_DEVICE) &&
8027             (config->intr_type == MSI_X))
8028                 sp->num_entries = config->rx_ring_num + 1;
8029
8030         /* Store the values of the MSIX table in the s2io_nic structure */
8031         store_xmsi_data(sp);
8032         /* reset Nic and bring it to known state */
8033         s2io_reset(sp);
8034
8035         /*
8036          * Initialize link state flags
8037          * and the card state parameter
8038          */
8039         sp->state = 0;
8040
8041         /* Initialize spinlocks */
8042         for (i = 0; i < sp->config.tx_fifo_num; i++) {
8043                 struct fifo_info *fifo = &mac_control->fifos[i];
8044
8045                 spin_lock_init(&fifo->tx_lock);
8046         }
8047
8048         /*
8049          * SXE-002: Configure link and activity LED to init state
8050          * on driver load.
8051          */
8052         subid = sp->pdev->subsystem_device;
8053         if ((subid & 0xFF) >= 0x07) {
8054                 val64 = readq(&bar0->gpio_control);
8055                 val64 |= 0x0000800000000000ULL;
8056                 writeq(val64, &bar0->gpio_control);
8057                 val64 = 0x0411040400000000ULL;
8058                 writeq(val64, (void __iomem *)bar0 + 0x2700);
8059                 val64 = readq(&bar0->gpio_control);
8060         }
8061
8062         sp->rx_csum = 1;        /* Rx chksum verify enabled by default */
8063
8064         if (register_netdev(dev)) {
8065                 DBG_PRINT(ERR_DBG, "Device registration failed\n");
8066                 ret = -ENODEV;
8067                 goto register_failed;
8068         }
8069         s2io_vpd_read(sp);
8070         DBG_PRINT(ERR_DBG, "Copyright(c) 2002-2010 Exar Corp.\n");
8071         DBG_PRINT(ERR_DBG, "%s: Neterion %s (rev %d)\n", dev->name,
8072                   sp->product_name, pdev->revision);
8073         DBG_PRINT(ERR_DBG, "%s: Driver version %s\n", dev->name,
8074                   s2io_driver_version);
8075         DBG_PRINT(ERR_DBG, "%s: MAC Address: %pM\n", dev->name, dev->dev_addr);
8076         DBG_PRINT(ERR_DBG, "Serial number: %s\n", sp->serial_num);
8077         if (sp->device_type & XFRAME_II_DEVICE) {
8078                 mode = s2io_print_pci_mode(sp);
8079                 if (mode < 0) {
8080                         ret = -EBADSLT;
8081                         unregister_netdev(dev);
8082                         goto set_swap_failed;
8083                 }
8084         }
8085         switch (sp->rxd_mode) {
8086         case RXD_MODE_1:
8087                 DBG_PRINT(ERR_DBG, "%s: 1-Buffer receive mode enabled\n",
8088                           dev->name);
8089                 break;
8090         case RXD_MODE_3B:
8091                 DBG_PRINT(ERR_DBG, "%s: 2-Buffer receive mode enabled\n",
8092                           dev->name);
8093                 break;
8094         }
8095
8096         switch (sp->config.napi) {
8097         case 0:
8098                 DBG_PRINT(ERR_DBG, "%s: NAPI disabled\n", dev->name);
8099                 break;
8100         case 1:
8101                 DBG_PRINT(ERR_DBG, "%s: NAPI enabled\n", dev->name);
8102                 break;
8103         }
8104
8105         DBG_PRINT(ERR_DBG, "%s: Using %d Tx fifo(s)\n", dev->name,
8106                   sp->config.tx_fifo_num);
8107
8108         DBG_PRINT(ERR_DBG, "%s: Using %d Rx ring(s)\n", dev->name,
8109                   sp->config.rx_ring_num);
8110
8111         switch (sp->config.intr_type) {
8112         case INTA:
8113                 DBG_PRINT(ERR_DBG, "%s: Interrupt type INTA\n", dev->name);
8114                 break;
8115         case MSI_X:
8116                 DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI-X\n", dev->name);
8117                 break;
8118         }
8119         if (sp->config.multiq) {
8120                 for (i = 0; i < sp->config.tx_fifo_num; i++) {
8121                         struct fifo_info *fifo = &mac_control->fifos[i];
8122
8123                         fifo->multiq = config->multiq;
8124                 }
8125                 DBG_PRINT(ERR_DBG, "%s: Multiqueue support enabled\n",
8126                           dev->name);
8127         } else
8128                 DBG_PRINT(ERR_DBG, "%s: Multiqueue support disabled\n",
8129                           dev->name);
8130
8131         switch (sp->config.tx_steering_type) {
8132         case NO_STEERING:
8133                 DBG_PRINT(ERR_DBG, "%s: No steering enabled for transmit\n",
8134                           dev->name);
8135                 break;
8136         case TX_PRIORITY_STEERING:
8137                 DBG_PRINT(ERR_DBG,
8138                           "%s: Priority steering enabled for transmit\n",
8139                           dev->name);
8140                 break;
8141         case TX_DEFAULT_STEERING:
8142                 DBG_PRINT(ERR_DBG,
8143                           "%s: Default steering enabled for transmit\n",
8144                           dev->name);
8145         }
8146
8147         DBG_PRINT(ERR_DBG, "%s: Large receive offload enabled\n",
8148                   dev->name);
8149         if (ufo)
8150                 DBG_PRINT(ERR_DBG,
8151                           "%s: UDP Fragmentation Offload(UFO) enabled\n",
8152                           dev->name);
8153         /* Initialize device name */
8154         snprintf(sp->name, sizeof(sp->name), "%s Neterion %s", dev->name,
8155                  sp->product_name);
8156
8157         if (vlan_tag_strip)
8158                 sp->vlan_strip_flag = 1;
8159         else
8160                 sp->vlan_strip_flag = 0;
8161
8162         /*
8163          * Make Link state as off at this point, when the Link change
8164          * interrupt comes the state will be automatically changed to
8165          * the right state.
8166          */
8167         netif_carrier_off(dev);
8168
8169         return 0;
8170
8171 register_failed:
8172 set_swap_failed:
8173         iounmap(sp->bar1);
8174 bar1_remap_failed:
8175         iounmap(sp->bar0);
8176 bar0_remap_failed:
8177 mem_alloc_failed:
8178         free_shared_mem(sp);
8179         pci_disable_device(pdev);
8180         pci_release_regions(pdev);
8181         free_netdev(dev);
8182
8183         return ret;
8184 }
8185
8186 /**
8187  * s2io_rem_nic - Free the PCI device
8188  * @pdev: structure containing the PCI related information of the device.
8189  * Description: This function is called by the Pci subsystem to release a
8190  * PCI device and free up all resource held up by the device. This could
8191  * be in response to a Hot plug event or when the driver is to be removed
8192  * from memory.
8193  */
8194
8195 static void s2io_rem_nic(struct pci_dev *pdev)
8196 {
8197         struct net_device *dev = pci_get_drvdata(pdev);
8198         struct s2io_nic *sp;
8199
8200         if (dev == NULL) {
8201                 DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n");
8202                 return;
8203         }
8204
8205         sp = netdev_priv(dev);
8206
8207         cancel_work_sync(&sp->rst_timer_task);
8208         cancel_work_sync(&sp->set_link_task);
8209
8210         unregister_netdev(dev);
8211
8212         free_shared_mem(sp);
8213         iounmap(sp->bar0);
8214         iounmap(sp->bar1);
8215         pci_release_regions(pdev);
8216         free_netdev(dev);
8217         pci_disable_device(pdev);
8218 }
8219
8220 module_pci_driver(s2io_driver);
8221
8222 static int check_L2_lro_capable(u8 *buffer, struct iphdr **ip,
8223                                 struct tcphdr **tcp, struct RxD_t *rxdp,
8224                                 struct s2io_nic *sp)
8225 {
8226         int ip_off;
8227         u8 l2_type = (u8)((rxdp->Control_1 >> 37) & 0x7), ip_len;
8228
8229         if (!(rxdp->Control_1 & RXD_FRAME_PROTO_TCP)) {
8230                 DBG_PRINT(INIT_DBG,
8231                           "%s: Non-TCP frames not supported for LRO\n",
8232                           __func__);
8233                 return -1;
8234         }
8235
8236         /* Checking for DIX type or DIX type with VLAN */
8237         if ((l2_type == 0) || (l2_type == 4)) {
8238                 ip_off = HEADER_ETHERNET_II_802_3_SIZE;
8239                 /*
8240                  * If vlan stripping is disabled and the frame is VLAN tagged,
8241                  * shift the offset by the VLAN header size bytes.
8242                  */
8243                 if ((!sp->vlan_strip_flag) &&
8244                     (rxdp->Control_1 & RXD_FRAME_VLAN_TAG))
8245                         ip_off += HEADER_VLAN_SIZE;
8246         } else {
8247                 /* LLC, SNAP etc are considered non-mergeable */
8248                 return -1;
8249         }
8250
8251         *ip = (struct iphdr *)(buffer + ip_off);
8252         ip_len = (u8)((*ip)->ihl);
8253         ip_len <<= 2;
8254         *tcp = (struct tcphdr *)((unsigned long)*ip + ip_len);
8255
8256         return 0;
8257 }
8258
8259 static int check_for_socket_match(struct lro *lro, struct iphdr *ip,
8260                                   struct tcphdr *tcp)
8261 {
8262         DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8263         if ((lro->iph->saddr != ip->saddr) ||
8264             (lro->iph->daddr != ip->daddr) ||
8265             (lro->tcph->source != tcp->source) ||
8266             (lro->tcph->dest != tcp->dest))
8267                 return -1;
8268         return 0;
8269 }
8270
8271 static inline int get_l4_pyld_length(struct iphdr *ip, struct tcphdr *tcp)
8272 {
8273         return ntohs(ip->tot_len) - (ip->ihl << 2) - (tcp->doff << 2);
8274 }
8275
8276 static void initiate_new_session(struct lro *lro, u8 *l2h,
8277                                  struct iphdr *ip, struct tcphdr *tcp,
8278                                  u32 tcp_pyld_len, u16 vlan_tag)
8279 {
8280         DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8281         lro->l2h = l2h;
8282         lro->iph = ip;
8283         lro->tcph = tcp;
8284         lro->tcp_next_seq = tcp_pyld_len + ntohl(tcp->seq);
8285         lro->tcp_ack = tcp->ack_seq;
8286         lro->sg_num = 1;
8287         lro->total_len = ntohs(ip->tot_len);
8288         lro->frags_len = 0;
8289         lro->vlan_tag = vlan_tag;
8290         /*
8291          * Check if we saw TCP timestamp.
8292          * Other consistency checks have already been done.
8293          */
8294         if (tcp->doff == 8) {
8295                 __be32 *ptr;
8296                 ptr = (__be32 *)(tcp+1);
8297                 lro->saw_ts = 1;
8298                 lro->cur_tsval = ntohl(*(ptr+1));
8299                 lro->cur_tsecr = *(ptr+2);
8300         }
8301         lro->in_use = 1;
8302 }
8303
8304 static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro)
8305 {
8306         struct iphdr *ip = lro->iph;
8307         struct tcphdr *tcp = lro->tcph;
8308         struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
8309
8310         DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8311
8312         /* Update L3 header */
8313         csum_replace2(&ip->check, ip->tot_len, htons(lro->total_len));
8314         ip->tot_len = htons(lro->total_len);
8315
8316         /* Update L4 header */
8317         tcp->ack_seq = lro->tcp_ack;
8318         tcp->window = lro->window;
8319
8320         /* Update tsecr field if this session has timestamps enabled */
8321         if (lro->saw_ts) {
8322                 __be32 *ptr = (__be32 *)(tcp + 1);
8323                 *(ptr+2) = lro->cur_tsecr;
8324         }
8325
8326         /* Update counters required for calculation of
8327          * average no. of packets aggregated.
8328          */
8329         swstats->sum_avg_pkts_aggregated += lro->sg_num;
8330         swstats->num_aggregations++;
8331 }
8332
8333 static void aggregate_new_rx(struct lro *lro, struct iphdr *ip,
8334                              struct tcphdr *tcp, u32 l4_pyld)
8335 {
8336         DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8337         lro->total_len += l4_pyld;
8338         lro->frags_len += l4_pyld;
8339         lro->tcp_next_seq += l4_pyld;
8340         lro->sg_num++;
8341
8342         /* Update ack seq no. and window ad(from this pkt) in LRO object */
8343         lro->tcp_ack = tcp->ack_seq;
8344         lro->window = tcp->window;
8345
8346         if (lro->saw_ts) {
8347                 __be32 *ptr;
8348                 /* Update tsecr and tsval from this packet */
8349                 ptr = (__be32 *)(tcp+1);
8350                 lro->cur_tsval = ntohl(*(ptr+1));
8351                 lro->cur_tsecr = *(ptr + 2);
8352         }
8353 }
8354
8355 static int verify_l3_l4_lro_capable(struct lro *l_lro, struct iphdr *ip,
8356                                     struct tcphdr *tcp, u32 tcp_pyld_len)
8357 {
8358         u8 *ptr;
8359
8360         DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8361
8362         if (!tcp_pyld_len) {
8363                 /* Runt frame or a pure ack */
8364                 return -1;
8365         }
8366
8367         if (ip->ihl != 5) /* IP has options */
8368                 return -1;
8369
8370         /* If we see CE codepoint in IP header, packet is not mergeable */
8371         if (INET_ECN_is_ce(ipv4_get_dsfield(ip)))
8372                 return -1;
8373
8374         /* If we see ECE or CWR flags in TCP header, packet is not mergeable */
8375         if (tcp->urg || tcp->psh || tcp->rst ||
8376             tcp->syn || tcp->fin ||
8377             tcp->ece || tcp->cwr || !tcp->ack) {
8378                 /*
8379                  * Currently recognize only the ack control word and
8380                  * any other control field being set would result in
8381                  * flushing the LRO session
8382                  */
8383                 return -1;
8384         }
8385
8386         /*
8387          * Allow only one TCP timestamp option. Don't aggregate if
8388          * any other options are detected.
8389          */
8390         if (tcp->doff != 5 && tcp->doff != 8)
8391                 return -1;
8392
8393         if (tcp->doff == 8) {
8394                 ptr = (u8 *)(tcp + 1);
8395                 while (*ptr == TCPOPT_NOP)
8396                         ptr++;
8397                 if (*ptr != TCPOPT_TIMESTAMP || *(ptr+1) != TCPOLEN_TIMESTAMP)
8398                         return -1;
8399
8400                 /* Ensure timestamp value increases monotonically */
8401                 if (l_lro)
8402                         if (l_lro->cur_tsval > ntohl(*((__be32 *)(ptr+2))))
8403                                 return -1;
8404
8405                 /* timestamp echo reply should be non-zero */
8406                 if (*((__be32 *)(ptr+6)) == 0)
8407                         return -1;
8408         }
8409
8410         return 0;
8411 }
8412
8413 static int s2io_club_tcp_session(struct ring_info *ring_data, u8 *buffer,
8414                                  u8 **tcp, u32 *tcp_len, struct lro **lro,
8415                                  struct RxD_t *rxdp, struct s2io_nic *sp)
8416 {
8417         struct iphdr *ip;
8418         struct tcphdr *tcph;
8419         int ret = 0, i;
8420         u16 vlan_tag = 0;
8421         struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
8422
8423         ret = check_L2_lro_capable(buffer, &ip, (struct tcphdr **)tcp,
8424                                    rxdp, sp);
8425         if (ret)
8426                 return ret;
8427
8428         DBG_PRINT(INFO_DBG, "IP Saddr: %x Daddr: %x\n", ip->saddr, ip->daddr);
8429
8430         vlan_tag = RXD_GET_VLAN_TAG(rxdp->Control_2);
8431         tcph = (struct tcphdr *)*tcp;
8432         *tcp_len = get_l4_pyld_length(ip, tcph);
8433         for (i = 0; i < MAX_LRO_SESSIONS; i++) {
8434                 struct lro *l_lro = &ring_data->lro0_n[i];
8435                 if (l_lro->in_use) {
8436                         if (check_for_socket_match(l_lro, ip, tcph))
8437                                 continue;
8438                         /* Sock pair matched */
8439                         *lro = l_lro;
8440
8441                         if ((*lro)->tcp_next_seq != ntohl(tcph->seq)) {
8442                                 DBG_PRINT(INFO_DBG, "%s: Out of sequence. "
8443                                           "expected 0x%x, actual 0x%x\n",
8444                                           __func__,
8445                                           (*lro)->tcp_next_seq,
8446                                           ntohl(tcph->seq));
8447
8448                                 swstats->outof_sequence_pkts++;
8449                                 ret = 2;
8450                                 break;
8451                         }
8452
8453                         if (!verify_l3_l4_lro_capable(l_lro, ip, tcph,
8454                                                       *tcp_len))
8455                                 ret = 1; /* Aggregate */
8456                         else
8457                                 ret = 2; /* Flush both */
8458                         break;
8459                 }
8460         }
8461
8462         if (ret == 0) {
8463                 /* Before searching for available LRO objects,
8464                  * check if the pkt is L3/L4 aggregatable. If not
8465                  * don't create new LRO session. Just send this
8466                  * packet up.
8467                  */
8468                 if (verify_l3_l4_lro_capable(NULL, ip, tcph, *tcp_len))
8469                         return 5;
8470
8471                 for (i = 0; i < MAX_LRO_SESSIONS; i++) {
8472                         struct lro *l_lro = &ring_data->lro0_n[i];
8473                         if (!(l_lro->in_use)) {
8474                                 *lro = l_lro;
8475                                 ret = 3; /* Begin anew */
8476                                 break;
8477                         }
8478                 }
8479         }
8480
8481         if (ret == 0) { /* sessions exceeded */
8482                 DBG_PRINT(INFO_DBG, "%s: All LRO sessions already in use\n",
8483                           __func__);
8484                 *lro = NULL;
8485                 return ret;
8486         }
8487
8488         switch (ret) {
8489         case 3:
8490                 initiate_new_session(*lro, buffer, ip, tcph, *tcp_len,
8491                                      vlan_tag);
8492                 break;
8493         case 2:
8494                 update_L3L4_header(sp, *lro);
8495                 break;
8496         case 1:
8497                 aggregate_new_rx(*lro, ip, tcph, *tcp_len);
8498                 if ((*lro)->sg_num == sp->lro_max_aggr_per_sess) {
8499                         update_L3L4_header(sp, *lro);
8500                         ret = 4; /* Flush the LRO */
8501                 }
8502                 break;
8503         default:
8504                 DBG_PRINT(ERR_DBG, "%s: Don't know, can't say!!\n", __func__);
8505                 break;
8506         }
8507
8508         return ret;
8509 }
8510
8511 static void clear_lro_session(struct lro *lro)
8512 {
8513         static u16 lro_struct_size = sizeof(struct lro);
8514
8515         memset(lro, 0, lro_struct_size);
8516 }
8517
8518 static void queue_rx_frame(struct sk_buff *skb, u16 vlan_tag)
8519 {
8520         struct net_device *dev = skb->dev;
8521         struct s2io_nic *sp = netdev_priv(dev);
8522
8523         skb->protocol = eth_type_trans(skb, dev);
8524         if (vlan_tag && sp->vlan_strip_flag)
8525                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);
8526         if (sp->config.napi)
8527                 netif_receive_skb(skb);
8528         else
8529                 netif_rx(skb);
8530 }
8531
8532 static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
8533                            struct sk_buff *skb, u32 tcp_len)
8534 {
8535         struct sk_buff *first = lro->parent;
8536         struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
8537
8538         first->len += tcp_len;
8539         first->data_len = lro->frags_len;
8540         skb_pull(skb, (skb->len - tcp_len));
8541         if (skb_shinfo(first)->frag_list)
8542                 lro->last_frag->next = skb;
8543         else
8544                 skb_shinfo(first)->frag_list = skb;
8545         first->truesize += skb->truesize;
8546         lro->last_frag = skb;
8547         swstats->clubbed_frms_cnt++;
8548 }
8549
8550 /**
8551  * s2io_io_error_detected - called when PCI error is detected
8552  * @pdev: Pointer to PCI device
8553  * @state: The current pci connection state
8554  *
8555  * This function is called after a PCI bus error affecting
8556  * this device has been detected.
8557  */
8558 static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev,
8559                                                pci_channel_state_t state)
8560 {
8561         struct net_device *netdev = pci_get_drvdata(pdev);
8562         struct s2io_nic *sp = netdev_priv(netdev);
8563
8564         netif_device_detach(netdev);
8565
8566         if (state == pci_channel_io_perm_failure)
8567                 return PCI_ERS_RESULT_DISCONNECT;
8568
8569         if (netif_running(netdev)) {
8570                 /* Bring down the card, while avoiding PCI I/O */
8571                 do_s2io_card_down(sp, 0);
8572         }
8573         pci_disable_device(pdev);
8574
8575         return PCI_ERS_RESULT_NEED_RESET;
8576 }
8577
8578 /**
8579  * s2io_io_slot_reset - called after the pci bus has been reset.
8580  * @pdev: Pointer to PCI device
8581  *
8582  * Restart the card from scratch, as if from a cold-boot.
8583  * At this point, the card has exprienced a hard reset,
8584  * followed by fixups by BIOS, and has its config space
8585  * set up identically to what it was at cold boot.
8586  */
8587 static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev)
8588 {
8589         struct net_device *netdev = pci_get_drvdata(pdev);
8590         struct s2io_nic *sp = netdev_priv(netdev);
8591
8592         if (pci_enable_device(pdev)) {
8593                 pr_err("Cannot re-enable PCI device after reset.\n");
8594                 return PCI_ERS_RESULT_DISCONNECT;
8595         }
8596
8597         pci_set_master(pdev);
8598         s2io_reset(sp);
8599
8600         return PCI_ERS_RESULT_RECOVERED;
8601 }
8602
8603 /**
8604  * s2io_io_resume - called when traffic can start flowing again.
8605  * @pdev: Pointer to PCI device
8606  *
8607  * This callback is called when the error recovery driver tells
8608  * us that its OK to resume normal operation.
8609  */
8610 static void s2io_io_resume(struct pci_dev *pdev)
8611 {
8612         struct net_device *netdev = pci_get_drvdata(pdev);
8613         struct s2io_nic *sp = netdev_priv(netdev);
8614
8615         if (netif_running(netdev)) {
8616                 if (s2io_card_up(sp)) {
8617                         pr_err("Can't bring device back up after reset.\n");
8618                         return;
8619                 }
8620
8621                 if (s2io_set_mac_addr(netdev, netdev->dev_addr) == FAILURE) {
8622                         s2io_card_down(sp);
8623                         pr_err("Can't restore mac addr after reset.\n");
8624                         return;
8625                 }
8626         }
8627
8628         netif_device_attach(netdev);
8629         netif_tx_wake_all_queues(netdev);
8630 }