2 * Copyright (C) 2015 Netronome Systems, Inc.
4 * This software is dual licensed under the GNU General License Version 2,
5 * June 1991 as shown in the file COPYING in the top-level directory of this
6 * source tree or the BSD 2-Clause License provided below. You have the
7 * option to license this software under the complete terms of either license.
9 * The BSD 2-Clause License:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * 1. Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * 2. Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 * Declarations for Netronome network device driver.
37 * Authors: Jakub Kicinski <jakub.kicinski@netronome.com>
38 * Jason McMullan <jason.mcmullan@netronome.com>
39 * Rolf Neugebauer <rolf.neugebauer@netronome.com>
45 #include <linux/interrupt.h>
46 #include <linux/netdevice.h>
47 #include <linux/pci.h>
48 #include <linux/io-64-nonatomic-hi-lo.h>
50 #include "nfp_net_ctrl.h"
52 #define nn_err(nn, fmt, args...) netdev_err((nn)->netdev, fmt, ## args)
53 #define nn_warn(nn, fmt, args...) netdev_warn((nn)->netdev, fmt, ## args)
54 #define nn_info(nn, fmt, args...) netdev_info((nn)->netdev, fmt, ## args)
55 #define nn_dbg(nn, fmt, args...) netdev_dbg((nn)->netdev, fmt, ## args)
56 #define nn_warn_ratelimit(nn, fmt, args...) \
58 if (unlikely(net_ratelimit())) \
59 netdev_warn((nn)->netdev, fmt, ## args); \
62 /* Max time to wait for NFP to respond on updates (in ms) */
63 #define NFP_NET_POLL_TIMEOUT 5000
66 #define NFP_NET_CRTL_BAR 0
67 #define NFP_NET_Q0_BAR 2
68 #define NFP_NET_Q1_BAR 4 /* OBSOLETE */
70 /* Max bits in DMA address */
71 #define NFP_NET_MAX_DMA_BITS 40
73 /* Default size for MTU and freelist buffer sizes */
74 #define NFP_NET_DEFAULT_MTU 1500
75 #define NFP_NET_DEFAULT_RX_BUFSZ 2048
77 /* Maximum number of bytes prepended to a packet */
78 #define NFP_NET_MAX_PREPEND 64
80 /* Interrupt definitions */
81 #define NFP_NET_NON_Q_VECTORS 2
82 #define NFP_NET_IRQ_LSC_IDX 0
83 #define NFP_NET_IRQ_EXN_IDX 1
85 /* Queue/Ring definitions */
86 #define NFP_NET_MAX_TX_RINGS 64 /* Max. # of Tx rings per device */
87 #define NFP_NET_MAX_RX_RINGS 64 /* Max. # of Rx rings per device */
89 #define NFP_NET_MIN_TX_DESCS 256 /* Min. # of Tx descs per ring */
90 #define NFP_NET_MIN_RX_DESCS 256 /* Min. # of Rx descs per ring */
91 #define NFP_NET_MAX_TX_DESCS (256 * 1024) /* Max. # of Tx descs per ring */
92 #define NFP_NET_MAX_RX_DESCS (256 * 1024) /* Max. # of Rx descs per ring */
94 #define NFP_NET_TX_DESCS_DEFAULT 4096 /* Default # of Tx descs per ring */
95 #define NFP_NET_RX_DESCS_DEFAULT 4096 /* Default # of Rx descs per ring */
97 #define NFP_NET_FL_BATCH 16 /* Add freelist in this Batch size */
99 /* Offload definitions */
100 #define NFP_NET_N_VXLAN_PORTS (NFP_NET_CFG_VXLAN_SZ / sizeof(__be16))
102 /* Forward declarations */
104 struct nfp_net_r_vector;
106 /* Convenience macro for writing dma address into RX/TX descriptors */
107 #define nfp_desc_set_dma_addr(desc, dma_addr) \
109 __typeof(desc) __d = (desc); \
110 dma_addr_t __addr = (dma_addr); \
112 __d->dma_addr_lo = cpu_to_le32(lower_32_bits(__addr)); \
113 __d->dma_addr_hi = upper_32_bits(__addr) & 0xff; \
116 /* TX descriptor format */
118 #define PCIE_DESC_TX_EOP BIT(7)
119 #define PCIE_DESC_TX_OFFSET_MASK GENMASK(6, 0)
120 #define PCIE_DESC_TX_MSS_MASK GENMASK(13, 0)
122 /* Flags in the host TX descriptor */
123 #define PCIE_DESC_TX_CSUM BIT(7)
124 #define PCIE_DESC_TX_IP4_CSUM BIT(6)
125 #define PCIE_DESC_TX_TCP_CSUM BIT(5)
126 #define PCIE_DESC_TX_UDP_CSUM BIT(4)
127 #define PCIE_DESC_TX_VLAN BIT(3)
128 #define PCIE_DESC_TX_LSO BIT(2)
129 #define PCIE_DESC_TX_ENCAP BIT(1)
130 #define PCIE_DESC_TX_O_IP4_CSUM BIT(0)
132 struct nfp_net_tx_desc {
135 u8 dma_addr_hi; /* High bits of host buf address */
136 __le16 dma_len; /* Length to DMA for this desc */
137 u8 offset_eop; /* Offset in buf where pkt starts +
138 * highest bit is eop flag.
140 __le32 dma_addr_lo; /* Low 32bit of host buf addr */
142 __le16 mss; /* MSS to be used for LSO */
143 u8 l4_offset; /* LSO, where the L4 data starts */
144 u8 flags; /* TX Flags, see @PCIE_DESC_TX_* */
146 __le16 vlan; /* VLAN tag to add if indicated */
147 __le16 data_len; /* Length of frame + meta data */
154 * struct nfp_net_tx_buf - software TX buffer descriptor
155 * @skb: sk_buff associated with this buffer
156 * @dma_addr: DMA mapping address of the buffer
157 * @fidx: Fragment index (-1 for the head and [0..nr_frags-1] for frags)
158 * @pkt_cnt: Number of packets to be produced out of the skb associated
159 * with this buffer (valid only on the head's buffer).
160 * Will be 1 for all non-TSO packets.
161 * @real_len: Number of bytes which to be produced out of the skb (valid only
162 * on the head's buffer). Equal to skb->len for non-TSO packets.
164 struct nfp_net_tx_buf {
173 * struct nfp_net_tx_ring - TX ring structure
174 * @r_vec: Back pointer to ring vector structure
175 * @idx: Ring index from Linux's perspective
176 * @qcidx: Queue Controller Peripheral (QCP) queue index for the TX queue
177 * @qcp_q: Pointer to base of the QCP TX queue
178 * @cnt: Size of the queue in number of descriptors
179 * @wr_p: TX ring write pointer (free running)
180 * @rd_p: TX ring read pointer (free running)
181 * @qcp_rd_p: Local copy of QCP TX queue read pointer
182 * @wr_ptr_add: Accumulated number of buffers to add to QCP write pointer
183 * (used for .xmit_more delayed kick)
184 * @txbufs: Array of transmitted TX buffers, to free on transmit
185 * @txds: Virtual address of TX ring in host memory
186 * @dma: DMA address of the TX ring
187 * @size: Size, in bytes, of the TX ring (needed to free)
189 struct nfp_net_tx_ring {
190 struct nfp_net_r_vector *r_vec;
203 struct nfp_net_tx_buf *txbufs;
204 struct nfp_net_tx_desc *txds;
208 } ____cacheline_aligned;
210 /* RX and freelist descriptor format */
212 #define PCIE_DESC_RX_DD BIT(7)
213 #define PCIE_DESC_RX_META_LEN_MASK GENMASK(6, 0)
215 /* Flags in the RX descriptor */
216 #define PCIE_DESC_RX_RSS cpu_to_le16(BIT(15))
217 #define PCIE_DESC_RX_I_IP4_CSUM cpu_to_le16(BIT(14))
218 #define PCIE_DESC_RX_I_IP4_CSUM_OK cpu_to_le16(BIT(13))
219 #define PCIE_DESC_RX_I_TCP_CSUM cpu_to_le16(BIT(12))
220 #define PCIE_DESC_RX_I_TCP_CSUM_OK cpu_to_le16(BIT(11))
221 #define PCIE_DESC_RX_I_UDP_CSUM cpu_to_le16(BIT(10))
222 #define PCIE_DESC_RX_I_UDP_CSUM_OK cpu_to_le16(BIT(9))
223 #define PCIE_DESC_RX_SPARE cpu_to_le16(BIT(8))
224 #define PCIE_DESC_RX_EOP cpu_to_le16(BIT(7))
225 #define PCIE_DESC_RX_IP4_CSUM cpu_to_le16(BIT(6))
226 #define PCIE_DESC_RX_IP4_CSUM_OK cpu_to_le16(BIT(5))
227 #define PCIE_DESC_RX_TCP_CSUM cpu_to_le16(BIT(4))
228 #define PCIE_DESC_RX_TCP_CSUM_OK cpu_to_le16(BIT(3))
229 #define PCIE_DESC_RX_UDP_CSUM cpu_to_le16(BIT(2))
230 #define PCIE_DESC_RX_UDP_CSUM_OK cpu_to_le16(BIT(1))
231 #define PCIE_DESC_RX_VLAN cpu_to_le16(BIT(0))
233 #define PCIE_DESC_RX_CSUM_ALL (PCIE_DESC_RX_IP4_CSUM | \
234 PCIE_DESC_RX_TCP_CSUM | \
235 PCIE_DESC_RX_UDP_CSUM | \
236 PCIE_DESC_RX_I_IP4_CSUM | \
237 PCIE_DESC_RX_I_TCP_CSUM | \
238 PCIE_DESC_RX_I_UDP_CSUM)
239 #define PCIE_DESC_RX_CSUM_OK_SHIFT 1
240 #define __PCIE_DESC_RX_CSUM_ALL le16_to_cpu(PCIE_DESC_RX_CSUM_ALL)
241 #define __PCIE_DESC_RX_CSUM_ALL_OK (__PCIE_DESC_RX_CSUM_ALL >> \
242 PCIE_DESC_RX_CSUM_OK_SHIFT)
244 struct nfp_net_rx_desc {
247 u8 dma_addr_hi; /* High bits of the buf address */
248 __le16 reserved; /* Must be zero */
249 u8 meta_len_dd; /* Must be zero */
251 __le32 dma_addr_lo; /* Low bits of the buffer address */
255 __le16 data_len; /* Length of the frame + meta data */
257 u8 meta_len_dd; /* Length of meta data prepended +
258 * descriptor done flag.
261 __le16 flags; /* RX flags. See @PCIE_DESC_RX_* */
262 __le16 vlan; /* VLAN if stripped */
269 struct nfp_net_rx_hash {
275 * struct nfp_net_rx_buf - software RX buffer descriptor
276 * @skb: sk_buff associated with this buffer
277 * @dma_addr: DMA mapping address of the buffer
279 struct nfp_net_rx_buf {
285 * struct nfp_net_rx_ring - RX ring structure
286 * @r_vec: Back pointer to ring vector structure
287 * @cnt: Size of the queue in number of descriptors
288 * @wr_p: FL/RX ring write pointer (free running)
289 * @rd_p: FL/RX ring read pointer (free running)
290 * @idx: Ring index from Linux's perspective
291 * @fl_qcidx: Queue Controller Peripheral (QCP) queue index for the freelist
292 * @rx_qcidx: Queue Controller Peripheral (QCP) queue index for the RX queue
293 * @qcp_fl: Pointer to base of the QCP freelist queue
294 * @qcp_rx: Pointer to base of the QCP RX queue
295 * @wr_ptr_add: Accumulated number of buffers to add to QCP write pointer
296 * (used for free list batching)
297 * @rxbufs: Array of transmitted FL/RX buffers
298 * @rxds: Virtual address of FL/RX ring in host memory
299 * @dma: DMA address of the FL/RX ring
300 * @size: Size, in bytes, of the FL/RX ring (needed to free)
302 struct nfp_net_rx_ring {
303 struct nfp_net_r_vector *r_vec;
317 struct nfp_net_rx_buf *rxbufs;
318 struct nfp_net_rx_desc *rxds;
322 } ____cacheline_aligned;
325 * struct nfp_net_r_vector - Per ring interrupt vector configuration
326 * @nfp_net: Backpointer to nfp_net structure
327 * @napi: NAPI structure for this ring vec
328 * @tx_ring: Pointer to TX ring
329 * @rx_ring: Pointer to RX ring
330 * @irq_idx: Index into MSI-X table
331 * @rx_sync: Seqlock for atomic updates of RX stats
332 * @rx_pkts: Number of received packets
333 * @rx_bytes: Number of received bytes
334 * @rx_drops: Number of packets dropped on RX due to lack of resources
335 * @hw_csum_rx_ok: Counter of packets where the HW checksum was OK
336 * @hw_csum_rx_inner_ok: Counter of packets where the inner HW checksum was OK
337 * @hw_csum_rx_error: Counter of packets with bad checksums
338 * @tx_sync: Seqlock for atomic updates of TX stats
339 * @tx_pkts: Number of Transmitted packets
340 * @tx_bytes: Number of Transmitted bytes
341 * @hw_csum_tx: Counter of packets with TX checksum offload requested
342 * @hw_csum_tx_inner: Counter of inner TX checksum offload requests
343 * @tx_gather: Counter of packets with Gather DMA
344 * @tx_lso: Counter of LSO packets sent
345 * @tx_errors: How many TX errors were encountered
346 * @tx_busy: How often was TX busy (no space)?
347 * @handler: Interrupt handler for this ring vector
348 * @name: Name of the interrupt vector
349 * @affinity_mask: SMP affinity mask for this vector
351 * This structure ties RX and TX rings to interrupt vectors and a NAPI
352 * context. This currently only supports one RX and TX ring per
353 * interrupt vector but might be extended in the future to allow
354 * association of multiple rings per vector.
356 struct nfp_net_r_vector {
357 struct nfp_net *nfp_net;
358 struct napi_struct napi;
360 struct nfp_net_tx_ring *tx_ring;
361 struct nfp_net_rx_ring *rx_ring;
365 struct u64_stats_sync rx_sync;
370 u64 hw_csum_rx_inner_ok;
371 u64 hw_csum_rx_error;
373 struct u64_stats_sync tx_sync;
377 u64 hw_csum_tx_inner;
383 irq_handler_t handler;
384 char name[IFNAMSIZ + 8];
385 cpumask_t affinity_mask;
386 } ____cacheline_aligned;
388 /* Firmware version as it is written in the 32bit value in the BAR */
389 struct nfp_net_fw_version {
396 static inline bool nfp_net_fw_ver_eq(struct nfp_net_fw_version *fw_ver,
397 u8 resv, u8 class, u8 major, u8 minor)
399 return fw_ver->resv == resv &&
400 fw_ver->class == class &&
401 fw_ver->major == major &&
402 fw_ver->minor == minor;
406 * struct nfp_net - NFP network device structure
407 * @pdev: Backpointer to PCI device
408 * @netdev: Backpointer to net_device structure
409 * @nfp_fallback: Is the driver used in fallback mode?
410 * @is_vf: Is the driver attached to a VF?
411 * @is_nfp3200: Is the driver for a NFP-3200 card?
412 * @fw_loaded: Is the firmware loaded?
413 * @ctrl: Local copy of the control register/word.
414 * @fl_bufsz: Currently configured size of the freelist buffers
415 * @rx_offset: Offset in the RX buffers where packet data starts
416 * @cpp: Pointer to the CPP handle
417 * @nfp_dev_cpp: Pointer to the NFP Device handle
418 * @ctrl_area: Pointer to the CPP area for the control BAR
419 * @tx_area: Pointer to the CPP area for the TX queues
420 * @rx_area: Pointer to the CPP area for the FL/RX queues
421 * @fw_ver: Firmware version
422 * @cap: Capabilities advertised by the Firmware
423 * @max_mtu: Maximum support MTU advertised by the Firmware
424 * @rss_cfg: RSS configuration
425 * @rss_key: RSS secret key
426 * @rss_itbl: RSS indirection table
427 * @max_tx_rings: Maximum number of TX rings supported by the Firmware
428 * @max_rx_rings: Maximum number of RX rings supported by the Firmware
429 * @num_tx_rings: Currently configured number of TX rings
430 * @num_rx_rings: Currently configured number of RX rings
431 * @txd_cnt: Size of the TX ring in number of descriptors
432 * @rxd_cnt: Size of the RX ring in number of descriptors
433 * @tx_rings: Array of pre-allocated TX ring structures
434 * @rx_rings: Array of pre-allocated RX ring structures
435 * @num_irqs: Number of allocated interrupt vectors
436 * @num_r_vecs: Number of used ring vectors
437 * @r_vecs: Pre-allocated array of ring vectors
438 * @irq_entries: Pre-allocated array of MSI-X entries
439 * @lsc_handler: Handler for Link State Change interrupt
440 * @lsc_name: Name for Link State Change interrupt
441 * @exn_handler: Handler for Exception interrupt
442 * @exn_name: Name for Exception interrupt
443 * @shared_handler: Handler for shared interrupts
444 * @shared_name: Name for shared interrupt
445 * @me_freq_mhz: ME clock_freq (MHz)
446 * @reconfig_lock: Protects HW reconfiguration request regs/machinery
447 * @link_up: Is the link up?
448 * @link_status_lock: Protects @link_up and ensures atomicity with BAR reading
449 * @rx_coalesce_usecs: RX interrupt moderation usecs delay parameter
450 * @rx_coalesce_max_frames: RX interrupt moderation frame count parameter
451 * @tx_coalesce_usecs: TX interrupt moderation usecs delay parameter
452 * @tx_coalesce_max_frames: TX interrupt moderation frame count parameter
453 * @vxlan_ports: VXLAN ports for RX inner csum offload communicated to HW
454 * @vxlan_usecnt: IPv4/IPv6 VXLAN port use counts
455 * @qcp_cfg: Pointer to QCP queue used for configuration notification
456 * @ctrl_bar: Pointer to mapped control BAR
457 * @tx_bar: Pointer to mapped TX queues
458 * @rx_bar: Pointer to mapped FL/RX queues
459 * @debugfs_dir: Device directory in debugfs
462 struct pci_dev *pdev;
463 struct net_device *netdev;
465 unsigned nfp_fallback:1;
467 unsigned is_nfp3200:1;
468 unsigned fw_loaded:1;
475 #ifdef CONFIG_PCI_IOV
476 unsigned int num_vfs;
477 struct vf_data_storage *vfinfo;
478 int vf_rate_link_speed;
482 struct platform_device *nfp_dev_cpp;
483 struct nfp_cpp_area *ctrl_area;
484 struct nfp_cpp_area *tx_area;
485 struct nfp_cpp_area *rx_area;
487 struct nfp_net_fw_version fw_ver;
492 u8 rss_key[NFP_NET_CFG_RSS_KEY_SZ];
493 u8 rss_itbl[NFP_NET_CFG_RSS_ITBL_SZ];
507 struct nfp_net_tx_ring tx_rings[NFP_NET_MAX_TX_RINGS];
508 struct nfp_net_rx_ring rx_rings[NFP_NET_MAX_RX_RINGS];
512 struct nfp_net_r_vector r_vecs[NFP_NET_MAX_TX_RINGS];
513 struct msix_entry irq_entries[NFP_NET_NON_Q_VECTORS +
514 NFP_NET_MAX_TX_RINGS];
516 irq_handler_t lsc_handler;
517 char lsc_name[IFNAMSIZ + 8];
519 irq_handler_t exn_handler;
520 char exn_name[IFNAMSIZ + 8];
522 irq_handler_t shared_handler;
523 char shared_name[IFNAMSIZ + 8];
528 spinlock_t link_status_lock;
530 spinlock_t reconfig_lock;
532 u32 rx_coalesce_usecs;
533 u32 rx_coalesce_max_frames;
534 u32 tx_coalesce_usecs;
535 u32 tx_coalesce_max_frames;
537 __be16 vxlan_ports[NFP_NET_N_VXLAN_PORTS];
538 u8 vxlan_usecnt[NFP_NET_N_VXLAN_PORTS];
542 u8 __iomem *ctrl_bar;
547 struct dentry *debugfs_dir;
550 /* Functions to read/write from/to a BAR
551 * Performs any endian conversion necessary.
553 static inline void nn_writeb(struct nfp_net *nn, int off, u8 val)
555 writeb(val, nn->ctrl_bar + off);
558 /* NFP-3200 can't handle 16-bit accesses too well - hence no readw/writew */
560 static inline u32 nn_readl(struct nfp_net *nn, int off)
562 return readl(nn->ctrl_bar + off);
565 static inline void nn_writel(struct nfp_net *nn, int off, u32 val)
567 writel(val, nn->ctrl_bar + off);
570 static inline u64 nn_readq(struct nfp_net *nn, int off)
572 return readq(nn->ctrl_bar + off);
575 static inline void nn_writeq(struct nfp_net *nn, int off, u64 val)
577 writeq(val, nn->ctrl_bar + off);
580 /* Flush posted PCI writes by reading something without side effects */
581 static inline void nn_pci_flush(struct nfp_net *nn)
583 nn_readl(nn, NFP_NET_CFG_VERSION);
586 /* Queue Controller Peripheral access functions and definitions.
588 * Some of the BARs of the NFP are mapped to portions of the Queue
589 * Controller Peripheral (QCP) address space on the NFP. A QCP queue
590 * has a read and a write pointer (as well as a size and flags,
591 * indicating overflow etc). The QCP offers a number of different
592 * operation on queue pointers, but here we only offer function to
593 * either add to a pointer or to read the pointer value.
595 #define NFP_QCP_QUEUE_ADDR_SZ 0x800
596 #define NFP_QCP_QUEUE_OFF(_x) ((_x) * NFP_QCP_QUEUE_ADDR_SZ)
597 #define NFP_QCP_QUEUE_ADD_RPTR 0x0000
598 #define NFP_QCP_QUEUE_ADD_WPTR 0x0004
599 #define NFP_QCP_QUEUE_STS_LO 0x0008
600 #define NFP_QCP_QUEUE_STS_LO_READPTR_mask 0x3ffff
601 #define NFP_QCP_QUEUE_STS_HI 0x000c
602 #define NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask 0x3ffff
604 /* The offset of a QCP queues in the PCIe Target (same on NFP3200 and NFP6000 */
605 #define NFP_PCIE_QUEUE(_q) (0x80000 + (NFP_QCP_QUEUE_ADDR_SZ * ((_q) & 0xff)))
607 /* nfp_qcp_ptr - Read or Write Pointer of a queue */
609 NFP_QCP_READ_PTR = 0,
613 /* There appear to be an *undocumented* upper limit on the value which
614 * one can add to a queue and that value is either 0x3f or 0x7f. We
615 * go with 0x3f as a conservative measure.
617 #define NFP_QCP_MAX_ADD 0x3f
619 static inline void _nfp_qcp_ptr_add(u8 __iomem *q,
620 enum nfp_qcp_ptr ptr, u32 val)
624 if (ptr == NFP_QCP_READ_PTR)
625 off = NFP_QCP_QUEUE_ADD_RPTR;
627 off = NFP_QCP_QUEUE_ADD_WPTR;
629 while (val > NFP_QCP_MAX_ADD) {
630 writel(NFP_QCP_MAX_ADD, q + off);
631 val -= NFP_QCP_MAX_ADD;
634 writel(val, q + off);
638 * nfp_qcp_rd_ptr_add() - Add the value to the read pointer of a queue
640 * @q: Base address for queue structure
641 * @val: Value to add to the queue pointer
643 * If @val is greater than @NFP_QCP_MAX_ADD multiple writes are performed.
645 static inline void nfp_qcp_rd_ptr_add(u8 __iomem *q, u32 val)
647 _nfp_qcp_ptr_add(q, NFP_QCP_READ_PTR, val);
651 * nfp_qcp_wr_ptr_add() - Add the value to the write pointer of a queue
653 * @q: Base address for queue structure
654 * @val: Value to add to the queue pointer
656 * If @val is greater than @NFP_QCP_MAX_ADD multiple writes are performed.
658 static inline void nfp_qcp_wr_ptr_add(u8 __iomem *q, u32 val)
660 _nfp_qcp_ptr_add(q, NFP_QCP_WRITE_PTR, val);
663 static inline u32 _nfp_qcp_read(u8 __iomem *q, enum nfp_qcp_ptr ptr)
668 if (ptr == NFP_QCP_READ_PTR)
669 off = NFP_QCP_QUEUE_STS_LO;
671 off = NFP_QCP_QUEUE_STS_HI;
673 val = readl(q + off);
675 if (ptr == NFP_QCP_READ_PTR)
676 return val & NFP_QCP_QUEUE_STS_LO_READPTR_mask;
678 return val & NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask;
682 * nfp_qcp_rd_ptr_read() - Read the current read pointer value for a queue
683 * @q: Base address for queue structure
685 * Return: Value read.
687 static inline u32 nfp_qcp_rd_ptr_read(u8 __iomem *q)
689 return _nfp_qcp_read(q, NFP_QCP_READ_PTR);
693 * nfp_qcp_wr_ptr_read() - Read the current write pointer value for a queue
694 * @q: Base address for queue structure
696 * Return: Value read.
698 static inline u32 nfp_qcp_wr_ptr_read(u8 __iomem *q)
700 return _nfp_qcp_read(q, NFP_QCP_WRITE_PTR);
704 extern const char nfp_net_driver_name[];
705 extern const char nfp_net_driver_version[];
708 void nfp_net_get_fw_version(struct nfp_net_fw_version *fw_ver,
709 void __iomem *ctrl_bar);
711 struct nfp_net *nfp_net_netdev_alloc(struct pci_dev *pdev,
712 int max_tx_rings, int max_rx_rings);
713 void nfp_net_netdev_free(struct nfp_net *nn);
714 int nfp_net_netdev_init(struct net_device *netdev);
715 void nfp_net_netdev_clean(struct net_device *netdev);
716 void nfp_net_set_ethtool_ops(struct net_device *netdev);
717 void nfp_net_info(struct nfp_net *nn);
718 int nfp_net_reconfig(struct nfp_net *nn, u32 update);
719 void nfp_net_rss_write_itbl(struct nfp_net *nn);
720 void nfp_net_rss_write_key(struct nfp_net *nn);
721 void nfp_net_coalesce_write_cfg(struct nfp_net *nn);
722 int nfp_net_irqs_alloc(struct nfp_net *nn);
723 void nfp_net_irqs_disable(struct nfp_net *nn);
725 #ifdef CONFIG_NFP_NET_DEBUG
726 void nfp_net_debugfs_create(void);
727 void nfp_net_debugfs_destroy(void);
728 void nfp_net_debugfs_adapter_add(struct nfp_net *nn);
729 void nfp_net_debugfs_adapter_del(struct nfp_net *nn);
731 static inline void nfp_net_debugfs_create(void)
735 static inline void nfp_net_debugfs_destroy(void)
739 static inline void nfp_net_debugfs_adapter_add(struct nfp_net *nn)
743 static inline void nfp_net_debugfs_adapter_del(struct nfp_net *nn)
746 #endif /* CONFIG_NFP_NET_DEBUG */
748 #endif /* _NFP_NET_H_ */