drivers/net/ethernet/nvidia/forcedeth.c

   1 /*
   2  * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
   3  *
   4  * Note: This driver is a cleanroom reimplementation based on reverse
   5  *      engineered documentation written by Carl-Daniel Hailfinger
   6  *      and Andrew de Quincey.
   7  *
   8  * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
   9  * trademarks of NVIDIA Corporation in the United States and other
  10  * countries.
  11  *
  12  * Copyright (C) 2003,4,5 Manfred Spraul
  13  * Copyright (C) 2004 Andrew de Quincey (wol support)
  14  * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
  15  *              IRQ rate fixes, bigendian fixes, cleanups, verification)
  16  * Copyright (c) 2004,2005,2006,2007,2008,2009 NVIDIA Corporation
  17  *
  18  * This program is free software; you can redistribute it and/or modify
  19  * it under the terms of the GNU General Public License as published by
  20  * the Free Software Foundation; either version 2 of the License, or
  21  * (at your option) any later version.
  22  *
  23  * This program is distributed in the hope that it will be useful,
  24  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  25  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  26  * GNU General Public License for more details.
  27  *
  28  * You should have received a copy of the GNU General Public License
  29  * along with this program; if not, write to the Free Software
  30  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  31  *
  32  * Known bugs:
  33  * We suspect that on some hardware no TX done interrupts are generated.
  34  * This means recovery from netif_stop_queue only happens if the hw timer
  35  * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
  36  * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
  37  * If your hardware reliably generates tx done interrupts, then you can remove
  38  * DEV_NEED_TIMERIRQ from the driver_data flags.
  39  * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
  40  * superfluous timer interrupts from the nic.
  41  */
  42
  43 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  44
  45 #define FORCEDETH_VERSION               "0.64"
  46 #define DRV_NAME                        "forcedeth"
  47
  48 #include <linux/module.h>
  49 #include <linux/types.h>
  50 #include <linux/pci.h>
  51 #include <linux/interrupt.h>
  52 #include <linux/netdevice.h>
  53 #include <linux/etherdevice.h>
  54 #include <linux/delay.h>
  55 #include <linux/sched.h>
  56 #include <linux/spinlock.h>
  57 #include <linux/ethtool.h>
  58 #include <linux/timer.h>
  59 #include <linux/skbuff.h>
  60 #include <linux/mii.h>
  61 #include <linux/random.h>
  62 #include <linux/init.h>
  63 #include <linux/if_vlan.h>
  64 #include <linux/dma-mapping.h>
  65 #include <linux/slab.h>
  66 #include <linux/uaccess.h>
  67 #include <linux/prefetch.h>
  68 #include  <linux/io.h>
  69
  70 #include <asm/irq.h>
  71 #include <asm/system.h>
  72
  73 #define TX_WORK_PER_LOOP  64
  74 #define RX_WORK_PER_LOOP  64
  75
  76 /*
  77  * Hardware access:
  78  */
  79
  80 #define DEV_NEED_TIMERIRQ          0x0000001  /* set the timer irq flag in the irq mask */
  81 #define DEV_NEED_LINKTIMER         0x0000002  /* poll link settings. Relies on the timer irq */
  82 #define DEV_HAS_LARGEDESC          0x0000004  /* device supports jumbo frames and needs packet format 2 */
  83 #define DEV_HAS_HIGH_DMA           0x0000008  /* device supports 64bit dma */
  84 #define DEV_HAS_CHECKSUM           0x0000010  /* device supports tx and rx checksum offloads */
  85 #define DEV_HAS_VLAN               0x0000020  /* device supports vlan tagging and striping */
  86 #define DEV_HAS_MSI                0x0000040  /* device supports MSI */
  87 #define DEV_HAS_MSI_X              0x0000080  /* device supports MSI-X */
  88 #define DEV_HAS_POWER_CNTRL        0x0000100  /* device supports power savings */
  89 #define DEV_HAS_STATISTICS_V1      0x0000200  /* device supports hw statistics version 1 */
  90 #define DEV_HAS_STATISTICS_V2      0x0000400  /* device supports hw statistics version 2 */
  91 #define DEV_HAS_STATISTICS_V3      0x0000800  /* device supports hw statistics version 3 */
  92 #define DEV_HAS_STATISTICS_V12     0x0000600  /* device supports hw statistics version 1 and 2 */
  93 #define DEV_HAS_STATISTICS_V123    0x0000e00  /* device supports hw statistics version 1, 2, and 3 */
  94 #define DEV_HAS_TEST_EXTENDED      0x0001000  /* device supports extended diagnostic test */
  95 #define DEV_HAS_MGMT_UNIT          0x0002000  /* device supports management unit */
  96 #define DEV_HAS_CORRECT_MACADDR    0x0004000  /* device supports correct mac address order */
  97 #define DEV_HAS_COLLISION_FIX      0x0008000  /* device supports tx collision fix */
  98 #define DEV_HAS_PAUSEFRAME_TX_V1   0x0010000  /* device supports tx pause frames version 1 */
  99 #define DEV_HAS_PAUSEFRAME_TX_V2   0x0020000  /* device supports tx pause frames version 2 */
 100 #define DEV_HAS_PAUSEFRAME_TX_V3   0x0040000  /* device supports tx pause frames version 3 */
 101 #define DEV_NEED_TX_LIMIT          0x0080000  /* device needs to limit tx */
 102 #define DEV_NEED_TX_LIMIT2         0x0180000  /* device needs to limit tx, expect for some revs */
 103 #define DEV_HAS_GEAR_MODE          0x0200000  /* device supports gear mode */
 104 #define DEV_NEED_PHY_INIT_FIX      0x0400000  /* device needs specific phy workaround */
 105 #define DEV_NEED_LOW_POWER_FIX     0x0800000  /* device needs special power up workaround */
 106 #define DEV_NEED_MSI_FIX           0x1000000  /* device needs msi workaround */
 107
 108 enum {
 109         NvRegIrqStatus = 0x000,
 110 #define NVREG_IRQSTAT_MIIEVENT  0x040
 111 #define NVREG_IRQSTAT_MASK              0x83ff
 112         NvRegIrqMask = 0x004,
 113 #define NVREG_IRQ_RX_ERROR              0x0001
 114 #define NVREG_IRQ_RX                    0x0002
 115 #define NVREG_IRQ_RX_NOBUF              0x0004
 116 #define NVREG_IRQ_TX_ERR                0x0008
 117 #define NVREG_IRQ_TX_OK                 0x0010
 118 #define NVREG_IRQ_TIMER                 0x0020
 119 #define NVREG_IRQ_LINK                  0x0040
 120 #define NVREG_IRQ_RX_FORCED             0x0080
 121 #define NVREG_IRQ_TX_FORCED             0x0100
 122 #define NVREG_IRQ_RECOVER_ERROR         0x8200
 123 #define NVREG_IRQMASK_THROUGHPUT        0x00df
 124 #define NVREG_IRQMASK_CPU               0x0060
 125 #define NVREG_IRQ_TX_ALL                (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
 126 #define NVREG_IRQ_RX_ALL                (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
 127 #define NVREG_IRQ_OTHER                 (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
 128
 129         NvRegUnknownSetupReg6 = 0x008,
 130 #define NVREG_UNKSETUP6_VAL             3
 131
 132 /*
 133  * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
 134  * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
 135  */
 136         NvRegPollingInterval = 0x00c,
 137 #define NVREG_POLL_DEFAULT_THROUGHPUT   65535 /* backup tx cleanup if loop max reached */
 138 #define NVREG_POLL_DEFAULT_CPU  13
 139         NvRegMSIMap0 = 0x020,
 140         NvRegMSIMap1 = 0x024,
 141         NvRegMSIIrqMask = 0x030,
 142 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
 143         NvRegMisc1 = 0x080,
 144 #define NVREG_MISC1_PAUSE_TX    0x01
 145 #define NVREG_MISC1_HD          0x02
 146 #define NVREG_MISC1_FORCE       0x3b0f3c
 147
 148         NvRegMacReset = 0x34,
 149 #define NVREG_MAC_RESET_ASSERT  0x0F3
 150         NvRegTransmitterControl = 0x084,
 151 #define NVREG_XMITCTL_START     0x01
 152 #define NVREG_XMITCTL_MGMT_ST   0x40000000
 153 #define NVREG_XMITCTL_SYNC_MASK         0x000f0000
 154 #define NVREG_XMITCTL_SYNC_NOT_READY    0x0
 155 #define NVREG_XMITCTL_SYNC_PHY_INIT     0x00040000
 156 #define NVREG_XMITCTL_MGMT_SEMA_MASK    0x00000f00
 157 #define NVREG_XMITCTL_MGMT_SEMA_FREE    0x0
 158 #define NVREG_XMITCTL_HOST_SEMA_MASK    0x0000f000
 159 #define NVREG_XMITCTL_HOST_SEMA_ACQ     0x0000f000
 160 #define NVREG_XMITCTL_HOST_LOADED       0x00004000
 161 #define NVREG_XMITCTL_TX_PATH_EN        0x01000000
 162 #define NVREG_XMITCTL_DATA_START        0x00100000
 163 #define NVREG_XMITCTL_DATA_READY        0x00010000
 164 #define NVREG_XMITCTL_DATA_ERROR        0x00020000
 165         NvRegTransmitterStatus = 0x088,
 166 #define NVREG_XMITSTAT_BUSY     0x01
 167
 168         NvRegPacketFilterFlags = 0x8c,
 169 #define NVREG_PFF_PAUSE_RX      0x08
 170 #define NVREG_PFF_ALWAYS        0x7F0000
 171 #define NVREG_PFF_PROMISC       0x80
 172 #define NVREG_PFF_MYADDR        0x20
 173 #define NVREG_PFF_LOOPBACK      0x10
 174
 175         NvRegOffloadConfig = 0x90,
 176 #define NVREG_OFFLOAD_HOMEPHY   0x601
 177 #define NVREG_OFFLOAD_NORMAL    RX_NIC_BUFSIZE
 178         NvRegReceiverControl = 0x094,
 179 #define NVREG_RCVCTL_START      0x01
 180 #define NVREG_RCVCTL_RX_PATH_EN 0x01000000
 181         NvRegReceiverStatus = 0x98,
 182 #define NVREG_RCVSTAT_BUSY      0x01
 183
 184         NvRegSlotTime = 0x9c,
 185 #define NVREG_SLOTTIME_LEGBF_ENABLED    0x80000000
 186 #define NVREG_SLOTTIME_10_100_FULL      0x00007f00
 187 #define NVREG_SLOTTIME_1000_FULL        0x0003ff00
 188 #define NVREG_SLOTTIME_HALF             0x0000ff00
 189 #define NVREG_SLOTTIME_DEFAULT          0x00007f00
 190 #define NVREG_SLOTTIME_MASK             0x000000ff
 191
 192         NvRegTxDeferral = 0xA0,
 193 #define NVREG_TX_DEFERRAL_DEFAULT               0x15050f
 194 #define NVREG_TX_DEFERRAL_RGMII_10_100          0x16070f
 195 #define NVREG_TX_DEFERRAL_RGMII_1000            0x14050f
 196 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_10      0x16190f
 197 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_100     0x16300f
 198 #define NVREG_TX_DEFERRAL_MII_STRETCH           0x152000
 199         NvRegRxDeferral = 0xA4,
 200 #define NVREG_RX_DEFERRAL_DEFAULT       0x16
 201         NvRegMacAddrA = 0xA8,
 202         NvRegMacAddrB = 0xAC,
 203         NvRegMulticastAddrA = 0xB0,
 204 #define NVREG_MCASTADDRA_FORCE  0x01
 205         NvRegMulticastAddrB = 0xB4,
 206         NvRegMulticastMaskA = 0xB8,
 207 #define NVREG_MCASTMASKA_NONE           0xffffffff
 208         NvRegMulticastMaskB = 0xBC,
 209 #define NVREG_MCASTMASKB_NONE           0xffff
 210
 211         NvRegPhyInterface = 0xC0,
 212 #define PHY_RGMII               0x10000000
 213         NvRegBackOffControl = 0xC4,
 214 #define NVREG_BKOFFCTRL_DEFAULT                 0x70000000
 215 #define NVREG_BKOFFCTRL_SEED_MASK               0x000003ff
 216 #define NVREG_BKOFFCTRL_SELECT                  24
 217 #define NVREG_BKOFFCTRL_GEAR                    12
 218
 219         NvRegTxRingPhysAddr = 0x100,
 220         NvRegRxRingPhysAddr = 0x104,
 221         NvRegRingSizes = 0x108,
 222 #define NVREG_RINGSZ_TXSHIFT 0
 223 #define NVREG_RINGSZ_RXSHIFT 16
 224         NvRegTransmitPoll = 0x10c,
 225 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
 226         NvRegLinkSpeed = 0x110,
 227 #define NVREG_LINKSPEED_FORCE 0x10000
 228 #define NVREG_LINKSPEED_10      1000
 229 #define NVREG_LINKSPEED_100     100
 230 #define NVREG_LINKSPEED_1000    50
 231 #define NVREG_LINKSPEED_MASK    (0xFFF)
 232         NvRegUnknownSetupReg5 = 0x130,
 233 #define NVREG_UNKSETUP5_BIT31   (1<<31)
 234         NvRegTxWatermark = 0x13c,
 235 #define NVREG_TX_WM_DESC1_DEFAULT       0x0200010
 236 #define NVREG_TX_WM_DESC2_3_DEFAULT     0x1e08000
 237 #define NVREG_TX_WM_DESC2_3_1000        0xfe08000
 238         NvRegTxRxControl = 0x144,
 239 #define NVREG_TXRXCTL_KICK      0x0001
 240 #define NVREG_TXRXCTL_BIT1      0x0002
 241 #define NVREG_TXRXCTL_BIT2      0x0004
 242 #define NVREG_TXRXCTL_IDLE      0x0008
 243 #define NVREG_TXRXCTL_RESET     0x0010
 244 #define NVREG_TXRXCTL_RXCHECK   0x0400
 245 #define NVREG_TXRXCTL_DESC_1    0
 246 #define NVREG_TXRXCTL_DESC_2    0x002100
 247 #define NVREG_TXRXCTL_DESC_3    0xc02200
 248 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
 249 #define NVREG_TXRXCTL_VLANINS   0x00080
 250         NvRegTxRingPhysAddrHigh = 0x148,
 251         NvRegRxRingPhysAddrHigh = 0x14C,
 252         NvRegTxPauseFrame = 0x170,
 253 #define NVREG_TX_PAUSEFRAME_DISABLE     0x0fff0080
 254 #define NVREG_TX_PAUSEFRAME_ENABLE_V1   0x01800010
 255 #define NVREG_TX_PAUSEFRAME_ENABLE_V2   0x056003f0
 256 #define NVREG_TX_PAUSEFRAME_ENABLE_V3   0x09f00880
 257         NvRegTxPauseFrameLimit = 0x174,
 258 #define NVREG_TX_PAUSEFRAMELIMIT_ENABLE 0x00010000
 259         NvRegMIIStatus = 0x180,
 260 #define NVREG_MIISTAT_ERROR             0x0001
 261 #define NVREG_MIISTAT_LINKCHANGE        0x0008
 262 #define NVREG_MIISTAT_MASK_RW           0x0007
 263 #define NVREG_MIISTAT_MASK_ALL          0x000f
 264         NvRegMIIMask = 0x184,
 265 #define NVREG_MII_LINKCHANGE            0x0008
 266
 267         NvRegAdapterControl = 0x188,
 268 #define NVREG_ADAPTCTL_START    0x02
 269 #define NVREG_ADAPTCTL_LINKUP   0x04
 270 #define NVREG_ADAPTCTL_PHYVALID 0x40000
 271 #define NVREG_ADAPTCTL_RUNNING  0x100000
 272 #define NVREG_ADAPTCTL_PHYSHIFT 24
 273         NvRegMIISpeed = 0x18c,
 274 #define NVREG_MIISPEED_BIT8     (1<<8)
 275 #define NVREG_MIIDELAY  5
 276         NvRegMIIControl = 0x190,
 277 #define NVREG_MIICTL_INUSE      0x08000
 278 #define NVREG_MIICTL_WRITE      0x00400
 279 #define NVREG_MIICTL_ADDRSHIFT  5
 280         NvRegMIIData = 0x194,
 281         NvRegTxUnicast = 0x1a0,
 282         NvRegTxMulticast = 0x1a4,
 283         NvRegTxBroadcast = 0x1a8,
 284         NvRegWakeUpFlags = 0x200,
 285 #define NVREG_WAKEUPFLAGS_VAL           0x7770
 286 #define NVREG_WAKEUPFLAGS_BUSYSHIFT     24
 287 #define NVREG_WAKEUPFLAGS_ENABLESHIFT   16
 288 #define NVREG_WAKEUPFLAGS_D3SHIFT       12
 289 #define NVREG_WAKEUPFLAGS_D2SHIFT       8
 290 #define NVREG_WAKEUPFLAGS_D1SHIFT       4
 291 #define NVREG_WAKEUPFLAGS_D0SHIFT       0
 292 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT         0x01
 293 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT      0x02
 294 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE     0x04
 295 #define NVREG_WAKEUPFLAGS_ENABLE        0x1111
 296
 297         NvRegMgmtUnitGetVersion = 0x204,
 298 #define NVREG_MGMTUNITGETVERSION        0x01
 299         NvRegMgmtUnitVersion = 0x208,
 300 #define NVREG_MGMTUNITVERSION           0x08
 301         NvRegPowerCap = 0x268,
 302 #define NVREG_POWERCAP_D3SUPP   (1<<30)
 303 #define NVREG_POWERCAP_D2SUPP   (1<<26)
 304 #define NVREG_POWERCAP_D1SUPP   (1<<25)
 305         NvRegPowerState = 0x26c,
 306 #define NVREG_POWERSTATE_POWEREDUP      0x8000
 307 #define NVREG_POWERSTATE_VALID          0x0100
 308 #define NVREG_POWERSTATE_MASK           0x0003
 309 #define NVREG_POWERSTATE_D0             0x0000
 310 #define NVREG_POWERSTATE_D1             0x0001
 311 #define NVREG_POWERSTATE_D2             0x0002
 312 #define NVREG_POWERSTATE_D3             0x0003
 313         NvRegMgmtUnitControl = 0x278,
 314 #define NVREG_MGMTUNITCONTROL_INUSE     0x20000
 315         NvRegTxCnt = 0x280,
 316         NvRegTxZeroReXmt = 0x284,
 317         NvRegTxOneReXmt = 0x288,
 318         NvRegTxManyReXmt = 0x28c,
 319         NvRegTxLateCol = 0x290,
 320         NvRegTxUnderflow = 0x294,
 321         NvRegTxLossCarrier = 0x298,
 322         NvRegTxExcessDef = 0x29c,
 323         NvRegTxRetryErr = 0x2a0,
 324         NvRegRxFrameErr = 0x2a4,
 325         NvRegRxExtraByte = 0x2a8,
 326         NvRegRxLateCol = 0x2ac,
 327         NvRegRxRunt = 0x2b0,
 328         NvRegRxFrameTooLong = 0x2b4,
 329         NvRegRxOverflow = 0x2b8,
 330         NvRegRxFCSErr = 0x2bc,
 331         NvRegRxFrameAlignErr = 0x2c0,
 332         NvRegRxLenErr = 0x2c4,
 333         NvRegRxUnicast = 0x2c8,
 334         NvRegRxMulticast = 0x2cc,
 335         NvRegRxBroadcast = 0x2d0,
 336         NvRegTxDef = 0x2d4,
 337         NvRegTxFrame = 0x2d8,
 338         NvRegRxCnt = 0x2dc,
 339         NvRegTxPause = 0x2e0,
 340         NvRegRxPause = 0x2e4,
 341         NvRegRxDropFrame = 0x2e8,
 342         NvRegVlanControl = 0x300,
 343 #define NVREG_VLANCONTROL_ENABLE        0x2000
 344         NvRegMSIXMap0 = 0x3e0,
 345         NvRegMSIXMap1 = 0x3e4,
 346         NvRegMSIXIrqStatus = 0x3f0,
 347
 348         NvRegPowerState2 = 0x600,
 349 #define NVREG_POWERSTATE2_POWERUP_MASK          0x0F15
 350 #define NVREG_POWERSTATE2_POWERUP_REV_A3        0x0001
 351 #define NVREG_POWERSTATE2_PHY_RESET             0x0004
 352 #define NVREG_POWERSTATE2_GATE_CLOCKS           0x0F00
 353 };
 354
 355 /* Big endian: should work, but is untested */
 356 struct ring_desc {
 357         __le32 buf;
 358         __le32 flaglen;
 359 };
 360
 361 struct ring_desc_ex {
 362         __le32 bufhigh;
 363         __le32 buflow;
 364         __le32 txvlan;
 365         __le32 flaglen;
 366 };
 367
 368 union ring_type {
 369         struct ring_desc *orig;
 370         struct ring_desc_ex *ex;
 371 };
 372
 373 #define FLAG_MASK_V1 0xffff0000
 374 #define FLAG_MASK_V2 0xffffc000
 375 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
 376 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
 377
 378 #define NV_TX_LASTPACKET        (1<<16)
 379 #define NV_TX_RETRYERROR        (1<<19)
 380 #define NV_TX_RETRYCOUNT_MASK   (0xF<<20)
 381 #define NV_TX_FORCED_INTERRUPT  (1<<24)
 382 #define NV_TX_DEFERRED          (1<<26)
 383 #define NV_TX_CARRIERLOST       (1<<27)
 384 #define NV_TX_LATECOLLISION     (1<<28)
 385 #define NV_TX_UNDERFLOW         (1<<29)
 386 #define NV_TX_ERROR             (1<<30)
 387 #define NV_TX_VALID             (1<<31)
 388
 389 #define NV_TX2_LASTPACKET       (1<<29)
 390 #define NV_TX2_RETRYERROR       (1<<18)
 391 #define NV_TX2_RETRYCOUNT_MASK  (0xF<<19)
 392 #define NV_TX2_FORCED_INTERRUPT (1<<30)
 393 #define NV_TX2_DEFERRED         (1<<25)
 394 #define NV_TX2_CARRIERLOST      (1<<26)
 395 #define NV_TX2_LATECOLLISION    (1<<27)
 396 #define NV_TX2_UNDERFLOW        (1<<28)
 397 /* error and valid are the same for both */
 398 #define NV_TX2_ERROR            (1<<30)
 399 #define NV_TX2_VALID            (1<<31)
 400 #define NV_TX2_TSO              (1<<28)
 401 #define NV_TX2_TSO_SHIFT        14
 402 #define NV_TX2_TSO_MAX_SHIFT    14
 403 #define NV_TX2_TSO_MAX_SIZE     (1<<NV_TX2_TSO_MAX_SHIFT)
 404 #define NV_TX2_CHECKSUM_L3      (1<<27)
 405 #define NV_TX2_CHECKSUM_L4      (1<<26)
 406
 407 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
 408
 409 #define NV_RX_DESCRIPTORVALID   (1<<16)
 410 #define NV_RX_MISSEDFRAME       (1<<17)
 411 #define NV_RX_SUBSTRACT1        (1<<18)
 412 #define NV_RX_ERROR1            (1<<23)
 413 #define NV_RX_ERROR2            (1<<24)
 414 #define NV_RX_ERROR3            (1<<25)
 415 #define NV_RX_ERROR4            (1<<26)
 416 #define NV_RX_CRCERR            (1<<27)
 417 #define NV_RX_OVERFLOW          (1<<28)
 418 #define NV_RX_FRAMINGERR        (1<<29)
 419 #define NV_RX_ERROR             (1<<30)
 420 #define NV_RX_AVAIL             (1<<31)
 421 #define NV_RX_ERROR_MASK        (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4|NV_RX_CRCERR|NV_RX_OVERFLOW|NV_RX_FRAMINGERR)
 422
 423 #define NV_RX2_CHECKSUMMASK     (0x1C000000)
 424 #define NV_RX2_CHECKSUM_IP      (0x10000000)
 425 #define NV_RX2_CHECKSUM_IP_TCP  (0x14000000)
 426 #define NV_RX2_CHECKSUM_IP_UDP  (0x18000000)
 427 #define NV_RX2_DESCRIPTORVALID  (1<<29)
 428 #define NV_RX2_SUBSTRACT1       (1<<25)
 429 #define NV_RX2_ERROR1           (1<<18)
 430 #define NV_RX2_ERROR2           (1<<19)
 431 #define NV_RX2_ERROR3           (1<<20)
 432 #define NV_RX2_ERROR4           (1<<21)
 433 #define NV_RX2_CRCERR           (1<<22)
 434 #define NV_RX2_OVERFLOW         (1<<23)
 435 #define NV_RX2_FRAMINGERR       (1<<24)
 436 /* error and avail are the same for both */
 437 #define NV_RX2_ERROR            (1<<30)
 438 #define NV_RX2_AVAIL            (1<<31)
 439 #define NV_RX2_ERROR_MASK       (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3|NV_RX2_ERROR4|NV_RX2_CRCERR|NV_RX2_OVERFLOW|NV_RX2_FRAMINGERR)
 440
 441 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
 442 #define NV_RX3_VLAN_TAG_MASK    (0x0000FFFF)
 443
 444 /* Miscellaneous hardware related defines: */
 445 #define NV_PCI_REGSZ_VER1       0x270
 446 #define NV_PCI_REGSZ_VER2       0x2d4
 447 #define NV_PCI_REGSZ_VER3       0x604
 448 #define NV_PCI_REGSZ_MAX        0x604
 449
 450 /* various timeout delays: all in usec */
 451 #define NV_TXRX_RESET_DELAY     4
 452 #define NV_TXSTOP_DELAY1        10
 453 #define NV_TXSTOP_DELAY1MAX     500000
 454 #define NV_TXSTOP_DELAY2        100
 455 #define NV_RXSTOP_DELAY1        10
 456 #define NV_RXSTOP_DELAY1MAX     500000
 457 #define NV_RXSTOP_DELAY2        100
 458 #define NV_SETUP5_DELAY         5
 459 #define NV_SETUP5_DELAYMAX      50000
 460 #define NV_POWERUP_DELAY        5
 461 #define NV_POWERUP_DELAYMAX     5000
 462 #define NV_MIIBUSY_DELAY        50
 463 #define NV_MIIPHY_DELAY 10
 464 #define NV_MIIPHY_DELAYMAX      10000
 465 #define NV_MAC_RESET_DELAY      64
 466
 467 #define NV_WAKEUPPATTERNS       5
 468 #define NV_WAKEUPMASKENTRIES    4
 469
 470 /* General driver defaults */
 471 #define NV_WATCHDOG_TIMEO       (5*HZ)
 472
 473 #define RX_RING_DEFAULT         512
 474 #define TX_RING_DEFAULT         256
 475 #define RX_RING_MIN             128
 476 #define TX_RING_MIN             64
 477 #define RING_MAX_DESC_VER_1     1024
 478 #define RING_MAX_DESC_VER_2_3   16384
 479
 480 /* rx/tx mac addr + type + vlan + align + slack*/
 481 #define NV_RX_HEADERS           (64)
 482 /* even more slack. */
 483 #define NV_RX_ALLOC_PAD         (64)
 484
 485 /* maximum mtu size */
 486 #define NV_PKTLIMIT_1   ETH_DATA_LEN    /* hard limit not known */
 487 #define NV_PKTLIMIT_2   9100    /* Actual limit according to NVidia: 9202 */
 488
 489 #define OOM_REFILL      (1+HZ/20)
 490 #define POLL_WAIT       (1+HZ/100)
 491 #define LINK_TIMEOUT    (3*HZ)
 492 #define STATS_INTERVAL  (10*HZ)
 493
 494 /*
 495  * desc_ver values:
 496  * The nic supports three different descriptor types:
 497  * - DESC_VER_1: Original
 498  * - DESC_VER_2: support for jumbo frames.
 499  * - DESC_VER_3: 64-bit format.
 500  */
 501 #define DESC_VER_1      1
 502 #define DESC_VER_2      2
 503 #define DESC_VER_3      3
 504
 505 /* PHY defines */
 506 #define PHY_OUI_MARVELL         0x5043
 507 #define PHY_OUI_CICADA          0x03f1
 508 #define PHY_OUI_VITESSE         0x01c1
 509 #define PHY_OUI_REALTEK         0x0732
 510 #define PHY_OUI_REALTEK2        0x0020
 511 #define PHYID1_OUI_MASK 0x03ff
 512 #define PHYID1_OUI_SHFT 6
 513 #define PHYID2_OUI_MASK 0xfc00
 514 #define PHYID2_OUI_SHFT 10
 515 #define PHYID2_MODEL_MASK               0x03f0
 516 #define PHY_MODEL_REALTEK_8211          0x0110
 517 #define PHY_REV_MASK                    0x0001
 518 #define PHY_REV_REALTEK_8211B           0x0000
 519 #define PHY_REV_REALTEK_8211C           0x0001
 520 #define PHY_MODEL_REALTEK_8201          0x0200
 521 #define PHY_MODEL_MARVELL_E3016         0x0220
 522 #define PHY_MARVELL_E3016_INITMASK      0x0300
 523 #define PHY_CICADA_INIT1        0x0f000
 524 #define PHY_CICADA_INIT2        0x0e00
 525 #define PHY_CICADA_INIT3        0x01000
 526 #define PHY_CICADA_INIT4        0x0200
 527 #define PHY_CICADA_INIT5        0x0004
 528 #define PHY_CICADA_INIT6        0x02000
 529 #define PHY_VITESSE_INIT_REG1   0x1f
 530 #define PHY_VITESSE_INIT_REG2   0x10
 531 #define PHY_VITESSE_INIT_REG3   0x11
 532 #define PHY_VITESSE_INIT_REG4   0x12
 533 #define PHY_VITESSE_INIT_MSK1   0xc
 534 #define PHY_VITESSE_INIT_MSK2   0x0180
 535 #define PHY_VITESSE_INIT1       0x52b5
 536 #define PHY_VITESSE_INIT2       0xaf8a
 537 #define PHY_VITESSE_INIT3       0x8
 538 #define PHY_VITESSE_INIT4       0x8f8a
 539 #define PHY_VITESSE_INIT5       0xaf86
 540 #define PHY_VITESSE_INIT6       0x8f86
 541 #define PHY_VITESSE_INIT7       0xaf82
 542 #define PHY_VITESSE_INIT8       0x0100
 543 #define PHY_VITESSE_INIT9       0x8f82
 544 #define PHY_VITESSE_INIT10      0x0
 545 #define PHY_REALTEK_INIT_REG1   0x1f
 546 #define PHY_REALTEK_INIT_REG2   0x19
 547 #define PHY_REALTEK_INIT_REG3   0x13
 548 #define PHY_REALTEK_INIT_REG4   0x14
 549 #define PHY_REALTEK_INIT_REG5   0x18
 550 #define PHY_REALTEK_INIT_REG6   0x11
 551 #define PHY_REALTEK_INIT_REG7   0x01
 552 #define PHY_REALTEK_INIT1       0x0000
 553 #define PHY_REALTEK_INIT2       0x8e00
 554 #define PHY_REALTEK_INIT3       0x0001
 555 #define PHY_REALTEK_INIT4       0xad17
 556 #define PHY_REALTEK_INIT5       0xfb54
 557 #define PHY_REALTEK_INIT6       0xf5c7
 558 #define PHY_REALTEK_INIT7       0x1000
 559 #define PHY_REALTEK_INIT8       0x0003
 560 #define PHY_REALTEK_INIT9       0x0008
 561 #define PHY_REALTEK_INIT10      0x0005
 562 #define PHY_REALTEK_INIT11      0x0200
 563 #define PHY_REALTEK_INIT_MSK1   0x0003
 564
 565 #define PHY_GIGABIT     0x0100
 566
 567 #define PHY_TIMEOUT     0x1
 568 #define PHY_ERROR       0x2
 569
 570 #define PHY_100 0x1
 571 #define PHY_1000        0x2
 572 #define PHY_HALF        0x100
 573
 574 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
 575 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
 576 #define NV_PAUSEFRAME_RX_ENABLE  0x0004
 577 #define NV_PAUSEFRAME_TX_ENABLE  0x0008
 578 #define NV_PAUSEFRAME_RX_REQ     0x0010
 579 #define NV_PAUSEFRAME_TX_REQ     0x0020
 580 #define NV_PAUSEFRAME_AUTONEG    0x0040
 581
 582 /* MSI/MSI-X defines */
 583 #define NV_MSI_X_MAX_VECTORS  8
 584 #define NV_MSI_X_VECTORS_MASK 0x000f
 585 #define NV_MSI_CAPABLE        0x0010
 586 #define NV_MSI_X_CAPABLE      0x0020
 587 #define NV_MSI_ENABLED        0x0040
 588 #define NV_MSI_X_ENABLED      0x0080
 589
 590 #define NV_MSI_X_VECTOR_ALL   0x0
 591 #define NV_MSI_X_VECTOR_RX    0x0
 592 #define NV_MSI_X_VECTOR_TX    0x1
 593 #define NV_MSI_X_VECTOR_OTHER 0x2
 594
 595 #define NV_MSI_PRIV_OFFSET 0x68
 596 #define NV_MSI_PRIV_VALUE  0xffffffff
 597
 598 #define NV_RESTART_TX         0x1
 599 #define NV_RESTART_RX         0x2
 600
 601 #define NV_TX_LIMIT_COUNT     16
 602
 603 #define NV_DYNAMIC_THRESHOLD        4
 604 #define NV_DYNAMIC_MAX_QUIET_COUNT  2048
 605
 606 /* statistics */
 607 struct nv_ethtool_str {
 608         char name[ETH_GSTRING_LEN];
 609 };
 610
 611 static const struct nv_ethtool_str nv_estats_str[] = {
 612         { "tx_bytes" }, /* includes Ethernet FCS CRC */
 613         { "tx_zero_rexmt" },
 614         { "tx_one_rexmt" },
 615         { "tx_many_rexmt" },
 616         { "tx_late_collision" },
 617         { "tx_fifo_errors" },
 618         { "tx_carrier_errors" },
 619         { "tx_excess_deferral" },
 620         { "tx_retry_error" },
 621         { "rx_frame_error" },
 622         { "rx_extra_byte" },
 623         { "rx_late_collision" },
 624         { "rx_runt" },
 625         { "rx_frame_too_long" },
 626         { "rx_over_errors" },
 627         { "rx_crc_errors" },
 628         { "rx_frame_align_error" },
 629         { "rx_length_error" },
 630         { "rx_unicast" },
 631         { "rx_multicast" },
 632         { "rx_broadcast" },
 633         { "rx_packets" },
 634         { "rx_errors_total" },
 635         { "tx_errors_total" },
 636
 637         /* version 2 stats */
 638         { "tx_deferral" },
 639         { "tx_packets" },
 640         { "rx_bytes" }, /* includes Ethernet FCS CRC */
 641         { "tx_pause" },
 642         { "rx_pause" },
 643         { "rx_drop_frame" },
 644
 645         /* version 3 stats */
 646         { "tx_unicast" },
 647         { "tx_multicast" },
 648         { "tx_broadcast" }
 649 };
 650
 651 struct nv_ethtool_stats {
 652         u64 tx_bytes; /* should be ifconfig->tx_bytes + 4*tx_packets */
 653         u64 tx_zero_rexmt;
 654         u64 tx_one_rexmt;
 655         u64 tx_many_rexmt;
 656         u64 tx_late_collision;
 657         u64 tx_fifo_errors;
 658         u64 tx_carrier_errors;
 659         u64 tx_excess_deferral;
 660         u64 tx_retry_error;
 661         u64 rx_frame_error;
 662         u64 rx_extra_byte;
 663         u64 rx_late_collision;
 664         u64 rx_runt;
 665         u64 rx_frame_too_long;
 666         u64 rx_over_errors;
 667         u64 rx_crc_errors;
 668         u64 rx_frame_align_error;
 669         u64 rx_length_error;
 670         u64 rx_unicast;
 671         u64 rx_multicast;
 672         u64 rx_broadcast;
 673         u64 rx_packets; /* should be ifconfig->rx_packets */
 674         u64 rx_errors_total;
 675         u64 tx_errors_total;
 676
 677         /* version 2 stats */
 678         u64 tx_deferral;
 679         u64 tx_packets; /* should be ifconfig->tx_packets */
 680         u64 rx_bytes;   /* should be ifconfig->rx_bytes + 4*rx_packets */
 681         u64 tx_pause;
 682         u64 rx_pause;
 683         u64 rx_drop_frame;
 684
 685         /* version 3 stats */
 686         u64 tx_unicast;
 687         u64 tx_multicast;
 688         u64 tx_broadcast;
 689 };
 690
 691 #define NV_DEV_STATISTICS_V3_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
 692 #define NV_DEV_STATISTICS_V2_COUNT (NV_DEV_STATISTICS_V3_COUNT - 3)
 693 #define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
 694
 695 /* diagnostics */
 696 #define NV_TEST_COUNT_BASE 3
 697 #define NV_TEST_COUNT_EXTENDED 4
 698
 699 static const struct nv_ethtool_str nv_etests_str[] = {
 700         { "link      (online/offline)" },
 701         { "register  (offline)       " },
 702         { "interrupt (offline)       " },
 703         { "loopback  (offline)       " }
 704 };
 705
 706 struct register_test {
 707         __u32 reg;
 708         __u32 mask;
 709 };
 710
 711 static const struct register_test nv_registers_test[] = {
 712         { NvRegUnknownSetupReg6, 0x01 },
 713         { NvRegMisc1, 0x03c },
 714         { NvRegOffloadConfig, 0x03ff },
 715         { NvRegMulticastAddrA, 0xffffffff },
 716         { NvRegTxWatermark, 0x0ff },
 717         { NvRegWakeUpFlags, 0x07777 },
 718         { 0, 0 }
 719 };
 720
 721 struct nv_skb_map {
 722         struct sk_buff *skb;
 723         dma_addr_t dma;
 724         unsigned int dma_len:31;
 725         unsigned int dma_single:1;
 726         struct ring_desc_ex *first_tx_desc;
 727         struct nv_skb_map *next_tx_ctx;
 728 };
 729
 730 /*
 731  * SMP locking:
 732  * All hardware access under netdev_priv(dev)->lock, except the performance
 733  * critical parts:
 734  * - rx is (pseudo-) lockless: it relies on the single-threading provided
 735  *      by the arch code for interrupts.
 736  * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
 737  *      needs netdev_priv(dev)->lock :-(
 738  * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
 739  */
 740
 741 /* in dev: base, irq */
 742 struct fe_priv {
 743         spinlock_t lock;
 744
 745         struct net_device *dev;
 746         struct napi_struct napi;
 747
 748         /* General data:
 749          * Locking: spin_lock(&np->lock); */
 750         struct nv_ethtool_stats estats;
 751         int in_shutdown;
 752         u32 linkspeed;
 753         int duplex;
 754         int autoneg;
 755         int fixed_mode;
 756         int phyaddr;
 757         int wolenabled;
 758         unsigned int phy_oui;
 759         unsigned int phy_model;
 760         unsigned int phy_rev;
 761         u16 gigabit;
 762         int intr_test;
 763         int recover_error;
 764         int quiet_count;
 765
 766         /* General data: RO fields */
 767         dma_addr_t ring_addr;
 768         struct pci_dev *pci_dev;
 769         u32 orig_mac[2];
 770         u32 events;
 771         u32 irqmask;
 772         u32 desc_ver;
 773         u32 txrxctl_bits;
 774         u32 vlanctl_bits;
 775         u32 driver_data;
 776         u32 device_id;
 777         u32 register_size;
 778         u32 mac_in_use;
 779         int mgmt_version;
 780         int mgmt_sema;
 781
 782         void __iomem *base;
 783
 784         /* rx specific fields.
 785          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 786          */
 787         union ring_type get_rx, put_rx, first_rx, last_rx;
 788         struct nv_skb_map *get_rx_ctx, *put_rx_ctx;
 789         struct nv_skb_map *first_rx_ctx, *last_rx_ctx;
 790         struct nv_skb_map *rx_skb;
 791
 792         union ring_type rx_ring;
 793         unsigned int rx_buf_sz;
 794         unsigned int pkt_limit;
 795         struct timer_list oom_kick;
 796         struct timer_list nic_poll;
 797         struct timer_list stats_poll;
 798         u32 nic_poll_irq;
 799         int rx_ring_size;
 800
 801         /* media detection workaround.
 802          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 803          */
 804         int need_linktimer;
 805         unsigned long link_timeout;
 806         /*
 807          * tx specific fields.
 808          */
 809         union ring_type get_tx, put_tx, first_tx, last_tx;
 810         struct nv_skb_map *get_tx_ctx, *put_tx_ctx;
 811         struct nv_skb_map *first_tx_ctx, *last_tx_ctx;
 812         struct nv_skb_map *tx_skb;
 813
 814         union ring_type tx_ring;
 815         u32 tx_flags;
 816         int tx_ring_size;
 817         int tx_limit;
 818         u32 tx_pkts_in_progress;
 819         struct nv_skb_map *tx_change_owner;
 820         struct nv_skb_map *tx_end_flip;
 821         int tx_stop;
 822
 823         /* msi/msi-x fields */
 824         u32 msi_flags;
 825         struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
 826
 827         /* flow control */
 828         u32 pause_flags;
 829
 830         /* power saved state */
 831         u32 saved_config_space[NV_PCI_REGSZ_MAX/4];
 832
 833         /* for different msi-x irq type */
 834         char name_rx[IFNAMSIZ + 3];       /* -rx    */
 835         char name_tx[IFNAMSIZ + 3];       /* -tx    */
 836         char name_other[IFNAMSIZ + 6];    /* -other */
 837 };
 838
 839 /*
 840  * Maximum number of loops until we assume that a bit in the irq mask
 841  * is stuck. Overridable with module param.
 842  */
 843 static int max_interrupt_work = 4;
 844
 845 /*
 846  * Optimization can be either throuput mode or cpu mode
 847  *
 848  * Throughput Mode: Every tx and rx packet will generate an interrupt.
 849  * CPU Mode: Interrupts are controlled by a timer.
 850  */
 851 enum {
 852         NV_OPTIMIZATION_MODE_THROUGHPUT,
 853         NV_OPTIMIZATION_MODE_CPU,
 854         NV_OPTIMIZATION_MODE_DYNAMIC
 855 };
 856 static int optimization_mode = NV_OPTIMIZATION_MODE_DYNAMIC;
 857
 858 /*
 859  * Poll interval for timer irq
 860  *
 861  * This interval determines how frequent an interrupt is generated.
 862  * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
 863  * Min = 0, and Max = 65535
 864  */
 865 static int poll_interval = -1;
 866
 867 /*
 868  * MSI interrupts
 869  */
 870 enum {
 871         NV_MSI_INT_DISABLED,
 872         NV_MSI_INT_ENABLED
 873 };
 874 static int msi = NV_MSI_INT_ENABLED;
 875
 876 /*
 877  * MSIX interrupts
 878  */
 879 enum {
 880         NV_MSIX_INT_DISABLED,
 881         NV_MSIX_INT_ENABLED
 882 };
 883 static int msix = NV_MSIX_INT_ENABLED;
 884
 885 /*
 886  * DMA 64bit
 887  */
 888 enum {
 889         NV_DMA_64BIT_DISABLED,
 890         NV_DMA_64BIT_ENABLED
 891 };
 892 static int dma_64bit = NV_DMA_64BIT_ENABLED;
 893
 894 /*
 895  * Debug output control for tx_timeout
 896  */
 897 static bool debug_tx_timeout = false;
 898
 899 /*
 900  * Crossover Detection
 901  * Realtek 8201 phy + some OEM boards do not work properly.
 902  */
 903 enum {
 904         NV_CROSSOVER_DETECTION_DISABLED,
 905         NV_CROSSOVER_DETECTION_ENABLED
 906 };
 907 static int phy_cross = NV_CROSSOVER_DETECTION_DISABLED;
 908
 909 /*
 910  * Power down phy when interface is down (persists through reboot;
 911  * older Linux and other OSes may not power it up again)
 912  */
 913 static int phy_power_down;
 914
 915 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
 916 {
 917         return netdev_priv(dev);
 918 }
 919
 920 static inline u8 __iomem *get_hwbase(struct net_device *dev)
 921 {
 922         return ((struct fe_priv *)netdev_priv(dev))->base;
 923 }
 924
 925 static inline void pci_push(u8 __iomem *base)
 926 {
 927         /* force out pending posted writes */
 928         readl(base);
 929 }
 930
 931 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
 932 {
 933         return le32_to_cpu(prd->flaglen)
 934                 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
 935 }
 936
 937 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
 938 {
 939         return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
 940 }
 941
 942 static bool nv_optimized(struct fe_priv *np)
 943 {
 944         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
 945                 return false;
 946         return true;
 947 }
 948
 949 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
 950                      int delay, int delaymax)
 951 {
 952         u8 __iomem *base = get_hwbase(dev);
 953
 954         pci_push(base);
 955         do {
 956                 udelay(delay);
 957                 delaymax -= delay;
 958                 if (delaymax < 0)
 959                         return 1;
 960         } while ((readl(base + offset) & mask) != target);
 961         return 0;
 962 }
 963
 964 #define NV_SETUP_RX_RING 0x01
 965 #define NV_SETUP_TX_RING 0x02
 966
 967 static inline u32 dma_low(dma_addr_t addr)
 968 {
 969         return addr;
 970 }
 971
 972 static inline u32 dma_high(dma_addr_t addr)
 973 {
 974         return addr>>31>>1;     /* 0 if 32bit, shift down by 32 if 64bit */
 975 }
 976
 977 static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
 978 {
 979         struct fe_priv *np = get_nvpriv(dev);
 980         u8 __iomem *base = get_hwbase(dev);
 981
 982         if (!nv_optimized(np)) {
 983                 if (rxtx_flags & NV_SETUP_RX_RING)
 984                         writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
 985                 if (rxtx_flags & NV_SETUP_TX_RING)
 986                         writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
 987         } else {
 988                 if (rxtx_flags & NV_SETUP_RX_RING) {
 989                         writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
 990                         writel(dma_high(np->ring_addr), base + NvRegRxRingPhysAddrHigh);
 991                 }
 992                 if (rxtx_flags & NV_SETUP_TX_RING) {
 993                         writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
 994                         writel(dma_high(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddrHigh);
 995                 }
 996         }
 997 }
 998
 999 static void free_rings(struct net_device *dev)
1000 {
1001         struct fe_priv *np = get_nvpriv(dev);
1002
1003         if (!nv_optimized(np)) {
1004                 if (np->rx_ring.orig)
1005                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
1006                                             np->rx_ring.orig, np->ring_addr);
1007         } else {
1008                 if (np->rx_ring.ex)
1009                         pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
1010                                             np->rx_ring.ex, np->ring_addr);
1011         }
1012         kfree(np->rx_skb);
1013         kfree(np->tx_skb);
1014 }
1015
1016 static int using_multi_irqs(struct net_device *dev)
1017 {
1018         struct fe_priv *np = get_nvpriv(dev);
1019
1020         if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
1021             ((np->msi_flags & NV_MSI_X_ENABLED) &&
1022              ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
1023                 return 0;
1024         else
1025                 return 1;
1026 }
1027
1028 static void nv_txrx_gate(struct net_device *dev, bool gate)
1029 {
1030         struct fe_priv *np = get_nvpriv(dev);
1031         u8 __iomem *base = get_hwbase(dev);
1032         u32 powerstate;
1033
1034         if (!np->mac_in_use &&
1035             (np->driver_data & DEV_HAS_POWER_CNTRL)) {
1036                 powerstate = readl(base + NvRegPowerState2);
1037                 if (gate)
1038                         powerstate |= NVREG_POWERSTATE2_GATE_CLOCKS;
1039                 else
1040                         powerstate &= ~NVREG_POWERSTATE2_GATE_CLOCKS;
1041                 writel(powerstate, base + NvRegPowerState2);
1042         }
1043 }
1044
1045 static void nv_enable_irq(struct net_device *dev)
1046 {
1047         struct fe_priv *np = get_nvpriv(dev);
1048
1049         if (!using_multi_irqs(dev)) {
1050                 if (np->msi_flags & NV_MSI_X_ENABLED)
1051                         enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1052                 else
1053                         enable_irq(np->pci_dev->irq);
1054         } else {
1055                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1056                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1057                 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1058         }
1059 }
1060
1061 static void nv_disable_irq(struct net_device *dev)
1062 {
1063         struct fe_priv *np = get_nvpriv(dev);
1064
1065         if (!using_multi_irqs(dev)) {
1066                 if (np->msi_flags & NV_MSI_X_ENABLED)
1067                         disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1068                 else
1069                         disable_irq(np->pci_dev->irq);
1070         } else {
1071                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1072                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1073                 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1074         }
1075 }
1076
1077 /* In MSIX mode, a write to irqmask behaves as XOR */
1078 static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
1079 {
1080         u8 __iomem *base = get_hwbase(dev);
1081
1082         writel(mask, base + NvRegIrqMask);
1083 }
1084
1085 static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
1086 {
1087         struct fe_priv *np = get_nvpriv(dev);
1088         u8 __iomem *base = get_hwbase(dev);
1089
1090         if (np->msi_flags & NV_MSI_X_ENABLED) {
1091                 writel(mask, base + NvRegIrqMask);
1092         } else {
1093                 if (np->msi_flags & NV_MSI_ENABLED)
1094                         writel(0, base + NvRegMSIIrqMask);
1095                 writel(0, base + NvRegIrqMask);
1096         }
1097 }
1098
1099 static void nv_napi_enable(struct net_device *dev)
1100 {
1101         struct fe_priv *np = get_nvpriv(dev);
1102
1103         napi_enable(&np->napi);
1104 }
1105
1106 static void nv_napi_disable(struct net_device *dev)
1107 {
1108         struct fe_priv *np = get_nvpriv(dev);
1109
1110         napi_disable(&np->napi);
1111 }
1112
1113 #define MII_READ        (-1)
1114 /* mii_rw: read/write a register on the PHY.
1115  *
1116  * Caller must guarantee serialization
1117  */
1118 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
1119 {
1120         u8 __iomem *base = get_hwbase(dev);
1121         u32 reg;
1122         int retval;
1123
1124         writel(NVREG_MIISTAT_MASK_RW, base + NvRegMIIStatus);
1125
1126         reg = readl(base + NvRegMIIControl);
1127         if (reg & NVREG_MIICTL_INUSE) {
1128                 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1129                 udelay(NV_MIIBUSY_DELAY);
1130         }
1131
1132         reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
1133         if (value != MII_READ) {
1134                 writel(value, base + NvRegMIIData);
1135                 reg |= NVREG_MIICTL_WRITE;
1136         }
1137         writel(reg, base + NvRegMIIControl);
1138
1139         if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
1140                         NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX)) {
1141                 retval = -1;
1142         } else if (value != MII_READ) {
1143                 /* it was a write operation - fewer failures are detectable */
1144                 retval = 0;
1145         } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1146                 retval = -1;
1147         } else {
1148                 retval = readl(base + NvRegMIIData);
1149         }
1150
1151         return retval;
1152 }
1153
1154 static int phy_reset(struct net_device *dev, u32 bmcr_setup)
1155 {
1156         struct fe_priv *np = netdev_priv(dev);
1157         u32 miicontrol;
1158         unsigned int tries = 0;
1159
1160         miicontrol = BMCR_RESET | bmcr_setup;
1161         if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol))
1162                 return -1;
1163
1164         /* wait for 500ms */
1165         msleep(500);
1166
1167         /* must wait till reset is deasserted */
1168         while (miicontrol & BMCR_RESET) {
1169                 usleep_range(10000, 20000);
1170                 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1171                 /* FIXME: 100 tries seem excessive */
1172                 if (tries++ > 100)
1173                         return -1;
1174         }
1175         return 0;
1176 }
1177
1178 static int init_realtek_8211b(struct net_device *dev, struct fe_priv *np)
1179 {
1180         static const struct {
1181                 int reg;
1182                 int init;
1183         } ri[] = {
1184                 { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 },
1185                 { PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2 },
1186                 { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3 },
1187                 { PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4 },
1188                 { PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5 },
1189                 { PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6 },
1190                 { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 },
1191         };
1192         int i;
1193
1194         for (i = 0; i < ARRAY_SIZE(ri); i++) {
1195                 if (mii_rw(dev, np->phyaddr, ri[i].reg, ri[i].init))
1196                         return PHY_ERROR;
1197         }
1198
1199         return 0;
1200 }
1201
1202 static int init_realtek_8211c(struct net_device *dev, struct fe_priv *np)
1203 {
1204         u32 reg;
1205         u8 __iomem *base = get_hwbase(dev);
1206         u32 powerstate = readl(base + NvRegPowerState2);
1207
1208         /* need to perform hw phy reset */
1209         powerstate |= NVREG_POWERSTATE2_PHY_RESET;
1210         writel(powerstate, base + NvRegPowerState2);
1211         msleep(25);
1212
1213         powerstate &= ~NVREG_POWERSTATE2_PHY_RESET;
1214         writel(powerstate, base + NvRegPowerState2);
1215         msleep(25);
1216
1217         reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1218         reg |= PHY_REALTEK_INIT9;
1219         if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg))
1220                 return PHY_ERROR;
1221         if (mii_rw(dev, np->phyaddr,
1222                    PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT10))
1223                 return PHY_ERROR;
1224         reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ);
1225         if (!(reg & PHY_REALTEK_INIT11)) {
1226                 reg |= PHY_REALTEK_INIT11;
1227                 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg))
1228                         return PHY_ERROR;
1229         }
1230         if (mii_rw(dev, np->phyaddr,
1231                    PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1))
1232                 return PHY_ERROR;
1233
1234         return 0;
1235 }
1236
1237 static int init_realtek_8201(struct net_device *dev, struct fe_priv *np)
1238 {
1239         u32 phy_reserved;
1240
1241         if (np->driver_data & DEV_NEED_PHY_INIT_FIX) {
1242                 phy_reserved = mii_rw(dev, np->phyaddr,
1243                                       PHY_REALTEK_INIT_REG6, MII_READ);
1244                 phy_reserved |= PHY_REALTEK_INIT7;
1245                 if (mii_rw(dev, np->phyaddr,
1246                            PHY_REALTEK_INIT_REG6, phy_reserved))
1247                         return PHY_ERROR;
1248         }
1249
1250         return 0;
1251 }
1252
1253 static int init_realtek_8201_cross(struct net_device *dev, struct fe_priv *np)
1254 {
1255         u32 phy_reserved;
1256
1257         if (phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
1258                 if (mii_rw(dev, np->phyaddr,
1259                            PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3))
1260                         return PHY_ERROR;
1261                 phy_reserved = mii_rw(dev, np->phyaddr,
1262                                       PHY_REALTEK_INIT_REG2, MII_READ);
1263                 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
1264                 phy_reserved |= PHY_REALTEK_INIT3;
1265                 if (mii_rw(dev, np->phyaddr,
1266                            PHY_REALTEK_INIT_REG2, phy_reserved))
1267                         return PHY_ERROR;
1268                 if (mii_rw(dev, np->phyaddr,
1269                            PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1))
1270                         return PHY_ERROR;
1271         }
1272
1273         return 0;
1274 }
1275
1276 static int init_cicada(struct net_device *dev, struct fe_priv *np,
1277                        u32 phyinterface)
1278 {
1279         u32 phy_reserved;
1280
1281         if (phyinterface & PHY_RGMII) {
1282                 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1283                 phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2);
1284                 phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4);
1285                 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved))
1286                         return PHY_ERROR;
1287                 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1288                 phy_reserved |= PHY_CICADA_INIT5;
1289                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved))
1290                         return PHY_ERROR;
1291         }
1292         phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1293         phy_reserved |= PHY_CICADA_INIT6;
1294         if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved))
1295                 return PHY_ERROR;
1296
1297         return 0;
1298 }
1299
1300 static int init_vitesse(struct net_device *dev, struct fe_priv *np)
1301 {
1302         u32 phy_reserved;
1303
1304         if (mii_rw(dev, np->phyaddr,
1305                    PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1))
1306                 return PHY_ERROR;
1307         if (mii_rw(dev, np->phyaddr,
1308                    PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2))
1309                 return PHY_ERROR;
1310         phy_reserved = mii_rw(dev, np->phyaddr,
1311                               PHY_VITESSE_INIT_REG4, MII_READ);
1312         if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1313                 return PHY_ERROR;
1314         phy_reserved = mii_rw(dev, np->phyaddr,
1315                               PHY_VITESSE_INIT_REG3, MII_READ);
1316         phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1317         phy_reserved |= PHY_VITESSE_INIT3;
1318         if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1319                 return PHY_ERROR;
1320         if (mii_rw(dev, np->phyaddr,
1321                    PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4))
1322                 return PHY_ERROR;
1323         if (mii_rw(dev, np->phyaddr,
1324                    PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5))
1325                 return PHY_ERROR;
1326         phy_reserved = mii_rw(dev, np->phyaddr,
1327                               PHY_VITESSE_INIT_REG4, MII_READ);
1328         phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1329         phy_reserved |= PHY_VITESSE_INIT3;
1330         if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1331                 return PHY_ERROR;
1332         phy_reserved = mii_rw(dev, np->phyaddr,
1333                               PHY_VITESSE_INIT_REG3, MII_READ);
1334         if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1335                 return PHY_ERROR;
1336         if (mii_rw(dev, np->phyaddr,
1337                    PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6))
1338                 return PHY_ERROR;
1339         if (mii_rw(dev, np->phyaddr,
1340                    PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7))
1341                 return PHY_ERROR;
1342         phy_reserved = mii_rw(dev, np->phyaddr,
1343                               PHY_VITESSE_INIT_REG4, MII_READ);
1344         if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1345                 return PHY_ERROR;
1346         phy_reserved = mii_rw(dev, np->phyaddr,
1347                               PHY_VITESSE_INIT_REG3, MII_READ);
1348         phy_reserved &= ~PHY_VITESSE_INIT_MSK2;
1349         phy_reserved |= PHY_VITESSE_INIT8;
1350         if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1351                 return PHY_ERROR;
1352         if (mii_rw(dev, np->phyaddr,
1353                    PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9))
1354                 return PHY_ERROR;
1355         if (mii_rw(dev, np->phyaddr,
1356                    PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10))
1357                 return PHY_ERROR;
1358
1359         return 0;
1360 }
1361
1362 static int phy_init(struct net_device *dev)
1363 {
1364         struct fe_priv *np = get_nvpriv(dev);
1365         u8 __iomem *base = get_hwbase(dev);
1366         u32 phyinterface;
1367         u32 mii_status, mii_control, mii_control_1000, reg;
1368
1369         /* phy errata for E3016 phy */
1370         if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1371                 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1372                 reg &= ~PHY_MARVELL_E3016_INITMASK;
1373                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1374                         netdev_info(dev, "%s: phy write to errata reg failed\n",
1375                                     pci_name(np->pci_dev));
1376                         return PHY_ERROR;
1377                 }
1378         }
1379         if (np->phy_oui == PHY_OUI_REALTEK) {
1380                 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1381                     np->phy_rev == PHY_REV_REALTEK_8211B) {
1382                         if (init_realtek_8211b(dev, np)) {
1383                                 netdev_info(dev, "%s: phy init failed\n",
1384                                             pci_name(np->pci_dev));
1385                                 return PHY_ERROR;
1386                         }
1387                 } else if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1388                            np->phy_rev == PHY_REV_REALTEK_8211C) {
1389                         if (init_realtek_8211c(dev, np)) {
1390                                 netdev_info(dev, "%s: phy init failed\n",
1391                                             pci_name(np->pci_dev));
1392                                 return PHY_ERROR;
1393                         }
1394                 } else if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1395                         if (init_realtek_8201(dev, np)) {
1396                                 netdev_info(dev, "%s: phy init failed\n",
1397                                             pci_name(np->pci_dev));
1398                                 return PHY_ERROR;
1399                         }
1400                 }
1401         }
1402
1403         /* set advertise register */
1404         reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1405         reg |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
1406                 ADVERTISE_100HALF | ADVERTISE_100FULL |
1407                 ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
1408         if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1409                 netdev_info(dev, "%s: phy write to advertise failed\n",
1410                             pci_name(np->pci_dev));
1411                 return PHY_ERROR;
1412         }
1413
1414         /* get phy interface type */
1415         phyinterface = readl(base + NvRegPhyInterface);
1416
1417         /* see if gigabit phy */
1418         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1419         if (mii_status & PHY_GIGABIT) {
1420                 np->gigabit = PHY_GIGABIT;
1421                 mii_control_1000 = mii_rw(dev, np->phyaddr,
1422                                           MII_CTRL1000, MII_READ);
1423                 mii_control_1000 &= ~ADVERTISE_1000HALF;
1424                 if (phyinterface & PHY_RGMII)
1425                         mii_control_1000 |= ADVERTISE_1000FULL;
1426                 else
1427                         mii_control_1000 &= ~ADVERTISE_1000FULL;
1428
1429                 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1430                         netdev_info(dev, "%s: phy init failed\n",
1431                                     pci_name(np->pci_dev));
1432                         return PHY_ERROR;
1433                 }
1434         } else
1435                 np->gigabit = 0;
1436
1437         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1438         mii_control |= BMCR_ANENABLE;
1439
1440         if (np->phy_oui == PHY_OUI_REALTEK &&
1441             np->phy_model == PHY_MODEL_REALTEK_8211 &&
1442             np->phy_rev == PHY_REV_REALTEK_8211C) {
1443                 /* start autoneg since we already performed hw reset above */
1444                 mii_control |= BMCR_ANRESTART;
1445                 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1446                         netdev_info(dev, "%s: phy init failed\n",
1447                                     pci_name(np->pci_dev));
1448                         return PHY_ERROR;
1449                 }
1450         } else {
1451                 /* reset the phy
1452                  * (certain phys need bmcr to be setup with reset)
1453                  */
1454                 if (phy_reset(dev, mii_control)) {
1455                         netdev_info(dev, "%s: phy reset failed\n",
1456                                     pci_name(np->pci_dev));
1457                         return PHY_ERROR;
1458                 }
1459         }
1460
1461         /* phy vendor specific configuration */
1462         if ((np->phy_oui == PHY_OUI_CICADA)) {
1463                 if (init_cicada(dev, np, phyinterface)) {
1464                         netdev_info(dev, "%s: phy init failed\n",
1465                                     pci_name(np->pci_dev));
1466                         return PHY_ERROR;
1467                 }
1468         } else if (np->phy_oui == PHY_OUI_VITESSE) {
1469                 if (init_vitesse(dev, np)) {
1470                         netdev_info(dev, "%s: phy init failed\n",
1471                                     pci_name(np->pci_dev));
1472                         return PHY_ERROR;
1473                 }
1474         } else if (np->phy_oui == PHY_OUI_REALTEK) {
1475                 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1476                     np->phy_rev == PHY_REV_REALTEK_8211B) {
1477                         /* reset could have cleared these out, set them back */
1478                         if (init_realtek_8211b(dev, np)) {
1479                                 netdev_info(dev, "%s: phy init failed\n",
1480                                             pci_name(np->pci_dev));
1481                                 return PHY_ERROR;
1482                         }
1483                 } else if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1484                         if (init_realtek_8201(dev, np) ||
1485                             init_realtek_8201_cross(dev, np)) {
1486                                 netdev_info(dev, "%s: phy init failed\n",
1487                                             pci_name(np->pci_dev));
1488                                 return PHY_ERROR;
1489                         }
1490                 }
1491         }
1492
1493         /* some phys clear out pause advertisement on reset, set it back */
1494         mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1495
1496         /* restart auto negotiation, power down phy */
1497         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1498         mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
1499         if (phy_power_down)
1500                 mii_control |= BMCR_PDOWN;
1501         if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control))
1502                 return PHY_ERROR;
1503
1504         return 0;
1505 }
1506
1507 static void nv_start_rx(struct net_device *dev)
1508 {
1509         struct fe_priv *np = netdev_priv(dev);
1510         u8 __iomem *base = get_hwbase(dev);
1511         u32 rx_ctrl = readl(base + NvRegReceiverControl);
1512
1513         /* Already running? Stop it. */
1514         if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
1515                 rx_ctrl &= ~NVREG_RCVCTL_START;
1516                 writel(rx_ctrl, base + NvRegReceiverControl);
1517                 pci_push(base);
1518         }
1519         writel(np->linkspeed, base + NvRegLinkSpeed);
1520         pci_push(base);
1521         rx_ctrl |= NVREG_RCVCTL_START;
1522         if (np->mac_in_use)
1523                 rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
1524         writel(rx_ctrl, base + NvRegReceiverControl);
1525         pci_push(base);
1526 }
1527
1528 static void nv_stop_rx(struct net_device *dev)
1529 {
1530         struct fe_priv *np = netdev_priv(dev);
1531         u8 __iomem *base = get_hwbase(dev);
1532         u32 rx_ctrl = readl(base + NvRegReceiverControl);
1533
1534         if (!np->mac_in_use)
1535                 rx_ctrl &= ~NVREG_RCVCTL_START;
1536         else
1537                 rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
1538         writel(rx_ctrl, base + NvRegReceiverControl);
1539         if (reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1540                       NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX))
1541                 netdev_info(dev, "%s: ReceiverStatus remained busy\n",
1542                             __func__);
1543
1544         udelay(NV_RXSTOP_DELAY2);
1545         if (!np->mac_in_use)
1546                 writel(0, base + NvRegLinkSpeed);
1547 }
1548
1549 static void nv_start_tx(struct net_device *dev)
1550 {
1551         struct fe_priv *np = netdev_priv(dev);
1552         u8 __iomem *base = get_hwbase(dev);
1553         u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1554
1555         tx_ctrl |= NVREG_XMITCTL_START;
1556         if (np->mac_in_use)
1557                 tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
1558         writel(tx_ctrl, base + NvRegTransmitterControl);
1559         pci_push(base);
1560 }
1561
1562 static void nv_stop_tx(struct net_device *dev)
1563 {
1564         struct fe_priv *np = netdev_priv(dev);
1565         u8 __iomem *base = get_hwbase(dev);
1566         u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1567
1568         if (!np->mac_in_use)
1569                 tx_ctrl &= ~NVREG_XMITCTL_START;
1570         else
1571                 tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
1572         writel(tx_ctrl, base + NvRegTransmitterControl);
1573         if (reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1574                       NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX))
1575                 netdev_info(dev, "%s: TransmitterStatus remained busy\n",
1576                             __func__);
1577
1578         udelay(NV_TXSTOP_DELAY2);
1579         if (!np->mac_in_use)
1580                 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
1581                        base + NvRegTransmitPoll);
1582 }
1583
1584 static void nv_start_rxtx(struct net_device *dev)
1585 {
1586         nv_start_rx(dev);
1587         nv_start_tx(dev);
1588 }
1589
1590 static void nv_stop_rxtx(struct net_device *dev)
1591 {
1592         nv_stop_rx(dev);
1593         nv_stop_tx(dev);
1594 }
1595
1596 static void nv_txrx_reset(struct net_device *dev)
1597 {
1598         struct fe_priv *np = netdev_priv(dev);
1599         u8 __iomem *base = get_hwbase(dev);
1600
1601         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1602         pci_push(base);
1603         udelay(NV_TXRX_RESET_DELAY);
1604         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1605         pci_push(base);
1606 }
1607
1608 static void nv_mac_reset(struct net_device *dev)
1609 {
1610         struct fe_priv *np = netdev_priv(dev);
1611         u8 __iomem *base = get_hwbase(dev);
1612         u32 temp1, temp2, temp3;
1613
1614         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1615         pci_push(base);
1616
1617         /* save registers since they will be cleared on reset */
1618         temp1 = readl(base + NvRegMacAddrA);
1619         temp2 = readl(base + NvRegMacAddrB);
1620         temp3 = readl(base + NvRegTransmitPoll);
1621
1622         writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1623         pci_push(base);
1624         udelay(NV_MAC_RESET_DELAY);
1625         writel(0, base + NvRegMacReset);
1626         pci_push(base);
1627         udelay(NV_MAC_RESET_DELAY);
1628
1629         /* restore saved registers */
1630         writel(temp1, base + NvRegMacAddrA);
1631         writel(temp2, base + NvRegMacAddrB);
1632         writel(temp3, base + NvRegTransmitPoll);
1633
1634         writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1635         pci_push(base);
1636 }
1637
1638 static void nv_get_hw_stats(struct net_device *dev)
1639 {
1640         struct fe_priv *np = netdev_priv(dev);
1641         u8 __iomem *base = get_hwbase(dev);
1642
1643         np->estats.tx_bytes += readl(base + NvRegTxCnt);
1644         np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
1645         np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
1646         np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
1647         np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
1648         np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
1649         np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
1650         np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
1651         np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
1652         np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
1653         np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
1654         np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
1655         np->estats.rx_runt += readl(base + NvRegRxRunt);
1656         np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
1657         np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
1658         np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
1659         np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
1660         np->estats.rx_length_error += readl(base + NvRegRxLenErr);
1661         np->estats.rx_unicast += readl(base + NvRegRxUnicast);
1662         np->estats.rx_multicast += readl(base + NvRegRxMulticast);
1663         np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
1664         np->estats.rx_packets =
1665                 np->estats.rx_unicast +
1666                 np->estats.rx_multicast +
1667                 np->estats.rx_broadcast;
1668         np->estats.rx_errors_total =
1669                 np->estats.rx_crc_errors +
1670                 np->estats.rx_over_errors +
1671                 np->estats.rx_frame_error +
1672                 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
1673                 np->estats.rx_late_collision +
1674                 np->estats.rx_runt +
1675                 np->estats.rx_frame_too_long;
1676         np->estats.tx_errors_total =
1677                 np->estats.tx_late_collision +
1678                 np->estats.tx_fifo_errors +
1679                 np->estats.tx_carrier_errors +
1680                 np->estats.tx_excess_deferral +
1681                 np->estats.tx_retry_error;
1682
1683         if (np->driver_data & DEV_HAS_STATISTICS_V2) {
1684                 np->estats.tx_deferral += readl(base + NvRegTxDef);
1685                 np->estats.tx_packets += readl(base + NvRegTxFrame);
1686                 np->estats.rx_bytes += readl(base + NvRegRxCnt);
1687                 np->estats.tx_pause += readl(base + NvRegTxPause);
1688                 np->estats.rx_pause += readl(base + NvRegRxPause);
1689                 np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
1690                 np->estats.rx_errors_total += np->estats.rx_drop_frame;
1691         }
1692
1693         if (np->driver_data & DEV_HAS_STATISTICS_V3) {
1694                 np->estats.tx_unicast += readl(base + NvRegTxUnicast);
1695                 np->estats.tx_multicast += readl(base + NvRegTxMulticast);
1696                 np->estats.tx_broadcast += readl(base + NvRegTxBroadcast);
1697         }
1698 }
1699
1700 /*
1701  * nv_get_stats: dev->get_stats function
1702  * Get latest stats value from the nic.
1703  * Called with read_lock(&dev_base_lock) held for read -
1704  * only synchronized against unregister_netdevice.
1705  */
1706 static struct net_device_stats *nv_get_stats(struct net_device *dev)
1707 {
1708         struct fe_priv *np = netdev_priv(dev);
1709
1710         /* If the nic supports hw counters then retrieve latest values */
1711         if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3)) {
1712                 nv_get_hw_stats(dev);
1713
1714                 /*
1715                  * Note: because HW stats are not always available and
1716                  * for consistency reasons, the following ifconfig
1717                  * stats are managed by software: rx_bytes, tx_bytes,
1718                  * rx_packets and tx_packets. The related hardware
1719                  * stats reported by ethtool should be equivalent to
1720                  * these ifconfig stats, with 4 additional bytes per
1721                  * packet (Ethernet FCS CRC).
1722                  */
1723
1724                 /* copy to net_device stats */
1725                 dev->stats.tx_fifo_errors = np->estats.tx_fifo_errors;
1726                 dev->stats.tx_carrier_errors = np->estats.tx_carrier_errors;
1727                 dev->stats.rx_crc_errors = np->estats.rx_crc_errors;
1728                 dev->stats.rx_over_errors = np->estats.rx_over_errors;
1729                 dev->stats.rx_fifo_errors = np->estats.rx_drop_frame;
1730                 dev->stats.rx_errors = np->estats.rx_errors_total;
1731                 dev->stats.tx_errors = np->estats.tx_errors_total;
1732         }
1733
1734         return &dev->stats;
1735 }
1736
1737 /*
1738  * nv_alloc_rx: fill rx ring entries.
1739  * Return 1 if the allocations for the skbs failed and the
1740  * rx engine is without Available descriptors
1741  */
1742 static int nv_alloc_rx(struct net_device *dev)
1743 {
1744         struct fe_priv *np = netdev_priv(dev);
1745         struct ring_desc *less_rx;
1746
1747         less_rx = np->get_rx.orig;
1748         if (less_rx-- == np->first_rx.orig)
1749                 less_rx = np->last_rx.orig;
1750
1751         while (np->put_rx.orig != less_rx) {
1752                 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1753                 if (skb) {
1754                         np->put_rx_ctx->skb = skb;
1755                         np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1756                                                              skb->data,
1757                                                              skb_tailroom(skb),
1758                                                              PCI_DMA_FROMDEVICE);
1759                         np->put_rx_ctx->dma_len = skb_tailroom(skb);
1760                         np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma);
1761                         wmb();
1762                         np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
1763                         if (unlikely(np->put_rx.orig++ == np->last_rx.orig))
1764                                 np->put_rx.orig = np->first_rx.orig;
1765                         if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1766                                 np->put_rx_ctx = np->first_rx_ctx;
1767                 } else
1768                         return 1;
1769         }
1770         return 0;
1771 }
1772
1773 static int nv_alloc_rx_optimized(struct net_device *dev)
1774 {
1775         struct fe_priv *np = netdev_priv(dev);
1776         struct ring_desc_ex *less_rx;
1777
1778         less_rx = np->get_rx.ex;
1779         if (less_rx-- == np->first_rx.ex)
1780                 less_rx = np->last_rx.ex;
1781
1782         while (np->put_rx.ex != less_rx) {
1783                 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1784                 if (skb) {
1785                         np->put_rx_ctx->skb = skb;
1786                         np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1787                                                              skb->data,
1788                                                              skb_tailroom(skb),
1789                                                              PCI_DMA_FROMDEVICE);
1790                         np->put_rx_ctx->dma_len = skb_tailroom(skb);
1791                         np->put_rx.ex->bufhigh = cpu_to_le32(dma_high(np->put_rx_ctx->dma));
1792                         np->put_rx.ex->buflow = cpu_to_le32(dma_low(np->put_rx_ctx->dma));
1793                         wmb();
1794                         np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
1795                         if (unlikely(np->put_rx.ex++ == np->last_rx.ex))
1796                                 np->put_rx.ex = np->first_rx.ex;
1797                         if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1798                                 np->put_rx_ctx = np->first_rx_ctx;
1799                 } else
1800                         return 1;
1801         }
1802         return 0;
1803 }
1804
1805 /* If rx bufs are exhausted called after 50ms to attempt to refresh */
1806 static void nv_do_rx_refill(unsigned long data)
1807 {
1808         struct net_device *dev = (struct net_device *) data;
1809         struct fe_priv *np = netdev_priv(dev);
1810
1811         /* Just reschedule NAPI rx processing */
1812         napi_schedule(&np->napi);
1813 }
1814
1815 static void nv_init_rx(struct net_device *dev)
1816 {
1817         struct fe_priv *np = netdev_priv(dev);
1818         int i;
1819
1820         np->get_rx = np->put_rx = np->first_rx = np->rx_ring;
1821
1822         if (!nv_optimized(np))
1823                 np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1];
1824         else
1825                 np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1];
1826         np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb;
1827         np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1];
1828
1829         for (i = 0; i < np->rx_ring_size; i++) {
1830                 if (!nv_optimized(np)) {
1831                         np->rx_ring.orig[i].flaglen = 0;
1832                         np->rx_ring.orig[i].buf = 0;
1833                 } else {
1834                         np->rx_ring.ex[i].flaglen = 0;
1835                         np->rx_ring.ex[i].txvlan = 0;
1836                         np->rx_ring.ex[i].bufhigh = 0;
1837                         np->rx_ring.ex[i].buflow = 0;
1838                 }
1839                 np->rx_skb[i].skb = NULL;
1840                 np->rx_skb[i].dma = 0;
1841         }
1842 }
1843
1844 static void nv_init_tx(struct net_device *dev)
1845 {
1846         struct fe_priv *np = netdev_priv(dev);
1847         int i;
1848
1849         np->get_tx = np->put_tx = np->first_tx = np->tx_ring;
1850
1851         if (!nv_optimized(np))
1852                 np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1];
1853         else
1854                 np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1];
1855         np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb;
1856         np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1];
1857         np->tx_pkts_in_progress = 0;
1858         np->tx_change_owner = NULL;
1859         np->tx_end_flip = NULL;
1860         np->tx_stop = 0;
1861
1862         for (i = 0; i < np->tx_ring_size; i++) {
1863                 if (!nv_optimized(np)) {
1864                         np->tx_ring.orig[i].flaglen = 0;
1865                         np->tx_ring.orig[i].buf = 0;
1866                 } else {
1867                         np->tx_ring.ex[i].flaglen = 0;
1868                         np->tx_ring.ex[i].txvlan = 0;
1869                         np->tx_ring.ex[i].bufhigh = 0;
1870                         np->tx_ring.ex[i].buflow = 0;
1871                 }
1872                 np->tx_skb[i].skb = NULL;
1873                 np->tx_skb[i].dma = 0;
1874                 np->tx_skb[i].dma_len = 0;
1875                 np->tx_skb[i].dma_single = 0;
1876                 np->tx_skb[i].first_tx_desc = NULL;
1877                 np->tx_skb[i].next_tx_ctx = NULL;
1878         }
1879 }
1880
1881 static int nv_init_ring(struct net_device *dev)
1882 {
1883         struct fe_priv *np = netdev_priv(dev);
1884
1885         nv_init_tx(dev);
1886         nv_init_rx(dev);
1887
1888         if (!nv_optimized(np))
1889                 return nv_alloc_rx(dev);
1890         else
1891                 return nv_alloc_rx_optimized(dev);
1892 }
1893
1894 static void nv_unmap_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb)
1895 {
1896         if (tx_skb->dma) {
1897                 if (tx_skb->dma_single)
1898                         pci_unmap_single(np->pci_dev, tx_skb->dma,
1899                                          tx_skb->dma_len,
1900                                          PCI_DMA_TODEVICE);
1901                 else
1902                         pci_unmap_page(np->pci_dev, tx_skb->dma,
1903                                        tx_skb->dma_len,
1904                                        PCI_DMA_TODEVICE);
1905                 tx_skb->dma = 0;
1906         }
1907 }
1908
1909 static int nv_release_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb)
1910 {
1911         nv_unmap_txskb(np, tx_skb);
1912         if (tx_skb->skb) {
1913                 dev_kfree_skb_any(tx_skb->skb);
1914                 tx_skb->skb = NULL;
1915                 return 1;
1916         }
1917         return 0;
1918 }
1919
1920 static void nv_drain_tx(struct net_device *dev)
1921 {
1922         struct fe_priv *np = netdev_priv(dev);
1923         unsigned int i;
1924
1925         for (i = 0; i < np->tx_ring_size; i++) {
1926                 if (!nv_optimized(np)) {
1927                         np->tx_ring.orig[i].flaglen = 0;
1928                         np->tx_ring.orig[i].buf = 0;
1929                 } else {
1930                         np->tx_ring.ex[i].flaglen = 0;
1931                         np->tx_ring.ex[i].txvlan = 0;
1932                         np->tx_ring.ex[i].bufhigh = 0;
1933                         np->tx_ring.ex[i].buflow = 0;
1934                 }
1935                 if (nv_release_txskb(np, &np->tx_skb[i]))
1936                         dev->stats.tx_dropped++;
1937                 np->tx_skb[i].dma = 0;
1938                 np->tx_skb[i].dma_len = 0;
1939                 np->tx_skb[i].dma_single = 0;
1940                 np->tx_skb[i].first_tx_desc = NULL;
1941                 np->tx_skb[i].next_tx_ctx = NULL;
1942         }
1943         np->tx_pkts_in_progress = 0;
1944         np->tx_change_owner = NULL;
1945         np->tx_end_flip = NULL;
1946 }
1947
1948 static void nv_drain_rx(struct net_device *dev)
1949 {
1950         struct fe_priv *np = netdev_priv(dev);
1951         int i;
1952
1953         for (i = 0; i < np->rx_ring_size; i++) {
1954                 if (!nv_optimized(np)) {
1955                         np->rx_ring.orig[i].flaglen = 0;
1956                         np->rx_ring.orig[i].buf = 0;
1957                 } else {
1958                         np->rx_ring.ex[i].flaglen = 0;
1959                         np->rx_ring.ex[i].txvlan = 0;
1960                         np->rx_ring.ex[i].bufhigh = 0;
1961                         np->rx_ring.ex[i].buflow = 0;
1962                 }
1963                 wmb();
1964                 if (np->rx_skb[i].skb) {
1965                         pci_unmap_single(np->pci_dev, np->rx_skb[i].dma,
1966                                          (skb_end_pointer(np->rx_skb[i].skb) -
1967                                           np->rx_skb[i].skb->data),
1968                                          PCI_DMA_FROMDEVICE);
1969                         dev_kfree_skb(np->rx_skb[i].skb);
1970                         np->rx_skb[i].skb = NULL;
1971                 }
1972         }
1973 }
1974
1975 static void nv_drain_rxtx(struct net_device *dev)
1976 {
1977         nv_drain_tx(dev);
1978         nv_drain_rx(dev);
1979 }
1980
1981 static inline u32 nv_get_empty_tx_slots(struct fe_priv *np)
1982 {
1983         return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size));
1984 }
1985
1986 static void nv_legacybackoff_reseed(struct net_device *dev)
1987 {
1988         u8 __iomem *base = get_hwbase(dev);
1989         u32 reg;
1990         u32 low;
1991         int tx_status = 0;
1992
1993         reg = readl(base + NvRegSlotTime) & ~NVREG_SLOTTIME_MASK;
1994         get_random_bytes(&low, sizeof(low));
1995         reg |= low & NVREG_SLOTTIME_MASK;
1996
1997         /* Need to stop tx before change takes effect.
1998          * Caller has already gained np->lock.
1999          */
2000         tx_status = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START;
2001         if (tx_status)
2002                 nv_stop_tx(dev);
2003         nv_stop_rx(dev);
2004         writel(reg, base + NvRegSlotTime);
2005         if (tx_status)
2006                 nv_start_tx(dev);
2007         nv_start_rx(dev);
2008 }
2009
2010 /* Gear Backoff Seeds */
2011 #define BACKOFF_SEEDSET_ROWS    8
2012 #define BACKOFF_SEEDSET_LFSRS   15
2013
2014 /* Known Good seed sets */
2015 static const u32 main_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2016         {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2017         {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 385, 761, 790, 974},
2018         {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2019         {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 386, 761, 790, 974},
2020         {266, 265, 276, 585, 397, 208, 345, 355, 365, 376, 385, 396, 771, 700, 984},
2021         {266, 265, 276, 586, 397, 208, 346, 355, 365, 376, 285, 396, 771, 700, 984},
2022         {366, 365, 376, 686, 497, 308, 447, 455, 466, 476, 485, 496, 871, 800,  84},
2023         {466, 465, 476, 786, 597, 408, 547, 555, 566, 576, 585, 597, 971, 900, 184} };
2024
2025 static const u32 gear_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2026         {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
2027         {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2028         {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 397},
2029         {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
2030         {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375,  30, 295},
2031         {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2032         {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2033         {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395} };
2034
2035 static void nv_gear_backoff_reseed(struct net_device *dev)
2036 {
2037         u8 __iomem *base = get_hwbase(dev);
2038         u32 miniseed1, miniseed2, miniseed2_reversed, miniseed3, miniseed3_reversed;
2039         u32 temp, seedset, combinedSeed;
2040         int i;
2041
2042         /* Setup seed for free running LFSR */
2043         /* We are going to read the time stamp counter 3 times
2044            and swizzle bits around to increase randomness */
2045         get_random_bytes(&miniseed1, sizeof(miniseed1));
2046         miniseed1 &= 0x0fff;
2047         if (miniseed1 == 0)
2048                 miniseed1 = 0xabc;
2049
2050         get_random_bytes(&miniseed2, sizeof(miniseed2));
2051         miniseed2 &= 0x0fff;
2052         if (miniseed2 == 0)
2053                 miniseed2 = 0xabc;
2054         miniseed2_reversed =
2055                 ((miniseed2 & 0xF00) >> 8) |
2056                  (miniseed2 & 0x0F0) |
2057                  ((miniseed2 & 0x00F) << 8);
2058
2059         get_random_bytes(&miniseed3, sizeof(miniseed3));
2060         miniseed3 &= 0x0fff;
2061         if (miniseed3 == 0)
2062                 miniseed3 = 0xabc;
2063         miniseed3_reversed =
2064                 ((miniseed3 & 0xF00) >> 8) |
2065                  (miniseed3 & 0x0F0) |
2066                  ((miniseed3 & 0x00F) << 8);
2067
2068         combinedSeed = ((miniseed1 ^ miniseed2_reversed) << 12) |
2069                        (miniseed2 ^ miniseed3_reversed);
2070
2071         /* Seeds can not be zero */
2072         if ((combinedSeed & NVREG_BKOFFCTRL_SEED_MASK) == 0)
2073                 combinedSeed |= 0x08;
2074         if ((combinedSeed & (NVREG_BKOFFCTRL_SEED_MASK << NVREG_BKOFFCTRL_GEAR)) == 0)
2075                 combinedSeed |= 0x8000;
2076
2077         /* No need to disable tx here */
2078         temp = NVREG_BKOFFCTRL_DEFAULT | (0 << NVREG_BKOFFCTRL_SELECT);
2079         temp |= combinedSeed & NVREG_BKOFFCTRL_SEED_MASK;
2080         temp |= combinedSeed >> NVREG_BKOFFCTRL_GEAR;
2081         writel(temp, base + NvRegBackOffControl);
2082
2083         /* Setup seeds for all gear LFSRs. */
2084         get_random_bytes(&seedset, sizeof(seedset));
2085         seedset = seedset % BACKOFF_SEEDSET_ROWS;
2086         for (i = 1; i <= BACKOFF_SEEDSET_LFSRS; i++) {
2087                 temp = NVREG_BKOFFCTRL_DEFAULT | (i << NVREG_BKOFFCTRL_SELECT);
2088                 temp |= main_seedset[seedset][i-1] & 0x3ff;
2089                 temp |= ((gear_seedset[seedset][i-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR);
2090                 writel(temp, base + NvRegBackOffControl);
2091         }
2092 }
2093
2094 /*
2095  * nv_start_xmit: dev->hard_start_xmit function
2096  * Called with netif_tx_lock held.
2097  */
2098 static netdev_tx_t nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
2099 {
2100         struct fe_priv *np = netdev_priv(dev);
2101         u32 tx_flags = 0;
2102         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
2103         unsigned int fragments = skb_shinfo(skb)->nr_frags;
2104         unsigned int i;
2105         u32 offset = 0;
2106         u32 bcnt;
2107         u32 size = skb_headlen(skb);
2108         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2109         u32 empty_slots;
2110         struct ring_desc *put_tx;
2111         struct ring_desc *start_tx;
2112         struct ring_desc *prev_tx;
2113         struct nv_skb_map *prev_tx_ctx;
2114         unsigned long flags;
2115
2116         /* add fragments to entries count */
2117         for (i = 0; i < fragments; i++) {
2118                 u32 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[i]);
2119
2120                 entries += (frag_size >> NV_TX2_TSO_MAX_SHIFT) +
2121                            ((frag_size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2122         }
2123
2124         spin_lock_irqsave(&np->lock, flags);
2125         empty_slots = nv_get_empty_tx_slots(np);
2126         if (unlikely(empty_slots <= entries)) {
2127                 netif_stop_queue(dev);
2128                 np->tx_stop = 1;
2129                 spin_unlock_irqrestore(&np->lock, flags);
2130                 return NETDEV_TX_BUSY;
2131         }
2132         spin_unlock_irqrestore(&np->lock, flags);
2133
2134         start_tx = put_tx = np->put_tx.orig;
2135
2136         /* setup the header buffer */
2137         do {
2138                 prev_tx = put_tx;
2139                 prev_tx_ctx = np->put_tx_ctx;
2140                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2141                 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2142                                                 PCI_DMA_TODEVICE);
2143                 np->put_tx_ctx->dma_len = bcnt;
2144                 np->put_tx_ctx->dma_single = 1;
2145                 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2146                 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2147
2148                 tx_flags = np->tx_flags;
2149                 offset += bcnt;
2150                 size -= bcnt;
2151                 if (unlikely(put_tx++ == np->last_tx.orig))
2152                         put_tx = np->first_tx.orig;
2153                 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2154                         np->put_tx_ctx = np->first_tx_ctx;
2155         } while (size);
2156
2157         /* setup the fragments */
2158         for (i = 0; i < fragments; i++) {
2159                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2160                 u32 frag_size = skb_frag_size(frag);
2161                 offset = 0;
2162
2163                 do {
2164                         prev_tx = put_tx;
2165                         prev_tx_ctx = np->put_tx_ctx;
2166                         bcnt = (frag_size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : frag_size;
2167                         np->put_tx_ctx->dma = skb_frag_dma_map(
2168                                                         &np->pci_dev->dev,
2169                                                         frag, offset,
2170                                                         bcnt,
2171                                                         DMA_TO_DEVICE);
2172                         np->put_tx_ctx->dma_len = bcnt;
2173                         np->put_tx_ctx->dma_single = 0;
2174                         put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2175                         put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2176
2177                         offset += bcnt;
2178                         frag_size -= bcnt;
2179                         if (unlikely(put_tx++ == np->last_tx.orig))
2180                                 put_tx = np->first_tx.orig;
2181                         if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2182                                 np->put_tx_ctx = np->first_tx_ctx;
2183                 } while (frag_size);
2184         }
2185
2186         /* set last fragment flag  */
2187         prev_tx->flaglen |= cpu_to_le32(tx_flags_extra);
2188
2189         /* save skb in this slot's context area */
2190         prev_tx_ctx->skb = skb;
2191
2192         if (skb_is_gso(skb))
2193                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2194         else
2195                 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2196                          NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2197
2198         spin_lock_irqsave(&np->lock, flags);
2199
2200         /* set tx flags */
2201         start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2202         np->put_tx.orig = put_tx;
2203
2204         spin_unlock_irqrestore(&np->lock, flags);
2205
2206         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2207         return NETDEV_TX_OK;
2208 }
2209
2210 static netdev_tx_t nv_start_xmit_optimized(struct sk_buff *skb,
2211                                            struct net_device *dev)
2212 {
2213         struct fe_priv *np = netdev_priv(dev);
2214         u32 tx_flags = 0;
2215         u32 tx_flags_extra;
2216         unsigned int fragments = skb_shinfo(skb)->nr_frags;
2217         unsigned int i;
2218         u32 offset = 0;
2219         u32 bcnt;
2220         u32 size = skb_headlen(skb);
2221         u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2222         u32 empty_slots;
2223         struct ring_desc_ex *put_tx;
2224         struct ring_desc_ex *start_tx;
2225         struct ring_desc_ex *prev_tx;
2226         struct nv_skb_map *prev_tx_ctx;
2227         struct nv_skb_map *start_tx_ctx;
2228         unsigned long flags;
2229
2230         /* add fragments to entries count */
2231         for (i = 0; i < fragments; i++) {
2232                 u32 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[i]);
2233
2234                 entries += (frag_size >> NV_TX2_TSO_MAX_SHIFT) +
2235                            ((frag_size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2236         }
2237
2238         spin_lock_irqsave(&np->lock, flags);
2239         empty_slots = nv_get_empty_tx_slots(np);
2240         if (unlikely(empty_slots <= entries)) {
2241                 netif_stop_queue(dev);
2242                 np->tx_stop = 1;
2243                 spin_unlock_irqrestore(&np->lock, flags);
2244                 return NETDEV_TX_BUSY;
2245         }
2246         spin_unlock_irqrestore(&np->lock, flags);
2247
2248         start_tx = put_tx = np->put_tx.ex;
2249         start_tx_ctx = np->put_tx_ctx;
2250
2251         /* setup the header buffer */
2252         do {
2253                 prev_tx = put_tx;
2254                 prev_tx_ctx = np->put_tx_ctx;
2255                 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2256                 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2257                                                 PCI_DMA_TODEVICE);
2258                 np->put_tx_ctx->dma_len = bcnt;
2259                 np->put_tx_ctx->dma_single = 1;
2260                 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2261                 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2262                 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2263
2264                 tx_flags = NV_TX2_VALID;
2265                 offset += bcnt;
2266                 size -= bcnt;
2267                 if (unlikely(put_tx++ == np->last_tx.ex))
2268                         put_tx = np->first_tx.ex;
2269                 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2270                         np->put_tx_ctx = np->first_tx_ctx;
2271         } while (size);
2272
2273         /* setup the fragments */
2274         for (i = 0; i < fragments; i++) {
2275                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2276                 u32 frag_size = skb_frag_size(frag);
2277                 offset = 0;
2278
2279                 do {
2280                         prev_tx = put_tx;
2281                         prev_tx_ctx = np->put_tx_ctx;
2282                         bcnt = (frag_size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : frag_size;
2283                         np->put_tx_ctx->dma = skb_frag_dma_map(
2284                                                         &np->pci_dev->dev,
2285                                                         frag, offset,
2286                                                         bcnt,
2287                                                         DMA_TO_DEVICE);
2288                         np->put_tx_ctx->dma_len = bcnt;
2289                         np->put_tx_ctx->dma_single = 0;
2290                         put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2291                         put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2292                         put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2293
2294                         offset += bcnt;
2295                         frag_size -= bcnt;
2296                         if (unlikely(put_tx++ == np->last_tx.ex))
2297                                 put_tx = np->first_tx.ex;
2298                         if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2299                                 np->put_tx_ctx = np->first_tx_ctx;
2300                 } while (frag_size);
2301         }
2302
2303         /* set last fragment flag  */
2304         prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET);
2305
2306         /* save skb in this slot's context area */
2307         prev_tx_ctx->skb = skb;
2308
2309         if (skb_is_gso(skb))
2310                 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2311         else
2312                 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2313                          NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2314
2315         /* vlan tag */
2316         if (vlan_tx_tag_present(skb))
2317                 start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT |
2318                                         vlan_tx_tag_get(skb));
2319         else
2320                 start_tx->txvlan = 0;
2321
2322         spin_lock_irqsave(&np->lock, flags);
2323
2324         if (np->tx_limit) {
2325                 /* Limit the number of outstanding tx. Setup all fragments, but
2326                  * do not set the VALID bit on the first descriptor. Save a pointer
2327                  * to that descriptor and also for next skb_map element.
2328                  */
2329
2330                 if (np->tx_pkts_in_progress == NV_TX_LIMIT_COUNT) {
2331                         if (!np->tx_change_owner)
2332                                 np->tx_change_owner = start_tx_ctx;
2333
2334                         /* remove VALID bit */
2335                         tx_flags &= ~NV_TX2_VALID;
2336                         start_tx_ctx->first_tx_desc = start_tx;
2337                         start_tx_ctx->next_tx_ctx = np->put_tx_ctx;
2338                         np->tx_end_flip = np->put_tx_ctx;
2339                 } else {
2340                         np->tx_pkts_in_progress++;
2341                 }
2342         }
2343
2344         /* set tx flags */
2345         start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2346         np->put_tx.ex = put_tx;
2347
2348         spin_unlock_irqrestore(&np->lock, flags);
2349
2350         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2351         return NETDEV_TX_OK;
2352 }
2353
2354 static inline void nv_tx_flip_ownership(struct net_device *dev)
2355 {
2356         struct fe_priv *np = netdev_priv(dev);
2357
2358         np->tx_pkts_in_progress--;
2359         if (np->tx_change_owner) {
2360                 np->tx_change_owner->first_tx_desc->flaglen |=
2361                         cpu_to_le32(NV_TX2_VALID);
2362                 np->tx_pkts_in_progress++;
2363
2364                 np->tx_change_owner = np->tx_change_owner->next_tx_ctx;
2365                 if (np->tx_change_owner == np->tx_end_flip)
2366                         np->tx_change_owner = NULL;
2367
2368                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2369         }
2370 }
2371
2372 /*
2373  * nv_tx_done: check for completed packets, release the skbs.
2374  *
2375  * Caller must own np->lock.
2376  */
2377 static int nv_tx_done(struct net_device *dev, int limit)
2378 {
2379         struct fe_priv *np = netdev_priv(dev);
2380         u32 flags;
2381         int tx_work = 0;
2382         struct ring_desc *orig_get_tx = np->get_tx.orig;
2383
2384         while ((np->get_tx.orig != np->put_tx.orig) &&
2385                !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID) &&
2386                (tx_work < limit)) {
2387
2388                 nv_unmap_txskb(np, np->get_tx_ctx);
2389
2390                 if (np->desc_ver == DESC_VER_1) {
2391                         if (flags & NV_TX_LASTPACKET) {
2392                                 if (flags & NV_TX_ERROR) {
2393                                         if ((flags & NV_TX_RETRYERROR) && !(flags & NV_TX_RETRYCOUNT_MASK))
2394                                                 nv_legacybackoff_reseed(dev);
2395                                 } else {
2396                                         dev->stats.tx_packets++;
2397                                         dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
2398                                 }
2399                                 dev_kfree_skb_any(np->get_tx_ctx->skb);
2400                                 np->get_tx_ctx->skb = NULL;
2401                                 tx_work++;
2402                         }
2403                 } else {
2404                         if (flags & NV_TX2_LASTPACKET) {
2405                                 if (flags & NV_TX2_ERROR) {
2406                                         if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK))
2407                                                 nv_legacybackoff_reseed(dev);
2408                                 } else {
2409                                         dev->stats.tx_packets++;
2410                                         dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
2411                                 }
2412                                 dev_kfree_skb_any(np->get_tx_ctx->skb);
2413                                 np->get_tx_ctx->skb = NULL;
2414                                 tx_work++;
2415                         }
2416                 }
2417                 if (unlikely(np->get_tx.orig++ == np->last_tx.orig))
2418                         np->get_tx.orig = np->first_tx.orig;
2419                 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2420                         np->get_tx_ctx = np->first_tx_ctx;
2421         }
2422         if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) {
2423                 np->tx_stop = 0;
2424                 netif_wake_queue(dev);
2425         }
2426         return tx_work;
2427 }
2428
2429 static int nv_tx_done_optimized(struct net_device *dev, int limit)
2430 {
2431         struct fe_priv *np = netdev_priv(dev);
2432         u32 flags;
2433         int tx_work = 0;
2434         struct ring_desc_ex *orig_get_tx = np->get_tx.ex;
2435
2436         while ((np->get_tx.ex != np->put_tx.ex) &&
2437                !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX2_VALID) &&
2438                (tx_work < limit)) {
2439
2440                 nv_unmap_txskb(np, np->get_tx_ctx);
2441
2442                 if (flags & NV_TX2_LASTPACKET) {
2443                         if (flags & NV_TX2_ERROR) {
2444                                 if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK)) {
2445                                         if (np->driver_data & DEV_HAS_GEAR_MODE)
2446                                                 nv_gear_backoff_reseed(dev);
2447                                         else
2448                                                 nv_legacybackoff_reseed(dev);
2449                                 }
2450                         } else {
2451                                 dev->stats.tx_packets++;
2452                                 dev->stats.tx_bytes += np->get_tx_ctx->skb->len;
2453                         }
2454
2455                         dev_kfree_skb_any(np->get_tx_ctx->skb);
2456                         np->get_tx_ctx->skb = NULL;
2457                         tx_work++;
2458
2459                         if (np->tx_limit)
2460                                 nv_tx_flip_ownership(dev);
2461                 }
2462                 if (unlikely(np->get_tx.ex++ == np->last_tx.ex))
2463                         np->get_tx.ex = np->first_tx.ex;
2464                 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2465                         np->get_tx_ctx = np->first_tx_ctx;
2466         }
2467         if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) {
2468                 np->tx_stop = 0;
2469                 netif_wake_queue(dev);
2470         }
2471         return tx_work;
2472 }
2473
2474 /*
2475  * nv_tx_timeout: dev->tx_timeout function
2476  * Called with netif_tx_lock held.
2477  */
2478 static void nv_tx_timeout(struct net_device *dev)
2479 {
2480         struct fe_priv *np = netdev_priv(dev);
2481         u8 __iomem *base = get_hwbase(dev);
2482         u32 status;
2483         union ring_type put_tx;
2484         int saved_tx_limit;
2485
2486         if (np->msi_flags & NV_MSI_X_ENABLED)
2487                 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2488         else
2489                 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2490
2491         netdev_warn(dev, "Got tx_timeout. irq status: %08x\n", status);
2492
2493         if (unlikely(debug_tx_timeout)) {
2494                 int i;
2495
2496                 netdev_info(dev, "Ring at %lx\n", (unsigned long)np->ring_addr);
2497                 netdev_info(dev, "Dumping tx registers\n");
2498                 for (i = 0; i <= np->register_size; i += 32) {
2499                         netdev_info(dev,
2500                                     "%3x: %08x %08x %08x %08x "
2501                                     "%08x %08x %08x %08x\n",
2502                                     i,
2503                                     readl(base + i + 0), readl(base + i + 4),
2504                                     readl(base + i + 8), readl(base + i + 12),
2505                                     readl(base + i + 16), readl(base + i + 20),
2506                                     readl(base + i + 24), readl(base + i + 28));
2507                 }
2508                 netdev_info(dev, "Dumping tx ring\n");
2509                 for (i = 0; i < np->tx_ring_size; i += 4) {
2510                         if (!nv_optimized(np)) {
2511                                 netdev_info(dev,
2512                                             "%03x: %08x %08x // %08x %08x "
2513                                             "// %08x %08x // %08x %08x\n",
2514                                             i,
2515                                             le32_to_cpu(np->tx_ring.orig[i].buf),
2516                                             le32_to_cpu(np->tx_ring.orig[i].flaglen),
2517                                             le32_to_cpu(np->tx_ring.orig[i+1].buf),
2518                                             le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
2519                                             le32_to_cpu(np->tx_ring.orig[i+2].buf),
2520                                             le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
2521                                             le32_to_cpu(np->tx_ring.orig[i+3].buf),
2522                                             le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
2523                         } else {
2524                                 netdev_info(dev,
2525                                             "%03x: %08x %08x %08x "
2526                                             "// %08x %08x %08x "
2527                                             "// %08x %08x %08x "
2528                                             "// %08x %08x %08x\n",
2529                                             i,
2530                                             le32_to_cpu(np->tx_ring.ex[i].bufhigh),
2531                                             le32_to_cpu(np->tx_ring.ex[i].buflow),
2532                                             le32_to_cpu(np->tx_ring.ex[i].flaglen),
2533                                             le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
2534                                             le32_to_cpu(np->tx_ring.ex[i+1].buflow),
2535                                             le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
2536                                             le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
2537                                             le32_to_cpu(np->tx_ring.ex[i+2].buflow),
2538                                             le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
2539                                             le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
2540                                             le32_to_cpu(np->tx_ring.ex[i+3].buflow),
2541                                             le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
2542                         }
2543                 }
2544         }
2545
2546         spin_lock_irq(&np->lock);
2547
2548         /* 1) stop tx engine */
2549         nv_stop_tx(dev);
2550
2551         /* 2) complete any outstanding tx and do not give HW any limited tx pkts */
2552         saved_tx_limit = np->tx_limit;
2553         np->tx_limit = 0; /* prevent giving HW any limited pkts */
2554         np->tx_stop = 0;  /* prevent waking tx queue */
2555         if (!nv_optimized(np))
2556                 nv_tx_done(dev, np->tx_ring_size);
2557         else
2558                 nv_tx_done_optimized(dev, np->tx_ring_size);
2559
2560         /* save current HW position */
2561         if (np->tx_change_owner)
2562                 put_tx.ex = np->tx_change_owner->first_tx_desc;
2563         else
2564                 put_tx = np->put_tx;
2565
2566         /* 3) clear all tx state */
2567         nv_drain_tx(dev);
2568         nv_init_tx(dev);
2569
2570         /* 4) restore state to current HW position */
2571         np->get_tx = np->put_tx = put_tx;
2572         np->tx_limit = saved_tx_limit;
2573
2574         /* 5) restart tx engine */
2575         nv_start_tx(dev);
2576         netif_wake_queue(dev);
2577         spin_unlock_irq(&np->lock);
2578 }
2579
2580 /*
2581  * Called when the nic notices a mismatch between the actual data len on the
2582  * wire and the len indicated in the 802 header
2583  */
2584 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
2585 {
2586         int hdrlen;     /* length of the 802 header */
2587         int protolen;   /* length as stored in the proto field */
2588
2589         /* 1) calculate len according to header */
2590         if (((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
2591                 protolen = ntohs(((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto);
2592                 hdrlen = VLAN_HLEN;
2593         } else {
2594                 protolen = ntohs(((struct ethhdr *)packet)->h_proto);
2595                 hdrlen = ETH_HLEN;
2596         }
2597         if (protolen > ETH_DATA_LEN)
2598                 return datalen; /* Value in proto field not a len, no checks possible */
2599
2600         protolen += hdrlen;
2601         /* consistency checks: */
2602         if (datalen > ETH_ZLEN) {
2603                 if (datalen >= protolen) {
2604                         /* more data on wire than in 802 header, trim of
2605                          * additional data.
2606                          */
2607                         return protolen;
2608                 } else {
2609                         /* less data on wire than mentioned in header.
2610                          * Discard the packet.
2611                          */
2612                         return -1;
2613                 }
2614         } else {
2615                 /* short packet. Accept only if 802 values are also short */
2616                 if (protolen > ETH_ZLEN) {
2617                         return -1;
2618                 }
2619                 return datalen;
2620         }
2621 }
2622
2623 static int nv_rx_process(struct net_device *dev, int limit)
2624 {
2625         struct fe_priv *np = netdev_priv(dev);
2626         u32 flags;
2627         int rx_work = 0;
2628         struct sk_buff *skb;
2629         int len;
2630
2631         while ((np->get_rx.orig != np->put_rx.orig) &&
2632               !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) &&
2633                 (rx_work < limit)) {
2634
2635                 /*
2636                  * the packet is for us - immediately tear down the pci mapping.
2637                  * TODO: check if a prefetch of the first cacheline improves
2638                  * the performance.
2639                  */
2640                 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2641                                 np->get_rx_ctx->dma_len,
2642                                 PCI_DMA_FROMDEVICE);
2643                 skb = np->get_rx_ctx->skb;
2644                 np->get_rx_ctx->skb = NULL;
2645
2646                 /* look at what we actually got: */
2647                 if (np->desc_ver == DESC_VER_1) {
2648                         if (likely(flags & NV_RX_DESCRIPTORVALID)) {
2649                                 len = flags & LEN_MASK_V1;
2650                                 if (unlikely(flags & NV_RX_ERROR)) {
2651                                         if ((flags & NV_RX_ERROR_MASK) == NV_RX_ERROR4) {
2652                                                 len = nv_getlen(dev, skb->data, len);
2653                                                 if (len < 0) {
2654                                                         dev_kfree_skb(skb);
2655                                                         goto next_pkt;
2656                                                 }
2657                                         }
2658                                         /* framing errors are soft errors */
2659                                         else if ((flags & NV_RX_ERROR_MASK) == NV_RX_FRAMINGERR) {
2660                                                 if (flags & NV_RX_SUBSTRACT1)
2661                                                         len--;
2662                                         }
2663                                         /* the rest are hard errors */
2664                                         else {
2665                                                 if (flags & NV_RX_MISSEDFRAME)
2666                                                         dev->stats.rx_missed_errors++;
2667                                                 dev_kfree_skb(skb);
2668                                                 goto next_pkt;
2669                                         }
2670                                 }
2671                         } else {
2672                                 dev_kfree_skb(skb);
2673                                 goto next_pkt;
2674                         }
2675                 } else {
2676                         if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2677                                 len = flags & LEN_MASK_V2;
2678                                 if (unlikely(flags & NV_RX2_ERROR)) {
2679                                         if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
2680                                                 len = nv_getlen(dev, skb->data, len);
2681                                                 if (len < 0) {
2682                                                         dev_kfree_skb(skb);
2683                                                         goto next_pkt;
2684                                                 }
2685                                         }
2686                                         /* framing errors are soft errors */
2687                                         else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2688                                                 if (flags & NV_RX2_SUBSTRACT1)
2689                                                         len--;
2690                                         }
2691                                         /* the rest are hard errors */
2692                                         else {
2693                                                 dev_kfree_skb(skb);
2694                                                 goto next_pkt;
2695                                         }
2696                                 }
2697                                 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2698                                     ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP))   /*ip and udp */
2699                                         skb->ip_summed = CHECKSUM_UNNECESSARY;
2700                         } else {
2701                                 dev_kfree_skb(skb);
2702                                 goto next_pkt;
2703                         }
2704                 }
2705                 /* got a valid packet - forward it to the network core */
2706                 skb_put(skb, len);
2707                 skb->protocol = eth_type_trans(skb, dev);
2708                 napi_gro_receive(&np->napi, skb);
2709                 dev->stats.rx_packets++;
2710                 dev->stats.rx_bytes += len;
2711 next_pkt:
2712                 if (unlikely(np->get_rx.orig++ == np->last_rx.orig))
2713                         np->get_rx.orig = np->first_rx.orig;
2714                 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2715                         np->get_rx_ctx = np->first_rx_ctx;
2716
2717                 rx_work++;
2718         }
2719
2720         return rx_work;
2721 }
2722
2723 static int nv_rx_process_optimized(struct net_device *dev, int limit)
2724 {
2725         struct fe_priv *np = netdev_priv(dev);
2726         u32 flags;
2727         u32 vlanflags = 0;
2728         int rx_work = 0;
2729         struct sk_buff *skb;
2730         int len;
2731
2732         while ((np->get_rx.ex != np->put_rx.ex) &&
2733               !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) &&
2734               (rx_work < limit)) {
2735
2736                 /*
2737                  * the packet is for us - immediately tear down the pci mapping.
2738                  * TODO: check if a prefetch of the first cacheline improves
2739                  * the performance.
2740                  */
2741                 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2742                                 np->get_rx_ctx->dma_len,
2743                                 PCI_DMA_FROMDEVICE);
2744                 skb = np->get_rx_ctx->skb;
2745                 np->get_rx_ctx->skb = NULL;
2746
2747                 /* look at what we actually got: */
2748                 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2749                         len = flags & LEN_MASK_V2;
2750                         if (unlikely(flags & NV_RX2_ERROR)) {
2751                                 if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
2752                                         len = nv_getlen(dev, skb->data, len);
2753                                         if (len < 0) {
2754                                                 dev_kfree_skb(skb);
2755                                                 goto next_pkt;
2756                                         }
2757                                 }
2758                                 /* framing errors are soft errors */
2759                                 else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2760                                         if (flags & NV_RX2_SUBSTRACT1)
2761                                                 len--;
2762                                 }
2763                                 /* the rest are hard errors */
2764                                 else {
2765                                         dev_kfree_skb(skb);
2766                                         goto next_pkt;
2767                                 }
2768                         }
2769
2770                         if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2771                             ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP))   /*ip and udp */
2772                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2773
2774                         /* got a valid packet - forward it to the network core */
2775                         skb_put(skb, len);
2776                         skb->protocol = eth_type_trans(skb, dev);
2777                         prefetch(skb->data);
2778
2779                         vlanflags = le32_to_cpu(np->get_rx.ex->buflow);
2780
2781                         /*
2782                          * There's need to check for NETIF_F_HW_VLAN_RX here.
2783                          * Even if vlan rx accel is disabled,
2784                          * NV_RX3_VLAN_TAG_PRESENT is pseudo randomly set.
2785                          */
2786                         if (dev->features & NETIF_F_HW_VLAN_RX &&
2787                             vlanflags & NV_RX3_VLAN_TAG_PRESENT) {
2788                                 u16 vid = vlanflags & NV_RX3_VLAN_TAG_MASK;
2789
2790                                 __vlan_hwaccel_put_tag(skb, vid);
2791                         }
2792                         napi_gro_receive(&np->napi, skb);
2793                         dev->stats.rx_packets++;
2794                         dev->stats.rx_bytes += len;
2795                 } else {
2796                         dev_kfree_skb(skb);
2797                 }
2798 next_pkt:
2799                 if (unlikely(np->get_rx.ex++ == np->last_rx.ex))
2800                         np->get_rx.ex = np->first_rx.ex;
2801                 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2802                         np->get_rx_ctx = np->first_rx_ctx;
2803
2804                 rx_work++;
2805         }
2806
2807         return rx_work;
2808 }
2809
2810 static void set_bufsize(struct net_device *dev)
2811 {
2812         struct fe_priv *np = netdev_priv(dev);
2813
2814         if (dev->mtu <= ETH_DATA_LEN)
2815                 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
2816         else
2817                 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
2818 }
2819
2820 /*
2821  * nv_change_mtu: dev->change_mtu function
2822  * Called with dev_base_lock held for read.
2823  */
2824 static int nv_change_mtu(struct net_device *dev, int new_mtu)
2825 {
2826         struct fe_priv *np = netdev_priv(dev);
2827         int old_mtu;
2828
2829         if (new_mtu < 64 || new_mtu > np->pkt_limit)
2830                 return -EINVAL;
2831
2832         old_mtu = dev->mtu;
2833         dev->mtu = new_mtu;
2834
2835         /* return early if the buffer sizes will not change */
2836         if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
2837                 return 0;
2838         if (old_mtu == new_mtu)
2839                 return 0;
2840
2841         /* synchronized against open : rtnl_lock() held by caller */
2842         if (netif_running(dev)) {
2843                 u8 __iomem *base = get_hwbase(dev);
2844                 /*
2845                  * It seems that the nic preloads valid ring entries into an
2846                  * internal buffer. The procedure for flushing everything is
2847                  * guessed, there is probably a simpler approach.
2848                  * Changing the MTU is a rare event, it shouldn't matter.
2849                  */
2850                 nv_disable_irq(dev);
2851                 nv_napi_disable(dev);
2852                 netif_tx_lock_bh(dev);
2853                 netif_addr_lock(dev);
2854                 spin_lock(&np->lock);
2855                 /* stop engines */
2856                 nv_stop_rxtx(dev);
2857                 nv_txrx_reset(dev);
2858                 /* drain rx queue */
2859                 nv_drain_rxtx(dev);
2860                 /* reinit driver view of the rx queue */
2861                 set_bufsize(dev);
2862                 if (nv_init_ring(dev)) {
2863                         if (!np->in_shutdown)
2864                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2865                 }
2866                 /* reinit nic view of the rx queue */
2867                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
2868                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
2869                 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
2870                         base + NvRegRingSizes);
2871                 pci_push(base);
2872                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2873                 pci_push(base);
2874
2875                 /* restart rx engine */
2876                 nv_start_rxtx(dev);
2877                 spin_unlock(&np->lock);
2878                 netif_addr_unlock(dev);
2879                 netif_tx_unlock_bh(dev);
2880                 nv_napi_enable(dev);
2881                 nv_enable_irq(dev);
2882         }
2883         return 0;
2884 }
2885
2886 static void nv_copy_mac_to_hw(struct net_device *dev)
2887 {
2888         u8 __iomem *base = get_hwbase(dev);
2889         u32 mac[2];
2890
2891         mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
2892                         (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
2893         mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
2894
2895         writel(mac[0], base + NvRegMacAddrA);
2896         writel(mac[1], base + NvRegMacAddrB);
2897 }
2898
2899 /*
2900  * nv_set_mac_address: dev->set_mac_address function
2901  * Called with rtnl_lock() held.
2902  */
2903 static int nv_set_mac_address(struct net_device *dev, void *addr)
2904 {
2905         struct fe_priv *np = netdev_priv(dev);
2906         struct sockaddr *macaddr = (struct sockaddr *)addr;
2907
2908         if (!is_valid_ether_addr(macaddr->sa_data))
2909                 return -EADDRNOTAVAIL;
2910
2911         /* synchronized against open : rtnl_lock() held by caller */
2912         memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
2913
2914         if (netif_running(dev)) {
2915                 netif_tx_lock_bh(dev);
2916                 netif_addr_lock(dev);
2917                 spin_lock_irq(&np->lock);
2918
2919                 /* stop rx engine */
2920                 nv_stop_rx(dev);
2921
2922                 /* set mac address */
2923                 nv_copy_mac_to_hw(dev);
2924
2925                 /* restart rx engine */
2926                 nv_start_rx(dev);
2927                 spin_unlock_irq(&np->lock);
2928                 netif_addr_unlock(dev);
2929                 netif_tx_unlock_bh(dev);
2930         } else {
2931                 nv_copy_mac_to_hw(dev);
2932         }
2933         return 0;
2934 }
2935
2936 /*
2937  * nv_set_multicast: dev->set_multicast function
2938  * Called with netif_tx_lock held.
2939  */
2940 static void nv_set_multicast(struct net_device *dev)
2941 {
2942         struct fe_priv *np = netdev_priv(dev);
2943         u8 __iomem *base = get_hwbase(dev);
2944         u32 addr[2];
2945         u32 mask[2];
2946         u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
2947
2948         memset(addr, 0, sizeof(addr));
2949         memset(mask, 0, sizeof(mask));
2950
2951         if (dev->flags & IFF_PROMISC) {
2952                 pff |= NVREG_PFF_PROMISC;
2953         } else {
2954                 pff |= NVREG_PFF_MYADDR;
2955
2956                 if (dev->flags & IFF_ALLMULTI || !netdev_mc_empty(dev)) {
2957                         u32 alwaysOff[2];
2958                         u32 alwaysOn[2];
2959
2960                         alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
2961                         if (dev->flags & IFF_ALLMULTI) {
2962                                 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
2963                         } else {
2964                                 struct netdev_hw_addr *ha;
2965
2966                                 netdev_for_each_mc_addr(ha, dev) {
2967                                         unsigned char *hw_addr = ha->addr;
2968                                         u32 a, b;
2969
2970                                         a = le32_to_cpu(*(__le32 *) hw_addr);
2971                                         b = le16_to_cpu(*(__le16 *) (&hw_addr[4]));
2972                                         alwaysOn[0] &= a;
2973                                         alwaysOff[0] &= ~a;
2974                                         alwaysOn[1] &= b;
2975                                         alwaysOff[1] &= ~b;
2976                                 }
2977                         }
2978                         addr[0] = alwaysOn[0];
2979                         addr[1] = alwaysOn[1];
2980                         mask[0] = alwaysOn[0] | alwaysOff[0];
2981                         mask[1] = alwaysOn[1] | alwaysOff[1];
2982                 } else {
2983                         mask[0] = NVREG_MCASTMASKA_NONE;
2984                         mask[1] = NVREG_MCASTMASKB_NONE;
2985                 }
2986         }
2987         addr[0] |= NVREG_MCASTADDRA_FORCE;
2988         pff |= NVREG_PFF_ALWAYS;
2989         spin_lock_irq(&np->lock);
2990         nv_stop_rx(dev);
2991         writel(addr[0], base + NvRegMulticastAddrA);
2992         writel(addr[1], base + NvRegMulticastAddrB);
2993         writel(mask[0], base + NvRegMulticastMaskA);
2994         writel(mask[1], base + NvRegMulticastMaskB);
2995         writel(pff, base + NvRegPacketFilterFlags);
2996         nv_start_rx(dev);
2997         spin_unlock_irq(&np->lock);
2998 }
2999
3000 static void nv_update_pause(struct net_device *dev, u32 pause_flags)
3001 {
3002         struct fe_priv *np = netdev_priv(dev);
3003         u8 __iomem *base = get_hwbase(dev);
3004
3005         np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
3006
3007         if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
3008                 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
3009                 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
3010                         writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
3011                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3012                 } else {
3013                         writel(pff, base + NvRegPacketFilterFlags);
3014                 }
3015         }
3016         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
3017                 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
3018                 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
3019                         u32 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V1;
3020                         if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V2)
3021                                 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V2;
3022                         if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V3) {
3023                                 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V3;
3024                                 /* limit the number of tx pause frames to a default of 8 */
3025                                 writel(readl(base + NvRegTxPauseFrameLimit)|NVREG_TX_PAUSEFRAMELIMIT_ENABLE, base + NvRegTxPauseFrameLimit);
3026                         }
3027                         writel(pause_enable,  base + NvRegTxPauseFrame);
3028                         writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
3029                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3030                 } else {
3031                         writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
3032                         writel(regmisc, base + NvRegMisc1);
3033                 }
3034         }
3035 }
3036
3037 static void nv_force_linkspeed(struct net_device *dev, int speed, int duplex)
3038 {
3039         struct fe_priv *np = netdev_priv(dev);
3040         u8 __iomem *base = get_hwbase(dev);
3041         u32 phyreg, txreg;
3042         int mii_status;
3043
3044         np->linkspeed = NVREG_LINKSPEED_FORCE|speed;
3045         np->duplex = duplex;
3046
3047         /* see if gigabit phy */
3048         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3049         if (mii_status & PHY_GIGABIT) {
3050                 np->gigabit = PHY_GIGABIT;
3051                 phyreg = readl(base + NvRegSlotTime);
3052                 phyreg &= ~(0x3FF00);
3053                 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
3054                         phyreg |= NVREG_SLOTTIME_10_100_FULL;
3055                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
3056                         phyreg |= NVREG_SLOTTIME_10_100_FULL;
3057                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
3058                         phyreg |= NVREG_SLOTTIME_1000_FULL;
3059                 writel(phyreg, base + NvRegSlotTime);
3060         }
3061
3062         phyreg = readl(base + NvRegPhyInterface);
3063         phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
3064         if (np->duplex == 0)
3065                 phyreg |= PHY_HALF;
3066         if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
3067                 phyreg |= PHY_100;
3068         else if ((np->linkspeed & NVREG_LINKSPEED_MASK) ==
3069                                                         NVREG_LINKSPEED_1000)
3070                 phyreg |= PHY_1000;
3071         writel(phyreg, base + NvRegPhyInterface);
3072
3073         if (phyreg & PHY_RGMII) {
3074                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) ==
3075                                                         NVREG_LINKSPEED_1000)
3076                         txreg = NVREG_TX_DEFERRAL_RGMII_1000;
3077                 else
3078                         txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
3079         } else {
3080                 txreg = NVREG_TX_DEFERRAL_DEFAULT;
3081         }
3082         writel(txreg, base + NvRegTxDeferral);
3083
3084         if (np->desc_ver == DESC_VER_1) {
3085                 txreg = NVREG_TX_WM_DESC1_DEFAULT;
3086         } else {
3087                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) ==
3088                                          NVREG_LINKSPEED_1000)
3089                         txreg = NVREG_TX_WM_DESC2_3_1000;
3090                 else
3091                         txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
3092         }
3093         writel(txreg, base + NvRegTxWatermark);
3094
3095         writel(NVREG_MISC1_FORCE | (np->duplex ? 0 : NVREG_MISC1_HD),
3096                         base + NvRegMisc1);
3097         pci_push(base);
3098         writel(np->linkspeed, base + NvRegLinkSpeed);
3099         pci_push(base);
3100
3101         return;
3102 }
3103
3104 /**
3105  * nv_update_linkspeed: Setup the MAC according to the link partner
3106  * @dev: Network device to be configured
3107  *
3108  * The function queries the PHY and checks if there is a link partner.
3109  * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
3110  * set to 10 MBit HD.
3111  *
3112  * The function returns 0 if there is no link partner and 1 if there is
3113  * a good link partner.
3114  */
3115 static int nv_update_linkspeed(struct net_device *dev)
3116 {
3117         struct fe_priv *np = netdev_priv(dev);
3118         u8 __iomem *base = get_hwbase(dev);
3119         int adv = 0;
3120         int lpa = 0;
3121         int adv_lpa, adv_pause, lpa_pause;
3122         int newls = np->linkspeed;
3123         int newdup = np->duplex;
3124         int mii_status;
3125         u32 bmcr;
3126         int retval = 0;
3127         u32 control_1000, status_1000, phyreg, pause_flags, txreg;
3128         u32 txrxFlags = 0;
3129         u32 phy_exp;
3130
3131         /* If device loopback is enabled, set carrier on and enable max link
3132          * speed.
3133          */
3134         bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3135         if (bmcr & BMCR_LOOPBACK) {
3136                 if (netif_running(dev)) {
3137                         nv_force_linkspeed(dev, NVREG_LINKSPEED_1000, 1);
3138                         if (!netif_carrier_ok(dev))
3139                                 netif_carrier_on(dev);
3140                 }
3141                 return 1;
3142         }
3143
3144         /* BMSR_LSTATUS is latched, read it twice:
3145          * we want the current value.
3146          */
3147         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3148         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3149
3150         if (!(mii_status & BMSR_LSTATUS)) {
3151                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3152                 newdup = 0;
3153                 retval = 0;
3154                 goto set_speed;
3155         }
3156
3157         if (np->autoneg == 0) {
3158                 if (np->fixed_mode & LPA_100FULL) {
3159                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3160                         newdup = 1;
3161                 } else if (np->fixed_mode & LPA_100HALF) {
3162                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3163                         newdup = 0;
3164                 } else if (np->fixed_mode & LPA_10FULL) {
3165                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3166                         newdup = 1;
3167                 } else {
3168                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3169                         newdup = 0;
3170                 }
3171                 retval = 1;
3172                 goto set_speed;
3173         }
3174         /* check auto negotiation is complete */
3175         if (!(mii_status & BMSR_ANEGCOMPLETE)) {
3176                 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
3177                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3178                 newdup = 0;
3179                 retval = 0;
3180                 goto set_speed;
3181         }
3182
3183         adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3184         lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
3185
3186         retval = 1;
3187         if (np->gigabit == PHY_GIGABIT) {
3188                 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3189                 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
3190
3191                 if ((control_1000 & ADVERTISE_1000FULL) &&
3192                         (status_1000 & LPA_1000FULL)) {
3193                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
3194                         newdup = 1;
3195                         goto set_speed;
3196                 }
3197         }
3198
3199         /* FIXME: handle parallel detection properly */
3200         adv_lpa = lpa & adv;
3201         if (adv_lpa & LPA_100FULL) {
3202                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3203                 newdup = 1;
3204         } else if (adv_lpa & LPA_100HALF) {
3205                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3206                 newdup = 0;
3207         } else if (adv_lpa & LPA_10FULL) {
3208                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3209                 newdup = 1;
3210         } else if (adv_lpa & LPA_10HALF) {
3211                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3212                 newdup = 0;
3213         } else {
3214                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3215                 newdup = 0;
3216         }
3217
3218 set_speed:
3219         if (np->duplex == newdup && np->linkspeed == newls)
3220                 return retval;
3221
3222         np->duplex = newdup;
3223         np->linkspeed = newls;
3224
3225         /* The transmitter and receiver must be restarted for safe update */
3226         if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START) {
3227                 txrxFlags |= NV_RESTART_TX;
3228                 nv_stop_tx(dev);
3229         }
3230         if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
3231                 txrxFlags |= NV_RESTART_RX;
3232                 nv_stop_rx(dev);
3233         }
3234
3235         if (np->gigabit == PHY_GIGABIT) {
3236                 phyreg = readl(base + NvRegSlotTime);
3237                 phyreg &= ~(0x3FF00);
3238                 if (((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) ||
3239                     ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100))
3240                         phyreg |= NVREG_SLOTTIME_10_100_FULL;
3241                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
3242                         phyreg |= NVREG_SLOTTIME_1000_FULL;
3243                 writel(phyreg, base + NvRegSlotTime);
3244         }
3245
3246         phyreg = readl(base + NvRegPhyInterface);
3247         phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
3248         if (np->duplex == 0)
3249                 phyreg |= PHY_HALF;
3250         if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
3251                 phyreg |= PHY_100;
3252         else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3253                 phyreg |= PHY_1000;
3254         writel(phyreg, base + NvRegPhyInterface);
3255
3256         phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */
3257         if (phyreg & PHY_RGMII) {
3258                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) {
3259                         txreg = NVREG_TX_DEFERRAL_RGMII_1000;
3260                 } else {
3261                         if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) {
3262                                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_10)
3263                                         txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10;
3264                                 else
3265                                         txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100;
3266                         } else {
3267                                 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
3268                         }
3269                 }
3270         } else {
3271                 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX))
3272                         txreg = NVREG_TX_DEFERRAL_MII_STRETCH;
3273                 else
3274                         txreg = NVREG_TX_DEFERRAL_DEFAULT;
3275         }
3276         writel(txreg, base + NvRegTxDeferral);
3277
3278         if (np->desc_ver == DESC_VER_1) {
3279                 txreg = NVREG_TX_WM_DESC1_DEFAULT;
3280         } else {
3281                 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3282                         txreg = NVREG_TX_WM_DESC2_3_1000;
3283                 else
3284                         txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
3285         }
3286         writel(txreg, base + NvRegTxWatermark);
3287
3288         writel(NVREG_MISC1_FORCE | (np->duplex ? 0 : NVREG_MISC1_HD),
3289                 base + NvRegMisc1);
3290         pci_push(base);
3291         writel(np->linkspeed, base + NvRegLinkSpeed);
3292         pci_push(base);
3293
3294         pause_flags = 0;
3295         /* setup pause frame */
3296         if (np->duplex != 0) {
3297                 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
3298                         adv_pause = adv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3299                         lpa_pause = lpa & (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
3300
3301                         switch (adv_pause) {
3302                         case ADVERTISE_PAUSE_CAP:
3303                                 if (lpa_pause & LPA_PAUSE_CAP) {
3304                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3305                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3306                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3307                                 }
3308                                 break;
3309                         case ADVERTISE_PAUSE_ASYM:
3310                                 if (lpa_pause == (LPA_PAUSE_CAP | LPA_PAUSE_ASYM))
3311                                         pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3312                                 break;
3313                         case ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM:
3314                                 if (lpa_pause & LPA_PAUSE_CAP) {
3315                                         pause_flags |=  NV_PAUSEFRAME_RX_ENABLE;
3316                                         if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3317                                                 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3318                                 }
3319                                 if (lpa_pause == LPA_PAUSE_ASYM)
3320                                         pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3321                                 break;
3322                         }
3323                 } else {
3324                         pause_flags = np->pause_flags;
3325                 }
3326         }
3327         nv_update_pause(dev, pause_flags);
3328
3329         if (txrxFlags & NV_RESTART_TX)
3330                 nv_start_tx(dev);
3331         if (txrxFlags & NV_RESTART_RX)
3332                 nv_start_rx(dev);
3333
3334         return retval;
3335 }
3336
3337 static void nv_linkchange(struct net_device *dev)
3338 {
3339         if (nv_update_linkspeed(dev)) {
3340                 if (!netif_carrier_ok(dev)) {
3341                         netif_carrier_on(dev);
3342                         netdev_info(dev, "link up\n");
3343                         nv_txrx_gate(dev, false);
3344                         nv_start_rx(dev);
3345                 }
3346         } else {
3347                 if (netif_carrier_ok(dev)) {
3348                         netif_carrier_off(dev);
3349                         netdev_info(dev, "link down\n");
3350                         nv_txrx_gate(dev, true);
3351                         nv_stop_rx(dev);
3352                 }
3353         }
3354 }
3355
3356 static void nv_link_irq(struct net_device *dev)
3357 {
3358         u8 __iomem *base = get_hwbase(dev);
3359         u32 miistat;
3360
3361         miistat = readl(base + NvRegMIIStatus);
3362         writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus);
3363
3364         if (miistat & (NVREG_MIISTAT_LINKCHANGE))
3365                 nv_linkchange(dev);
3366 }
3367
3368 static void nv_msi_workaround(struct fe_priv *np)
3369 {
3370
3371         /* Need to toggle the msi irq mask within the ethernet device,
3372          * otherwise, future interrupts will not be detected.
3373          */
3374         if (np->msi_flags & NV_MSI_ENABLED) {
3375                 u8 __iomem *base = np->base;
3376
3377                 writel(0, base + NvRegMSIIrqMask);
3378                 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3379         }
3380 }
3381
3382 static inline int nv_change_interrupt_mode(struct net_device *dev, int total_work)
3383 {
3384         struct fe_priv *np = netdev_priv(dev);
3385
3386         if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC) {
3387                 if (total_work > NV_DYNAMIC_THRESHOLD) {
3388                         /* transition to poll based interrupts */
3389                         np->quiet_count = 0;
3390                         if (np->irqmask != NVREG_IRQMASK_CPU) {
3391                                 np->irqmask = NVREG_IRQMASK_CPU;
3392                                 return 1;
3393                         }
3394                 } else {
3395                         if (np->quiet_count < NV_DYNAMIC_MAX_QUIET_COUNT) {
3396                                 np->quiet_count++;
3397                         } else {
3398                                 /* reached a period of low activity, switch
3399                                    to per tx/rx packet interrupts */
3400                                 if (np->irqmask != NVREG_IRQMASK_THROUGHPUT) {
3401                                         np->irqmask = NVREG_IRQMASK_THROUGHPUT;
3402                                         return 1;
3403                                 }
3404                         }
3405                 }
3406         }
3407         return 0;
3408 }
3409
3410 static irqreturn_t nv_nic_irq(int foo, void *data)
3411 {
3412         struct net_device *dev = (struct net_device *) data;
3413         struct fe_priv *np = netdev_priv(dev);
3414         u8 __iomem *base = get_hwbase(dev);
3415
3416         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3417                 np->events = readl(base + NvRegIrqStatus);
3418                 writel(np->events, base + NvRegIrqStatus);
3419         } else {
3420                 np->events = readl(base + NvRegMSIXIrqStatus);
3421                 writel(np->events, base + NvRegMSIXIrqStatus);
3422         }
3423         if (!(np->events & np->irqmask))
3424                 return IRQ_NONE;
3425
3426         nv_msi_workaround(np);
3427
3428         if (napi_schedule_prep(&np->napi)) {
3429                 /*
3430                  * Disable further irq's (msix not enabled with napi)
3431                  */
3432                 writel(0, base + NvRegIrqMask);
3433                 __napi_schedule(&np->napi);
3434         }
3435
3436         return IRQ_HANDLED;
3437 }
3438
3439 /**
3440  * All _optimized functions are used to help increase performance
3441  * (reduce CPU and increase throughput). They use descripter version 3,
3442  * compiler directives, and reduce memory accesses.
3443  */
3444 static irqreturn_t nv_nic_irq_optimized(int foo, void *data)
3445 {
3446         struct net_device *dev = (struct net_device *) data;
3447         struct fe_priv *np = netdev_priv(dev);
3448         u8 __iomem *base = get_hwbase(dev);
3449
3450         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3451                 np->events = readl(base + NvRegIrqStatus);
3452                 writel(np->events, base + NvRegIrqStatus);
3453         } else {
3454                 np->events = readl(base + NvRegMSIXIrqStatus);
3455                 writel(np->events, base + NvRegMSIXIrqStatus);
3456         }
3457         if (!(np->events & np->irqmask))
3458                 return IRQ_NONE;
3459
3460         nv_msi_workaround(np);
3461
3462         if (napi_schedule_prep(&np->napi)) {
3463                 /*
3464                  * Disable further irq's (msix not enabled with napi)
3465                  */
3466                 writel(0, base + NvRegIrqMask);
3467                 __napi_schedule(&np->napi);
3468         }
3469
3470         return IRQ_HANDLED;
3471 }
3472
3473 static irqreturn_t nv_nic_irq_tx(int foo, void *data)
3474 {
3475         struct net_device *dev = (struct net_device *) data;
3476         struct fe_priv *np = netdev_priv(dev);
3477         u8 __iomem *base = get_hwbase(dev);
3478         u32 events;
3479         int i;
3480         unsigned long flags;
3481
3482         for (i = 0;; i++) {
3483                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
3484                 writel(events, base + NvRegMSIXIrqStatus);
3485                 netdev_dbg(dev, "tx irq events: %08x\n", events);
3486                 if (!(events & np->irqmask))
3487                         break;
3488
3489                 spin_lock_irqsave(&np->lock, flags);
3490                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3491                 spin_unlock_irqrestore(&np->lock, flags);
3492
3493                 if (unlikely(i > max_interrupt_work)) {
3494                         spin_lock_irqsave(&np->lock, flags);
3495                         /* disable interrupts on the nic */
3496                         writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
3497                         pci_push(base);
3498
3499                         if (!np->in_shutdown) {
3500                                 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
3501                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3502                         }
3503                         spin_unlock_irqrestore(&np->lock, flags);
3504                         netdev_dbg(dev, "%s: too many iterations (%d)\n",
3505                                    __func__, i);
3506                         break;
3507                 }
3508
3509         }
3510
3511         return IRQ_RETVAL(i);
3512 }
3513
3514 static int nv_napi_poll(struct napi_struct *napi, int budget)
3515 {
3516         struct fe_priv *np = container_of(napi, struct fe_priv, napi);
3517         struct net_device *dev = np->dev;
3518         u8 __iomem *base = get_hwbase(dev);
3519         unsigned long flags;
3520         int retcode;
3521         int rx_count, tx_work = 0, rx_work = 0;
3522
3523         do {
3524                 if (!nv_optimized(np)) {
3525                         spin_lock_irqsave(&np->lock, flags);
3526                         tx_work += nv_tx_done(dev, np->tx_ring_size);
3527                         spin_unlock_irqrestore(&np->lock, flags);
3528
3529                         rx_count = nv_rx_process(dev, budget - rx_work);
3530                         retcode = nv_alloc_rx(dev);
3531                 } else {
3532                         spin_lock_irqsave(&np->lock, flags);
3533                         tx_work += nv_tx_done_optimized(dev, np->tx_ring_size);
3534                         spin_unlock_irqrestore(&np->lock, flags);
3535
3536                         rx_count = nv_rx_process_optimized(dev,
3537                             budget - rx_work);
3538                         retcode = nv_alloc_rx_optimized(dev);
3539                 }
3540         } while (retcode == 0 &&
3541                  rx_count > 0 && (rx_work += rx_count) < budget);
3542
3543         if (retcode) {
3544                 spin_lock_irqsave(&np->lock, flags);
3545                 if (!np->in_shutdown)
3546                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3547                 spin_unlock_irqrestore(&np->lock, flags);
3548         }
3549
3550         nv_change_interrupt_mode(dev, tx_work + rx_work);
3551
3552         if (unlikely(np->events & NVREG_IRQ_LINK)) {
3553                 spin_lock_irqsave(&np->lock, flags);
3554                 nv_link_irq(dev);
3555                 spin_unlock_irqrestore(&np->lock, flags);
3556         }
3557         if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3558                 spin_lock_irqsave(&np->lock, flags);
3559                 nv_linkchange(dev);
3560                 spin_unlock_irqrestore(&np->lock, flags);
3561                 np->link_timeout = jiffies + LINK_TIMEOUT;
3562         }
3563         if (unlikely(np->events & NVREG_IRQ_RECOVER_ERROR)) {
3564                 spin_lock_irqsave(&np->lock, flags);
3565                 if (!np->in_shutdown) {
3566                         np->nic_poll_irq = np->irqmask;
3567                         np->recover_error = 1;
3568                         mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3569                 }
3570                 spin_unlock_irqrestore(&np->lock, flags);
3571                 napi_complete(napi);
3572                 return rx_work;
3573         }
3574
3575         if (rx_work < budget) {
3576                 /* re-enable interrupts
3577                    (msix not enabled in napi) */
3578                 napi_complete(napi);
3579
3580                 writel(np->irqmask, base + NvRegIrqMask);
3581         }
3582         return rx_work;
3583 }
3584
3585 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3586 {
3587         struct net_device *dev = (struct net_device *) data;
3588         struct fe_priv *np = netdev_priv(dev);
3589         u8 __iomem *base = get_hwbase(dev);
3590         u32 events;
3591         int i;
3592         unsigned long flags;
3593
3594         for (i = 0;; i++) {
3595                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3596                 writel(events, base + NvRegMSIXIrqStatus);
3597                 netdev_dbg(dev, "rx irq events: %08x\n", events);
3598                 if (!(events & np->irqmask))
3599                         break;
3600
3601                 if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
3602                         if (unlikely(nv_alloc_rx_optimized(dev))) {
3603                                 spin_lock_irqsave(&np->lock, flags);
3604                                 if (!np->in_shutdown)
3605                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3606                                 spin_unlock_irqrestore(&np->lock, flags);
3607                         }
3608                 }
3609
3610                 if (unlikely(i > max_interrupt_work)) {
3611                         spin_lock_irqsave(&np->lock, flags);
3612                         /* disable interrupts on the nic */
3613                         writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3614                         pci_push(base);
3615
3616                         if (!np->in_shutdown) {
3617                                 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
3618                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3619                         }
3620                         spin_unlock_irqrestore(&np->lock, flags);
3621                         netdev_dbg(dev, "%s: too many iterations (%d)\n",
3622                                    __func__, i);
3623                         break;
3624                 }
3625         }
3626
3627         return IRQ_RETVAL(i);
3628 }
3629
3630 static irqreturn_t nv_nic_irq_other(int foo, void *data)
3631 {
3632         struct net_device *dev = (struct net_device *) data;
3633         struct fe_priv *np = netdev_priv(dev);
3634         u8 __iomem *base = get_hwbase(dev);
3635         u32 events;
3636         int i;
3637         unsigned long flags;
3638
3639         for (i = 0;; i++) {
3640                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
3641                 writel(events, base + NvRegMSIXIrqStatus);
3642                 netdev_dbg(dev, "irq events: %08x\n", events);
3643                 if (!(events & np->irqmask))
3644                         break;
3645
3646                 /* check tx in case we reached max loop limit in tx isr */
3647                 spin_lock_irqsave(&np->lock, flags);
3648                 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3649                 spin_unlock_irqrestore(&np->lock, flags);
3650
3651                 if (events & NVREG_IRQ_LINK) {
3652                         spin_lock_irqsave(&np->lock, flags);
3653                         nv_link_irq(dev);
3654                         spin_unlock_irqrestore(&np->lock, flags);
3655                 }
3656                 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
3657                         spin_lock_irqsave(&np->lock, flags);
3658                         nv_linkchange(dev);
3659                         spin_unlock_irqrestore(&np->lock, flags);
3660                         np->link_timeout = jiffies + LINK_TIMEOUT;
3661                 }
3662                 if (events & NVREG_IRQ_RECOVER_ERROR) {
3663                         spin_lock_irq(&np->lock);
3664                         /* disable interrupts on the nic */
3665                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3666                         pci_push(base);
3667
3668                         if (!np->in_shutdown) {
3669                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3670                                 np->recover_error = 1;
3671                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3672                         }
3673                         spin_unlock_irq(&np->lock);
3674                         break;
3675                 }
3676                 if (unlikely(i > max_interrupt_work)) {
3677                         spin_lock_irqsave(&np->lock, flags);
3678                         /* disable interrupts on the nic */
3679                         writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3680                         pci_push(base);
3681
3682                         if (!np->in_shutdown) {
3683                                 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3684                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3685                         }
3686                         spin_unlock_irqrestore(&np->lock, flags);
3687                         netdev_dbg(dev, "%s: too many iterations (%d)\n",
3688                                    __func__, i);
3689                         break;
3690                 }
3691
3692         }
3693
3694         return IRQ_RETVAL(i);
3695 }
3696
3697 static irqreturn_t nv_nic_irq_test(int foo, void *data)
3698 {
3699         struct net_device *dev = (struct net_device *) data;
3700         struct fe_priv *np = netdev_priv(dev);
3701         u8 __iomem *base = get_hwbase(dev);
3702         u32 events;
3703
3704         if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3705                 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3706                 writel(events & NVREG_IRQ_TIMER, base + NvRegIrqStatus);
3707         } else {
3708                 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3709                 writel(events & NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
3710         }
3711         pci_push(base);
3712         if (!(events & NVREG_IRQ_TIMER))
3713                 return IRQ_RETVAL(0);
3714
3715         nv_msi_workaround(np);
3716
3717         spin_lock(&np->lock);
3718         np->intr_test = 1;
3719         spin_unlock(&np->lock);
3720
3721         return IRQ_RETVAL(1);
3722 }
3723
3724 static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
3725 {
3726         u8 __iomem *base = get_hwbase(dev);
3727         int i;
3728         u32 msixmap = 0;
3729
3730         /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
3731          * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
3732          * the remaining 8 interrupts.
3733          */
3734         for (i = 0; i < 8; i++) {
3735                 if ((irqmask >> i) & 0x1)
3736                         msixmap |= vector << (i << 2);
3737         }
3738         writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
3739
3740         msixmap = 0;
3741         for (i = 0; i < 8; i++) {
3742                 if ((irqmask >> (i + 8)) & 0x1)
3743                         msixmap |= vector << (i << 2);
3744         }
3745         writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
3746 }
3747
3748 static int nv_request_irq(struct net_device *dev, int intr_test)
3749 {
3750         struct fe_priv *np = get_nvpriv(dev);
3751         u8 __iomem *base = get_hwbase(dev);
3752         int ret = 1;
3753         int i;
3754         irqreturn_t (*handler)(int foo, void *data);
3755
3756         if (intr_test) {
3757                 handler = nv_nic_irq_test;
3758         } else {
3759                 if (nv_optimized(np))
3760                         handler = nv_nic_irq_optimized;
3761                 else
3762                         handler = nv_nic_irq;
3763         }
3764
3765         if (np->msi_flags & NV_MSI_X_CAPABLE) {
3766                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++)
3767                         np->msi_x_entry[i].entry = i;
3768                 ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK));
3769                 if (ret == 0) {
3770                         np->msi_flags |= NV_MSI_X_ENABLED;
3771                         if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
3772                                 /* Request irq for rx handling */
3773                                 sprintf(np->name_rx, "%s-rx", dev->name);
3774                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector,
3775                                                 nv_nic_irq_rx, IRQF_SHARED, np->name_rx, dev) != 0) {
3776                                         netdev_info(dev,
3777                                                     "request_irq failed for rx %d\n",
3778                                                     ret);
3779                                         pci_disable_msix(np->pci_dev);
3780                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3781                                         goto out_err;
3782                                 }
3783                                 /* Request irq for tx handling */
3784                                 sprintf(np->name_tx, "%s-tx", dev->name);
3785                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector,
3786                                                 nv_nic_irq_tx, IRQF_SHARED, np->name_tx, dev) != 0) {
3787                                         netdev_info(dev,
3788                                                     "request_irq failed for tx %d\n",
3789                                                     ret);
3790                                         pci_disable_msix(np->pci_dev);
3791                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3792                                         goto out_free_rx;
3793                                 }
3794                                 /* Request irq for link and timer handling */
3795                                 sprintf(np->name_other, "%s-other", dev->name);
3796                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector,
3797                                                 nv_nic_irq_other, IRQF_SHARED, np->name_other, dev) != 0) {
3798                                         netdev_info(dev,
3799                                                     "request_irq failed for link %d\n",
3800                                                     ret);
3801                                         pci_disable_msix(np->pci_dev);
3802                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3803                                         goto out_free_tx;
3804                                 }
3805                                 /* map interrupts to their respective vector */
3806                                 writel(0, base + NvRegMSIXMap0);
3807                                 writel(0, base + NvRegMSIXMap1);
3808                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
3809                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
3810                                 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
3811                         } else {
3812                                 /* Request irq for all interrupts */
3813                                 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) {
3814                                         netdev_info(dev,
3815                                                     "request_irq failed %d\n",
3816                                                     ret);
3817                                         pci_disable_msix(np->pci_dev);
3818                                         np->msi_flags &= ~NV_MSI_X_ENABLED;
3819                                         goto out_err;
3820                                 }
3821
3822                                 /* map interrupts to vector 0 */
3823                                 writel(0, base + NvRegMSIXMap0);
3824                                 writel(0, base + NvRegMSIXMap1);
3825                         }
3826                         netdev_info(dev, "MSI-X enabled\n");
3827                 }
3828         }
3829         if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
3830                 ret = pci_enable_msi(np->pci_dev);
3831                 if (ret == 0) {
3832                         np->msi_flags |= NV_MSI_ENABLED;
3833                         dev->irq = np->pci_dev->irq;
3834                         if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) {
3835                                 netdev_info(dev, "request_irq failed %d\n",
3836                                             ret);
3837                                 pci_disable_msi(np->pci_dev);
3838                                 np->msi_flags &= ~NV_MSI_ENABLED;
3839                                 dev->irq = np->pci_dev->irq;
3840                                 goto out_err;
3841                         }
3842
3843                         /* map interrupts to vector 0 */
3844                         writel(0, base + NvRegMSIMap0);
3845                         writel(0, base + NvRegMSIMap1);
3846                         /* enable msi vector 0 */
3847                         writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3848                         netdev_info(dev, "MSI enabled\n");
3849                 }
3850         }
3851         if (ret != 0) {
3852                 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0)
3853                         goto out_err;
3854
3855         }
3856
3857         return 0;
3858 out_free_tx:
3859         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
3860 out_free_rx:
3861         free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
3862 out_err:
3863         return 1;
3864 }
3865
3866 static void nv_free_irq(struct net_device *dev)
3867 {
3868         struct fe_priv *np = get_nvpriv(dev);
3869         int i;
3870
3871         if (np->msi_flags & NV_MSI_X_ENABLED) {
3872                 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++)
3873                         free_irq(np->msi_x_entry[i].vector, dev);
3874                 pci_disable_msix(np->pci_dev);
3875                 np->msi_flags &= ~NV_MSI_X_ENABLED;
3876         } else {
3877                 free_irq(np->pci_dev->irq, dev);
3878                 if (np->msi_flags & NV_MSI_ENABLED) {
3879                         pci_disable_msi(np->pci_dev);
3880                         np->msi_flags &= ~NV_MSI_ENABLED;
3881                 }
3882         }
3883 }
3884
3885 static void nv_do_nic_poll(unsigned long data)
3886 {
3887         struct net_device *dev = (struct net_device *) data;
3888         struct fe_priv *np = netdev_priv(dev);
3889         u8 __iomem *base = get_hwbase(dev);
3890         u32 mask = 0;
3891
3892         /*
3893          * First disable irq(s) and then
3894          * reenable interrupts on the nic, we have to do this before calling
3895          * nv_nic_irq because that may decide to do otherwise
3896          */
3897
3898         if (!using_multi_irqs(dev)) {
3899                 if (np->msi_flags & NV_MSI_X_ENABLED)
3900                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
3901                 else
3902                         disable_irq_lockdep(np->pci_dev->irq);
3903                 mask = np->irqmask;
3904         } else {
3905                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
3906                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
3907                         mask |= NVREG_IRQ_RX_ALL;
3908                 }
3909                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
3910                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
3911                         mask |= NVREG_IRQ_TX_ALL;
3912                 }
3913                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
3914                         disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
3915                         mask |= NVREG_IRQ_OTHER;
3916                 }
3917         }
3918         /* disable_irq() contains synchronize_irq, thus no irq handler can run now */
3919
3920         if (np->recover_error) {
3921                 np->recover_error = 0;
3922                 netdev_info(dev, "MAC in recoverable error state\n");
3923                 if (netif_running(dev)) {
3924                         netif_tx_lock_bh(dev);
3925                         netif_addr_lock(dev);
3926                         spin_lock(&np->lock);
3927                         /* stop engines */
3928                         nv_stop_rxtx(dev);
3929                         if (np->driver_data & DEV_HAS_POWER_CNTRL)
3930                                 nv_mac_reset(dev);
3931                         nv_txrx_reset(dev);
3932                         /* drain rx queue */
3933                         nv_drain_rxtx(dev);
3934                         /* reinit driver view of the rx queue */
3935                         set_bufsize(dev);
3936                         if (nv_init_ring(dev)) {
3937                                 if (!np->in_shutdown)
3938                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3939                         }
3940                         /* reinit nic view of the rx queue */
3941                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3942                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3943                         writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3944                                 base + NvRegRingSizes);
3945                         pci_push(base);
3946                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3947                         pci_push(base);
3948                         /* clear interrupts */
3949                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
3950                                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3951                         else
3952                                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3953
3954                         /* restart rx engine */
3955                         nv_start_rxtx(dev);
3956                         spin_unlock(&np->lock);
3957                         netif_addr_unlock(dev);
3958                         netif_tx_unlock_bh(dev);
3959                 }
3960         }
3961
3962         writel(mask, base + NvRegIrqMask);
3963         pci_push(base);
3964
3965         if (!using_multi_irqs(dev)) {
3966                 np->nic_poll_irq = 0;
3967                 if (nv_optimized(np))
3968                         nv_nic_irq_optimized(0, dev);
3969                 else
3970                         nv_nic_irq(0, dev);
3971                 if (np->msi_flags & NV_MSI_X_ENABLED)
3972                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
3973                 else
3974                         enable_irq_lockdep(np->pci_dev->irq);
3975         } else {
3976                 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
3977                         np->nic_poll_irq &= ~NVREG_IRQ_RX_ALL;
3978                         nv_nic_irq_rx(0, dev);
3979                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
3980                 }
3981                 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
3982                         np->nic_poll_irq &= ~NVREG_IRQ_TX_ALL;
3983                         nv_nic_irq_tx(0, dev);
3984                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
3985                 }
3986                 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
3987                         np->nic_poll_irq &= ~NVREG_IRQ_OTHER;
3988                         nv_nic_irq_other(0, dev);
3989                         enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
3990                 }
3991         }
3992
3993 }
3994
3995 #ifdef CONFIG_NET_POLL_CONTROLLER
3996 static void nv_poll_controller(struct net_device *dev)
3997 {
3998         nv_do_nic_poll((unsigned long) dev);
3999 }
4000 #endif
4001
4002 static void nv_do_stats_poll(unsigned long data)
4003 {
4004         struct net_device *dev = (struct net_device *) data;
4005         struct fe_priv *np = netdev_priv(dev);
4006
4007         nv_get_hw_stats(dev);
4008
4009         if (!np->in_shutdown)
4010                 mod_timer(&np->stats_poll,
4011                         round_jiffies(jiffies + STATS_INTERVAL));
4012 }
4013
4014 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4015 {
4016         struct fe_priv *np = netdev_priv(dev);
4017         strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
4018         strlcpy(info->version, FORCEDETH_VERSION, sizeof(info->version));
4019         strlcpy(info->bus_info, pci_name(np->pci_dev), sizeof(info->bus_info));
4020 }
4021
4022 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4023 {
4024         struct fe_priv *np = netdev_priv(dev);
4025         wolinfo->supported = WAKE_MAGIC;
4026
4027         spin_lock_irq(&np->lock);
4028         if (np->wolenabled)
4029                 wolinfo->wolopts = WAKE_MAGIC;
4030         spin_unlock_irq(&np->lock);
4031 }
4032
4033 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4034 {
4035         struct fe_priv *np = netdev_priv(dev);
4036         u8 __iomem *base = get_hwbase(dev);
4037         u32 flags = 0;
4038
4039         if (wolinfo->wolopts == 0) {
4040                 np->wolenabled = 0;
4041         } else if (wolinfo->wolopts & WAKE_MAGIC) {
4042                 np->wolenabled = 1;
4043                 flags = NVREG_WAKEUPFLAGS_ENABLE;
4044         }
4045         if (netif_running(dev)) {
4046                 spin_lock_irq(&np->lock);
4047                 writel(flags, base + NvRegWakeUpFlags);
4048                 spin_unlock_irq(&np->lock);
4049         }
4050         device_set_wakeup_enable(&np->pci_dev->dev, np->wolenabled);
4051         return 0;
4052 }
4053
4054 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4055 {
4056         struct fe_priv *np = netdev_priv(dev);
4057         u32 speed;
4058         int adv;
4059
4060         spin_lock_irq(&np->lock);
4061         ecmd->port = PORT_MII;
4062         if (!netif_running(dev)) {
4063                 /* We do not track link speed / duplex setting if the
4064                  * interface is disabled. Force a link check */
4065                 if (nv_update_linkspeed(dev)) {
4066                         if (!netif_carrier_ok(dev))
4067                                 netif_carrier_on(dev);
4068                 } else {
4069                         if (netif_carrier_ok(dev))
4070                                 netif_carrier_off(dev);
4071                 }
4072         }
4073
4074         if (netif_carrier_ok(dev)) {
4075                 switch (np->linkspeed & (NVREG_LINKSPEED_MASK)) {
4076                 case NVREG_LINKSPEED_10:
4077                         speed = SPEED_10;
4078                         break;
4079                 case NVREG_LINKSPEED_100:
4080                         speed = SPEED_100;
4081                         break;
4082                 case NVREG_LINKSPEED_1000:
4083                         speed = SPEED_1000;
4084                         break;
4085                 default:
4086                         speed = -1;
4087                         break;
4088                 }
4089                 ecmd->duplex = DUPLEX_HALF;
4090                 if (np->duplex)
4091                         ecmd->duplex = DUPLEX_FULL;
4092         } else {
4093                 speed = -1;
4094                 ecmd->duplex = -1;
4095         }
4096         ethtool_cmd_speed_set(ecmd, speed);
4097         ecmd->autoneg = np->autoneg;
4098
4099         ecmd->advertising = ADVERTISED_MII;
4100         if (np->autoneg) {
4101                 ecmd->advertising |= ADVERTISED_Autoneg;
4102                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4103                 if (adv & ADVERTISE_10HALF)
4104                         ecmd->advertising |= ADVERTISED_10baseT_Half;
4105                 if (adv & ADVERTISE_10FULL)
4106                         ecmd->advertising |= ADVERTISED_10baseT_Full;
4107                 if (adv & ADVERTISE_100HALF)
4108                         ecmd->advertising |= ADVERTISED_100baseT_Half;
4109                 if (adv & ADVERTISE_100FULL)
4110                         ecmd->advertising |= ADVERTISED_100baseT_Full;
4111                 if (np->gigabit == PHY_GIGABIT) {
4112                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4113                         if (adv & ADVERTISE_1000FULL)
4114                                 ecmd->advertising |= ADVERTISED_1000baseT_Full;
4115                 }
4116         }
4117         ecmd->supported = (SUPPORTED_Autoneg |
4118                 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
4119                 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
4120                 SUPPORTED_MII);
4121         if (np->gigabit == PHY_GIGABIT)
4122                 ecmd->supported |= SUPPORTED_1000baseT_Full;
4123
4124         ecmd->phy_address = np->phyaddr;
4125         ecmd->transceiver = XCVR_EXTERNAL;
4126
4127         /* ignore maxtxpkt, maxrxpkt for now */
4128         spin_unlock_irq(&np->lock);
4129         return 0;
4130 }
4131
4132 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4133 {
4134         struct fe_priv *np = netdev_priv(dev);
4135         u32 speed = ethtool_cmd_speed(ecmd);
4136
4137         if (ecmd->port != PORT_MII)
4138                 return -EINVAL;
4139         if (ecmd->transceiver != XCVR_EXTERNAL)
4140                 return -EINVAL;
4141         if (ecmd->phy_address != np->phyaddr) {
4142                 /* TODO: support switching between multiple phys. Should be
4143                  * trivial, but not enabled due to lack of test hardware. */
4144                 return -EINVAL;
4145         }
4146         if (ecmd->autoneg == AUTONEG_ENABLE) {
4147                 u32 mask;
4148
4149                 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4150                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4151                 if (np->gigabit == PHY_GIGABIT)
4152                         mask |= ADVERTISED_1000baseT_Full;
4153
4154                 if ((ecmd->advertising & mask) == 0)
4155                         return -EINVAL;
4156
4157         } else if (ecmd->autoneg == AUTONEG_DISABLE) {
4158                 /* Note: autonegotiation disable, speed 1000 intentionally
4159                  * forbidden - no one should need that. */
4160
4161                 if (speed != SPEED_10 && speed != SPEED_100)
4162                         return -EINVAL;
4163                 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
4164                         return -EINVAL;
4165         } else {
4166                 return -EINVAL;
4167         }
4168
4169         netif_carrier_off(dev);
4170         if (netif_running(dev)) {
4171                 unsigned long flags;
4172
4173                 nv_disable_irq(dev);
4174                 netif_tx_lock_bh(dev);
4175                 netif_addr_lock(dev);
4176                 /* with plain spinlock lockdep complains */
4177                 spin_lock_irqsave(&np->lock, flags);
4178                 /* stop engines */
4179                 /* FIXME:
4180                  * this can take some time, and interrupts are disabled
4181                  * due to spin_lock_irqsave, but let's hope no daemon
4182                  * is going to change the settings very often...
4183                  * Worst case:
4184                  * NV_RXSTOP_DELAY1MAX + NV_TXSTOP_DELAY1MAX
4185                  * + some minor delays, which is up to a second approximately
4186                  */
4187                 nv_stop_rxtx(dev);
4188                 spin_unlock_irqrestore(&np->lock, flags);
4189                 netif_addr_unlock(dev);
4190                 netif_tx_unlock_bh(dev);
4191         }
4192
4193         if (ecmd->autoneg == AUTONEG_ENABLE) {
4194                 int adv, bmcr;
4195
4196                 np->autoneg = 1;
4197
4198                 /* advertise only what has been requested */
4199                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4200                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4201                 if (ecmd->advertising & ADVERTISED_10baseT_Half)
4202                         adv |= ADVERTISE_10HALF;
4203                 if (ecmd->advertising & ADVERTISED_10baseT_Full)
4204                         adv |= ADVERTISE_10FULL;
4205                 if (ecmd->advertising & ADVERTISED_100baseT_Half)
4206                         adv |= ADVERTISE_100HALF;
4207                 if (ecmd->advertising & ADVERTISED_100baseT_Full)
4208                         adv |= ADVERTISE_100FULL;
4209                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ)  /* for rx we set both advertisements but disable tx pause */
4210                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4211                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4212                         adv |=  ADVERTISE_PAUSE_ASYM;
4213                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4214
4215                 if (np->gigabit == PHY_GIGABIT) {
4216                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4217                         adv &= ~ADVERTISE_1000FULL;
4218                         if (ecmd->advertising & ADVERTISED_1000baseT_Full)
4219                                 adv |= ADVERTISE_1000FULL;
4220                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4221                 }
4222
4223                 if (netif_running(dev))
4224                         netdev_info(dev, "link down\n");
4225                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4226                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4227                         bmcr |= BMCR_ANENABLE;
4228                         /* reset the phy in order for settings to stick,
4229                          * and cause autoneg to start */
4230                         if (phy_reset(dev, bmcr)) {
4231                                 netdev_info(dev, "phy reset failed\n");
4232                                 return -EINVAL;
4233                         }
4234                 } else {
4235                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4236                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4237                 }
4238         } else {
4239                 int adv, bmcr;
4240
4241                 np->autoneg = 0;
4242
4243                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4244                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4245                 if (speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
4246                         adv |= ADVERTISE_10HALF;
4247                 if (speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
4248                         adv |= ADVERTISE_10FULL;
4249                 if (speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
4250                         adv |= ADVERTISE_100HALF;
4251                 if (speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
4252                         adv |= ADVERTISE_100FULL;
4253                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4254                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisements but disable tx pause */
4255                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4256                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4257                 }
4258                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
4259                         adv |=  ADVERTISE_PAUSE_ASYM;
4260                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4261                 }
4262                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4263                 np->fixed_mode = adv;
4264
4265                 if (np->gigabit == PHY_GIGABIT) {
4266                         adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4267                         adv &= ~ADVERTISE_1000FULL;
4268                         mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4269                 }
4270
4271                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4272                 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
4273                 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
4274                         bmcr |= BMCR_FULLDPLX;
4275                 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
4276                         bmcr |= BMCR_SPEED100;
4277                 if (np->phy_oui == PHY_OUI_MARVELL) {
4278                         /* reset the phy in order for forced mode settings to stick */
4279                         if (phy_reset(dev, bmcr)) {
4280                                 netdev_info(dev, "phy reset failed\n");
4281                                 return -EINVAL;
4282                         }
4283                 } else {
4284                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4285                         if (netif_running(dev)) {
4286                                 /* Wait a bit and then reconfigure the nic. */
4287                                 udelay(10);
4288                                 nv_linkchange(dev);
4289                         }
4290                 }
4291         }
4292
4293         if (netif_running(dev)) {
4294                 nv_start_rxtx(dev);
4295                 nv_enable_irq(dev);
4296         }
4297
4298         return 0;
4299 }
4300
4301 #define FORCEDETH_REGS_VER      1
4302
4303 static int nv_get_regs_len(struct net_device *dev)
4304 {
4305         struct fe_priv *np = netdev_priv(dev);
4306         return np->register_size;
4307 }
4308
4309 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
4310 {
4311         struct fe_priv *np = netdev_priv(dev);
4312         u8 __iomem *base = get_hwbase(dev);
4313         u32 *rbuf = buf;
4314         int i;
4315
4316         regs->version = FORCEDETH_REGS_VER;
4317         spin_lock_irq(&np->lock);
4318         for (i = 0; i <= np->register_size/sizeof(u32); i++)
4319                 rbuf[i] = readl(base + i*sizeof(u32));
4320         spin_unlock_irq(&np->lock);
4321 }
4322
4323 static int nv_nway_reset(struct net_device *dev)
4324 {
4325         struct fe_priv *np = netdev_priv(dev);
4326         int ret;
4327
4328         if (np->autoneg) {
4329                 int bmcr;
4330
4331                 netif_carrier_off(dev);
4332                 if (netif_running(dev)) {
4333                         nv_disable_irq(dev);
4334                         netif_tx_lock_bh(dev);
4335                         netif_addr_lock(dev);
4336                         spin_lock(&np->lock);
4337                         /* stop engines */
4338                         nv_stop_rxtx(dev);
4339                         spin_unlock(&np->lock);
4340                         netif_addr_unlock(dev);
4341                         netif_tx_unlock_bh(dev);
4342                         netdev_info(dev, "link down\n");
4343                 }
4344
4345                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4346                 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4347                         bmcr |= BMCR_ANENABLE;
4348                         /* reset the phy in order for settings to stick*/
4349                         if (phy_reset(dev, bmcr)) {
4350                                 netdev_info(dev, "phy reset failed\n");
4351                                 return -EINVAL;
4352                         }
4353                 } else {
4354                         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4355                         mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4356                 }
4357
4358                 if (netif_running(dev)) {
4359                         nv_start_rxtx(dev);
4360                         nv_enable_irq(dev);
4361                 }
4362                 ret = 0;
4363         } else {
4364                 ret = -EINVAL;
4365         }
4366
4367         return ret;
4368 }
4369
4370 static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4371 {
4372         struct fe_priv *np = netdev_priv(dev);
4373
4374         ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4375         ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4376
4377         ring->rx_pending = np->rx_ring_size;
4378         ring->tx_pending = np->tx_ring_size;
4379 }
4380
4381 static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4382 {
4383         struct fe_priv *np = netdev_priv(dev);
4384         u8 __iomem *base = get_hwbase(dev);
4385         u8 *rxtx_ring, *rx_skbuff, *tx_skbuff;
4386         dma_addr_t ring_addr;
4387
4388         if (ring->rx_pending < RX_RING_MIN ||
4389             ring->tx_pending < TX_RING_MIN ||
4390             ring->rx_mini_pending != 0 ||
4391             ring->rx_jumbo_pending != 0 ||
4392             (np->desc_ver == DESC_VER_1 &&
4393              (ring->rx_pending > RING_MAX_DESC_VER_1 ||
4394               ring->tx_pending > RING_MAX_DESC_VER_1)) ||
4395             (np->desc_ver != DESC_VER_1 &&
4396              (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
4397               ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
4398                 return -EINVAL;
4399         }
4400
4401         /* allocate new rings */
4402         if (!nv_optimized(np)) {
4403                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4404                                             sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4405                                             &ring_addr);
4406         } else {
4407                 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4408                                             sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4409                                             &ring_addr);
4410         }
4411         rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL);
4412         tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL);
4413         if (!rxtx_ring || !rx_skbuff || !tx_skbuff) {
4414                 /* fall back to old rings */
4415                 if (!nv_optimized(np)) {
4416                         if (rxtx_ring)
4417                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4418                                                     rxtx_ring, ring_addr);
4419                 } else {
4420                         if (rxtx_ring)
4421                                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4422                                                     rxtx_ring, ring_addr);
4423                 }
4424
4425                 kfree(rx_skbuff);
4426                 kfree(tx_skbuff);
4427                 goto exit;
4428         }
4429
4430         if (netif_running(dev)) {
4431                 nv_disable_irq(dev);
4432                 nv_napi_disable(dev);
4433                 netif_tx_lock_bh(dev);
4434                 netif_addr_lock(dev);
4435                 spin_lock(&np->lock);
4436                 /* stop engines */
4437                 nv_stop_rxtx(dev);
4438                 nv_txrx_reset(dev);
4439                 /* drain queues */
4440                 nv_drain_rxtx(dev);
4441                 /* delete queues */
4442                 free_rings(dev);
4443         }
4444
4445         /* set new values */
4446         np->rx_ring_size = ring->rx_pending;
4447         np->tx_ring_size = ring->tx_pending;
4448
4449         if (!nv_optimized(np)) {
4450                 np->rx_ring.orig = (struct ring_desc *)rxtx_ring;
4451                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4452         } else {
4453                 np->rx_ring.ex = (struct ring_desc_ex *)rxtx_ring;
4454                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4455         }
4456         np->rx_skb = (struct nv_skb_map *)rx_skbuff;
4457         np->tx_skb = (struct nv_skb_map *)tx_skbuff;
4458         np->ring_addr = ring_addr;
4459
4460         memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
4461         memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
4462
4463         if (netif_running(dev)) {
4464                 /* reinit driver view of the queues */
4465                 set_bufsize(dev);
4466                 if (nv_init_ring(dev)) {
4467                         if (!np->in_shutdown)
4468                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4469                 }
4470
4471                 /* reinit nic view of the queues */
4472                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4473                 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4474                 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4475                         base + NvRegRingSizes);
4476                 pci_push(base);
4477                 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4478                 pci_push(base);
4479
4480                 /* restart engines */
4481                 nv_start_rxtx(dev);
4482                 spin_unlock(&np->lock);
4483                 netif_addr_unlock(dev);
4484                 netif_tx_unlock_bh(dev);
4485                 nv_napi_enable(dev);
4486                 nv_enable_irq(dev);
4487         }
4488         return 0;
4489 exit:
4490         return -ENOMEM;
4491 }
4492
4493 static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4494 {
4495         struct fe_priv *np = netdev_priv(dev);
4496
4497         pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
4498         pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
4499         pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
4500 }
4501
4502 static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4503 {
4504         struct fe_priv *np = netdev_priv(dev);
4505         int adv, bmcr;
4506
4507         if ((!np->autoneg && np->duplex == 0) ||
4508             (np->autoneg && !pause->autoneg && np->duplex == 0)) {
4509                 netdev_info(dev, "can not set pause settings when forced link is in half duplex\n");
4510                 return -EINVAL;
4511         }
4512         if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
4513                 netdev_info(dev, "hardware does not support tx pause frames\n");
4514                 return -EINVAL;
4515         }
4516
4517         netif_carrier_off(dev);
4518         if (netif_running(dev)) {
4519                 nv_disable_irq(dev);
4520                 netif_tx_lock_bh(dev);
4521                 netif_addr_lock(dev);
4522                 spin_lock(&np->lock);
4523                 /* stop engines */
4524                 nv_stop_rxtx(dev);
4525                 spin_unlock(&np->lock);
4526                 netif_addr_unlock(dev);
4527                 netif_tx_unlock_bh(dev);
4528         }
4529
4530         np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
4531         if (pause->rx_pause)
4532                 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
4533         if (pause->tx_pause)
4534                 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
4535
4536         if (np->autoneg && pause->autoneg) {
4537                 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
4538
4539                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4540                 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4541                 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisements but disable tx pause */
4542                         adv |=  ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4543                 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4544                         adv |=  ADVERTISE_PAUSE_ASYM;
4545                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4546
4547                 if (netif_running(dev))
4548                         netdev_info(dev, "link down\n");
4549                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4550                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4551                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4552         } else {
4553                 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4554                 if (pause->rx_pause)
4555                         np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4556                 if (pause->tx_pause)
4557                         np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4558
4559                 if (!netif_running(dev))
4560                         nv_update_linkspeed(dev);
4561                 else
4562                         nv_update_pause(dev, np->pause_flags);
4563         }
4564
4565         if (netif_running(dev)) {
4566                 nv_start_rxtx(dev);
4567                 nv_enable_irq(dev);
4568         }
4569         return 0;
4570 }
4571
4572 static int nv_set_loopback(struct net_device *dev, netdev_features_t features)
4573 {
4574         struct fe_priv *np = netdev_priv(dev);
4575         unsigned long flags;
4576         u32 miicontrol;
4577         int err, retval = 0;
4578
4579         spin_lock_irqsave(&np->lock, flags);
4580         miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4581         if (features & NETIF_F_LOOPBACK) {
4582                 if (miicontrol & BMCR_LOOPBACK) {
4583                         spin_unlock_irqrestore(&np->lock, flags);
4584                         netdev_info(dev, "Loopback already enabled\n");
4585                         return 0;
4586                 }
4587                 nv_disable_irq(dev);
4588                 /* Turn on loopback mode */
4589                 miicontrol |= BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
4590                 err = mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol);
4591                 if (err) {
4592                         retval = PHY_ERROR;
4593                         spin_unlock_irqrestore(&np->lock, flags);
4594                         phy_init(dev);
4595                 } else {
4596                         if (netif_running(dev)) {
4597                                 /* Force 1000 Mbps full-duplex */
4598                                 nv_force_linkspeed(dev, NVREG_LINKSPEED_1000,
4599                                                                          1);
4600                                 /* Force link up */
4601                                 netif_carrier_on(dev);
4602                         }
4603                         spin_unlock_irqrestore(&np->lock, flags);
4604                         netdev_info(dev,
4605                                 "Internal PHY loopback mode enabled.\n");
4606                 }
4607         } else {
4608                 if (!(miicontrol & BMCR_LOOPBACK)) {
4609                         spin_unlock_irqrestore(&np->lock, flags);
4610                         netdev_info(dev, "Loopback already disabled\n");
4611                         return 0;
4612                 }
4613                 nv_disable_irq(dev);
4614                 /* Turn off loopback */
4615                 spin_unlock_irqrestore(&np->lock, flags);
4616                 netdev_info(dev, "Internal PHY loopback mode disabled.\n");
4617                 phy_init(dev);
4618         }
4619         msleep(500);
4620         spin_lock_irqsave(&np->lock, flags);
4621         nv_enable_irq(dev);
4622         spin_unlock_irqrestore(&np->lock, flags);
4623
4624         return retval;
4625 }
4626
4627 static netdev_features_t nv_fix_features(struct net_device *dev,
4628         netdev_features_t features)
4629 {
4630         /* vlan is dependent on rx checksum offload */
4631         if (features & (NETIF_F_HW_VLAN_TX|NETIF_F_HW_VLAN_RX))
4632                 features |= NETIF_F_RXCSUM;
4633
4634         return features;
4635 }
4636
4637 static void nv_vlan_mode(struct net_device *dev, netdev_features_t features)
4638 {
4639         struct fe_priv *np = get_nvpriv(dev);
4640
4641         spin_lock_irq(&np->lock);
4642
4643         if (features & NETIF_F_HW_VLAN_RX)
4644                 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP;
4645         else
4646                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
4647
4648         if (features & NETIF_F_HW_VLAN_TX)
4649                 np->txrxctl_bits |= NVREG_TXRXCTL_VLANINS;
4650         else
4651                 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
4652
4653         writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4654
4655         spin_unlock_irq(&np->lock);
4656 }
4657
4658 static int nv_set_features(struct net_device *dev, netdev_features_t features)
4659 {
4660         struct fe_priv *np = netdev_priv(dev);
4661         u8 __iomem *base = get_hwbase(dev);
4662         netdev_features_t changed = dev->features ^ features;
4663         int retval;
4664
4665         if ((changed & NETIF_F_LOOPBACK) && netif_running(dev)) {
4666                 retval = nv_set_loopback(dev, features);
4667                 if (retval != 0)
4668                         return retval;
4669         }
4670
4671         if (changed & NETIF_F_RXCSUM) {
4672                 spin_lock_irq(&np->lock);
4673
4674                 if (features & NETIF_F_RXCSUM)
4675                         np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4676                 else
4677                         np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
4678
4679                 if (netif_running(dev))
4680                         writel(np->txrxctl_bits, base + NvRegTxRxControl);
4681
4682                 spin_unlock_irq(&np->lock);
4683         }
4684
4685         if (changed & (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX))
4686                 nv_vlan_mode(dev, features);
4687
4688         return 0;
4689 }
4690
4691 static int nv_get_sset_count(struct net_device *dev, int sset)
4692 {
4693         struct fe_priv *np = netdev_priv(dev);
4694
4695         switch (sset) {
4696         case ETH_SS_TEST:
4697                 if (np->driver_data & DEV_HAS_TEST_EXTENDED)
4698                         return NV_TEST_COUNT_EXTENDED;
4699                 else
4700                         return NV_TEST_COUNT_BASE;
4701         case ETH_SS_STATS:
4702                 if (np->driver_data & DEV_HAS_STATISTICS_V3)
4703                         return NV_DEV_STATISTICS_V3_COUNT;
4704                 else if (np->driver_data & DEV_HAS_STATISTICS_V2)
4705                         return NV_DEV_STATISTICS_V2_COUNT;
4706                 else if (np->driver_data & DEV_HAS_STATISTICS_V1)
4707                         return NV_DEV_STATISTICS_V1_COUNT;
4708                 else
4709                         return 0;
4710         default:
4711                 return -EOPNOTSUPP;
4712         }
4713 }
4714
4715 static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer)
4716 {
4717         struct fe_priv *np = netdev_priv(dev);
4718
4719         /* update stats */
4720         nv_get_hw_stats(dev);
4721
4722         memcpy(buffer, &np->estats, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(u64));
4723 }
4724
4725 static int nv_link_test(struct net_device *dev)
4726 {
4727         struct fe_priv *np = netdev_priv(dev);
4728         int mii_status;
4729
4730         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4731         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4732
4733         /* check phy link status */
4734         if (!(mii_status & BMSR_LSTATUS))
4735                 return 0;
4736         else
4737                 return 1;
4738 }
4739
4740 static int nv_register_test(struct net_device *dev)
4741 {
4742         u8 __iomem *base = get_hwbase(dev);
4743         int i = 0;
4744         u32 orig_read, new_read;
4745
4746         do {
4747                 orig_read = readl(base + nv_registers_test[i].reg);
4748
4749                 /* xor with mask to toggle bits */
4750                 orig_read ^= nv_registers_test[i].mask;
4751
4752                 writel(orig_read, base + nv_registers_test[i].reg);
4753
4754                 new_read = readl(base + nv_registers_test[i].reg);
4755
4756                 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
4757                         return 0;
4758
4759                 /* restore original value */
4760                 orig_read ^= nv_registers_test[i].mask;
4761                 writel(orig_read, base + nv_registers_test[i].reg);
4762
4763         } while (nv_registers_test[++i].reg != 0);
4764
4765         return 1;
4766 }
4767
4768 static int nv_interrupt_test(struct net_device *dev)
4769 {
4770         struct fe_priv *np = netdev_priv(dev);
4771         u8 __iomem *base = get_hwbase(dev);
4772         int ret = 1;
4773         int testcnt;
4774         u32 save_msi_flags, save_poll_interval = 0;
4775
4776         if (netif_running(dev)) {
4777                 /* free current irq */
4778                 nv_free_irq(dev);
4779                 save_poll_interval = readl(base+NvRegPollingInterval);
4780         }
4781
4782         /* flag to test interrupt handler */
4783         np->intr_test = 0;
4784
4785         /* setup test irq */
4786         save_msi_flags = np->msi_flags;
4787         np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
4788         np->msi_flags |= 0x001; /* setup 1 vector */
4789         if (nv_request_irq(dev, 1))
4790                 return 0;
4791
4792         /* setup timer interrupt */
4793         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4794         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4795
4796         nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4797
4798         /* wait for at least one interrupt */
4799         msleep(100);
4800
4801         spin_lock_irq(&np->lock);
4802
4803         /* flag should be set within ISR */
4804         testcnt = np->intr_test;
4805         if (!testcnt)
4806                 ret = 2;
4807
4808         nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4809         if (!(np->msi_flags & NV_MSI_X_ENABLED))
4810                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4811         else
4812                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4813
4814         spin_unlock_irq(&np->lock);
4815
4816         nv_free_irq(dev);
4817
4818         np->msi_flags = save_msi_flags;
4819
4820         if (netif_running(dev)) {
4821                 writel(save_poll_interval, base + NvRegPollingInterval);
4822                 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4823                 /* restore original irq */
4824                 if (nv_request_irq(dev, 0))
4825                         return 0;
4826         }
4827
4828         return ret;
4829 }
4830
4831 static int nv_loopback_test(struct net_device *dev)
4832 {
4833         struct fe_priv *np = netdev_priv(dev);
4834         u8 __iomem *base = get_hwbase(dev);
4835         struct sk_buff *tx_skb, *rx_skb;
4836         dma_addr_t test_dma_addr;
4837         u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
4838         u32 flags;
4839         int len, i, pkt_len;
4840         u8 *pkt_data;
4841         u32 filter_flags = 0;
4842         u32 misc1_flags = 0;
4843         int ret = 1;
4844
4845         if (netif_running(dev)) {
4846                 nv_disable_irq(dev);
4847                 filter_flags = readl(base + NvRegPacketFilterFlags);
4848                 misc1_flags = readl(base + NvRegMisc1);
4849         } else {
4850                 nv_txrx_reset(dev);
4851         }
4852
4853         /* reinit driver view of the rx queue */
4854         set_bufsize(dev);
4855         nv_init_ring(dev);
4856
4857         /* setup hardware for loopback */
4858         writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
4859         writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
4860
4861         /* reinit nic view of the rx queue */
4862         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4863         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4864         writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4865                 base + NvRegRingSizes);
4866         pci_push(base);
4867
4868         /* restart rx engine */
4869         nv_start_rxtx(dev);
4870
4871         /* setup packet for tx */
4872         pkt_len = ETH_DATA_LEN;
4873         tx_skb = dev_alloc_skb(pkt_len);
4874         if (!tx_skb) {
4875                 netdev_err(dev, "dev_alloc_skb() failed during loopback test\n");
4876                 ret = 0;
4877                 goto out;
4878         }
4879         test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
4880                                        skb_tailroom(tx_skb),
4881                                        PCI_DMA_FROMDEVICE);
4882         pkt_data = skb_put(tx_skb, pkt_len);
4883         for (i = 0; i < pkt_len; i++)
4884                 pkt_data[i] = (u8)(i & 0xff);
4885
4886         if (!nv_optimized(np)) {
4887                 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
4888                 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4889         } else {
4890                 np->tx_ring.ex[0].bufhigh = cpu_to_le32(dma_high(test_dma_addr));
4891                 np->tx_ring.ex[0].buflow = cpu_to_le32(dma_low(test_dma_addr));
4892                 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4893         }
4894         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4895         pci_push(get_hwbase(dev));
4896
4897         msleep(500);
4898
4899         /* check for rx of the packet */
4900         if (!nv_optimized(np)) {
4901                 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
4902                 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
4903
4904         } else {
4905                 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
4906                 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
4907         }
4908
4909         if (flags & NV_RX_AVAIL) {
4910                 ret = 0;
4911         } else if (np->desc_ver == DESC_VER_1) {
4912                 if (flags & NV_RX_ERROR)
4913                         ret = 0;
4914         } else {
4915                 if (flags & NV_RX2_ERROR)
4916                         ret = 0;
4917         }
4918
4919         if (ret) {
4920                 if (len != pkt_len) {
4921                         ret = 0;
4922                 } else {
4923                         rx_skb = np->rx_skb[0].skb;
4924                         for (i = 0; i < pkt_len; i++) {
4925                                 if (rx_skb->data[i] != (u8)(i & 0xff)) {
4926                                         ret = 0;
4927                                         break;
4928                                 }
4929                         }
4930                 }
4931         }
4932
4933         pci_unmap_single(np->pci_dev, test_dma_addr,
4934                        (skb_end_pointer(tx_skb) - tx_skb->data),
4935                        PCI_DMA_TODEVICE);
4936         dev_kfree_skb_any(tx_skb);
4937  out:
4938         /* stop engines */
4939         nv_stop_rxtx(dev);
4940         nv_txrx_reset(dev);
4941         /* drain rx queue */
4942         nv_drain_rxtx(dev);
4943
4944         if (netif_running(dev)) {
4945                 writel(misc1_flags, base + NvRegMisc1);
4946                 writel(filter_flags, base + NvRegPacketFilterFlags);
4947                 nv_enable_irq(dev);
4948         }
4949
4950         return ret;
4951 }
4952
4953 static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
4954 {
4955         struct fe_priv *np = netdev_priv(dev);
4956         u8 __iomem *base = get_hwbase(dev);
4957         int result;
4958         memset(buffer, 0, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(u64));
4959
4960         if (!nv_link_test(dev)) {
4961                 test->flags |= ETH_TEST_FL_FAILED;
4962                 buffer[0] = 1;
4963         }
4964
4965         if (test->flags & ETH_TEST_FL_OFFLINE) {
4966                 if (netif_running(dev)) {
4967                         netif_stop_queue(dev);
4968                         nv_napi_disable(dev);
4969                         netif_tx_lock_bh(dev);
4970                         netif_addr_lock(dev);
4971                         spin_lock_irq(&np->lock);
4972                         nv_disable_hw_interrupts(dev, np->irqmask);
4973                         if (!(np->msi_flags & NV_MSI_X_ENABLED))
4974                                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4975                         else
4976                                 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4977                         /* stop engines */
4978                         nv_stop_rxtx(dev);
4979                         nv_txrx_reset(dev);
4980                         /* drain rx queue */
4981                         nv_drain_rxtx(dev);
4982                         spin_unlock_irq(&np->lock);
4983                         netif_addr_unlock(dev);
4984                         netif_tx_unlock_bh(dev);
4985                 }
4986
4987                 if (!nv_register_test(dev)) {
4988                         test->flags |= ETH_TEST_FL_FAILED;
4989                         buffer[1] = 1;
4990                 }
4991
4992                 result = nv_interrupt_test(dev);
4993                 if (result != 1) {
4994                         test->flags |= ETH_TEST_FL_FAILED;
4995                         buffer[2] = 1;
4996                 }
4997                 if (result == 0) {
4998                         /* bail out */
4999                         return;
5000                 }
5001
5002                 if (!nv_loopback_test(dev)) {
5003                         test->flags |= ETH_TEST_FL_FAILED;
5004                         buffer[3] = 1;
5005                 }
5006
5007                 if (netif_running(dev)) {
5008                         /* reinit driver view of the rx queue */
5009                         set_bufsize(dev);
5010                         if (nv_init_ring(dev)) {
5011                                 if (!np->in_shutdown)
5012                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5013                         }
5014                         /* reinit nic view of the rx queue */
5015                         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5016                         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5017                         writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5018                                 base + NvRegRingSizes);
5019                         pci_push(base);
5020                         writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5021                         pci_push(base);
5022                         /* restart rx engine */
5023                         nv_start_rxtx(dev);
5024                         netif_start_queue(dev);
5025                         nv_napi_enable(dev);
5026                         nv_enable_hw_interrupts(dev, np->irqmask);
5027                 }
5028         }
5029 }
5030
5031 static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
5032 {
5033         switch (stringset) {
5034         case ETH_SS_STATS:
5035                 memcpy(buffer, &nv_estats_str, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(struct nv_ethtool_str));
5036                 break;
5037         case ETH_SS_TEST:
5038                 memcpy(buffer, &nv_etests_str, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(struct nv_ethtool_str));
5039                 break;
5040         }
5041 }
5042
5043 static const struct ethtool_ops ops = {
5044         .get_drvinfo = nv_get_drvinfo,
5045         .get_link = ethtool_op_get_link,
5046         .get_wol = nv_get_wol,
5047         .set_wol = nv_set_wol,
5048         .get_settings = nv_get_settings,
5049         .set_settings = nv_set_settings,
5050         .get_regs_len = nv_get_regs_len,
5051         .get_regs = nv_get_regs,
5052         .nway_reset = nv_nway_reset,
5053         .get_ringparam = nv_get_ringparam,
5054         .set_ringparam = nv_set_ringparam,
5055         .get_pauseparam = nv_get_pauseparam,
5056         .set_pauseparam = nv_set_pauseparam,
5057         .get_strings = nv_get_strings,
5058         .get_ethtool_stats = nv_get_ethtool_stats,
5059         .get_sset_count = nv_get_sset_count,
5060         .self_test = nv_self_test,
5061 };
5062
5063 /* The mgmt unit and driver use a semaphore to access the phy during init */
5064 static int nv_mgmt_acquire_sema(struct net_device *dev)
5065 {
5066         struct fe_priv *np = netdev_priv(dev);
5067         u8 __iomem *base = get_hwbase(dev);
5068         int i;
5069         u32 tx_ctrl, mgmt_sema;
5070
5071         for (i = 0; i < 10; i++) {
5072                 mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
5073                 if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE)
5074                         break;
5075                 msleep(500);
5076         }
5077
5078         if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE)
5079                 return 0;
5080
5081         for (i = 0; i < 2; i++) {
5082                 tx_ctrl = readl(base + NvRegTransmitterControl);
5083                 tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
5084                 writel(tx_ctrl, base + NvRegTransmitterControl);
5085
5086                 /* verify that semaphore was acquired */
5087                 tx_ctrl = readl(base + NvRegTransmitterControl);
5088                 if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) &&
5089                     ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE)) {
5090                         np->mgmt_sema = 1;
5091                         return 1;
5092                 } else
5093                         udelay(50);
5094         }
5095
5096         return 0;
5097 }
5098
5099 static void nv_mgmt_release_sema(struct net_device *dev)
5100 {
5101         struct fe_priv *np = netdev_priv(dev);
5102         u8 __iomem *base = get_hwbase(dev);
5103         u32 tx_ctrl;
5104
5105         if (np->driver_data & DEV_HAS_MGMT_UNIT) {
5106                 if (np->mgmt_sema) {
5107                         tx_ctrl = readl(base + NvRegTransmitterControl);
5108                         tx_ctrl &= ~NVREG_XMITCTL_HOST_SEMA_ACQ;
5109                         writel(tx_ctrl, base + NvRegTransmitterControl);
5110                 }
5111         }
5112 }
5113
5114
5115 static int nv_mgmt_get_version(struct net_device *dev)
5116 {
5117         struct fe_priv *np = netdev_priv(dev);
5118         u8 __iomem *base = get_hwbase(dev);
5119         u32 data_ready = readl(base + NvRegTransmitterControl);
5120         u32 data_ready2 = 0;
5121         unsigned long start;
5122         int ready = 0;
5123
5124         writel(NVREG_MGMTUNITGETVERSION, base + NvRegMgmtUnitGetVersion);
5125         writel(data_ready ^ NVREG_XMITCTL_DATA_START, base + NvRegTransmitterControl);
5126         start = jiffies;
5127         while (time_before(jiffies, start + 5*HZ)) {
5128                 data_ready2 = readl(base + NvRegTransmitterControl);
5129                 if ((data_ready & NVREG_XMITCTL_DATA_READY) != (data_ready2 & NVREG_XMITCTL_DATA_READY)) {
5130                         ready = 1;
5131                         break;
5132                 }
5133                 schedule_timeout_uninterruptible(1);
5134         }
5135
5136         if (!ready || (data_ready2 & NVREG_XMITCTL_DATA_ERROR))
5137                 return 0;
5138
5139         np->mgmt_version = readl(base + NvRegMgmtUnitVersion) & NVREG_MGMTUNITVERSION;
5140
5141         return 1;
5142 }
5143
5144 static int nv_open(struct net_device *dev)
5145 {
5146         struct fe_priv *np = netdev_priv(dev);
5147         u8 __iomem *base = get_hwbase(dev);
5148         int ret = 1;
5149         int oom, i;
5150         u32 low;
5151
5152         /* power up phy */
5153         mii_rw(dev, np->phyaddr, MII_BMCR,
5154                mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN);
5155
5156         nv_txrx_gate(dev, false);
5157         /* erase previous misconfiguration */
5158         if (np->driver_data & DEV_HAS_POWER_CNTRL)
5159                 nv_mac_reset(dev);
5160         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5161         writel(0, base + NvRegMulticastAddrB);
5162         writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5163         writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5164         writel(0, base + NvRegPacketFilterFlags);
5165
5166         writel(0, base + NvRegTransmitterControl);
5167         writel(0, base + NvRegReceiverControl);
5168
5169         writel(0, base + NvRegAdapterControl);
5170
5171         if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
5172                 writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);
5173
5174         /* initialize descriptor rings */
5175         set_bufsize(dev);
5176         oom = nv_init_ring(dev);
5177
5178         writel(0, base + NvRegLinkSpeed);
5179         writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5180         nv_txrx_reset(dev);
5181         writel(0, base + NvRegUnknownSetupReg6);
5182
5183         np->in_shutdown = 0;
5184
5185         /* give hw rings */
5186         setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5187         writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5188                 base + NvRegRingSizes);
5189
5190         writel(np->linkspeed, base + NvRegLinkSpeed);
5191         if (np->desc_ver == DESC_VER_1)
5192                 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
5193         else
5194                 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
5195         writel(np->txrxctl_bits, base + NvRegTxRxControl);
5196         writel(np->vlanctl_bits, base + NvRegVlanControl);
5197         pci_push(base);
5198         writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
5199         if (reg_delay(dev, NvRegUnknownSetupReg5,
5200                       NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
5201                       NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX))
5202                 netdev_info(dev,
5203                             "%s: SetupReg5, Bit 31 remained off\n", __func__);
5204
5205         writel(0, base + NvRegMIIMask);
5206         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5207         writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5208
5209         writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
5210         writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
5211         writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
5212         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5213
5214         writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
5215
5216         get_random_bytes(&low, sizeof(low));
5217         low &= NVREG_SLOTTIME_MASK;
5218         if (np->desc_ver == DESC_VER_1) {
5219                 writel(low|NVREG_SLOTTIME_DEFAULT, base + NvRegSlotTime);
5220         } else {
5221                 if (!(np->driver_data & DEV_HAS_GEAR_MODE)) {
5222                         /* setup legacy backoff */
5223                         writel(NVREG_SLOTTIME_LEGBF_ENABLED|NVREG_SLOTTIME_10_100_FULL|low, base + NvRegSlotTime);
5224                 } else {
5225                         writel(NVREG_SLOTTIME_10_100_FULL, base + NvRegSlotTime);
5226                         nv_gear_backoff_reseed(dev);
5227                 }
5228         }
5229         writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
5230         writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
5231         if (poll_interval == -1) {
5232                 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
5233                         writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
5234                 else
5235                         writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
5236         } else
5237                 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
5238         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
5239         writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
5240                         base + NvRegAdapterControl);
5241         writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
5242         writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
5243         if (np->wolenabled)
5244                 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
5245
5246         i = readl(base + NvRegPowerState);
5247         if ((i & NVREG_POWERSTATE_POWEREDUP) == 0)
5248                 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
5249
5250         pci_push(base);
5251         udelay(10);
5252         writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
5253
5254         nv_disable_hw_interrupts(dev, np->irqmask);
5255         pci_push(base);
5256         writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5257         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5258         pci_push(base);
5259
5260         if (nv_request_irq(dev, 0))
5261                 goto out_drain;
5262
5263         /* ask for interrupts */
5264         nv_enable_hw_interrupts(dev, np->irqmask);
5265
5266         spin_lock_irq(&np->lock);
5267         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5268         writel(0, base + NvRegMulticastAddrB);
5269         writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5270         writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5271         writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5272         /* One manual link speed update: Interrupts are enabled, future link
5273          * speed changes cause interrupts and are handled by nv_link_irq().
5274          */
5275         {
5276                 u32 miistat;
5277                 miistat = readl(base + NvRegMIIStatus);
5278                 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5279         }
5280         /* set linkspeed to invalid value, thus force nv_update_linkspeed
5281          * to init hw */
5282         np->linkspeed = 0;
5283         ret = nv_update_linkspeed(dev);
5284         nv_start_rxtx(dev);
5285         netif_start_queue(dev);
5286         nv_napi_enable(dev);
5287
5288         if (ret) {
5289                 netif_carrier_on(dev);
5290         } else {
5291                 netdev_info(dev, "no link during initialization\n");
5292                 netif_carrier_off(dev);
5293         }
5294         if (oom)
5295                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5296
5297         /* start statistics timer */
5298         if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
5299                 mod_timer(&np->stats_poll,
5300                         round_jiffies(jiffies + STATS_INTERVAL));
5301
5302         spin_unlock_irq(&np->lock);
5303
5304         /* If the loopback feature was set while the device was down, make sure
5305          * that it's set correctly now.
5306          */
5307         if (dev->features & NETIF_F_LOOPBACK)
5308                 nv_set_loopback(dev, dev->features);
5309
5310         return 0;
5311 out_drain:
5312         nv_drain_rxtx(dev);
5313         return ret;
5314 }
5315
5316 static int nv_close(struct net_device *dev)
5317 {
5318         struct fe_priv *np = netdev_priv(dev);
5319         u8 __iomem *base;
5320
5321         spin_lock_irq(&np->lock);
5322         np->in_shutdown = 1;
5323         spin_unlock_irq(&np->lock);
5324         nv_napi_disable(dev);
5325         synchronize_irq(np->pci_dev->irq);
5326
5327         del_timer_sync(&np->oom_kick);
5328         del_timer_sync(&np->nic_poll);
5329         del_timer_sync(&np->stats_poll);
5330
5331         netif_stop_queue(dev);
5332         spin_lock_irq(&np->lock);
5333         nv_stop_rxtx(dev);
5334         nv_txrx_reset(dev);
5335
5336         /* disable interrupts on the nic or we will lock up */
5337         base = get_hwbase(dev);
5338         nv_disable_hw_interrupts(dev, np->irqmask);
5339         pci_push(base);
5340
5341         spin_unlock_irq(&np->lock);
5342
5343         nv_free_irq(dev);
5344
5345         nv_drain_rxtx(dev);
5346
5347         if (np->wolenabled || !phy_power_down) {
5348                 nv_txrx_gate(dev, false);
5349                 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5350                 nv_start_rx(dev);
5351         } else {
5352                 /* power down phy */
5353                 mii_rw(dev, np->phyaddr, MII_BMCR,
5354                        mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ)|BMCR_PDOWN);
5355                 nv_txrx_gate(dev, true);
5356         }
5357
5358         /* FIXME: power down nic */
5359
5360         return 0;
5361 }
5362
5363 static const struct net_device_ops nv_netdev_ops = {
5364         .ndo_open               = nv_open,
5365         .ndo_stop               = nv_close,
5366         .ndo_get_stats          = nv_get_stats,
5367         .ndo_start_xmit         = nv_start_xmit,
5368         .ndo_tx_timeout         = nv_tx_timeout,
5369         .ndo_change_mtu         = nv_change_mtu,
5370         .ndo_fix_features       = nv_fix_features,
5371         .ndo_set_features       = nv_set_features,
5372         .ndo_validate_addr      = eth_validate_addr,
5373         .ndo_set_mac_address    = nv_set_mac_address,
5374         .ndo_set_rx_mode        = nv_set_multicast,
5375 #ifdef CONFIG_NET_POLL_CONTROLLER
5376         .ndo_poll_controller    = nv_poll_controller,
5377 #endif
5378 };
5379
5380 static const struct net_device_ops nv_netdev_ops_optimized = {
5381         .ndo_open               = nv_open,
5382         .ndo_stop               = nv_close,
5383         .ndo_get_stats          = nv_get_stats,
5384         .ndo_start_xmit         = nv_start_xmit_optimized,
5385         .ndo_tx_timeout         = nv_tx_timeout,
5386         .ndo_change_mtu         = nv_change_mtu,
5387         .ndo_fix_features       = nv_fix_features,
5388         .ndo_set_features       = nv_set_features,
5389         .ndo_validate_addr      = eth_validate_addr,
5390         .ndo_set_mac_address    = nv_set_mac_address,
5391         .ndo_set_rx_mode        = nv_set_multicast,
5392 #ifdef CONFIG_NET_POLL_CONTROLLER
5393         .ndo_poll_controller    = nv_poll_controller,
5394 #endif
5395 };
5396
5397 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
5398 {
5399         struct net_device *dev;
5400         struct fe_priv *np;
5401         unsigned long addr;
5402         u8 __iomem *base;
5403         int err, i;
5404         u32 powerstate, txreg;
5405         u32 phystate_orig = 0, phystate;
5406         int phyinitialized = 0;
5407         static int printed_version;
5408
5409         if (!printed_version++)
5410                 pr_info("Reverse Engineered nForce ethernet driver. Version %s.\n",
5411                         FORCEDETH_VERSION);
5412
5413         dev = alloc_etherdev(sizeof(struct fe_priv));
5414         err = -ENOMEM;
5415         if (!dev)
5416                 goto out;
5417
5418         np = netdev_priv(dev);
5419         np->dev = dev;
5420         np->pci_dev = pci_dev;
5421         spin_lock_init(&np->lock);
5422         SET_NETDEV_DEV(dev, &pci_dev->dev);
5423
5424         init_timer(&np->oom_kick);
5425         np->oom_kick.data = (unsigned long) dev;
5426         np->oom_kick.function = nv_do_rx_refill;        /* timer handler */
5427         init_timer(&np->nic_poll);
5428         np->nic_poll.data = (unsigned long) dev;
5429         np->nic_poll.function = nv_do_nic_poll; /* timer handler */
5430         init_timer(&np->stats_poll);
5431         np->stats_poll.data = (unsigned long) dev;
5432         np->stats_poll.function = nv_do_stats_poll;     /* timer handler */
5433
5434         err = pci_enable_device(pci_dev);
5435         if (err)
5436                 goto out_free;
5437
5438         pci_set_master(pci_dev);
5439
5440         err = pci_request_regions(pci_dev, DRV_NAME);
5441         if (err < 0)
5442                 goto out_disable;
5443
5444         if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
5445                 np->register_size = NV_PCI_REGSZ_VER3;
5446         else if (id->driver_data & DEV_HAS_STATISTICS_V1)
5447                 np->register_size = NV_PCI_REGSZ_VER2;
5448         else
5449                 np->register_size = NV_PCI_REGSZ_VER1;
5450
5451         err = -EINVAL;
5452         addr = 0;
5453         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
5454                 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
5455                                 pci_resource_len(pci_dev, i) >= np->register_size) {
5456                         addr = pci_resource_start(pci_dev, i);
5457                         break;
5458                 }
5459         }
5460         if (i == DEVICE_COUNT_RESOURCE) {
5461                 dev_info(&pci_dev->dev, "Couldn't find register window\n");
5462                 goto out_relreg;
5463         }
5464
5465         /* copy of driver data */
5466         np->driver_data = id->driver_data;
5467         /* copy of device id */
5468         np->device_id = id->device;
5469
5470         /* handle different descriptor versions */
5471         if (id->driver_data & DEV_HAS_HIGH_DMA) {
5472                 /* packet format 3: supports 40-bit addressing */
5473                 np->desc_ver = DESC_VER_3;
5474                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
5475                 if (dma_64bit) {
5476                         if (pci_set_dma_mask(pci_dev, DMA_BIT_MASK(39)))
5477                                 dev_info(&pci_dev->dev,
5478                                          "64-bit DMA failed, using 32-bit addressing\n");
5479                         else
5480                                 dev->features |= NETIF_F_HIGHDMA;
5481                         if (pci_set_consistent_dma_mask(pci_dev, DMA_BIT_MASK(39))) {
5482                                 dev_info(&pci_dev->dev,
5483                                          "64-bit DMA (consistent) failed, using 32-bit ring buffers\n");
5484                         }
5485                 }
5486         } else if (id->driver_data & DEV_HAS_LARGEDESC) {
5487                 /* packet format 2: supports jumbo frames */
5488                 np->desc_ver = DESC_VER_2;
5489                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
5490         } else {
5491                 /* original packet format */
5492                 np->desc_ver = DESC_VER_1;
5493                 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
5494         }
5495
5496         np->pkt_limit = NV_PKTLIMIT_1;
5497         if (id->driver_data & DEV_HAS_LARGEDESC)
5498                 np->pkt_limit = NV_PKTLIMIT_2;
5499
5500         if (id->driver_data & DEV_HAS_CHECKSUM) {
5501                 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
5502                 dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_SG |
5503                         NETIF_F_TSO | NETIF_F_RXCSUM;
5504         }
5505
5506         np->vlanctl_bits = 0;
5507         if (id->driver_data & DEV_HAS_VLAN) {
5508                 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
5509                 dev->hw_features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
5510         }
5511
5512         dev->features |= dev->hw_features;
5513
5514         /* Add loopback capability to the device. */
5515         dev->hw_features |= NETIF_F_LOOPBACK;
5516
5517         np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
5518         if ((id->driver_data & DEV_HAS_PAUSEFRAME_TX_V1) ||
5519             (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V2) ||
5520             (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V3)) {
5521                 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
5522         }
5523
5524         err = -ENOMEM;
5525         np->base = ioremap(addr, np->register_size);
5526         if (!np->base)
5527                 goto out_relreg;
5528         dev->base_addr = (unsigned long)np->base;
5529
5530         dev->irq = pci_dev->irq;
5531
5532         np->rx_ring_size = RX_RING_DEFAULT;
5533         np->tx_ring_size = TX_RING_DEFAULT;
5534
5535         if (!nv_optimized(np)) {
5536                 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
5537                                         sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
5538                                         &np->ring_addr);
5539                 if (!np->rx_ring.orig)
5540                         goto out_unmap;
5541                 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
5542         } else {
5543                 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
5544                                         sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
5545                                         &np->ring_addr);
5546                 if (!np->rx_ring.ex)
5547                         goto out_unmap;
5548                 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
5549         }
5550         np->rx_skb = kcalloc(np->rx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5551         np->tx_skb = kcalloc(np->tx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5552         if (!np->rx_skb || !np->tx_skb)
5553                 goto out_freering;
5554
5555         if (!nv_optimized(np))
5556                 dev->netdev_ops = &nv_netdev_ops;
5557         else
5558                 dev->netdev_ops = &nv_netdev_ops_optimized;
5559
5560         netif_napi_add(dev, &np->napi, nv_napi_poll, RX_WORK_PER_LOOP);
5561         SET_ETHTOOL_OPS(dev, &ops);
5562         dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
5563
5564         pci_set_drvdata(pci_dev, dev);
5565
5566         /* read the mac address */
5567         base = get_hwbase(dev);
5568         np->orig_mac[0] = readl(base + NvRegMacAddrA);
5569         np->orig_mac[1] = readl(base + NvRegMacAddrB);
5570
5571         /* check the workaround bit for correct mac address order */
5572         txreg = readl(base + NvRegTransmitPoll);
5573         if (id->driver_data & DEV_HAS_CORRECT_MACADDR) {
5574                 /* mac address is already in correct order */
5575                 dev->dev_addr[0] = (np->orig_mac[0] >>  0) & 0xff;
5576                 dev->dev_addr[1] = (np->orig_mac[0] >>  8) & 0xff;
5577                 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5578                 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5579                 dev->dev_addr[4] = (np->orig_mac[1] >>  0) & 0xff;
5580                 dev->dev_addr[5] = (np->orig_mac[1] >>  8) & 0xff;
5581         } else if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {
5582                 /* mac address is already in correct order */
5583                 dev->dev_addr[0] = (np->orig_mac[0] >>  0) & 0xff;
5584                 dev->dev_addr[1] = (np->orig_mac[0] >>  8) & 0xff;
5585                 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5586                 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5587                 dev->dev_addr[4] = (np->orig_mac[1] >>  0) & 0xff;
5588                 dev->dev_addr[5] = (np->orig_mac[1] >>  8) & 0xff;
5589                 /*
5590                  * Set orig mac address back to the reversed version.
5591                  * This flag will be cleared during low power transition.
5592                  * Therefore, we should always put back the reversed address.
5593                  */
5594                 np->orig_mac[0] = (dev->dev_addr[5] << 0) + (dev->dev_addr[4] << 8) +
5595                         (dev->dev_addr[3] << 16) + (dev->dev_addr[2] << 24);
5596                 np->orig_mac[1] = (dev->dev_addr[1] << 0) + (dev->dev_addr[0] << 8);
5597         } else {
5598                 /* need to reverse mac address to correct order */
5599                 dev->dev_addr[0] = (np->orig_mac[1] >>  8) & 0xff;
5600                 dev->dev_addr[1] = (np->orig_mac[1] >>  0) & 0xff;
5601                 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
5602                 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
5603                 dev->dev_addr[4] = (np->orig_mac[0] >>  8) & 0xff;
5604                 dev->dev_addr[5] = (np->orig_mac[0] >>  0) & 0xff;
5605                 writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5606                 dev_dbg(&pci_dev->dev,
5607                         "%s: set workaround bit for reversed mac addr\n",
5608                         __func__);
5609         }
5610         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
5611
5612         if (!is_valid_ether_addr(dev->perm_addr)) {
5613                 /*
5614                  * Bad mac address. At least one bios sets the mac address
5615                  * to 01:23:45:67:89:ab
5616                  */
5617                 dev_err(&pci_dev->dev,
5618                         "Invalid MAC address detected: %pM - Please complain to your hardware vendor.\n",
5619                         dev->dev_addr);
5620                 random_ether_addr(dev->dev_addr);
5621                 dev_err(&pci_dev->dev,
5622                         "Using random MAC address: %pM\n", dev->dev_addr);
5623         }
5624
5625         /* set mac address */
5626         nv_copy_mac_to_hw(dev);
5627
5628         /* disable WOL */
5629         writel(0, base + NvRegWakeUpFlags);
5630         np->wolenabled = 0;
5631         device_set_wakeup_enable(&pci_dev->dev, false);
5632
5633         if (id->driver_data & DEV_HAS_POWER_CNTRL) {
5634
5635                 /* take phy and nic out of low power mode */
5636                 powerstate = readl(base + NvRegPowerState2);
5637                 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
5638                 if ((id->driver_data & DEV_NEED_LOW_POWER_FIX) &&
5639                     pci_dev->revision >= 0xA3)
5640                         powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
5641                 writel(powerstate, base + NvRegPowerState2);
5642         }
5643
5644         if (np->desc_ver == DESC_VER_1)
5645                 np->tx_flags = NV_TX_VALID;
5646         else
5647                 np->tx_flags = NV_TX2_VALID;
5648
5649         np->msi_flags = 0;
5650         if ((id->driver_data & DEV_HAS_MSI) && msi)
5651                 np->msi_flags |= NV_MSI_CAPABLE;
5652
5653         if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
5654                 /* msix has had reported issues when modifying irqmask
5655                    as in the case of napi, therefore, disable for now
5656                 */
5657 #if 0
5658                 np->msi_flags |= NV_MSI_X_CAPABLE;
5659 #endif
5660         }
5661
5662         if (optimization_mode == NV_OPTIMIZATION_MODE_CPU) {
5663                 np->irqmask = NVREG_IRQMASK_CPU;
5664                 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5665                         np->msi_flags |= 0x0001;
5666         } else if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC &&
5667                    !(id->driver_data & DEV_NEED_TIMERIRQ)) {
5668                 /* start off in throughput mode */
5669                 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5670                 /* remove support for msix mode */
5671                 np->msi_flags &= ~NV_MSI_X_CAPABLE;
5672         } else {
5673                 optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
5674                 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5675                 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5676                         np->msi_flags |= 0x0003;
5677         }
5678
5679         if (id->driver_data & DEV_NEED_TIMERIRQ)
5680                 np->irqmask |= NVREG_IRQ_TIMER;
5681         if (id->driver_data & DEV_NEED_LINKTIMER) {
5682                 np->need_linktimer = 1;
5683                 np->link_timeout = jiffies + LINK_TIMEOUT;
5684         } else {
5685                 np->need_linktimer = 0;
5686         }
5687
5688         /* Limit the number of tx's outstanding for hw bug */
5689         if (id->driver_data & DEV_NEED_TX_LIMIT) {
5690                 np->tx_limit = 1;
5691                 if (((id->driver_data & DEV_NEED_TX_LIMIT2) == DEV_NEED_TX_LIMIT2) &&
5692                     pci_dev->revision >= 0xA2)
5693                         np->tx_limit = 0;
5694         }
5695
5696         /* clear phy state and temporarily halt phy interrupts */
5697         writel(0, base + NvRegMIIMask);
5698         phystate = readl(base + NvRegAdapterControl);
5699         if (phystate & NVREG_ADAPTCTL_RUNNING) {
5700                 phystate_orig = 1;
5701                 phystate &= ~NVREG_ADAPTCTL_RUNNING;
5702                 writel(phystate, base + NvRegAdapterControl);
5703         }
5704         writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5705
5706         if (id->driver_data & DEV_HAS_MGMT_UNIT) {
5707                 /* management unit running on the mac? */
5708                 if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST) &&
5709                     (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) &&
5710                     nv_mgmt_acquire_sema(dev) &&
5711                     nv_mgmt_get_version(dev)) {
5712                         np->mac_in_use = 1;
5713                         if (np->mgmt_version > 0)
5714                                 np->mac_in_use = readl(base + NvRegMgmtUnitControl) & NVREG_MGMTUNITCONTROL_INUSE;
5715                         /* management unit setup the phy already? */
5716                         if (np->mac_in_use &&
5717                             ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) ==
5718                              NVREG_XMITCTL_SYNC_PHY_INIT)) {
5719                                 /* phy is inited by mgmt unit */
5720                                 phyinitialized = 1;
5721                         } else {
5722                                 /* we need to init the phy */
5723                         }
5724                 }
5725         }
5726
5727         /* find a suitable phy */
5728         for (i = 1; i <= 32; i++) {
5729                 int id1, id2;
5730                 int phyaddr = i & 0x1F;
5731
5732                 spin_lock_irq(&np->lock);
5733                 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
5734                 spin_unlock_irq(&np->lock);
5735                 if (id1 < 0 || id1 == 0xffff)
5736                         continue;
5737                 spin_lock_irq(&np->lock);
5738                 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
5739                 spin_unlock_irq(&np->lock);
5740                 if (id2 < 0 || id2 == 0xffff)
5741                         continue;
5742
5743                 np->phy_model = id2 & PHYID2_MODEL_MASK;
5744                 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
5745                 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
5746                 np->phyaddr = phyaddr;
5747                 np->phy_oui = id1 | id2;
5748
5749                 /* Realtek hardcoded phy id1 to all zero's on certain phys */
5750                 if (np->phy_oui == PHY_OUI_REALTEK2)
5751                         np->phy_oui = PHY_OUI_REALTEK;
5752                 /* Setup phy revision for Realtek */
5753                 if (np->phy_oui == PHY_OUI_REALTEK && np->phy_model == PHY_MODEL_REALTEK_8211)
5754                         np->phy_rev = mii_rw(dev, phyaddr, MII_RESV1, MII_READ) & PHY_REV_MASK;
5755
5756                 break;
5757         }
5758         if (i == 33) {
5759                 dev_info(&pci_dev->dev, "open: Could not find a valid PHY\n");
5760                 goto out_error;
5761         }
5762
5763         if (!phyinitialized) {
5764                 /* reset it */
5765                 phy_init(dev);
5766         } else {
5767                 /* see if it is a gigabit phy */
5768                 u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
5769                 if (mii_status & PHY_GIGABIT)
5770                         np->gigabit = PHY_GIGABIT;
5771         }
5772
5773         /* set default link speed settings */
5774         np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
5775         np->duplex = 0;
5776         np->autoneg = 1;
5777
5778         err = register_netdev(dev);
5779         if (err) {
5780                 dev_info(&pci_dev->dev, "unable to register netdev: %d\n", err);
5781                 goto out_error;
5782         }
5783
5784         if (id->driver_data & DEV_HAS_VLAN)
5785                 nv_vlan_mode(dev, dev->features);
5786
5787         netif_carrier_off(dev);
5788
5789         dev_info(&pci_dev->dev, "ifname %s, PHY OUI 0x%x @ %d, addr %pM\n",
5790                  dev->name, np->phy_oui, np->phyaddr, dev->dev_addr);
5791
5792         dev_info(&pci_dev->dev, "%s%s%s%s%s%s%s%s%s%s%sdesc-v%u\n",
5793                  dev->features & NETIF_F_HIGHDMA ? "highdma " : "",
5794                  dev->features & (NETIF_F_IP_CSUM | NETIF_F_SG) ?
5795                         "csum " : "",
5796                  dev->features & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX) ?
5797                         "vlan " : "",
5798                  dev->features & (NETIF_F_LOOPBACK) ?
5799                         "loopback " : "",
5800                  id->driver_data & DEV_HAS_POWER_CNTRL ? "pwrctl " : "",
5801                  id->driver_data & DEV_HAS_MGMT_UNIT ? "mgmt " : "",
5802                  id->driver_data & DEV_NEED_TIMERIRQ ? "timirq " : "",
5803                  np->gigabit == PHY_GIGABIT ? "gbit " : "",
5804                  np->need_linktimer ? "lnktim " : "",
5805                  np->msi_flags & NV_MSI_CAPABLE ? "msi " : "",
5806                  np->msi_flags & NV_MSI_X_CAPABLE ? "msi-x " : "",
5807                  np->desc_ver);
5808
5809         return 0;
5810
5811 out_error:
5812         if (phystate_orig)
5813                 writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
5814         pci_set_drvdata(pci_dev, NULL);
5815 out_freering:
5816         free_rings(dev);
5817 out_unmap:
5818         iounmap(get_hwbase(dev));
5819 out_relreg:
5820         pci_release_regions(pci_dev);
5821 out_disable:
5822         pci_disable_device(pci_dev);
5823 out_free:
5824         free_netdev(dev);
5825 out:
5826         return err;
5827 }
5828
5829 static void nv_restore_phy(struct net_device *dev)
5830 {
5831         struct fe_priv *np = netdev_priv(dev);
5832         u16 phy_reserved, mii_control;
5833
5834         if (np->phy_oui == PHY_OUI_REALTEK &&
5835             np->phy_model == PHY_MODEL_REALTEK_8201 &&
5836             phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
5837                 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3);
5838                 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
5839                 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
5840                 phy_reserved |= PHY_REALTEK_INIT8;
5841                 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved);
5842                 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1);
5843
5844                 /* restart auto negotiation */
5845                 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
5846                 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
5847                 mii_rw(dev, np->phyaddr, MII_BMCR, mii_control);
5848         }
5849 }
5850
5851 static void nv_restore_mac_addr(struct pci_dev *pci_dev)
5852 {
5853         struct net_device *dev = pci_get_drvdata(pci_dev);
5854         struct fe_priv *np = netdev_priv(dev);
5855         u8 __iomem *base = get_hwbase(dev);
5856
5857         /* special op: write back the misordered MAC address - otherwise
5858          * the next nv_probe would see a wrong address.
5859          */
5860         writel(np->orig_mac[0], base + NvRegMacAddrA);
5861         writel(np->orig_mac[1], base + NvRegMacAddrB);
5862         writel(readl(base + NvRegTransmitPoll) & ~NVREG_TRANSMITPOLL_MAC_ADDR_REV,
5863                base + NvRegTransmitPoll);
5864 }
5865
5866 static void __devexit nv_remove(struct pci_dev *pci_dev)
5867 {
5868         struct net_device *dev = pci_get_drvdata(pci_dev);
5869
5870         unregister_netdev(dev);
5871
5872         nv_restore_mac_addr(pci_dev);
5873
5874         /* restore any phy related changes */
5875         nv_restore_phy(dev);
5876
5877         nv_mgmt_release_sema(dev);
5878
5879         /* free all structures */
5880         free_rings(dev);
5881         iounmap(get_hwbase(dev));
5882         pci_release_regions(pci_dev);
5883         pci_disable_device(pci_dev);
5884         free_netdev(dev);
5885         pci_set_drvdata(pci_dev, NULL);
5886 }
5887
5888 #ifdef CONFIG_PM_SLEEP
5889 static int nv_suspend(struct device *device)
5890 {
5891         struct pci_dev *pdev = to_pci_dev(device);
5892         struct net_device *dev = pci_get_drvdata(pdev);
5893         struct fe_priv *np = netdev_priv(dev);
5894         u8 __iomem *base = get_hwbase(dev);
5895         int i;
5896
5897         if (netif_running(dev)) {
5898                 /* Gross. */
5899                 nv_close(dev);
5900         }
5901         netif_device_detach(dev);
5902
5903         /* save non-pci configuration space */
5904         for (i = 0; i <= np->register_size/sizeof(u32); i++)
5905                 np->saved_config_space[i] = readl(base + i*sizeof(u32));
5906
5907         return 0;
5908 }
5909
5910 static int nv_resume(struct device *device)
5911 {
5912         struct pci_dev *pdev = to_pci_dev(device);
5913         struct net_device *dev = pci_get_drvdata(pdev);
5914         struct fe_priv *np = netdev_priv(dev);
5915         u8 __iomem *base = get_hwbase(dev);
5916         int i, rc = 0;
5917
5918         /* restore non-pci configuration space */
5919         for (i = 0; i <= np->register_size/sizeof(u32); i++)
5920                 writel(np->saved_config_space[i], base+i*sizeof(u32));
5921
5922         if (np->driver_data & DEV_NEED_MSI_FIX)
5923                 pci_write_config_dword(pdev, NV_MSI_PRIV_OFFSET, NV_MSI_PRIV_VALUE);
5924
5925         /* restore phy state, including autoneg */
5926         phy_init(dev);
5927
5928         netif_device_attach(dev);
5929         if (netif_running(dev)) {
5930                 rc = nv_open(dev);
5931                 nv_set_multicast(dev);
5932         }
5933         return rc;
5934 }
5935
5936 static SIMPLE_DEV_PM_OPS(nv_pm_ops, nv_suspend, nv_resume);
5937 #define NV_PM_OPS (&nv_pm_ops)
5938
5939 #else
5940 #define NV_PM_OPS NULL
5941 #endif /* CONFIG_PM_SLEEP */
5942
5943 #ifdef CONFIG_PM
5944 static void nv_shutdown(struct pci_dev *pdev)
5945 {
5946         struct net_device *dev = pci_get_drvdata(pdev);
5947         struct fe_priv *np = netdev_priv(dev);
5948
5949         if (netif_running(dev))
5950                 nv_close(dev);
5951
5952         /*
5953          * Restore the MAC so a kernel started by kexec won't get confused.
5954          * If we really go for poweroff, we must not restore the MAC,
5955          * otherwise the MAC for WOL will be reversed at least on some boards.
5956          */
5957         if (system_state != SYSTEM_POWER_OFF)
5958                 nv_restore_mac_addr(pdev);
5959
5960         pci_disable_device(pdev);
5961         /*
5962          * Apparently it is not possible to reinitialise from D3 hot,
5963          * only put the device into D3 if we really go for poweroff.
5964          */
5965         if (system_state == SYSTEM_POWER_OFF) {
5966                 pci_wake_from_d3(pdev, np->wolenabled);
5967                 pci_set_power_state(pdev, PCI_D3hot);
5968         }
5969 }
5970 #else
5971 #define nv_shutdown NULL
5972 #endif /* CONFIG_PM */
5973
5974 static DEFINE_PCI_DEVICE_TABLE(pci_tbl) = {
5975         {       /* nForce Ethernet Controller */
5976                 PCI_DEVICE(0x10DE, 0x01C3),
5977                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
5978         },
5979         {       /* nForce2 Ethernet Controller */
5980                 PCI_DEVICE(0x10DE, 0x0066),
5981                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
5982         },
5983         {       /* nForce3 Ethernet Controller */
5984                 PCI_DEVICE(0x10DE, 0x00D6),
5985                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
5986         },
5987         {       /* nForce3 Ethernet Controller */
5988                 PCI_DEVICE(0x10DE, 0x0086),
5989                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5990         },
5991         {       /* nForce3 Ethernet Controller */
5992                 PCI_DEVICE(0x10DE, 0x008C),
5993                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5994         },
5995         {       /* nForce3 Ethernet Controller */
5996                 PCI_DEVICE(0x10DE, 0x00E6),
5997                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5998         },
5999         {       /* nForce3 Ethernet Controller */
6000                 PCI_DEVICE(0x10DE, 0x00DF),
6001                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6002         },
6003         {       /* CK804 Ethernet Controller */
6004                 PCI_DEVICE(0x10DE, 0x0056),
6005                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6006         },
6007         {       /* CK804 Ethernet Controller */
6008                 PCI_DEVICE(0x10DE, 0x0057),
6009                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6010         },
6011         {       /* MCP04 Ethernet Controller */
6012                 PCI_DEVICE(0x10DE, 0x0037),
6013                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6014         },
6015         {       /* MCP04 Ethernet Controller */
6016                 PCI_DEVICE(0x10DE, 0x0038),
6017                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6018         },
6019         {       /* MCP51 Ethernet Controller */
6020                 PCI_DEVICE(0x10DE, 0x0268),
6021                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
6022         },
6023         {       /* MCP51 Ethernet Controller */
6024                 PCI_DEVICE(0x10DE, 0x0269),
6025                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
6026         },
6027         {       /* MCP55 Ethernet Controller */
6028                 PCI_DEVICE(0x10DE, 0x0372),
6029                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
6030         },
6031         {       /* MCP55 Ethernet Controller */
6032                 PCI_DEVICE(0x10DE, 0x0373),
6033                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
6034         },
6035         {       /* MCP61 Ethernet Controller */
6036                 PCI_DEVICE(0x10DE, 0x03E5),
6037                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6038         },
6039         {       /* MCP61 Ethernet Controller */
6040                 PCI_DEVICE(0x10DE, 0x03E6),
6041                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6042         },
6043         {       /* MCP61 Ethernet Controller */
6044                 PCI_DEVICE(0x10DE, 0x03EE),
6045                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6046         },
6047         {       /* MCP61 Ethernet Controller */
6048                 PCI_DEVICE(0x10DE, 0x03EF),
6049                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6050         },
6051         {       /* MCP65 Ethernet Controller */
6052                 PCI_DEVICE(0x10DE, 0x0450),
6053                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6054         },
6055         {       /* MCP65 Ethernet Controller */
6056                 PCI_DEVICE(0x10DE, 0x0451),
6057                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6058         },
6059         {       /* MCP65 Ethernet Controller */
6060                 PCI_DEVICE(0x10DE, 0x0452),
6061                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6062         },
6063         {       /* MCP65 Ethernet Controller */
6064                 PCI_DEVICE(0x10DE, 0x0453),
6065                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6066         },
6067         {       /* MCP67 Ethernet Controller */
6068                 PCI_DEVICE(0x10DE, 0x054C),
6069                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6070         },
6071         {       /* MCP67 Ethernet Controller */
6072                 PCI_DEVICE(0x10DE, 0x054D),
6073                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6074         },
6075         {       /* MCP67 Ethernet Controller */
6076                 PCI_DEVICE(0x10DE, 0x054E),
6077                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6078         },
6079         {       /* MCP67 Ethernet Controller */
6080                 PCI_DEVICE(0x10DE, 0x054F),
6081                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6082         },
6083         {       /* MCP73 Ethernet Controller */
6084                 PCI_DEVICE(0x10DE, 0x07DC),
6085                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6086         },
6087         {       /* MCP73 Ethernet Controller */
6088                 PCI_DEVICE(0x10DE, 0x07DD),
6089                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6090         },
6091         {       /* MCP73 Ethernet Controller */
6092                 PCI_DEVICE(0x10DE, 0x07DE),
6093                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6094         },
6095         {       /* MCP73 Ethernet Controller */
6096                 PCI_DEVICE(0x10DE, 0x07DF),
6097                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6098         },
6099         {       /* MCP77 Ethernet Controller */
6100                 PCI_DEVICE(0x10DE, 0x0760),
6101                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6102         },
6103         {       /* MCP77 Ethernet Controller */
6104                 PCI_DEVICE(0x10DE, 0x0761),
6105                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6106         },
6107         {       /* MCP77 Ethernet Controller */
6108                 PCI_DEVICE(0x10DE, 0x0762),
6109                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6110         },
6111         {       /* MCP77 Ethernet Controller */
6112                 PCI_DEVICE(0x10DE, 0x0763),
6113                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6114         },
6115         {       /* MCP79 Ethernet Controller */
6116                 PCI_DEVICE(0x10DE, 0x0AB0),
6117                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6118         },
6119         {       /* MCP79 Ethernet Controller */
6120                 PCI_DEVICE(0x10DE, 0x0AB1),
6121                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6122         },
6123         {       /* MCP79 Ethernet Controller */
6124                 PCI_DEVICE(0x10DE, 0x0AB2),
6125                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6126         },
6127         {       /* MCP79 Ethernet Controller */
6128                 PCI_DEVICE(0x10DE, 0x0AB3),
6129                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6130         },
6131         {       /* MCP89 Ethernet Controller */
6132                 PCI_DEVICE(0x10DE, 0x0D7D),
6133                 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX,
6134         },
6135         {0,},
6136 };
6137
6138 static struct pci_driver driver = {
6139         .name           = DRV_NAME,
6140         .id_table       = pci_tbl,
6141         .probe          = nv_probe,
6142         .remove         = __devexit_p(nv_remove),
6143         .shutdown       = nv_shutdown,
6144         .driver.pm      = NV_PM_OPS,
6145 };
6146
6147 static int __init init_nic(void)
6148 {
6149         return pci_register_driver(&driver);
6150 }
6151
6152 static void __exit exit_nic(void)
6153 {
6154         pci_unregister_driver(&driver);
6155 }
6156
6157 module_param(max_interrupt_work, int, 0);
6158 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
6159 module_param(optimization_mode, int, 0);
6160 MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer. In dynamic mode (2), the mode toggles between throughput and CPU mode based on network load.");
6161 module_param(poll_interval, int, 0);
6162 MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
6163 module_param(msi, int, 0);
6164 MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
6165 module_param(msix, int, 0);
6166 MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
6167 module_param(dma_64bit, int, 0);
6168 MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
6169 module_param(phy_cross, int, 0);
6170 MODULE_PARM_DESC(phy_cross, "Phy crossover detection for Realtek 8201 phy is enabled by setting to 1 and disabled by setting to 0.");
6171 module_param(phy_power_down, int, 0);
6172 MODULE_PARM_DESC(phy_power_down, "Power down phy and disable link when interface is down (1), or leave phy powered up (0).");
6173 module_param(debug_tx_timeout, bool, 0);
6174 MODULE_PARM_DESC(debug_tx_timeout,
6175                  "Dump tx related registers and ring when tx_timeout happens");
6176
6177 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
6178 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
6179 MODULE_LICENSE("GPL");
6180
6181 MODULE_DEVICE_TABLE(pci, pci_tbl);
6182
6183 module_init(init_nic);
6184 module_exit(exit_nic);