2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/interrupt.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/firmware.h>
28 #include <linux/pci-aspm.h>
29 #include <linux/prefetch.h>
30 #include <linux/ipv6.h>
31 #include <net/ip6_checksum.h>
36 #define RTL8169_VERSION "2.3LK-NAPI"
37 #define MODULENAME "r8169"
38 #define PFX MODULENAME ": "
40 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
41 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
42 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
43 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
44 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
45 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
46 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
47 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
48 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
49 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
50 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
51 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
52 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
53 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
54 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
55 #define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw"
56 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
57 #define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw"
58 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
61 #define assert(expr) \
63 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
64 #expr,__FILE__,__func__,__LINE__); \
66 #define dprintk(fmt, args...) \
67 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
69 #define assert(expr) do {} while (0)
70 #define dprintk(fmt, args...) do {} while (0)
71 #endif /* RTL8169_DEBUG */
73 #define R8169_MSG_DEFAULT \
74 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
76 #define TX_SLOTS_AVAIL(tp) \
77 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
79 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
80 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
81 (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
83 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
84 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
85 static const int multicast_filter_limit = 32;
87 #define MAX_READ_REQUEST_SHIFT 12
88 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
89 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
91 #define R8169_REGS_SIZE 256
92 #define R8169_NAPI_WEIGHT 64
93 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
94 #define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
95 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
96 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
98 #define RTL8169_TX_TIMEOUT (6*HZ)
99 #define RTL8169_PHY_TIMEOUT (10*HZ)
101 /* write/read MMIO register */
102 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
103 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
104 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
105 #define RTL_R8(reg) readb (ioaddr + (reg))
106 #define RTL_R16(reg) readw (ioaddr + (reg))
107 #define RTL_R32(reg) readl (ioaddr + (reg))
110 RTL_GIGA_MAC_VER_01 = 0,
161 RTL_GIGA_MAC_NONE = 0xff,
164 enum rtl_tx_desc_version {
169 #define JUMBO_1K ETH_DATA_LEN
170 #define JUMBO_4K (4*1024 - ETH_HLEN - 2)
171 #define JUMBO_6K (6*1024 - ETH_HLEN - 2)
172 #define JUMBO_7K (7*1024 - ETH_HLEN - 2)
173 #define JUMBO_9K (9*1024 - ETH_HLEN - 2)
175 #define _R(NAME,TD,FW,SZ,B) { \
183 static const struct {
185 enum rtl_tx_desc_version txd_version;
189 } rtl_chip_infos[] = {
191 [RTL_GIGA_MAC_VER_01] =
192 _R("RTL8169", RTL_TD_0, NULL, JUMBO_7K, true),
193 [RTL_GIGA_MAC_VER_02] =
194 _R("RTL8169s", RTL_TD_0, NULL, JUMBO_7K, true),
195 [RTL_GIGA_MAC_VER_03] =
196 _R("RTL8110s", RTL_TD_0, NULL, JUMBO_7K, true),
197 [RTL_GIGA_MAC_VER_04] =
198 _R("RTL8169sb/8110sb", RTL_TD_0, NULL, JUMBO_7K, true),
199 [RTL_GIGA_MAC_VER_05] =
200 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
201 [RTL_GIGA_MAC_VER_06] =
202 _R("RTL8169sc/8110sc", RTL_TD_0, NULL, JUMBO_7K, true),
204 [RTL_GIGA_MAC_VER_07] =
205 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
206 [RTL_GIGA_MAC_VER_08] =
207 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
208 [RTL_GIGA_MAC_VER_09] =
209 _R("RTL8102e", RTL_TD_1, NULL, JUMBO_1K, true),
210 [RTL_GIGA_MAC_VER_10] =
211 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
212 [RTL_GIGA_MAC_VER_11] =
213 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
214 [RTL_GIGA_MAC_VER_12] =
215 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
216 [RTL_GIGA_MAC_VER_13] =
217 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
218 [RTL_GIGA_MAC_VER_14] =
219 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
220 [RTL_GIGA_MAC_VER_15] =
221 _R("RTL8100e", RTL_TD_0, NULL, JUMBO_1K, true),
222 [RTL_GIGA_MAC_VER_16] =
223 _R("RTL8101e", RTL_TD_0, NULL, JUMBO_1K, true),
224 [RTL_GIGA_MAC_VER_17] =
225 _R("RTL8168b/8111b", RTL_TD_0, NULL, JUMBO_4K, false),
226 [RTL_GIGA_MAC_VER_18] =
227 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
228 [RTL_GIGA_MAC_VER_19] =
229 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
230 [RTL_GIGA_MAC_VER_20] =
231 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
232 [RTL_GIGA_MAC_VER_21] =
233 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
234 [RTL_GIGA_MAC_VER_22] =
235 _R("RTL8168c/8111c", RTL_TD_1, NULL, JUMBO_6K, false),
236 [RTL_GIGA_MAC_VER_23] =
237 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
238 [RTL_GIGA_MAC_VER_24] =
239 _R("RTL8168cp/8111cp", RTL_TD_1, NULL, JUMBO_6K, false),
240 [RTL_GIGA_MAC_VER_25] =
241 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1,
243 [RTL_GIGA_MAC_VER_26] =
244 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2,
246 [RTL_GIGA_MAC_VER_27] =
247 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
248 [RTL_GIGA_MAC_VER_28] =
249 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
250 [RTL_GIGA_MAC_VER_29] =
251 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
253 [RTL_GIGA_MAC_VER_30] =
254 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1,
256 [RTL_GIGA_MAC_VER_31] =
257 _R("RTL8168dp/8111dp", RTL_TD_1, NULL, JUMBO_9K, false),
258 [RTL_GIGA_MAC_VER_32] =
259 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1,
261 [RTL_GIGA_MAC_VER_33] =
262 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2,
264 [RTL_GIGA_MAC_VER_34] =
265 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3,
267 [RTL_GIGA_MAC_VER_35] =
268 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_1,
270 [RTL_GIGA_MAC_VER_36] =
271 _R("RTL8168f/8111f", RTL_TD_1, FIRMWARE_8168F_2,
273 [RTL_GIGA_MAC_VER_37] =
274 _R("RTL8402", RTL_TD_1, FIRMWARE_8402_1,
276 [RTL_GIGA_MAC_VER_38] =
277 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_1,
279 [RTL_GIGA_MAC_VER_39] =
280 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_1,
282 [RTL_GIGA_MAC_VER_40] =
283 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_2,
285 [RTL_GIGA_MAC_VER_41] =
286 _R("RTL8168g/8111g", RTL_TD_1, NULL, JUMBO_9K, false),
287 [RTL_GIGA_MAC_VER_42] =
288 _R("RTL8168g/8111g", RTL_TD_1, FIRMWARE_8168G_3,
290 [RTL_GIGA_MAC_VER_43] =
291 _R("RTL8106e", RTL_TD_1, FIRMWARE_8106E_2,
293 [RTL_GIGA_MAC_VER_44] =
294 _R("RTL8411", RTL_TD_1, FIRMWARE_8411_2,
296 [RTL_GIGA_MAC_VER_45] =
297 _R("RTL8168h/8111h", RTL_TD_1, FIRMWARE_8168H_1,
299 [RTL_GIGA_MAC_VER_46] =
300 _R("RTL8168h/8111h", RTL_TD_1, FIRMWARE_8168H_2,
302 [RTL_GIGA_MAC_VER_47] =
303 _R("RTL8107e", RTL_TD_1, FIRMWARE_8107E_1,
305 [RTL_GIGA_MAC_VER_48] =
306 _R("RTL8107e", RTL_TD_1, FIRMWARE_8107E_2,
308 [RTL_GIGA_MAC_VER_49] =
309 _R("RTL8168ep/8111ep", RTL_TD_1, NULL,
311 [RTL_GIGA_MAC_VER_50] =
312 _R("RTL8168ep/8111ep", RTL_TD_1, NULL,
314 [RTL_GIGA_MAC_VER_51] =
315 _R("RTL8168ep/8111ep", RTL_TD_1, NULL,
326 static const struct pci_device_id rtl8169_pci_tbl[] = {
327 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
328 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
329 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
330 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
331 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
332 { PCI_VENDOR_ID_DLINK, 0x4300,
333 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
334 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
335 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
336 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
337 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
338 { PCI_VENDOR_ID_LINKSYS, 0x1032,
339 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
341 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
345 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
347 static int rx_buf_sz = 16383;
354 MAC0 = 0, /* Ethernet hardware address. */
356 MAR0 = 8, /* Multicast filter. */
357 CounterAddrLow = 0x10,
358 CounterAddrHigh = 0x14,
359 TxDescStartAddrLow = 0x20,
360 TxDescStartAddrHigh = 0x24,
361 TxHDescStartAddrLow = 0x28,
362 TxHDescStartAddrHigh = 0x2c,
371 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
372 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
375 #define RX128_INT_EN (1 << 15) /* 8111c and later */
376 #define RX_MULTI_EN (1 << 14) /* 8111c only */
377 #define RXCFG_FIFO_SHIFT 13
378 /* No threshold before first PCI xfer */
379 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
380 #define RX_EARLY_OFF (1 << 11)
381 #define RXCFG_DMA_SHIFT 8
382 /* Unlimited maximum PCI burst. */
383 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
390 #define PME_SIGNAL (1 << 5) /* 8168c and later */
401 RxDescAddrLow = 0xe4,
402 RxDescAddrHigh = 0xe8,
403 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
405 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
407 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
409 #define TxPacketMax (8064 >> 7)
410 #define EarlySize 0x27
413 FuncEventMask = 0xf4,
414 FuncPresetState = 0xf8,
419 FuncForceEvent = 0xfc,
422 enum rtl8110_registers {
428 enum rtl8168_8101_registers {
431 #define CSIAR_FLAG 0x80000000
432 #define CSIAR_WRITE_CMD 0x80000000
433 #define CSIAR_BYTE_ENABLE 0x0f
434 #define CSIAR_BYTE_ENABLE_SHIFT 12
435 #define CSIAR_ADDR_MASK 0x0fff
436 #define CSIAR_FUNC_CARD 0x00000000
437 #define CSIAR_FUNC_SDIO 0x00010000
438 #define CSIAR_FUNC_NIC 0x00020000
439 #define CSIAR_FUNC_NIC2 0x00010000
442 #define EPHYAR_FLAG 0x80000000
443 #define EPHYAR_WRITE_CMD 0x80000000
444 #define EPHYAR_REG_MASK 0x1f
445 #define EPHYAR_REG_SHIFT 16
446 #define EPHYAR_DATA_MASK 0xffff
448 #define PFM_EN (1 << 6)
449 #define TX_10M_PS_EN (1 << 7)
451 #define FIX_NAK_1 (1 << 4)
452 #define FIX_NAK_2 (1 << 3)
455 #define NOW_IS_OOB (1 << 7)
456 #define TX_EMPTY (1 << 5)
457 #define RX_EMPTY (1 << 4)
458 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
459 #define EN_NDP (1 << 3)
460 #define EN_OOB_RESET (1 << 2)
461 #define LINK_LIST_RDY (1 << 1)
463 #define EFUSEAR_FLAG 0x80000000
464 #define EFUSEAR_WRITE_CMD 0x80000000
465 #define EFUSEAR_READ_CMD 0x00000000
466 #define EFUSEAR_REG_MASK 0x03ff
467 #define EFUSEAR_REG_SHIFT 8
468 #define EFUSEAR_DATA_MASK 0xff
470 #define PFM_D3COLD_EN (1 << 6)
473 enum rtl8168_registers {
478 #define ERIAR_FLAG 0x80000000
479 #define ERIAR_WRITE_CMD 0x80000000
480 #define ERIAR_READ_CMD 0x00000000
481 #define ERIAR_ADDR_BYTE_ALIGN 4
482 #define ERIAR_TYPE_SHIFT 16
483 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
484 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
485 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
486 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
487 #define ERIAR_MASK_SHIFT 12
488 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
489 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
490 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
491 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
492 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
493 EPHY_RXER_NUM = 0x7c,
494 OCPDR = 0xb0, /* OCP GPHY access */
495 #define OCPDR_WRITE_CMD 0x80000000
496 #define OCPDR_READ_CMD 0x00000000
497 #define OCPDR_REG_MASK 0x7f
498 #define OCPDR_GPHY_REG_SHIFT 16
499 #define OCPDR_DATA_MASK 0xffff
501 #define OCPAR_FLAG 0x80000000
502 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
503 #define OCPAR_GPHY_READ_CMD 0x0000f060
505 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
506 MISC = 0xf0, /* 8168e only. */
507 #define TXPLA_RST (1 << 29)
508 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
509 #define PWM_EN (1 << 22)
510 #define RXDV_GATED_EN (1 << 19)
511 #define EARLY_TALLY_EN (1 << 16)
514 enum rtl_register_content {
515 /* InterruptStatusBits */
519 TxDescUnavail = 0x0080,
543 /* TXPoll register p.5 */
544 HPQ = 0x80, /* Poll cmd on the high prio queue */
545 NPQ = 0x40, /* Poll cmd on the low prio queue */
546 FSWInt = 0x01, /* Forced software interrupt */
550 Cfg9346_Unlock = 0xc0,
555 AcceptBroadcast = 0x08,
556 AcceptMulticast = 0x04,
558 AcceptAllPhys = 0x01,
559 #define RX_CONFIG_ACCEPT_MASK 0x3f
562 TxInterFrameGapShift = 24,
563 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
565 /* Config1 register p.24 */
568 Speed_down = (1 << 4),
572 PMEnable = (1 << 0), /* Power Management Enable */
574 /* Config2 register p. 25 */
575 ClkReqEn = (1 << 7), /* Clock Request Enable */
576 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
577 PCI_Clock_66MHz = 0x01,
578 PCI_Clock_33MHz = 0x00,
580 /* Config3 register p.25 */
581 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
582 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
583 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
584 Rdy_to_L23 = (1 << 1), /* L23 Enable */
585 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
587 /* Config4 register */
588 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
590 /* Config5 register p.27 */
591 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
592 MWF = (1 << 5), /* Accept Multicast wakeup frame */
593 UWF = (1 << 4), /* Accept Unicast wakeup frame */
595 LanWake = (1 << 1), /* LanWake enable/disable */
596 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
597 ASPM_en = (1 << 0), /* ASPM enable */
600 TBIReset = 0x80000000,
601 TBILoopback = 0x40000000,
602 TBINwEnable = 0x20000000,
603 TBINwRestart = 0x10000000,
604 TBILinkOk = 0x02000000,
605 TBINwComplete = 0x01000000,
608 EnableBist = (1 << 15), // 8168 8101
609 Mac_dbgo_oe = (1 << 14), // 8168 8101
610 Normal_mode = (1 << 13), // unused
611 Force_half_dup = (1 << 12), // 8168 8101
612 Force_rxflow_en = (1 << 11), // 8168 8101
613 Force_txflow_en = (1 << 10), // 8168 8101
614 Cxpl_dbg_sel = (1 << 9), // 8168 8101
615 ASF = (1 << 8), // 8168 8101
616 PktCntrDisable = (1 << 7), // 8168 8101
617 Mac_dbgo_sel = 0x001c, // 8168
622 INTT_0 = 0x0000, // 8168
623 INTT_1 = 0x0001, // 8168
624 INTT_2 = 0x0002, // 8168
625 INTT_3 = 0x0003, // 8168
627 /* rtl8169_PHYstatus */
638 TBILinkOK = 0x02000000,
640 /* DumpCounterCommand */
643 /* magic enable v2 */
644 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */
648 /* First doubleword. */
649 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
650 RingEnd = (1 << 30), /* End of descriptor ring */
651 FirstFrag = (1 << 29), /* First segment of a packet */
652 LastFrag = (1 << 28), /* Final segment of a packet */
656 enum rtl_tx_desc_bit {
657 /* First doubleword. */
658 TD_LSO = (1 << 27), /* Large Send Offload */
659 #define TD_MSS_MAX 0x07ffu /* MSS value */
661 /* Second doubleword. */
662 TxVlanTag = (1 << 17), /* Add VLAN tag */
665 /* 8169, 8168b and 810x except 8102e. */
666 enum rtl_tx_desc_bit_0 {
667 /* First doubleword. */
668 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
669 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
670 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
671 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
674 /* 8102e, 8168c and beyond. */
675 enum rtl_tx_desc_bit_1 {
676 /* First doubleword. */
677 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
678 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
679 #define GTTCPHO_SHIFT 18
680 #define GTTCPHO_MAX 0x7fU
682 /* Second doubleword. */
683 #define TCPHO_SHIFT 18
684 #define TCPHO_MAX 0x3ffU
685 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
686 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
687 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
688 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
689 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
692 enum rtl_rx_desc_bit {
694 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
695 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
697 #define RxProtoUDP (PID1)
698 #define RxProtoTCP (PID0)
699 #define RxProtoIP (PID1 | PID0)
700 #define RxProtoMask RxProtoIP
702 IPFail = (1 << 16), /* IP checksum failed */
703 UDPFail = (1 << 15), /* UDP/IP checksum failed */
704 TCPFail = (1 << 14), /* TCP/IP checksum failed */
705 RxVlanTag = (1 << 16), /* VLAN tag available */
708 #define RsvdMask 0x3fffc000
725 u8 __pad[sizeof(void *) - sizeof(u32)];
729 RTL_FEATURE_WOL = (1 << 0),
730 RTL_FEATURE_MSI = (1 << 1),
731 RTL_FEATURE_GMII = (1 << 2),
734 struct rtl8169_counters {
741 __le32 tx_one_collision;
742 __le32 tx_multi_collision;
751 RTL_FLAG_TASK_ENABLED,
752 RTL_FLAG_TASK_SLOW_PENDING,
753 RTL_FLAG_TASK_RESET_PENDING,
754 RTL_FLAG_TASK_PHY_PENDING,
758 struct rtl8169_stats {
761 struct u64_stats_sync syncp;
764 struct rtl8169_private {
765 void __iomem *mmio_addr; /* memory map physical address */
766 struct pci_dev *pci_dev;
767 struct net_device *dev;
768 struct napi_struct napi;
772 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
773 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
775 struct rtl8169_stats rx_stats;
776 struct rtl8169_stats tx_stats;
777 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
778 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
779 dma_addr_t TxPhyAddr;
780 dma_addr_t RxPhyAddr;
781 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
782 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
783 struct timer_list timer;
789 void (*write)(struct rtl8169_private *, int, int);
790 int (*read)(struct rtl8169_private *, int);
793 struct pll_power_ops {
794 void (*down)(struct rtl8169_private *);
795 void (*up)(struct rtl8169_private *);
799 void (*enable)(struct rtl8169_private *);
800 void (*disable)(struct rtl8169_private *);
804 void (*write)(struct rtl8169_private *, int, int);
805 u32 (*read)(struct rtl8169_private *, int);
808 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
809 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
810 void (*phy_reset_enable)(struct rtl8169_private *tp);
811 void (*hw_start)(struct net_device *);
812 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
813 unsigned int (*link_ok)(void __iomem *);
814 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
815 bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
818 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
820 struct work_struct work;
825 struct mii_if_info mii;
826 struct rtl8169_counters counters;
831 const struct firmware *fw;
833 #define RTL_VER_SIZE 32
835 char version[RTL_VER_SIZE];
837 struct rtl_fw_phy_action {
842 #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
847 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
848 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
849 module_param(use_dac, int, 0);
850 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
851 module_param_named(debug, debug.msg_enable, int, 0);
852 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
853 MODULE_LICENSE("GPL");
854 MODULE_VERSION(RTL8169_VERSION);
855 MODULE_FIRMWARE(FIRMWARE_8168D_1);
856 MODULE_FIRMWARE(FIRMWARE_8168D_2);
857 MODULE_FIRMWARE(FIRMWARE_8168E_1);
858 MODULE_FIRMWARE(FIRMWARE_8168E_2);
859 MODULE_FIRMWARE(FIRMWARE_8168E_3);
860 MODULE_FIRMWARE(FIRMWARE_8105E_1);
861 MODULE_FIRMWARE(FIRMWARE_8168F_1);
862 MODULE_FIRMWARE(FIRMWARE_8168F_2);
863 MODULE_FIRMWARE(FIRMWARE_8402_1);
864 MODULE_FIRMWARE(FIRMWARE_8411_1);
865 MODULE_FIRMWARE(FIRMWARE_8411_2);
866 MODULE_FIRMWARE(FIRMWARE_8106E_1);
867 MODULE_FIRMWARE(FIRMWARE_8106E_2);
868 MODULE_FIRMWARE(FIRMWARE_8168G_2);
869 MODULE_FIRMWARE(FIRMWARE_8168G_3);
870 MODULE_FIRMWARE(FIRMWARE_8168H_1);
871 MODULE_FIRMWARE(FIRMWARE_8168H_2);
872 MODULE_FIRMWARE(FIRMWARE_8107E_1);
873 MODULE_FIRMWARE(FIRMWARE_8107E_2);
875 static void rtl_lock_work(struct rtl8169_private *tp)
877 mutex_lock(&tp->wk.mutex);
880 static void rtl_unlock_work(struct rtl8169_private *tp)
882 mutex_unlock(&tp->wk.mutex);
885 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
887 pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
888 PCI_EXP_DEVCTL_READRQ, force);
892 bool (*check)(struct rtl8169_private *);
896 static void rtl_udelay(unsigned int d)
901 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
902 void (*delay)(unsigned int), unsigned int d, int n,
907 for (i = 0; i < n; i++) {
909 if (c->check(tp) == high)
912 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
913 c->msg, !high, n, d);
917 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
918 const struct rtl_cond *c,
919 unsigned int d, int n)
921 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
924 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
925 const struct rtl_cond *c,
926 unsigned int d, int n)
928 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
931 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
932 const struct rtl_cond *c,
933 unsigned int d, int n)
935 return rtl_loop_wait(tp, c, msleep, d, n, true);
938 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
939 const struct rtl_cond *c,
940 unsigned int d, int n)
942 return rtl_loop_wait(tp, c, msleep, d, n, false);
945 #define DECLARE_RTL_COND(name) \
946 static bool name ## _check(struct rtl8169_private *); \
948 static const struct rtl_cond name = { \
949 .check = name ## _check, \
953 static bool name ## _check(struct rtl8169_private *tp)
955 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
957 if (reg & 0xffff0001) {
958 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
964 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
966 void __iomem *ioaddr = tp->mmio_addr;
968 return RTL_R32(GPHY_OCP) & OCPAR_FLAG;
971 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
973 void __iomem *ioaddr = tp->mmio_addr;
975 if (rtl_ocp_reg_failure(tp, reg))
978 RTL_W32(GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
980 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
983 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
985 void __iomem *ioaddr = tp->mmio_addr;
987 if (rtl_ocp_reg_failure(tp, reg))
990 RTL_W32(GPHY_OCP, reg << 15);
992 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
993 (RTL_R32(GPHY_OCP) & 0xffff) : ~0;
996 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
998 void __iomem *ioaddr = tp->mmio_addr;
1000 if (rtl_ocp_reg_failure(tp, reg))
1003 RTL_W32(OCPDR, OCPAR_FLAG | (reg << 15) | data);
1006 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
1008 void __iomem *ioaddr = tp->mmio_addr;
1010 if (rtl_ocp_reg_failure(tp, reg))
1013 RTL_W32(OCPDR, reg << 15);
1015 return RTL_R32(OCPDR);
1018 #define OCP_STD_PHY_BASE 0xa400
1020 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
1023 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
1027 if (tp->ocp_base != OCP_STD_PHY_BASE)
1030 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
1033 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
1035 if (tp->ocp_base != OCP_STD_PHY_BASE)
1038 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
1041 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
1044 tp->ocp_base = value << 4;
1048 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
1051 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
1053 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
1056 DECLARE_RTL_COND(rtl_phyar_cond)
1058 void __iomem *ioaddr = tp->mmio_addr;
1060 return RTL_R32(PHYAR) & 0x80000000;
1063 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
1065 void __iomem *ioaddr = tp->mmio_addr;
1067 RTL_W32(PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
1069 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
1071 * According to hardware specs a 20us delay is required after write
1072 * complete indication, but before sending next command.
1077 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
1079 void __iomem *ioaddr = tp->mmio_addr;
1082 RTL_W32(PHYAR, 0x0 | (reg & 0x1f) << 16);
1084 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
1085 RTL_R32(PHYAR) & 0xffff : ~0;
1088 * According to hardware specs a 20us delay is required after read
1089 * complete indication, but before sending next command.
1096 DECLARE_RTL_COND(rtl_ocpar_cond)
1098 void __iomem *ioaddr = tp->mmio_addr;
1100 return RTL_R32(OCPAR) & OCPAR_FLAG;
1103 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
1105 void __iomem *ioaddr = tp->mmio_addr;
1107 RTL_W32(OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
1108 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
1109 RTL_W32(EPHY_RXER_NUM, 0);
1111 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
1114 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
1116 r8168dp_1_mdio_access(tp, reg,
1117 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
1120 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
1122 void __iomem *ioaddr = tp->mmio_addr;
1124 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
1127 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
1128 RTL_W32(EPHY_RXER_NUM, 0);
1130 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
1131 RTL_R32(OCPDR) & OCPDR_DATA_MASK : ~0;
1134 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1136 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
1138 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
1141 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
1143 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
1146 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1148 void __iomem *ioaddr = tp->mmio_addr;
1150 r8168dp_2_mdio_start(ioaddr);
1152 r8169_mdio_write(tp, reg, value);
1154 r8168dp_2_mdio_stop(ioaddr);
1157 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1159 void __iomem *ioaddr = tp->mmio_addr;
1162 r8168dp_2_mdio_start(ioaddr);
1164 value = r8169_mdio_read(tp, reg);
1166 r8168dp_2_mdio_stop(ioaddr);
1171 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1173 tp->mdio_ops.write(tp, location, val);
1176 static int rtl_readphy(struct rtl8169_private *tp, int location)
1178 return tp->mdio_ops.read(tp, location);
1181 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1183 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1186 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1190 val = rtl_readphy(tp, reg_addr);
1191 rtl_writephy(tp, reg_addr, (val & ~m) | p);
1194 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
1197 struct rtl8169_private *tp = netdev_priv(dev);
1199 rtl_writephy(tp, location, val);
1202 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
1204 struct rtl8169_private *tp = netdev_priv(dev);
1206 return rtl_readphy(tp, location);
1209 DECLARE_RTL_COND(rtl_ephyar_cond)
1211 void __iomem *ioaddr = tp->mmio_addr;
1213 return RTL_R32(EPHYAR) & EPHYAR_FLAG;
1216 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1218 void __iomem *ioaddr = tp->mmio_addr;
1220 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1221 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1223 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1228 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1230 void __iomem *ioaddr = tp->mmio_addr;
1232 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1234 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1235 RTL_R32(EPHYAR) & EPHYAR_DATA_MASK : ~0;
1238 DECLARE_RTL_COND(rtl_eriar_cond)
1240 void __iomem *ioaddr = tp->mmio_addr;
1242 return RTL_R32(ERIAR) & ERIAR_FLAG;
1245 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1248 void __iomem *ioaddr = tp->mmio_addr;
1250 BUG_ON((addr & 3) || (mask == 0));
1251 RTL_W32(ERIDR, val);
1252 RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1254 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1257 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1259 void __iomem *ioaddr = tp->mmio_addr;
1261 RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1263 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1264 RTL_R32(ERIDR) : ~0;
1267 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1272 val = rtl_eri_read(tp, addr, type);
1273 rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
1276 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1278 void __iomem *ioaddr = tp->mmio_addr;
1280 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1281 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1282 RTL_R32(OCPDR) : ~0;
1285 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1287 return rtl_eri_read(tp, reg, ERIAR_OOB);
1290 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1292 switch (tp->mac_version) {
1293 case RTL_GIGA_MAC_VER_27:
1294 case RTL_GIGA_MAC_VER_28:
1295 case RTL_GIGA_MAC_VER_31:
1296 return r8168dp_ocp_read(tp, mask, reg);
1297 case RTL_GIGA_MAC_VER_49:
1298 case RTL_GIGA_MAC_VER_50:
1299 case RTL_GIGA_MAC_VER_51:
1300 return r8168ep_ocp_read(tp, mask, reg);
1307 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1310 void __iomem *ioaddr = tp->mmio_addr;
1312 RTL_W32(OCPDR, data);
1313 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1314 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1317 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1320 rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1324 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
1326 switch (tp->mac_version) {
1327 case RTL_GIGA_MAC_VER_27:
1328 case RTL_GIGA_MAC_VER_28:
1329 case RTL_GIGA_MAC_VER_31:
1330 r8168dp_ocp_write(tp, mask, reg, data);
1332 case RTL_GIGA_MAC_VER_49:
1333 case RTL_GIGA_MAC_VER_50:
1334 case RTL_GIGA_MAC_VER_51:
1335 r8168ep_ocp_write(tp, mask, reg, data);
1343 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
1345 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
1347 ocp_write(tp, 0x1, 0x30, 0x00000001);
1350 #define OOB_CMD_RESET 0x00
1351 #define OOB_CMD_DRIVER_START 0x05
1352 #define OOB_CMD_DRIVER_STOP 0x06
1354 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1356 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1359 DECLARE_RTL_COND(rtl_ocp_read_cond)
1363 reg = rtl8168_get_ocp_reg(tp);
1365 return ocp_read(tp, 0x0f, reg) & 0x00000800;
1368 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1370 return ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1373 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1375 void __iomem *ioaddr = tp->mmio_addr;
1377 return RTL_R8(IBISR0) & 0x02;
1380 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1382 void __iomem *ioaddr = tp->mmio_addr;
1384 RTL_W8(IBCR2, RTL_R8(IBCR2) & ~0x01);
1385 rtl_msleep_loop_wait_low(tp, &rtl_ocp_tx_cond, 50, 2000);
1386 RTL_W8(IBISR0, RTL_R8(IBISR0) | 0x20);
1387 RTL_W8(IBCR0, RTL_R8(IBCR0) & ~0x01);
1390 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1392 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
1393 rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
1396 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1398 ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1399 ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1400 rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1403 static void rtl8168_driver_start(struct rtl8169_private *tp)
1405 switch (tp->mac_version) {
1406 case RTL_GIGA_MAC_VER_27:
1407 case RTL_GIGA_MAC_VER_28:
1408 case RTL_GIGA_MAC_VER_31:
1409 rtl8168dp_driver_start(tp);
1411 case RTL_GIGA_MAC_VER_49:
1412 case RTL_GIGA_MAC_VER_50:
1413 case RTL_GIGA_MAC_VER_51:
1414 rtl8168ep_driver_start(tp);
1422 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1424 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1425 rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
1428 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1430 rtl8168ep_stop_cmac(tp);
1431 ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1432 ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1433 rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1436 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1438 switch (tp->mac_version) {
1439 case RTL_GIGA_MAC_VER_27:
1440 case RTL_GIGA_MAC_VER_28:
1441 case RTL_GIGA_MAC_VER_31:
1442 rtl8168dp_driver_stop(tp);
1444 case RTL_GIGA_MAC_VER_49:
1445 case RTL_GIGA_MAC_VER_50:
1446 case RTL_GIGA_MAC_VER_51:
1447 rtl8168ep_driver_stop(tp);
1455 static int r8168dp_check_dash(struct rtl8169_private *tp)
1457 u16 reg = rtl8168_get_ocp_reg(tp);
1459 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
1462 static int r8168ep_check_dash(struct rtl8169_private *tp)
1464 return (ocp_read(tp, 0x0f, 0x128) & 0x00000001) ? 1 : 0;
1467 static int r8168_check_dash(struct rtl8169_private *tp)
1469 switch (tp->mac_version) {
1470 case RTL_GIGA_MAC_VER_27:
1471 case RTL_GIGA_MAC_VER_28:
1472 case RTL_GIGA_MAC_VER_31:
1473 return r8168dp_check_dash(tp);
1474 case RTL_GIGA_MAC_VER_49:
1475 case RTL_GIGA_MAC_VER_50:
1476 case RTL_GIGA_MAC_VER_51:
1477 return r8168ep_check_dash(tp);
1489 static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
1490 const struct exgmac_reg *r, int len)
1493 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1498 DECLARE_RTL_COND(rtl_efusear_cond)
1500 void __iomem *ioaddr = tp->mmio_addr;
1502 return RTL_R32(EFUSEAR) & EFUSEAR_FLAG;
1505 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1507 void __iomem *ioaddr = tp->mmio_addr;
1509 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1511 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1512 RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1515 static u16 rtl_get_events(struct rtl8169_private *tp)
1517 void __iomem *ioaddr = tp->mmio_addr;
1519 return RTL_R16(IntrStatus);
1522 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1524 void __iomem *ioaddr = tp->mmio_addr;
1526 RTL_W16(IntrStatus, bits);
1530 static void rtl_irq_disable(struct rtl8169_private *tp)
1532 void __iomem *ioaddr = tp->mmio_addr;
1534 RTL_W16(IntrMask, 0);
1538 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1540 void __iomem *ioaddr = tp->mmio_addr;
1542 RTL_W16(IntrMask, bits);
1545 #define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1546 #define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1547 #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1549 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1551 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1554 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1556 void __iomem *ioaddr = tp->mmio_addr;
1558 rtl_irq_disable(tp);
1559 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1563 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1565 void __iomem *ioaddr = tp->mmio_addr;
1567 return RTL_R32(TBICSR) & TBIReset;
1570 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1572 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1575 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1577 return RTL_R32(TBICSR) & TBILinkOk;
1580 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1582 return RTL_R8(PHYstatus) & LinkStatus;
1585 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1587 void __iomem *ioaddr = tp->mmio_addr;
1589 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1592 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1596 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1597 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1600 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1602 void __iomem *ioaddr = tp->mmio_addr;
1603 struct net_device *dev = tp->dev;
1605 if (!netif_running(dev))
1608 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1609 tp->mac_version == RTL_GIGA_MAC_VER_38) {
1610 if (RTL_R8(PHYstatus) & _1000bpsF) {
1611 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1613 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1615 } else if (RTL_R8(PHYstatus) & _100bps) {
1616 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1618 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1621 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1623 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1626 /* Reset packet filter */
1627 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1629 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1631 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1632 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1633 if (RTL_R8(PHYstatus) & _1000bpsF) {
1634 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1636 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1639 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1641 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1644 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1645 if (RTL_R8(PHYstatus) & _10bps) {
1646 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1648 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1651 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1657 static void __rtl8169_check_link_status(struct net_device *dev,
1658 struct rtl8169_private *tp,
1659 void __iomem *ioaddr, bool pm)
1661 if (tp->link_ok(ioaddr)) {
1662 rtl_link_chg_patch(tp);
1663 /* This is to cancel a scheduled suspend if there's one. */
1665 pm_request_resume(&tp->pci_dev->dev);
1666 netif_carrier_on(dev);
1667 if (net_ratelimit())
1668 netif_info(tp, ifup, dev, "link up\n");
1670 netif_carrier_off(dev);
1671 netif_info(tp, ifdown, dev, "link down\n");
1673 pm_schedule_suspend(&tp->pci_dev->dev, 5000);
1677 static void rtl8169_check_link_status(struct net_device *dev,
1678 struct rtl8169_private *tp,
1679 void __iomem *ioaddr)
1681 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1684 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1686 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1688 void __iomem *ioaddr = tp->mmio_addr;
1692 options = RTL_R8(Config1);
1693 if (!(options & PMEnable))
1696 options = RTL_R8(Config3);
1697 if (options & LinkUp)
1698 wolopts |= WAKE_PHY;
1699 switch (tp->mac_version) {
1700 case RTL_GIGA_MAC_VER_34:
1701 case RTL_GIGA_MAC_VER_35:
1702 case RTL_GIGA_MAC_VER_36:
1703 case RTL_GIGA_MAC_VER_37:
1704 case RTL_GIGA_MAC_VER_38:
1705 case RTL_GIGA_MAC_VER_40:
1706 case RTL_GIGA_MAC_VER_41:
1707 case RTL_GIGA_MAC_VER_42:
1708 case RTL_GIGA_MAC_VER_43:
1709 case RTL_GIGA_MAC_VER_44:
1710 case RTL_GIGA_MAC_VER_45:
1711 case RTL_GIGA_MAC_VER_46:
1712 case RTL_GIGA_MAC_VER_47:
1713 case RTL_GIGA_MAC_VER_48:
1714 case RTL_GIGA_MAC_VER_49:
1715 case RTL_GIGA_MAC_VER_50:
1716 case RTL_GIGA_MAC_VER_51:
1717 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
1718 wolopts |= WAKE_MAGIC;
1721 if (options & MagicPacket)
1722 wolopts |= WAKE_MAGIC;
1726 options = RTL_R8(Config5);
1728 wolopts |= WAKE_UCAST;
1730 wolopts |= WAKE_BCAST;
1732 wolopts |= WAKE_MCAST;
1737 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1739 struct rtl8169_private *tp = netdev_priv(dev);
1743 wol->supported = WAKE_ANY;
1744 wol->wolopts = __rtl8169_get_wol(tp);
1746 rtl_unlock_work(tp);
1749 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1751 void __iomem *ioaddr = tp->mmio_addr;
1752 unsigned int i, tmp;
1753 static const struct {
1758 { WAKE_PHY, Config3, LinkUp },
1759 { WAKE_UCAST, Config5, UWF },
1760 { WAKE_BCAST, Config5, BWF },
1761 { WAKE_MCAST, Config5, MWF },
1762 { WAKE_ANY, Config5, LanWake },
1763 { WAKE_MAGIC, Config3, MagicPacket }
1767 RTL_W8(Cfg9346, Cfg9346_Unlock);
1769 switch (tp->mac_version) {
1770 case RTL_GIGA_MAC_VER_34:
1771 case RTL_GIGA_MAC_VER_35:
1772 case RTL_GIGA_MAC_VER_36:
1773 case RTL_GIGA_MAC_VER_37:
1774 case RTL_GIGA_MAC_VER_38:
1775 case RTL_GIGA_MAC_VER_40:
1776 case RTL_GIGA_MAC_VER_41:
1777 case RTL_GIGA_MAC_VER_42:
1778 case RTL_GIGA_MAC_VER_43:
1779 case RTL_GIGA_MAC_VER_44:
1780 case RTL_GIGA_MAC_VER_45:
1781 case RTL_GIGA_MAC_VER_46:
1782 case RTL_GIGA_MAC_VER_47:
1783 case RTL_GIGA_MAC_VER_48:
1784 case RTL_GIGA_MAC_VER_49:
1785 case RTL_GIGA_MAC_VER_50:
1786 case RTL_GIGA_MAC_VER_51:
1787 tmp = ARRAY_SIZE(cfg) - 1;
1788 if (wolopts & WAKE_MAGIC)
1804 tmp = ARRAY_SIZE(cfg);
1808 for (i = 0; i < tmp; i++) {
1809 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1810 if (wolopts & cfg[i].opt)
1811 options |= cfg[i].mask;
1812 RTL_W8(cfg[i].reg, options);
1815 switch (tp->mac_version) {
1816 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1817 options = RTL_R8(Config1) & ~PMEnable;
1819 options |= PMEnable;
1820 RTL_W8(Config1, options);
1823 options = RTL_R8(Config2) & ~PME_SIGNAL;
1825 options |= PME_SIGNAL;
1826 RTL_W8(Config2, options);
1830 RTL_W8(Cfg9346, Cfg9346_Lock);
1833 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1835 struct rtl8169_private *tp = netdev_priv(dev);
1840 tp->features |= RTL_FEATURE_WOL;
1842 tp->features &= ~RTL_FEATURE_WOL;
1843 __rtl8169_set_wol(tp, wol->wolopts);
1845 rtl_unlock_work(tp);
1847 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1852 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1854 return rtl_chip_infos[tp->mac_version].fw_name;
1857 static void rtl8169_get_drvinfo(struct net_device *dev,
1858 struct ethtool_drvinfo *info)
1860 struct rtl8169_private *tp = netdev_priv(dev);
1861 struct rtl_fw *rtl_fw = tp->rtl_fw;
1863 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1864 strlcpy(info->version, RTL8169_VERSION, sizeof(info->version));
1865 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1866 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1867 if (!IS_ERR_OR_NULL(rtl_fw))
1868 strlcpy(info->fw_version, rtl_fw->version,
1869 sizeof(info->fw_version));
1872 static int rtl8169_get_regs_len(struct net_device *dev)
1874 return R8169_REGS_SIZE;
1877 static int rtl8169_set_speed_tbi(struct net_device *dev,
1878 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1880 struct rtl8169_private *tp = netdev_priv(dev);
1881 void __iomem *ioaddr = tp->mmio_addr;
1885 reg = RTL_R32(TBICSR);
1886 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1887 (duplex == DUPLEX_FULL)) {
1888 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1889 } else if (autoneg == AUTONEG_ENABLE)
1890 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1892 netif_warn(tp, link, dev,
1893 "incorrect speed setting refused in TBI mode\n");
1900 static int rtl8169_set_speed_xmii(struct net_device *dev,
1901 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1903 struct rtl8169_private *tp = netdev_priv(dev);
1904 int giga_ctrl, bmcr;
1907 rtl_writephy(tp, 0x1f, 0x0000);
1909 if (autoneg == AUTONEG_ENABLE) {
1912 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1913 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1914 ADVERTISE_100HALF | ADVERTISE_100FULL);
1916 if (adv & ADVERTISED_10baseT_Half)
1917 auto_nego |= ADVERTISE_10HALF;
1918 if (adv & ADVERTISED_10baseT_Full)
1919 auto_nego |= ADVERTISE_10FULL;
1920 if (adv & ADVERTISED_100baseT_Half)
1921 auto_nego |= ADVERTISE_100HALF;
1922 if (adv & ADVERTISED_100baseT_Full)
1923 auto_nego |= ADVERTISE_100FULL;
1925 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1927 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1928 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1930 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1931 if (tp->mii.supports_gmii) {
1932 if (adv & ADVERTISED_1000baseT_Half)
1933 giga_ctrl |= ADVERTISE_1000HALF;
1934 if (adv & ADVERTISED_1000baseT_Full)
1935 giga_ctrl |= ADVERTISE_1000FULL;
1936 } else if (adv & (ADVERTISED_1000baseT_Half |
1937 ADVERTISED_1000baseT_Full)) {
1938 netif_info(tp, link, dev,
1939 "PHY does not support 1000Mbps\n");
1943 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1945 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1946 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1950 if (speed == SPEED_10)
1952 else if (speed == SPEED_100)
1953 bmcr = BMCR_SPEED100;
1957 if (duplex == DUPLEX_FULL)
1958 bmcr |= BMCR_FULLDPLX;
1961 rtl_writephy(tp, MII_BMCR, bmcr);
1963 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1964 tp->mac_version == RTL_GIGA_MAC_VER_03) {
1965 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1966 rtl_writephy(tp, 0x17, 0x2138);
1967 rtl_writephy(tp, 0x0e, 0x0260);
1969 rtl_writephy(tp, 0x17, 0x2108);
1970 rtl_writephy(tp, 0x0e, 0x0000);
1979 static int rtl8169_set_speed(struct net_device *dev,
1980 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1982 struct rtl8169_private *tp = netdev_priv(dev);
1985 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1989 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1990 (advertising & ADVERTISED_1000baseT_Full)) {
1991 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1997 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1999 struct rtl8169_private *tp = netdev_priv(dev);
2002 del_timer_sync(&tp->timer);
2005 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
2006 cmd->duplex, cmd->advertising);
2007 rtl_unlock_work(tp);
2012 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
2013 netdev_features_t features)
2015 struct rtl8169_private *tp = netdev_priv(dev);
2017 if (dev->mtu > TD_MSS_MAX)
2018 features &= ~NETIF_F_ALL_TSO;
2020 if (dev->mtu > JUMBO_1K &&
2021 !rtl_chip_infos[tp->mac_version].jumbo_tx_csum)
2022 features &= ~NETIF_F_IP_CSUM;
2027 static void __rtl8169_set_features(struct net_device *dev,
2028 netdev_features_t features)
2030 struct rtl8169_private *tp = netdev_priv(dev);
2031 void __iomem *ioaddr = tp->mmio_addr;
2034 rx_config = RTL_R32(RxConfig);
2035 if (features & NETIF_F_RXALL)
2036 rx_config |= (AcceptErr | AcceptRunt);
2038 rx_config &= ~(AcceptErr | AcceptRunt);
2040 RTL_W32(RxConfig, rx_config);
2042 if (features & NETIF_F_RXCSUM)
2043 tp->cp_cmd |= RxChkSum;
2045 tp->cp_cmd &= ~RxChkSum;
2047 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2048 tp->cp_cmd |= RxVlan;
2050 tp->cp_cmd &= ~RxVlan;
2052 tp->cp_cmd |= RTL_R16(CPlusCmd) & ~(RxVlan | RxChkSum);
2054 RTL_W16(CPlusCmd, tp->cp_cmd);
2058 static int rtl8169_set_features(struct net_device *dev,
2059 netdev_features_t features)
2061 struct rtl8169_private *tp = netdev_priv(dev);
2063 features &= NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX;
2066 if (features ^ dev->features)
2067 __rtl8169_set_features(dev, features);
2068 rtl_unlock_work(tp);
2074 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
2076 return (vlan_tx_tag_present(skb)) ?
2077 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
2080 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
2082 u32 opts2 = le32_to_cpu(desc->opts2);
2084 if (opts2 & RxVlanTag)
2085 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
2088 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
2090 struct rtl8169_private *tp = netdev_priv(dev);
2091 void __iomem *ioaddr = tp->mmio_addr;
2095 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
2096 cmd->port = PORT_FIBRE;
2097 cmd->transceiver = XCVR_INTERNAL;
2099 status = RTL_R32(TBICSR);
2100 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
2101 cmd->autoneg = !!(status & TBINwEnable);
2103 ethtool_cmd_speed_set(cmd, SPEED_1000);
2104 cmd->duplex = DUPLEX_FULL; /* Always set */
2109 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
2111 struct rtl8169_private *tp = netdev_priv(dev);
2113 return mii_ethtool_gset(&tp->mii, cmd);
2116 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2118 struct rtl8169_private *tp = netdev_priv(dev);
2122 rc = tp->get_settings(dev, cmd);
2123 rtl_unlock_work(tp);
2128 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2131 struct rtl8169_private *tp = netdev_priv(dev);
2132 u32 __iomem *data = tp->mmio_addr;
2137 for (i = 0; i < R8169_REGS_SIZE; i += 4)
2138 memcpy_fromio(dw++, data++, 4);
2139 rtl_unlock_work(tp);
2142 static u32 rtl8169_get_msglevel(struct net_device *dev)
2144 struct rtl8169_private *tp = netdev_priv(dev);
2146 return tp->msg_enable;
2149 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
2151 struct rtl8169_private *tp = netdev_priv(dev);
2153 tp->msg_enable = value;
2156 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
2163 "tx_single_collisions",
2164 "tx_multi_collisions",
2172 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
2176 return ARRAY_SIZE(rtl8169_gstrings);
2182 DECLARE_RTL_COND(rtl_counters_cond)
2184 void __iomem *ioaddr = tp->mmio_addr;
2186 return RTL_R32(CounterAddrLow) & CounterDump;
2189 static void rtl8169_update_counters(struct net_device *dev)
2191 struct rtl8169_private *tp = netdev_priv(dev);
2192 void __iomem *ioaddr = tp->mmio_addr;
2193 struct device *d = &tp->pci_dev->dev;
2194 struct rtl8169_counters *counters;
2199 * Some chips are unable to dump tally counters when the receiver
2202 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
2205 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
2209 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
2210 cmd = (u64)paddr & DMA_BIT_MASK(32);
2211 RTL_W32(CounterAddrLow, cmd);
2212 RTL_W32(CounterAddrLow, cmd | CounterDump);
2214 if (rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000))
2215 memcpy(&tp->counters, counters, sizeof(*counters));
2217 RTL_W32(CounterAddrLow, 0);
2218 RTL_W32(CounterAddrHigh, 0);
2220 dma_free_coherent(d, sizeof(*counters), counters, paddr);
2223 static void rtl8169_get_ethtool_stats(struct net_device *dev,
2224 struct ethtool_stats *stats, u64 *data)
2226 struct rtl8169_private *tp = netdev_priv(dev);
2230 rtl8169_update_counters(dev);
2232 data[0] = le64_to_cpu(tp->counters.tx_packets);
2233 data[1] = le64_to_cpu(tp->counters.rx_packets);
2234 data[2] = le64_to_cpu(tp->counters.tx_errors);
2235 data[3] = le32_to_cpu(tp->counters.rx_errors);
2236 data[4] = le16_to_cpu(tp->counters.rx_missed);
2237 data[5] = le16_to_cpu(tp->counters.align_errors);
2238 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
2239 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
2240 data[8] = le64_to_cpu(tp->counters.rx_unicast);
2241 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
2242 data[10] = le32_to_cpu(tp->counters.rx_multicast);
2243 data[11] = le16_to_cpu(tp->counters.tx_aborted);
2244 data[12] = le16_to_cpu(tp->counters.tx_underun);
2247 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2251 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
2256 static const struct ethtool_ops rtl8169_ethtool_ops = {
2257 .get_drvinfo = rtl8169_get_drvinfo,
2258 .get_regs_len = rtl8169_get_regs_len,
2259 .get_link = ethtool_op_get_link,
2260 .get_settings = rtl8169_get_settings,
2261 .set_settings = rtl8169_set_settings,
2262 .get_msglevel = rtl8169_get_msglevel,
2263 .set_msglevel = rtl8169_set_msglevel,
2264 .get_regs = rtl8169_get_regs,
2265 .get_wol = rtl8169_get_wol,
2266 .set_wol = rtl8169_set_wol,
2267 .get_strings = rtl8169_get_strings,
2268 .get_sset_count = rtl8169_get_sset_count,
2269 .get_ethtool_stats = rtl8169_get_ethtool_stats,
2270 .get_ts_info = ethtool_op_get_ts_info,
2273 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
2274 struct net_device *dev, u8 default_version)
2276 void __iomem *ioaddr = tp->mmio_addr;
2278 * The driver currently handles the 8168Bf and the 8168Be identically
2279 * but they can be identified more specifically through the test below
2282 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2284 * Same thing for the 8101Eb and the 8101Ec:
2286 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2288 static const struct rtl_mac_info {
2293 /* 8168EP family. */
2294 { 0x7cf00000, 0x50200000, RTL_GIGA_MAC_VER_51 },
2295 { 0x7cf00000, 0x50100000, RTL_GIGA_MAC_VER_50 },
2296 { 0x7cf00000, 0x50000000, RTL_GIGA_MAC_VER_49 },
2299 { 0x7cf00000, 0x54100000, RTL_GIGA_MAC_VER_46 },
2300 { 0x7cf00000, 0x54000000, RTL_GIGA_MAC_VER_45 },
2303 { 0x7cf00000, 0x5c800000, RTL_GIGA_MAC_VER_44 },
2304 { 0x7cf00000, 0x50900000, RTL_GIGA_MAC_VER_42 },
2305 { 0x7cf00000, 0x4c100000, RTL_GIGA_MAC_VER_41 },
2306 { 0x7cf00000, 0x4c000000, RTL_GIGA_MAC_VER_40 },
2309 { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38 },
2310 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
2311 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
2314 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
2315 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
2316 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
2317 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
2320 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
2321 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
2322 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
2324 /* 8168DP family. */
2325 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
2326 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
2327 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
2330 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
2331 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
2332 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
2333 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
2334 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
2335 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
2336 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
2337 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
2338 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
2341 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
2342 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
2343 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
2344 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
2347 { 0x7cf00000, 0x44900000, RTL_GIGA_MAC_VER_39 },
2348 { 0x7c800000, 0x44800000, RTL_GIGA_MAC_VER_39 },
2349 { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37 },
2350 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
2351 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
2352 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
2353 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2354 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
2355 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
2356 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
2357 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
2358 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
2359 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
2360 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2361 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
2362 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2363 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
2364 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
2365 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
2366 /* FIXME: where did these entries come from ? -- FR */
2367 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
2368 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
2371 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
2372 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
2373 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
2374 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
2375 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
2376 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
2379 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
2381 const struct rtl_mac_info *p = mac_info;
2384 reg = RTL_R32(TxConfig);
2385 while ((reg & p->mask) != p->val)
2387 tp->mac_version = p->mac_version;
2389 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2390 netif_notice(tp, probe, dev,
2391 "unknown MAC, using family default\n");
2392 tp->mac_version = default_version;
2393 } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2394 tp->mac_version = tp->mii.supports_gmii ?
2395 RTL_GIGA_MAC_VER_42 :
2396 RTL_GIGA_MAC_VER_43;
2397 } else if (tp->mac_version == RTL_GIGA_MAC_VER_45) {
2398 tp->mac_version = tp->mii.supports_gmii ?
2399 RTL_GIGA_MAC_VER_45 :
2400 RTL_GIGA_MAC_VER_47;
2401 } else if (tp->mac_version == RTL_GIGA_MAC_VER_46) {
2402 tp->mac_version = tp->mii.supports_gmii ?
2403 RTL_GIGA_MAC_VER_46 :
2404 RTL_GIGA_MAC_VER_48;
2408 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2410 dprintk("mac_version = 0x%02x\n", tp->mac_version);
2418 static void rtl_writephy_batch(struct rtl8169_private *tp,
2419 const struct phy_reg *regs, int len)
2422 rtl_writephy(tp, regs->reg, regs->val);
2427 #define PHY_READ 0x00000000
2428 #define PHY_DATA_OR 0x10000000
2429 #define PHY_DATA_AND 0x20000000
2430 #define PHY_BJMPN 0x30000000
2431 #define PHY_MDIO_CHG 0x40000000
2432 #define PHY_CLEAR_READCOUNT 0x70000000
2433 #define PHY_WRITE 0x80000000
2434 #define PHY_READCOUNT_EQ_SKIP 0x90000000
2435 #define PHY_COMP_EQ_SKIPN 0xa0000000
2436 #define PHY_COMP_NEQ_SKIPN 0xb0000000
2437 #define PHY_WRITE_PREVIOUS 0xc0000000
2438 #define PHY_SKIPN 0xd0000000
2439 #define PHY_DELAY_MS 0xe0000000
2443 char version[RTL_VER_SIZE];
2449 #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2451 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2453 const struct firmware *fw = rtl_fw->fw;
2454 struct fw_info *fw_info = (struct fw_info *)fw->data;
2455 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2456 char *version = rtl_fw->version;
2459 if (fw->size < FW_OPCODE_SIZE)
2462 if (!fw_info->magic) {
2463 size_t i, size, start;
2466 if (fw->size < sizeof(*fw_info))
2469 for (i = 0; i < fw->size; i++)
2470 checksum += fw->data[i];
2474 start = le32_to_cpu(fw_info->fw_start);
2475 if (start > fw->size)
2478 size = le32_to_cpu(fw_info->fw_len);
2479 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2482 memcpy(version, fw_info->version, RTL_VER_SIZE);
2484 pa->code = (__le32 *)(fw->data + start);
2487 if (fw->size % FW_OPCODE_SIZE)
2490 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2492 pa->code = (__le32 *)fw->data;
2493 pa->size = fw->size / FW_OPCODE_SIZE;
2495 version[RTL_VER_SIZE - 1] = 0;
2502 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2503 struct rtl_fw_phy_action *pa)
2508 for (index = 0; index < pa->size; index++) {
2509 u32 action = le32_to_cpu(pa->code[index]);
2510 u32 regno = (action & 0x0fff0000) >> 16;
2512 switch(action & 0xf0000000) {
2517 case PHY_CLEAR_READCOUNT:
2519 case PHY_WRITE_PREVIOUS:
2524 if (regno > index) {
2525 netif_err(tp, ifup, tp->dev,
2526 "Out of range of firmware\n");
2530 case PHY_READCOUNT_EQ_SKIP:
2531 if (index + 2 >= pa->size) {
2532 netif_err(tp, ifup, tp->dev,
2533 "Out of range of firmware\n");
2537 case PHY_COMP_EQ_SKIPN:
2538 case PHY_COMP_NEQ_SKIPN:
2540 if (index + 1 + regno >= pa->size) {
2541 netif_err(tp, ifup, tp->dev,
2542 "Out of range of firmware\n");
2548 netif_err(tp, ifup, tp->dev,
2549 "Invalid action 0x%08x\n", action);
2558 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2560 struct net_device *dev = tp->dev;
2563 if (!rtl_fw_format_ok(tp, rtl_fw)) {
2564 netif_err(tp, ifup, dev, "invalid firwmare\n");
2568 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2574 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2576 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2577 struct mdio_ops org, *ops = &tp->mdio_ops;
2581 predata = count = 0;
2582 org.write = ops->write;
2583 org.read = ops->read;
2585 for (index = 0; index < pa->size; ) {
2586 u32 action = le32_to_cpu(pa->code[index]);
2587 u32 data = action & 0x0000ffff;
2588 u32 regno = (action & 0x0fff0000) >> 16;
2593 switch(action & 0xf0000000) {
2595 predata = rtl_readphy(tp, regno);
2612 ops->write = org.write;
2613 ops->read = org.read;
2614 } else if (data == 1) {
2615 ops->write = mac_mcu_write;
2616 ops->read = mac_mcu_read;
2621 case PHY_CLEAR_READCOUNT:
2626 rtl_writephy(tp, regno, data);
2629 case PHY_READCOUNT_EQ_SKIP:
2630 index += (count == data) ? 2 : 1;
2632 case PHY_COMP_EQ_SKIPN:
2633 if (predata == data)
2637 case PHY_COMP_NEQ_SKIPN:
2638 if (predata != data)
2642 case PHY_WRITE_PREVIOUS:
2643 rtl_writephy(tp, regno, predata);
2659 ops->write = org.write;
2660 ops->read = org.read;
2663 static void rtl_release_firmware(struct rtl8169_private *tp)
2665 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2666 release_firmware(tp->rtl_fw->fw);
2669 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2672 static void rtl_apply_firmware(struct rtl8169_private *tp)
2674 struct rtl_fw *rtl_fw = tp->rtl_fw;
2676 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2677 if (!IS_ERR_OR_NULL(rtl_fw))
2678 rtl_phy_write_fw(tp, rtl_fw);
2681 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2683 if (rtl_readphy(tp, reg) != val)
2684 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2686 rtl_apply_firmware(tp);
2689 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2691 static const struct phy_reg phy_reg_init[] = {
2753 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2756 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2758 static const struct phy_reg phy_reg_init[] = {
2764 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2767 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2769 struct pci_dev *pdev = tp->pci_dev;
2771 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2772 (pdev->subsystem_device != 0xe000))
2775 rtl_writephy(tp, 0x1f, 0x0001);
2776 rtl_writephy(tp, 0x10, 0xf01b);
2777 rtl_writephy(tp, 0x1f, 0x0000);
2780 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2782 static const struct phy_reg phy_reg_init[] = {
2822 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2824 rtl8169scd_hw_phy_config_quirk(tp);
2827 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2829 static const struct phy_reg phy_reg_init[] = {
2877 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2880 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2882 static const struct phy_reg phy_reg_init[] = {
2887 rtl_writephy(tp, 0x1f, 0x0001);
2888 rtl_patchphy(tp, 0x16, 1 << 0);
2890 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2893 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2895 static const struct phy_reg phy_reg_init[] = {
2901 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2904 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2906 static const struct phy_reg phy_reg_init[] = {
2914 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2917 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2919 static const struct phy_reg phy_reg_init[] = {
2925 rtl_writephy(tp, 0x1f, 0x0000);
2926 rtl_patchphy(tp, 0x14, 1 << 5);
2927 rtl_patchphy(tp, 0x0d, 1 << 5);
2929 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2932 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2934 static const struct phy_reg phy_reg_init[] = {
2954 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2956 rtl_patchphy(tp, 0x14, 1 << 5);
2957 rtl_patchphy(tp, 0x0d, 1 << 5);
2958 rtl_writephy(tp, 0x1f, 0x0000);
2961 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2963 static const struct phy_reg phy_reg_init[] = {
2981 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2983 rtl_patchphy(tp, 0x16, 1 << 0);
2984 rtl_patchphy(tp, 0x14, 1 << 5);
2985 rtl_patchphy(tp, 0x0d, 1 << 5);
2986 rtl_writephy(tp, 0x1f, 0x0000);
2989 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2991 static const struct phy_reg phy_reg_init[] = {
3003 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3005 rtl_patchphy(tp, 0x16, 1 << 0);
3006 rtl_patchphy(tp, 0x14, 1 << 5);
3007 rtl_patchphy(tp, 0x0d, 1 << 5);
3008 rtl_writephy(tp, 0x1f, 0x0000);
3011 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
3013 rtl8168c_3_hw_phy_config(tp);
3016 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
3018 static const struct phy_reg phy_reg_init_0[] = {
3019 /* Channel Estimation */
3040 * Enhance line driver power
3049 * Can not link to 1Gbps with bad cable
3050 * Decrease SNR threshold form 21.07dB to 19.04dB
3059 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
3063 * Fine Tune Switching regulator parameter
3065 rtl_writephy(tp, 0x1f, 0x0002);
3066 rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
3067 rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
3069 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3070 static const struct phy_reg phy_reg_init[] = {
3080 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3082 val = rtl_readphy(tp, 0x0d);
3084 if ((val & 0x00ff) != 0x006c) {
3085 static const u32 set[] = {
3086 0x0065, 0x0066, 0x0067, 0x0068,
3087 0x0069, 0x006a, 0x006b, 0x006c
3091 rtl_writephy(tp, 0x1f, 0x0002);
3094 for (i = 0; i < ARRAY_SIZE(set); i++)
3095 rtl_writephy(tp, 0x0d, val | set[i]);
3098 static const struct phy_reg phy_reg_init[] = {
3106 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3109 /* RSET couple improve */
3110 rtl_writephy(tp, 0x1f, 0x0002);
3111 rtl_patchphy(tp, 0x0d, 0x0300);
3112 rtl_patchphy(tp, 0x0f, 0x0010);
3114 /* Fine tune PLL performance */
3115 rtl_writephy(tp, 0x1f, 0x0002);
3116 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3117 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3119 rtl_writephy(tp, 0x1f, 0x0005);
3120 rtl_writephy(tp, 0x05, 0x001b);
3122 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
3124 rtl_writephy(tp, 0x1f, 0x0000);
3127 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
3129 static const struct phy_reg phy_reg_init_0[] = {
3130 /* Channel Estimation */
3151 * Enhance line driver power
3160 * Can not link to 1Gbps with bad cable
3161 * Decrease SNR threshold form 21.07dB to 19.04dB
3170 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
3172 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
3173 static const struct phy_reg phy_reg_init[] = {
3184 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3186 val = rtl_readphy(tp, 0x0d);
3187 if ((val & 0x00ff) != 0x006c) {
3188 static const u32 set[] = {
3189 0x0065, 0x0066, 0x0067, 0x0068,
3190 0x0069, 0x006a, 0x006b, 0x006c
3194 rtl_writephy(tp, 0x1f, 0x0002);
3197 for (i = 0; i < ARRAY_SIZE(set); i++)
3198 rtl_writephy(tp, 0x0d, val | set[i]);
3201 static const struct phy_reg phy_reg_init[] = {
3209 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3212 /* Fine tune PLL performance */
3213 rtl_writephy(tp, 0x1f, 0x0002);
3214 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
3215 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
3217 /* Switching regulator Slew rate */
3218 rtl_writephy(tp, 0x1f, 0x0002);
3219 rtl_patchphy(tp, 0x0f, 0x0017);
3221 rtl_writephy(tp, 0x1f, 0x0005);
3222 rtl_writephy(tp, 0x05, 0x001b);
3224 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
3226 rtl_writephy(tp, 0x1f, 0x0000);
3229 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
3231 static const struct phy_reg phy_reg_init[] = {
3287 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3290 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3292 static const struct phy_reg phy_reg_init[] = {
3302 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3303 rtl_patchphy(tp, 0x0d, 1 << 5);
3306 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3308 static const struct phy_reg phy_reg_init[] = {
3309 /* Enable Delay cap */
3315 /* Channel estimation fine tune */
3324 /* Update PFM & 10M TX idle timer */
3336 rtl_apply_firmware(tp);
3338 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3340 /* DCO enable for 10M IDLE Power */
3341 rtl_writephy(tp, 0x1f, 0x0007);
3342 rtl_writephy(tp, 0x1e, 0x0023);
3343 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3344 rtl_writephy(tp, 0x1f, 0x0000);
3346 /* For impedance matching */
3347 rtl_writephy(tp, 0x1f, 0x0002);
3348 rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
3349 rtl_writephy(tp, 0x1f, 0x0000);
3351 /* PHY auto speed down */
3352 rtl_writephy(tp, 0x1f, 0x0007);
3353 rtl_writephy(tp, 0x1e, 0x002d);
3354 rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
3355 rtl_writephy(tp, 0x1f, 0x0000);
3356 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3358 rtl_writephy(tp, 0x1f, 0x0005);
3359 rtl_writephy(tp, 0x05, 0x8b86);
3360 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3361 rtl_writephy(tp, 0x1f, 0x0000);
3363 rtl_writephy(tp, 0x1f, 0x0005);
3364 rtl_writephy(tp, 0x05, 0x8b85);
3365 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3366 rtl_writephy(tp, 0x1f, 0x0007);
3367 rtl_writephy(tp, 0x1e, 0x0020);
3368 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
3369 rtl_writephy(tp, 0x1f, 0x0006);
3370 rtl_writephy(tp, 0x00, 0x5a00);
3371 rtl_writephy(tp, 0x1f, 0x0000);
3372 rtl_writephy(tp, 0x0d, 0x0007);
3373 rtl_writephy(tp, 0x0e, 0x003c);
3374 rtl_writephy(tp, 0x0d, 0x4007);
3375 rtl_writephy(tp, 0x0e, 0x0000);
3376 rtl_writephy(tp, 0x0d, 0x0000);
3379 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3382 addr[0] | (addr[1] << 8),
3383 addr[2] | (addr[3] << 8),
3384 addr[4] | (addr[5] << 8)
3386 const struct exgmac_reg e[] = {
3387 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3388 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3389 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3390 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3393 rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3396 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3398 static const struct phy_reg phy_reg_init[] = {
3399 /* Enable Delay cap */
3408 /* Channel estimation fine tune */
3425 rtl_apply_firmware(tp);
3427 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3429 /* For 4-corner performance improve */
3430 rtl_writephy(tp, 0x1f, 0x0005);
3431 rtl_writephy(tp, 0x05, 0x8b80);
3432 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3433 rtl_writephy(tp, 0x1f, 0x0000);
3435 /* PHY auto speed down */
3436 rtl_writephy(tp, 0x1f, 0x0004);
3437 rtl_writephy(tp, 0x1f, 0x0007);
3438 rtl_writephy(tp, 0x1e, 0x002d);
3439 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3440 rtl_writephy(tp, 0x1f, 0x0002);
3441 rtl_writephy(tp, 0x1f, 0x0000);
3442 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3444 /* improve 10M EEE waveform */
3445 rtl_writephy(tp, 0x1f, 0x0005);
3446 rtl_writephy(tp, 0x05, 0x8b86);
3447 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3448 rtl_writephy(tp, 0x1f, 0x0000);
3450 /* Improve 2-pair detection performance */
3451 rtl_writephy(tp, 0x1f, 0x0005);
3452 rtl_writephy(tp, 0x05, 0x8b85);
3453 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3454 rtl_writephy(tp, 0x1f, 0x0000);
3457 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, ERIAR_EXGMAC);
3458 rtl_writephy(tp, 0x1f, 0x0005);
3459 rtl_writephy(tp, 0x05, 0x8b85);
3460 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3461 rtl_writephy(tp, 0x1f, 0x0004);
3462 rtl_writephy(tp, 0x1f, 0x0007);
3463 rtl_writephy(tp, 0x1e, 0x0020);
3464 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
3465 rtl_writephy(tp, 0x1f, 0x0002);
3466 rtl_writephy(tp, 0x1f, 0x0000);
3467 rtl_writephy(tp, 0x0d, 0x0007);
3468 rtl_writephy(tp, 0x0e, 0x003c);
3469 rtl_writephy(tp, 0x0d, 0x4007);
3470 rtl_writephy(tp, 0x0e, 0x0000);
3471 rtl_writephy(tp, 0x0d, 0x0000);
3474 rtl_writephy(tp, 0x1f, 0x0003);
3475 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3476 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3477 rtl_writephy(tp, 0x1f, 0x0000);
3479 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3480 rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3483 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3485 /* For 4-corner performance improve */
3486 rtl_writephy(tp, 0x1f, 0x0005);
3487 rtl_writephy(tp, 0x05, 0x8b80);
3488 rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3489 rtl_writephy(tp, 0x1f, 0x0000);
3491 /* PHY auto speed down */
3492 rtl_writephy(tp, 0x1f, 0x0007);
3493 rtl_writephy(tp, 0x1e, 0x002d);
3494 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3495 rtl_writephy(tp, 0x1f, 0x0000);
3496 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3498 /* Improve 10M EEE waveform */
3499 rtl_writephy(tp, 0x1f, 0x0005);
3500 rtl_writephy(tp, 0x05, 0x8b86);
3501 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3502 rtl_writephy(tp, 0x1f, 0x0000);
3505 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3507 static const struct phy_reg phy_reg_init[] = {
3508 /* Channel estimation fine tune */
3513 /* Modify green table for giga & fnet */
3530 /* Modify green table for 10M */
3536 /* Disable hiimpedance detection (RTCT) */
3542 rtl_apply_firmware(tp);
3544 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3546 rtl8168f_hw_phy_config(tp);
3548 /* Improve 2-pair detection performance */
3549 rtl_writephy(tp, 0x1f, 0x0005);
3550 rtl_writephy(tp, 0x05, 0x8b85);
3551 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3552 rtl_writephy(tp, 0x1f, 0x0000);
3555 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3557 rtl_apply_firmware(tp);
3559 rtl8168f_hw_phy_config(tp);
3562 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3564 static const struct phy_reg phy_reg_init[] = {
3565 /* Channel estimation fine tune */
3570 /* Modify green table for giga & fnet */
3587 /* Modify green table for 10M */
3593 /* Disable hiimpedance detection (RTCT) */
3600 rtl_apply_firmware(tp);
3602 rtl8168f_hw_phy_config(tp);
3604 /* Improve 2-pair detection performance */
3605 rtl_writephy(tp, 0x1f, 0x0005);
3606 rtl_writephy(tp, 0x05, 0x8b85);
3607 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3608 rtl_writephy(tp, 0x1f, 0x0000);
3610 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3612 /* Modify green table for giga */
3613 rtl_writephy(tp, 0x1f, 0x0005);
3614 rtl_writephy(tp, 0x05, 0x8b54);
3615 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3616 rtl_writephy(tp, 0x05, 0x8b5d);
3617 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3618 rtl_writephy(tp, 0x05, 0x8a7c);
3619 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3620 rtl_writephy(tp, 0x05, 0x8a7f);
3621 rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3622 rtl_writephy(tp, 0x05, 0x8a82);
3623 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3624 rtl_writephy(tp, 0x05, 0x8a85);
3625 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3626 rtl_writephy(tp, 0x05, 0x8a88);
3627 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3628 rtl_writephy(tp, 0x1f, 0x0000);
3630 /* uc same-seed solution */
3631 rtl_writephy(tp, 0x1f, 0x0005);
3632 rtl_writephy(tp, 0x05, 0x8b85);
3633 rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3634 rtl_writephy(tp, 0x1f, 0x0000);
3637 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
3638 rtl_writephy(tp, 0x1f, 0x0005);
3639 rtl_writephy(tp, 0x05, 0x8b85);
3640 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3641 rtl_writephy(tp, 0x1f, 0x0004);
3642 rtl_writephy(tp, 0x1f, 0x0007);
3643 rtl_writephy(tp, 0x1e, 0x0020);
3644 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
3645 rtl_writephy(tp, 0x1f, 0x0000);
3646 rtl_writephy(tp, 0x0d, 0x0007);
3647 rtl_writephy(tp, 0x0e, 0x003c);
3648 rtl_writephy(tp, 0x0d, 0x4007);
3649 rtl_writephy(tp, 0x0e, 0x0000);
3650 rtl_writephy(tp, 0x0d, 0x0000);
3653 rtl_writephy(tp, 0x1f, 0x0003);
3654 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3655 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3656 rtl_writephy(tp, 0x1f, 0x0000);
3659 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3661 rtl_apply_firmware(tp);
3663 rtl_writephy(tp, 0x1f, 0x0a46);
3664 if (rtl_readphy(tp, 0x10) & 0x0100) {
3665 rtl_writephy(tp, 0x1f, 0x0bcc);
3666 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
3668 rtl_writephy(tp, 0x1f, 0x0bcc);
3669 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
3672 rtl_writephy(tp, 0x1f, 0x0a46);
3673 if (rtl_readphy(tp, 0x13) & 0x0100) {
3674 rtl_writephy(tp, 0x1f, 0x0c41);
3675 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
3677 rtl_writephy(tp, 0x1f, 0x0c41);
3678 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
3681 /* Enable PHY auto speed down */
3682 rtl_writephy(tp, 0x1f, 0x0a44);
3683 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3685 rtl_writephy(tp, 0x1f, 0x0bcc);
3686 rtl_w0w1_phy(tp, 0x14, 0x0100, 0x0000);
3687 rtl_writephy(tp, 0x1f, 0x0a44);
3688 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3689 rtl_writephy(tp, 0x1f, 0x0a43);
3690 rtl_writephy(tp, 0x13, 0x8084);
3691 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3692 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3694 /* EEE auto-fallback function */
3695 rtl_writephy(tp, 0x1f, 0x0a4b);
3696 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3698 /* Enable UC LPF tune function */
3699 rtl_writephy(tp, 0x1f, 0x0a43);
3700 rtl_writephy(tp, 0x13, 0x8012);
3701 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3703 rtl_writephy(tp, 0x1f, 0x0c42);
3704 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3706 /* Improve SWR Efficiency */
3707 rtl_writephy(tp, 0x1f, 0x0bcd);
3708 rtl_writephy(tp, 0x14, 0x5065);
3709 rtl_writephy(tp, 0x14, 0xd065);
3710 rtl_writephy(tp, 0x1f, 0x0bc8);
3711 rtl_writephy(tp, 0x11, 0x5655);
3712 rtl_writephy(tp, 0x1f, 0x0bcd);
3713 rtl_writephy(tp, 0x14, 0x1065);
3714 rtl_writephy(tp, 0x14, 0x9065);
3715 rtl_writephy(tp, 0x14, 0x1065);
3717 /* Check ALDPS bit, disable it if enabled */
3718 rtl_writephy(tp, 0x1f, 0x0a43);
3719 if (rtl_readphy(tp, 0x10) & 0x0004)
3720 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3722 rtl_writephy(tp, 0x1f, 0x0000);
3725 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3727 rtl_apply_firmware(tp);
3730 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3735 rtl_apply_firmware(tp);
3737 /* CHN EST parameters adjust - giga master */
3738 rtl_writephy(tp, 0x1f, 0x0a43);
3739 rtl_writephy(tp, 0x13, 0x809b);
3740 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3741 rtl_writephy(tp, 0x13, 0x80a2);
3742 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3743 rtl_writephy(tp, 0x13, 0x80a4);
3744 rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3745 rtl_writephy(tp, 0x13, 0x809c);
3746 rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3747 rtl_writephy(tp, 0x1f, 0x0000);
3749 /* CHN EST parameters adjust - giga slave */
3750 rtl_writephy(tp, 0x1f, 0x0a43);
3751 rtl_writephy(tp, 0x13, 0x80ad);
3752 rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
3753 rtl_writephy(tp, 0x13, 0x80b4);
3754 rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
3755 rtl_writephy(tp, 0x13, 0x80ac);
3756 rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
3757 rtl_writephy(tp, 0x1f, 0x0000);
3759 /* CHN EST parameters adjust - fnet */
3760 rtl_writephy(tp, 0x1f, 0x0a43);
3761 rtl_writephy(tp, 0x13, 0x808e);
3762 rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
3763 rtl_writephy(tp, 0x13, 0x8090);
3764 rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
3765 rtl_writephy(tp, 0x13, 0x8092);
3766 rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
3767 rtl_writephy(tp, 0x1f, 0x0000);
3769 /* enable R-tune & PGA-retune function */
3771 rtl_writephy(tp, 0x1f, 0x0a46);
3772 data = rtl_readphy(tp, 0x13);
3775 dout_tapbin |= data;
3776 data = rtl_readphy(tp, 0x12);
3779 dout_tapbin |= data;
3780 dout_tapbin = ~(dout_tapbin^0x08);
3782 dout_tapbin &= 0xf000;
3783 rtl_writephy(tp, 0x1f, 0x0a43);
3784 rtl_writephy(tp, 0x13, 0x827a);
3785 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3786 rtl_writephy(tp, 0x13, 0x827b);
3787 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3788 rtl_writephy(tp, 0x13, 0x827c);
3789 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3790 rtl_writephy(tp, 0x13, 0x827d);
3791 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3793 rtl_writephy(tp, 0x1f, 0x0a43);
3794 rtl_writephy(tp, 0x13, 0x0811);
3795 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3796 rtl_writephy(tp, 0x1f, 0x0a42);
3797 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3798 rtl_writephy(tp, 0x1f, 0x0000);
3800 /* enable GPHY 10M */
3801 rtl_writephy(tp, 0x1f, 0x0a44);
3802 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3803 rtl_writephy(tp, 0x1f, 0x0000);
3805 /* SAR ADC performance */
3806 rtl_writephy(tp, 0x1f, 0x0bca);
3807 rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
3808 rtl_writephy(tp, 0x1f, 0x0000);
3810 rtl_writephy(tp, 0x1f, 0x0a43);
3811 rtl_writephy(tp, 0x13, 0x803f);
3812 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3813 rtl_writephy(tp, 0x13, 0x8047);
3814 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3815 rtl_writephy(tp, 0x13, 0x804f);
3816 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3817 rtl_writephy(tp, 0x13, 0x8057);
3818 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3819 rtl_writephy(tp, 0x13, 0x805f);
3820 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3821 rtl_writephy(tp, 0x13, 0x8067);
3822 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3823 rtl_writephy(tp, 0x13, 0x806f);
3824 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3825 rtl_writephy(tp, 0x1f, 0x0000);
3827 /* disable phy pfm mode */
3828 rtl_writephy(tp, 0x1f, 0x0a44);
3829 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0080);
3830 rtl_writephy(tp, 0x1f, 0x0000);
3832 /* Check ALDPS bit, disable it if enabled */
3833 rtl_writephy(tp, 0x1f, 0x0a43);
3834 if (rtl_readphy(tp, 0x10) & 0x0004)
3835 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3837 rtl_writephy(tp, 0x1f, 0x0000);
3840 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3842 u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3846 rtl_apply_firmware(tp);
3848 /* CHIN EST parameter update */
3849 rtl_writephy(tp, 0x1f, 0x0a43);
3850 rtl_writephy(tp, 0x13, 0x808a);
3851 rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
3852 rtl_writephy(tp, 0x1f, 0x0000);
3854 /* enable R-tune & PGA-retune function */
3855 rtl_writephy(tp, 0x1f, 0x0a43);
3856 rtl_writephy(tp, 0x13, 0x0811);
3857 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3858 rtl_writephy(tp, 0x1f, 0x0a42);
3859 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3860 rtl_writephy(tp, 0x1f, 0x0000);
3862 /* enable GPHY 10M */
3863 rtl_writephy(tp, 0x1f, 0x0a44);
3864 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3865 rtl_writephy(tp, 0x1f, 0x0000);
3867 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3868 data = r8168_mac_ocp_read(tp, 0xdd02);
3869 ioffset_p3 = ((data & 0x80)>>7);
3872 data = r8168_mac_ocp_read(tp, 0xdd00);
3873 ioffset_p3 |= ((data & (0xe000))>>13);
3874 ioffset_p2 = ((data & (0x1e00))>>9);
3875 ioffset_p1 = ((data & (0x01e0))>>5);
3876 ioffset_p0 = ((data & 0x0010)>>4);
3878 ioffset_p0 |= (data & (0x07));
3879 data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3881 if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
3882 (ioffset_p1 != 0x0f) || (ioffset_p0 == 0x0f)) {
3883 rtl_writephy(tp, 0x1f, 0x0bcf);
3884 rtl_writephy(tp, 0x16, data);
3885 rtl_writephy(tp, 0x1f, 0x0000);
3888 /* Modify rlen (TX LPF corner frequency) level */
3889 rtl_writephy(tp, 0x1f, 0x0bcd);
3890 data = rtl_readphy(tp, 0x16);
3895 data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3896 rtl_writephy(tp, 0x17, data);
3897 rtl_writephy(tp, 0x1f, 0x0bcd);
3898 rtl_writephy(tp, 0x1f, 0x0000);
3900 /* disable phy pfm mode */
3901 rtl_writephy(tp, 0x1f, 0x0a44);
3902 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0080);
3903 rtl_writephy(tp, 0x1f, 0x0000);
3905 /* Check ALDPS bit, disable it if enabled */
3906 rtl_writephy(tp, 0x1f, 0x0a43);
3907 if (rtl_readphy(tp, 0x10) & 0x0004)
3908 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3910 rtl_writephy(tp, 0x1f, 0x0000);
3913 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3915 /* Enable PHY auto speed down */
3916 rtl_writephy(tp, 0x1f, 0x0a44);
3917 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3918 rtl_writephy(tp, 0x1f, 0x0000);
3920 /* patch 10M & ALDPS */
3921 rtl_writephy(tp, 0x1f, 0x0bcc);
3922 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
3923 rtl_writephy(tp, 0x1f, 0x0a44);
3924 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3925 rtl_writephy(tp, 0x1f, 0x0a43);
3926 rtl_writephy(tp, 0x13, 0x8084);
3927 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3928 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3929 rtl_writephy(tp, 0x1f, 0x0000);
3931 /* Enable EEE auto-fallback function */
3932 rtl_writephy(tp, 0x1f, 0x0a4b);
3933 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3934 rtl_writephy(tp, 0x1f, 0x0000);
3936 /* Enable UC LPF tune function */
3937 rtl_writephy(tp, 0x1f, 0x0a43);
3938 rtl_writephy(tp, 0x13, 0x8012);
3939 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3940 rtl_writephy(tp, 0x1f, 0x0000);
3942 /* set rg_sel_sdm_rate */
3943 rtl_writephy(tp, 0x1f, 0x0c42);
3944 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3945 rtl_writephy(tp, 0x1f, 0x0000);
3947 /* Check ALDPS bit, disable it if enabled */
3948 rtl_writephy(tp, 0x1f, 0x0a43);
3949 if (rtl_readphy(tp, 0x10) & 0x0004)
3950 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3952 rtl_writephy(tp, 0x1f, 0x0000);
3955 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
3957 /* patch 10M & ALDPS */
3958 rtl_writephy(tp, 0x1f, 0x0bcc);
3959 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
3960 rtl_writephy(tp, 0x1f, 0x0a44);
3961 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3962 rtl_writephy(tp, 0x1f, 0x0a43);
3963 rtl_writephy(tp, 0x13, 0x8084);
3964 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3965 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3966 rtl_writephy(tp, 0x1f, 0x0000);
3968 /* Enable UC LPF tune function */
3969 rtl_writephy(tp, 0x1f, 0x0a43);
3970 rtl_writephy(tp, 0x13, 0x8012);
3971 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3972 rtl_writephy(tp, 0x1f, 0x0000);
3974 /* Set rg_sel_sdm_rate */
3975 rtl_writephy(tp, 0x1f, 0x0c42);
3976 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3977 rtl_writephy(tp, 0x1f, 0x0000);
3979 /* Channel estimation parameters */
3980 rtl_writephy(tp, 0x1f, 0x0a43);
3981 rtl_writephy(tp, 0x13, 0x80f3);
3982 rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
3983 rtl_writephy(tp, 0x13, 0x80f0);
3984 rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
3985 rtl_writephy(tp, 0x13, 0x80ef);
3986 rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
3987 rtl_writephy(tp, 0x13, 0x80f6);
3988 rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
3989 rtl_writephy(tp, 0x13, 0x80ec);
3990 rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
3991 rtl_writephy(tp, 0x13, 0x80ed);
3992 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3993 rtl_writephy(tp, 0x13, 0x80f2);
3994 rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
3995 rtl_writephy(tp, 0x13, 0x80f4);
3996 rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
3997 rtl_writephy(tp, 0x1f, 0x0a43);
3998 rtl_writephy(tp, 0x13, 0x8110);
3999 rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
4000 rtl_writephy(tp, 0x13, 0x810f);
4001 rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
4002 rtl_writephy(tp, 0x13, 0x8111);
4003 rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
4004 rtl_writephy(tp, 0x13, 0x8113);
4005 rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
4006 rtl_writephy(tp, 0x13, 0x8115);
4007 rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
4008 rtl_writephy(tp, 0x13, 0x810e);
4009 rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
4010 rtl_writephy(tp, 0x13, 0x810c);
4011 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
4012 rtl_writephy(tp, 0x13, 0x810b);
4013 rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
4014 rtl_writephy(tp, 0x1f, 0x0a43);
4015 rtl_writephy(tp, 0x13, 0x80d1);
4016 rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
4017 rtl_writephy(tp, 0x13, 0x80cd);
4018 rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
4019 rtl_writephy(tp, 0x13, 0x80d3);
4020 rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
4021 rtl_writephy(tp, 0x13, 0x80d5);
4022 rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
4023 rtl_writephy(tp, 0x13, 0x80d7);
4024 rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
4026 /* Force PWM-mode */
4027 rtl_writephy(tp, 0x1f, 0x0bcd);
4028 rtl_writephy(tp, 0x14, 0x5065);
4029 rtl_writephy(tp, 0x14, 0xd065);
4030 rtl_writephy(tp, 0x1f, 0x0bc8);
4031 rtl_writephy(tp, 0x12, 0x00ed);
4032 rtl_writephy(tp, 0x1f, 0x0bcd);
4033 rtl_writephy(tp, 0x14, 0x1065);
4034 rtl_writephy(tp, 0x14, 0x9065);
4035 rtl_writephy(tp, 0x14, 0x1065);
4036 rtl_writephy(tp, 0x1f, 0x0000);
4038 /* Check ALDPS bit, disable it if enabled */
4039 rtl_writephy(tp, 0x1f, 0x0a43);
4040 if (rtl_readphy(tp, 0x10) & 0x0004)
4041 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
4043 rtl_writephy(tp, 0x1f, 0x0000);
4046 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
4048 static const struct phy_reg phy_reg_init[] = {
4055 rtl_writephy(tp, 0x1f, 0x0000);
4056 rtl_patchphy(tp, 0x11, 1 << 12);
4057 rtl_patchphy(tp, 0x19, 1 << 13);
4058 rtl_patchphy(tp, 0x10, 1 << 15);
4060 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4063 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
4065 static const struct phy_reg phy_reg_init[] = {
4079 /* Disable ALDPS before ram code */
4080 rtl_writephy(tp, 0x1f, 0x0000);
4081 rtl_writephy(tp, 0x18, 0x0310);
4084 rtl_apply_firmware(tp);
4086 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4089 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
4091 /* Disable ALDPS before setting firmware */
4092 rtl_writephy(tp, 0x1f, 0x0000);
4093 rtl_writephy(tp, 0x18, 0x0310);
4096 rtl_apply_firmware(tp);
4099 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4100 rtl_writephy(tp, 0x1f, 0x0004);
4101 rtl_writephy(tp, 0x10, 0x401f);
4102 rtl_writephy(tp, 0x19, 0x7030);
4103 rtl_writephy(tp, 0x1f, 0x0000);
4106 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
4108 static const struct phy_reg phy_reg_init[] = {
4115 /* Disable ALDPS before ram code */
4116 rtl_writephy(tp, 0x1f, 0x0000);
4117 rtl_writephy(tp, 0x18, 0x0310);
4120 rtl_apply_firmware(tp);
4122 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4123 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
4125 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4128 static void rtl_hw_phy_config(struct net_device *dev)
4130 struct rtl8169_private *tp = netdev_priv(dev);
4132 rtl8169_print_mac_version(tp);
4134 switch (tp->mac_version) {
4135 case RTL_GIGA_MAC_VER_01:
4137 case RTL_GIGA_MAC_VER_02:
4138 case RTL_GIGA_MAC_VER_03:
4139 rtl8169s_hw_phy_config(tp);
4141 case RTL_GIGA_MAC_VER_04:
4142 rtl8169sb_hw_phy_config(tp);
4144 case RTL_GIGA_MAC_VER_05:
4145 rtl8169scd_hw_phy_config(tp);
4147 case RTL_GIGA_MAC_VER_06:
4148 rtl8169sce_hw_phy_config(tp);
4150 case RTL_GIGA_MAC_VER_07:
4151 case RTL_GIGA_MAC_VER_08:
4152 case RTL_GIGA_MAC_VER_09:
4153 rtl8102e_hw_phy_config(tp);
4155 case RTL_GIGA_MAC_VER_11:
4156 rtl8168bb_hw_phy_config(tp);
4158 case RTL_GIGA_MAC_VER_12:
4159 rtl8168bef_hw_phy_config(tp);
4161 case RTL_GIGA_MAC_VER_17:
4162 rtl8168bef_hw_phy_config(tp);
4164 case RTL_GIGA_MAC_VER_18:
4165 rtl8168cp_1_hw_phy_config(tp);
4167 case RTL_GIGA_MAC_VER_19:
4168 rtl8168c_1_hw_phy_config(tp);
4170 case RTL_GIGA_MAC_VER_20:
4171 rtl8168c_2_hw_phy_config(tp);
4173 case RTL_GIGA_MAC_VER_21:
4174 rtl8168c_3_hw_phy_config(tp);
4176 case RTL_GIGA_MAC_VER_22:
4177 rtl8168c_4_hw_phy_config(tp);
4179 case RTL_GIGA_MAC_VER_23:
4180 case RTL_GIGA_MAC_VER_24:
4181 rtl8168cp_2_hw_phy_config(tp);
4183 case RTL_GIGA_MAC_VER_25:
4184 rtl8168d_1_hw_phy_config(tp);
4186 case RTL_GIGA_MAC_VER_26:
4187 rtl8168d_2_hw_phy_config(tp);
4189 case RTL_GIGA_MAC_VER_27:
4190 rtl8168d_3_hw_phy_config(tp);
4192 case RTL_GIGA_MAC_VER_28:
4193 rtl8168d_4_hw_phy_config(tp);
4195 case RTL_GIGA_MAC_VER_29:
4196 case RTL_GIGA_MAC_VER_30:
4197 rtl8105e_hw_phy_config(tp);
4199 case RTL_GIGA_MAC_VER_31:
4202 case RTL_GIGA_MAC_VER_32:
4203 case RTL_GIGA_MAC_VER_33:
4204 rtl8168e_1_hw_phy_config(tp);
4206 case RTL_GIGA_MAC_VER_34:
4207 rtl8168e_2_hw_phy_config(tp);
4209 case RTL_GIGA_MAC_VER_35:
4210 rtl8168f_1_hw_phy_config(tp);
4212 case RTL_GIGA_MAC_VER_36:
4213 rtl8168f_2_hw_phy_config(tp);
4216 case RTL_GIGA_MAC_VER_37:
4217 rtl8402_hw_phy_config(tp);
4220 case RTL_GIGA_MAC_VER_38:
4221 rtl8411_hw_phy_config(tp);
4224 case RTL_GIGA_MAC_VER_39:
4225 rtl8106e_hw_phy_config(tp);
4228 case RTL_GIGA_MAC_VER_40:
4229 rtl8168g_1_hw_phy_config(tp);
4231 case RTL_GIGA_MAC_VER_42:
4232 case RTL_GIGA_MAC_VER_43:
4233 case RTL_GIGA_MAC_VER_44:
4234 rtl8168g_2_hw_phy_config(tp);
4236 case RTL_GIGA_MAC_VER_45:
4237 case RTL_GIGA_MAC_VER_47:
4238 rtl8168h_1_hw_phy_config(tp);
4240 case RTL_GIGA_MAC_VER_46:
4241 case RTL_GIGA_MAC_VER_48:
4242 rtl8168h_2_hw_phy_config(tp);
4245 case RTL_GIGA_MAC_VER_49:
4246 rtl8168ep_1_hw_phy_config(tp);
4248 case RTL_GIGA_MAC_VER_50:
4249 case RTL_GIGA_MAC_VER_51:
4250 rtl8168ep_2_hw_phy_config(tp);
4253 case RTL_GIGA_MAC_VER_41:
4259 static void rtl_phy_work(struct rtl8169_private *tp)
4261 struct timer_list *timer = &tp->timer;
4262 void __iomem *ioaddr = tp->mmio_addr;
4263 unsigned long timeout = RTL8169_PHY_TIMEOUT;
4265 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
4267 if (tp->phy_reset_pending(tp)) {
4269 * A busy loop could burn quite a few cycles on nowadays CPU.
4270 * Let's delay the execution of the timer for a few ticks.
4276 if (tp->link_ok(ioaddr))
4279 netif_dbg(tp, link, tp->dev, "PHY reset until link up\n");
4281 tp->phy_reset_enable(tp);
4284 mod_timer(timer, jiffies + timeout);
4287 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
4289 if (!test_and_set_bit(flag, tp->wk.flags))
4290 schedule_work(&tp->wk.work);
4293 static void rtl8169_phy_timer(unsigned long __opaque)
4295 struct net_device *dev = (struct net_device *)__opaque;
4296 struct rtl8169_private *tp = netdev_priv(dev);
4298 rtl_schedule_task(tp, RTL_FLAG_TASK_PHY_PENDING);
4301 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
4302 void __iomem *ioaddr)
4305 pci_release_regions(pdev);
4306 pci_clear_mwi(pdev);
4307 pci_disable_device(pdev);
4311 DECLARE_RTL_COND(rtl_phy_reset_cond)
4313 return tp->phy_reset_pending(tp);
4316 static void rtl8169_phy_reset(struct net_device *dev,
4317 struct rtl8169_private *tp)
4319 tp->phy_reset_enable(tp);
4320 rtl_msleep_loop_wait_low(tp, &rtl_phy_reset_cond, 1, 100);
4323 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
4325 void __iomem *ioaddr = tp->mmio_addr;
4327 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
4328 (RTL_R8(PHYstatus) & TBI_Enable);
4331 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
4333 void __iomem *ioaddr = tp->mmio_addr;
4335 rtl_hw_phy_config(dev);
4337 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
4338 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4342 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4344 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
4345 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4347 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4348 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4350 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4351 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4354 rtl8169_phy_reset(dev, tp);
4356 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
4357 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4358 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4359 (tp->mii.supports_gmii ?
4360 ADVERTISED_1000baseT_Half |
4361 ADVERTISED_1000baseT_Full : 0));
4363 if (rtl_tbi_enabled(tp))
4364 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4367 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4369 void __iomem *ioaddr = tp->mmio_addr;
4373 RTL_W8(Cfg9346, Cfg9346_Unlock);
4375 RTL_W32(MAC4, addr[4] | addr[5] << 8);
4378 RTL_W32(MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
4381 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4382 rtl_rar_exgmac_set(tp, addr);
4384 RTL_W8(Cfg9346, Cfg9346_Lock);
4386 rtl_unlock_work(tp);
4389 static int rtl_set_mac_address(struct net_device *dev, void *p)
4391 struct rtl8169_private *tp = netdev_priv(dev);
4392 struct sockaddr *addr = p;
4394 if (!is_valid_ether_addr(addr->sa_data))
4395 return -EADDRNOTAVAIL;
4397 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
4399 rtl_rar_set(tp, dev->dev_addr);
4404 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4406 struct rtl8169_private *tp = netdev_priv(dev);
4407 struct mii_ioctl_data *data = if_mii(ifr);
4409 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
4412 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
4413 struct mii_ioctl_data *data, int cmd)
4417 data->phy_id = 32; /* Internal PHY */
4421 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
4425 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
4431 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
4436 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
4438 if (tp->features & RTL_FEATURE_MSI) {
4439 pci_disable_msi(pdev);
4440 tp->features &= ~RTL_FEATURE_MSI;
4444 static void rtl_init_mdio_ops(struct rtl8169_private *tp)
4446 struct mdio_ops *ops = &tp->mdio_ops;
4448 switch (tp->mac_version) {
4449 case RTL_GIGA_MAC_VER_27:
4450 ops->write = r8168dp_1_mdio_write;
4451 ops->read = r8168dp_1_mdio_read;
4453 case RTL_GIGA_MAC_VER_28:
4454 case RTL_GIGA_MAC_VER_31:
4455 ops->write = r8168dp_2_mdio_write;
4456 ops->read = r8168dp_2_mdio_read;
4458 case RTL_GIGA_MAC_VER_40:
4459 case RTL_GIGA_MAC_VER_41:
4460 case RTL_GIGA_MAC_VER_42:
4461 case RTL_GIGA_MAC_VER_43:
4462 case RTL_GIGA_MAC_VER_44:
4463 case RTL_GIGA_MAC_VER_45:
4464 case RTL_GIGA_MAC_VER_46:
4465 case RTL_GIGA_MAC_VER_47:
4466 case RTL_GIGA_MAC_VER_48:
4467 case RTL_GIGA_MAC_VER_49:
4468 case RTL_GIGA_MAC_VER_50:
4469 case RTL_GIGA_MAC_VER_51:
4470 ops->write = r8168g_mdio_write;
4471 ops->read = r8168g_mdio_read;
4474 ops->write = r8169_mdio_write;
4475 ops->read = r8169_mdio_read;
4480 static void rtl_speed_down(struct rtl8169_private *tp)
4485 rtl_writephy(tp, 0x1f, 0x0000);
4486 lpa = rtl_readphy(tp, MII_LPA);
4488 if (lpa & (LPA_10HALF | LPA_10FULL))
4489 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full;
4490 else if (lpa & (LPA_100HALF | LPA_100FULL))
4491 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4492 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4494 adv = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4495 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
4496 (tp->mii.supports_gmii ?
4497 ADVERTISED_1000baseT_Half |
4498 ADVERTISED_1000baseT_Full : 0);
4500 rtl8169_set_speed(tp->dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
4504 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4506 void __iomem *ioaddr = tp->mmio_addr;
4508 switch (tp->mac_version) {
4509 case RTL_GIGA_MAC_VER_25:
4510 case RTL_GIGA_MAC_VER_26:
4511 case RTL_GIGA_MAC_VER_29:
4512 case RTL_GIGA_MAC_VER_30:
4513 case RTL_GIGA_MAC_VER_32:
4514 case RTL_GIGA_MAC_VER_33:
4515 case RTL_GIGA_MAC_VER_34:
4516 case RTL_GIGA_MAC_VER_37:
4517 case RTL_GIGA_MAC_VER_38:
4518 case RTL_GIGA_MAC_VER_39:
4519 case RTL_GIGA_MAC_VER_40:
4520 case RTL_GIGA_MAC_VER_41:
4521 case RTL_GIGA_MAC_VER_42:
4522 case RTL_GIGA_MAC_VER_43:
4523 case RTL_GIGA_MAC_VER_44:
4524 case RTL_GIGA_MAC_VER_45:
4525 case RTL_GIGA_MAC_VER_46:
4526 case RTL_GIGA_MAC_VER_47:
4527 case RTL_GIGA_MAC_VER_48:
4528 case RTL_GIGA_MAC_VER_49:
4529 case RTL_GIGA_MAC_VER_50:
4530 case RTL_GIGA_MAC_VER_51:
4531 RTL_W32(RxConfig, RTL_R32(RxConfig) |
4532 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4539 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
4541 if (!(__rtl8169_get_wol(tp) & WAKE_ANY))
4545 rtl_wol_suspend_quirk(tp);
4550 static void r810x_phy_power_down(struct rtl8169_private *tp)
4552 rtl_writephy(tp, 0x1f, 0x0000);
4553 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4556 static void r810x_phy_power_up(struct rtl8169_private *tp)
4558 rtl_writephy(tp, 0x1f, 0x0000);
4559 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4562 static void r810x_pll_power_down(struct rtl8169_private *tp)
4564 void __iomem *ioaddr = tp->mmio_addr;
4566 if (rtl_wol_pll_power_down(tp))
4569 r810x_phy_power_down(tp);
4571 switch (tp->mac_version) {
4572 case RTL_GIGA_MAC_VER_07:
4573 case RTL_GIGA_MAC_VER_08:
4574 case RTL_GIGA_MAC_VER_09:
4575 case RTL_GIGA_MAC_VER_10:
4576 case RTL_GIGA_MAC_VER_13:
4577 case RTL_GIGA_MAC_VER_16:
4580 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4585 static void r810x_pll_power_up(struct rtl8169_private *tp)
4587 void __iomem *ioaddr = tp->mmio_addr;
4589 r810x_phy_power_up(tp);
4591 switch (tp->mac_version) {
4592 case RTL_GIGA_MAC_VER_07:
4593 case RTL_GIGA_MAC_VER_08:
4594 case RTL_GIGA_MAC_VER_09:
4595 case RTL_GIGA_MAC_VER_10:
4596 case RTL_GIGA_MAC_VER_13:
4597 case RTL_GIGA_MAC_VER_16:
4599 case RTL_GIGA_MAC_VER_47:
4600 case RTL_GIGA_MAC_VER_48:
4601 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
4604 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4609 static void r8168_phy_power_up(struct rtl8169_private *tp)
4611 rtl_writephy(tp, 0x1f, 0x0000);
4612 switch (tp->mac_version) {
4613 case RTL_GIGA_MAC_VER_11:
4614 case RTL_GIGA_MAC_VER_12:
4615 case RTL_GIGA_MAC_VER_17:
4616 case RTL_GIGA_MAC_VER_18:
4617 case RTL_GIGA_MAC_VER_19:
4618 case RTL_GIGA_MAC_VER_20:
4619 case RTL_GIGA_MAC_VER_21:
4620 case RTL_GIGA_MAC_VER_22:
4621 case RTL_GIGA_MAC_VER_23:
4622 case RTL_GIGA_MAC_VER_24:
4623 case RTL_GIGA_MAC_VER_25:
4624 case RTL_GIGA_MAC_VER_26:
4625 case RTL_GIGA_MAC_VER_27:
4626 case RTL_GIGA_MAC_VER_28:
4627 case RTL_GIGA_MAC_VER_31:
4628 rtl_writephy(tp, 0x0e, 0x0000);
4633 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
4636 static void r8168_phy_power_down(struct rtl8169_private *tp)
4638 rtl_writephy(tp, 0x1f, 0x0000);
4639 switch (tp->mac_version) {
4640 case RTL_GIGA_MAC_VER_32:
4641 case RTL_GIGA_MAC_VER_33:
4642 case RTL_GIGA_MAC_VER_40:
4643 case RTL_GIGA_MAC_VER_41:
4644 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
4647 case RTL_GIGA_MAC_VER_11:
4648 case RTL_GIGA_MAC_VER_12:
4649 case RTL_GIGA_MAC_VER_17:
4650 case RTL_GIGA_MAC_VER_18:
4651 case RTL_GIGA_MAC_VER_19:
4652 case RTL_GIGA_MAC_VER_20:
4653 case RTL_GIGA_MAC_VER_21:
4654 case RTL_GIGA_MAC_VER_22:
4655 case RTL_GIGA_MAC_VER_23:
4656 case RTL_GIGA_MAC_VER_24:
4657 case RTL_GIGA_MAC_VER_25:
4658 case RTL_GIGA_MAC_VER_26:
4659 case RTL_GIGA_MAC_VER_27:
4660 case RTL_GIGA_MAC_VER_28:
4661 case RTL_GIGA_MAC_VER_31:
4662 rtl_writephy(tp, 0x0e, 0x0200);
4664 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
4669 static void r8168_pll_power_down(struct rtl8169_private *tp)
4671 void __iomem *ioaddr = tp->mmio_addr;
4673 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4674 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
4675 tp->mac_version == RTL_GIGA_MAC_VER_31 ||
4676 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
4677 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
4678 tp->mac_version == RTL_GIGA_MAC_VER_51) &&
4679 r8168_check_dash(tp)) {
4683 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
4684 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
4685 (RTL_R16(CPlusCmd) & ASF)) {
4689 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4690 tp->mac_version == RTL_GIGA_MAC_VER_33)
4691 rtl_ephy_write(tp, 0x19, 0xff64);
4693 if (rtl_wol_pll_power_down(tp))
4696 r8168_phy_power_down(tp);
4698 switch (tp->mac_version) {
4699 case RTL_GIGA_MAC_VER_25:
4700 case RTL_GIGA_MAC_VER_26:
4701 case RTL_GIGA_MAC_VER_27:
4702 case RTL_GIGA_MAC_VER_28:
4703 case RTL_GIGA_MAC_VER_31:
4704 case RTL_GIGA_MAC_VER_32:
4705 case RTL_GIGA_MAC_VER_33:
4706 case RTL_GIGA_MAC_VER_44:
4707 case RTL_GIGA_MAC_VER_45:
4708 case RTL_GIGA_MAC_VER_46:
4709 case RTL_GIGA_MAC_VER_50:
4710 case RTL_GIGA_MAC_VER_51:
4711 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4713 case RTL_GIGA_MAC_VER_40:
4714 case RTL_GIGA_MAC_VER_41:
4715 case RTL_GIGA_MAC_VER_49:
4716 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
4717 0xfc000000, ERIAR_EXGMAC);
4718 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
4723 static void r8168_pll_power_up(struct rtl8169_private *tp)
4725 void __iomem *ioaddr = tp->mmio_addr;
4727 switch (tp->mac_version) {
4728 case RTL_GIGA_MAC_VER_25:
4729 case RTL_GIGA_MAC_VER_26:
4730 case RTL_GIGA_MAC_VER_27:
4731 case RTL_GIGA_MAC_VER_28:
4732 case RTL_GIGA_MAC_VER_31:
4733 case RTL_GIGA_MAC_VER_32:
4734 case RTL_GIGA_MAC_VER_33:
4735 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
4737 case RTL_GIGA_MAC_VER_44:
4738 case RTL_GIGA_MAC_VER_45:
4739 case RTL_GIGA_MAC_VER_46:
4740 case RTL_GIGA_MAC_VER_50:
4741 case RTL_GIGA_MAC_VER_51:
4742 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
4744 case RTL_GIGA_MAC_VER_40:
4745 case RTL_GIGA_MAC_VER_41:
4746 case RTL_GIGA_MAC_VER_49:
4747 RTL_W8(PMCH, RTL_R8(PMCH) | 0xc0);
4748 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
4749 0x00000000, ERIAR_EXGMAC);
4753 r8168_phy_power_up(tp);
4756 static void rtl_generic_op(struct rtl8169_private *tp,
4757 void (*op)(struct rtl8169_private *))
4763 static void rtl_pll_power_down(struct rtl8169_private *tp)
4765 rtl_generic_op(tp, tp->pll_power_ops.down);
4768 static void rtl_pll_power_up(struct rtl8169_private *tp)
4770 rtl_generic_op(tp, tp->pll_power_ops.up);
4773 static void rtl_init_pll_power_ops(struct rtl8169_private *tp)
4775 struct pll_power_ops *ops = &tp->pll_power_ops;
4777 switch (tp->mac_version) {
4778 case RTL_GIGA_MAC_VER_07:
4779 case RTL_GIGA_MAC_VER_08:
4780 case RTL_GIGA_MAC_VER_09:
4781 case RTL_GIGA_MAC_VER_10:
4782 case RTL_GIGA_MAC_VER_16:
4783 case RTL_GIGA_MAC_VER_29:
4784 case RTL_GIGA_MAC_VER_30:
4785 case RTL_GIGA_MAC_VER_37:
4786 case RTL_GIGA_MAC_VER_39:
4787 case RTL_GIGA_MAC_VER_43:
4788 case RTL_GIGA_MAC_VER_47:
4789 case RTL_GIGA_MAC_VER_48:
4790 ops->down = r810x_pll_power_down;
4791 ops->up = r810x_pll_power_up;
4794 case RTL_GIGA_MAC_VER_11:
4795 case RTL_GIGA_MAC_VER_12:
4796 case RTL_GIGA_MAC_VER_17:
4797 case RTL_GIGA_MAC_VER_18:
4798 case RTL_GIGA_MAC_VER_19:
4799 case RTL_GIGA_MAC_VER_20:
4800 case RTL_GIGA_MAC_VER_21:
4801 case RTL_GIGA_MAC_VER_22:
4802 case RTL_GIGA_MAC_VER_23:
4803 case RTL_GIGA_MAC_VER_24:
4804 case RTL_GIGA_MAC_VER_25:
4805 case RTL_GIGA_MAC_VER_26:
4806 case RTL_GIGA_MAC_VER_27:
4807 case RTL_GIGA_MAC_VER_28:
4808 case RTL_GIGA_MAC_VER_31:
4809 case RTL_GIGA_MAC_VER_32:
4810 case RTL_GIGA_MAC_VER_33:
4811 case RTL_GIGA_MAC_VER_34:
4812 case RTL_GIGA_MAC_VER_35:
4813 case RTL_GIGA_MAC_VER_36:
4814 case RTL_GIGA_MAC_VER_38:
4815 case RTL_GIGA_MAC_VER_40:
4816 case RTL_GIGA_MAC_VER_41:
4817 case RTL_GIGA_MAC_VER_42:
4818 case RTL_GIGA_MAC_VER_44:
4819 case RTL_GIGA_MAC_VER_45:
4820 case RTL_GIGA_MAC_VER_46:
4821 case RTL_GIGA_MAC_VER_49:
4822 case RTL_GIGA_MAC_VER_50:
4823 case RTL_GIGA_MAC_VER_51:
4824 ops->down = r8168_pll_power_down;
4825 ops->up = r8168_pll_power_up;
4835 static void rtl_init_rxcfg(struct rtl8169_private *tp)
4837 void __iomem *ioaddr = tp->mmio_addr;
4839 switch (tp->mac_version) {
4840 case RTL_GIGA_MAC_VER_01:
4841 case RTL_GIGA_MAC_VER_02:
4842 case RTL_GIGA_MAC_VER_03:
4843 case RTL_GIGA_MAC_VER_04:
4844 case RTL_GIGA_MAC_VER_05:
4845 case RTL_GIGA_MAC_VER_06:
4846 case RTL_GIGA_MAC_VER_10:
4847 case RTL_GIGA_MAC_VER_11:
4848 case RTL_GIGA_MAC_VER_12:
4849 case RTL_GIGA_MAC_VER_13:
4850 case RTL_GIGA_MAC_VER_14:
4851 case RTL_GIGA_MAC_VER_15:
4852 case RTL_GIGA_MAC_VER_16:
4853 case RTL_GIGA_MAC_VER_17:
4854 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4856 case RTL_GIGA_MAC_VER_18:
4857 case RTL_GIGA_MAC_VER_19:
4858 case RTL_GIGA_MAC_VER_20:
4859 case RTL_GIGA_MAC_VER_21:
4860 case RTL_GIGA_MAC_VER_22:
4861 case RTL_GIGA_MAC_VER_23:
4862 case RTL_GIGA_MAC_VER_24:
4863 case RTL_GIGA_MAC_VER_34:
4864 case RTL_GIGA_MAC_VER_35:
4865 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4867 case RTL_GIGA_MAC_VER_40:
4868 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
4870 case RTL_GIGA_MAC_VER_41:
4871 case RTL_GIGA_MAC_VER_42:
4872 case RTL_GIGA_MAC_VER_43:
4873 case RTL_GIGA_MAC_VER_44:
4874 case RTL_GIGA_MAC_VER_45:
4875 case RTL_GIGA_MAC_VER_46:
4876 case RTL_GIGA_MAC_VER_47:
4877 case RTL_GIGA_MAC_VER_48:
4878 case RTL_GIGA_MAC_VER_49:
4879 case RTL_GIGA_MAC_VER_50:
4880 case RTL_GIGA_MAC_VER_51:
4881 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST | RX_EARLY_OFF);
4884 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
4889 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4891 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
4894 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4896 void __iomem *ioaddr = tp->mmio_addr;
4898 RTL_W8(Cfg9346, Cfg9346_Unlock);
4899 rtl_generic_op(tp, tp->jumbo_ops.enable);
4900 RTL_W8(Cfg9346, Cfg9346_Lock);
4903 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4905 void __iomem *ioaddr = tp->mmio_addr;
4907 RTL_W8(Cfg9346, Cfg9346_Unlock);
4908 rtl_generic_op(tp, tp->jumbo_ops.disable);
4909 RTL_W8(Cfg9346, Cfg9346_Lock);
4912 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4914 void __iomem *ioaddr = tp->mmio_addr;
4916 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4917 RTL_W8(Config4, RTL_R8(Config4) | Jumbo_En1);
4918 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
4921 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4923 void __iomem *ioaddr = tp->mmio_addr;
4925 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4926 RTL_W8(Config4, RTL_R8(Config4) & ~Jumbo_En1);
4927 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
4930 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4932 void __iomem *ioaddr = tp->mmio_addr;
4934 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4937 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4939 void __iomem *ioaddr = tp->mmio_addr;
4941 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4944 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4946 void __iomem *ioaddr = tp->mmio_addr;
4948 RTL_W8(MaxTxPacketSize, 0x3f);
4949 RTL_W8(Config3, RTL_R8(Config3) | Jumbo_En0);
4950 RTL_W8(Config4, RTL_R8(Config4) | 0x01);
4951 rtl_tx_performance_tweak(tp->pci_dev, 0x2 << MAX_READ_REQUEST_SHIFT);
4954 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4956 void __iomem *ioaddr = tp->mmio_addr;
4958 RTL_W8(MaxTxPacketSize, 0x0c);
4959 RTL_W8(Config3, RTL_R8(Config3) & ~Jumbo_En0);
4960 RTL_W8(Config4, RTL_R8(Config4) & ~0x01);
4961 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
4964 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4966 rtl_tx_performance_tweak(tp->pci_dev,
4967 (0x2 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4970 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4972 rtl_tx_performance_tweak(tp->pci_dev,
4973 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
4976 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4978 void __iomem *ioaddr = tp->mmio_addr;
4980 r8168b_0_hw_jumbo_enable(tp);
4982 RTL_W8(Config4, RTL_R8(Config4) | (1 << 0));
4985 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4987 void __iomem *ioaddr = tp->mmio_addr;
4989 r8168b_0_hw_jumbo_disable(tp);
4991 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4994 static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
4996 struct jumbo_ops *ops = &tp->jumbo_ops;
4998 switch (tp->mac_version) {
4999 case RTL_GIGA_MAC_VER_11:
5000 ops->disable = r8168b_0_hw_jumbo_disable;
5001 ops->enable = r8168b_0_hw_jumbo_enable;
5003 case RTL_GIGA_MAC_VER_12:
5004 case RTL_GIGA_MAC_VER_17:
5005 ops->disable = r8168b_1_hw_jumbo_disable;
5006 ops->enable = r8168b_1_hw_jumbo_enable;
5008 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
5009 case RTL_GIGA_MAC_VER_19:
5010 case RTL_GIGA_MAC_VER_20:
5011 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
5012 case RTL_GIGA_MAC_VER_22:
5013 case RTL_GIGA_MAC_VER_23:
5014 case RTL_GIGA_MAC_VER_24:
5015 case RTL_GIGA_MAC_VER_25:
5016 case RTL_GIGA_MAC_VER_26:
5017 ops->disable = r8168c_hw_jumbo_disable;
5018 ops->enable = r8168c_hw_jumbo_enable;
5020 case RTL_GIGA_MAC_VER_27:
5021 case RTL_GIGA_MAC_VER_28:
5022 ops->disable = r8168dp_hw_jumbo_disable;
5023 ops->enable = r8168dp_hw_jumbo_enable;
5025 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
5026 case RTL_GIGA_MAC_VER_32:
5027 case RTL_GIGA_MAC_VER_33:
5028 case RTL_GIGA_MAC_VER_34:
5029 ops->disable = r8168e_hw_jumbo_disable;
5030 ops->enable = r8168e_hw_jumbo_enable;
5034 * No action needed for jumbo frames with 8169.
5035 * No jumbo for 810x at all.
5037 case RTL_GIGA_MAC_VER_40:
5038 case RTL_GIGA_MAC_VER_41:
5039 case RTL_GIGA_MAC_VER_42:
5040 case RTL_GIGA_MAC_VER_43:
5041 case RTL_GIGA_MAC_VER_44:
5042 case RTL_GIGA_MAC_VER_45:
5043 case RTL_GIGA_MAC_VER_46:
5044 case RTL_GIGA_MAC_VER_47:
5045 case RTL_GIGA_MAC_VER_48:
5046 case RTL_GIGA_MAC_VER_49:
5047 case RTL_GIGA_MAC_VER_50:
5048 case RTL_GIGA_MAC_VER_51:
5050 ops->disable = NULL;
5056 DECLARE_RTL_COND(rtl_chipcmd_cond)
5058 void __iomem *ioaddr = tp->mmio_addr;
5060 return RTL_R8(ChipCmd) & CmdReset;
5063 static void rtl_hw_reset(struct rtl8169_private *tp)
5065 void __iomem *ioaddr = tp->mmio_addr;
5067 RTL_W8(ChipCmd, CmdReset);
5069 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
5071 netdev_reset_queue(tp->dev);
5074 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
5076 struct rtl_fw *rtl_fw;
5080 name = rtl_lookup_firmware_name(tp);
5082 goto out_no_firmware;
5084 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
5088 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
5092 rc = rtl_check_firmware(tp, rtl_fw);
5094 goto err_release_firmware;
5096 tp->rtl_fw = rtl_fw;
5100 err_release_firmware:
5101 release_firmware(rtl_fw->fw);
5105 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
5112 static void rtl_request_firmware(struct rtl8169_private *tp)
5114 if (IS_ERR(tp->rtl_fw))
5115 rtl_request_uncached_firmware(tp);
5118 static void rtl_rx_close(struct rtl8169_private *tp)
5120 void __iomem *ioaddr = tp->mmio_addr;
5122 RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
5125 DECLARE_RTL_COND(rtl_npq_cond)
5127 void __iomem *ioaddr = tp->mmio_addr;
5129 return RTL_R8(TxPoll) & NPQ;
5132 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
5134 void __iomem *ioaddr = tp->mmio_addr;
5136 return RTL_R32(TxConfig) & TXCFG_EMPTY;
5139 static void rtl8169_hw_reset(struct rtl8169_private *tp)
5141 void __iomem *ioaddr = tp->mmio_addr;
5143 /* Disable interrupts */
5144 rtl8169_irq_mask_and_ack(tp);
5148 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
5149 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
5150 tp->mac_version == RTL_GIGA_MAC_VER_31) {
5151 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
5152 } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
5153 tp->mac_version == RTL_GIGA_MAC_VER_35 ||
5154 tp->mac_version == RTL_GIGA_MAC_VER_36 ||
5155 tp->mac_version == RTL_GIGA_MAC_VER_37 ||
5156 tp->mac_version == RTL_GIGA_MAC_VER_38 ||
5157 tp->mac_version == RTL_GIGA_MAC_VER_40 ||
5158 tp->mac_version == RTL_GIGA_MAC_VER_41 ||
5159 tp->mac_version == RTL_GIGA_MAC_VER_42 ||
5160 tp->mac_version == RTL_GIGA_MAC_VER_43 ||
5161 tp->mac_version == RTL_GIGA_MAC_VER_44 ||
5162 tp->mac_version == RTL_GIGA_MAC_VER_45 ||
5163 tp->mac_version == RTL_GIGA_MAC_VER_46 ||
5164 tp->mac_version == RTL_GIGA_MAC_VER_47 ||
5165 tp->mac_version == RTL_GIGA_MAC_VER_48 ||
5166 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
5167 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
5168 tp->mac_version == RTL_GIGA_MAC_VER_51) {
5169 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
5170 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
5172 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
5179 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
5181 void __iomem *ioaddr = tp->mmio_addr;
5183 /* Set DMA burst size and Interframe Gap Time */
5184 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
5185 (InterFrameGap << TxInterFrameGapShift));
5188 static void rtl_hw_start(struct net_device *dev)
5190 struct rtl8169_private *tp = netdev_priv(dev);
5194 rtl_irq_enable_all(tp);
5197 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
5198 void __iomem *ioaddr)
5201 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
5202 * register to be written before TxDescAddrLow to work.
5203 * Switching from MMIO to I/O access fixes the issue as well.
5205 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
5206 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
5207 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
5208 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
5211 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
5215 cmd = RTL_R16(CPlusCmd);
5216 RTL_W16(CPlusCmd, cmd);
5220 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
5222 /* Low hurts. Let's disable the filtering. */
5223 RTL_W16(RxMaxSize, rx_buf_sz + 1);
5226 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
5228 static const struct rtl_cfg2_info {
5233 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
5234 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
5235 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
5236 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
5238 const struct rtl_cfg2_info *p = cfg2_info;
5242 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
5243 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
5244 if ((p->mac_version == mac_version) && (p->clk == clk)) {
5245 RTL_W32(0x7c, p->val);
5251 static void rtl_set_rx_mode(struct net_device *dev)
5253 struct rtl8169_private *tp = netdev_priv(dev);
5254 void __iomem *ioaddr = tp->mmio_addr;
5255 u32 mc_filter[2]; /* Multicast hash filter */
5259 if (dev->flags & IFF_PROMISC) {
5260 /* Unconditionally log net taps. */
5261 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
5263 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5265 mc_filter[1] = mc_filter[0] = 0xffffffff;
5266 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
5267 (dev->flags & IFF_ALLMULTI)) {
5268 /* Too many to filter perfectly -- accept all multicasts. */
5269 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5270 mc_filter[1] = mc_filter[0] = 0xffffffff;
5272 struct netdev_hw_addr *ha;
5274 rx_mode = AcceptBroadcast | AcceptMyPhys;
5275 mc_filter[1] = mc_filter[0] = 0;
5276 netdev_for_each_mc_addr(ha, dev) {
5277 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
5278 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5279 rx_mode |= AcceptMulticast;
5283 if (dev->features & NETIF_F_RXALL)
5284 rx_mode |= (AcceptErr | AcceptRunt);
5286 tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
5288 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
5289 u32 data = mc_filter[0];
5291 mc_filter[0] = swab32(mc_filter[1]);
5292 mc_filter[1] = swab32(data);
5295 if (tp->mac_version == RTL_GIGA_MAC_VER_35)
5296 mc_filter[1] = mc_filter[0] = 0xffffffff;
5298 RTL_W32(MAR0 + 4, mc_filter[1]);
5299 RTL_W32(MAR0 + 0, mc_filter[0]);
5301 RTL_W32(RxConfig, tmp);
5304 static void rtl_hw_start_8169(struct net_device *dev)
5306 struct rtl8169_private *tp = netdev_priv(dev);
5307 void __iomem *ioaddr = tp->mmio_addr;
5308 struct pci_dev *pdev = tp->pci_dev;
5310 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
5311 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
5312 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
5315 RTL_W8(Cfg9346, Cfg9346_Unlock);
5316 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
5317 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5318 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
5319 tp->mac_version == RTL_GIGA_MAC_VER_04)
5320 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5324 RTL_W8(EarlyTxThres, NoEarlyTx);
5326 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
5328 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
5329 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5330 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
5331 tp->mac_version == RTL_GIGA_MAC_VER_04)
5332 rtl_set_rx_tx_config_registers(tp);
5334 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
5336 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
5337 tp->mac_version == RTL_GIGA_MAC_VER_03) {
5338 dprintk("Set MAC Reg C+CR Offset 0xe0. "
5339 "Bit-3 and bit-14 MUST be 1\n");
5340 tp->cp_cmd |= (1 << 14);
5343 RTL_W16(CPlusCmd, tp->cp_cmd);
5345 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
5348 * Undocumented corner. Supposedly:
5349 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
5351 RTL_W16(IntrMitigate, 0x0000);
5353 rtl_set_rx_tx_desc_registers(tp, ioaddr);
5355 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
5356 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
5357 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
5358 tp->mac_version != RTL_GIGA_MAC_VER_04) {
5359 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
5360 rtl_set_rx_tx_config_registers(tp);
5363 RTL_W8(Cfg9346, Cfg9346_Lock);
5365 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
5368 RTL_W32(RxMissed, 0);
5370 rtl_set_rx_mode(dev);
5372 /* no early-rx interrupts */
5373 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
5376 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
5378 if (tp->csi_ops.write)
5379 tp->csi_ops.write(tp, addr, value);
5382 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
5384 return tp->csi_ops.read ? tp->csi_ops.read(tp, addr) : ~0;
5387 static void rtl_csi_access_enable(struct rtl8169_private *tp, u32 bits)
5391 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
5392 rtl_csi_write(tp, 0x070c, csi | bits);
5395 static void rtl_csi_access_enable_1(struct rtl8169_private *tp)
5397 rtl_csi_access_enable(tp, 0x17000000);
5400 static void rtl_csi_access_enable_2(struct rtl8169_private *tp)
5402 rtl_csi_access_enable(tp, 0x27000000);
5405 DECLARE_RTL_COND(rtl_csiar_cond)
5407 void __iomem *ioaddr = tp->mmio_addr;
5409 return RTL_R32(CSIAR) & CSIAR_FLAG;
5412 static void r8169_csi_write(struct rtl8169_private *tp, int addr, int value)
5414 void __iomem *ioaddr = tp->mmio_addr;
5416 RTL_W32(CSIDR, value);
5417 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5418 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5420 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5423 static u32 r8169_csi_read(struct rtl8169_private *tp, int addr)
5425 void __iomem *ioaddr = tp->mmio_addr;
5427 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
5428 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5430 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5431 RTL_R32(CSIDR) : ~0;
5434 static void r8402_csi_write(struct rtl8169_private *tp, int addr, int value)
5436 void __iomem *ioaddr = tp->mmio_addr;
5438 RTL_W32(CSIDR, value);
5439 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5440 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5443 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5446 static u32 r8402_csi_read(struct rtl8169_private *tp, int addr)
5448 void __iomem *ioaddr = tp->mmio_addr;
5450 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC |
5451 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5453 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5454 RTL_R32(CSIDR) : ~0;
5457 static void r8411_csi_write(struct rtl8169_private *tp, int addr, int value)
5459 void __iomem *ioaddr = tp->mmio_addr;
5461 RTL_W32(CSIDR, value);
5462 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
5463 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT |
5466 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
5469 static u32 r8411_csi_read(struct rtl8169_private *tp, int addr)
5471 void __iomem *ioaddr = tp->mmio_addr;
5473 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | CSIAR_FUNC_NIC2 |
5474 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
5476 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
5477 RTL_R32(CSIDR) : ~0;
5480 static void rtl_init_csi_ops(struct rtl8169_private *tp)
5482 struct csi_ops *ops = &tp->csi_ops;
5484 switch (tp->mac_version) {
5485 case RTL_GIGA_MAC_VER_01:
5486 case RTL_GIGA_MAC_VER_02:
5487 case RTL_GIGA_MAC_VER_03:
5488 case RTL_GIGA_MAC_VER_04:
5489 case RTL_GIGA_MAC_VER_05:
5490 case RTL_GIGA_MAC_VER_06:
5491 case RTL_GIGA_MAC_VER_10:
5492 case RTL_GIGA_MAC_VER_11:
5493 case RTL_GIGA_MAC_VER_12:
5494 case RTL_GIGA_MAC_VER_13:
5495 case RTL_GIGA_MAC_VER_14:
5496 case RTL_GIGA_MAC_VER_15:
5497 case RTL_GIGA_MAC_VER_16:
5498 case RTL_GIGA_MAC_VER_17:
5503 case RTL_GIGA_MAC_VER_37:
5504 case RTL_GIGA_MAC_VER_38:
5505 ops->write = r8402_csi_write;
5506 ops->read = r8402_csi_read;
5509 case RTL_GIGA_MAC_VER_44:
5510 ops->write = r8411_csi_write;
5511 ops->read = r8411_csi_read;
5515 ops->write = r8169_csi_write;
5516 ops->read = r8169_csi_read;
5522 unsigned int offset;
5527 static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
5533 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
5534 rtl_ephy_write(tp, e->offset, w);
5539 static void rtl_disable_clock_request(struct pci_dev *pdev)
5541 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
5542 PCI_EXP_LNKCTL_CLKREQ_EN);
5545 static void rtl_enable_clock_request(struct pci_dev *pdev)
5547 pcie_capability_set_word(pdev, PCI_EXP_LNKCTL,
5548 PCI_EXP_LNKCTL_CLKREQ_EN);
5551 static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
5553 void __iomem *ioaddr = tp->mmio_addr;
5556 data = RTL_R8(Config3);
5561 data &= ~Rdy_to_L23;
5563 RTL_W8(Config3, data);
5566 #define R8168_CPCMD_QUIRK_MASK (\
5577 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
5579 void __iomem *ioaddr = tp->mmio_addr;
5580 struct pci_dev *pdev = tp->pci_dev;
5582 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5584 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5586 if (tp->dev->mtu <= ETH_DATA_LEN) {
5587 rtl_tx_performance_tweak(pdev, (0x5 << MAX_READ_REQUEST_SHIFT) |
5588 PCI_EXP_DEVCTL_NOSNOOP_EN);
5592 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
5594 void __iomem *ioaddr = tp->mmio_addr;
5596 rtl_hw_start_8168bb(tp);
5598 RTL_W8(MaxTxPacketSize, TxPacketMax);
5600 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
5603 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
5605 void __iomem *ioaddr = tp->mmio_addr;
5606 struct pci_dev *pdev = tp->pci_dev;
5608 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
5610 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5612 if (tp->dev->mtu <= ETH_DATA_LEN)
5613 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5615 rtl_disable_clock_request(pdev);
5617 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5620 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
5622 static const struct ephy_info e_info_8168cp[] = {
5623 { 0x01, 0, 0x0001 },
5624 { 0x02, 0x0800, 0x1000 },
5625 { 0x03, 0, 0x0042 },
5626 { 0x06, 0x0080, 0x0000 },
5630 rtl_csi_access_enable_2(tp);
5632 rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
5634 __rtl_hw_start_8168cp(tp);
5637 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
5639 void __iomem *ioaddr = tp->mmio_addr;
5640 struct pci_dev *pdev = tp->pci_dev;
5642 rtl_csi_access_enable_2(tp);
5644 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5646 if (tp->dev->mtu <= ETH_DATA_LEN)
5647 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5649 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5652 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
5654 void __iomem *ioaddr = tp->mmio_addr;
5655 struct pci_dev *pdev = tp->pci_dev;
5657 rtl_csi_access_enable_2(tp);
5659 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
5662 RTL_W8(DBG_REG, 0x20);
5664 RTL_W8(MaxTxPacketSize, TxPacketMax);
5666 if (tp->dev->mtu <= ETH_DATA_LEN)
5667 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5669 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5672 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
5674 void __iomem *ioaddr = tp->mmio_addr;
5675 static const struct ephy_info e_info_8168c_1[] = {
5676 { 0x02, 0x0800, 0x1000 },
5677 { 0x03, 0, 0x0002 },
5678 { 0x06, 0x0080, 0x0000 }
5681 rtl_csi_access_enable_2(tp);
5683 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
5685 rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
5687 __rtl_hw_start_8168cp(tp);
5690 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
5692 static const struct ephy_info e_info_8168c_2[] = {
5693 { 0x01, 0, 0x0001 },
5694 { 0x03, 0x0400, 0x0220 }
5697 rtl_csi_access_enable_2(tp);
5699 rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
5701 __rtl_hw_start_8168cp(tp);
5704 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
5706 rtl_hw_start_8168c_2(tp);
5709 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
5711 rtl_csi_access_enable_2(tp);
5713 __rtl_hw_start_8168cp(tp);
5716 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
5718 void __iomem *ioaddr = tp->mmio_addr;
5719 struct pci_dev *pdev = tp->pci_dev;
5721 rtl_csi_access_enable_2(tp);
5723 rtl_disable_clock_request(pdev);
5725 RTL_W8(MaxTxPacketSize, TxPacketMax);
5727 if (tp->dev->mtu <= ETH_DATA_LEN)
5728 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5730 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
5733 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
5735 void __iomem *ioaddr = tp->mmio_addr;
5736 struct pci_dev *pdev = tp->pci_dev;
5738 rtl_csi_access_enable_1(tp);
5740 if (tp->dev->mtu <= ETH_DATA_LEN)
5741 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5743 RTL_W8(MaxTxPacketSize, TxPacketMax);
5745 rtl_disable_clock_request(pdev);
5748 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
5750 void __iomem *ioaddr = tp->mmio_addr;
5751 struct pci_dev *pdev = tp->pci_dev;
5752 static const struct ephy_info e_info_8168d_4[] = {
5754 { 0x19, 0x20, 0x50 },
5759 rtl_csi_access_enable_1(tp);
5761 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5763 RTL_W8(MaxTxPacketSize, TxPacketMax);
5765 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
5766 const struct ephy_info *e = e_info_8168d_4 + i;
5769 w = rtl_ephy_read(tp, e->offset);
5770 rtl_ephy_write(tp, 0x03, (w & e->mask) | e->bits);
5773 rtl_enable_clock_request(pdev);
5776 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
5778 void __iomem *ioaddr = tp->mmio_addr;
5779 struct pci_dev *pdev = tp->pci_dev;
5780 static const struct ephy_info e_info_8168e_1[] = {
5781 { 0x00, 0x0200, 0x0100 },
5782 { 0x00, 0x0000, 0x0004 },
5783 { 0x06, 0x0002, 0x0001 },
5784 { 0x06, 0x0000, 0x0030 },
5785 { 0x07, 0x0000, 0x2000 },
5786 { 0x00, 0x0000, 0x0020 },
5787 { 0x03, 0x5800, 0x2000 },
5788 { 0x03, 0x0000, 0x0001 },
5789 { 0x01, 0x0800, 0x1000 },
5790 { 0x07, 0x0000, 0x4000 },
5791 { 0x1e, 0x0000, 0x2000 },
5792 { 0x19, 0xffff, 0xfe6c },
5793 { 0x0a, 0x0000, 0x0040 }
5796 rtl_csi_access_enable_2(tp);
5798 rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
5800 if (tp->dev->mtu <= ETH_DATA_LEN)
5801 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5803 RTL_W8(MaxTxPacketSize, TxPacketMax);
5805 rtl_disable_clock_request(pdev);
5807 /* Reset tx FIFO pointer */
5808 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
5809 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
5811 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5814 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
5816 void __iomem *ioaddr = tp->mmio_addr;
5817 struct pci_dev *pdev = tp->pci_dev;
5818 static const struct ephy_info e_info_8168e_2[] = {
5819 { 0x09, 0x0000, 0x0080 },
5820 { 0x19, 0x0000, 0x0224 }
5823 rtl_csi_access_enable_1(tp);
5825 rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
5827 if (tp->dev->mtu <= ETH_DATA_LEN)
5828 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5830 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5831 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5832 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5833 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5834 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5835 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
5836 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5837 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5839 RTL_W8(MaxTxPacketSize, EarlySize);
5841 rtl_disable_clock_request(pdev);
5843 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5844 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5846 /* Adjust EEE LED frequency */
5847 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5849 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5850 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5851 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5854 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
5856 void __iomem *ioaddr = tp->mmio_addr;
5857 struct pci_dev *pdev = tp->pci_dev;
5859 rtl_csi_access_enable_2(tp);
5861 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5863 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5864 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5865 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5866 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5867 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5868 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5869 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5870 rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5871 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5872 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
5874 RTL_W8(MaxTxPacketSize, EarlySize);
5876 rtl_disable_clock_request(pdev);
5878 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5879 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
5880 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5881 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
5882 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
5885 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5887 void __iomem *ioaddr = tp->mmio_addr;
5888 static const struct ephy_info e_info_8168f_1[] = {
5889 { 0x06, 0x00c0, 0x0020 },
5890 { 0x08, 0x0001, 0x0002 },
5891 { 0x09, 0x0000, 0x0080 },
5892 { 0x19, 0x0000, 0x0224 }
5895 rtl_hw_start_8168f(tp);
5897 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5899 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5901 /* Adjust EEE LED frequency */
5902 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5905 static void rtl_hw_start_8411(struct rtl8169_private *tp)
5907 static const struct ephy_info e_info_8168f_1[] = {
5908 { 0x06, 0x00c0, 0x0020 },
5909 { 0x0f, 0xffff, 0x5200 },
5910 { 0x1e, 0x0000, 0x4000 },
5911 { 0x19, 0x0000, 0x0224 }
5914 rtl_hw_start_8168f(tp);
5915 rtl_pcie_state_l2l3_enable(tp, false);
5917 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5919 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
5922 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5924 void __iomem *ioaddr = tp->mmio_addr;
5925 struct pci_dev *pdev = tp->pci_dev;
5927 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
5929 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5930 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5931 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5932 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5934 rtl_csi_access_enable_1(tp);
5936 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
5938 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5939 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5940 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
5942 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
5943 RTL_W8(MaxTxPacketSize, EarlySize);
5945 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5946 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5948 /* Adjust EEE LED frequency */
5949 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
5951 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5952 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
5954 rtl_pcie_state_l2l3_enable(tp, false);
5957 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
5959 void __iomem *ioaddr = tp->mmio_addr;
5960 static const struct ephy_info e_info_8168g_2[] = {
5961 { 0x00, 0x0000, 0x0008 },
5962 { 0x0c, 0x3df0, 0x0200 },
5963 { 0x19, 0xffff, 0xfc00 },
5964 { 0x1e, 0xffff, 0x20eb }
5967 rtl_hw_start_8168g_1(tp);
5969 /* disable aspm and clock request before access ephy */
5970 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
5971 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
5972 rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
5975 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
5977 void __iomem *ioaddr = tp->mmio_addr;
5978 static const struct ephy_info e_info_8411_2[] = {
5979 { 0x00, 0x0000, 0x0008 },
5980 { 0x0c, 0x3df0, 0x0200 },
5981 { 0x0f, 0xffff, 0x5200 },
5982 { 0x19, 0x0020, 0x0000 },
5983 { 0x1e, 0x0000, 0x2000 }
5986 rtl_hw_start_8168g_1(tp);
5988 /* disable aspm and clock request before access ephy */
5989 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
5990 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
5991 rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
5994 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
5996 void __iomem *ioaddr = tp->mmio_addr;
5997 struct pci_dev *pdev = tp->pci_dev;
6000 static const struct ephy_info e_info_8168h_1[] = {
6001 { 0x1e, 0x0800, 0x0001 },
6002 { 0x1d, 0x0000, 0x0800 },
6003 { 0x05, 0xffff, 0x2089 },
6004 { 0x06, 0xffff, 0x5881 },
6005 { 0x04, 0xffff, 0x154a },
6006 { 0x01, 0xffff, 0x068b }
6009 /* disable aspm and clock request before access ephy */
6010 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6011 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6012 rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
6014 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6016 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
6017 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
6018 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
6019 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6021 rtl_csi_access_enable_1(tp);
6023 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6025 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6026 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6028 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
6030 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
6032 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
6034 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
6035 RTL_W8(MaxTxPacketSize, EarlySize);
6037 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6038 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6040 /* Adjust EEE LED frequency */
6041 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6043 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6044 RTL_W8(DLLPR, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
6046 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN);
6048 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
6050 rtl_pcie_state_l2l3_enable(tp, false);
6052 rtl_writephy(tp, 0x1f, 0x0c42);
6053 rg_saw_cnt = rtl_readphy(tp, 0x13);
6054 rtl_writephy(tp, 0x1f, 0x0000);
6055 if (rg_saw_cnt > 0) {
6058 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
6059 sw_cnt_1ms_ini &= 0x0fff;
6060 data = r8168_mac_ocp_read(tp, 0xd412);
6062 data |= sw_cnt_1ms_ini;
6063 r8168_mac_ocp_write(tp, 0xd412, data);
6066 data = r8168_mac_ocp_read(tp, 0xe056);
6069 r8168_mac_ocp_write(tp, 0xe056, data);
6071 data = r8168_mac_ocp_read(tp, 0xe052);
6074 r8168_mac_ocp_write(tp, 0xe052, data);
6076 data = r8168_mac_ocp_read(tp, 0xe0d6);
6079 r8168_mac_ocp_write(tp, 0xe0d6, data);
6081 data = r8168_mac_ocp_read(tp, 0xd420);
6084 r8168_mac_ocp_write(tp, 0xd420, data);
6086 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
6087 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
6088 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
6089 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
6092 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
6094 void __iomem *ioaddr = tp->mmio_addr;
6095 struct pci_dev *pdev = tp->pci_dev;
6097 rtl8168ep_stop_cmac(tp);
6099 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6101 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
6102 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f, ERIAR_EXGMAC);
6103 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f, ERIAR_EXGMAC);
6104 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
6106 rtl_csi_access_enable_1(tp);
6108 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6110 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6111 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6113 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f80, 0x00, ERIAR_EXGMAC);
6115 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
6117 RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
6118 RTL_W8(MaxTxPacketSize, EarlySize);
6120 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6121 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6123 /* Adjust EEE LED frequency */
6124 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
6126 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
6128 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN);
6130 rtl_pcie_state_l2l3_enable(tp, false);
6133 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
6135 void __iomem *ioaddr = tp->mmio_addr;
6136 static const struct ephy_info e_info_8168ep_1[] = {
6137 { 0x00, 0xffff, 0x10ab },
6138 { 0x06, 0xffff, 0xf030 },
6139 { 0x08, 0xffff, 0x2006 },
6140 { 0x0d, 0xffff, 0x1666 },
6141 { 0x0c, 0x3ff0, 0x0000 }
6144 /* disable aspm and clock request before access ephy */
6145 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6146 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6147 rtl_ephy_init(tp, e_info_8168ep_1, ARRAY_SIZE(e_info_8168ep_1));
6149 rtl_hw_start_8168ep(tp);
6152 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
6154 void __iomem *ioaddr = tp->mmio_addr;
6155 static const struct ephy_info e_info_8168ep_2[] = {
6156 { 0x00, 0xffff, 0x10a3 },
6157 { 0x19, 0xffff, 0xfc00 },
6158 { 0x1e, 0xffff, 0x20ea }
6161 /* disable aspm and clock request before access ephy */
6162 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6163 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6164 rtl_ephy_init(tp, e_info_8168ep_2, ARRAY_SIZE(e_info_8168ep_2));
6166 rtl_hw_start_8168ep(tp);
6168 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6169 RTL_W8(DLLPR, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
6172 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
6174 void __iomem *ioaddr = tp->mmio_addr;
6176 static const struct ephy_info e_info_8168ep_3[] = {
6177 { 0x00, 0xffff, 0x10a3 },
6178 { 0x19, 0xffff, 0x7c00 },
6179 { 0x1e, 0xffff, 0x20eb },
6180 { 0x0d, 0xffff, 0x1666 }
6183 /* disable aspm and clock request before access ephy */
6184 RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
6185 RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
6186 rtl_ephy_init(tp, e_info_8168ep_3, ARRAY_SIZE(e_info_8168ep_3));
6188 rtl_hw_start_8168ep(tp);
6190 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6191 RTL_W8(DLLPR, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
6193 data = r8168_mac_ocp_read(tp, 0xd3e2);
6196 r8168_mac_ocp_write(tp, 0xd3e2, data);
6198 data = r8168_mac_ocp_read(tp, 0xd3e4);
6200 r8168_mac_ocp_write(tp, 0xd3e4, data);
6202 data = r8168_mac_ocp_read(tp, 0xe860);
6204 r8168_mac_ocp_write(tp, 0xe860, data);
6207 static void rtl_hw_start_8168(struct net_device *dev)
6209 struct rtl8169_private *tp = netdev_priv(dev);
6210 void __iomem *ioaddr = tp->mmio_addr;
6212 RTL_W8(Cfg9346, Cfg9346_Unlock);
6214 RTL_W8(MaxTxPacketSize, TxPacketMax);
6216 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
6218 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
6220 RTL_W16(CPlusCmd, tp->cp_cmd);
6222 RTL_W16(IntrMitigate, 0x5151);
6224 /* Work around for RxFIFO overflow. */
6225 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
6226 tp->event_slow |= RxFIFOOver | PCSTimeout;
6227 tp->event_slow &= ~RxOverflow;
6230 rtl_set_rx_tx_desc_registers(tp, ioaddr);
6232 rtl_set_rx_tx_config_registers(tp);
6236 switch (tp->mac_version) {
6237 case RTL_GIGA_MAC_VER_11:
6238 rtl_hw_start_8168bb(tp);
6241 case RTL_GIGA_MAC_VER_12:
6242 case RTL_GIGA_MAC_VER_17:
6243 rtl_hw_start_8168bef(tp);
6246 case RTL_GIGA_MAC_VER_18:
6247 rtl_hw_start_8168cp_1(tp);
6250 case RTL_GIGA_MAC_VER_19:
6251 rtl_hw_start_8168c_1(tp);
6254 case RTL_GIGA_MAC_VER_20:
6255 rtl_hw_start_8168c_2(tp);
6258 case RTL_GIGA_MAC_VER_21:
6259 rtl_hw_start_8168c_3(tp);
6262 case RTL_GIGA_MAC_VER_22:
6263 rtl_hw_start_8168c_4(tp);
6266 case RTL_GIGA_MAC_VER_23:
6267 rtl_hw_start_8168cp_2(tp);
6270 case RTL_GIGA_MAC_VER_24:
6271 rtl_hw_start_8168cp_3(tp);
6274 case RTL_GIGA_MAC_VER_25:
6275 case RTL_GIGA_MAC_VER_26:
6276 case RTL_GIGA_MAC_VER_27:
6277 rtl_hw_start_8168d(tp);
6280 case RTL_GIGA_MAC_VER_28:
6281 rtl_hw_start_8168d_4(tp);
6284 case RTL_GIGA_MAC_VER_31:
6285 rtl_hw_start_8168dp(tp);
6288 case RTL_GIGA_MAC_VER_32:
6289 case RTL_GIGA_MAC_VER_33:
6290 rtl_hw_start_8168e_1(tp);
6292 case RTL_GIGA_MAC_VER_34:
6293 rtl_hw_start_8168e_2(tp);
6296 case RTL_GIGA_MAC_VER_35:
6297 case RTL_GIGA_MAC_VER_36:
6298 rtl_hw_start_8168f_1(tp);
6301 case RTL_GIGA_MAC_VER_38:
6302 rtl_hw_start_8411(tp);
6305 case RTL_GIGA_MAC_VER_40:
6306 case RTL_GIGA_MAC_VER_41:
6307 rtl_hw_start_8168g_1(tp);
6309 case RTL_GIGA_MAC_VER_42:
6310 rtl_hw_start_8168g_2(tp);
6313 case RTL_GIGA_MAC_VER_44:
6314 rtl_hw_start_8411_2(tp);
6317 case RTL_GIGA_MAC_VER_45:
6318 case RTL_GIGA_MAC_VER_46:
6319 rtl_hw_start_8168h_1(tp);
6322 case RTL_GIGA_MAC_VER_49:
6323 rtl_hw_start_8168ep_1(tp);
6326 case RTL_GIGA_MAC_VER_50:
6327 rtl_hw_start_8168ep_2(tp);
6330 case RTL_GIGA_MAC_VER_51:
6331 rtl_hw_start_8168ep_3(tp);
6335 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
6336 dev->name, tp->mac_version);
6340 RTL_W8(Cfg9346, Cfg9346_Lock);
6342 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
6344 rtl_set_rx_mode(dev);
6346 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6349 #define R810X_CPCMD_QUIRK_MASK (\
6360 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
6362 void __iomem *ioaddr = tp->mmio_addr;
6363 struct pci_dev *pdev = tp->pci_dev;
6364 static const struct ephy_info e_info_8102e_1[] = {
6365 { 0x01, 0, 0x6e65 },
6366 { 0x02, 0, 0x091f },
6367 { 0x03, 0, 0xc2f9 },
6368 { 0x06, 0, 0xafb5 },
6369 { 0x07, 0, 0x0e00 },
6370 { 0x19, 0, 0xec80 },
6371 { 0x01, 0, 0x2e65 },
6376 rtl_csi_access_enable_2(tp);
6378 RTL_W8(DBG_REG, FIX_NAK_1);
6380 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6383 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
6384 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
6386 cfg1 = RTL_R8(Config1);
6387 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
6388 RTL_W8(Config1, cfg1 & ~LEDS0);
6390 rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
6393 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
6395 void __iomem *ioaddr = tp->mmio_addr;
6396 struct pci_dev *pdev = tp->pci_dev;
6398 rtl_csi_access_enable_2(tp);
6400 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
6402 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
6403 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
6406 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
6408 rtl_hw_start_8102e_2(tp);
6410 rtl_ephy_write(tp, 0x03, 0xc2f9);
6413 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
6415 void __iomem *ioaddr = tp->mmio_addr;
6416 static const struct ephy_info e_info_8105e_1[] = {
6417 { 0x07, 0, 0x4000 },
6418 { 0x19, 0, 0x0200 },
6419 { 0x19, 0, 0x0020 },
6420 { 0x1e, 0, 0x2000 },
6421 { 0x03, 0, 0x0001 },
6422 { 0x19, 0, 0x0100 },
6423 { 0x19, 0, 0x0004 },
6427 /* Force LAN exit from ASPM if Rx/Tx are not idle */
6428 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6430 /* Disable Early Tally Counter */
6431 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
6433 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
6434 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
6436 rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
6438 rtl_pcie_state_l2l3_enable(tp, false);
6441 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
6443 rtl_hw_start_8105e_1(tp);
6444 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
6447 static void rtl_hw_start_8402(struct rtl8169_private *tp)
6449 void __iomem *ioaddr = tp->mmio_addr;
6450 static const struct ephy_info e_info_8402[] = {
6451 { 0x19, 0xffff, 0xff64 },
6455 rtl_csi_access_enable_2(tp);
6457 /* Force LAN exit from ASPM if Rx/Tx are not idle */
6458 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6460 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
6461 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
6463 rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
6465 rtl_tx_performance_tweak(tp->pci_dev, 0x5 << MAX_READ_REQUEST_SHIFT);
6467 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
6468 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
6469 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
6470 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
6471 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6472 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
6473 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
6475 rtl_pcie_state_l2l3_enable(tp, false);
6478 static void rtl_hw_start_8106(struct rtl8169_private *tp)
6480 void __iomem *ioaddr = tp->mmio_addr;
6482 /* Force LAN exit from ASPM if Rx/Tx are not idle */
6483 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
6485 RTL_W32(MISC, (RTL_R32(MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
6486 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
6487 RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
6489 rtl_pcie_state_l2l3_enable(tp, false);
6492 static void rtl_hw_start_8101(struct net_device *dev)
6494 struct rtl8169_private *tp = netdev_priv(dev);
6495 void __iomem *ioaddr = tp->mmio_addr;
6496 struct pci_dev *pdev = tp->pci_dev;
6498 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
6499 tp->event_slow &= ~RxFIFOOver;
6501 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
6502 tp->mac_version == RTL_GIGA_MAC_VER_16)
6503 pcie_capability_set_word(pdev, PCI_EXP_DEVCTL,
6504 PCI_EXP_DEVCTL_NOSNOOP_EN);
6506 RTL_W8(Cfg9346, Cfg9346_Unlock);
6508 RTL_W8(MaxTxPacketSize, TxPacketMax);
6510 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
6512 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
6513 RTL_W16(CPlusCmd, tp->cp_cmd);
6515 rtl_set_rx_tx_desc_registers(tp, ioaddr);
6517 rtl_set_rx_tx_config_registers(tp);
6519 switch (tp->mac_version) {
6520 case RTL_GIGA_MAC_VER_07:
6521 rtl_hw_start_8102e_1(tp);
6524 case RTL_GIGA_MAC_VER_08:
6525 rtl_hw_start_8102e_3(tp);
6528 case RTL_GIGA_MAC_VER_09:
6529 rtl_hw_start_8102e_2(tp);
6532 case RTL_GIGA_MAC_VER_29:
6533 rtl_hw_start_8105e_1(tp);
6535 case RTL_GIGA_MAC_VER_30:
6536 rtl_hw_start_8105e_2(tp);
6539 case RTL_GIGA_MAC_VER_37:
6540 rtl_hw_start_8402(tp);
6543 case RTL_GIGA_MAC_VER_39:
6544 rtl_hw_start_8106(tp);
6546 case RTL_GIGA_MAC_VER_43:
6547 rtl_hw_start_8168g_2(tp);
6549 case RTL_GIGA_MAC_VER_47:
6550 case RTL_GIGA_MAC_VER_48:
6551 rtl_hw_start_8168h_1(tp);
6555 RTL_W8(Cfg9346, Cfg9346_Lock);
6557 RTL_W16(IntrMitigate, 0x0000);
6559 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
6561 rtl_set_rx_mode(dev);
6565 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6568 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
6570 struct rtl8169_private *tp = netdev_priv(dev);
6572 if (new_mtu < ETH_ZLEN ||
6573 new_mtu > rtl_chip_infos[tp->mac_version].jumbo_max)
6576 if (new_mtu > ETH_DATA_LEN)
6577 rtl_hw_jumbo_enable(tp);
6579 rtl_hw_jumbo_disable(tp);
6582 netdev_update_features(dev);
6587 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
6589 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
6590 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
6593 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
6594 void **data_buff, struct RxDesc *desc)
6596 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
6601 rtl8169_make_unusable_by_asic(desc);
6604 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
6606 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
6608 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
6611 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
6614 desc->addr = cpu_to_le64(mapping);
6616 rtl8169_mark_to_asic(desc, rx_buf_sz);
6619 static inline void *rtl8169_align(void *data)
6621 return (void *)ALIGN((long)data, 16);
6624 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
6625 struct RxDesc *desc)
6629 struct device *d = &tp->pci_dev->dev;
6630 struct net_device *dev = tp->dev;
6631 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
6633 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
6637 if (rtl8169_align(data) != data) {
6639 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
6644 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
6646 if (unlikely(dma_mapping_error(d, mapping))) {
6647 if (net_ratelimit())
6648 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
6652 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6660 static void rtl8169_rx_clear(struct rtl8169_private *tp)
6664 for (i = 0; i < NUM_RX_DESC; i++) {
6665 if (tp->Rx_databuff[i]) {
6666 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
6667 tp->RxDescArray + i);
6672 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
6674 desc->opts1 |= cpu_to_le32(RingEnd);
6677 static int rtl8169_rx_fill(struct rtl8169_private *tp)
6681 for (i = 0; i < NUM_RX_DESC; i++) {
6684 if (tp->Rx_databuff[i])
6687 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6689 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
6692 tp->Rx_databuff[i] = data;
6695 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
6699 rtl8169_rx_clear(tp);
6703 static int rtl8169_init_ring(struct net_device *dev)
6705 struct rtl8169_private *tp = netdev_priv(dev);
6707 rtl8169_init_ring_indexes(tp);
6709 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6710 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
6712 return rtl8169_rx_fill(tp);
6715 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
6716 struct TxDesc *desc)
6718 unsigned int len = tx_skb->len;
6720 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
6728 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
6733 for (i = 0; i < n; i++) {
6734 unsigned int entry = (start + i) % NUM_TX_DESC;
6735 struct ring_info *tx_skb = tp->tx_skb + entry;
6736 unsigned int len = tx_skb->len;
6739 struct sk_buff *skb = tx_skb->skb;
6741 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
6742 tp->TxDescArray + entry);
6744 tp->dev->stats.tx_dropped++;
6745 dev_kfree_skb_any(skb);
6752 static void rtl8169_tx_clear(struct rtl8169_private *tp)
6754 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
6755 tp->cur_tx = tp->dirty_tx = 0;
6758 static void rtl_reset_work(struct rtl8169_private *tp)
6760 struct net_device *dev = tp->dev;
6763 napi_disable(&tp->napi);
6764 netif_stop_queue(dev);
6765 synchronize_sched();
6767 rtl8169_hw_reset(tp);
6769 for (i = 0; i < NUM_RX_DESC; i++)
6770 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
6772 rtl8169_tx_clear(tp);
6773 rtl8169_init_ring_indexes(tp);
6775 napi_enable(&tp->napi);
6777 netif_wake_queue(dev);
6778 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
6781 static void rtl8169_tx_timeout(struct net_device *dev)
6783 struct rtl8169_private *tp = netdev_priv(dev);
6785 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6788 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
6791 struct skb_shared_info *info = skb_shinfo(skb);
6792 unsigned int cur_frag, entry;
6793 struct TxDesc *uninitialized_var(txd);
6794 struct device *d = &tp->pci_dev->dev;
6797 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
6798 const skb_frag_t *frag = info->frags + cur_frag;
6803 entry = (entry + 1) % NUM_TX_DESC;
6805 txd = tp->TxDescArray + entry;
6806 len = skb_frag_size(frag);
6807 addr = skb_frag_address(frag);
6808 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
6809 if (unlikely(dma_mapping_error(d, mapping))) {
6810 if (net_ratelimit())
6811 netif_err(tp, drv, tp->dev,
6812 "Failed to map TX fragments DMA!\n");
6816 /* Anti gcc 2.95.3 bugware (sic) */
6817 status = opts[0] | len |
6818 (RingEnd * !((entry + 1) % NUM_TX_DESC));
6820 txd->opts1 = cpu_to_le32(status);
6821 txd->opts2 = cpu_to_le32(opts[1]);
6822 txd->addr = cpu_to_le64(mapping);
6824 tp->tx_skb[entry].len = len;
6828 tp->tx_skb[entry].skb = skb;
6829 txd->opts1 |= cpu_to_le32(LastFrag);
6835 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
6839 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
6841 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
6844 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6845 struct net_device *dev);
6846 /* r8169_csum_workaround()
6847 * The hw limites the value the transport offset. When the offset is out of the
6848 * range, calculate the checksum by sw.
6850 static void r8169_csum_workaround(struct rtl8169_private *tp,
6851 struct sk_buff *skb)
6853 if (skb_shinfo(skb)->gso_size) {
6854 netdev_features_t features = tp->dev->features;
6855 struct sk_buff *segs, *nskb;
6857 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
6858 segs = skb_gso_segment(skb, features);
6859 if (IS_ERR(segs) || !segs)
6866 rtl8169_start_xmit(nskb, tp->dev);
6870 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6871 if (skb_checksum_help(skb) < 0)
6874 rtl8169_start_xmit(skb, tp->dev);
6876 struct net_device_stats *stats;
6879 stats = &tp->dev->stats;
6880 stats->tx_dropped++;
6885 /* msdn_giant_send_check()
6886 * According to the document of microsoft, the TCP Pseudo Header excludes the
6887 * packet length for IPv6 TCP large packets.
6889 static int msdn_giant_send_check(struct sk_buff *skb)
6891 const struct ipv6hdr *ipv6h;
6895 ret = skb_cow_head(skb, 0);
6899 ipv6h = ipv6_hdr(skb);
6903 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
6908 static inline __be16 get_protocol(struct sk_buff *skb)
6912 if (skb->protocol == htons(ETH_P_8021Q))
6913 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
6915 protocol = skb->protocol;
6920 static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
6921 struct sk_buff *skb, u32 *opts)
6923 u32 mss = skb_shinfo(skb)->gso_size;
6927 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
6928 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6929 const struct iphdr *ip = ip_hdr(skb);
6931 if (ip->protocol == IPPROTO_TCP)
6932 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
6933 else if (ip->protocol == IPPROTO_UDP)
6934 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
6942 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
6943 struct sk_buff *skb, u32 *opts)
6945 u32 transport_offset = (u32)skb_transport_offset(skb);
6946 u32 mss = skb_shinfo(skb)->gso_size;
6949 if (transport_offset > GTTCPHO_MAX) {
6950 netif_warn(tp, tx_err, tp->dev,
6951 "Invalid transport offset 0x%x for TSO\n",
6956 switch (get_protocol(skb)) {
6957 case htons(ETH_P_IP):
6958 opts[0] |= TD1_GTSENV4;
6961 case htons(ETH_P_IPV6):
6962 if (msdn_giant_send_check(skb))
6965 opts[0] |= TD1_GTSENV6;
6973 opts[0] |= transport_offset << GTTCPHO_SHIFT;
6974 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
6975 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6978 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
6979 return !(skb_checksum_help(skb) || eth_skb_pad(skb));
6981 if (transport_offset > TCPHO_MAX) {
6982 netif_warn(tp, tx_err, tp->dev,
6983 "Invalid transport offset 0x%x\n",
6988 switch (get_protocol(skb)) {
6989 case htons(ETH_P_IP):
6990 opts[1] |= TD1_IPv4_CS;
6991 ip_protocol = ip_hdr(skb)->protocol;
6994 case htons(ETH_P_IPV6):
6995 opts[1] |= TD1_IPv6_CS;
6996 ip_protocol = ipv6_hdr(skb)->nexthdr;
7000 ip_protocol = IPPROTO_RAW;
7004 if (ip_protocol == IPPROTO_TCP)
7005 opts[1] |= TD1_TCP_CS;
7006 else if (ip_protocol == IPPROTO_UDP)
7007 opts[1] |= TD1_UDP_CS;
7011 opts[1] |= transport_offset << TCPHO_SHIFT;
7013 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
7014 return !eth_skb_pad(skb);
7020 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
7021 struct net_device *dev)
7023 struct rtl8169_private *tp = netdev_priv(dev);
7024 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
7025 struct TxDesc *txd = tp->TxDescArray + entry;
7026 void __iomem *ioaddr = tp->mmio_addr;
7027 struct device *d = &tp->pci_dev->dev;
7033 if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
7034 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
7038 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
7041 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
7044 if (!tp->tso_csum(tp, skb, opts)) {
7045 r8169_csum_workaround(tp, skb);
7046 return NETDEV_TX_OK;
7049 len = skb_headlen(skb);
7050 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
7051 if (unlikely(dma_mapping_error(d, mapping))) {
7052 if (net_ratelimit())
7053 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
7057 tp->tx_skb[entry].len = len;
7058 txd->addr = cpu_to_le64(mapping);
7060 frags = rtl8169_xmit_frags(tp, skb, opts);
7064 opts[0] |= FirstFrag;
7066 opts[0] |= FirstFrag | LastFrag;
7067 tp->tx_skb[entry].skb = skb;
7070 txd->opts2 = cpu_to_le32(opts[1]);
7072 netdev_sent_queue(dev, skb->len);
7074 skb_tx_timestamp(skb);
7078 /* Anti gcc 2.95.3 bugware (sic) */
7079 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
7080 txd->opts1 = cpu_to_le32(status);
7082 tp->cur_tx += frags + 1;
7086 RTL_W8(TxPoll, NPQ);
7090 if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
7091 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
7092 * not miss a ring update when it notices a stopped queue.
7095 netif_stop_queue(dev);
7096 /* Sync with rtl_tx:
7097 * - publish queue status and cur_tx ring index (write barrier)
7098 * - refresh dirty_tx ring index (read barrier).
7099 * May the current thread have a pessimistic view of the ring
7100 * status and forget to wake up queue, a racing rtl_tx thread
7104 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
7105 netif_wake_queue(dev);
7108 return NETDEV_TX_OK;
7111 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
7113 dev_kfree_skb_any(skb);
7114 dev->stats.tx_dropped++;
7115 return NETDEV_TX_OK;
7118 netif_stop_queue(dev);
7119 dev->stats.tx_dropped++;
7120 return NETDEV_TX_BUSY;
7123 static void rtl8169_pcierr_interrupt(struct net_device *dev)
7125 struct rtl8169_private *tp = netdev_priv(dev);
7126 struct pci_dev *pdev = tp->pci_dev;
7127 u16 pci_status, pci_cmd;
7129 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
7130 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
7132 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
7133 pci_cmd, pci_status);
7136 * The recovery sequence below admits a very elaborated explanation:
7137 * - it seems to work;
7138 * - I did not see what else could be done;
7139 * - it makes iop3xx happy.
7141 * Feel free to adjust to your needs.
7143 if (pdev->broken_parity_status)
7144 pci_cmd &= ~PCI_COMMAND_PARITY;
7146 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
7148 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
7150 pci_write_config_word(pdev, PCI_STATUS,
7151 pci_status & (PCI_STATUS_DETECTED_PARITY |
7152 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
7153 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
7155 /* The infamous DAC f*ckup only happens at boot time */
7156 if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
7157 void __iomem *ioaddr = tp->mmio_addr;
7159 netif_info(tp, intr, dev, "disabling PCI DAC\n");
7160 tp->cp_cmd &= ~PCIDAC;
7161 RTL_W16(CPlusCmd, tp->cp_cmd);
7162 dev->features &= ~NETIF_F_HIGHDMA;
7165 rtl8169_hw_reset(tp);
7167 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7170 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
7172 unsigned int dirty_tx, tx_left;
7173 unsigned int bytes_compl = 0, pkts_compl = 0;
7175 dirty_tx = tp->dirty_tx;
7177 tx_left = tp->cur_tx - dirty_tx;
7179 while (tx_left > 0) {
7180 unsigned int entry = dirty_tx % NUM_TX_DESC;
7181 struct ring_info *tx_skb = tp->tx_skb + entry;
7185 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
7186 if (status & DescOwn)
7189 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
7190 tp->TxDescArray + entry);
7191 if (status & LastFrag) {
7193 bytes_compl += tx_skb->skb->len;
7194 dev_kfree_skb_any(tx_skb->skb);
7201 if (tp->dirty_tx != dirty_tx) {
7202 netdev_completed_queue(tp->dev, pkts_compl, bytes_compl);
7204 u64_stats_update_begin(&tp->tx_stats.syncp);
7205 tp->tx_stats.packets += pkts_compl;
7206 tp->tx_stats.bytes += bytes_compl;
7207 u64_stats_update_end(&tp->tx_stats.syncp);
7209 tp->dirty_tx = dirty_tx;
7210 /* Sync with rtl8169_start_xmit:
7211 * - publish dirty_tx ring index (write barrier)
7212 * - refresh cur_tx ring index and queue status (read barrier)
7213 * May the current thread miss the stopped queue condition,
7214 * a racing xmit thread can only have a right view of the
7218 if (netif_queue_stopped(dev) &&
7219 TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
7220 netif_wake_queue(dev);
7223 * 8168 hack: TxPoll requests are lost when the Tx packets are
7224 * too close. Let's kick an extra TxPoll request when a burst
7225 * of start_xmit activity is detected (if it is not detected,
7226 * it is slow enough). -- FR
7228 if (tp->cur_tx != dirty_tx) {
7229 void __iomem *ioaddr = tp->mmio_addr;
7231 RTL_W8(TxPoll, NPQ);
7236 static inline int rtl8169_fragmented_frame(u32 status)
7238 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
7241 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
7243 u32 status = opts1 & RxProtoMask;
7245 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
7246 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
7247 skb->ip_summed = CHECKSUM_UNNECESSARY;
7249 skb_checksum_none_assert(skb);
7252 static struct sk_buff *rtl8169_try_rx_copy(void *data,
7253 struct rtl8169_private *tp,
7257 struct sk_buff *skb;
7258 struct device *d = &tp->pci_dev->dev;
7260 data = rtl8169_align(data);
7261 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
7263 skb = napi_alloc_skb(&tp->napi, pkt_size);
7265 memcpy(skb->data, data, pkt_size);
7266 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
7271 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
7273 unsigned int cur_rx, rx_left;
7276 cur_rx = tp->cur_rx;
7278 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
7279 unsigned int entry = cur_rx % NUM_RX_DESC;
7280 struct RxDesc *desc = tp->RxDescArray + entry;
7284 status = le32_to_cpu(desc->opts1) & tp->opts1_mask;
7286 if (status & DescOwn)
7288 if (unlikely(status & RxRES)) {
7289 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
7291 dev->stats.rx_errors++;
7292 if (status & (RxRWT | RxRUNT))
7293 dev->stats.rx_length_errors++;
7295 dev->stats.rx_crc_errors++;
7296 if (status & RxFOVF) {
7297 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7298 dev->stats.rx_fifo_errors++;
7300 if ((status & (RxRUNT | RxCRC)) &&
7301 !(status & (RxRWT | RxFOVF)) &&
7302 (dev->features & NETIF_F_RXALL))
7305 struct sk_buff *skb;
7310 addr = le64_to_cpu(desc->addr);
7311 if (likely(!(dev->features & NETIF_F_RXFCS)))
7312 pkt_size = (status & 0x00003fff) - 4;
7314 pkt_size = status & 0x00003fff;
7317 * The driver does not support incoming fragmented
7318 * frames. They are seen as a symptom of over-mtu
7321 if (unlikely(rtl8169_fragmented_frame(status))) {
7322 dev->stats.rx_dropped++;
7323 dev->stats.rx_length_errors++;
7324 goto release_descriptor;
7327 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
7328 tp, pkt_size, addr);
7330 dev->stats.rx_dropped++;
7331 goto release_descriptor;
7334 rtl8169_rx_csum(skb, status);
7335 skb_put(skb, pkt_size);
7336 skb->protocol = eth_type_trans(skb, dev);
7338 rtl8169_rx_vlan_tag(desc, skb);
7340 napi_gro_receive(&tp->napi, skb);
7342 u64_stats_update_begin(&tp->rx_stats.syncp);
7343 tp->rx_stats.packets++;
7344 tp->rx_stats.bytes += pkt_size;
7345 u64_stats_update_end(&tp->rx_stats.syncp);
7350 rtl8169_mark_to_asic(desc, rx_buf_sz);
7353 count = cur_rx - tp->cur_rx;
7354 tp->cur_rx = cur_rx;
7359 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
7361 struct net_device *dev = dev_instance;
7362 struct rtl8169_private *tp = netdev_priv(dev);
7366 status = rtl_get_events(tp);
7367 if (status && status != 0xffff) {
7368 status &= RTL_EVENT_NAPI | tp->event_slow;
7372 rtl_irq_disable(tp);
7373 napi_schedule(&tp->napi);
7376 return IRQ_RETVAL(handled);
7380 * Workqueue context.
7382 static void rtl_slow_event_work(struct rtl8169_private *tp)
7384 struct net_device *dev = tp->dev;
7387 status = rtl_get_events(tp) & tp->event_slow;
7388 rtl_ack_events(tp, status);
7390 if (unlikely(status & RxFIFOOver)) {
7391 switch (tp->mac_version) {
7392 /* Work around for rx fifo overflow */
7393 case RTL_GIGA_MAC_VER_11:
7394 netif_stop_queue(dev);
7395 /* XXX - Hack alert. See rtl_task(). */
7396 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
7402 if (unlikely(status & SYSErr))
7403 rtl8169_pcierr_interrupt(dev);
7405 if (status & LinkChg)
7406 __rtl8169_check_link_status(dev, tp, tp->mmio_addr, true);
7408 rtl_irq_enable_all(tp);
7411 static void rtl_task(struct work_struct *work)
7413 static const struct {
7415 void (*action)(struct rtl8169_private *);
7417 /* XXX - keep rtl_slow_event_work() as first element. */
7418 { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work },
7419 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
7420 { RTL_FLAG_TASK_PHY_PENDING, rtl_phy_work }
7422 struct rtl8169_private *tp =
7423 container_of(work, struct rtl8169_private, wk.work);
7424 struct net_device *dev = tp->dev;
7429 if (!netif_running(dev) ||
7430 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
7433 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
7436 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
7438 rtl_work[i].action(tp);
7442 rtl_unlock_work(tp);
7445 static int rtl8169_poll(struct napi_struct *napi, int budget)
7447 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
7448 struct net_device *dev = tp->dev;
7449 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
7453 status = rtl_get_events(tp);
7454 rtl_ack_events(tp, status & ~tp->event_slow);
7456 if (status & RTL_EVENT_NAPI_RX)
7457 work_done = rtl_rx(dev, tp, (u32) budget);
7459 if (status & RTL_EVENT_NAPI_TX)
7462 if (status & tp->event_slow) {
7463 enable_mask &= ~tp->event_slow;
7465 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
7468 if (work_done < budget) {
7469 napi_complete(napi);
7471 rtl_irq_enable(tp, enable_mask);
7478 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
7480 struct rtl8169_private *tp = netdev_priv(dev);
7482 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
7485 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
7486 RTL_W32(RxMissed, 0);
7489 static void rtl8169_down(struct net_device *dev)
7491 struct rtl8169_private *tp = netdev_priv(dev);
7492 void __iomem *ioaddr = tp->mmio_addr;
7494 del_timer_sync(&tp->timer);
7496 napi_disable(&tp->napi);
7497 netif_stop_queue(dev);
7499 rtl8169_hw_reset(tp);
7501 * At this point device interrupts can not be enabled in any function,
7502 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
7503 * and napi is disabled (rtl8169_poll).
7505 rtl8169_rx_missed(dev, ioaddr);
7507 /* Give a racing hard_start_xmit a few cycles to complete. */
7508 synchronize_sched();
7510 rtl8169_tx_clear(tp);
7512 rtl8169_rx_clear(tp);
7514 rtl_pll_power_down(tp);
7517 static int rtl8169_close(struct net_device *dev)
7519 struct rtl8169_private *tp = netdev_priv(dev);
7520 struct pci_dev *pdev = tp->pci_dev;
7522 pm_runtime_get_sync(&pdev->dev);
7524 /* Update counters before going down */
7525 rtl8169_update_counters(dev);
7528 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7531 rtl_unlock_work(tp);
7533 cancel_work_sync(&tp->wk.work);
7535 free_irq(pdev->irq, dev);
7537 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7539 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7541 tp->TxDescArray = NULL;
7542 tp->RxDescArray = NULL;
7544 pm_runtime_put_sync(&pdev->dev);
7549 #ifdef CONFIG_NET_POLL_CONTROLLER
7550 static void rtl8169_netpoll(struct net_device *dev)
7552 struct rtl8169_private *tp = netdev_priv(dev);
7554 rtl8169_interrupt(tp->pci_dev->irq, dev);
7558 static int rtl_open(struct net_device *dev)
7560 struct rtl8169_private *tp = netdev_priv(dev);
7561 void __iomem *ioaddr = tp->mmio_addr;
7562 struct pci_dev *pdev = tp->pci_dev;
7563 int retval = -ENOMEM;
7565 pm_runtime_get_sync(&pdev->dev);
7568 * Rx and Tx descriptors needs 256 bytes alignment.
7569 * dma_alloc_coherent provides more.
7571 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
7572 &tp->TxPhyAddr, GFP_KERNEL);
7573 if (!tp->TxDescArray)
7574 goto err_pm_runtime_put;
7576 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
7577 &tp->RxPhyAddr, GFP_KERNEL);
7578 if (!tp->RxDescArray)
7581 retval = rtl8169_init_ring(dev);
7585 INIT_WORK(&tp->wk.work, rtl_task);
7589 rtl_request_firmware(tp);
7591 retval = request_irq(pdev->irq, rtl8169_interrupt,
7592 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
7595 goto err_release_fw_2;
7599 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7601 napi_enable(&tp->napi);
7603 rtl8169_init_phy(dev, tp);
7605 __rtl8169_set_features(dev, dev->features);
7607 rtl_pll_power_up(tp);
7611 netif_start_queue(dev);
7613 rtl_unlock_work(tp);
7615 tp->saved_wolopts = 0;
7616 pm_runtime_put_noidle(&pdev->dev);
7618 rtl8169_check_link_status(dev, tp, ioaddr);
7623 rtl_release_firmware(tp);
7624 rtl8169_rx_clear(tp);
7626 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
7628 tp->RxDescArray = NULL;
7630 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
7632 tp->TxDescArray = NULL;
7634 pm_runtime_put_noidle(&pdev->dev);
7638 static struct rtnl_link_stats64 *
7639 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
7641 struct rtl8169_private *tp = netdev_priv(dev);
7642 void __iomem *ioaddr = tp->mmio_addr;
7645 if (netif_running(dev))
7646 rtl8169_rx_missed(dev, ioaddr);
7649 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
7650 stats->rx_packets = tp->rx_stats.packets;
7651 stats->rx_bytes = tp->rx_stats.bytes;
7652 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
7656 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
7657 stats->tx_packets = tp->tx_stats.packets;
7658 stats->tx_bytes = tp->tx_stats.bytes;
7659 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
7661 stats->rx_dropped = dev->stats.rx_dropped;
7662 stats->tx_dropped = dev->stats.tx_dropped;
7663 stats->rx_length_errors = dev->stats.rx_length_errors;
7664 stats->rx_errors = dev->stats.rx_errors;
7665 stats->rx_crc_errors = dev->stats.rx_crc_errors;
7666 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
7667 stats->rx_missed_errors = dev->stats.rx_missed_errors;
7672 static void rtl8169_net_suspend(struct net_device *dev)
7674 struct rtl8169_private *tp = netdev_priv(dev);
7676 if (!netif_running(dev))
7679 netif_device_detach(dev);
7680 netif_stop_queue(dev);
7683 napi_disable(&tp->napi);
7684 clear_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7685 rtl_unlock_work(tp);
7687 rtl_pll_power_down(tp);
7692 static int rtl8169_suspend(struct device *device)
7694 struct pci_dev *pdev = to_pci_dev(device);
7695 struct net_device *dev = pci_get_drvdata(pdev);
7697 rtl8169_net_suspend(dev);
7702 static void __rtl8169_resume(struct net_device *dev)
7704 struct rtl8169_private *tp = netdev_priv(dev);
7706 netif_device_attach(dev);
7708 rtl_pll_power_up(tp);
7711 napi_enable(&tp->napi);
7712 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7713 rtl_unlock_work(tp);
7715 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7718 static int rtl8169_resume(struct device *device)
7720 struct pci_dev *pdev = to_pci_dev(device);
7721 struct net_device *dev = pci_get_drvdata(pdev);
7722 struct rtl8169_private *tp = netdev_priv(dev);
7724 rtl8169_init_phy(dev, tp);
7726 if (netif_running(dev))
7727 __rtl8169_resume(dev);
7732 static int rtl8169_runtime_suspend(struct device *device)
7734 struct pci_dev *pdev = to_pci_dev(device);
7735 struct net_device *dev = pci_get_drvdata(pdev);
7736 struct rtl8169_private *tp = netdev_priv(dev);
7738 if (!tp->TxDescArray)
7742 tp->saved_wolopts = __rtl8169_get_wol(tp);
7743 __rtl8169_set_wol(tp, WAKE_ANY);
7744 rtl_unlock_work(tp);
7746 rtl8169_net_suspend(dev);
7751 static int rtl8169_runtime_resume(struct device *device)
7753 struct pci_dev *pdev = to_pci_dev(device);
7754 struct net_device *dev = pci_get_drvdata(pdev);
7755 struct rtl8169_private *tp = netdev_priv(dev);
7757 if (!tp->TxDescArray)
7761 __rtl8169_set_wol(tp, tp->saved_wolopts);
7762 tp->saved_wolopts = 0;
7763 rtl_unlock_work(tp);
7765 rtl8169_init_phy(dev, tp);
7767 __rtl8169_resume(dev);
7772 static int rtl8169_runtime_idle(struct device *device)
7774 struct pci_dev *pdev = to_pci_dev(device);
7775 struct net_device *dev = pci_get_drvdata(pdev);
7776 struct rtl8169_private *tp = netdev_priv(dev);
7778 return tp->TxDescArray ? -EBUSY : 0;
7781 static const struct dev_pm_ops rtl8169_pm_ops = {
7782 .suspend = rtl8169_suspend,
7783 .resume = rtl8169_resume,
7784 .freeze = rtl8169_suspend,
7785 .thaw = rtl8169_resume,
7786 .poweroff = rtl8169_suspend,
7787 .restore = rtl8169_resume,
7788 .runtime_suspend = rtl8169_runtime_suspend,
7789 .runtime_resume = rtl8169_runtime_resume,
7790 .runtime_idle = rtl8169_runtime_idle,
7793 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
7795 #else /* !CONFIG_PM */
7797 #define RTL8169_PM_OPS NULL
7799 #endif /* !CONFIG_PM */
7801 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
7803 void __iomem *ioaddr = tp->mmio_addr;
7805 /* WoL fails with 8168b when the receiver is disabled. */
7806 switch (tp->mac_version) {
7807 case RTL_GIGA_MAC_VER_11:
7808 case RTL_GIGA_MAC_VER_12:
7809 case RTL_GIGA_MAC_VER_17:
7810 pci_clear_master(tp->pci_dev);
7812 RTL_W8(ChipCmd, CmdRxEnb);
7821 static void rtl_shutdown(struct pci_dev *pdev)
7823 struct net_device *dev = pci_get_drvdata(pdev);
7824 struct rtl8169_private *tp = netdev_priv(dev);
7825 struct device *d = &pdev->dev;
7827 pm_runtime_get_sync(d);
7829 rtl8169_net_suspend(dev);
7831 /* Restore original MAC address */
7832 rtl_rar_set(tp, dev->perm_addr);
7834 rtl8169_hw_reset(tp);
7836 if (system_state == SYSTEM_POWER_OFF) {
7837 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
7838 rtl_wol_suspend_quirk(tp);
7839 rtl_wol_shutdown_quirk(tp);
7842 pci_wake_from_d3(pdev, true);
7843 pci_set_power_state(pdev, PCI_D3hot);
7846 pm_runtime_put_noidle(d);
7849 static void rtl_remove_one(struct pci_dev *pdev)
7851 struct net_device *dev = pci_get_drvdata(pdev);
7852 struct rtl8169_private *tp = netdev_priv(dev);
7854 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
7855 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
7856 tp->mac_version == RTL_GIGA_MAC_VER_31 ||
7857 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
7858 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
7859 tp->mac_version == RTL_GIGA_MAC_VER_51) &&
7860 r8168_check_dash(tp)) {
7861 rtl8168_driver_stop(tp);
7864 netif_napi_del(&tp->napi);
7866 unregister_netdev(dev);
7868 rtl_release_firmware(tp);
7870 if (pci_dev_run_wake(pdev))
7871 pm_runtime_get_noresume(&pdev->dev);
7873 /* restore original MAC address */
7874 rtl_rar_set(tp, dev->perm_addr);
7876 rtl_disable_msi(pdev, tp);
7877 rtl8169_release_board(pdev, dev, tp->mmio_addr);
7880 static const struct net_device_ops rtl_netdev_ops = {
7881 .ndo_open = rtl_open,
7882 .ndo_stop = rtl8169_close,
7883 .ndo_get_stats64 = rtl8169_get_stats64,
7884 .ndo_start_xmit = rtl8169_start_xmit,
7885 .ndo_tx_timeout = rtl8169_tx_timeout,
7886 .ndo_validate_addr = eth_validate_addr,
7887 .ndo_change_mtu = rtl8169_change_mtu,
7888 .ndo_fix_features = rtl8169_fix_features,
7889 .ndo_set_features = rtl8169_set_features,
7890 .ndo_set_mac_address = rtl_set_mac_address,
7891 .ndo_do_ioctl = rtl8169_ioctl,
7892 .ndo_set_rx_mode = rtl_set_rx_mode,
7893 #ifdef CONFIG_NET_POLL_CONTROLLER
7894 .ndo_poll_controller = rtl8169_netpoll,
7899 static const struct rtl_cfg_info {
7900 void (*hw_start)(struct net_device *);
7901 unsigned int region;
7906 } rtl_cfg_infos [] = {
7908 .hw_start = rtl_hw_start_8169,
7911 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
7912 .features = RTL_FEATURE_GMII,
7913 .default_ver = RTL_GIGA_MAC_VER_01,
7916 .hw_start = rtl_hw_start_8168,
7919 .event_slow = SYSErr | LinkChg | RxOverflow,
7920 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
7921 .default_ver = RTL_GIGA_MAC_VER_11,
7924 .hw_start = rtl_hw_start_8101,
7927 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
7929 .features = RTL_FEATURE_MSI,
7930 .default_ver = RTL_GIGA_MAC_VER_13,
7934 /* Cfg9346_Unlock assumed. */
7935 static unsigned rtl_try_msi(struct rtl8169_private *tp,
7936 const struct rtl_cfg_info *cfg)
7938 void __iomem *ioaddr = tp->mmio_addr;
7942 cfg2 = RTL_R8(Config2) & ~MSIEnable;
7943 if (cfg->features & RTL_FEATURE_MSI) {
7944 if (pci_enable_msi(tp->pci_dev)) {
7945 netif_info(tp, hw, tp->dev, "no MSI. Back to INTx.\n");
7948 msi = RTL_FEATURE_MSI;
7951 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
7952 RTL_W8(Config2, cfg2);
7956 DECLARE_RTL_COND(rtl_link_list_ready_cond)
7958 void __iomem *ioaddr = tp->mmio_addr;
7960 return RTL_R8(MCU) & LINK_LIST_RDY;
7963 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
7965 void __iomem *ioaddr = tp->mmio_addr;
7967 return (RTL_R8(MCU) & RXTX_EMPTY) == RXTX_EMPTY;
7970 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
7972 void __iomem *ioaddr = tp->mmio_addr;
7975 tp->ocp_base = OCP_STD_PHY_BASE;
7977 RTL_W32(MISC, RTL_R32(MISC) | RXDV_GATED_EN);
7979 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
7982 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
7985 RTL_W8(ChipCmd, RTL_R8(ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
7987 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
7989 data = r8168_mac_ocp_read(tp, 0xe8de);
7991 r8168_mac_ocp_write(tp, 0xe8de, data);
7993 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7996 data = r8168_mac_ocp_read(tp, 0xe8de);
7998 r8168_mac_ocp_write(tp, 0xe8de, data);
8000 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
8004 static void rtl_hw_init_8168ep(struct rtl8169_private *tp)
8006 rtl8168ep_stop_cmac(tp);
8007 rtl_hw_init_8168g(tp);
8010 static void rtl_hw_initialize(struct rtl8169_private *tp)
8012 switch (tp->mac_version) {
8013 case RTL_GIGA_MAC_VER_40:
8014 case RTL_GIGA_MAC_VER_41:
8015 case RTL_GIGA_MAC_VER_42:
8016 case RTL_GIGA_MAC_VER_43:
8017 case RTL_GIGA_MAC_VER_44:
8018 case RTL_GIGA_MAC_VER_45:
8019 case RTL_GIGA_MAC_VER_46:
8020 case RTL_GIGA_MAC_VER_47:
8021 case RTL_GIGA_MAC_VER_48:
8022 rtl_hw_init_8168g(tp);
8024 case RTL_GIGA_MAC_VER_49:
8025 case RTL_GIGA_MAC_VER_50:
8026 case RTL_GIGA_MAC_VER_51:
8027 rtl_hw_init_8168ep(tp);
8034 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
8036 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
8037 const unsigned int region = cfg->region;
8038 struct rtl8169_private *tp;
8039 struct mii_if_info *mii;
8040 struct net_device *dev;
8041 void __iomem *ioaddr;
8045 if (netif_msg_drv(&debug)) {
8046 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
8047 MODULENAME, RTL8169_VERSION);
8050 dev = alloc_etherdev(sizeof (*tp));
8056 SET_NETDEV_DEV(dev, &pdev->dev);
8057 dev->netdev_ops = &rtl_netdev_ops;
8058 tp = netdev_priv(dev);
8061 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
8065 mii->mdio_read = rtl_mdio_read;
8066 mii->mdio_write = rtl_mdio_write;
8067 mii->phy_id_mask = 0x1f;
8068 mii->reg_num_mask = 0x1f;
8069 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
8071 /* disable ASPM completely as that cause random device stop working
8072 * problems as well as full system hangs for some PCIe devices users */
8073 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
8074 PCIE_LINK_STATE_CLKPM);
8076 /* enable device (incl. PCI PM wakeup and hotplug setup) */
8077 rc = pci_enable_device(pdev);
8079 netif_err(tp, probe, dev, "enable failure\n");
8080 goto err_out_free_dev_1;
8083 if (pci_set_mwi(pdev) < 0)
8084 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
8086 /* make sure PCI base addr 1 is MMIO */
8087 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
8088 netif_err(tp, probe, dev,
8089 "region #%d not an MMIO resource, aborting\n",
8095 /* check for weird/broken PCI region reporting */
8096 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
8097 netif_err(tp, probe, dev,
8098 "Invalid PCI region size(s), aborting\n");
8103 rc = pci_request_regions(pdev, MODULENAME);
8105 netif_err(tp, probe, dev, "could not request regions\n");
8111 if ((sizeof(dma_addr_t) > 4) &&
8112 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
8113 tp->cp_cmd |= PCIDAC;
8114 dev->features |= NETIF_F_HIGHDMA;
8116 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
8118 netif_err(tp, probe, dev, "DMA configuration failed\n");
8119 goto err_out_free_res_3;
8123 /* ioremap MMIO region */
8124 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
8126 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
8128 goto err_out_free_res_3;
8130 tp->mmio_addr = ioaddr;
8132 if (!pci_is_pcie(pdev))
8133 netif_info(tp, probe, dev, "not PCI Express\n");
8135 /* Identify chip attached to board */
8136 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
8140 rtl_irq_disable(tp);
8142 rtl_hw_initialize(tp);
8146 rtl_ack_events(tp, 0xffff);
8148 pci_set_master(pdev);
8150 rtl_init_mdio_ops(tp);
8151 rtl_init_pll_power_ops(tp);
8152 rtl_init_jumbo_ops(tp);
8153 rtl_init_csi_ops(tp);
8155 rtl8169_print_mac_version(tp);
8157 chipset = tp->mac_version;
8158 tp->txd_version = rtl_chip_infos[chipset].txd_version;
8160 RTL_W8(Cfg9346, Cfg9346_Unlock);
8161 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
8162 RTL_W8(Config5, RTL_R8(Config5) & (BWF | MWF | UWF | LanWake | PMEStatus));
8163 switch (tp->mac_version) {
8164 case RTL_GIGA_MAC_VER_34:
8165 case RTL_GIGA_MAC_VER_35:
8166 case RTL_GIGA_MAC_VER_36:
8167 case RTL_GIGA_MAC_VER_37:
8168 case RTL_GIGA_MAC_VER_38:
8169 case RTL_GIGA_MAC_VER_40:
8170 case RTL_GIGA_MAC_VER_41:
8171 case RTL_GIGA_MAC_VER_42:
8172 case RTL_GIGA_MAC_VER_43:
8173 case RTL_GIGA_MAC_VER_44:
8174 case RTL_GIGA_MAC_VER_45:
8175 case RTL_GIGA_MAC_VER_46:
8176 case RTL_GIGA_MAC_VER_47:
8177 case RTL_GIGA_MAC_VER_48:
8178 case RTL_GIGA_MAC_VER_49:
8179 case RTL_GIGA_MAC_VER_50:
8180 case RTL_GIGA_MAC_VER_51:
8181 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
8182 tp->features |= RTL_FEATURE_WOL;
8183 if ((RTL_R8(Config3) & LinkUp) != 0)
8184 tp->features |= RTL_FEATURE_WOL;
8187 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
8188 tp->features |= RTL_FEATURE_WOL;
8191 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
8192 tp->features |= RTL_FEATURE_WOL;
8193 tp->features |= rtl_try_msi(tp, cfg);
8194 RTL_W8(Cfg9346, Cfg9346_Lock);
8196 if (rtl_tbi_enabled(tp)) {
8197 tp->set_speed = rtl8169_set_speed_tbi;
8198 tp->get_settings = rtl8169_gset_tbi;
8199 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
8200 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
8201 tp->link_ok = rtl8169_tbi_link_ok;
8202 tp->do_ioctl = rtl_tbi_ioctl;
8204 tp->set_speed = rtl8169_set_speed_xmii;
8205 tp->get_settings = rtl8169_gset_xmii;
8206 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
8207 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
8208 tp->link_ok = rtl8169_xmii_link_ok;
8209 tp->do_ioctl = rtl_xmii_ioctl;
8212 mutex_init(&tp->wk.mutex);
8213 u64_stats_init(&tp->rx_stats.syncp);
8214 u64_stats_init(&tp->tx_stats.syncp);
8216 /* Get MAC address */
8217 if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
8218 tp->mac_version == RTL_GIGA_MAC_VER_36 ||
8219 tp->mac_version == RTL_GIGA_MAC_VER_37 ||
8220 tp->mac_version == RTL_GIGA_MAC_VER_38 ||
8221 tp->mac_version == RTL_GIGA_MAC_VER_40 ||
8222 tp->mac_version == RTL_GIGA_MAC_VER_41 ||
8223 tp->mac_version == RTL_GIGA_MAC_VER_42 ||
8224 tp->mac_version == RTL_GIGA_MAC_VER_43 ||
8225 tp->mac_version == RTL_GIGA_MAC_VER_44 ||
8226 tp->mac_version == RTL_GIGA_MAC_VER_45 ||
8227 tp->mac_version == RTL_GIGA_MAC_VER_46 ||
8228 tp->mac_version == RTL_GIGA_MAC_VER_47 ||
8229 tp->mac_version == RTL_GIGA_MAC_VER_48 ||
8230 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8231 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8232 tp->mac_version == RTL_GIGA_MAC_VER_51) {
8235 *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);
8236 *(u16 *)&mac_addr[2] = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC);
8238 if (is_valid_ether_addr((u8 *)mac_addr))
8239 rtl_rar_set(tp, (u8 *)mac_addr);
8241 for (i = 0; i < ETH_ALEN; i++)
8242 dev->dev_addr[i] = RTL_R8(MAC0 + i);
8244 dev->ethtool_ops = &rtl8169_ethtool_ops;
8245 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
8247 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
8249 /* don't enable SG, IP_CSUM and TSO by default - it might not work
8250 * properly for all devices */
8251 dev->features |= NETIF_F_RXCSUM |
8252 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
8254 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
8255 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
8256 NETIF_F_HW_VLAN_CTAG_RX;
8257 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
8260 tp->cp_cmd |= RxChkSum | RxVlan;
8263 * Pretend we are using VLANs; This bypasses a nasty bug where
8264 * Interrupts stop flowing on high load on 8110SCd controllers.
8266 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
8267 /* Disallow toggling */
8268 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
8270 if (tp->txd_version == RTL_TD_0)
8271 tp->tso_csum = rtl8169_tso_csum_v1;
8272 else if (tp->txd_version == RTL_TD_1) {
8273 tp->tso_csum = rtl8169_tso_csum_v2;
8274 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
8278 dev->hw_features |= NETIF_F_RXALL;
8279 dev->hw_features |= NETIF_F_RXFCS;
8281 tp->hw_start = cfg->hw_start;
8282 tp->event_slow = cfg->event_slow;
8284 tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ?
8285 ~(RxBOVF | RxFOVF) : ~0;
8287 init_timer(&tp->timer);
8288 tp->timer.data = (unsigned long) dev;
8289 tp->timer.function = rtl8169_phy_timer;
8291 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
8293 rc = register_netdev(dev);
8297 pci_set_drvdata(pdev, dev);
8299 netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
8300 rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
8301 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
8302 if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
8303 netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
8304 "tx checksumming: %s]\n",
8305 rtl_chip_infos[chipset].jumbo_max,
8306 rtl_chip_infos[chipset].jumbo_tx_csum ? "ok" : "ko");
8309 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
8310 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
8311 tp->mac_version == RTL_GIGA_MAC_VER_31 ||
8312 tp->mac_version == RTL_GIGA_MAC_VER_49 ||
8313 tp->mac_version == RTL_GIGA_MAC_VER_50 ||
8314 tp->mac_version == RTL_GIGA_MAC_VER_51) &&
8315 r8168_check_dash(tp)) {
8316 rtl8168_driver_start(tp);
8319 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
8321 if (pci_dev_run_wake(pdev))
8322 pm_runtime_put_noidle(&pdev->dev);
8324 netif_carrier_off(dev);
8330 netif_napi_del(&tp->napi);
8331 rtl_disable_msi(pdev, tp);
8334 pci_release_regions(pdev);
8336 pci_clear_mwi(pdev);
8337 pci_disable_device(pdev);
8343 static struct pci_driver rtl8169_pci_driver = {
8345 .id_table = rtl8169_pci_tbl,
8346 .probe = rtl_init_one,
8347 .remove = rtl_remove_one,
8348 .shutdown = rtl_shutdown,
8349 .driver.pm = RTL8169_PM_OPS,
8352 module_pci_driver(rtl8169_pci_driver);