drivers/net/ethernet/renesas/sh_eth.c

   1 /*  SuperH Ethernet device driver
   2  *
   3  *  Copyright (C) 2014  Renesas Electronics Corporation
   4  *  Copyright (C) 2006-2012 Nobuhiro Iwamatsu
   5  *  Copyright (C) 2008-2014 Renesas Solutions Corp.
   6  *  Copyright (C) 2013-2014 Cogent Embedded, Inc.
   7  *  Copyright (C) 2014 Codethink Limited
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms and conditions of the GNU General Public License,
  11  *  version 2, as published by the Free Software Foundation.
  12  *
  13  *  This program is distributed in the hope it will be useful, but WITHOUT
  14  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  16  *  more details.
  17  *
  18  *  The full GNU General Public License is included in this distribution in
  19  *  the file called "COPYING".
  20  */
  21
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/spinlock.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/etherdevice.h>
  28 #include <linux/delay.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/mdio-bitbang.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/of.h>
  33 #include <linux/of_device.h>
  34 #include <linux/of_irq.h>
  35 #include <linux/of_net.h>
  36 #include <linux/phy.h>
  37 #include <linux/cache.h>
  38 #include <linux/io.h>
  39 #include <linux/pm_runtime.h>
  40 #include <linux/slab.h>
  41 #include <linux/ethtool.h>
  42 #include <linux/if_vlan.h>
  43 #include <linux/clk.h>
  44 #include <linux/sh_eth.h>
  45 #include <linux/of_mdio.h>
  46
  47 #include "sh_eth.h"
  48
  49 #define SH_ETH_DEF_MSG_ENABLE \
  50                 (NETIF_MSG_LINK | \
  51                 NETIF_MSG_TIMER | \
  52                 NETIF_MSG_RX_ERR| \
  53                 NETIF_MSG_TX_ERR)
  54
  55 #define SH_ETH_OFFSET_INVALID   ((u16)~0)
  56
  57 #define SH_ETH_OFFSET_DEFAULTS                  \
  58         [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID
  59
  60 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
  61         SH_ETH_OFFSET_DEFAULTS,
  62
  63         [EDSR]          = 0x0000,
  64         [EDMR]          = 0x0400,
  65         [EDTRR]         = 0x0408,
  66         [EDRRR]         = 0x0410,
  67         [EESR]          = 0x0428,
  68         [EESIPR]        = 0x0430,
  69         [TDLAR]         = 0x0010,
  70         [TDFAR]         = 0x0014,
  71         [TDFXR]         = 0x0018,
  72         [TDFFR]         = 0x001c,
  73         [RDLAR]         = 0x0030,
  74         [RDFAR]         = 0x0034,
  75         [RDFXR]         = 0x0038,
  76         [RDFFR]         = 0x003c,
  77         [TRSCER]        = 0x0438,
  78         [RMFCR]         = 0x0440,
  79         [TFTR]          = 0x0448,
  80         [FDR]           = 0x0450,
  81         [RMCR]          = 0x0458,
  82         [RPADIR]        = 0x0460,
  83         [FCFTR]         = 0x0468,
  84         [CSMR]          = 0x04E4,
  85
  86         [ECMR]          = 0x0500,
  87         [ECSR]          = 0x0510,
  88         [ECSIPR]        = 0x0518,
  89         [PIR]           = 0x0520,
  90         [PSR]           = 0x0528,
  91         [PIPR]          = 0x052c,
  92         [RFLR]          = 0x0508,
  93         [APR]           = 0x0554,
  94         [MPR]           = 0x0558,
  95         [PFTCR]         = 0x055c,
  96         [PFRCR]         = 0x0560,
  97         [TPAUSER]       = 0x0564,
  98         [GECMR]         = 0x05b0,
  99         [BCULR]         = 0x05b4,
 100         [MAHR]          = 0x05c0,
 101         [MALR]          = 0x05c8,
 102         [TROCR]         = 0x0700,
 103         [CDCR]          = 0x0708,
 104         [LCCR]          = 0x0710,
 105         [CEFCR]         = 0x0740,
 106         [FRECR]         = 0x0748,
 107         [TSFRCR]        = 0x0750,
 108         [TLFRCR]        = 0x0758,
 109         [RFCR]          = 0x0760,
 110         [CERCR]         = 0x0768,
 111         [CEECR]         = 0x0770,
 112         [MAFCR]         = 0x0778,
 113         [RMII_MII]      = 0x0790,
 114
 115         [ARSTR]         = 0x0000,
 116         [TSU_CTRST]     = 0x0004,
 117         [TSU_FWEN0]     = 0x0010,
 118         [TSU_FWEN1]     = 0x0014,
 119         [TSU_FCM]       = 0x0018,
 120         [TSU_BSYSL0]    = 0x0020,
 121         [TSU_BSYSL1]    = 0x0024,
 122         [TSU_PRISL0]    = 0x0028,
 123         [TSU_PRISL1]    = 0x002c,
 124         [TSU_FWSL0]     = 0x0030,
 125         [TSU_FWSL1]     = 0x0034,
 126         [TSU_FWSLC]     = 0x0038,
 127         [TSU_QTAG0]     = 0x0040,
 128         [TSU_QTAG1]     = 0x0044,
 129         [TSU_FWSR]      = 0x0050,
 130         [TSU_FWINMK]    = 0x0054,
 131         [TSU_ADQT0]     = 0x0048,
 132         [TSU_ADQT1]     = 0x004c,
 133         [TSU_VTAG0]     = 0x0058,
 134         [TSU_VTAG1]     = 0x005c,
 135         [TSU_ADSBSY]    = 0x0060,
 136         [TSU_TEN]       = 0x0064,
 137         [TSU_POST1]     = 0x0070,
 138         [TSU_POST2]     = 0x0074,
 139         [TSU_POST3]     = 0x0078,
 140         [TSU_POST4]     = 0x007c,
 141         [TSU_ADRH0]     = 0x0100,
 142
 143         [TXNLCR0]       = 0x0080,
 144         [TXALCR0]       = 0x0084,
 145         [RXNLCR0]       = 0x0088,
 146         [RXALCR0]       = 0x008c,
 147         [FWNLCR0]       = 0x0090,
 148         [FWALCR0]       = 0x0094,
 149         [TXNLCR1]       = 0x00a0,
 150         [TXALCR1]       = 0x00a0,
 151         [RXNLCR1]       = 0x00a8,
 152         [RXALCR1]       = 0x00ac,
 153         [FWNLCR1]       = 0x00b0,
 154         [FWALCR1]       = 0x00b4,
 155 };
 156
 157 static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
 158         SH_ETH_OFFSET_DEFAULTS,
 159
 160         [EDSR]          = 0x0000,
 161         [EDMR]          = 0x0400,
 162         [EDTRR]         = 0x0408,
 163         [EDRRR]         = 0x0410,
 164         [EESR]          = 0x0428,
 165         [EESIPR]        = 0x0430,
 166         [TDLAR]         = 0x0010,
 167         [TDFAR]         = 0x0014,
 168         [TDFXR]         = 0x0018,
 169         [TDFFR]         = 0x001c,
 170         [RDLAR]         = 0x0030,
 171         [RDFAR]         = 0x0034,
 172         [RDFXR]         = 0x0038,
 173         [RDFFR]         = 0x003c,
 174         [TRSCER]        = 0x0438,
 175         [RMFCR]         = 0x0440,
 176         [TFTR]          = 0x0448,
 177         [FDR]           = 0x0450,
 178         [RMCR]          = 0x0458,
 179         [RPADIR]        = 0x0460,
 180         [FCFTR]         = 0x0468,
 181         [CSMR]          = 0x04E4,
 182
 183         [ECMR]          = 0x0500,
 184         [RFLR]          = 0x0508,
 185         [ECSR]          = 0x0510,
 186         [ECSIPR]        = 0x0518,
 187         [PIR]           = 0x0520,
 188         [APR]           = 0x0554,
 189         [MPR]           = 0x0558,
 190         [PFTCR]         = 0x055c,
 191         [PFRCR]         = 0x0560,
 192         [TPAUSER]       = 0x0564,
 193         [MAHR]          = 0x05c0,
 194         [MALR]          = 0x05c8,
 195         [CEFCR]         = 0x0740,
 196         [FRECR]         = 0x0748,
 197         [TSFRCR]        = 0x0750,
 198         [TLFRCR]        = 0x0758,
 199         [RFCR]          = 0x0760,
 200         [MAFCR]         = 0x0778,
 201
 202         [ARSTR]         = 0x0000,
 203         [TSU_CTRST]     = 0x0004,
 204         [TSU_VTAG0]     = 0x0058,
 205         [TSU_ADSBSY]    = 0x0060,
 206         [TSU_TEN]       = 0x0064,
 207         [TSU_ADRH0]     = 0x0100,
 208
 209         [TXNLCR0]       = 0x0080,
 210         [TXALCR0]       = 0x0084,
 211         [RXNLCR0]       = 0x0088,
 212         [RXALCR0]       = 0x008C,
 213 };
 214
 215 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
 216         SH_ETH_OFFSET_DEFAULTS,
 217
 218         [ECMR]          = 0x0300,
 219         [RFLR]          = 0x0308,
 220         [ECSR]          = 0x0310,
 221         [ECSIPR]        = 0x0318,
 222         [PIR]           = 0x0320,
 223         [PSR]           = 0x0328,
 224         [RDMLR]         = 0x0340,
 225         [IPGR]          = 0x0350,
 226         [APR]           = 0x0354,
 227         [MPR]           = 0x0358,
 228         [RFCF]          = 0x0360,
 229         [TPAUSER]       = 0x0364,
 230         [TPAUSECR]      = 0x0368,
 231         [MAHR]          = 0x03c0,
 232         [MALR]          = 0x03c8,
 233         [TROCR]         = 0x03d0,
 234         [CDCR]          = 0x03d4,
 235         [LCCR]          = 0x03d8,
 236         [CNDCR]         = 0x03dc,
 237         [CEFCR]         = 0x03e4,
 238         [FRECR]         = 0x03e8,
 239         [TSFRCR]        = 0x03ec,
 240         [TLFRCR]        = 0x03f0,
 241         [RFCR]          = 0x03f4,
 242         [MAFCR]         = 0x03f8,
 243
 244         [EDMR]          = 0x0200,
 245         [EDTRR]         = 0x0208,
 246         [EDRRR]         = 0x0210,
 247         [TDLAR]         = 0x0218,
 248         [RDLAR]         = 0x0220,
 249         [EESR]          = 0x0228,
 250         [EESIPR]        = 0x0230,
 251         [TRSCER]        = 0x0238,
 252         [RMFCR]         = 0x0240,
 253         [TFTR]          = 0x0248,
 254         [FDR]           = 0x0250,
 255         [RMCR]          = 0x0258,
 256         [TFUCR]         = 0x0264,
 257         [RFOCR]         = 0x0268,
 258         [RMIIMODE]      = 0x026c,
 259         [FCFTR]         = 0x0270,
 260         [TRIMD]         = 0x027c,
 261 };
 262
 263 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
 264         SH_ETH_OFFSET_DEFAULTS,
 265
 266         [ECMR]          = 0x0100,
 267         [RFLR]          = 0x0108,
 268         [ECSR]          = 0x0110,
 269         [ECSIPR]        = 0x0118,
 270         [PIR]           = 0x0120,
 271         [PSR]           = 0x0128,
 272         [RDMLR]         = 0x0140,
 273         [IPGR]          = 0x0150,
 274         [APR]           = 0x0154,
 275         [MPR]           = 0x0158,
 276         [TPAUSER]       = 0x0164,
 277         [RFCF]          = 0x0160,
 278         [TPAUSECR]      = 0x0168,
 279         [BCFRR]         = 0x016c,
 280         [MAHR]          = 0x01c0,
 281         [MALR]          = 0x01c8,
 282         [TROCR]         = 0x01d0,
 283         [CDCR]          = 0x01d4,
 284         [LCCR]          = 0x01d8,
 285         [CNDCR]         = 0x01dc,
 286         [CEFCR]         = 0x01e4,
 287         [FRECR]         = 0x01e8,
 288         [TSFRCR]        = 0x01ec,
 289         [TLFRCR]        = 0x01f0,
 290         [RFCR]          = 0x01f4,
 291         [MAFCR]         = 0x01f8,
 292         [RTRATE]        = 0x01fc,
 293
 294         [EDMR]          = 0x0000,
 295         [EDTRR]         = 0x0008,
 296         [EDRRR]         = 0x0010,
 297         [TDLAR]         = 0x0018,
 298         [RDLAR]         = 0x0020,
 299         [EESR]          = 0x0028,
 300         [EESIPR]        = 0x0030,
 301         [TRSCER]        = 0x0038,
 302         [RMFCR]         = 0x0040,
 303         [TFTR]          = 0x0048,
 304         [FDR]           = 0x0050,
 305         [RMCR]          = 0x0058,
 306         [TFUCR]         = 0x0064,
 307         [RFOCR]         = 0x0068,
 308         [FCFTR]         = 0x0070,
 309         [RPADIR]        = 0x0078,
 310         [TRIMD]         = 0x007c,
 311         [RBWAR]         = 0x00c8,
 312         [RDFAR]         = 0x00cc,
 313         [TBRAR]         = 0x00d4,
 314         [TDFAR]         = 0x00d8,
 315 };
 316
 317 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
 318         SH_ETH_OFFSET_DEFAULTS,
 319
 320         [EDMR]          = 0x0000,
 321         [EDTRR]         = 0x0004,
 322         [EDRRR]         = 0x0008,
 323         [TDLAR]         = 0x000c,
 324         [RDLAR]         = 0x0010,
 325         [EESR]          = 0x0014,
 326         [EESIPR]        = 0x0018,
 327         [TRSCER]        = 0x001c,
 328         [RMFCR]         = 0x0020,
 329         [TFTR]          = 0x0024,
 330         [FDR]           = 0x0028,
 331         [RMCR]          = 0x002c,
 332         [EDOCR]         = 0x0030,
 333         [FCFTR]         = 0x0034,
 334         [RPADIR]        = 0x0038,
 335         [TRIMD]         = 0x003c,
 336         [RBWAR]         = 0x0040,
 337         [RDFAR]         = 0x0044,
 338         [TBRAR]         = 0x004c,
 339         [TDFAR]         = 0x0050,
 340
 341         [ECMR]          = 0x0160,
 342         [ECSR]          = 0x0164,
 343         [ECSIPR]        = 0x0168,
 344         [PIR]           = 0x016c,
 345         [MAHR]          = 0x0170,
 346         [MALR]          = 0x0174,
 347         [RFLR]          = 0x0178,
 348         [PSR]           = 0x017c,
 349         [TROCR]         = 0x0180,
 350         [CDCR]          = 0x0184,
 351         [LCCR]          = 0x0188,
 352         [CNDCR]         = 0x018c,
 353         [CEFCR]         = 0x0194,
 354         [FRECR]         = 0x0198,
 355         [TSFRCR]        = 0x019c,
 356         [TLFRCR]        = 0x01a0,
 357         [RFCR]          = 0x01a4,
 358         [MAFCR]         = 0x01a8,
 359         [IPGR]          = 0x01b4,
 360         [APR]           = 0x01b8,
 361         [MPR]           = 0x01bc,
 362         [TPAUSER]       = 0x01c4,
 363         [BCFR]          = 0x01cc,
 364
 365         [ARSTR]         = 0x0000,
 366         [TSU_CTRST]     = 0x0004,
 367         [TSU_FWEN0]     = 0x0010,
 368         [TSU_FWEN1]     = 0x0014,
 369         [TSU_FCM]       = 0x0018,
 370         [TSU_BSYSL0]    = 0x0020,
 371         [TSU_BSYSL1]    = 0x0024,
 372         [TSU_PRISL0]    = 0x0028,
 373         [TSU_PRISL1]    = 0x002c,
 374         [TSU_FWSL0]     = 0x0030,
 375         [TSU_FWSL1]     = 0x0034,
 376         [TSU_FWSLC]     = 0x0038,
 377         [TSU_QTAGM0]    = 0x0040,
 378         [TSU_QTAGM1]    = 0x0044,
 379         [TSU_ADQT0]     = 0x0048,
 380         [TSU_ADQT1]     = 0x004c,
 381         [TSU_FWSR]      = 0x0050,
 382         [TSU_FWINMK]    = 0x0054,
 383         [TSU_ADSBSY]    = 0x0060,
 384         [TSU_TEN]       = 0x0064,
 385         [TSU_POST1]     = 0x0070,
 386         [TSU_POST2]     = 0x0074,
 387         [TSU_POST3]     = 0x0078,
 388         [TSU_POST4]     = 0x007c,
 389
 390         [TXNLCR0]       = 0x0080,
 391         [TXALCR0]       = 0x0084,
 392         [RXNLCR0]       = 0x0088,
 393         [RXALCR0]       = 0x008c,
 394         [FWNLCR0]       = 0x0090,
 395         [FWALCR0]       = 0x0094,
 396         [TXNLCR1]       = 0x00a0,
 397         [TXALCR1]       = 0x00a0,
 398         [RXNLCR1]       = 0x00a8,
 399         [RXALCR1]       = 0x00ac,
 400         [FWNLCR1]       = 0x00b0,
 401         [FWALCR1]       = 0x00b4,
 402
 403         [TSU_ADRH0]     = 0x0100,
 404 };
 405
 406 static void sh_eth_rcv_snd_disable(struct net_device *ndev);
 407 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev);
 408
 409 static void sh_eth_write(struct net_device *ndev, u32 data, int enum_index)
 410 {
 411         struct sh_eth_private *mdp = netdev_priv(ndev);
 412         u16 offset = mdp->reg_offset[enum_index];
 413
 414         if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
 415                 return;
 416
 417         iowrite32(data, mdp->addr + offset);
 418 }
 419
 420 static u32 sh_eth_read(struct net_device *ndev, int enum_index)
 421 {
 422         struct sh_eth_private *mdp = netdev_priv(ndev);
 423         u16 offset = mdp->reg_offset[enum_index];
 424
 425         if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
 426                 return ~0U;
 427
 428         return ioread32(mdp->addr + offset);
 429 }
 430
 431 static bool sh_eth_is_gether(struct sh_eth_private *mdp)
 432 {
 433         return mdp->reg_offset == sh_eth_offset_gigabit;
 434 }
 435
 436 static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp)
 437 {
 438         return mdp->reg_offset == sh_eth_offset_fast_rz;
 439 }
 440
 441 static void sh_eth_select_mii(struct net_device *ndev)
 442 {
 443         u32 value = 0x0;
 444         struct sh_eth_private *mdp = netdev_priv(ndev);
 445
 446         switch (mdp->phy_interface) {
 447         case PHY_INTERFACE_MODE_GMII:
 448                 value = 0x2;
 449                 break;
 450         case PHY_INTERFACE_MODE_MII:
 451                 value = 0x1;
 452                 break;
 453         case PHY_INTERFACE_MODE_RMII:
 454                 value = 0x0;
 455                 break;
 456         default:
 457                 netdev_warn(ndev,
 458                             "PHY interface mode was not setup. Set to MII.\n");
 459                 value = 0x1;
 460                 break;
 461         }
 462
 463         sh_eth_write(ndev, value, RMII_MII);
 464 }
 465
 466 static void sh_eth_set_duplex(struct net_device *ndev)
 467 {
 468         struct sh_eth_private *mdp = netdev_priv(ndev);
 469
 470         if (mdp->duplex) /* Full */
 471                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
 472         else            /* Half */
 473                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
 474 }
 475
 476 static void sh_eth_chip_reset(struct net_device *ndev)
 477 {
 478         struct sh_eth_private *mdp = netdev_priv(ndev);
 479
 480         /* reset device */
 481         sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
 482         mdelay(1);
 483 }
 484
 485 static void sh_eth_set_rate_gether(struct net_device *ndev)
 486 {
 487         struct sh_eth_private *mdp = netdev_priv(ndev);
 488
 489         switch (mdp->speed) {
 490         case 10: /* 10BASE */
 491                 sh_eth_write(ndev, GECMR_10, GECMR);
 492                 break;
 493         case 100:/* 100BASE */
 494                 sh_eth_write(ndev, GECMR_100, GECMR);
 495                 break;
 496         case 1000: /* 1000BASE */
 497                 sh_eth_write(ndev, GECMR_1000, GECMR);
 498                 break;
 499         default:
 500                 break;
 501         }
 502 }
 503
 504 #ifdef CONFIG_OF
 505 /* R7S72100 */
 506 static struct sh_eth_cpu_data r7s72100_data = {
 507         .chip_reset     = sh_eth_chip_reset,
 508         .set_duplex     = sh_eth_set_duplex,
 509
 510         .register_type  = SH_ETH_REG_FAST_RZ,
 511
 512         .ecsr_value     = ECSR_ICD,
 513         .ecsipr_value   = ECSIPR_ICDIP,
 514         .eesipr_value   = 0xff7f009f,
 515
 516         .tx_check       = EESR_TC1 | EESR_FTC,
 517         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 518                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 519                           EESR_TDE | EESR_ECI,
 520         .fdr_value      = 0x0000070f,
 521
 522         .no_psr         = 1,
 523         .apr            = 1,
 524         .mpr            = 1,
 525         .tpauser        = 1,
 526         .hw_swap        = 1,
 527         .rpadir         = 1,
 528         .rpadir_value   = 2 << 16,
 529         .no_trimd       = 1,
 530         .no_ade         = 1,
 531         .hw_crc         = 1,
 532         .tsu            = 1,
 533         .shift_rd0      = 1,
 534 };
 535
 536 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
 537 {
 538         struct sh_eth_private *mdp = netdev_priv(ndev);
 539
 540         /* reset device */
 541         sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
 542         mdelay(1);
 543
 544         sh_eth_select_mii(ndev);
 545 }
 546
 547 /* R8A7740 */
 548 static struct sh_eth_cpu_data r8a7740_data = {
 549         .chip_reset     = sh_eth_chip_reset_r8a7740,
 550         .set_duplex     = sh_eth_set_duplex,
 551         .set_rate       = sh_eth_set_rate_gether,
 552
 553         .register_type  = SH_ETH_REG_GIGABIT,
 554
 555         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 556         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 557         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 558
 559         .tx_check       = EESR_TC1 | EESR_FTC,
 560         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 561                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 562                           EESR_TDE | EESR_ECI,
 563         .fdr_value      = 0x0000070f,
 564
 565         .apr            = 1,
 566         .mpr            = 1,
 567         .tpauser        = 1,
 568         .bculr          = 1,
 569         .hw_swap        = 1,
 570         .rpadir         = 1,
 571         .rpadir_value   = 2 << 16,
 572         .no_trimd       = 1,
 573         .no_ade         = 1,
 574         .tsu            = 1,
 575         .select_mii     = 1,
 576         .shift_rd0      = 1,
 577 };
 578
 579 /* There is CPU dependent code */
 580 static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
 581 {
 582         struct sh_eth_private *mdp = netdev_priv(ndev);
 583
 584         switch (mdp->speed) {
 585         case 10: /* 10BASE */
 586                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_ELB, ECMR);
 587                 break;
 588         case 100:/* 100BASE */
 589                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_ELB, ECMR);
 590                 break;
 591         default:
 592                 break;
 593         }
 594 }
 595
 596 /* R8A7778/9 */
 597 static struct sh_eth_cpu_data r8a777x_data = {
 598         .set_duplex     = sh_eth_set_duplex,
 599         .set_rate       = sh_eth_set_rate_r8a777x,
 600
 601         .register_type  = SH_ETH_REG_FAST_RCAR,
 602
 603         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 604         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 605         .eesipr_value   = 0x01ff009f,
 606
 607         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 608         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 609                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 610                           EESR_ECI,
 611         .fdr_value      = 0x00000f0f,
 612
 613         .apr            = 1,
 614         .mpr            = 1,
 615         .tpauser        = 1,
 616         .hw_swap        = 1,
 617 };
 618
 619 /* R8A7790/1 */
 620 static struct sh_eth_cpu_data r8a779x_data = {
 621         .set_duplex     = sh_eth_set_duplex,
 622         .set_rate       = sh_eth_set_rate_r8a777x,
 623
 624         .register_type  = SH_ETH_REG_FAST_RCAR,
 625
 626         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 627         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 628         .eesipr_value   = 0x01ff009f,
 629
 630         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 631         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 632                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 633                           EESR_ECI,
 634         .fdr_value      = 0x00000f0f,
 635
 636         .trscer_err_mask = DESC_I_RINT8,
 637
 638         .apr            = 1,
 639         .mpr            = 1,
 640         .tpauser        = 1,
 641         .hw_swap        = 1,
 642         .rmiimode       = 1,
 643 };
 644 #endif /* CONFIG_OF */
 645
 646 static void sh_eth_set_rate_sh7724(struct net_device *ndev)
 647 {
 648         struct sh_eth_private *mdp = netdev_priv(ndev);
 649
 650         switch (mdp->speed) {
 651         case 10: /* 10BASE */
 652                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR);
 653                 break;
 654         case 100:/* 100BASE */
 655                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR);
 656                 break;
 657         default:
 658                 break;
 659         }
 660 }
 661
 662 /* SH7724 */
 663 static struct sh_eth_cpu_data sh7724_data = {
 664         .set_duplex     = sh_eth_set_duplex,
 665         .set_rate       = sh_eth_set_rate_sh7724,
 666
 667         .register_type  = SH_ETH_REG_FAST_SH4,
 668
 669         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 670         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 671         .eesipr_value   = 0x01ff009f,
 672
 673         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 674         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 675                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 676                           EESR_ECI,
 677
 678         .apr            = 1,
 679         .mpr            = 1,
 680         .tpauser        = 1,
 681         .hw_swap        = 1,
 682         .rpadir         = 1,
 683         .rpadir_value   = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
 684 };
 685
 686 static void sh_eth_set_rate_sh7757(struct net_device *ndev)
 687 {
 688         struct sh_eth_private *mdp = netdev_priv(ndev);
 689
 690         switch (mdp->speed) {
 691         case 10: /* 10BASE */
 692                 sh_eth_write(ndev, 0, RTRATE);
 693                 break;
 694         case 100:/* 100BASE */
 695                 sh_eth_write(ndev, 1, RTRATE);
 696                 break;
 697         default:
 698                 break;
 699         }
 700 }
 701
 702 /* SH7757 */
 703 static struct sh_eth_cpu_data sh7757_data = {
 704         .set_duplex     = sh_eth_set_duplex,
 705         .set_rate       = sh_eth_set_rate_sh7757,
 706
 707         .register_type  = SH_ETH_REG_FAST_SH4,
 708
 709         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 710
 711         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 712         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 713                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 714                           EESR_ECI,
 715
 716         .irq_flags      = IRQF_SHARED,
 717         .apr            = 1,
 718         .mpr            = 1,
 719         .tpauser        = 1,
 720         .hw_swap        = 1,
 721         .no_ade         = 1,
 722         .rpadir         = 1,
 723         .rpadir_value   = 2 << 16,
 724         .rtrate         = 1,
 725 };
 726
 727 #define SH_GIGA_ETH_BASE        0xfee00000UL
 728 #define GIGA_MALR(port)         (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
 729 #define GIGA_MAHR(port)         (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
 730 static void sh_eth_chip_reset_giga(struct net_device *ndev)
 731 {
 732         int i;
 733         u32 mahr[2], malr[2];
 734
 735         /* save MAHR and MALR */
 736         for (i = 0; i < 2; i++) {
 737                 malr[i] = ioread32((void *)GIGA_MALR(i));
 738                 mahr[i] = ioread32((void *)GIGA_MAHR(i));
 739         }
 740
 741         /* reset device */
 742         iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800));
 743         mdelay(1);
 744
 745         /* restore MAHR and MALR */
 746         for (i = 0; i < 2; i++) {
 747                 iowrite32(malr[i], (void *)GIGA_MALR(i));
 748                 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
 749         }
 750 }
 751
 752 static void sh_eth_set_rate_giga(struct net_device *ndev)
 753 {
 754         struct sh_eth_private *mdp = netdev_priv(ndev);
 755
 756         switch (mdp->speed) {
 757         case 10: /* 10BASE */
 758                 sh_eth_write(ndev, 0x00000000, GECMR);
 759                 break;
 760         case 100:/* 100BASE */
 761                 sh_eth_write(ndev, 0x00000010, GECMR);
 762                 break;
 763         case 1000: /* 1000BASE */
 764                 sh_eth_write(ndev, 0x00000020, GECMR);
 765                 break;
 766         default:
 767                 break;
 768         }
 769 }
 770
 771 /* SH7757(GETHERC) */
 772 static struct sh_eth_cpu_data sh7757_data_giga = {
 773         .chip_reset     = sh_eth_chip_reset_giga,
 774         .set_duplex     = sh_eth_set_duplex,
 775         .set_rate       = sh_eth_set_rate_giga,
 776
 777         .register_type  = SH_ETH_REG_GIGABIT,
 778
 779         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 780         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 781         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 782
 783         .tx_check       = EESR_TC1 | EESR_FTC,
 784         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 785                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 786                           EESR_TDE | EESR_ECI,
 787         .fdr_value      = 0x0000072f,
 788
 789         .irq_flags      = IRQF_SHARED,
 790         .apr            = 1,
 791         .mpr            = 1,
 792         .tpauser        = 1,
 793         .bculr          = 1,
 794         .hw_swap        = 1,
 795         .rpadir         = 1,
 796         .rpadir_value   = 2 << 16,
 797         .no_trimd       = 1,
 798         .no_ade         = 1,
 799         .tsu            = 1,
 800 };
 801
 802 /* SH7734 */
 803 static struct sh_eth_cpu_data sh7734_data = {
 804         .chip_reset     = sh_eth_chip_reset,
 805         .set_duplex     = sh_eth_set_duplex,
 806         .set_rate       = sh_eth_set_rate_gether,
 807
 808         .register_type  = SH_ETH_REG_GIGABIT,
 809
 810         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 811         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 812         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 813
 814         .tx_check       = EESR_TC1 | EESR_FTC,
 815         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 816                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 817                           EESR_TDE | EESR_ECI,
 818
 819         .apr            = 1,
 820         .mpr            = 1,
 821         .tpauser        = 1,
 822         .bculr          = 1,
 823         .hw_swap        = 1,
 824         .no_trimd       = 1,
 825         .no_ade         = 1,
 826         .tsu            = 1,
 827         .hw_crc         = 1,
 828         .select_mii     = 1,
 829 };
 830
 831 /* SH7763 */
 832 static struct sh_eth_cpu_data sh7763_data = {
 833         .chip_reset     = sh_eth_chip_reset,
 834         .set_duplex     = sh_eth_set_duplex,
 835         .set_rate       = sh_eth_set_rate_gether,
 836
 837         .register_type  = SH_ETH_REG_GIGABIT,
 838
 839         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 840         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 841         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 842
 843         .tx_check       = EESR_TC1 | EESR_FTC,
 844         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 845                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 846                           EESR_ECI,
 847
 848         .apr            = 1,
 849         .mpr            = 1,
 850         .tpauser        = 1,
 851         .bculr          = 1,
 852         .hw_swap        = 1,
 853         .no_trimd       = 1,
 854         .no_ade         = 1,
 855         .tsu            = 1,
 856         .irq_flags      = IRQF_SHARED,
 857 };
 858
 859 static struct sh_eth_cpu_data sh7619_data = {
 860         .register_type  = SH_ETH_REG_FAST_SH3_SH2,
 861
 862         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 863
 864         .apr            = 1,
 865         .mpr            = 1,
 866         .tpauser        = 1,
 867         .hw_swap        = 1,
 868 };
 869
 870 static struct sh_eth_cpu_data sh771x_data = {
 871         .register_type  = SH_ETH_REG_FAST_SH3_SH2,
 872
 873         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 874         .tsu            = 1,
 875 };
 876
 877 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
 878 {
 879         if (!cd->ecsr_value)
 880                 cd->ecsr_value = DEFAULT_ECSR_INIT;
 881
 882         if (!cd->ecsipr_value)
 883                 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
 884
 885         if (!cd->fcftr_value)
 886                 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
 887                                   DEFAULT_FIFO_F_D_RFD;
 888
 889         if (!cd->fdr_value)
 890                 cd->fdr_value = DEFAULT_FDR_INIT;
 891
 892         if (!cd->tx_check)
 893                 cd->tx_check = DEFAULT_TX_CHECK;
 894
 895         if (!cd->eesr_err_check)
 896                 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
 897
 898         if (!cd->trscer_err_mask)
 899                 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK;
 900 }
 901
 902 static int sh_eth_check_reset(struct net_device *ndev)
 903 {
 904         int ret = 0;
 905         int cnt = 100;
 906
 907         while (cnt > 0) {
 908                 if (!(sh_eth_read(ndev, EDMR) & 0x3))
 909                         break;
 910                 mdelay(1);
 911                 cnt--;
 912         }
 913         if (cnt <= 0) {
 914                 netdev_err(ndev, "Device reset failed\n");
 915                 ret = -ETIMEDOUT;
 916         }
 917         return ret;
 918 }
 919
 920 static int sh_eth_reset(struct net_device *ndev)
 921 {
 922         struct sh_eth_private *mdp = netdev_priv(ndev);
 923         int ret = 0;
 924
 925         if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) {
 926                 sh_eth_write(ndev, EDSR_ENALL, EDSR);
 927                 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
 928                              EDMR);
 929
 930                 ret = sh_eth_check_reset(ndev);
 931                 if (ret)
 932                         return ret;
 933
 934                 /* Table Init */
 935                 sh_eth_write(ndev, 0x0, TDLAR);
 936                 sh_eth_write(ndev, 0x0, TDFAR);
 937                 sh_eth_write(ndev, 0x0, TDFXR);
 938                 sh_eth_write(ndev, 0x0, TDFFR);
 939                 sh_eth_write(ndev, 0x0, RDLAR);
 940                 sh_eth_write(ndev, 0x0, RDFAR);
 941                 sh_eth_write(ndev, 0x0, RDFXR);
 942                 sh_eth_write(ndev, 0x0, RDFFR);
 943
 944                 /* Reset HW CRC register */
 945                 if (mdp->cd->hw_crc)
 946                         sh_eth_write(ndev, 0x0, CSMR);
 947
 948                 /* Select MII mode */
 949                 if (mdp->cd->select_mii)
 950                         sh_eth_select_mii(ndev);
 951         } else {
 952                 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,
 953                              EDMR);
 954                 mdelay(3);
 955                 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
 956                              EDMR);
 957         }
 958
 959         return ret;
 960 }
 961
 962 static void sh_eth_set_receive_align(struct sk_buff *skb)
 963 {
 964         uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1);
 965
 966         if (reserve)
 967                 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve);
 968 }
 969
 970
 971 /* CPU <-> EDMAC endian convert */
 972 static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
 973 {
 974         switch (mdp->edmac_endian) {
 975         case EDMAC_LITTLE_ENDIAN:
 976                 return cpu_to_le32(x);
 977         case EDMAC_BIG_ENDIAN:
 978                 return cpu_to_be32(x);
 979         }
 980         return x;
 981 }
 982
 983 static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
 984 {
 985         switch (mdp->edmac_endian) {
 986         case EDMAC_LITTLE_ENDIAN:
 987                 return le32_to_cpu(x);
 988         case EDMAC_BIG_ENDIAN:
 989                 return be32_to_cpu(x);
 990         }
 991         return x;
 992 }
 993
 994 /* Program the hardware MAC address from dev->dev_addr. */
 995 static void update_mac_address(struct net_device *ndev)
 996 {
 997         sh_eth_write(ndev,
 998                      (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
 999                      (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
1000         sh_eth_write(ndev,
1001                      (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
1002 }
1003
1004 /* Get MAC address from SuperH MAC address register
1005  *
1006  * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
1007  * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
1008  * When you want use this device, you must set MAC address in bootloader.
1009  *
1010  */
1011 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
1012 {
1013         if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
1014                 memcpy(ndev->dev_addr, mac, ETH_ALEN);
1015         } else {
1016                 u32 mahr = sh_eth_read(ndev, MAHR);
1017                 u32 malr = sh_eth_read(ndev, MALR);
1018
1019                 ndev->dev_addr[0] = (mahr >> 24) & 0xFF;
1020                 ndev->dev_addr[1] = (mahr >> 16) & 0xFF;
1021                 ndev->dev_addr[2] = (mahr >>  8) & 0xFF;
1022                 ndev->dev_addr[3] = (mahr >>  0) & 0xFF;
1023                 ndev->dev_addr[4] = (malr >>  8) & 0xFF;
1024                 ndev->dev_addr[5] = (malr >>  0) & 0xFF;
1025         }
1026 }
1027
1028 static u32 sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
1029 {
1030         if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp))
1031                 return EDTRR_TRNS_GETHER;
1032         else
1033                 return EDTRR_TRNS_ETHER;
1034 }
1035
1036 struct bb_info {
1037         void (*set_gate)(void *addr);
1038         struct mdiobb_ctrl ctrl;
1039         void *addr;
1040 };
1041
1042 static void sh_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
1043 {
1044         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1045         u32 pir;
1046
1047         if (bitbang->set_gate)
1048                 bitbang->set_gate(bitbang->addr);
1049
1050         pir = ioread32(bitbang->addr);
1051         if (set)
1052                 pir |=  mask;
1053         else
1054                 pir &= ~mask;
1055         iowrite32(pir, bitbang->addr);
1056 }
1057
1058 /* Data I/O pin control */
1059 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1060 {
1061         sh_mdio_ctrl(ctrl, PIR_MMD, bit);
1062 }
1063
1064 /* Set bit data*/
1065 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1066 {
1067         sh_mdio_ctrl(ctrl, PIR_MDO, bit);
1068 }
1069
1070 /* Get bit data*/
1071 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1072 {
1073         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1074
1075         if (bitbang->set_gate)
1076                 bitbang->set_gate(bitbang->addr);
1077
1078         return (ioread32(bitbang->addr) & PIR_MDI) != 0;
1079 }
1080
1081 /* MDC pin control */
1082 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1083 {
1084         sh_mdio_ctrl(ctrl, PIR_MDC, bit);
1085 }
1086
1087 /* mdio bus control struct */
1088 static struct mdiobb_ops bb_ops = {
1089         .owner = THIS_MODULE,
1090         .set_mdc = sh_mdc_ctrl,
1091         .set_mdio_dir = sh_mmd_ctrl,
1092         .set_mdio_data = sh_set_mdio,
1093         .get_mdio_data = sh_get_mdio,
1094 };
1095
1096 /* free skb and descriptor buffer */
1097 static void sh_eth_ring_free(struct net_device *ndev)
1098 {
1099         struct sh_eth_private *mdp = netdev_priv(ndev);
1100         int ringsize, i;
1101
1102         /* Free Rx skb ringbuffer */
1103         if (mdp->rx_skbuff) {
1104                 for (i = 0; i < mdp->num_rx_ring; i++)
1105                         dev_kfree_skb(mdp->rx_skbuff[i]);
1106         }
1107         kfree(mdp->rx_skbuff);
1108         mdp->rx_skbuff = NULL;
1109
1110         /* Free Tx skb ringbuffer */
1111         if (mdp->tx_skbuff) {
1112                 for (i = 0; i < mdp->num_tx_ring; i++)
1113                         dev_kfree_skb(mdp->tx_skbuff[i]);
1114         }
1115         kfree(mdp->tx_skbuff);
1116         mdp->tx_skbuff = NULL;
1117
1118         if (mdp->rx_ring) {
1119                 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1120                 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1121                                   mdp->rx_desc_dma);
1122                 mdp->rx_ring = NULL;
1123         }
1124
1125         if (mdp->tx_ring) {
1126                 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1127                 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1128                                   mdp->tx_desc_dma);
1129                 mdp->tx_ring = NULL;
1130         }
1131 }
1132
1133 /* format skb and descriptor buffer */
1134 static void sh_eth_ring_format(struct net_device *ndev)
1135 {
1136         struct sh_eth_private *mdp = netdev_priv(ndev);
1137         int i;
1138         struct sk_buff *skb;
1139         struct sh_eth_rxdesc *rxdesc = NULL;
1140         struct sh_eth_txdesc *txdesc = NULL;
1141         int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1142         int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
1143         int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1144         dma_addr_t dma_addr;
1145         u32 buf_len;
1146
1147         mdp->cur_rx = 0;
1148         mdp->cur_tx = 0;
1149         mdp->dirty_rx = 0;
1150         mdp->dirty_tx = 0;
1151
1152         memset(mdp->rx_ring, 0, rx_ringsize);
1153
1154         /* build Rx ring buffer */
1155         for (i = 0; i < mdp->num_rx_ring; i++) {
1156                 /* skb */
1157                 mdp->rx_skbuff[i] = NULL;
1158                 skb = netdev_alloc_skb(ndev, skbuff_size);
1159                 if (skb == NULL)
1160                         break;
1161                 sh_eth_set_receive_align(skb);
1162
1163                 /* RX descriptor */
1164                 rxdesc = &mdp->rx_ring[i];
1165                 /* The size of the buffer is a multiple of 32 bytes. */
1166                 buf_len = ALIGN(mdp->rx_buf_sz, 32);
1167                 rxdesc->len = cpu_to_edmac(mdp, buf_len << 16);
1168                 dma_addr = dma_map_single(&ndev->dev, skb->data, buf_len,
1169                                           DMA_FROM_DEVICE);
1170                 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1171                         kfree_skb(skb);
1172                         break;
1173                 }
1174                 mdp->rx_skbuff[i] = skb;
1175                 rxdesc->addr = cpu_to_edmac(mdp, dma_addr);
1176                 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1177
1178                 /* Rx descriptor address set */
1179                 if (i == 0) {
1180                         sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
1181                         if (sh_eth_is_gether(mdp) ||
1182                             sh_eth_is_rz_fast_ether(mdp))
1183                                 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
1184                 }
1185         }
1186
1187         mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
1188
1189         /* Mark the last entry as wrapping the ring. */
1190         rxdesc->status |= cpu_to_edmac(mdp, RD_RDLE);
1191
1192         memset(mdp->tx_ring, 0, tx_ringsize);
1193
1194         /* build Tx ring buffer */
1195         for (i = 0; i < mdp->num_tx_ring; i++) {
1196                 mdp->tx_skbuff[i] = NULL;
1197                 txdesc = &mdp->tx_ring[i];
1198                 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1199                 txdesc->len = cpu_to_edmac(mdp, 0);
1200                 if (i == 0) {
1201                         /* Tx descriptor address set */
1202                         sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
1203                         if (sh_eth_is_gether(mdp) ||
1204                             sh_eth_is_rz_fast_ether(mdp))
1205                                 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
1206                 }
1207         }
1208
1209         txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1210 }
1211
1212 /* Get skb and descriptor buffer */
1213 static int sh_eth_ring_init(struct net_device *ndev)
1214 {
1215         struct sh_eth_private *mdp = netdev_priv(ndev);
1216         int rx_ringsize, tx_ringsize;
1217
1218         /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1219          * card needs room to do 8 byte alignment, +2 so we can reserve
1220          * the first 2 bytes, and +16 gets room for the status word from the
1221          * card.
1222          */
1223         mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1224                           (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
1225         if (mdp->cd->rpadir)
1226                 mdp->rx_buf_sz += NET_IP_ALIGN;
1227
1228         /* Allocate RX and TX skb rings */
1229         mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff),
1230                                  GFP_KERNEL);
1231         if (!mdp->rx_skbuff)
1232                 return -ENOMEM;
1233
1234         mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff),
1235                                  GFP_KERNEL);
1236         if (!mdp->tx_skbuff)
1237                 goto ring_free;
1238
1239         /* Allocate all Rx descriptors. */
1240         rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1241         mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
1242                                           GFP_KERNEL);
1243         if (!mdp->rx_ring)
1244                 goto ring_free;
1245
1246         mdp->dirty_rx = 0;
1247
1248         /* Allocate all Tx descriptors. */
1249         tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1250         mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
1251                                           GFP_KERNEL);
1252         if (!mdp->tx_ring)
1253                 goto ring_free;
1254         return 0;
1255
1256 ring_free:
1257         /* Free Rx and Tx skb ring buffer and DMA buffer */
1258         sh_eth_ring_free(ndev);
1259
1260         return -ENOMEM;
1261 }
1262
1263 static int sh_eth_dev_init(struct net_device *ndev, bool start)
1264 {
1265         int ret = 0;
1266         struct sh_eth_private *mdp = netdev_priv(ndev);
1267         u32 val;
1268
1269         /* Soft Reset */
1270         ret = sh_eth_reset(ndev);
1271         if (ret)
1272                 return ret;
1273
1274         if (mdp->cd->rmiimode)
1275                 sh_eth_write(ndev, 0x1, RMIIMODE);
1276
1277         /* Descriptor format */
1278         sh_eth_ring_format(ndev);
1279         if (mdp->cd->rpadir)
1280                 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
1281
1282         /* all sh_eth int mask */
1283         sh_eth_write(ndev, 0, EESIPR);
1284
1285 #if defined(__LITTLE_ENDIAN)
1286         if (mdp->cd->hw_swap)
1287                 sh_eth_write(ndev, EDMR_EL, EDMR);
1288         else
1289 #endif
1290                 sh_eth_write(ndev, 0, EDMR);
1291
1292         /* FIFO size set */
1293         sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1294         sh_eth_write(ndev, 0, TFTR);
1295
1296         /* Frame recv control (enable multiple-packets per rx irq) */
1297         sh_eth_write(ndev, RMCR_RNC, RMCR);
1298
1299         sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);
1300
1301         if (mdp->cd->bculr)
1302                 sh_eth_write(ndev, 0x800, BCULR);       /* Burst sycle set */
1303
1304         sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
1305
1306         if (!mdp->cd->no_trimd)
1307                 sh_eth_write(ndev, 0, TRIMD);
1308
1309         /* Recv frame limit set register */
1310         sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1311                      RFLR);
1312
1313         sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
1314         if (start) {
1315                 mdp->irq_enabled = true;
1316                 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1317         }
1318
1319         /* PAUSE Prohibition */
1320         val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
1321                 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
1322
1323         sh_eth_write(ndev, val, ECMR);
1324
1325         if (mdp->cd->set_rate)
1326                 mdp->cd->set_rate(ndev);
1327
1328         /* E-MAC Status Register clear */
1329         sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1330
1331         /* E-MAC Interrupt Enable register */
1332         if (start)
1333                 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1334
1335         /* Set MAC address */
1336         update_mac_address(ndev);
1337
1338         /* mask reset */
1339         if (mdp->cd->apr)
1340                 sh_eth_write(ndev, APR_AP, APR);
1341         if (mdp->cd->mpr)
1342                 sh_eth_write(ndev, MPR_MP, MPR);
1343         if (mdp->cd->tpauser)
1344                 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1345
1346         if (start) {
1347                 /* Setting the Rx mode will start the Rx process. */
1348                 sh_eth_write(ndev, EDRRR_R, EDRRR);
1349
1350                 netif_start_queue(ndev);
1351         }
1352
1353         return ret;
1354 }
1355
1356 static void sh_eth_dev_exit(struct net_device *ndev)
1357 {
1358         struct sh_eth_private *mdp = netdev_priv(ndev);
1359         int i;
1360
1361         /* Deactivate all TX descriptors, so DMA should stop at next
1362          * packet boundary if it's currently running
1363          */
1364         for (i = 0; i < mdp->num_tx_ring; i++)
1365                 mdp->tx_ring[i].status &= ~cpu_to_edmac(mdp, TD_TACT);
1366
1367         /* Disable TX FIFO egress to MAC */
1368         sh_eth_rcv_snd_disable(ndev);
1369
1370         /* Stop RX DMA at next packet boundary */
1371         sh_eth_write(ndev, 0, EDRRR);
1372
1373         /* Aside from TX DMA, we can't tell when the hardware is
1374          * really stopped, so we need to reset to make sure.
1375          * Before doing that, wait for long enough to *probably*
1376          * finish transmitting the last packet and poll stats.
1377          */
1378         msleep(2); /* max frame time at 10 Mbps < 1250 us */
1379         sh_eth_get_stats(ndev);
1380         sh_eth_reset(ndev);
1381
1382         /* Set MAC address again */
1383         update_mac_address(ndev);
1384 }
1385
1386 /* free Tx skb function */
1387 static int sh_eth_txfree(struct net_device *ndev)
1388 {
1389         struct sh_eth_private *mdp = netdev_priv(ndev);
1390         struct sh_eth_txdesc *txdesc;
1391         int free_num = 0;
1392         int entry = 0;
1393
1394         for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1395                 entry = mdp->dirty_tx % mdp->num_tx_ring;
1396                 txdesc = &mdp->tx_ring[entry];
1397                 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
1398                         break;
1399                 /* TACT bit must be checked before all the following reads */
1400                 dma_rmb();
1401                 netif_info(mdp, tx_done, ndev,
1402                            "tx entry %d status 0x%08x\n",
1403                            entry, edmac_to_cpu(mdp, txdesc->status));
1404                 /* Free the original skb. */
1405                 if (mdp->tx_skbuff[entry]) {
1406                         dma_unmap_single(&ndev->dev,
1407                                          edmac_to_cpu(mdp, txdesc->addr),
1408                                          edmac_to_cpu(mdp, txdesc->len) >> 16,
1409                                          DMA_TO_DEVICE);
1410                         dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1411                         mdp->tx_skbuff[entry] = NULL;
1412                         free_num++;
1413                 }
1414                 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1415                 if (entry >= mdp->num_tx_ring - 1)
1416                         txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1417
1418                 ndev->stats.tx_packets++;
1419                 ndev->stats.tx_bytes += edmac_to_cpu(mdp, txdesc->len) >> 16;
1420         }
1421         return free_num;
1422 }
1423
1424 /* Packet receive function */
1425 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
1426 {
1427         struct sh_eth_private *mdp = netdev_priv(ndev);
1428         struct sh_eth_rxdesc *rxdesc;
1429
1430         int entry = mdp->cur_rx % mdp->num_rx_ring;
1431         int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
1432         int limit;
1433         struct sk_buff *skb;
1434         u16 pkt_len = 0;
1435         u32 desc_status;
1436         int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1437         dma_addr_t dma_addr;
1438         u32 buf_len;
1439
1440         boguscnt = min(boguscnt, *quota);
1441         limit = boguscnt;
1442         rxdesc = &mdp->rx_ring[entry];
1443         while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
1444                 /* RACT bit must be checked before all the following reads */
1445                 dma_rmb();
1446                 desc_status = edmac_to_cpu(mdp, rxdesc->status);
1447                 pkt_len = edmac_to_cpu(mdp, rxdesc->len) & RD_RFL;
1448
1449                 if (--boguscnt < 0)
1450                         break;
1451
1452                 netif_info(mdp, rx_status, ndev,
1453                            "rx entry %d status 0x%08x len %d\n",
1454                            entry, desc_status, pkt_len);
1455
1456                 if (!(desc_status & RDFEND))
1457                         ndev->stats.rx_length_errors++;
1458
1459                 /* In case of almost all GETHER/ETHERs, the Receive Frame State
1460                  * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1461                  * bit 0. However, in case of the R8A7740 and R7S72100
1462                  * the RFS bits are from bit 25 to bit 16. So, the
1463                  * driver needs right shifting by 16.
1464                  */
1465                 if (mdp->cd->shift_rd0)
1466                         desc_status >>= 16;
1467
1468                 skb = mdp->rx_skbuff[entry];
1469                 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1470                                    RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1471                         ndev->stats.rx_errors++;
1472                         if (desc_status & RD_RFS1)
1473                                 ndev->stats.rx_crc_errors++;
1474                         if (desc_status & RD_RFS2)
1475                                 ndev->stats.rx_frame_errors++;
1476                         if (desc_status & RD_RFS3)
1477                                 ndev->stats.rx_length_errors++;
1478                         if (desc_status & RD_RFS4)
1479                                 ndev->stats.rx_length_errors++;
1480                         if (desc_status & RD_RFS6)
1481                                 ndev->stats.rx_missed_errors++;
1482                         if (desc_status & RD_RFS10)
1483                                 ndev->stats.rx_over_errors++;
1484                 } else  if (skb) {
1485                         dma_addr = edmac_to_cpu(mdp, rxdesc->addr);
1486                         if (!mdp->cd->hw_swap)
1487                                 sh_eth_soft_swap(
1488                                         phys_to_virt(ALIGN(dma_addr, 4)),
1489                                         pkt_len + 2);
1490                         mdp->rx_skbuff[entry] = NULL;
1491                         if (mdp->cd->rpadir)
1492                                 skb_reserve(skb, NET_IP_ALIGN);
1493                         dma_unmap_single(&ndev->dev, dma_addr,
1494                                          ALIGN(mdp->rx_buf_sz, 32),
1495                                          DMA_FROM_DEVICE);
1496                         skb_put(skb, pkt_len);
1497                         skb->protocol = eth_type_trans(skb, ndev);
1498                         netif_receive_skb(skb);
1499                         ndev->stats.rx_packets++;
1500                         ndev->stats.rx_bytes += pkt_len;
1501                         if (desc_status & RD_RFS8)
1502                                 ndev->stats.multicast++;
1503                 }
1504                 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
1505                 rxdesc = &mdp->rx_ring[entry];
1506         }
1507
1508         /* Refill the Rx ring buffers. */
1509         for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1510                 entry = mdp->dirty_rx % mdp->num_rx_ring;
1511                 rxdesc = &mdp->rx_ring[entry];
1512                 /* The size of the buffer is 32 byte boundary. */
1513                 buf_len = ALIGN(mdp->rx_buf_sz, 32);
1514                 rxdesc->len = cpu_to_edmac(mdp, buf_len << 16);
1515
1516                 if (mdp->rx_skbuff[entry] == NULL) {
1517                         skb = netdev_alloc_skb(ndev, skbuff_size);
1518                         if (skb == NULL)
1519                                 break;  /* Better luck next round. */
1520                         sh_eth_set_receive_align(skb);
1521                         dma_addr = dma_map_single(&ndev->dev, skb->data,
1522                                                   buf_len, DMA_FROM_DEVICE);
1523                         if (dma_mapping_error(&ndev->dev, dma_addr)) {
1524                                 kfree_skb(skb);
1525                                 break;
1526                         }
1527                         mdp->rx_skbuff[entry] = skb;
1528
1529                         skb_checksum_none_assert(skb);
1530                         rxdesc->addr = cpu_to_edmac(mdp, dma_addr);
1531                 }
1532                 dma_wmb(); /* RACT bit must be set after all the above writes */
1533                 if (entry >= mdp->num_rx_ring - 1)
1534                         rxdesc->status |=
1535                                 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDLE);
1536                 else
1537                         rxdesc->status |=
1538                                 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1539         }
1540
1541         /* Restart Rx engine if stopped. */
1542         /* If we don't need to check status, don't. -KDU */
1543         if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1544                 /* fix the values for the next receiving if RDE is set */
1545                 if (intr_status & EESR_RDE &&
1546                     mdp->reg_offset[RDFAR] != SH_ETH_OFFSET_INVALID) {
1547                         u32 count = (sh_eth_read(ndev, RDFAR) -
1548                                      sh_eth_read(ndev, RDLAR)) >> 4;
1549
1550                         mdp->cur_rx = count;
1551                         mdp->dirty_rx = count;
1552                 }
1553                 sh_eth_write(ndev, EDRRR_R, EDRRR);
1554         }
1555
1556         *quota -= limit - boguscnt - 1;
1557
1558         return *quota <= 0;
1559 }
1560
1561 static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1562 {
1563         /* disable tx and rx */
1564         sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
1565                 ~(ECMR_RE | ECMR_TE), ECMR);
1566 }
1567
1568 static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1569 {
1570         /* enable tx and rx */
1571         sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
1572                 (ECMR_RE | ECMR_TE), ECMR);
1573 }
1574
1575 /* error control function */
1576 static void sh_eth_error(struct net_device *ndev, u32 intr_status)
1577 {
1578         struct sh_eth_private *mdp = netdev_priv(ndev);
1579         u32 felic_stat;
1580         u32 link_stat;
1581         u32 mask;
1582
1583         if (intr_status & EESR_ECI) {
1584                 felic_stat = sh_eth_read(ndev, ECSR);
1585                 sh_eth_write(ndev, felic_stat, ECSR);   /* clear int */
1586                 if (felic_stat & ECSR_ICD)
1587                         ndev->stats.tx_carrier_errors++;
1588                 if (felic_stat & ECSR_LCHNG) {
1589                         /* Link Changed */
1590                         if (mdp->cd->no_psr || mdp->no_ether_link) {
1591                                 goto ignore_link;
1592                         } else {
1593                                 link_stat = (sh_eth_read(ndev, PSR));
1594                                 if (mdp->ether_link_active_low)
1595                                         link_stat = ~link_stat;
1596                         }
1597                         if (!(link_stat & PHY_ST_LINK)) {
1598                                 sh_eth_rcv_snd_disable(ndev);
1599                         } else {
1600                                 /* Link Up */
1601                                 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
1602                                                    ~DMAC_M_ECI, EESIPR);
1603                                 /* clear int */
1604                                 sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
1605                                              ECSR);
1606                                 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
1607                                                    DMAC_M_ECI, EESIPR);
1608                                 /* enable tx and rx */
1609                                 sh_eth_rcv_snd_enable(ndev);
1610                         }
1611                 }
1612         }
1613
1614 ignore_link:
1615         if (intr_status & EESR_TWB) {
1616                 /* Unused write back interrupt */
1617                 if (intr_status & EESR_TABT) {  /* Transmit Abort int */
1618                         ndev->stats.tx_aborted_errors++;
1619                         netif_err(mdp, tx_err, ndev, "Transmit Abort\n");
1620                 }
1621         }
1622
1623         if (intr_status & EESR_RABT) {
1624                 /* Receive Abort int */
1625                 if (intr_status & EESR_RFRMER) {
1626                         /* Receive Frame Overflow int */
1627                         ndev->stats.rx_frame_errors++;
1628                 }
1629         }
1630
1631         if (intr_status & EESR_TDE) {
1632                 /* Transmit Descriptor Empty int */
1633                 ndev->stats.tx_fifo_errors++;
1634                 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n");
1635         }
1636
1637         if (intr_status & EESR_TFE) {
1638                 /* FIFO under flow */
1639                 ndev->stats.tx_fifo_errors++;
1640                 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n");
1641         }
1642
1643         if (intr_status & EESR_RDE) {
1644                 /* Receive Descriptor Empty int */
1645                 ndev->stats.rx_over_errors++;
1646         }
1647
1648         if (intr_status & EESR_RFE) {
1649                 /* Receive FIFO Overflow int */
1650                 ndev->stats.rx_fifo_errors++;
1651         }
1652
1653         if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1654                 /* Address Error */
1655                 ndev->stats.tx_fifo_errors++;
1656                 netif_err(mdp, tx_err, ndev, "Address Error\n");
1657         }
1658
1659         mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1660         if (mdp->cd->no_ade)
1661                 mask &= ~EESR_ADE;
1662         if (intr_status & mask) {
1663                 /* Tx error */
1664                 u32 edtrr = sh_eth_read(ndev, EDTRR);
1665
1666                 /* dmesg */
1667                 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1668                            intr_status, mdp->cur_tx, mdp->dirty_tx,
1669                            (u32)ndev->state, edtrr);
1670                 /* dirty buffer free */
1671                 sh_eth_txfree(ndev);
1672
1673                 /* SH7712 BUG */
1674                 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
1675                         /* tx dma start */
1676                         sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1677                 }
1678                 /* wakeup */
1679                 netif_wake_queue(ndev);
1680         }
1681 }
1682
1683 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1684 {
1685         struct net_device *ndev = netdev;
1686         struct sh_eth_private *mdp = netdev_priv(ndev);
1687         struct sh_eth_cpu_data *cd = mdp->cd;
1688         irqreturn_t ret = IRQ_NONE;
1689         u32 intr_status, intr_enable;
1690
1691         spin_lock(&mdp->lock);
1692
1693         /* Get interrupt status */
1694         intr_status = sh_eth_read(ndev, EESR);
1695         /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1696          * enabled since it's the one that  comes thru regardless of the mask,
1697          * and we need to fully handle it in sh_eth_error() in order to quench
1698          * it as it doesn't get cleared by just writing 1 to the ECI bit...
1699          */
1700         intr_enable = sh_eth_read(ndev, EESIPR);
1701         intr_status &= intr_enable | DMAC_M_ECI;
1702         if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check))
1703                 ret = IRQ_HANDLED;
1704         else
1705                 goto out;
1706
1707         if (!likely(mdp->irq_enabled)) {
1708                 sh_eth_write(ndev, 0, EESIPR);
1709                 goto out;
1710         }
1711
1712         if (intr_status & EESR_RX_CHECK) {
1713                 if (napi_schedule_prep(&mdp->napi)) {
1714                         /* Mask Rx interrupts */
1715                         sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1716                                      EESIPR);
1717                         __napi_schedule(&mdp->napi);
1718                 } else {
1719                         netdev_warn(ndev,
1720                                     "ignoring interrupt, status 0x%08x, mask 0x%08x.\n",
1721                                     intr_status, intr_enable);
1722                 }
1723         }
1724
1725         /* Tx Check */
1726         if (intr_status & cd->tx_check) {
1727                 /* Clear Tx interrupts */
1728                 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1729
1730                 sh_eth_txfree(ndev);
1731                 netif_wake_queue(ndev);
1732         }
1733
1734         if (intr_status & cd->eesr_err_check) {
1735                 /* Clear error interrupts */
1736                 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1737
1738                 sh_eth_error(ndev, intr_status);
1739         }
1740
1741 out:
1742         spin_unlock(&mdp->lock);
1743
1744         return ret;
1745 }
1746
1747 static int sh_eth_poll(struct napi_struct *napi, int budget)
1748 {
1749         struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1750                                                   napi);
1751         struct net_device *ndev = napi->dev;
1752         int quota = budget;
1753         u32 intr_status;
1754
1755         for (;;) {
1756                 intr_status = sh_eth_read(ndev, EESR);
1757                 if (!(intr_status & EESR_RX_CHECK))
1758                         break;
1759                 /* Clear Rx interrupts */
1760                 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1761
1762                 if (sh_eth_rx(ndev, intr_status, &quota))
1763                         goto out;
1764         }
1765
1766         napi_complete(napi);
1767
1768         /* Reenable Rx interrupts */
1769         if (mdp->irq_enabled)
1770                 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1771 out:
1772         return budget - quota;
1773 }
1774
1775 /* PHY state control function */
1776 static void sh_eth_adjust_link(struct net_device *ndev)
1777 {
1778         struct sh_eth_private *mdp = netdev_priv(ndev);
1779         struct phy_device *phydev = mdp->phydev;
1780         int new_state = 0;
1781
1782         if (phydev->link) {
1783                 if (phydev->duplex != mdp->duplex) {
1784                         new_state = 1;
1785                         mdp->duplex = phydev->duplex;
1786                         if (mdp->cd->set_duplex)
1787                                 mdp->cd->set_duplex(ndev);
1788                 }
1789
1790                 if (phydev->speed != mdp->speed) {
1791                         new_state = 1;
1792                         mdp->speed = phydev->speed;
1793                         if (mdp->cd->set_rate)
1794                                 mdp->cd->set_rate(ndev);
1795                 }
1796                 if (!mdp->link) {
1797                         sh_eth_write(ndev,
1798                                      sh_eth_read(ndev, ECMR) & ~ECMR_TXF,
1799                                      ECMR);
1800                         new_state = 1;
1801                         mdp->link = phydev->link;
1802                         if (mdp->cd->no_psr || mdp->no_ether_link)
1803                                 sh_eth_rcv_snd_enable(ndev);
1804                 }
1805         } else if (mdp->link) {
1806                 new_state = 1;
1807                 mdp->link = 0;
1808                 mdp->speed = 0;
1809                 mdp->duplex = -1;
1810                 if (mdp->cd->no_psr || mdp->no_ether_link)
1811                         sh_eth_rcv_snd_disable(ndev);
1812         }
1813
1814         if (new_state && netif_msg_link(mdp))
1815                 phy_print_status(phydev);
1816 }
1817
1818 /* PHY init function */
1819 static int sh_eth_phy_init(struct net_device *ndev)
1820 {
1821         struct device_node *np = ndev->dev.parent->of_node;
1822         struct sh_eth_private *mdp = netdev_priv(ndev);
1823         struct phy_device *phydev = NULL;
1824
1825         mdp->link = 0;
1826         mdp->speed = 0;
1827         mdp->duplex = -1;
1828
1829         /* Try connect to PHY */
1830         if (np) {
1831                 struct device_node *pn;
1832
1833                 pn = of_parse_phandle(np, "phy-handle", 0);
1834                 phydev = of_phy_connect(ndev, pn,
1835                                         sh_eth_adjust_link, 0,
1836                                         mdp->phy_interface);
1837
1838                 if (!phydev)
1839                         phydev = ERR_PTR(-ENOENT);
1840         } else {
1841                 char phy_id[MII_BUS_ID_SIZE + 3];
1842
1843                 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1844                          mdp->mii_bus->id, mdp->phy_id);
1845
1846                 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1847                                      mdp->phy_interface);
1848         }
1849
1850         if (IS_ERR(phydev)) {
1851                 netdev_err(ndev, "failed to connect PHY\n");
1852                 return PTR_ERR(phydev);
1853         }
1854
1855         netdev_info(ndev, "attached PHY %d (IRQ %d) to driver %s\n",
1856                     phydev->addr, phydev->irq, phydev->drv->name);
1857
1858         mdp->phydev = phydev;
1859
1860         return 0;
1861 }
1862
1863 /* PHY control start function */
1864 static int sh_eth_phy_start(struct net_device *ndev)
1865 {
1866         struct sh_eth_private *mdp = netdev_priv(ndev);
1867         int ret;
1868
1869         ret = sh_eth_phy_init(ndev);
1870         if (ret)
1871                 return ret;
1872
1873         phy_start(mdp->phydev);
1874
1875         return 0;
1876 }
1877
1878 static int sh_eth_get_settings(struct net_device *ndev,
1879                                struct ethtool_cmd *ecmd)
1880 {
1881         struct sh_eth_private *mdp = netdev_priv(ndev);
1882         unsigned long flags;
1883         int ret;
1884
1885         if (!mdp->phydev)
1886                 return -ENODEV;
1887
1888         spin_lock_irqsave(&mdp->lock, flags);
1889         ret = phy_ethtool_gset(mdp->phydev, ecmd);
1890         spin_unlock_irqrestore(&mdp->lock, flags);
1891
1892         return ret;
1893 }
1894
1895 static int sh_eth_set_settings(struct net_device *ndev,
1896                                struct ethtool_cmd *ecmd)
1897 {
1898         struct sh_eth_private *mdp = netdev_priv(ndev);
1899         unsigned long flags;
1900         int ret;
1901
1902         if (!mdp->phydev)
1903                 return -ENODEV;
1904
1905         spin_lock_irqsave(&mdp->lock, flags);
1906
1907         /* disable tx and rx */
1908         sh_eth_rcv_snd_disable(ndev);
1909
1910         ret = phy_ethtool_sset(mdp->phydev, ecmd);
1911         if (ret)
1912                 goto error_exit;
1913
1914         if (ecmd->duplex == DUPLEX_FULL)
1915                 mdp->duplex = 1;
1916         else
1917                 mdp->duplex = 0;
1918
1919         if (mdp->cd->set_duplex)
1920                 mdp->cd->set_duplex(ndev);
1921
1922 error_exit:
1923         mdelay(1);
1924
1925         /* enable tx and rx */
1926         sh_eth_rcv_snd_enable(ndev);
1927
1928         spin_unlock_irqrestore(&mdp->lock, flags);
1929
1930         return ret;
1931 }
1932
1933 /* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the
1934  * version must be bumped as well.  Just adding registers up to that
1935  * limit is fine, as long as the existing register indices don't
1936  * change.
1937  */
1938 #define SH_ETH_REG_DUMP_VERSION         1
1939 #define SH_ETH_REG_DUMP_MAX_REGS        256
1940
1941 static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf)
1942 {
1943         struct sh_eth_private *mdp = netdev_priv(ndev);
1944         struct sh_eth_cpu_data *cd = mdp->cd;
1945         u32 *valid_map;
1946         size_t len;
1947
1948         BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS);
1949
1950         /* Dump starts with a bitmap that tells ethtool which
1951          * registers are defined for this chip.
1952          */
1953         len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32);
1954         if (buf) {
1955                 valid_map = buf;
1956                 buf += len;
1957         } else {
1958                 valid_map = NULL;
1959         }
1960
1961         /* Add a register to the dump, if it has a defined offset.
1962          * This automatically skips most undefined registers, but for
1963          * some it is also necessary to check a capability flag in
1964          * struct sh_eth_cpu_data.
1965          */
1966 #define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32)
1967 #define add_reg_from(reg, read_expr) do {                               \
1968                 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) {    \
1969                         if (buf) {                                      \
1970                                 mark_reg_valid(reg);                    \
1971                                 *buf++ = read_expr;                     \
1972                         }                                               \
1973                         ++len;                                          \
1974                 }                                                       \
1975         } while (0)
1976 #define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg))
1977 #define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg))
1978
1979         add_reg(EDSR);
1980         add_reg(EDMR);
1981         add_reg(EDTRR);
1982         add_reg(EDRRR);
1983         add_reg(EESR);
1984         add_reg(EESIPR);
1985         add_reg(TDLAR);
1986         add_reg(TDFAR);
1987         add_reg(TDFXR);
1988         add_reg(TDFFR);
1989         add_reg(RDLAR);
1990         add_reg(RDFAR);
1991         add_reg(RDFXR);
1992         add_reg(RDFFR);
1993         add_reg(TRSCER);
1994         add_reg(RMFCR);
1995         add_reg(TFTR);
1996         add_reg(FDR);
1997         add_reg(RMCR);
1998         add_reg(TFUCR);
1999         add_reg(RFOCR);
2000         if (cd->rmiimode)
2001                 add_reg(RMIIMODE);
2002         add_reg(FCFTR);
2003         if (cd->rpadir)
2004                 add_reg(RPADIR);
2005         if (!cd->no_trimd)
2006                 add_reg(TRIMD);
2007         add_reg(ECMR);
2008         add_reg(ECSR);
2009         add_reg(ECSIPR);
2010         add_reg(PIR);
2011         if (!cd->no_psr)
2012                 add_reg(PSR);
2013         add_reg(RDMLR);
2014         add_reg(RFLR);
2015         add_reg(IPGR);
2016         if (cd->apr)
2017                 add_reg(APR);
2018         if (cd->mpr)
2019                 add_reg(MPR);
2020         add_reg(RFCR);
2021         add_reg(RFCF);
2022         if (cd->tpauser)
2023                 add_reg(TPAUSER);
2024         add_reg(TPAUSECR);
2025         add_reg(GECMR);
2026         if (cd->bculr)
2027                 add_reg(BCULR);
2028         add_reg(MAHR);
2029         add_reg(MALR);
2030         add_reg(TROCR);
2031         add_reg(CDCR);
2032         add_reg(LCCR);
2033         add_reg(CNDCR);
2034         add_reg(CEFCR);
2035         add_reg(FRECR);
2036         add_reg(TSFRCR);
2037         add_reg(TLFRCR);
2038         add_reg(CERCR);
2039         add_reg(CEECR);
2040         add_reg(MAFCR);
2041         if (cd->rtrate)
2042                 add_reg(RTRATE);
2043         if (cd->hw_crc)
2044                 add_reg(CSMR);
2045         if (cd->select_mii)
2046                 add_reg(RMII_MII);
2047         add_reg(ARSTR);
2048         if (cd->tsu) {
2049                 add_tsu_reg(TSU_CTRST);
2050                 add_tsu_reg(TSU_FWEN0);
2051                 add_tsu_reg(TSU_FWEN1);
2052                 add_tsu_reg(TSU_FCM);
2053                 add_tsu_reg(TSU_BSYSL0);
2054                 add_tsu_reg(TSU_BSYSL1);
2055                 add_tsu_reg(TSU_PRISL0);
2056                 add_tsu_reg(TSU_PRISL1);
2057                 add_tsu_reg(TSU_FWSL0);
2058                 add_tsu_reg(TSU_FWSL1);
2059                 add_tsu_reg(TSU_FWSLC);
2060                 add_tsu_reg(TSU_QTAG0);
2061                 add_tsu_reg(TSU_QTAG1);
2062                 add_tsu_reg(TSU_QTAGM0);
2063                 add_tsu_reg(TSU_QTAGM1);
2064                 add_tsu_reg(TSU_FWSR);
2065                 add_tsu_reg(TSU_FWINMK);
2066                 add_tsu_reg(TSU_ADQT0);
2067                 add_tsu_reg(TSU_ADQT1);
2068                 add_tsu_reg(TSU_VTAG0);
2069                 add_tsu_reg(TSU_VTAG1);
2070                 add_tsu_reg(TSU_ADSBSY);
2071                 add_tsu_reg(TSU_TEN);
2072                 add_tsu_reg(TSU_POST1);
2073                 add_tsu_reg(TSU_POST2);
2074                 add_tsu_reg(TSU_POST3);
2075                 add_tsu_reg(TSU_POST4);
2076                 if (mdp->reg_offset[TSU_ADRH0] != SH_ETH_OFFSET_INVALID) {
2077                         /* This is the start of a table, not just a single
2078                          * register.
2079                          */
2080                         if (buf) {
2081                                 unsigned int i;
2082
2083                                 mark_reg_valid(TSU_ADRH0);
2084                                 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++)
2085                                         *buf++ = ioread32(
2086                                                 mdp->tsu_addr +
2087                                                 mdp->reg_offset[TSU_ADRH0] +
2088                                                 i * 4);
2089                         }
2090                         len += SH_ETH_TSU_CAM_ENTRIES * 2;
2091                 }
2092         }
2093
2094 #undef mark_reg_valid
2095 #undef add_reg_from
2096 #undef add_reg
2097 #undef add_tsu_reg
2098
2099         return len * 4;
2100 }
2101
2102 static int sh_eth_get_regs_len(struct net_device *ndev)
2103 {
2104         return __sh_eth_get_regs(ndev, NULL);
2105 }
2106
2107 static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs,
2108                             void *buf)
2109 {
2110         struct sh_eth_private *mdp = netdev_priv(ndev);
2111
2112         regs->version = SH_ETH_REG_DUMP_VERSION;
2113
2114         pm_runtime_get_sync(&mdp->pdev->dev);
2115         __sh_eth_get_regs(ndev, buf);
2116         pm_runtime_put_sync(&mdp->pdev->dev);
2117 }
2118
2119 static int sh_eth_nway_reset(struct net_device *ndev)
2120 {
2121         struct sh_eth_private *mdp = netdev_priv(ndev);
2122         unsigned long flags;
2123         int ret;
2124
2125         if (!mdp->phydev)
2126                 return -ENODEV;
2127
2128         spin_lock_irqsave(&mdp->lock, flags);
2129         ret = phy_start_aneg(mdp->phydev);
2130         spin_unlock_irqrestore(&mdp->lock, flags);
2131
2132         return ret;
2133 }
2134
2135 static u32 sh_eth_get_msglevel(struct net_device *ndev)
2136 {
2137         struct sh_eth_private *mdp = netdev_priv(ndev);
2138         return mdp->msg_enable;
2139 }
2140
2141 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
2142 {
2143         struct sh_eth_private *mdp = netdev_priv(ndev);
2144         mdp->msg_enable = value;
2145 }
2146
2147 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
2148         "rx_current", "tx_current",
2149         "rx_dirty", "tx_dirty",
2150 };
2151 #define SH_ETH_STATS_LEN  ARRAY_SIZE(sh_eth_gstrings_stats)
2152
2153 static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
2154 {
2155         switch (sset) {
2156         case ETH_SS_STATS:
2157                 return SH_ETH_STATS_LEN;
2158         default:
2159                 return -EOPNOTSUPP;
2160         }
2161 }
2162
2163 static void sh_eth_get_ethtool_stats(struct net_device *ndev,
2164                                      struct ethtool_stats *stats, u64 *data)
2165 {
2166         struct sh_eth_private *mdp = netdev_priv(ndev);
2167         int i = 0;
2168
2169         /* device-specific stats */
2170         data[i++] = mdp->cur_rx;
2171         data[i++] = mdp->cur_tx;
2172         data[i++] = mdp->dirty_rx;
2173         data[i++] = mdp->dirty_tx;
2174 }
2175
2176 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
2177 {
2178         switch (stringset) {
2179         case ETH_SS_STATS:
2180                 memcpy(data, *sh_eth_gstrings_stats,
2181                        sizeof(sh_eth_gstrings_stats));
2182                 break;
2183         }
2184 }
2185
2186 static void sh_eth_get_ringparam(struct net_device *ndev,
2187                                  struct ethtool_ringparam *ring)
2188 {
2189         struct sh_eth_private *mdp = netdev_priv(ndev);
2190
2191         ring->rx_max_pending = RX_RING_MAX;
2192         ring->tx_max_pending = TX_RING_MAX;
2193         ring->rx_pending = mdp->num_rx_ring;
2194         ring->tx_pending = mdp->num_tx_ring;
2195 }
2196
2197 static int sh_eth_set_ringparam(struct net_device *ndev,
2198                                 struct ethtool_ringparam *ring)
2199 {
2200         struct sh_eth_private *mdp = netdev_priv(ndev);
2201         int ret;
2202
2203         if (ring->tx_pending > TX_RING_MAX ||
2204             ring->rx_pending > RX_RING_MAX ||
2205             ring->tx_pending < TX_RING_MIN ||
2206             ring->rx_pending < RX_RING_MIN)
2207                 return -EINVAL;
2208         if (ring->rx_mini_pending || ring->rx_jumbo_pending)
2209                 return -EINVAL;
2210
2211         if (netif_running(ndev)) {
2212                 netif_device_detach(ndev);
2213                 netif_tx_disable(ndev);
2214
2215                 /* Serialise with the interrupt handler and NAPI, then
2216                  * disable interrupts.  We have to clear the
2217                  * irq_enabled flag first to ensure that interrupts
2218                  * won't be re-enabled.
2219                  */
2220                 mdp->irq_enabled = false;
2221                 synchronize_irq(ndev->irq);
2222                 napi_synchronize(&mdp->napi);
2223                 sh_eth_write(ndev, 0x0000, EESIPR);
2224
2225                 sh_eth_dev_exit(ndev);
2226
2227                 /* Free all the skbuffs in the Rx queue and the DMA buffers. */
2228                 sh_eth_ring_free(ndev);
2229         }
2230
2231         /* Set new parameters */
2232         mdp->num_rx_ring = ring->rx_pending;
2233         mdp->num_tx_ring = ring->tx_pending;
2234
2235         if (netif_running(ndev)) {
2236                 ret = sh_eth_ring_init(ndev);
2237                 if (ret < 0) {
2238                         netdev_err(ndev, "%s: sh_eth_ring_init failed.\n",
2239                                    __func__);
2240                         return ret;
2241                 }
2242                 ret = sh_eth_dev_init(ndev, false);
2243                 if (ret < 0) {
2244                         netdev_err(ndev, "%s: sh_eth_dev_init failed.\n",
2245                                    __func__);
2246                         return ret;
2247                 }
2248
2249                 mdp->irq_enabled = true;
2250                 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
2251                 /* Setting the Rx mode will start the Rx process. */
2252                 sh_eth_write(ndev, EDRRR_R, EDRRR);
2253                 netif_device_attach(ndev);
2254         }
2255
2256         return 0;
2257 }
2258
2259 static const struct ethtool_ops sh_eth_ethtool_ops = {
2260         .get_settings   = sh_eth_get_settings,
2261         .set_settings   = sh_eth_set_settings,
2262         .get_regs_len   = sh_eth_get_regs_len,
2263         .get_regs       = sh_eth_get_regs,
2264         .nway_reset     = sh_eth_nway_reset,
2265         .get_msglevel   = sh_eth_get_msglevel,
2266         .set_msglevel   = sh_eth_set_msglevel,
2267         .get_link       = ethtool_op_get_link,
2268         .get_strings    = sh_eth_get_strings,
2269         .get_ethtool_stats  = sh_eth_get_ethtool_stats,
2270         .get_sset_count     = sh_eth_get_sset_count,
2271         .get_ringparam  = sh_eth_get_ringparam,
2272         .set_ringparam  = sh_eth_set_ringparam,
2273 };
2274
2275 /* network device open function */
2276 static int sh_eth_open(struct net_device *ndev)
2277 {
2278         int ret = 0;
2279         struct sh_eth_private *mdp = netdev_priv(ndev);
2280
2281         pm_runtime_get_sync(&mdp->pdev->dev);
2282
2283         napi_enable(&mdp->napi);
2284
2285         ret = request_irq(ndev->irq, sh_eth_interrupt,
2286                           mdp->cd->irq_flags, ndev->name, ndev);
2287         if (ret) {
2288                 netdev_err(ndev, "Can not assign IRQ number\n");
2289                 goto out_napi_off;
2290         }
2291
2292         /* Descriptor set */
2293         ret = sh_eth_ring_init(ndev);
2294         if (ret)
2295                 goto out_free_irq;
2296
2297         /* device init */
2298         ret = sh_eth_dev_init(ndev, true);
2299         if (ret)
2300                 goto out_free_irq;
2301
2302         /* PHY control start*/
2303         ret = sh_eth_phy_start(ndev);
2304         if (ret)
2305                 goto out_free_irq;
2306
2307         mdp->is_opened = 1;
2308
2309         return ret;
2310
2311 out_free_irq:
2312         free_irq(ndev->irq, ndev);
2313 out_napi_off:
2314         napi_disable(&mdp->napi);
2315         pm_runtime_put_sync(&mdp->pdev->dev);
2316         return ret;
2317 }
2318
2319 /* Timeout function */
2320 static void sh_eth_tx_timeout(struct net_device *ndev)
2321 {
2322         struct sh_eth_private *mdp = netdev_priv(ndev);
2323         struct sh_eth_rxdesc *rxdesc;
2324         int i;
2325
2326         netif_stop_queue(ndev);
2327
2328         netif_err(mdp, timer, ndev,
2329                   "transmit timed out, status %8.8x, resetting...\n",
2330                   sh_eth_read(ndev, EESR));
2331
2332         /* tx_errors count up */
2333         ndev->stats.tx_errors++;
2334
2335         /* Free all the skbuffs in the Rx queue. */
2336         for (i = 0; i < mdp->num_rx_ring; i++) {
2337                 rxdesc = &mdp->rx_ring[i];
2338                 rxdesc->status = cpu_to_edmac(mdp, 0);
2339                 rxdesc->addr = cpu_to_edmac(mdp, 0xBADF00D0);
2340                 dev_kfree_skb(mdp->rx_skbuff[i]);
2341                 mdp->rx_skbuff[i] = NULL;
2342         }
2343         for (i = 0; i < mdp->num_tx_ring; i++) {
2344                 dev_kfree_skb(mdp->tx_skbuff[i]);
2345                 mdp->tx_skbuff[i] = NULL;
2346         }
2347
2348         /* device init */
2349         sh_eth_dev_init(ndev, true);
2350 }
2351
2352 /* Packet transmit function */
2353 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2354 {
2355         struct sh_eth_private *mdp = netdev_priv(ndev);
2356         struct sh_eth_txdesc *txdesc;
2357         dma_addr_t dma_addr;
2358         u32 entry;
2359         unsigned long flags;
2360
2361         spin_lock_irqsave(&mdp->lock, flags);
2362         if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
2363                 if (!sh_eth_txfree(ndev)) {
2364                         netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
2365                         netif_stop_queue(ndev);
2366                         spin_unlock_irqrestore(&mdp->lock, flags);
2367                         return NETDEV_TX_BUSY;
2368                 }
2369         }
2370         spin_unlock_irqrestore(&mdp->lock, flags);
2371
2372         if (skb_put_padto(skb, ETH_ZLEN))
2373                 return NETDEV_TX_OK;
2374
2375         entry = mdp->cur_tx % mdp->num_tx_ring;
2376         mdp->tx_skbuff[entry] = skb;
2377         txdesc = &mdp->tx_ring[entry];
2378         /* soft swap. */
2379         if (!mdp->cd->hw_swap)
2380                 sh_eth_soft_swap(PTR_ALIGN(skb->data, 4), skb->len + 2);
2381         dma_addr = dma_map_single(&ndev->dev, skb->data, skb->len,
2382                                   DMA_TO_DEVICE);
2383         if (dma_mapping_error(&ndev->dev, dma_addr)) {
2384                 kfree_skb(skb);
2385                 return NETDEV_TX_OK;
2386         }
2387         txdesc->addr = cpu_to_edmac(mdp, dma_addr);
2388         txdesc->len  = cpu_to_edmac(mdp, skb->len << 16);
2389
2390         dma_wmb(); /* TACT bit must be set after all the above writes */
2391         if (entry >= mdp->num_tx_ring - 1)
2392                 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
2393         else
2394                 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
2395
2396         mdp->cur_tx++;
2397
2398         if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
2399                 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
2400
2401         return NETDEV_TX_OK;
2402 }
2403
2404 /* The statistics registers have write-clear behaviour, which means we
2405  * will lose any increment between the read and write.  We mitigate
2406  * this by only clearing when we read a non-zero value, so we will
2407  * never falsely report a total of zero.
2408  */
2409 static void
2410 sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg)
2411 {
2412         u32 delta = sh_eth_read(ndev, reg);
2413
2414         if (delta) {
2415                 *stat += delta;
2416                 sh_eth_write(ndev, 0, reg);
2417         }
2418 }
2419
2420 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2421 {
2422         struct sh_eth_private *mdp = netdev_priv(ndev);
2423
2424         if (sh_eth_is_rz_fast_ether(mdp))
2425                 return &ndev->stats;
2426
2427         if (!mdp->is_opened)
2428                 return &ndev->stats;
2429
2430         sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR);
2431         sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR);
2432         sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR);
2433
2434         if (sh_eth_is_gether(mdp)) {
2435                 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2436                                    CERCR);
2437                 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2438                                    CEECR);
2439         } else {
2440                 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2441                                    CNDCR);
2442         }
2443
2444         return &ndev->stats;
2445 }
2446
2447 /* device close function */
2448 static int sh_eth_close(struct net_device *ndev)
2449 {
2450         struct sh_eth_private *mdp = netdev_priv(ndev);
2451
2452         netif_stop_queue(ndev);
2453
2454         /* Serialise with the interrupt handler and NAPI, then disable
2455          * interrupts.  We have to clear the irq_enabled flag first to
2456          * ensure that interrupts won't be re-enabled.
2457          */
2458         mdp->irq_enabled = false;
2459         synchronize_irq(ndev->irq);
2460         napi_disable(&mdp->napi);
2461         sh_eth_write(ndev, 0x0000, EESIPR);
2462
2463         sh_eth_dev_exit(ndev);
2464
2465         /* PHY Disconnect */
2466         if (mdp->phydev) {
2467                 phy_stop(mdp->phydev);
2468                 phy_disconnect(mdp->phydev);
2469                 mdp->phydev = NULL;
2470         }
2471
2472         free_irq(ndev->irq, ndev);
2473
2474         /* Free all the skbuffs in the Rx queue and the DMA buffer. */
2475         sh_eth_ring_free(ndev);
2476
2477         pm_runtime_put_sync(&mdp->pdev->dev);
2478
2479         mdp->is_opened = 0;
2480
2481         return 0;
2482 }
2483
2484 /* ioctl to device function */
2485 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2486 {
2487         struct sh_eth_private *mdp = netdev_priv(ndev);
2488         struct phy_device *phydev = mdp->phydev;
2489
2490         if (!netif_running(ndev))
2491                 return -EINVAL;
2492
2493         if (!phydev)
2494                 return -ENODEV;
2495
2496         return phy_mii_ioctl(phydev, rq, cmd);
2497 }
2498
2499 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2500 static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2501                                             int entry)
2502 {
2503         return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2504 }
2505
2506 static u32 sh_eth_tsu_get_post_mask(int entry)
2507 {
2508         return 0x0f << (28 - ((entry % 8) * 4));
2509 }
2510
2511 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2512 {
2513         return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2514 }
2515
2516 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2517                                              int entry)
2518 {
2519         struct sh_eth_private *mdp = netdev_priv(ndev);
2520         u32 tmp;
2521         void *reg_offset;
2522
2523         reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2524         tmp = ioread32(reg_offset);
2525         iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2526 }
2527
2528 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2529                                               int entry)
2530 {
2531         struct sh_eth_private *mdp = netdev_priv(ndev);
2532         u32 post_mask, ref_mask, tmp;
2533         void *reg_offset;
2534
2535         reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2536         post_mask = sh_eth_tsu_get_post_mask(entry);
2537         ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2538
2539         tmp = ioread32(reg_offset);
2540         iowrite32(tmp & ~post_mask, reg_offset);
2541
2542         /* If other port enables, the function returns "true" */
2543         return tmp & ref_mask;
2544 }
2545
2546 static int sh_eth_tsu_busy(struct net_device *ndev)
2547 {
2548         int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2549         struct sh_eth_private *mdp = netdev_priv(ndev);
2550
2551         while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2552                 udelay(10);
2553                 timeout--;
2554                 if (timeout <= 0) {
2555                         netdev_err(ndev, "%s: timeout\n", __func__);
2556                         return -ETIMEDOUT;
2557                 }
2558         }
2559
2560         return 0;
2561 }
2562
2563 static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2564                                   const u8 *addr)
2565 {
2566         u32 val;
2567
2568         val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2569         iowrite32(val, reg);
2570         if (sh_eth_tsu_busy(ndev) < 0)
2571                 return -EBUSY;
2572
2573         val = addr[4] << 8 | addr[5];
2574         iowrite32(val, reg + 4);
2575         if (sh_eth_tsu_busy(ndev) < 0)
2576                 return -EBUSY;
2577
2578         return 0;
2579 }
2580
2581 static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2582 {
2583         u32 val;
2584
2585         val = ioread32(reg);
2586         addr[0] = (val >> 24) & 0xff;
2587         addr[1] = (val >> 16) & 0xff;
2588         addr[2] = (val >> 8) & 0xff;
2589         addr[3] = val & 0xff;
2590         val = ioread32(reg + 4);
2591         addr[4] = (val >> 8) & 0xff;
2592         addr[5] = val & 0xff;
2593 }
2594
2595
2596 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2597 {
2598         struct sh_eth_private *mdp = netdev_priv(ndev);
2599         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2600         int i;
2601         u8 c_addr[ETH_ALEN];
2602
2603         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2604                 sh_eth_tsu_read_entry(reg_offset, c_addr);
2605                 if (ether_addr_equal(addr, c_addr))
2606                         return i;
2607         }
2608
2609         return -ENOENT;
2610 }
2611
2612 static int sh_eth_tsu_find_empty(struct net_device *ndev)
2613 {
2614         u8 blank[ETH_ALEN];
2615         int entry;
2616
2617         memset(blank, 0, sizeof(blank));
2618         entry = sh_eth_tsu_find_entry(ndev, blank);
2619         return (entry < 0) ? -ENOMEM : entry;
2620 }
2621
2622 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2623                                               int entry)
2624 {
2625         struct sh_eth_private *mdp = netdev_priv(ndev);
2626         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2627         int ret;
2628         u8 blank[ETH_ALEN];
2629
2630         sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2631                          ~(1 << (31 - entry)), TSU_TEN);
2632
2633         memset(blank, 0, sizeof(blank));
2634         ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2635         if (ret < 0)
2636                 return ret;
2637         return 0;
2638 }
2639
2640 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2641 {
2642         struct sh_eth_private *mdp = netdev_priv(ndev);
2643         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2644         int i, ret;
2645
2646         if (!mdp->cd->tsu)
2647                 return 0;
2648
2649         i = sh_eth_tsu_find_entry(ndev, addr);
2650         if (i < 0) {
2651                 /* No entry found, create one */
2652                 i = sh_eth_tsu_find_empty(ndev);
2653                 if (i < 0)
2654                         return -ENOMEM;
2655                 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2656                 if (ret < 0)
2657                         return ret;
2658
2659                 /* Enable the entry */
2660                 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2661                                  (1 << (31 - i)), TSU_TEN);
2662         }
2663
2664         /* Entry found or created, enable POST */
2665         sh_eth_tsu_enable_cam_entry_post(ndev, i);
2666
2667         return 0;
2668 }
2669
2670 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2671 {
2672         struct sh_eth_private *mdp = netdev_priv(ndev);
2673         int i, ret;
2674
2675         if (!mdp->cd->tsu)
2676                 return 0;
2677
2678         i = sh_eth_tsu_find_entry(ndev, addr);
2679         if (i) {
2680                 /* Entry found */
2681                 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2682                         goto done;
2683
2684                 /* Disable the entry if both ports was disabled */
2685                 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2686                 if (ret < 0)
2687                         return ret;
2688         }
2689 done:
2690         return 0;
2691 }
2692
2693 static int sh_eth_tsu_purge_all(struct net_device *ndev)
2694 {
2695         struct sh_eth_private *mdp = netdev_priv(ndev);
2696         int i, ret;
2697
2698         if (!mdp->cd->tsu)
2699                 return 0;
2700
2701         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2702                 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2703                         continue;
2704
2705                 /* Disable the entry if both ports was disabled */
2706                 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2707                 if (ret < 0)
2708                         return ret;
2709         }
2710
2711         return 0;
2712 }
2713
2714 static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2715 {
2716         struct sh_eth_private *mdp = netdev_priv(ndev);
2717         u8 addr[ETH_ALEN];
2718         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2719         int i;
2720
2721         if (!mdp->cd->tsu)
2722                 return;
2723
2724         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2725                 sh_eth_tsu_read_entry(reg_offset, addr);
2726                 if (is_multicast_ether_addr(addr))
2727                         sh_eth_tsu_del_entry(ndev, addr);
2728         }
2729 }
2730
2731 /* Update promiscuous flag and multicast filter */
2732 static void sh_eth_set_rx_mode(struct net_device *ndev)
2733 {
2734         struct sh_eth_private *mdp = netdev_priv(ndev);
2735         u32 ecmr_bits;
2736         int mcast_all = 0;
2737         unsigned long flags;
2738
2739         spin_lock_irqsave(&mdp->lock, flags);
2740         /* Initial condition is MCT = 1, PRM = 0.
2741          * Depending on ndev->flags, set PRM or clear MCT
2742          */
2743         ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM;
2744         if (mdp->cd->tsu)
2745                 ecmr_bits |= ECMR_MCT;
2746
2747         if (!(ndev->flags & IFF_MULTICAST)) {
2748                 sh_eth_tsu_purge_mcast(ndev);
2749                 mcast_all = 1;
2750         }
2751         if (ndev->flags & IFF_ALLMULTI) {
2752                 sh_eth_tsu_purge_mcast(ndev);
2753                 ecmr_bits &= ~ECMR_MCT;
2754                 mcast_all = 1;
2755         }
2756
2757         if (ndev->flags & IFF_PROMISC) {
2758                 sh_eth_tsu_purge_all(ndev);
2759                 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2760         } else if (mdp->cd->tsu) {
2761                 struct netdev_hw_addr *ha;
2762                 netdev_for_each_mc_addr(ha, ndev) {
2763                         if (mcast_all && is_multicast_ether_addr(ha->addr))
2764                                 continue;
2765
2766                         if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2767                                 if (!mcast_all) {
2768                                         sh_eth_tsu_purge_mcast(ndev);
2769                                         ecmr_bits &= ~ECMR_MCT;
2770                                         mcast_all = 1;
2771                                 }
2772                         }
2773                 }
2774         }
2775
2776         /* update the ethernet mode */
2777         sh_eth_write(ndev, ecmr_bits, ECMR);
2778
2779         spin_unlock_irqrestore(&mdp->lock, flags);
2780 }
2781
2782 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2783 {
2784         if (!mdp->port)
2785                 return TSU_VTAG0;
2786         else
2787                 return TSU_VTAG1;
2788 }
2789
2790 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2791                                   __be16 proto, u16 vid)
2792 {
2793         struct sh_eth_private *mdp = netdev_priv(ndev);
2794         int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2795
2796         if (unlikely(!mdp->cd->tsu))
2797                 return -EPERM;
2798
2799         /* No filtering if vid = 0 */
2800         if (!vid)
2801                 return 0;
2802
2803         mdp->vlan_num_ids++;
2804
2805         /* The controller has one VLAN tag HW filter. So, if the filter is
2806          * already enabled, the driver disables it and the filte
2807          */
2808         if (mdp->vlan_num_ids > 1) {
2809                 /* disable VLAN filter */
2810                 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2811                 return 0;
2812         }
2813
2814         sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2815                          vtag_reg_index);
2816
2817         return 0;
2818 }
2819
2820 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2821                                    __be16 proto, u16 vid)
2822 {
2823         struct sh_eth_private *mdp = netdev_priv(ndev);
2824         int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2825
2826         if (unlikely(!mdp->cd->tsu))
2827                 return -EPERM;
2828
2829         /* No filtering if vid = 0 */
2830         if (!vid)
2831                 return 0;
2832
2833         mdp->vlan_num_ids--;
2834         sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2835
2836         return 0;
2837 }
2838
2839 /* SuperH's TSU register init function */
2840 static void sh_eth_tsu_init(struct sh_eth_private *mdp)
2841 {
2842         if (sh_eth_is_rz_fast_ether(mdp)) {
2843                 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2844                 return;
2845         }
2846
2847         sh_eth_tsu_write(mdp, 0, TSU_FWEN0);    /* Disable forward(0->1) */
2848         sh_eth_tsu_write(mdp, 0, TSU_FWEN1);    /* Disable forward(1->0) */
2849         sh_eth_tsu_write(mdp, 0, TSU_FCM);      /* forward fifo 3k-3k */
2850         sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2851         sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2852         sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2853         sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2854         sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2855         sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2856         sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
2857         if (sh_eth_is_gether(mdp)) {
2858                 sh_eth_tsu_write(mdp, 0, TSU_QTAG0);    /* Disable QTAG(0->1) */
2859                 sh_eth_tsu_write(mdp, 0, TSU_QTAG1);    /* Disable QTAG(1->0) */
2860         } else {
2861                 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0);   /* Disable QTAG(0->1) */
2862                 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1);   /* Disable QTAG(1->0) */
2863         }
2864         sh_eth_tsu_write(mdp, 0, TSU_FWSR);     /* all interrupt status clear */
2865         sh_eth_tsu_write(mdp, 0, TSU_FWINMK);   /* Disable all interrupt */
2866         sh_eth_tsu_write(mdp, 0, TSU_TEN);      /* Disable all CAM entry */
2867         sh_eth_tsu_write(mdp, 0, TSU_POST1);    /* Disable CAM entry [ 0- 7] */
2868         sh_eth_tsu_write(mdp, 0, TSU_POST2);    /* Disable CAM entry [ 8-15] */
2869         sh_eth_tsu_write(mdp, 0, TSU_POST3);    /* Disable CAM entry [16-23] */
2870         sh_eth_tsu_write(mdp, 0, TSU_POST4);    /* Disable CAM entry [24-31] */
2871 }
2872
2873 /* MDIO bus release function */
2874 static int sh_mdio_release(struct sh_eth_private *mdp)
2875 {
2876         /* unregister mdio bus */
2877         mdiobus_unregister(mdp->mii_bus);
2878
2879         /* free bitbang info */
2880         free_mdio_bitbang(mdp->mii_bus);
2881
2882         return 0;
2883 }
2884
2885 /* MDIO bus init function */
2886 static int sh_mdio_init(struct sh_eth_private *mdp,
2887                         struct sh_eth_plat_data *pd)
2888 {
2889         int ret, i;
2890         struct bb_info *bitbang;
2891         struct platform_device *pdev = mdp->pdev;
2892         struct device *dev = &mdp->pdev->dev;
2893
2894         /* create bit control struct for PHY */
2895         bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL);
2896         if (!bitbang)
2897                 return -ENOMEM;
2898
2899         /* bitbang init */
2900         bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
2901         bitbang->set_gate = pd->set_mdio_gate;
2902         bitbang->ctrl.ops = &bb_ops;
2903
2904         /* MII controller setting */
2905         mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
2906         if (!mdp->mii_bus)
2907                 return -ENOMEM;
2908
2909         /* Hook up MII support for ethtool */
2910         mdp->mii_bus->name = "sh_mii";
2911         mdp->mii_bus->parent = dev;
2912         snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2913                  pdev->name, pdev->id);
2914
2915         /* PHY IRQ */
2916         mdp->mii_bus->irq = devm_kmalloc_array(dev, PHY_MAX_ADDR, sizeof(int),
2917                                                GFP_KERNEL);
2918         if (!mdp->mii_bus->irq) {
2919                 ret = -ENOMEM;
2920                 goto out_free_bus;
2921         }
2922
2923         /* register MDIO bus */
2924         if (dev->of_node) {
2925                 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node);
2926         } else {
2927                 for (i = 0; i < PHY_MAX_ADDR; i++)
2928                         mdp->mii_bus->irq[i] = PHY_POLL;
2929                 if (pd->phy_irq > 0)
2930                         mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
2931
2932                 ret = mdiobus_register(mdp->mii_bus);
2933         }
2934
2935         if (ret)
2936                 goto out_free_bus;
2937
2938         return 0;
2939
2940 out_free_bus:
2941         free_mdio_bitbang(mdp->mii_bus);
2942         return ret;
2943 }
2944
2945 static const u16 *sh_eth_get_register_offset(int register_type)
2946 {
2947         const u16 *reg_offset = NULL;
2948
2949         switch (register_type) {
2950         case SH_ETH_REG_GIGABIT:
2951                 reg_offset = sh_eth_offset_gigabit;
2952                 break;
2953         case SH_ETH_REG_FAST_RZ:
2954                 reg_offset = sh_eth_offset_fast_rz;
2955                 break;
2956         case SH_ETH_REG_FAST_RCAR:
2957                 reg_offset = sh_eth_offset_fast_rcar;
2958                 break;
2959         case SH_ETH_REG_FAST_SH4:
2960                 reg_offset = sh_eth_offset_fast_sh4;
2961                 break;
2962         case SH_ETH_REG_FAST_SH3_SH2:
2963                 reg_offset = sh_eth_offset_fast_sh3_sh2;
2964                 break;
2965         default:
2966                 break;
2967         }
2968
2969         return reg_offset;
2970 }
2971
2972 static const struct net_device_ops sh_eth_netdev_ops = {
2973         .ndo_open               = sh_eth_open,
2974         .ndo_stop               = sh_eth_close,
2975         .ndo_start_xmit         = sh_eth_start_xmit,
2976         .ndo_get_stats          = sh_eth_get_stats,
2977         .ndo_set_rx_mode        = sh_eth_set_rx_mode,
2978         .ndo_tx_timeout         = sh_eth_tx_timeout,
2979         .ndo_do_ioctl           = sh_eth_do_ioctl,
2980         .ndo_validate_addr      = eth_validate_addr,
2981         .ndo_set_mac_address    = eth_mac_addr,
2982         .ndo_change_mtu         = eth_change_mtu,
2983 };
2984
2985 static const struct net_device_ops sh_eth_netdev_ops_tsu = {
2986         .ndo_open               = sh_eth_open,
2987         .ndo_stop               = sh_eth_close,
2988         .ndo_start_xmit         = sh_eth_start_xmit,
2989         .ndo_get_stats          = sh_eth_get_stats,
2990         .ndo_set_rx_mode        = sh_eth_set_rx_mode,
2991         .ndo_vlan_rx_add_vid    = sh_eth_vlan_rx_add_vid,
2992         .ndo_vlan_rx_kill_vid   = sh_eth_vlan_rx_kill_vid,
2993         .ndo_tx_timeout         = sh_eth_tx_timeout,
2994         .ndo_do_ioctl           = sh_eth_do_ioctl,
2995         .ndo_validate_addr      = eth_validate_addr,
2996         .ndo_set_mac_address    = eth_mac_addr,
2997         .ndo_change_mtu         = eth_change_mtu,
2998 };
2999
3000 #ifdef CONFIG_OF
3001 static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3002 {
3003         struct device_node *np = dev->of_node;
3004         struct sh_eth_plat_data *pdata;
3005         const char *mac_addr;
3006
3007         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
3008         if (!pdata)
3009                 return NULL;
3010
3011         pdata->phy_interface = of_get_phy_mode(np);
3012
3013         mac_addr = of_get_mac_address(np);
3014         if (mac_addr)
3015                 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
3016
3017         pdata->no_ether_link =
3018                 of_property_read_bool(np, "renesas,no-ether-link");
3019         pdata->ether_link_active_low =
3020                 of_property_read_bool(np, "renesas,ether-link-active-low");
3021
3022         return pdata;
3023 }
3024
3025 static const struct of_device_id sh_eth_match_table[] = {
3026         { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
3027         { .compatible = "renesas,ether-r8a7778", .data = &r8a777x_data },
3028         { .compatible = "renesas,ether-r8a7779", .data = &r8a777x_data },
3029         { .compatible = "renesas,ether-r8a7790", .data = &r8a779x_data },
3030         { .compatible = "renesas,ether-r8a7791", .data = &r8a779x_data },
3031         { .compatible = "renesas,ether-r8a7793", .data = &r8a779x_data },
3032         { .compatible = "renesas,ether-r8a7794", .data = &r8a779x_data },
3033         { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
3034         { }
3035 };
3036 MODULE_DEVICE_TABLE(of, sh_eth_match_table);
3037 #else
3038 static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3039 {
3040         return NULL;
3041 }
3042 #endif
3043
3044 static int sh_eth_drv_probe(struct platform_device *pdev)
3045 {
3046         int ret, devno = 0;
3047         struct resource *res;
3048         struct net_device *ndev = NULL;
3049         struct sh_eth_private *mdp = NULL;
3050         struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
3051         const struct platform_device_id *id = platform_get_device_id(pdev);
3052
3053         /* get base addr */
3054         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3055
3056         ndev = alloc_etherdev(sizeof(struct sh_eth_private));
3057         if (!ndev)
3058                 return -ENOMEM;
3059
3060         pm_runtime_enable(&pdev->dev);
3061         pm_runtime_get_sync(&pdev->dev);
3062
3063         devno = pdev->id;
3064         if (devno < 0)
3065                 devno = 0;
3066
3067         ndev->dma = -1;
3068         ret = platform_get_irq(pdev, 0);
3069         if (ret < 0)
3070                 goto out_release;
3071         ndev->irq = ret;
3072
3073         SET_NETDEV_DEV(ndev, &pdev->dev);
3074
3075         mdp = netdev_priv(ndev);
3076         mdp->num_tx_ring = TX_RING_SIZE;
3077         mdp->num_rx_ring = RX_RING_SIZE;
3078         mdp->addr = devm_ioremap_resource(&pdev->dev, res);
3079         if (IS_ERR(mdp->addr)) {
3080                 ret = PTR_ERR(mdp->addr);
3081                 goto out_release;
3082         }
3083
3084         ndev->base_addr = res->start;
3085
3086         spin_lock_init(&mdp->lock);
3087         mdp->pdev = pdev;
3088
3089         if (pdev->dev.of_node)
3090                 pd = sh_eth_parse_dt(&pdev->dev);
3091         if (!pd) {
3092                 dev_err(&pdev->dev, "no platform data\n");
3093                 ret = -EINVAL;
3094                 goto out_release;
3095         }
3096
3097         /* get PHY ID */
3098         mdp->phy_id = pd->phy;
3099         mdp->phy_interface = pd->phy_interface;
3100         /* EDMAC endian */
3101         mdp->edmac_endian = pd->edmac_endian;
3102         mdp->no_ether_link = pd->no_ether_link;
3103         mdp->ether_link_active_low = pd->ether_link_active_low;
3104
3105         /* set cpu data */
3106         if (id) {
3107                 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
3108         } else  {
3109                 const struct of_device_id *match;
3110
3111                 match = of_match_device(of_match_ptr(sh_eth_match_table),
3112                                         &pdev->dev);
3113                 mdp->cd = (struct sh_eth_cpu_data *)match->data;
3114         }
3115         mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
3116         if (!mdp->reg_offset) {
3117                 dev_err(&pdev->dev, "Unknown register type (%d)\n",
3118                         mdp->cd->register_type);
3119                 ret = -EINVAL;
3120                 goto out_release;
3121         }
3122         sh_eth_set_default_cpu_data(mdp->cd);
3123
3124         /* set function */
3125         if (mdp->cd->tsu)
3126                 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
3127         else
3128                 ndev->netdev_ops = &sh_eth_netdev_ops;
3129         ndev->ethtool_ops = &sh_eth_ethtool_ops;
3130         ndev->watchdog_timeo = TX_TIMEOUT;
3131
3132         /* debug message level */
3133         mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
3134
3135         /* read and set MAC address */
3136         read_mac_address(ndev, pd->mac_addr);
3137         if (!is_valid_ether_addr(ndev->dev_addr)) {
3138                 dev_warn(&pdev->dev,
3139                          "no valid MAC address supplied, using a random one.\n");
3140                 eth_hw_addr_random(ndev);
3141         }
3142
3143         /* ioremap the TSU registers */
3144         if (mdp->cd->tsu) {
3145                 struct resource *rtsu;
3146                 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3147                 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
3148                 if (IS_ERR(mdp->tsu_addr)) {
3149                         ret = PTR_ERR(mdp->tsu_addr);
3150                         goto out_release;
3151                 }
3152                 mdp->port = devno % 2;
3153                 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
3154         }
3155
3156         /* initialize first or needed device */
3157         if (!devno || pd->needs_init) {
3158                 if (mdp->cd->chip_reset)
3159                         mdp->cd->chip_reset(ndev);
3160
3161                 if (mdp->cd->tsu) {
3162                         /* TSU init (Init only)*/
3163                         sh_eth_tsu_init(mdp);
3164                 }
3165         }
3166
3167         if (mdp->cd->rmiimode)
3168                 sh_eth_write(ndev, 0x1, RMIIMODE);
3169
3170         /* MDIO bus init */
3171         ret = sh_mdio_init(mdp, pd);
3172         if (ret) {
3173                 dev_err(&ndev->dev, "failed to initialise MDIO\n");
3174                 goto out_release;
3175         }
3176
3177         netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
3178
3179         /* network device register */
3180         ret = register_netdev(ndev);
3181         if (ret)
3182                 goto out_napi_del;
3183
3184         /* print device information */
3185         netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
3186                     (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
3187
3188         pm_runtime_put(&pdev->dev);
3189         platform_set_drvdata(pdev, ndev);
3190
3191         return ret;
3192
3193 out_napi_del:
3194         netif_napi_del(&mdp->napi);
3195         sh_mdio_release(mdp);
3196
3197 out_release:
3198         /* net_dev free */
3199         if (ndev)
3200                 free_netdev(ndev);
3201
3202         pm_runtime_put(&pdev->dev);
3203         pm_runtime_disable(&pdev->dev);
3204         return ret;
3205 }
3206
3207 static int sh_eth_drv_remove(struct platform_device *pdev)
3208 {
3209         struct net_device *ndev = platform_get_drvdata(pdev);
3210         struct sh_eth_private *mdp = netdev_priv(ndev);
3211
3212         unregister_netdev(ndev);
3213         netif_napi_del(&mdp->napi);
3214         sh_mdio_release(mdp);
3215         pm_runtime_disable(&pdev->dev);
3216         free_netdev(ndev);
3217
3218         return 0;
3219 }
3220
3221 #ifdef CONFIG_PM
3222 #ifdef CONFIG_PM_SLEEP
3223 static int sh_eth_suspend(struct device *dev)
3224 {
3225         struct net_device *ndev = dev_get_drvdata(dev);
3226         int ret = 0;
3227
3228         if (netif_running(ndev)) {
3229                 netif_device_detach(ndev);
3230                 ret = sh_eth_close(ndev);
3231         }
3232
3233         return ret;
3234 }
3235
3236 static int sh_eth_resume(struct device *dev)
3237 {
3238         struct net_device *ndev = dev_get_drvdata(dev);
3239         int ret = 0;
3240
3241         if (netif_running(ndev)) {
3242                 ret = sh_eth_open(ndev);
3243                 if (ret < 0)
3244                         return ret;
3245                 netif_device_attach(ndev);
3246         }
3247
3248         return ret;
3249 }
3250 #endif
3251
3252 static int sh_eth_runtime_nop(struct device *dev)
3253 {
3254         /* Runtime PM callback shared between ->runtime_suspend()
3255          * and ->runtime_resume(). Simply returns success.
3256          *
3257          * This driver re-initializes all registers after
3258          * pm_runtime_get_sync() anyway so there is no need
3259          * to save and restore registers here.
3260          */
3261         return 0;
3262 }
3263
3264 static const struct dev_pm_ops sh_eth_dev_pm_ops = {
3265         SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume)
3266         SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL)
3267 };
3268 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
3269 #else
3270 #define SH_ETH_PM_OPS NULL
3271 #endif
3272
3273 static struct platform_device_id sh_eth_id_table[] = {
3274         { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
3275         { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
3276         { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
3277         { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
3278         { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
3279         { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
3280         { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
3281         { }
3282 };
3283 MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
3284
3285 static struct platform_driver sh_eth_driver = {
3286         .probe = sh_eth_drv_probe,
3287         .remove = sh_eth_drv_remove,
3288         .id_table = sh_eth_id_table,
3289         .driver = {
3290                    .name = CARDNAME,
3291                    .pm = SH_ETH_PM_OPS,
3292                    .of_match_table = of_match_ptr(sh_eth_match_table),
3293         },
3294 };
3295
3296 module_platform_driver(sh_eth_driver);
3297
3298 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3299 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3300 MODULE_LICENSE("GPL v2");