drivers/net/ethernet/renesas/sh_eth.c

   1 /*  SuperH Ethernet device driver
   2  *
   3  *  Copyright (C) 2014  Renesas Electronics Corporation
   4  *  Copyright (C) 2006-2012 Nobuhiro Iwamatsu
   5  *  Copyright (C) 2008-2014 Renesas Solutions Corp.
   6  *  Copyright (C) 2013-2014 Cogent Embedded, Inc.
   7  *  Copyright (C) 2014 Codethink Limited
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms and conditions of the GNU General Public License,
  11  *  version 2, as published by the Free Software Foundation.
  12  *
  13  *  This program is distributed in the hope it will be useful, but WITHOUT
  14  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  16  *  more details.
  17  *
  18  *  The full GNU General Public License is included in this distribution in
  19  *  the file called "COPYING".
  20  */
  21
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/spinlock.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/etherdevice.h>
  28 #include <linux/delay.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/mdio-bitbang.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/of.h>
  33 #include <linux/of_device.h>
  34 #include <linux/of_irq.h>
  35 #include <linux/of_net.h>
  36 #include <linux/phy.h>
  37 #include <linux/cache.h>
  38 #include <linux/io.h>
  39 #include <linux/pm_runtime.h>
  40 #include <linux/slab.h>
  41 #include <linux/ethtool.h>
  42 #include <linux/if_vlan.h>
  43 #include <linux/clk.h>
  44 #include <linux/sh_eth.h>
  45 #include <linux/of_mdio.h>
  46
  47 #include "sh_eth.h"
  48
  49 #define SH_ETH_DEF_MSG_ENABLE \
  50                 (NETIF_MSG_LINK | \
  51                 NETIF_MSG_TIMER | \
  52                 NETIF_MSG_RX_ERR| \
  53                 NETIF_MSG_TX_ERR)
  54
  55 #define SH_ETH_OFFSET_DEFAULTS                  \
  56         [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID
  57
  58 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
  59         SH_ETH_OFFSET_DEFAULTS,
  60
  61         [EDSR]          = 0x0000,
  62         [EDMR]          = 0x0400,
  63         [EDTRR]         = 0x0408,
  64         [EDRRR]         = 0x0410,
  65         [EESR]          = 0x0428,
  66         [EESIPR]        = 0x0430,
  67         [TDLAR]         = 0x0010,
  68         [TDFAR]         = 0x0014,
  69         [TDFXR]         = 0x0018,
  70         [TDFFR]         = 0x001c,
  71         [RDLAR]         = 0x0030,
  72         [RDFAR]         = 0x0034,
  73         [RDFXR]         = 0x0038,
  74         [RDFFR]         = 0x003c,
  75         [TRSCER]        = 0x0438,
  76         [RMFCR]         = 0x0440,
  77         [TFTR]          = 0x0448,
  78         [FDR]           = 0x0450,
  79         [RMCR]          = 0x0458,
  80         [RPADIR]        = 0x0460,
  81         [FCFTR]         = 0x0468,
  82         [CSMR]          = 0x04E4,
  83
  84         [ECMR]          = 0x0500,
  85         [ECSR]          = 0x0510,
  86         [ECSIPR]        = 0x0518,
  87         [PIR]           = 0x0520,
  88         [PSR]           = 0x0528,
  89         [PIPR]          = 0x052c,
  90         [RFLR]          = 0x0508,
  91         [APR]           = 0x0554,
  92         [MPR]           = 0x0558,
  93         [PFTCR]         = 0x055c,
  94         [PFRCR]         = 0x0560,
  95         [TPAUSER]       = 0x0564,
  96         [GECMR]         = 0x05b0,
  97         [BCULR]         = 0x05b4,
  98         [MAHR]          = 0x05c0,
  99         [MALR]          = 0x05c8,
 100         [TROCR]         = 0x0700,
 101         [CDCR]          = 0x0708,
 102         [LCCR]          = 0x0710,
 103         [CEFCR]         = 0x0740,
 104         [FRECR]         = 0x0748,
 105         [TSFRCR]        = 0x0750,
 106         [TLFRCR]        = 0x0758,
 107         [RFCR]          = 0x0760,
 108         [CERCR]         = 0x0768,
 109         [CEECR]         = 0x0770,
 110         [MAFCR]         = 0x0778,
 111         [RMII_MII]      = 0x0790,
 112
 113         [ARSTR]         = 0x0000,
 114         [TSU_CTRST]     = 0x0004,
 115         [TSU_FWEN0]     = 0x0010,
 116         [TSU_FWEN1]     = 0x0014,
 117         [TSU_FCM]       = 0x0018,
 118         [TSU_BSYSL0]    = 0x0020,
 119         [TSU_BSYSL1]    = 0x0024,
 120         [TSU_PRISL0]    = 0x0028,
 121         [TSU_PRISL1]    = 0x002c,
 122         [TSU_FWSL0]     = 0x0030,
 123         [TSU_FWSL1]     = 0x0034,
 124         [TSU_FWSLC]     = 0x0038,
 125         [TSU_QTAG0]     = 0x0040,
 126         [TSU_QTAG1]     = 0x0044,
 127         [TSU_FWSR]      = 0x0050,
 128         [TSU_FWINMK]    = 0x0054,
 129         [TSU_ADQT0]     = 0x0048,
 130         [TSU_ADQT1]     = 0x004c,
 131         [TSU_VTAG0]     = 0x0058,
 132         [TSU_VTAG1]     = 0x005c,
 133         [TSU_ADSBSY]    = 0x0060,
 134         [TSU_TEN]       = 0x0064,
 135         [TSU_POST1]     = 0x0070,
 136         [TSU_POST2]     = 0x0074,
 137         [TSU_POST3]     = 0x0078,
 138         [TSU_POST4]     = 0x007c,
 139         [TSU_ADRH0]     = 0x0100,
 140
 141         [TXNLCR0]       = 0x0080,
 142         [TXALCR0]       = 0x0084,
 143         [RXNLCR0]       = 0x0088,
 144         [RXALCR0]       = 0x008c,
 145         [FWNLCR0]       = 0x0090,
 146         [FWALCR0]       = 0x0094,
 147         [TXNLCR1]       = 0x00a0,
 148         [TXALCR1]       = 0x00a0,
 149         [RXNLCR1]       = 0x00a8,
 150         [RXALCR1]       = 0x00ac,
 151         [FWNLCR1]       = 0x00b0,
 152         [FWALCR1]       = 0x00b4,
 153 };
 154
 155 static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
 156         SH_ETH_OFFSET_DEFAULTS,
 157
 158         [EDSR]          = 0x0000,
 159         [EDMR]          = 0x0400,
 160         [EDTRR]         = 0x0408,
 161         [EDRRR]         = 0x0410,
 162         [EESR]          = 0x0428,
 163         [EESIPR]        = 0x0430,
 164         [TDLAR]         = 0x0010,
 165         [TDFAR]         = 0x0014,
 166         [TDFXR]         = 0x0018,
 167         [TDFFR]         = 0x001c,
 168         [RDLAR]         = 0x0030,
 169         [RDFAR]         = 0x0034,
 170         [RDFXR]         = 0x0038,
 171         [RDFFR]         = 0x003c,
 172         [TRSCER]        = 0x0438,
 173         [RMFCR]         = 0x0440,
 174         [TFTR]          = 0x0448,
 175         [FDR]           = 0x0450,
 176         [RMCR]          = 0x0458,
 177         [RPADIR]        = 0x0460,
 178         [FCFTR]         = 0x0468,
 179         [CSMR]          = 0x04E4,
 180
 181         [ECMR]          = 0x0500,
 182         [RFLR]          = 0x0508,
 183         [ECSR]          = 0x0510,
 184         [ECSIPR]        = 0x0518,
 185         [PIR]           = 0x0520,
 186         [APR]           = 0x0554,
 187         [MPR]           = 0x0558,
 188         [PFTCR]         = 0x055c,
 189         [PFRCR]         = 0x0560,
 190         [TPAUSER]       = 0x0564,
 191         [MAHR]          = 0x05c0,
 192         [MALR]          = 0x05c8,
 193         [CEFCR]         = 0x0740,
 194         [FRECR]         = 0x0748,
 195         [TSFRCR]        = 0x0750,
 196         [TLFRCR]        = 0x0758,
 197         [RFCR]          = 0x0760,
 198         [MAFCR]         = 0x0778,
 199
 200         [ARSTR]         = 0x0000,
 201         [TSU_CTRST]     = 0x0004,
 202         [TSU_VTAG0]     = 0x0058,
 203         [TSU_ADSBSY]    = 0x0060,
 204         [TSU_TEN]       = 0x0064,
 205         [TSU_ADRH0]     = 0x0100,
 206
 207         [TXNLCR0]       = 0x0080,
 208         [TXALCR0]       = 0x0084,
 209         [RXNLCR0]       = 0x0088,
 210         [RXALCR0]       = 0x008C,
 211 };
 212
 213 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
 214         SH_ETH_OFFSET_DEFAULTS,
 215
 216         [ECMR]          = 0x0300,
 217         [RFLR]          = 0x0308,
 218         [ECSR]          = 0x0310,
 219         [ECSIPR]        = 0x0318,
 220         [PIR]           = 0x0320,
 221         [PSR]           = 0x0328,
 222         [RDMLR]         = 0x0340,
 223         [IPGR]          = 0x0350,
 224         [APR]           = 0x0354,
 225         [MPR]           = 0x0358,
 226         [RFCF]          = 0x0360,
 227         [TPAUSER]       = 0x0364,
 228         [TPAUSECR]      = 0x0368,
 229         [MAHR]          = 0x03c0,
 230         [MALR]          = 0x03c8,
 231         [TROCR]         = 0x03d0,
 232         [CDCR]          = 0x03d4,
 233         [LCCR]          = 0x03d8,
 234         [CNDCR]         = 0x03dc,
 235         [CEFCR]         = 0x03e4,
 236         [FRECR]         = 0x03e8,
 237         [TSFRCR]        = 0x03ec,
 238         [TLFRCR]        = 0x03f0,
 239         [RFCR]          = 0x03f4,
 240         [MAFCR]         = 0x03f8,
 241
 242         [EDMR]          = 0x0200,
 243         [EDTRR]         = 0x0208,
 244         [EDRRR]         = 0x0210,
 245         [TDLAR]         = 0x0218,
 246         [RDLAR]         = 0x0220,
 247         [EESR]          = 0x0228,
 248         [EESIPR]        = 0x0230,
 249         [TRSCER]        = 0x0238,
 250         [RMFCR]         = 0x0240,
 251         [TFTR]          = 0x0248,
 252         [FDR]           = 0x0250,
 253         [RMCR]          = 0x0258,
 254         [TFUCR]         = 0x0264,
 255         [RFOCR]         = 0x0268,
 256         [RMIIMODE]      = 0x026c,
 257         [FCFTR]         = 0x0270,
 258         [TRIMD]         = 0x027c,
 259 };
 260
 261 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
 262         SH_ETH_OFFSET_DEFAULTS,
 263
 264         [ECMR]          = 0x0100,
 265         [RFLR]          = 0x0108,
 266         [ECSR]          = 0x0110,
 267         [ECSIPR]        = 0x0118,
 268         [PIR]           = 0x0120,
 269         [PSR]           = 0x0128,
 270         [RDMLR]         = 0x0140,
 271         [IPGR]          = 0x0150,
 272         [APR]           = 0x0154,
 273         [MPR]           = 0x0158,
 274         [TPAUSER]       = 0x0164,
 275         [RFCF]          = 0x0160,
 276         [TPAUSECR]      = 0x0168,
 277         [BCFRR]         = 0x016c,
 278         [MAHR]          = 0x01c0,
 279         [MALR]          = 0x01c8,
 280         [TROCR]         = 0x01d0,
 281         [CDCR]          = 0x01d4,
 282         [LCCR]          = 0x01d8,
 283         [CNDCR]         = 0x01dc,
 284         [CEFCR]         = 0x01e4,
 285         [FRECR]         = 0x01e8,
 286         [TSFRCR]        = 0x01ec,
 287         [TLFRCR]        = 0x01f0,
 288         [RFCR]          = 0x01f4,
 289         [MAFCR]         = 0x01f8,
 290         [RTRATE]        = 0x01fc,
 291
 292         [EDMR]          = 0x0000,
 293         [EDTRR]         = 0x0008,
 294         [EDRRR]         = 0x0010,
 295         [TDLAR]         = 0x0018,
 296         [RDLAR]         = 0x0020,
 297         [EESR]          = 0x0028,
 298         [EESIPR]        = 0x0030,
 299         [TRSCER]        = 0x0038,
 300         [RMFCR]         = 0x0040,
 301         [TFTR]          = 0x0048,
 302         [FDR]           = 0x0050,
 303         [RMCR]          = 0x0058,
 304         [TFUCR]         = 0x0064,
 305         [RFOCR]         = 0x0068,
 306         [FCFTR]         = 0x0070,
 307         [RPADIR]        = 0x0078,
 308         [TRIMD]         = 0x007c,
 309         [RBWAR]         = 0x00c8,
 310         [RDFAR]         = 0x00cc,
 311         [TBRAR]         = 0x00d4,
 312         [TDFAR]         = 0x00d8,
 313 };
 314
 315 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
 316         SH_ETH_OFFSET_DEFAULTS,
 317
 318         [EDMR]          = 0x0000,
 319         [EDTRR]         = 0x0004,
 320         [EDRRR]         = 0x0008,
 321         [TDLAR]         = 0x000c,
 322         [RDLAR]         = 0x0010,
 323         [EESR]          = 0x0014,
 324         [EESIPR]        = 0x0018,
 325         [TRSCER]        = 0x001c,
 326         [RMFCR]         = 0x0020,
 327         [TFTR]          = 0x0024,
 328         [FDR]           = 0x0028,
 329         [RMCR]          = 0x002c,
 330         [EDOCR]         = 0x0030,
 331         [FCFTR]         = 0x0034,
 332         [RPADIR]        = 0x0038,
 333         [TRIMD]         = 0x003c,
 334         [RBWAR]         = 0x0040,
 335         [RDFAR]         = 0x0044,
 336         [TBRAR]         = 0x004c,
 337         [TDFAR]         = 0x0050,
 338
 339         [ECMR]          = 0x0160,
 340         [ECSR]          = 0x0164,
 341         [ECSIPR]        = 0x0168,
 342         [PIR]           = 0x016c,
 343         [MAHR]          = 0x0170,
 344         [MALR]          = 0x0174,
 345         [RFLR]          = 0x0178,
 346         [PSR]           = 0x017c,
 347         [TROCR]         = 0x0180,
 348         [CDCR]          = 0x0184,
 349         [LCCR]          = 0x0188,
 350         [CNDCR]         = 0x018c,
 351         [CEFCR]         = 0x0194,
 352         [FRECR]         = 0x0198,
 353         [TSFRCR]        = 0x019c,
 354         [TLFRCR]        = 0x01a0,
 355         [RFCR]          = 0x01a4,
 356         [MAFCR]         = 0x01a8,
 357         [IPGR]          = 0x01b4,
 358         [APR]           = 0x01b8,
 359         [MPR]           = 0x01bc,
 360         [TPAUSER]       = 0x01c4,
 361         [BCFR]          = 0x01cc,
 362
 363         [ARSTR]         = 0x0000,
 364         [TSU_CTRST]     = 0x0004,
 365         [TSU_FWEN0]     = 0x0010,
 366         [TSU_FWEN1]     = 0x0014,
 367         [TSU_FCM]       = 0x0018,
 368         [TSU_BSYSL0]    = 0x0020,
 369         [TSU_BSYSL1]    = 0x0024,
 370         [TSU_PRISL0]    = 0x0028,
 371         [TSU_PRISL1]    = 0x002c,
 372         [TSU_FWSL0]     = 0x0030,
 373         [TSU_FWSL1]     = 0x0034,
 374         [TSU_FWSLC]     = 0x0038,
 375         [TSU_QTAGM0]    = 0x0040,
 376         [TSU_QTAGM1]    = 0x0044,
 377         [TSU_ADQT0]     = 0x0048,
 378         [TSU_ADQT1]     = 0x004c,
 379         [TSU_FWSR]      = 0x0050,
 380         [TSU_FWINMK]    = 0x0054,
 381         [TSU_ADSBSY]    = 0x0060,
 382         [TSU_TEN]       = 0x0064,
 383         [TSU_POST1]     = 0x0070,
 384         [TSU_POST2]     = 0x0074,
 385         [TSU_POST3]     = 0x0078,
 386         [TSU_POST4]     = 0x007c,
 387
 388         [TXNLCR0]       = 0x0080,
 389         [TXALCR0]       = 0x0084,
 390         [RXNLCR0]       = 0x0088,
 391         [RXALCR0]       = 0x008c,
 392         [FWNLCR0]       = 0x0090,
 393         [FWALCR0]       = 0x0094,
 394         [TXNLCR1]       = 0x00a0,
 395         [TXALCR1]       = 0x00a0,
 396         [RXNLCR1]       = 0x00a8,
 397         [RXALCR1]       = 0x00ac,
 398         [FWNLCR1]       = 0x00b0,
 399         [FWALCR1]       = 0x00b4,
 400
 401         [TSU_ADRH0]     = 0x0100,
 402 };
 403
 404 static void sh_eth_rcv_snd_disable(struct net_device *ndev);
 405 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev);
 406
 407 static bool sh_eth_is_gether(struct sh_eth_private *mdp)
 408 {
 409         return mdp->reg_offset == sh_eth_offset_gigabit;
 410 }
 411
 412 static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp)
 413 {
 414         return mdp->reg_offset == sh_eth_offset_fast_rz;
 415 }
 416
 417 static void sh_eth_select_mii(struct net_device *ndev)
 418 {
 419         u32 value = 0x0;
 420         struct sh_eth_private *mdp = netdev_priv(ndev);
 421
 422         switch (mdp->phy_interface) {
 423         case PHY_INTERFACE_MODE_GMII:
 424                 value = 0x2;
 425                 break;
 426         case PHY_INTERFACE_MODE_MII:
 427                 value = 0x1;
 428                 break;
 429         case PHY_INTERFACE_MODE_RMII:
 430                 value = 0x0;
 431                 break;
 432         default:
 433                 netdev_warn(ndev,
 434                             "PHY interface mode was not setup. Set to MII.\n");
 435                 value = 0x1;
 436                 break;
 437         }
 438
 439         sh_eth_write(ndev, value, RMII_MII);
 440 }
 441
 442 static void sh_eth_set_duplex(struct net_device *ndev)
 443 {
 444         struct sh_eth_private *mdp = netdev_priv(ndev);
 445
 446         if (mdp->duplex) /* Full */
 447                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
 448         else            /* Half */
 449                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
 450 }
 451
 452 /* There is CPU dependent code */
 453 static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
 454 {
 455         struct sh_eth_private *mdp = netdev_priv(ndev);
 456
 457         switch (mdp->speed) {
 458         case 10: /* 10BASE */
 459                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_ELB, ECMR);
 460                 break;
 461         case 100:/* 100BASE */
 462                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_ELB, ECMR);
 463                 break;
 464         default:
 465                 break;
 466         }
 467 }
 468
 469 /* R8A7778/9 */
 470 static struct sh_eth_cpu_data r8a777x_data = {
 471         .set_duplex     = sh_eth_set_duplex,
 472         .set_rate       = sh_eth_set_rate_r8a777x,
 473
 474         .register_type  = SH_ETH_REG_FAST_RCAR,
 475
 476         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 477         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 478         .eesipr_value   = 0x01ff009f,
 479
 480         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 481         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 482                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 483                           EESR_ECI,
 484         .fdr_value      = 0x00000f0f,
 485
 486         .apr            = 1,
 487         .mpr            = 1,
 488         .tpauser        = 1,
 489         .hw_swap        = 1,
 490 };
 491
 492 /* R8A7790/1 */
 493 static struct sh_eth_cpu_data r8a779x_data = {
 494         .set_duplex     = sh_eth_set_duplex,
 495         .set_rate       = sh_eth_set_rate_r8a777x,
 496
 497         .register_type  = SH_ETH_REG_FAST_RCAR,
 498
 499         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 500         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 501         .eesipr_value   = 0x01ff009f,
 502
 503         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 504         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 505                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 506                           EESR_ECI,
 507         .fdr_value      = 0x00000f0f,
 508
 509         .trscer_err_mask = DESC_I_RINT8,
 510
 511         .apr            = 1,
 512         .mpr            = 1,
 513         .tpauser        = 1,
 514         .hw_swap        = 1,
 515         .rmiimode       = 1,
 516 };
 517
 518 static void sh_eth_set_rate_sh7724(struct net_device *ndev)
 519 {
 520         struct sh_eth_private *mdp = netdev_priv(ndev);
 521
 522         switch (mdp->speed) {
 523         case 10: /* 10BASE */
 524                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR);
 525                 break;
 526         case 100:/* 100BASE */
 527                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR);
 528                 break;
 529         default:
 530                 break;
 531         }
 532 }
 533
 534 /* SH7724 */
 535 static struct sh_eth_cpu_data sh7724_data = {
 536         .set_duplex     = sh_eth_set_duplex,
 537         .set_rate       = sh_eth_set_rate_sh7724,
 538
 539         .register_type  = SH_ETH_REG_FAST_SH4,
 540
 541         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 542         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 543         .eesipr_value   = 0x01ff009f,
 544
 545         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 546         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 547                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 548                           EESR_ECI,
 549
 550         .apr            = 1,
 551         .mpr            = 1,
 552         .tpauser        = 1,
 553         .hw_swap        = 1,
 554         .rpadir         = 1,
 555         .rpadir_value   = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
 556 };
 557
 558 static void sh_eth_set_rate_sh7757(struct net_device *ndev)
 559 {
 560         struct sh_eth_private *mdp = netdev_priv(ndev);
 561
 562         switch (mdp->speed) {
 563         case 10: /* 10BASE */
 564                 sh_eth_write(ndev, 0, RTRATE);
 565                 break;
 566         case 100:/* 100BASE */
 567                 sh_eth_write(ndev, 1, RTRATE);
 568                 break;
 569         default:
 570                 break;
 571         }
 572 }
 573
 574 /* SH7757 */
 575 static struct sh_eth_cpu_data sh7757_data = {
 576         .set_duplex     = sh_eth_set_duplex,
 577         .set_rate       = sh_eth_set_rate_sh7757,
 578
 579         .register_type  = SH_ETH_REG_FAST_SH4,
 580
 581         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 582
 583         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 584         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 585                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 586                           EESR_ECI,
 587
 588         .irq_flags      = IRQF_SHARED,
 589         .apr            = 1,
 590         .mpr            = 1,
 591         .tpauser        = 1,
 592         .hw_swap        = 1,
 593         .no_ade         = 1,
 594         .rpadir         = 1,
 595         .rpadir_value   = 2 << 16,
 596         .rtrate         = 1,
 597 };
 598
 599 #define SH_GIGA_ETH_BASE        0xfee00000UL
 600 #define GIGA_MALR(port)         (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
 601 #define GIGA_MAHR(port)         (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
 602 static void sh_eth_chip_reset_giga(struct net_device *ndev)
 603 {
 604         int i;
 605         u32 mahr[2], malr[2];
 606
 607         /* save MAHR and MALR */
 608         for (i = 0; i < 2; i++) {
 609                 malr[i] = ioread32((void *)GIGA_MALR(i));
 610                 mahr[i] = ioread32((void *)GIGA_MAHR(i));
 611         }
 612
 613         /* reset device */
 614         iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800));
 615         mdelay(1);
 616
 617         /* restore MAHR and MALR */
 618         for (i = 0; i < 2; i++) {
 619                 iowrite32(malr[i], (void *)GIGA_MALR(i));
 620                 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
 621         }
 622 }
 623
 624 static void sh_eth_set_rate_giga(struct net_device *ndev)
 625 {
 626         struct sh_eth_private *mdp = netdev_priv(ndev);
 627
 628         switch (mdp->speed) {
 629         case 10: /* 10BASE */
 630                 sh_eth_write(ndev, 0x00000000, GECMR);
 631                 break;
 632         case 100:/* 100BASE */
 633                 sh_eth_write(ndev, 0x00000010, GECMR);
 634                 break;
 635         case 1000: /* 1000BASE */
 636                 sh_eth_write(ndev, 0x00000020, GECMR);
 637                 break;
 638         default:
 639                 break;
 640         }
 641 }
 642
 643 /* SH7757(GETHERC) */
 644 static struct sh_eth_cpu_data sh7757_data_giga = {
 645         .chip_reset     = sh_eth_chip_reset_giga,
 646         .set_duplex     = sh_eth_set_duplex,
 647         .set_rate       = sh_eth_set_rate_giga,
 648
 649         .register_type  = SH_ETH_REG_GIGABIT,
 650
 651         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 652         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 653         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 654
 655         .tx_check       = EESR_TC1 | EESR_FTC,
 656         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 657                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 658                           EESR_TDE | EESR_ECI,
 659         .fdr_value      = 0x0000072f,
 660
 661         .irq_flags      = IRQF_SHARED,
 662         .apr            = 1,
 663         .mpr            = 1,
 664         .tpauser        = 1,
 665         .bculr          = 1,
 666         .hw_swap        = 1,
 667         .rpadir         = 1,
 668         .rpadir_value   = 2 << 16,
 669         .no_trimd       = 1,
 670         .no_ade         = 1,
 671         .tsu            = 1,
 672 };
 673
 674 static void sh_eth_chip_reset(struct net_device *ndev)
 675 {
 676         struct sh_eth_private *mdp = netdev_priv(ndev);
 677
 678         /* reset device */
 679         sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
 680         mdelay(1);
 681 }
 682
 683 static void sh_eth_set_rate_gether(struct net_device *ndev)
 684 {
 685         struct sh_eth_private *mdp = netdev_priv(ndev);
 686
 687         switch (mdp->speed) {
 688         case 10: /* 10BASE */
 689                 sh_eth_write(ndev, GECMR_10, GECMR);
 690                 break;
 691         case 100:/* 100BASE */
 692                 sh_eth_write(ndev, GECMR_100, GECMR);
 693                 break;
 694         case 1000: /* 1000BASE */
 695                 sh_eth_write(ndev, GECMR_1000, GECMR);
 696                 break;
 697         default:
 698                 break;
 699         }
 700 }
 701
 702 /* SH7734 */
 703 static struct sh_eth_cpu_data sh7734_data = {
 704         .chip_reset     = sh_eth_chip_reset,
 705         .set_duplex     = sh_eth_set_duplex,
 706         .set_rate       = sh_eth_set_rate_gether,
 707
 708         .register_type  = SH_ETH_REG_GIGABIT,
 709
 710         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 711         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 712         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 713
 714         .tx_check       = EESR_TC1 | EESR_FTC,
 715         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 716                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 717                           EESR_TDE | EESR_ECI,
 718
 719         .apr            = 1,
 720         .mpr            = 1,
 721         .tpauser        = 1,
 722         .bculr          = 1,
 723         .hw_swap        = 1,
 724         .no_trimd       = 1,
 725         .no_ade         = 1,
 726         .tsu            = 1,
 727         .hw_crc         = 1,
 728         .select_mii     = 1,
 729 };
 730
 731 /* SH7763 */
 732 static struct sh_eth_cpu_data sh7763_data = {
 733         .chip_reset     = sh_eth_chip_reset,
 734         .set_duplex     = sh_eth_set_duplex,
 735         .set_rate       = sh_eth_set_rate_gether,
 736
 737         .register_type  = SH_ETH_REG_GIGABIT,
 738
 739         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 740         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 741         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 742
 743         .tx_check       = EESR_TC1 | EESR_FTC,
 744         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 745                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 746                           EESR_ECI,
 747
 748         .apr            = 1,
 749         .mpr            = 1,
 750         .tpauser        = 1,
 751         .bculr          = 1,
 752         .hw_swap        = 1,
 753         .no_trimd       = 1,
 754         .no_ade         = 1,
 755         .tsu            = 1,
 756         .irq_flags      = IRQF_SHARED,
 757 };
 758
 759 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
 760 {
 761         struct sh_eth_private *mdp = netdev_priv(ndev);
 762
 763         /* reset device */
 764         sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
 765         mdelay(1);
 766
 767         sh_eth_select_mii(ndev);
 768 }
 769
 770 /* R8A7740 */
 771 static struct sh_eth_cpu_data r8a7740_data = {
 772         .chip_reset     = sh_eth_chip_reset_r8a7740,
 773         .set_duplex     = sh_eth_set_duplex,
 774         .set_rate       = sh_eth_set_rate_gether,
 775
 776         .register_type  = SH_ETH_REG_GIGABIT,
 777
 778         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 779         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 780         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 781
 782         .tx_check       = EESR_TC1 | EESR_FTC,
 783         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 784                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 785                           EESR_TDE | EESR_ECI,
 786         .fdr_value      = 0x0000070f,
 787
 788         .apr            = 1,
 789         .mpr            = 1,
 790         .tpauser        = 1,
 791         .bculr          = 1,
 792         .hw_swap        = 1,
 793         .rpadir         = 1,
 794         .rpadir_value   = 2 << 16,
 795         .no_trimd       = 1,
 796         .no_ade         = 1,
 797         .tsu            = 1,
 798         .select_mii     = 1,
 799         .shift_rd0      = 1,
 800 };
 801
 802 /* R7S72100 */
 803 static struct sh_eth_cpu_data r7s72100_data = {
 804         .chip_reset     = sh_eth_chip_reset,
 805         .set_duplex     = sh_eth_set_duplex,
 806
 807         .register_type  = SH_ETH_REG_FAST_RZ,
 808
 809         .ecsr_value     = ECSR_ICD,
 810         .ecsipr_value   = ECSIPR_ICDIP,
 811         .eesipr_value   = 0xff7f009f,
 812
 813         .tx_check       = EESR_TC1 | EESR_FTC,
 814         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 815                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 816                           EESR_TDE | EESR_ECI,
 817         .fdr_value      = 0x0000070f,
 818
 819         .no_psr         = 1,
 820         .apr            = 1,
 821         .mpr            = 1,
 822         .tpauser        = 1,
 823         .hw_swap        = 1,
 824         .rpadir         = 1,
 825         .rpadir_value   = 2 << 16,
 826         .no_trimd       = 1,
 827         .no_ade         = 1,
 828         .hw_crc         = 1,
 829         .tsu            = 1,
 830         .shift_rd0      = 1,
 831 };
 832
 833 static struct sh_eth_cpu_data sh7619_data = {
 834         .register_type  = SH_ETH_REG_FAST_SH3_SH2,
 835
 836         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 837
 838         .apr            = 1,
 839         .mpr            = 1,
 840         .tpauser        = 1,
 841         .hw_swap        = 1,
 842 };
 843
 844 static struct sh_eth_cpu_data sh771x_data = {
 845         .register_type  = SH_ETH_REG_FAST_SH3_SH2,
 846
 847         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 848         .tsu            = 1,
 849 };
 850
 851 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
 852 {
 853         if (!cd->ecsr_value)
 854                 cd->ecsr_value = DEFAULT_ECSR_INIT;
 855
 856         if (!cd->ecsipr_value)
 857                 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
 858
 859         if (!cd->fcftr_value)
 860                 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
 861                                   DEFAULT_FIFO_F_D_RFD;
 862
 863         if (!cd->fdr_value)
 864                 cd->fdr_value = DEFAULT_FDR_INIT;
 865
 866         if (!cd->tx_check)
 867                 cd->tx_check = DEFAULT_TX_CHECK;
 868
 869         if (!cd->eesr_err_check)
 870                 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
 871
 872         if (!cd->trscer_err_mask)
 873                 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK;
 874 }
 875
 876 static int sh_eth_check_reset(struct net_device *ndev)
 877 {
 878         int ret = 0;
 879         int cnt = 100;
 880
 881         while (cnt > 0) {
 882                 if (!(sh_eth_read(ndev, EDMR) & 0x3))
 883                         break;
 884                 mdelay(1);
 885                 cnt--;
 886         }
 887         if (cnt <= 0) {
 888                 netdev_err(ndev, "Device reset failed\n");
 889                 ret = -ETIMEDOUT;
 890         }
 891         return ret;
 892 }
 893
 894 static int sh_eth_reset(struct net_device *ndev)
 895 {
 896         struct sh_eth_private *mdp = netdev_priv(ndev);
 897         int ret = 0;
 898
 899         if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) {
 900                 sh_eth_write(ndev, EDSR_ENALL, EDSR);
 901                 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
 902                              EDMR);
 903
 904                 ret = sh_eth_check_reset(ndev);
 905                 if (ret)
 906                         return ret;
 907
 908                 /* Table Init */
 909                 sh_eth_write(ndev, 0x0, TDLAR);
 910                 sh_eth_write(ndev, 0x0, TDFAR);
 911                 sh_eth_write(ndev, 0x0, TDFXR);
 912                 sh_eth_write(ndev, 0x0, TDFFR);
 913                 sh_eth_write(ndev, 0x0, RDLAR);
 914                 sh_eth_write(ndev, 0x0, RDFAR);
 915                 sh_eth_write(ndev, 0x0, RDFXR);
 916                 sh_eth_write(ndev, 0x0, RDFFR);
 917
 918                 /* Reset HW CRC register */
 919                 if (mdp->cd->hw_crc)
 920                         sh_eth_write(ndev, 0x0, CSMR);
 921
 922                 /* Select MII mode */
 923                 if (mdp->cd->select_mii)
 924                         sh_eth_select_mii(ndev);
 925         } else {
 926                 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,
 927                              EDMR);
 928                 mdelay(3);
 929                 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
 930                              EDMR);
 931         }
 932
 933         return ret;
 934 }
 935
 936 static void sh_eth_set_receive_align(struct sk_buff *skb)
 937 {
 938         uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1);
 939
 940         if (reserve)
 941                 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve);
 942 }
 943
 944
 945 /* CPU <-> EDMAC endian convert */
 946 static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
 947 {
 948         switch (mdp->edmac_endian) {
 949         case EDMAC_LITTLE_ENDIAN:
 950                 return cpu_to_le32(x);
 951         case EDMAC_BIG_ENDIAN:
 952                 return cpu_to_be32(x);
 953         }
 954         return x;
 955 }
 956
 957 static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
 958 {
 959         switch (mdp->edmac_endian) {
 960         case EDMAC_LITTLE_ENDIAN:
 961                 return le32_to_cpu(x);
 962         case EDMAC_BIG_ENDIAN:
 963                 return be32_to_cpu(x);
 964         }
 965         return x;
 966 }
 967
 968 /* Program the hardware MAC address from dev->dev_addr. */
 969 static void update_mac_address(struct net_device *ndev)
 970 {
 971         sh_eth_write(ndev,
 972                      (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
 973                      (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
 974         sh_eth_write(ndev,
 975                      (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
 976 }
 977
 978 /* Get MAC address from SuperH MAC address register
 979  *
 980  * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
 981  * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
 982  * When you want use this device, you must set MAC address in bootloader.
 983  *
 984  */
 985 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
 986 {
 987         if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
 988                 memcpy(ndev->dev_addr, mac, ETH_ALEN);
 989         } else {
 990                 ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24);
 991                 ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF;
 992                 ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF;
 993                 ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF);
 994                 ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF;
 995                 ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF);
 996         }
 997 }
 998
 999 static u32 sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
1000 {
1001         if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp))
1002                 return EDTRR_TRNS_GETHER;
1003         else
1004                 return EDTRR_TRNS_ETHER;
1005 }
1006
1007 struct bb_info {
1008         void (*set_gate)(void *addr);
1009         struct mdiobb_ctrl ctrl;
1010         void *addr;
1011         u32 mmd_msk;/* MMD */
1012         u32 mdo_msk;
1013         u32 mdi_msk;
1014         u32 mdc_msk;
1015 };
1016
1017 /* PHY bit set */
1018 static void bb_set(void *addr, u32 msk)
1019 {
1020         iowrite32(ioread32(addr) | msk, addr);
1021 }
1022
1023 /* PHY bit clear */
1024 static void bb_clr(void *addr, u32 msk)
1025 {
1026         iowrite32((ioread32(addr) & ~msk), addr);
1027 }
1028
1029 /* PHY bit read */
1030 static int bb_read(void *addr, u32 msk)
1031 {
1032         return (ioread32(addr) & msk) != 0;
1033 }
1034
1035 /* Data I/O pin control */
1036 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1037 {
1038         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1039
1040         if (bitbang->set_gate)
1041                 bitbang->set_gate(bitbang->addr);
1042
1043         if (bit)
1044                 bb_set(bitbang->addr, bitbang->mmd_msk);
1045         else
1046                 bb_clr(bitbang->addr, bitbang->mmd_msk);
1047 }
1048
1049 /* Set bit data*/
1050 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1051 {
1052         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1053
1054         if (bitbang->set_gate)
1055                 bitbang->set_gate(bitbang->addr);
1056
1057         if (bit)
1058                 bb_set(bitbang->addr, bitbang->mdo_msk);
1059         else
1060                 bb_clr(bitbang->addr, bitbang->mdo_msk);
1061 }
1062
1063 /* Get bit data*/
1064 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1065 {
1066         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1067
1068         if (bitbang->set_gate)
1069                 bitbang->set_gate(bitbang->addr);
1070
1071         return bb_read(bitbang->addr, bitbang->mdi_msk);
1072 }
1073
1074 /* MDC pin control */
1075 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1076 {
1077         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1078
1079         if (bitbang->set_gate)
1080                 bitbang->set_gate(bitbang->addr);
1081
1082         if (bit)
1083                 bb_set(bitbang->addr, bitbang->mdc_msk);
1084         else
1085                 bb_clr(bitbang->addr, bitbang->mdc_msk);
1086 }
1087
1088 /* mdio bus control struct */
1089 static struct mdiobb_ops bb_ops = {
1090         .owner = THIS_MODULE,
1091         .set_mdc = sh_mdc_ctrl,
1092         .set_mdio_dir = sh_mmd_ctrl,
1093         .set_mdio_data = sh_set_mdio,
1094         .get_mdio_data = sh_get_mdio,
1095 };
1096
1097 /* free skb and descriptor buffer */
1098 static void sh_eth_ring_free(struct net_device *ndev)
1099 {
1100         struct sh_eth_private *mdp = netdev_priv(ndev);
1101         int ringsize, i;
1102
1103         /* Free Rx skb ringbuffer */
1104         if (mdp->rx_skbuff) {
1105                 for (i = 0; i < mdp->num_rx_ring; i++)
1106                         dev_kfree_skb(mdp->rx_skbuff[i]);
1107         }
1108         kfree(mdp->rx_skbuff);
1109         mdp->rx_skbuff = NULL;
1110
1111         /* Free Tx skb ringbuffer */
1112         if (mdp->tx_skbuff) {
1113                 for (i = 0; i < mdp->num_tx_ring; i++)
1114                         dev_kfree_skb(mdp->tx_skbuff[i]);
1115         }
1116         kfree(mdp->tx_skbuff);
1117         mdp->tx_skbuff = NULL;
1118
1119         if (mdp->rx_ring) {
1120                 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1121                 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1122                                   mdp->rx_desc_dma);
1123                 mdp->rx_ring = NULL;
1124         }
1125
1126         if (mdp->tx_ring) {
1127                 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1128                 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1129                                   mdp->tx_desc_dma);
1130                 mdp->tx_ring = NULL;
1131         }
1132 }
1133
1134 /* format skb and descriptor buffer */
1135 static void sh_eth_ring_format(struct net_device *ndev)
1136 {
1137         struct sh_eth_private *mdp = netdev_priv(ndev);
1138         int i;
1139         struct sk_buff *skb;
1140         struct sh_eth_rxdesc *rxdesc = NULL;
1141         struct sh_eth_txdesc *txdesc = NULL;
1142         int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1143         int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
1144         int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1145         dma_addr_t dma_addr;
1146
1147         mdp->cur_rx = 0;
1148         mdp->cur_tx = 0;
1149         mdp->dirty_rx = 0;
1150         mdp->dirty_tx = 0;
1151
1152         memset(mdp->rx_ring, 0, rx_ringsize);
1153
1154         /* build Rx ring buffer */
1155         for (i = 0; i < mdp->num_rx_ring; i++) {
1156                 /* skb */
1157                 mdp->rx_skbuff[i] = NULL;
1158                 skb = netdev_alloc_skb(ndev, skbuff_size);
1159                 if (skb == NULL)
1160                         break;
1161                 sh_eth_set_receive_align(skb);
1162
1163                 /* RX descriptor */
1164                 rxdesc = &mdp->rx_ring[i];
1165                 /* The size of the buffer is a multiple of 32 bytes. */
1166                 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 32);
1167                 dma_addr = dma_map_single(&ndev->dev, skb->data,
1168                                           rxdesc->buffer_length,
1169                                           DMA_FROM_DEVICE);
1170                 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1171                         kfree_skb(skb);
1172                         break;
1173                 }
1174                 mdp->rx_skbuff[i] = skb;
1175                 rxdesc->addr = dma_addr;
1176                 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1177
1178                 /* Rx descriptor address set */
1179                 if (i == 0) {
1180                         sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
1181                         if (sh_eth_is_gether(mdp) ||
1182                             sh_eth_is_rz_fast_ether(mdp))
1183                                 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
1184                 }
1185         }
1186
1187         mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
1188
1189         /* Mark the last entry as wrapping the ring. */
1190         rxdesc->status |= cpu_to_edmac(mdp, RD_RDLE);
1191
1192         memset(mdp->tx_ring, 0, tx_ringsize);
1193
1194         /* build Tx ring buffer */
1195         for (i = 0; i < mdp->num_tx_ring; i++) {
1196                 mdp->tx_skbuff[i] = NULL;
1197                 txdesc = &mdp->tx_ring[i];
1198                 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1199                 txdesc->buffer_length = 0;
1200                 if (i == 0) {
1201                         /* Tx descriptor address set */
1202                         sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
1203                         if (sh_eth_is_gether(mdp) ||
1204                             sh_eth_is_rz_fast_ether(mdp))
1205                                 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
1206                 }
1207         }
1208
1209         txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1210 }
1211
1212 /* Get skb and descriptor buffer */
1213 static int sh_eth_ring_init(struct net_device *ndev)
1214 {
1215         struct sh_eth_private *mdp = netdev_priv(ndev);
1216         int rx_ringsize, tx_ringsize;
1217
1218         /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1219          * card needs room to do 8 byte alignment, +2 so we can reserve
1220          * the first 2 bytes, and +16 gets room for the status word from the
1221          * card.
1222          */
1223         mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1224                           (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
1225         if (mdp->cd->rpadir)
1226                 mdp->rx_buf_sz += NET_IP_ALIGN;
1227
1228         /* Allocate RX and TX skb rings */
1229         mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff),
1230                                  GFP_KERNEL);
1231         if (!mdp->rx_skbuff)
1232                 return -ENOMEM;
1233
1234         mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff),
1235                                  GFP_KERNEL);
1236         if (!mdp->tx_skbuff)
1237                 goto ring_free;
1238
1239         /* Allocate all Rx descriptors. */
1240         rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1241         mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
1242                                           GFP_KERNEL);
1243         if (!mdp->rx_ring)
1244                 goto ring_free;
1245
1246         mdp->dirty_rx = 0;
1247
1248         /* Allocate all Tx descriptors. */
1249         tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1250         mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
1251                                           GFP_KERNEL);
1252         if (!mdp->tx_ring)
1253                 goto ring_free;
1254         return 0;
1255
1256 ring_free:
1257         /* Free Rx and Tx skb ring buffer and DMA buffer */
1258         sh_eth_ring_free(ndev);
1259
1260         return -ENOMEM;
1261 }
1262
1263 static int sh_eth_dev_init(struct net_device *ndev, bool start)
1264 {
1265         int ret = 0;
1266         struct sh_eth_private *mdp = netdev_priv(ndev);
1267         u32 val;
1268
1269         /* Soft Reset */
1270         ret = sh_eth_reset(ndev);
1271         if (ret)
1272                 return ret;
1273
1274         if (mdp->cd->rmiimode)
1275                 sh_eth_write(ndev, 0x1, RMIIMODE);
1276
1277         /* Descriptor format */
1278         sh_eth_ring_format(ndev);
1279         if (mdp->cd->rpadir)
1280                 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
1281
1282         /* all sh_eth int mask */
1283         sh_eth_write(ndev, 0, EESIPR);
1284
1285 #if defined(__LITTLE_ENDIAN)
1286         if (mdp->cd->hw_swap)
1287                 sh_eth_write(ndev, EDMR_EL, EDMR);
1288         else
1289 #endif
1290                 sh_eth_write(ndev, 0, EDMR);
1291
1292         /* FIFO size set */
1293         sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1294         sh_eth_write(ndev, 0, TFTR);
1295
1296         /* Frame recv control (enable multiple-packets per rx irq) */
1297         sh_eth_write(ndev, RMCR_RNC, RMCR);
1298
1299         sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);
1300
1301         if (mdp->cd->bculr)
1302                 sh_eth_write(ndev, 0x800, BCULR);       /* Burst sycle set */
1303
1304         sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
1305
1306         if (!mdp->cd->no_trimd)
1307                 sh_eth_write(ndev, 0, TRIMD);
1308
1309         /* Recv frame limit set register */
1310         sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1311                      RFLR);
1312
1313         sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
1314         if (start) {
1315                 mdp->irq_enabled = true;
1316                 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1317         }
1318
1319         /* PAUSE Prohibition */
1320         val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
1321                 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
1322
1323         sh_eth_write(ndev, val, ECMR);
1324
1325         if (mdp->cd->set_rate)
1326                 mdp->cd->set_rate(ndev);
1327
1328         /* E-MAC Status Register clear */
1329         sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1330
1331         /* E-MAC Interrupt Enable register */
1332         if (start)
1333                 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1334
1335         /* Set MAC address */
1336         update_mac_address(ndev);
1337
1338         /* mask reset */
1339         if (mdp->cd->apr)
1340                 sh_eth_write(ndev, APR_AP, APR);
1341         if (mdp->cd->mpr)
1342                 sh_eth_write(ndev, MPR_MP, MPR);
1343         if (mdp->cd->tpauser)
1344                 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1345
1346         if (start) {
1347                 /* Setting the Rx mode will start the Rx process. */
1348                 sh_eth_write(ndev, EDRRR_R, EDRRR);
1349
1350                 netif_start_queue(ndev);
1351         }
1352
1353         return ret;
1354 }
1355
1356 static void sh_eth_dev_exit(struct net_device *ndev)
1357 {
1358         struct sh_eth_private *mdp = netdev_priv(ndev);
1359         int i;
1360
1361         /* Deactivate all TX descriptors, so DMA should stop at next
1362          * packet boundary if it's currently running
1363          */
1364         for (i = 0; i < mdp->num_tx_ring; i++)
1365                 mdp->tx_ring[i].status &= ~cpu_to_edmac(mdp, TD_TACT);
1366
1367         /* Disable TX FIFO egress to MAC */
1368         sh_eth_rcv_snd_disable(ndev);
1369
1370         /* Stop RX DMA at next packet boundary */
1371         sh_eth_write(ndev, 0, EDRRR);
1372
1373         /* Aside from TX DMA, we can't tell when the hardware is
1374          * really stopped, so we need to reset to make sure.
1375          * Before doing that, wait for long enough to *probably*
1376          * finish transmitting the last packet and poll stats.
1377          */
1378         msleep(2); /* max frame time at 10 Mbps < 1250 us */
1379         sh_eth_get_stats(ndev);
1380         sh_eth_reset(ndev);
1381
1382         /* Set MAC address again */
1383         update_mac_address(ndev);
1384 }
1385
1386 /* free Tx skb function */
1387 static int sh_eth_txfree(struct net_device *ndev)
1388 {
1389         struct sh_eth_private *mdp = netdev_priv(ndev);
1390         struct sh_eth_txdesc *txdesc;
1391         int free_num = 0;
1392         int entry = 0;
1393
1394         for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1395                 entry = mdp->dirty_tx % mdp->num_tx_ring;
1396                 txdesc = &mdp->tx_ring[entry];
1397                 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
1398                         break;
1399                 /* TACT bit must be checked before all the following reads */
1400                 dma_rmb();
1401                 netif_info(mdp, tx_done, ndev,
1402                            "tx entry %d status 0x%08x\n",
1403                            entry, edmac_to_cpu(mdp, txdesc->status));
1404                 /* Free the original skb. */
1405                 if (mdp->tx_skbuff[entry]) {
1406                         dma_unmap_single(&ndev->dev, txdesc->addr,
1407                                          txdesc->buffer_length, DMA_TO_DEVICE);
1408                         dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1409                         mdp->tx_skbuff[entry] = NULL;
1410                         free_num++;
1411                 }
1412                 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1413                 if (entry >= mdp->num_tx_ring - 1)
1414                         txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1415
1416                 ndev->stats.tx_packets++;
1417                 ndev->stats.tx_bytes += txdesc->buffer_length;
1418         }
1419         return free_num;
1420 }
1421
1422 /* Packet receive function */
1423 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
1424 {
1425         struct sh_eth_private *mdp = netdev_priv(ndev);
1426         struct sh_eth_rxdesc *rxdesc;
1427
1428         int entry = mdp->cur_rx % mdp->num_rx_ring;
1429         int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
1430         int limit;
1431         struct sk_buff *skb;
1432         u16 pkt_len = 0;
1433         u32 desc_status;
1434         int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1435         dma_addr_t dma_addr;
1436
1437         boguscnt = min(boguscnt, *quota);
1438         limit = boguscnt;
1439         rxdesc = &mdp->rx_ring[entry];
1440         while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
1441                 /* RACT bit must be checked before all the following reads */
1442                 dma_rmb();
1443                 desc_status = edmac_to_cpu(mdp, rxdesc->status);
1444                 pkt_len = rxdesc->frame_length;
1445
1446                 if (--boguscnt < 0)
1447                         break;
1448
1449                 netif_info(mdp, rx_status, ndev,
1450                            "rx entry %d status 0x%08x len %d\n",
1451                            entry, desc_status, pkt_len);
1452
1453                 if (!(desc_status & RDFEND))
1454                         ndev->stats.rx_length_errors++;
1455
1456                 /* In case of almost all GETHER/ETHERs, the Receive Frame State
1457                  * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1458                  * bit 0. However, in case of the R8A7740 and R7S72100
1459                  * the RFS bits are from bit 25 to bit 16. So, the
1460                  * driver needs right shifting by 16.
1461                  */
1462                 if (mdp->cd->shift_rd0)
1463                         desc_status >>= 16;
1464
1465                 skb = mdp->rx_skbuff[entry];
1466                 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1467                                    RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1468                         ndev->stats.rx_errors++;
1469                         if (desc_status & RD_RFS1)
1470                                 ndev->stats.rx_crc_errors++;
1471                         if (desc_status & RD_RFS2)
1472                                 ndev->stats.rx_frame_errors++;
1473                         if (desc_status & RD_RFS3)
1474                                 ndev->stats.rx_length_errors++;
1475                         if (desc_status & RD_RFS4)
1476                                 ndev->stats.rx_length_errors++;
1477                         if (desc_status & RD_RFS6)
1478                                 ndev->stats.rx_missed_errors++;
1479                         if (desc_status & RD_RFS10)
1480                                 ndev->stats.rx_over_errors++;
1481                 } else  if (skb) {
1482                         if (!mdp->cd->hw_swap)
1483                                 sh_eth_soft_swap(
1484                                         phys_to_virt(ALIGN(rxdesc->addr, 4)),
1485                                         pkt_len + 2);
1486                         mdp->rx_skbuff[entry] = NULL;
1487                         if (mdp->cd->rpadir)
1488                                 skb_reserve(skb, NET_IP_ALIGN);
1489                         dma_unmap_single(&ndev->dev, rxdesc->addr,
1490                                          ALIGN(mdp->rx_buf_sz, 32),
1491                                          DMA_FROM_DEVICE);
1492                         skb_put(skb, pkt_len);
1493                         skb->protocol = eth_type_trans(skb, ndev);
1494                         netif_receive_skb(skb);
1495                         ndev->stats.rx_packets++;
1496                         ndev->stats.rx_bytes += pkt_len;
1497                         if (desc_status & RD_RFS8)
1498                                 ndev->stats.multicast++;
1499                 }
1500                 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
1501                 rxdesc = &mdp->rx_ring[entry];
1502         }
1503
1504         /* Refill the Rx ring buffers. */
1505         for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1506                 entry = mdp->dirty_rx % mdp->num_rx_ring;
1507                 rxdesc = &mdp->rx_ring[entry];
1508                 /* The size of the buffer is 32 byte boundary. */
1509                 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 32);
1510
1511                 if (mdp->rx_skbuff[entry] == NULL) {
1512                         skb = netdev_alloc_skb(ndev, skbuff_size);
1513                         if (skb == NULL)
1514                                 break;  /* Better luck next round. */
1515                         sh_eth_set_receive_align(skb);
1516                         dma_addr = dma_map_single(&ndev->dev, skb->data,
1517                                                   rxdesc->buffer_length,
1518                                                   DMA_FROM_DEVICE);
1519                         if (dma_mapping_error(&ndev->dev, dma_addr)) {
1520                                 kfree_skb(skb);
1521                                 break;
1522                         }
1523                         mdp->rx_skbuff[entry] = skb;
1524
1525                         skb_checksum_none_assert(skb);
1526                         rxdesc->addr = dma_addr;
1527                 }
1528                 dma_wmb(); /* RACT bit must be set after all the above writes */
1529                 if (entry >= mdp->num_rx_ring - 1)
1530                         rxdesc->status |=
1531                                 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDLE);
1532                 else
1533                         rxdesc->status |=
1534                                 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1535         }
1536
1537         /* Restart Rx engine if stopped. */
1538         /* If we don't need to check status, don't. -KDU */
1539         if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1540                 /* fix the values for the next receiving if RDE is set */
1541                 if (intr_status & EESR_RDE &&
1542                     mdp->reg_offset[RDFAR] != SH_ETH_OFFSET_INVALID) {
1543                         u32 count = (sh_eth_read(ndev, RDFAR) -
1544                                      sh_eth_read(ndev, RDLAR)) >> 4;
1545
1546                         mdp->cur_rx = count;
1547                         mdp->dirty_rx = count;
1548                 }
1549                 sh_eth_write(ndev, EDRRR_R, EDRRR);
1550         }
1551
1552         *quota -= limit - boguscnt - 1;
1553
1554         return *quota <= 0;
1555 }
1556
1557 static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1558 {
1559         /* disable tx and rx */
1560         sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
1561                 ~(ECMR_RE | ECMR_TE), ECMR);
1562 }
1563
1564 static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1565 {
1566         /* enable tx and rx */
1567         sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
1568                 (ECMR_RE | ECMR_TE), ECMR);
1569 }
1570
1571 /* error control function */
1572 static void sh_eth_error(struct net_device *ndev, u32 intr_status)
1573 {
1574         struct sh_eth_private *mdp = netdev_priv(ndev);
1575         u32 felic_stat;
1576         u32 link_stat;
1577         u32 mask;
1578
1579         if (intr_status & EESR_ECI) {
1580                 felic_stat = sh_eth_read(ndev, ECSR);
1581                 sh_eth_write(ndev, felic_stat, ECSR);   /* clear int */
1582                 if (felic_stat & ECSR_ICD)
1583                         ndev->stats.tx_carrier_errors++;
1584                 if (felic_stat & ECSR_LCHNG) {
1585                         /* Link Changed */
1586                         if (mdp->cd->no_psr || mdp->no_ether_link) {
1587                                 goto ignore_link;
1588                         } else {
1589                                 link_stat = (sh_eth_read(ndev, PSR));
1590                                 if (mdp->ether_link_active_low)
1591                                         link_stat = ~link_stat;
1592                         }
1593                         if (!(link_stat & PHY_ST_LINK)) {
1594                                 sh_eth_rcv_snd_disable(ndev);
1595                         } else {
1596                                 /* Link Up */
1597                                 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
1598                                                    ~DMAC_M_ECI, EESIPR);
1599                                 /* clear int */
1600                                 sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
1601                                              ECSR);
1602                                 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
1603                                                    DMAC_M_ECI, EESIPR);
1604                                 /* enable tx and rx */
1605                                 sh_eth_rcv_snd_enable(ndev);
1606                         }
1607                 }
1608         }
1609
1610 ignore_link:
1611         if (intr_status & EESR_TWB) {
1612                 /* Unused write back interrupt */
1613                 if (intr_status & EESR_TABT) {  /* Transmit Abort int */
1614                         ndev->stats.tx_aborted_errors++;
1615                         netif_err(mdp, tx_err, ndev, "Transmit Abort\n");
1616                 }
1617         }
1618
1619         if (intr_status & EESR_RABT) {
1620                 /* Receive Abort int */
1621                 if (intr_status & EESR_RFRMER) {
1622                         /* Receive Frame Overflow int */
1623                         ndev->stats.rx_frame_errors++;
1624                 }
1625         }
1626
1627         if (intr_status & EESR_TDE) {
1628                 /* Transmit Descriptor Empty int */
1629                 ndev->stats.tx_fifo_errors++;
1630                 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n");
1631         }
1632
1633         if (intr_status & EESR_TFE) {
1634                 /* FIFO under flow */
1635                 ndev->stats.tx_fifo_errors++;
1636                 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n");
1637         }
1638
1639         if (intr_status & EESR_RDE) {
1640                 /* Receive Descriptor Empty int */
1641                 ndev->stats.rx_over_errors++;
1642         }
1643
1644         if (intr_status & EESR_RFE) {
1645                 /* Receive FIFO Overflow int */
1646                 ndev->stats.rx_fifo_errors++;
1647         }
1648
1649         if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1650                 /* Address Error */
1651                 ndev->stats.tx_fifo_errors++;
1652                 netif_err(mdp, tx_err, ndev, "Address Error\n");
1653         }
1654
1655         mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1656         if (mdp->cd->no_ade)
1657                 mask &= ~EESR_ADE;
1658         if (intr_status & mask) {
1659                 /* Tx error */
1660                 u32 edtrr = sh_eth_read(ndev, EDTRR);
1661
1662                 /* dmesg */
1663                 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1664                            intr_status, mdp->cur_tx, mdp->dirty_tx,
1665                            (u32)ndev->state, edtrr);
1666                 /* dirty buffer free */
1667                 sh_eth_txfree(ndev);
1668
1669                 /* SH7712 BUG */
1670                 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
1671                         /* tx dma start */
1672                         sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1673                 }
1674                 /* wakeup */
1675                 netif_wake_queue(ndev);
1676         }
1677 }
1678
1679 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1680 {
1681         struct net_device *ndev = netdev;
1682         struct sh_eth_private *mdp = netdev_priv(ndev);
1683         struct sh_eth_cpu_data *cd = mdp->cd;
1684         irqreturn_t ret = IRQ_NONE;
1685         u32 intr_status, intr_enable;
1686
1687         spin_lock(&mdp->lock);
1688
1689         /* Get interrupt status */
1690         intr_status = sh_eth_read(ndev, EESR);
1691         /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1692          * enabled since it's the one that  comes thru regardless of the mask,
1693          * and we need to fully handle it in sh_eth_error() in order to quench
1694          * it as it doesn't get cleared by just writing 1 to the ECI bit...
1695          */
1696         intr_enable = sh_eth_read(ndev, EESIPR);
1697         intr_status &= intr_enable | DMAC_M_ECI;
1698         if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check))
1699                 ret = IRQ_HANDLED;
1700         else
1701                 goto out;
1702
1703         if (!likely(mdp->irq_enabled)) {
1704                 sh_eth_write(ndev, 0, EESIPR);
1705                 goto out;
1706         }
1707
1708         if (intr_status & EESR_RX_CHECK) {
1709                 if (napi_schedule_prep(&mdp->napi)) {
1710                         /* Mask Rx interrupts */
1711                         sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1712                                      EESIPR);
1713                         __napi_schedule(&mdp->napi);
1714                 } else {
1715                         netdev_warn(ndev,
1716                                     "ignoring interrupt, status 0x%08x, mask 0x%08x.\n",
1717                                     intr_status, intr_enable);
1718                 }
1719         }
1720
1721         /* Tx Check */
1722         if (intr_status & cd->tx_check) {
1723                 /* Clear Tx interrupts */
1724                 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1725
1726                 sh_eth_txfree(ndev);
1727                 netif_wake_queue(ndev);
1728         }
1729
1730         if (intr_status & cd->eesr_err_check) {
1731                 /* Clear error interrupts */
1732                 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1733
1734                 sh_eth_error(ndev, intr_status);
1735         }
1736
1737 out:
1738         spin_unlock(&mdp->lock);
1739
1740         return ret;
1741 }
1742
1743 static int sh_eth_poll(struct napi_struct *napi, int budget)
1744 {
1745         struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1746                                                   napi);
1747         struct net_device *ndev = napi->dev;
1748         int quota = budget;
1749         u32 intr_status;
1750
1751         for (;;) {
1752                 intr_status = sh_eth_read(ndev, EESR);
1753                 if (!(intr_status & EESR_RX_CHECK))
1754                         break;
1755                 /* Clear Rx interrupts */
1756                 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1757
1758                 if (sh_eth_rx(ndev, intr_status, &quota))
1759                         goto out;
1760         }
1761
1762         napi_complete(napi);
1763
1764         /* Reenable Rx interrupts */
1765         if (mdp->irq_enabled)
1766                 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1767 out:
1768         return budget - quota;
1769 }
1770
1771 /* PHY state control function */
1772 static void sh_eth_adjust_link(struct net_device *ndev)
1773 {
1774         struct sh_eth_private *mdp = netdev_priv(ndev);
1775         struct phy_device *phydev = mdp->phydev;
1776         int new_state = 0;
1777
1778         if (phydev->link) {
1779                 if (phydev->duplex != mdp->duplex) {
1780                         new_state = 1;
1781                         mdp->duplex = phydev->duplex;
1782                         if (mdp->cd->set_duplex)
1783                                 mdp->cd->set_duplex(ndev);
1784                 }
1785
1786                 if (phydev->speed != mdp->speed) {
1787                         new_state = 1;
1788                         mdp->speed = phydev->speed;
1789                         if (mdp->cd->set_rate)
1790                                 mdp->cd->set_rate(ndev);
1791                 }
1792                 if (!mdp->link) {
1793                         sh_eth_write(ndev,
1794                                      sh_eth_read(ndev, ECMR) & ~ECMR_TXF,
1795                                      ECMR);
1796                         new_state = 1;
1797                         mdp->link = phydev->link;
1798                         if (mdp->cd->no_psr || mdp->no_ether_link)
1799                                 sh_eth_rcv_snd_enable(ndev);
1800                 }
1801         } else if (mdp->link) {
1802                 new_state = 1;
1803                 mdp->link = 0;
1804                 mdp->speed = 0;
1805                 mdp->duplex = -1;
1806                 if (mdp->cd->no_psr || mdp->no_ether_link)
1807                         sh_eth_rcv_snd_disable(ndev);
1808         }
1809
1810         if (new_state && netif_msg_link(mdp))
1811                 phy_print_status(phydev);
1812 }
1813
1814 /* PHY init function */
1815 static int sh_eth_phy_init(struct net_device *ndev)
1816 {
1817         struct device_node *np = ndev->dev.parent->of_node;
1818         struct sh_eth_private *mdp = netdev_priv(ndev);
1819         struct phy_device *phydev = NULL;
1820
1821         mdp->link = 0;
1822         mdp->speed = 0;
1823         mdp->duplex = -1;
1824
1825         /* Try connect to PHY */
1826         if (np) {
1827                 struct device_node *pn;
1828
1829                 pn = of_parse_phandle(np, "phy-handle", 0);
1830                 phydev = of_phy_connect(ndev, pn,
1831                                         sh_eth_adjust_link, 0,
1832                                         mdp->phy_interface);
1833
1834                 if (!phydev)
1835                         phydev = ERR_PTR(-ENOENT);
1836         } else {
1837                 char phy_id[MII_BUS_ID_SIZE + 3];
1838
1839                 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1840                          mdp->mii_bus->id, mdp->phy_id);
1841
1842                 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1843                                      mdp->phy_interface);
1844         }
1845
1846         if (IS_ERR(phydev)) {
1847                 netdev_err(ndev, "failed to connect PHY\n");
1848                 return PTR_ERR(phydev);
1849         }
1850
1851         netdev_info(ndev, "attached PHY %d (IRQ %d) to driver %s\n",
1852                     phydev->addr, phydev->irq, phydev->drv->name);
1853
1854         mdp->phydev = phydev;
1855
1856         return 0;
1857 }
1858
1859 /* PHY control start function */
1860 static int sh_eth_phy_start(struct net_device *ndev)
1861 {
1862         struct sh_eth_private *mdp = netdev_priv(ndev);
1863         int ret;
1864
1865         ret = sh_eth_phy_init(ndev);
1866         if (ret)
1867                 return ret;
1868
1869         phy_start(mdp->phydev);
1870
1871         return 0;
1872 }
1873
1874 static int sh_eth_get_settings(struct net_device *ndev,
1875                                struct ethtool_cmd *ecmd)
1876 {
1877         struct sh_eth_private *mdp = netdev_priv(ndev);
1878         unsigned long flags;
1879         int ret;
1880
1881         if (!mdp->phydev)
1882                 return -ENODEV;
1883
1884         spin_lock_irqsave(&mdp->lock, flags);
1885         ret = phy_ethtool_gset(mdp->phydev, ecmd);
1886         spin_unlock_irqrestore(&mdp->lock, flags);
1887
1888         return ret;
1889 }
1890
1891 static int sh_eth_set_settings(struct net_device *ndev,
1892                                struct ethtool_cmd *ecmd)
1893 {
1894         struct sh_eth_private *mdp = netdev_priv(ndev);
1895         unsigned long flags;
1896         int ret;
1897
1898         if (!mdp->phydev)
1899                 return -ENODEV;
1900
1901         spin_lock_irqsave(&mdp->lock, flags);
1902
1903         /* disable tx and rx */
1904         sh_eth_rcv_snd_disable(ndev);
1905
1906         ret = phy_ethtool_sset(mdp->phydev, ecmd);
1907         if (ret)
1908                 goto error_exit;
1909
1910         if (ecmd->duplex == DUPLEX_FULL)
1911                 mdp->duplex = 1;
1912         else
1913                 mdp->duplex = 0;
1914
1915         if (mdp->cd->set_duplex)
1916                 mdp->cd->set_duplex(ndev);
1917
1918 error_exit:
1919         mdelay(1);
1920
1921         /* enable tx and rx */
1922         sh_eth_rcv_snd_enable(ndev);
1923
1924         spin_unlock_irqrestore(&mdp->lock, flags);
1925
1926         return ret;
1927 }
1928
1929 /* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the
1930  * version must be bumped as well.  Just adding registers up to that
1931  * limit is fine, as long as the existing register indices don't
1932  * change.
1933  */
1934 #define SH_ETH_REG_DUMP_VERSION         1
1935 #define SH_ETH_REG_DUMP_MAX_REGS        256
1936
1937 static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf)
1938 {
1939         struct sh_eth_private *mdp = netdev_priv(ndev);
1940         struct sh_eth_cpu_data *cd = mdp->cd;
1941         u32 *valid_map;
1942         size_t len;
1943
1944         BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS);
1945
1946         /* Dump starts with a bitmap that tells ethtool which
1947          * registers are defined for this chip.
1948          */
1949         len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32);
1950         if (buf) {
1951                 valid_map = buf;
1952                 buf += len;
1953         } else {
1954                 valid_map = NULL;
1955         }
1956
1957         /* Add a register to the dump, if it has a defined offset.
1958          * This automatically skips most undefined registers, but for
1959          * some it is also necessary to check a capability flag in
1960          * struct sh_eth_cpu_data.
1961          */
1962 #define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32)
1963 #define add_reg_from(reg, read_expr) do {                               \
1964                 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) {    \
1965                         if (buf) {                                      \
1966                                 mark_reg_valid(reg);                    \
1967                                 *buf++ = read_expr;                     \
1968                         }                                               \
1969                         ++len;                                          \
1970                 }                                                       \
1971         } while (0)
1972 #define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg))
1973 #define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg))
1974
1975         add_reg(EDSR);
1976         add_reg(EDMR);
1977         add_reg(EDTRR);
1978         add_reg(EDRRR);
1979         add_reg(EESR);
1980         add_reg(EESIPR);
1981         add_reg(TDLAR);
1982         add_reg(TDFAR);
1983         add_reg(TDFXR);
1984         add_reg(TDFFR);
1985         add_reg(RDLAR);
1986         add_reg(RDFAR);
1987         add_reg(RDFXR);
1988         add_reg(RDFFR);
1989         add_reg(TRSCER);
1990         add_reg(RMFCR);
1991         add_reg(TFTR);
1992         add_reg(FDR);
1993         add_reg(RMCR);
1994         add_reg(TFUCR);
1995         add_reg(RFOCR);
1996         if (cd->rmiimode)
1997                 add_reg(RMIIMODE);
1998         add_reg(FCFTR);
1999         if (cd->rpadir)
2000                 add_reg(RPADIR);
2001         if (!cd->no_trimd)
2002                 add_reg(TRIMD);
2003         add_reg(ECMR);
2004         add_reg(ECSR);
2005         add_reg(ECSIPR);
2006         add_reg(PIR);
2007         if (!cd->no_psr)
2008                 add_reg(PSR);
2009         add_reg(RDMLR);
2010         add_reg(RFLR);
2011         add_reg(IPGR);
2012         if (cd->apr)
2013                 add_reg(APR);
2014         if (cd->mpr)
2015                 add_reg(MPR);
2016         add_reg(RFCR);
2017         add_reg(RFCF);
2018         if (cd->tpauser)
2019                 add_reg(TPAUSER);
2020         add_reg(TPAUSECR);
2021         add_reg(GECMR);
2022         if (cd->bculr)
2023                 add_reg(BCULR);
2024         add_reg(MAHR);
2025         add_reg(MALR);
2026         add_reg(TROCR);
2027         add_reg(CDCR);
2028         add_reg(LCCR);
2029         add_reg(CNDCR);
2030         add_reg(CEFCR);
2031         add_reg(FRECR);
2032         add_reg(TSFRCR);
2033         add_reg(TLFRCR);
2034         add_reg(CERCR);
2035         add_reg(CEECR);
2036         add_reg(MAFCR);
2037         if (cd->rtrate)
2038                 add_reg(RTRATE);
2039         if (cd->hw_crc)
2040                 add_reg(CSMR);
2041         if (cd->select_mii)
2042                 add_reg(RMII_MII);
2043         add_reg(ARSTR);
2044         if (cd->tsu) {
2045                 add_tsu_reg(TSU_CTRST);
2046                 add_tsu_reg(TSU_FWEN0);
2047                 add_tsu_reg(TSU_FWEN1);
2048                 add_tsu_reg(TSU_FCM);
2049                 add_tsu_reg(TSU_BSYSL0);
2050                 add_tsu_reg(TSU_BSYSL1);
2051                 add_tsu_reg(TSU_PRISL0);
2052                 add_tsu_reg(TSU_PRISL1);
2053                 add_tsu_reg(TSU_FWSL0);
2054                 add_tsu_reg(TSU_FWSL1);
2055                 add_tsu_reg(TSU_FWSLC);
2056                 add_tsu_reg(TSU_QTAG0);
2057                 add_tsu_reg(TSU_QTAG1);
2058                 add_tsu_reg(TSU_QTAGM0);
2059                 add_tsu_reg(TSU_QTAGM1);
2060                 add_tsu_reg(TSU_FWSR);
2061                 add_tsu_reg(TSU_FWINMK);
2062                 add_tsu_reg(TSU_ADQT0);
2063                 add_tsu_reg(TSU_ADQT1);
2064                 add_tsu_reg(TSU_VTAG0);
2065                 add_tsu_reg(TSU_VTAG1);
2066                 add_tsu_reg(TSU_ADSBSY);
2067                 add_tsu_reg(TSU_TEN);
2068                 add_tsu_reg(TSU_POST1);
2069                 add_tsu_reg(TSU_POST2);
2070                 add_tsu_reg(TSU_POST3);
2071                 add_tsu_reg(TSU_POST4);
2072                 if (mdp->reg_offset[TSU_ADRH0] != SH_ETH_OFFSET_INVALID) {
2073                         /* This is the start of a table, not just a single
2074                          * register.
2075                          */
2076                         if (buf) {
2077                                 unsigned int i;
2078
2079                                 mark_reg_valid(TSU_ADRH0);
2080                                 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++)
2081                                         *buf++ = ioread32(
2082                                                 mdp->tsu_addr +
2083                                                 mdp->reg_offset[TSU_ADRH0] +
2084                                                 i * 4);
2085                         }
2086                         len += SH_ETH_TSU_CAM_ENTRIES * 2;
2087                 }
2088         }
2089
2090 #undef mark_reg_valid
2091 #undef add_reg_from
2092 #undef add_reg
2093 #undef add_tsu_reg
2094
2095         return len * 4;
2096 }
2097
2098 static int sh_eth_get_regs_len(struct net_device *ndev)
2099 {
2100         return __sh_eth_get_regs(ndev, NULL);
2101 }
2102
2103 static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs,
2104                             void *buf)
2105 {
2106         struct sh_eth_private *mdp = netdev_priv(ndev);
2107
2108         regs->version = SH_ETH_REG_DUMP_VERSION;
2109
2110         pm_runtime_get_sync(&mdp->pdev->dev);
2111         __sh_eth_get_regs(ndev, buf);
2112         pm_runtime_put_sync(&mdp->pdev->dev);
2113 }
2114
2115 static int sh_eth_nway_reset(struct net_device *ndev)
2116 {
2117         struct sh_eth_private *mdp = netdev_priv(ndev);
2118         unsigned long flags;
2119         int ret;
2120
2121         if (!mdp->phydev)
2122                 return -ENODEV;
2123
2124         spin_lock_irqsave(&mdp->lock, flags);
2125         ret = phy_start_aneg(mdp->phydev);
2126         spin_unlock_irqrestore(&mdp->lock, flags);
2127
2128         return ret;
2129 }
2130
2131 static u32 sh_eth_get_msglevel(struct net_device *ndev)
2132 {
2133         struct sh_eth_private *mdp = netdev_priv(ndev);
2134         return mdp->msg_enable;
2135 }
2136
2137 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
2138 {
2139         struct sh_eth_private *mdp = netdev_priv(ndev);
2140         mdp->msg_enable = value;
2141 }
2142
2143 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
2144         "rx_current", "tx_current",
2145         "rx_dirty", "tx_dirty",
2146 };
2147 #define SH_ETH_STATS_LEN  ARRAY_SIZE(sh_eth_gstrings_stats)
2148
2149 static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
2150 {
2151         switch (sset) {
2152         case ETH_SS_STATS:
2153                 return SH_ETH_STATS_LEN;
2154         default:
2155                 return -EOPNOTSUPP;
2156         }
2157 }
2158
2159 static void sh_eth_get_ethtool_stats(struct net_device *ndev,
2160                                      struct ethtool_stats *stats, u64 *data)
2161 {
2162         struct sh_eth_private *mdp = netdev_priv(ndev);
2163         int i = 0;
2164
2165         /* device-specific stats */
2166         data[i++] = mdp->cur_rx;
2167         data[i++] = mdp->cur_tx;
2168         data[i++] = mdp->dirty_rx;
2169         data[i++] = mdp->dirty_tx;
2170 }
2171
2172 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
2173 {
2174         switch (stringset) {
2175         case ETH_SS_STATS:
2176                 memcpy(data, *sh_eth_gstrings_stats,
2177                        sizeof(sh_eth_gstrings_stats));
2178                 break;
2179         }
2180 }
2181
2182 static void sh_eth_get_ringparam(struct net_device *ndev,
2183                                  struct ethtool_ringparam *ring)
2184 {
2185         struct sh_eth_private *mdp = netdev_priv(ndev);
2186
2187         ring->rx_max_pending = RX_RING_MAX;
2188         ring->tx_max_pending = TX_RING_MAX;
2189         ring->rx_pending = mdp->num_rx_ring;
2190         ring->tx_pending = mdp->num_tx_ring;
2191 }
2192
2193 static int sh_eth_set_ringparam(struct net_device *ndev,
2194                                 struct ethtool_ringparam *ring)
2195 {
2196         struct sh_eth_private *mdp = netdev_priv(ndev);
2197         int ret;
2198
2199         if (ring->tx_pending > TX_RING_MAX ||
2200             ring->rx_pending > RX_RING_MAX ||
2201             ring->tx_pending < TX_RING_MIN ||
2202             ring->rx_pending < RX_RING_MIN)
2203                 return -EINVAL;
2204         if (ring->rx_mini_pending || ring->rx_jumbo_pending)
2205                 return -EINVAL;
2206
2207         if (netif_running(ndev)) {
2208                 netif_device_detach(ndev);
2209                 netif_tx_disable(ndev);
2210
2211                 /* Serialise with the interrupt handler and NAPI, then
2212                  * disable interrupts.  We have to clear the
2213                  * irq_enabled flag first to ensure that interrupts
2214                  * won't be re-enabled.
2215                  */
2216                 mdp->irq_enabled = false;
2217                 synchronize_irq(ndev->irq);
2218                 napi_synchronize(&mdp->napi);
2219                 sh_eth_write(ndev, 0x0000, EESIPR);
2220
2221                 sh_eth_dev_exit(ndev);
2222
2223                 /* Free all the skbuffs in the Rx queue and the DMA buffers. */
2224                 sh_eth_ring_free(ndev);
2225         }
2226
2227         /* Set new parameters */
2228         mdp->num_rx_ring = ring->rx_pending;
2229         mdp->num_tx_ring = ring->tx_pending;
2230
2231         if (netif_running(ndev)) {
2232                 ret = sh_eth_ring_init(ndev);
2233                 if (ret < 0) {
2234                         netdev_err(ndev, "%s: sh_eth_ring_init failed.\n",
2235                                    __func__);
2236                         return ret;
2237                 }
2238                 ret = sh_eth_dev_init(ndev, false);
2239                 if (ret < 0) {
2240                         netdev_err(ndev, "%s: sh_eth_dev_init failed.\n",
2241                                    __func__);
2242                         return ret;
2243                 }
2244
2245                 mdp->irq_enabled = true;
2246                 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
2247                 /* Setting the Rx mode will start the Rx process. */
2248                 sh_eth_write(ndev, EDRRR_R, EDRRR);
2249                 netif_device_attach(ndev);
2250         }
2251
2252         return 0;
2253 }
2254
2255 static const struct ethtool_ops sh_eth_ethtool_ops = {
2256         .get_settings   = sh_eth_get_settings,
2257         .set_settings   = sh_eth_set_settings,
2258         .get_regs_len   = sh_eth_get_regs_len,
2259         .get_regs       = sh_eth_get_regs,
2260         .nway_reset     = sh_eth_nway_reset,
2261         .get_msglevel   = sh_eth_get_msglevel,
2262         .set_msglevel   = sh_eth_set_msglevel,
2263         .get_link       = ethtool_op_get_link,
2264         .get_strings    = sh_eth_get_strings,
2265         .get_ethtool_stats  = sh_eth_get_ethtool_stats,
2266         .get_sset_count     = sh_eth_get_sset_count,
2267         .get_ringparam  = sh_eth_get_ringparam,
2268         .set_ringparam  = sh_eth_set_ringparam,
2269 };
2270
2271 /* network device open function */
2272 static int sh_eth_open(struct net_device *ndev)
2273 {
2274         int ret = 0;
2275         struct sh_eth_private *mdp = netdev_priv(ndev);
2276
2277         pm_runtime_get_sync(&mdp->pdev->dev);
2278
2279         napi_enable(&mdp->napi);
2280
2281         ret = request_irq(ndev->irq, sh_eth_interrupt,
2282                           mdp->cd->irq_flags, ndev->name, ndev);
2283         if (ret) {
2284                 netdev_err(ndev, "Can not assign IRQ number\n");
2285                 goto out_napi_off;
2286         }
2287
2288         /* Descriptor set */
2289         ret = sh_eth_ring_init(ndev);
2290         if (ret)
2291                 goto out_free_irq;
2292
2293         /* device init */
2294         ret = sh_eth_dev_init(ndev, true);
2295         if (ret)
2296                 goto out_free_irq;
2297
2298         /* PHY control start*/
2299         ret = sh_eth_phy_start(ndev);
2300         if (ret)
2301                 goto out_free_irq;
2302
2303         mdp->is_opened = 1;
2304
2305         return ret;
2306
2307 out_free_irq:
2308         free_irq(ndev->irq, ndev);
2309 out_napi_off:
2310         napi_disable(&mdp->napi);
2311         pm_runtime_put_sync(&mdp->pdev->dev);
2312         return ret;
2313 }
2314
2315 /* Timeout function */
2316 static void sh_eth_tx_timeout(struct net_device *ndev)
2317 {
2318         struct sh_eth_private *mdp = netdev_priv(ndev);
2319         struct sh_eth_rxdesc *rxdesc;
2320         int i;
2321
2322         netif_stop_queue(ndev);
2323
2324         netif_err(mdp, timer, ndev,
2325                   "transmit timed out, status %8.8x, resetting...\n",
2326                   sh_eth_read(ndev, EESR));
2327
2328         /* tx_errors count up */
2329         ndev->stats.tx_errors++;
2330
2331         /* Free all the skbuffs in the Rx queue. */
2332         for (i = 0; i < mdp->num_rx_ring; i++) {
2333                 rxdesc = &mdp->rx_ring[i];
2334                 rxdesc->status = 0;
2335                 rxdesc->addr = 0xBADF00D0;
2336                 dev_kfree_skb(mdp->rx_skbuff[i]);
2337                 mdp->rx_skbuff[i] = NULL;
2338         }
2339         for (i = 0; i < mdp->num_tx_ring; i++) {
2340                 dev_kfree_skb(mdp->tx_skbuff[i]);
2341                 mdp->tx_skbuff[i] = NULL;
2342         }
2343
2344         /* device init */
2345         sh_eth_dev_init(ndev, true);
2346 }
2347
2348 /* Packet transmit function */
2349 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2350 {
2351         struct sh_eth_private *mdp = netdev_priv(ndev);
2352         struct sh_eth_txdesc *txdesc;
2353         u32 entry;
2354         unsigned long flags;
2355
2356         spin_lock_irqsave(&mdp->lock, flags);
2357         if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
2358                 if (!sh_eth_txfree(ndev)) {
2359                         netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
2360                         netif_stop_queue(ndev);
2361                         spin_unlock_irqrestore(&mdp->lock, flags);
2362                         return NETDEV_TX_BUSY;
2363                 }
2364         }
2365         spin_unlock_irqrestore(&mdp->lock, flags);
2366
2367         if (skb_put_padto(skb, ETH_ZLEN))
2368                 return NETDEV_TX_OK;
2369
2370         entry = mdp->cur_tx % mdp->num_tx_ring;
2371         mdp->tx_skbuff[entry] = skb;
2372         txdesc = &mdp->tx_ring[entry];
2373         /* soft swap. */
2374         if (!mdp->cd->hw_swap)
2375                 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
2376                                  skb->len + 2);
2377         txdesc->addr = dma_map_single(&ndev->dev, skb->data, skb->len,
2378                                       DMA_TO_DEVICE);
2379         if (dma_mapping_error(&ndev->dev, txdesc->addr)) {
2380                 kfree_skb(skb);
2381                 return NETDEV_TX_OK;
2382         }
2383         txdesc->buffer_length = skb->len;
2384
2385         dma_wmb(); /* TACT bit must be set after all the above writes */
2386         if (entry >= mdp->num_tx_ring - 1)
2387                 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
2388         else
2389                 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
2390
2391         mdp->cur_tx++;
2392
2393         if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
2394                 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
2395
2396         return NETDEV_TX_OK;
2397 }
2398
2399 /* The statistics registers have write-clear behaviour, which means we
2400  * will lose any increment between the read and write.  We mitigate
2401  * this by only clearing when we read a non-zero value, so we will
2402  * never falsely report a total of zero.
2403  */
2404 static void
2405 sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg)
2406 {
2407         u32 delta = sh_eth_read(ndev, reg);
2408
2409         if (delta) {
2410                 *stat += delta;
2411                 sh_eth_write(ndev, 0, reg);
2412         }
2413 }
2414
2415 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2416 {
2417         struct sh_eth_private *mdp = netdev_priv(ndev);
2418
2419         if (sh_eth_is_rz_fast_ether(mdp))
2420                 return &ndev->stats;
2421
2422         if (!mdp->is_opened)
2423                 return &ndev->stats;
2424
2425         sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR);
2426         sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR);
2427         sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR);
2428
2429         if (sh_eth_is_gether(mdp)) {
2430                 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2431                                    CERCR);
2432                 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2433                                    CEECR);
2434         } else {
2435                 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2436                                    CNDCR);
2437         }
2438
2439         return &ndev->stats;
2440 }
2441
2442 /* device close function */
2443 static int sh_eth_close(struct net_device *ndev)
2444 {
2445         struct sh_eth_private *mdp = netdev_priv(ndev);
2446
2447         netif_stop_queue(ndev);
2448
2449         /* Serialise with the interrupt handler and NAPI, then disable
2450          * interrupts.  We have to clear the irq_enabled flag first to
2451          * ensure that interrupts won't be re-enabled.
2452          */
2453         mdp->irq_enabled = false;
2454         synchronize_irq(ndev->irq);
2455         napi_disable(&mdp->napi);
2456         sh_eth_write(ndev, 0x0000, EESIPR);
2457
2458         sh_eth_dev_exit(ndev);
2459
2460         /* PHY Disconnect */
2461         if (mdp->phydev) {
2462                 phy_stop(mdp->phydev);
2463                 phy_disconnect(mdp->phydev);
2464                 mdp->phydev = NULL;
2465         }
2466
2467         free_irq(ndev->irq, ndev);
2468
2469         /* Free all the skbuffs in the Rx queue and the DMA buffer. */
2470         sh_eth_ring_free(ndev);
2471
2472         pm_runtime_put_sync(&mdp->pdev->dev);
2473
2474         mdp->is_opened = 0;
2475
2476         return 0;
2477 }
2478
2479 /* ioctl to device function */
2480 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2481 {
2482         struct sh_eth_private *mdp = netdev_priv(ndev);
2483         struct phy_device *phydev = mdp->phydev;
2484
2485         if (!netif_running(ndev))
2486                 return -EINVAL;
2487
2488         if (!phydev)
2489                 return -ENODEV;
2490
2491         return phy_mii_ioctl(phydev, rq, cmd);
2492 }
2493
2494 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2495 static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2496                                             int entry)
2497 {
2498         return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2499 }
2500
2501 static u32 sh_eth_tsu_get_post_mask(int entry)
2502 {
2503         return 0x0f << (28 - ((entry % 8) * 4));
2504 }
2505
2506 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2507 {
2508         return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2509 }
2510
2511 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2512                                              int entry)
2513 {
2514         struct sh_eth_private *mdp = netdev_priv(ndev);
2515         u32 tmp;
2516         void *reg_offset;
2517
2518         reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2519         tmp = ioread32(reg_offset);
2520         iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2521 }
2522
2523 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2524                                               int entry)
2525 {
2526         struct sh_eth_private *mdp = netdev_priv(ndev);
2527         u32 post_mask, ref_mask, tmp;
2528         void *reg_offset;
2529
2530         reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2531         post_mask = sh_eth_tsu_get_post_mask(entry);
2532         ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2533
2534         tmp = ioread32(reg_offset);
2535         iowrite32(tmp & ~post_mask, reg_offset);
2536
2537         /* If other port enables, the function returns "true" */
2538         return tmp & ref_mask;
2539 }
2540
2541 static int sh_eth_tsu_busy(struct net_device *ndev)
2542 {
2543         int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2544         struct sh_eth_private *mdp = netdev_priv(ndev);
2545
2546         while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2547                 udelay(10);
2548                 timeout--;
2549                 if (timeout <= 0) {
2550                         netdev_err(ndev, "%s: timeout\n", __func__);
2551                         return -ETIMEDOUT;
2552                 }
2553         }
2554
2555         return 0;
2556 }
2557
2558 static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2559                                   const u8 *addr)
2560 {
2561         u32 val;
2562
2563         val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2564         iowrite32(val, reg);
2565         if (sh_eth_tsu_busy(ndev) < 0)
2566                 return -EBUSY;
2567
2568         val = addr[4] << 8 | addr[5];
2569         iowrite32(val, reg + 4);
2570         if (sh_eth_tsu_busy(ndev) < 0)
2571                 return -EBUSY;
2572
2573         return 0;
2574 }
2575
2576 static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2577 {
2578         u32 val;
2579
2580         val = ioread32(reg);
2581         addr[0] = (val >> 24) & 0xff;
2582         addr[1] = (val >> 16) & 0xff;
2583         addr[2] = (val >> 8) & 0xff;
2584         addr[3] = val & 0xff;
2585         val = ioread32(reg + 4);
2586         addr[4] = (val >> 8) & 0xff;
2587         addr[5] = val & 0xff;
2588 }
2589
2590
2591 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2592 {
2593         struct sh_eth_private *mdp = netdev_priv(ndev);
2594         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2595         int i;
2596         u8 c_addr[ETH_ALEN];
2597
2598         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2599                 sh_eth_tsu_read_entry(reg_offset, c_addr);
2600                 if (ether_addr_equal(addr, c_addr))
2601                         return i;
2602         }
2603
2604         return -ENOENT;
2605 }
2606
2607 static int sh_eth_tsu_find_empty(struct net_device *ndev)
2608 {
2609         u8 blank[ETH_ALEN];
2610         int entry;
2611
2612         memset(blank, 0, sizeof(blank));
2613         entry = sh_eth_tsu_find_entry(ndev, blank);
2614         return (entry < 0) ? -ENOMEM : entry;
2615 }
2616
2617 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2618                                               int entry)
2619 {
2620         struct sh_eth_private *mdp = netdev_priv(ndev);
2621         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2622         int ret;
2623         u8 blank[ETH_ALEN];
2624
2625         sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2626                          ~(1 << (31 - entry)), TSU_TEN);
2627
2628         memset(blank, 0, sizeof(blank));
2629         ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2630         if (ret < 0)
2631                 return ret;
2632         return 0;
2633 }
2634
2635 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2636 {
2637         struct sh_eth_private *mdp = netdev_priv(ndev);
2638         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2639         int i, ret;
2640
2641         if (!mdp->cd->tsu)
2642                 return 0;
2643
2644         i = sh_eth_tsu_find_entry(ndev, addr);
2645         if (i < 0) {
2646                 /* No entry found, create one */
2647                 i = sh_eth_tsu_find_empty(ndev);
2648                 if (i < 0)
2649                         return -ENOMEM;
2650                 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2651                 if (ret < 0)
2652                         return ret;
2653
2654                 /* Enable the entry */
2655                 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2656                                  (1 << (31 - i)), TSU_TEN);
2657         }
2658
2659         /* Entry found or created, enable POST */
2660         sh_eth_tsu_enable_cam_entry_post(ndev, i);
2661
2662         return 0;
2663 }
2664
2665 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2666 {
2667         struct sh_eth_private *mdp = netdev_priv(ndev);
2668         int i, ret;
2669
2670         if (!mdp->cd->tsu)
2671                 return 0;
2672
2673         i = sh_eth_tsu_find_entry(ndev, addr);
2674         if (i) {
2675                 /* Entry found */
2676                 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2677                         goto done;
2678
2679                 /* Disable the entry if both ports was disabled */
2680                 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2681                 if (ret < 0)
2682                         return ret;
2683         }
2684 done:
2685         return 0;
2686 }
2687
2688 static int sh_eth_tsu_purge_all(struct net_device *ndev)
2689 {
2690         struct sh_eth_private *mdp = netdev_priv(ndev);
2691         int i, ret;
2692
2693         if (!mdp->cd->tsu)
2694                 return 0;
2695
2696         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2697                 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2698                         continue;
2699
2700                 /* Disable the entry if both ports was disabled */
2701                 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2702                 if (ret < 0)
2703                         return ret;
2704         }
2705
2706         return 0;
2707 }
2708
2709 static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2710 {
2711         struct sh_eth_private *mdp = netdev_priv(ndev);
2712         u8 addr[ETH_ALEN];
2713         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2714         int i;
2715
2716         if (!mdp->cd->tsu)
2717                 return;
2718
2719         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2720                 sh_eth_tsu_read_entry(reg_offset, addr);
2721                 if (is_multicast_ether_addr(addr))
2722                         sh_eth_tsu_del_entry(ndev, addr);
2723         }
2724 }
2725
2726 /* Update promiscuous flag and multicast filter */
2727 static void sh_eth_set_rx_mode(struct net_device *ndev)
2728 {
2729         struct sh_eth_private *mdp = netdev_priv(ndev);
2730         u32 ecmr_bits;
2731         int mcast_all = 0;
2732         unsigned long flags;
2733
2734         spin_lock_irqsave(&mdp->lock, flags);
2735         /* Initial condition is MCT = 1, PRM = 0.
2736          * Depending on ndev->flags, set PRM or clear MCT
2737          */
2738         ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM;
2739         if (mdp->cd->tsu)
2740                 ecmr_bits |= ECMR_MCT;
2741
2742         if (!(ndev->flags & IFF_MULTICAST)) {
2743                 sh_eth_tsu_purge_mcast(ndev);
2744                 mcast_all = 1;
2745         }
2746         if (ndev->flags & IFF_ALLMULTI) {
2747                 sh_eth_tsu_purge_mcast(ndev);
2748                 ecmr_bits &= ~ECMR_MCT;
2749                 mcast_all = 1;
2750         }
2751
2752         if (ndev->flags & IFF_PROMISC) {
2753                 sh_eth_tsu_purge_all(ndev);
2754                 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2755         } else if (mdp->cd->tsu) {
2756                 struct netdev_hw_addr *ha;
2757                 netdev_for_each_mc_addr(ha, ndev) {
2758                         if (mcast_all && is_multicast_ether_addr(ha->addr))
2759                                 continue;
2760
2761                         if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2762                                 if (!mcast_all) {
2763                                         sh_eth_tsu_purge_mcast(ndev);
2764                                         ecmr_bits &= ~ECMR_MCT;
2765                                         mcast_all = 1;
2766                                 }
2767                         }
2768                 }
2769         }
2770
2771         /* update the ethernet mode */
2772         sh_eth_write(ndev, ecmr_bits, ECMR);
2773
2774         spin_unlock_irqrestore(&mdp->lock, flags);
2775 }
2776
2777 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2778 {
2779         if (!mdp->port)
2780                 return TSU_VTAG0;
2781         else
2782                 return TSU_VTAG1;
2783 }
2784
2785 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2786                                   __be16 proto, u16 vid)
2787 {
2788         struct sh_eth_private *mdp = netdev_priv(ndev);
2789         int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2790
2791         if (unlikely(!mdp->cd->tsu))
2792                 return -EPERM;
2793
2794         /* No filtering if vid = 0 */
2795         if (!vid)
2796                 return 0;
2797
2798         mdp->vlan_num_ids++;
2799
2800         /* The controller has one VLAN tag HW filter. So, if the filter is
2801          * already enabled, the driver disables it and the filte
2802          */
2803         if (mdp->vlan_num_ids > 1) {
2804                 /* disable VLAN filter */
2805                 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2806                 return 0;
2807         }
2808
2809         sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2810                          vtag_reg_index);
2811
2812         return 0;
2813 }
2814
2815 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2816                                    __be16 proto, u16 vid)
2817 {
2818         struct sh_eth_private *mdp = netdev_priv(ndev);
2819         int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2820
2821         if (unlikely(!mdp->cd->tsu))
2822                 return -EPERM;
2823
2824         /* No filtering if vid = 0 */
2825         if (!vid)
2826                 return 0;
2827
2828         mdp->vlan_num_ids--;
2829         sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2830
2831         return 0;
2832 }
2833
2834 /* SuperH's TSU register init function */
2835 static void sh_eth_tsu_init(struct sh_eth_private *mdp)
2836 {
2837         if (sh_eth_is_rz_fast_ether(mdp)) {
2838                 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2839                 return;
2840         }
2841
2842         sh_eth_tsu_write(mdp, 0, TSU_FWEN0);    /* Disable forward(0->1) */
2843         sh_eth_tsu_write(mdp, 0, TSU_FWEN1);    /* Disable forward(1->0) */
2844         sh_eth_tsu_write(mdp, 0, TSU_FCM);      /* forward fifo 3k-3k */
2845         sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2846         sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2847         sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2848         sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2849         sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2850         sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2851         sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
2852         if (sh_eth_is_gether(mdp)) {
2853                 sh_eth_tsu_write(mdp, 0, TSU_QTAG0);    /* Disable QTAG(0->1) */
2854                 sh_eth_tsu_write(mdp, 0, TSU_QTAG1);    /* Disable QTAG(1->0) */
2855         } else {
2856                 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0);   /* Disable QTAG(0->1) */
2857                 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1);   /* Disable QTAG(1->0) */
2858         }
2859         sh_eth_tsu_write(mdp, 0, TSU_FWSR);     /* all interrupt status clear */
2860         sh_eth_tsu_write(mdp, 0, TSU_FWINMK);   /* Disable all interrupt */
2861         sh_eth_tsu_write(mdp, 0, TSU_TEN);      /* Disable all CAM entry */
2862         sh_eth_tsu_write(mdp, 0, TSU_POST1);    /* Disable CAM entry [ 0- 7] */
2863         sh_eth_tsu_write(mdp, 0, TSU_POST2);    /* Disable CAM entry [ 8-15] */
2864         sh_eth_tsu_write(mdp, 0, TSU_POST3);    /* Disable CAM entry [16-23] */
2865         sh_eth_tsu_write(mdp, 0, TSU_POST4);    /* Disable CAM entry [24-31] */
2866 }
2867
2868 /* MDIO bus release function */
2869 static int sh_mdio_release(struct sh_eth_private *mdp)
2870 {
2871         /* unregister mdio bus */
2872         mdiobus_unregister(mdp->mii_bus);
2873
2874         /* free bitbang info */
2875         free_mdio_bitbang(mdp->mii_bus);
2876
2877         return 0;
2878 }
2879
2880 /* MDIO bus init function */
2881 static int sh_mdio_init(struct sh_eth_private *mdp,
2882                         struct sh_eth_plat_data *pd)
2883 {
2884         int ret, i;
2885         struct bb_info *bitbang;
2886         struct platform_device *pdev = mdp->pdev;
2887         struct device *dev = &mdp->pdev->dev;
2888
2889         /* create bit control struct for PHY */
2890         bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL);
2891         if (!bitbang)
2892                 return -ENOMEM;
2893
2894         /* bitbang init */
2895         bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
2896         bitbang->set_gate = pd->set_mdio_gate;
2897         bitbang->mdi_msk = PIR_MDI;
2898         bitbang->mdo_msk = PIR_MDO;
2899         bitbang->mmd_msk = PIR_MMD;
2900         bitbang->mdc_msk = PIR_MDC;
2901         bitbang->ctrl.ops = &bb_ops;
2902
2903         /* MII controller setting */
2904         mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
2905         if (!mdp->mii_bus)
2906                 return -ENOMEM;
2907
2908         /* Hook up MII support for ethtool */
2909         mdp->mii_bus->name = "sh_mii";
2910         mdp->mii_bus->parent = dev;
2911         snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2912                  pdev->name, pdev->id);
2913
2914         /* PHY IRQ */
2915         mdp->mii_bus->irq = devm_kmalloc_array(dev, PHY_MAX_ADDR, sizeof(int),
2916                                                GFP_KERNEL);
2917         if (!mdp->mii_bus->irq) {
2918                 ret = -ENOMEM;
2919                 goto out_free_bus;
2920         }
2921
2922         /* register MDIO bus */
2923         if (dev->of_node) {
2924                 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node);
2925         } else {
2926                 for (i = 0; i < PHY_MAX_ADDR; i++)
2927                         mdp->mii_bus->irq[i] = PHY_POLL;
2928                 if (pd->phy_irq > 0)
2929                         mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
2930
2931                 ret = mdiobus_register(mdp->mii_bus);
2932         }
2933
2934         if (ret)
2935                 goto out_free_bus;
2936
2937         return 0;
2938
2939 out_free_bus:
2940         free_mdio_bitbang(mdp->mii_bus);
2941         return ret;
2942 }
2943
2944 static const u16 *sh_eth_get_register_offset(int register_type)
2945 {
2946         const u16 *reg_offset = NULL;
2947
2948         switch (register_type) {
2949         case SH_ETH_REG_GIGABIT:
2950                 reg_offset = sh_eth_offset_gigabit;
2951                 break;
2952         case SH_ETH_REG_FAST_RZ:
2953                 reg_offset = sh_eth_offset_fast_rz;
2954                 break;
2955         case SH_ETH_REG_FAST_RCAR:
2956                 reg_offset = sh_eth_offset_fast_rcar;
2957                 break;
2958         case SH_ETH_REG_FAST_SH4:
2959                 reg_offset = sh_eth_offset_fast_sh4;
2960                 break;
2961         case SH_ETH_REG_FAST_SH3_SH2:
2962                 reg_offset = sh_eth_offset_fast_sh3_sh2;
2963                 break;
2964         default:
2965                 break;
2966         }
2967
2968         return reg_offset;
2969 }
2970
2971 static const struct net_device_ops sh_eth_netdev_ops = {
2972         .ndo_open               = sh_eth_open,
2973         .ndo_stop               = sh_eth_close,
2974         .ndo_start_xmit         = sh_eth_start_xmit,
2975         .ndo_get_stats          = sh_eth_get_stats,
2976         .ndo_set_rx_mode        = sh_eth_set_rx_mode,
2977         .ndo_tx_timeout         = sh_eth_tx_timeout,
2978         .ndo_do_ioctl           = sh_eth_do_ioctl,
2979         .ndo_validate_addr      = eth_validate_addr,
2980         .ndo_set_mac_address    = eth_mac_addr,
2981         .ndo_change_mtu         = eth_change_mtu,
2982 };
2983
2984 static const struct net_device_ops sh_eth_netdev_ops_tsu = {
2985         .ndo_open               = sh_eth_open,
2986         .ndo_stop               = sh_eth_close,
2987         .ndo_start_xmit         = sh_eth_start_xmit,
2988         .ndo_get_stats          = sh_eth_get_stats,
2989         .ndo_set_rx_mode        = sh_eth_set_rx_mode,
2990         .ndo_vlan_rx_add_vid    = sh_eth_vlan_rx_add_vid,
2991         .ndo_vlan_rx_kill_vid   = sh_eth_vlan_rx_kill_vid,
2992         .ndo_tx_timeout         = sh_eth_tx_timeout,
2993         .ndo_do_ioctl           = sh_eth_do_ioctl,
2994         .ndo_validate_addr      = eth_validate_addr,
2995         .ndo_set_mac_address    = eth_mac_addr,
2996         .ndo_change_mtu         = eth_change_mtu,
2997 };
2998
2999 #ifdef CONFIG_OF
3000 static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3001 {
3002         struct device_node *np = dev->of_node;
3003         struct sh_eth_plat_data *pdata;
3004         const char *mac_addr;
3005
3006         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
3007         if (!pdata)
3008                 return NULL;
3009
3010         pdata->phy_interface = of_get_phy_mode(np);
3011
3012         mac_addr = of_get_mac_address(np);
3013         if (mac_addr)
3014                 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
3015
3016         pdata->no_ether_link =
3017                 of_property_read_bool(np, "renesas,no-ether-link");
3018         pdata->ether_link_active_low =
3019                 of_property_read_bool(np, "renesas,ether-link-active-low");
3020
3021         return pdata;
3022 }
3023
3024 static const struct of_device_id sh_eth_match_table[] = {
3025         { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
3026         { .compatible = "renesas,ether-r8a7778", .data = &r8a777x_data },
3027         { .compatible = "renesas,ether-r8a7779", .data = &r8a777x_data },
3028         { .compatible = "renesas,ether-r8a7790", .data = &r8a779x_data },
3029         { .compatible = "renesas,ether-r8a7791", .data = &r8a779x_data },
3030         { .compatible = "renesas,ether-r8a7793", .data = &r8a779x_data },
3031         { .compatible = "renesas,ether-r8a7794", .data = &r8a779x_data },
3032         { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
3033         { }
3034 };
3035 MODULE_DEVICE_TABLE(of, sh_eth_match_table);
3036 #else
3037 static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3038 {
3039         return NULL;
3040 }
3041 #endif
3042
3043 static int sh_eth_drv_probe(struct platform_device *pdev)
3044 {
3045         int ret, devno = 0;
3046         struct resource *res;
3047         struct net_device *ndev = NULL;
3048         struct sh_eth_private *mdp = NULL;
3049         struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
3050         const struct platform_device_id *id = platform_get_device_id(pdev);
3051
3052         /* get base addr */
3053         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3054
3055         ndev = alloc_etherdev(sizeof(struct sh_eth_private));
3056         if (!ndev)
3057                 return -ENOMEM;
3058
3059         pm_runtime_enable(&pdev->dev);
3060         pm_runtime_get_sync(&pdev->dev);
3061
3062         devno = pdev->id;
3063         if (devno < 0)
3064                 devno = 0;
3065
3066         ndev->dma = -1;
3067         ret = platform_get_irq(pdev, 0);
3068         if (ret < 0)
3069                 goto out_release;
3070         ndev->irq = ret;
3071
3072         SET_NETDEV_DEV(ndev, &pdev->dev);
3073
3074         mdp = netdev_priv(ndev);
3075         mdp->num_tx_ring = TX_RING_SIZE;
3076         mdp->num_rx_ring = RX_RING_SIZE;
3077         mdp->addr = devm_ioremap_resource(&pdev->dev, res);
3078         if (IS_ERR(mdp->addr)) {
3079                 ret = PTR_ERR(mdp->addr);
3080                 goto out_release;
3081         }
3082
3083         ndev->base_addr = res->start;
3084
3085         spin_lock_init(&mdp->lock);
3086         mdp->pdev = pdev;
3087
3088         if (pdev->dev.of_node)
3089                 pd = sh_eth_parse_dt(&pdev->dev);
3090         if (!pd) {
3091                 dev_err(&pdev->dev, "no platform data\n");
3092                 ret = -EINVAL;
3093                 goto out_release;
3094         }
3095
3096         /* get PHY ID */
3097         mdp->phy_id = pd->phy;
3098         mdp->phy_interface = pd->phy_interface;
3099         /* EDMAC endian */
3100         mdp->edmac_endian = pd->edmac_endian;
3101         mdp->no_ether_link = pd->no_ether_link;
3102         mdp->ether_link_active_low = pd->ether_link_active_low;
3103
3104         /* set cpu data */
3105         if (id) {
3106                 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
3107         } else  {
3108                 const struct of_device_id *match;
3109
3110                 match = of_match_device(of_match_ptr(sh_eth_match_table),
3111                                         &pdev->dev);
3112                 mdp->cd = (struct sh_eth_cpu_data *)match->data;
3113         }
3114         mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
3115         if (!mdp->reg_offset) {
3116                 dev_err(&pdev->dev, "Unknown register type (%d)\n",
3117                         mdp->cd->register_type);
3118                 ret = -EINVAL;
3119                 goto out_release;
3120         }
3121         sh_eth_set_default_cpu_data(mdp->cd);
3122
3123         /* set function */
3124         if (mdp->cd->tsu)
3125                 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
3126         else
3127                 ndev->netdev_ops = &sh_eth_netdev_ops;
3128         ndev->ethtool_ops = &sh_eth_ethtool_ops;
3129         ndev->watchdog_timeo = TX_TIMEOUT;
3130
3131         /* debug message level */
3132         mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
3133
3134         /* read and set MAC address */
3135         read_mac_address(ndev, pd->mac_addr);
3136         if (!is_valid_ether_addr(ndev->dev_addr)) {
3137                 dev_warn(&pdev->dev,
3138                          "no valid MAC address supplied, using a random one.\n");
3139                 eth_hw_addr_random(ndev);
3140         }
3141
3142         /* ioremap the TSU registers */
3143         if (mdp->cd->tsu) {
3144                 struct resource *rtsu;
3145                 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3146                 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
3147                 if (IS_ERR(mdp->tsu_addr)) {
3148                         ret = PTR_ERR(mdp->tsu_addr);
3149                         goto out_release;
3150                 }
3151                 mdp->port = devno % 2;
3152                 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
3153         }
3154
3155         /* initialize first or needed device */
3156         if (!devno || pd->needs_init) {
3157                 if (mdp->cd->chip_reset)
3158                         mdp->cd->chip_reset(ndev);
3159
3160                 if (mdp->cd->tsu) {
3161                         /* TSU init (Init only)*/
3162                         sh_eth_tsu_init(mdp);
3163                 }
3164         }
3165
3166         if (mdp->cd->rmiimode)
3167                 sh_eth_write(ndev, 0x1, RMIIMODE);
3168
3169         /* MDIO bus init */
3170         ret = sh_mdio_init(mdp, pd);
3171         if (ret) {
3172                 dev_err(&ndev->dev, "failed to initialise MDIO\n");
3173                 goto out_release;
3174         }
3175
3176         netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
3177
3178         /* network device register */
3179         ret = register_netdev(ndev);
3180         if (ret)
3181                 goto out_napi_del;
3182
3183         /* print device information */
3184         netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
3185                     (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
3186
3187         pm_runtime_put(&pdev->dev);
3188         platform_set_drvdata(pdev, ndev);
3189
3190         return ret;
3191
3192 out_napi_del:
3193         netif_napi_del(&mdp->napi);
3194         sh_mdio_release(mdp);
3195
3196 out_release:
3197         /* net_dev free */
3198         if (ndev)
3199                 free_netdev(ndev);
3200
3201         pm_runtime_put(&pdev->dev);
3202         pm_runtime_disable(&pdev->dev);
3203         return ret;
3204 }
3205
3206 static int sh_eth_drv_remove(struct platform_device *pdev)
3207 {
3208         struct net_device *ndev = platform_get_drvdata(pdev);
3209         struct sh_eth_private *mdp = netdev_priv(ndev);
3210
3211         unregister_netdev(ndev);
3212         netif_napi_del(&mdp->napi);
3213         sh_mdio_release(mdp);
3214         pm_runtime_disable(&pdev->dev);
3215         free_netdev(ndev);
3216
3217         return 0;
3218 }
3219
3220 #ifdef CONFIG_PM
3221 #ifdef CONFIG_PM_SLEEP
3222 static int sh_eth_suspend(struct device *dev)
3223 {
3224         struct net_device *ndev = dev_get_drvdata(dev);
3225         int ret = 0;
3226
3227         if (netif_running(ndev)) {
3228                 netif_device_detach(ndev);
3229                 ret = sh_eth_close(ndev);
3230         }
3231
3232         return ret;
3233 }
3234
3235 static int sh_eth_resume(struct device *dev)
3236 {
3237         struct net_device *ndev = dev_get_drvdata(dev);
3238         int ret = 0;
3239
3240         if (netif_running(ndev)) {
3241                 ret = sh_eth_open(ndev);
3242                 if (ret < 0)
3243                         return ret;
3244                 netif_device_attach(ndev);
3245         }
3246
3247         return ret;
3248 }
3249 #endif
3250
3251 static int sh_eth_runtime_nop(struct device *dev)
3252 {
3253         /* Runtime PM callback shared between ->runtime_suspend()
3254          * and ->runtime_resume(). Simply returns success.
3255          *
3256          * This driver re-initializes all registers after
3257          * pm_runtime_get_sync() anyway so there is no need
3258          * to save and restore registers here.
3259          */
3260         return 0;
3261 }
3262
3263 static const struct dev_pm_ops sh_eth_dev_pm_ops = {
3264         SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume)
3265         SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL)
3266 };
3267 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
3268 #else
3269 #define SH_ETH_PM_OPS NULL
3270 #endif
3271
3272 static struct platform_device_id sh_eth_id_table[] = {
3273         { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
3274         { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
3275         { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
3276         { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
3277         { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
3278         { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
3279         { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
3280         { "r7s72100-ether", (kernel_ulong_t)&r7s72100_data },
3281         { "r8a7740-gether", (kernel_ulong_t)&r8a7740_data },
3282         { "r8a777x-ether", (kernel_ulong_t)&r8a777x_data },
3283         { "r8a7790-ether", (kernel_ulong_t)&r8a779x_data },
3284         { "r8a7791-ether", (kernel_ulong_t)&r8a779x_data },
3285         { "r8a7793-ether", (kernel_ulong_t)&r8a779x_data },
3286         { "r8a7794-ether", (kernel_ulong_t)&r8a779x_data },
3287         { }
3288 };
3289 MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
3290
3291 static struct platform_driver sh_eth_driver = {
3292         .probe = sh_eth_drv_probe,
3293         .remove = sh_eth_drv_remove,
3294         .id_table = sh_eth_id_table,
3295         .driver = {
3296                    .name = CARDNAME,
3297                    .pm = SH_ETH_PM_OPS,
3298                    .of_match_table = of_match_ptr(sh_eth_match_table),
3299         },
3300 };
3301
3302 module_platform_driver(sh_eth_driver);
3303
3304 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3305 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3306 MODULE_LICENSE("GPL v2");