drivers/net/ethernet/renesas/sh_eth.c

   1 /*  SuperH Ethernet device driver
   2  *
   3  *  Copyright (C) 2014  Renesas Electronics Corporation
   4  *  Copyright (C) 2006-2012 Nobuhiro Iwamatsu
   5  *  Copyright (C) 2008-2014 Renesas Solutions Corp.
   6  *  Copyright (C) 2013-2014 Cogent Embedded, Inc.
   7  *  Copyright (C) 2014 Codethink Limited
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms and conditions of the GNU General Public License,
  11  *  version 2, as published by the Free Software Foundation.
  12  *
  13  *  This program is distributed in the hope it will be useful, but WITHOUT
  14  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  16  *  more details.
  17  *
  18  *  The full GNU General Public License is included in this distribution in
  19  *  the file called "COPYING".
  20  */
  21
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/spinlock.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/etherdevice.h>
  28 #include <linux/delay.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/mdio-bitbang.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/of.h>
  33 #include <linux/of_device.h>
  34 #include <linux/of_irq.h>
  35 #include <linux/of_net.h>
  36 #include <linux/phy.h>
  37 #include <linux/cache.h>
  38 #include <linux/io.h>
  39 #include <linux/pm_runtime.h>
  40 #include <linux/slab.h>
  41 #include <linux/ethtool.h>
  42 #include <linux/if_vlan.h>
  43 #include <linux/clk.h>
  44 #include <linux/sh_eth.h>
  45 #include <linux/of_mdio.h>
  46
  47 #include "sh_eth.h"
  48
  49 #define SH_ETH_DEF_MSG_ENABLE \
  50                 (NETIF_MSG_LINK | \
  51                 NETIF_MSG_TIMER | \
  52                 NETIF_MSG_RX_ERR| \
  53                 NETIF_MSG_TX_ERR)
  54
  55 #define SH_ETH_OFFSET_INVALID   ((u16)~0)
  56
  57 #define SH_ETH_OFFSET_DEFAULTS                  \
  58         [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID
  59
  60 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
  61         SH_ETH_OFFSET_DEFAULTS,
  62
  63         [EDSR]          = 0x0000,
  64         [EDMR]          = 0x0400,
  65         [EDTRR]         = 0x0408,
  66         [EDRRR]         = 0x0410,
  67         [EESR]          = 0x0428,
  68         [EESIPR]        = 0x0430,
  69         [TDLAR]         = 0x0010,
  70         [TDFAR]         = 0x0014,
  71         [TDFXR]         = 0x0018,
  72         [TDFFR]         = 0x001c,
  73         [RDLAR]         = 0x0030,
  74         [RDFAR]         = 0x0034,
  75         [RDFXR]         = 0x0038,
  76         [RDFFR]         = 0x003c,
  77         [TRSCER]        = 0x0438,
  78         [RMFCR]         = 0x0440,
  79         [TFTR]          = 0x0448,
  80         [FDR]           = 0x0450,
  81         [RMCR]          = 0x0458,
  82         [RPADIR]        = 0x0460,
  83         [FCFTR]         = 0x0468,
  84         [CSMR]          = 0x04E4,
  85
  86         [ECMR]          = 0x0500,
  87         [ECSR]          = 0x0510,
  88         [ECSIPR]        = 0x0518,
  89         [PIR]           = 0x0520,
  90         [PSR]           = 0x0528,
  91         [PIPR]          = 0x052c,
  92         [RFLR]          = 0x0508,
  93         [APR]           = 0x0554,
  94         [MPR]           = 0x0558,
  95         [PFTCR]         = 0x055c,
  96         [PFRCR]         = 0x0560,
  97         [TPAUSER]       = 0x0564,
  98         [GECMR]         = 0x05b0,
  99         [BCULR]         = 0x05b4,
 100         [MAHR]          = 0x05c0,
 101         [MALR]          = 0x05c8,
 102         [TROCR]         = 0x0700,
 103         [CDCR]          = 0x0708,
 104         [LCCR]          = 0x0710,
 105         [CEFCR]         = 0x0740,
 106         [FRECR]         = 0x0748,
 107         [TSFRCR]        = 0x0750,
 108         [TLFRCR]        = 0x0758,
 109         [RFCR]          = 0x0760,
 110         [CERCR]         = 0x0768,
 111         [CEECR]         = 0x0770,
 112         [MAFCR]         = 0x0778,
 113         [RMII_MII]      = 0x0790,
 114
 115         [ARSTR]         = 0x0000,
 116         [TSU_CTRST]     = 0x0004,
 117         [TSU_FWEN0]     = 0x0010,
 118         [TSU_FWEN1]     = 0x0014,
 119         [TSU_FCM]       = 0x0018,
 120         [TSU_BSYSL0]    = 0x0020,
 121         [TSU_BSYSL1]    = 0x0024,
 122         [TSU_PRISL0]    = 0x0028,
 123         [TSU_PRISL1]    = 0x002c,
 124         [TSU_FWSL0]     = 0x0030,
 125         [TSU_FWSL1]     = 0x0034,
 126         [TSU_FWSLC]     = 0x0038,
 127         [TSU_QTAG0]     = 0x0040,
 128         [TSU_QTAG1]     = 0x0044,
 129         [TSU_FWSR]      = 0x0050,
 130         [TSU_FWINMK]    = 0x0054,
 131         [TSU_ADQT0]     = 0x0048,
 132         [TSU_ADQT1]     = 0x004c,
 133         [TSU_VTAG0]     = 0x0058,
 134         [TSU_VTAG1]     = 0x005c,
 135         [TSU_ADSBSY]    = 0x0060,
 136         [TSU_TEN]       = 0x0064,
 137         [TSU_POST1]     = 0x0070,
 138         [TSU_POST2]     = 0x0074,
 139         [TSU_POST3]     = 0x0078,
 140         [TSU_POST4]     = 0x007c,
 141         [TSU_ADRH0]     = 0x0100,
 142
 143         [TXNLCR0]       = 0x0080,
 144         [TXALCR0]       = 0x0084,
 145         [RXNLCR0]       = 0x0088,
 146         [RXALCR0]       = 0x008c,
 147         [FWNLCR0]       = 0x0090,
 148         [FWALCR0]       = 0x0094,
 149         [TXNLCR1]       = 0x00a0,
 150         [TXALCR1]       = 0x00a0,
 151         [RXNLCR1]       = 0x00a8,
 152         [RXALCR1]       = 0x00ac,
 153         [FWNLCR1]       = 0x00b0,
 154         [FWALCR1]       = 0x00b4,
 155 };
 156
 157 static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
 158         SH_ETH_OFFSET_DEFAULTS,
 159
 160         [EDSR]          = 0x0000,
 161         [EDMR]          = 0x0400,
 162         [EDTRR]         = 0x0408,
 163         [EDRRR]         = 0x0410,
 164         [EESR]          = 0x0428,
 165         [EESIPR]        = 0x0430,
 166         [TDLAR]         = 0x0010,
 167         [TDFAR]         = 0x0014,
 168         [TDFXR]         = 0x0018,
 169         [TDFFR]         = 0x001c,
 170         [RDLAR]         = 0x0030,
 171         [RDFAR]         = 0x0034,
 172         [RDFXR]         = 0x0038,
 173         [RDFFR]         = 0x003c,
 174         [TRSCER]        = 0x0438,
 175         [RMFCR]         = 0x0440,
 176         [TFTR]          = 0x0448,
 177         [FDR]           = 0x0450,
 178         [RMCR]          = 0x0458,
 179         [RPADIR]        = 0x0460,
 180         [FCFTR]         = 0x0468,
 181         [CSMR]          = 0x04E4,
 182
 183         [ECMR]          = 0x0500,
 184         [RFLR]          = 0x0508,
 185         [ECSR]          = 0x0510,
 186         [ECSIPR]        = 0x0518,
 187         [PIR]           = 0x0520,
 188         [APR]           = 0x0554,
 189         [MPR]           = 0x0558,
 190         [PFTCR]         = 0x055c,
 191         [PFRCR]         = 0x0560,
 192         [TPAUSER]       = 0x0564,
 193         [MAHR]          = 0x05c0,
 194         [MALR]          = 0x05c8,
 195         [CEFCR]         = 0x0740,
 196         [FRECR]         = 0x0748,
 197         [TSFRCR]        = 0x0750,
 198         [TLFRCR]        = 0x0758,
 199         [RFCR]          = 0x0760,
 200         [MAFCR]         = 0x0778,
 201
 202         [ARSTR]         = 0x0000,
 203         [TSU_CTRST]     = 0x0004,
 204         [TSU_VTAG0]     = 0x0058,
 205         [TSU_ADSBSY]    = 0x0060,
 206         [TSU_TEN]       = 0x0064,
 207         [TSU_ADRH0]     = 0x0100,
 208
 209         [TXNLCR0]       = 0x0080,
 210         [TXALCR0]       = 0x0084,
 211         [RXNLCR0]       = 0x0088,
 212         [RXALCR0]       = 0x008C,
 213 };
 214
 215 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
 216         SH_ETH_OFFSET_DEFAULTS,
 217
 218         [ECMR]          = 0x0300,
 219         [RFLR]          = 0x0308,
 220         [ECSR]          = 0x0310,
 221         [ECSIPR]        = 0x0318,
 222         [PIR]           = 0x0320,
 223         [PSR]           = 0x0328,
 224         [RDMLR]         = 0x0340,
 225         [IPGR]          = 0x0350,
 226         [APR]           = 0x0354,
 227         [MPR]           = 0x0358,
 228         [RFCF]          = 0x0360,
 229         [TPAUSER]       = 0x0364,
 230         [TPAUSECR]      = 0x0368,
 231         [MAHR]          = 0x03c0,
 232         [MALR]          = 0x03c8,
 233         [TROCR]         = 0x03d0,
 234         [CDCR]          = 0x03d4,
 235         [LCCR]          = 0x03d8,
 236         [CNDCR]         = 0x03dc,
 237         [CEFCR]         = 0x03e4,
 238         [FRECR]         = 0x03e8,
 239         [TSFRCR]        = 0x03ec,
 240         [TLFRCR]        = 0x03f0,
 241         [RFCR]          = 0x03f4,
 242         [MAFCR]         = 0x03f8,
 243
 244         [EDMR]          = 0x0200,
 245         [EDTRR]         = 0x0208,
 246         [EDRRR]         = 0x0210,
 247         [TDLAR]         = 0x0218,
 248         [RDLAR]         = 0x0220,
 249         [EESR]          = 0x0228,
 250         [EESIPR]        = 0x0230,
 251         [TRSCER]        = 0x0238,
 252         [RMFCR]         = 0x0240,
 253         [TFTR]          = 0x0248,
 254         [FDR]           = 0x0250,
 255         [RMCR]          = 0x0258,
 256         [TFUCR]         = 0x0264,
 257         [RFOCR]         = 0x0268,
 258         [RMIIMODE]      = 0x026c,
 259         [FCFTR]         = 0x0270,
 260         [TRIMD]         = 0x027c,
 261 };
 262
 263 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
 264         SH_ETH_OFFSET_DEFAULTS,
 265
 266         [ECMR]          = 0x0100,
 267         [RFLR]          = 0x0108,
 268         [ECSR]          = 0x0110,
 269         [ECSIPR]        = 0x0118,
 270         [PIR]           = 0x0120,
 271         [PSR]           = 0x0128,
 272         [RDMLR]         = 0x0140,
 273         [IPGR]          = 0x0150,
 274         [APR]           = 0x0154,
 275         [MPR]           = 0x0158,
 276         [TPAUSER]       = 0x0164,
 277         [RFCF]          = 0x0160,
 278         [TPAUSECR]      = 0x0168,
 279         [BCFRR]         = 0x016c,
 280         [MAHR]          = 0x01c0,
 281         [MALR]          = 0x01c8,
 282         [TROCR]         = 0x01d0,
 283         [CDCR]          = 0x01d4,
 284         [LCCR]          = 0x01d8,
 285         [CNDCR]         = 0x01dc,
 286         [CEFCR]         = 0x01e4,
 287         [FRECR]         = 0x01e8,
 288         [TSFRCR]        = 0x01ec,
 289         [TLFRCR]        = 0x01f0,
 290         [RFCR]          = 0x01f4,
 291         [MAFCR]         = 0x01f8,
 292         [RTRATE]        = 0x01fc,
 293
 294         [EDMR]          = 0x0000,
 295         [EDTRR]         = 0x0008,
 296         [EDRRR]         = 0x0010,
 297         [TDLAR]         = 0x0018,
 298         [RDLAR]         = 0x0020,
 299         [EESR]          = 0x0028,
 300         [EESIPR]        = 0x0030,
 301         [TRSCER]        = 0x0038,
 302         [RMFCR]         = 0x0040,
 303         [TFTR]          = 0x0048,
 304         [FDR]           = 0x0050,
 305         [RMCR]          = 0x0058,
 306         [TFUCR]         = 0x0064,
 307         [RFOCR]         = 0x0068,
 308         [FCFTR]         = 0x0070,
 309         [RPADIR]        = 0x0078,
 310         [TRIMD]         = 0x007c,
 311         [RBWAR]         = 0x00c8,
 312         [RDFAR]         = 0x00cc,
 313         [TBRAR]         = 0x00d4,
 314         [TDFAR]         = 0x00d8,
 315 };
 316
 317 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
 318         SH_ETH_OFFSET_DEFAULTS,
 319
 320         [EDMR]          = 0x0000,
 321         [EDTRR]         = 0x0004,
 322         [EDRRR]         = 0x0008,
 323         [TDLAR]         = 0x000c,
 324         [RDLAR]         = 0x0010,
 325         [EESR]          = 0x0014,
 326         [EESIPR]        = 0x0018,
 327         [TRSCER]        = 0x001c,
 328         [RMFCR]         = 0x0020,
 329         [TFTR]          = 0x0024,
 330         [FDR]           = 0x0028,
 331         [RMCR]          = 0x002c,
 332         [EDOCR]         = 0x0030,
 333         [FCFTR]         = 0x0034,
 334         [RPADIR]        = 0x0038,
 335         [TRIMD]         = 0x003c,
 336         [RBWAR]         = 0x0040,
 337         [RDFAR]         = 0x0044,
 338         [TBRAR]         = 0x004c,
 339         [TDFAR]         = 0x0050,
 340
 341         [ECMR]          = 0x0160,
 342         [ECSR]          = 0x0164,
 343         [ECSIPR]        = 0x0168,
 344         [PIR]           = 0x016c,
 345         [MAHR]          = 0x0170,
 346         [MALR]          = 0x0174,
 347         [RFLR]          = 0x0178,
 348         [PSR]           = 0x017c,
 349         [TROCR]         = 0x0180,
 350         [CDCR]          = 0x0184,
 351         [LCCR]          = 0x0188,
 352         [CNDCR]         = 0x018c,
 353         [CEFCR]         = 0x0194,
 354         [FRECR]         = 0x0198,
 355         [TSFRCR]        = 0x019c,
 356         [TLFRCR]        = 0x01a0,
 357         [RFCR]          = 0x01a4,
 358         [MAFCR]         = 0x01a8,
 359         [IPGR]          = 0x01b4,
 360         [APR]           = 0x01b8,
 361         [MPR]           = 0x01bc,
 362         [TPAUSER]       = 0x01c4,
 363         [BCFR]          = 0x01cc,
 364
 365         [ARSTR]         = 0x0000,
 366         [TSU_CTRST]     = 0x0004,
 367         [TSU_FWEN0]     = 0x0010,
 368         [TSU_FWEN1]     = 0x0014,
 369         [TSU_FCM]       = 0x0018,
 370         [TSU_BSYSL0]    = 0x0020,
 371         [TSU_BSYSL1]    = 0x0024,
 372         [TSU_PRISL0]    = 0x0028,
 373         [TSU_PRISL1]    = 0x002c,
 374         [TSU_FWSL0]     = 0x0030,
 375         [TSU_FWSL1]     = 0x0034,
 376         [TSU_FWSLC]     = 0x0038,
 377         [TSU_QTAGM0]    = 0x0040,
 378         [TSU_QTAGM1]    = 0x0044,
 379         [TSU_ADQT0]     = 0x0048,
 380         [TSU_ADQT1]     = 0x004c,
 381         [TSU_FWSR]      = 0x0050,
 382         [TSU_FWINMK]    = 0x0054,
 383         [TSU_ADSBSY]    = 0x0060,
 384         [TSU_TEN]       = 0x0064,
 385         [TSU_POST1]     = 0x0070,
 386         [TSU_POST2]     = 0x0074,
 387         [TSU_POST3]     = 0x0078,
 388         [TSU_POST4]     = 0x007c,
 389
 390         [TXNLCR0]       = 0x0080,
 391         [TXALCR0]       = 0x0084,
 392         [RXNLCR0]       = 0x0088,
 393         [RXALCR0]       = 0x008c,
 394         [FWNLCR0]       = 0x0090,
 395         [FWALCR0]       = 0x0094,
 396         [TXNLCR1]       = 0x00a0,
 397         [TXALCR1]       = 0x00a0,
 398         [RXNLCR1]       = 0x00a8,
 399         [RXALCR1]       = 0x00ac,
 400         [FWNLCR1]       = 0x00b0,
 401         [FWALCR1]       = 0x00b4,
 402
 403         [TSU_ADRH0]     = 0x0100,
 404 };
 405
 406 static void sh_eth_rcv_snd_disable(struct net_device *ndev);
 407 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev);
 408
 409 static void sh_eth_write(struct net_device *ndev, u32 data, int enum_index)
 410 {
 411         struct sh_eth_private *mdp = netdev_priv(ndev);
 412         u16 offset = mdp->reg_offset[enum_index];
 413
 414         if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
 415                 return;
 416
 417         iowrite32(data, mdp->addr + offset);
 418 }
 419
 420 static u32 sh_eth_read(struct net_device *ndev, int enum_index)
 421 {
 422         struct sh_eth_private *mdp = netdev_priv(ndev);
 423         u16 offset = mdp->reg_offset[enum_index];
 424
 425         if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
 426                 return ~0U;
 427
 428         return ioread32(mdp->addr + offset);
 429 }
 430
 431 static bool sh_eth_is_gether(struct sh_eth_private *mdp)
 432 {
 433         return mdp->reg_offset == sh_eth_offset_gigabit;
 434 }
 435
 436 static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp)
 437 {
 438         return mdp->reg_offset == sh_eth_offset_fast_rz;
 439 }
 440
 441 static void sh_eth_select_mii(struct net_device *ndev)
 442 {
 443         u32 value = 0x0;
 444         struct sh_eth_private *mdp = netdev_priv(ndev);
 445
 446         switch (mdp->phy_interface) {
 447         case PHY_INTERFACE_MODE_GMII:
 448                 value = 0x2;
 449                 break;
 450         case PHY_INTERFACE_MODE_MII:
 451                 value = 0x1;
 452                 break;
 453         case PHY_INTERFACE_MODE_RMII:
 454                 value = 0x0;
 455                 break;
 456         default:
 457                 netdev_warn(ndev,
 458                             "PHY interface mode was not setup. Set to MII.\n");
 459                 value = 0x1;
 460                 break;
 461         }
 462
 463         sh_eth_write(ndev, value, RMII_MII);
 464 }
 465
 466 static void sh_eth_set_duplex(struct net_device *ndev)
 467 {
 468         struct sh_eth_private *mdp = netdev_priv(ndev);
 469
 470         if (mdp->duplex) /* Full */
 471                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
 472         else            /* Half */
 473                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
 474 }
 475
 476 /* There is CPU dependent code */
 477 static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
 478 {
 479         struct sh_eth_private *mdp = netdev_priv(ndev);
 480
 481         switch (mdp->speed) {
 482         case 10: /* 10BASE */
 483                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_ELB, ECMR);
 484                 break;
 485         case 100:/* 100BASE */
 486                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_ELB, ECMR);
 487                 break;
 488         default:
 489                 break;
 490         }
 491 }
 492
 493 /* R8A7778/9 */
 494 static struct sh_eth_cpu_data r8a777x_data = {
 495         .set_duplex     = sh_eth_set_duplex,
 496         .set_rate       = sh_eth_set_rate_r8a777x,
 497
 498         .register_type  = SH_ETH_REG_FAST_RCAR,
 499
 500         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 501         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 502         .eesipr_value   = 0x01ff009f,
 503
 504         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 505         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 506                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 507                           EESR_ECI,
 508         .fdr_value      = 0x00000f0f,
 509
 510         .apr            = 1,
 511         .mpr            = 1,
 512         .tpauser        = 1,
 513         .hw_swap        = 1,
 514 };
 515
 516 /* R8A7790/1 */
 517 static struct sh_eth_cpu_data r8a779x_data = {
 518         .set_duplex     = sh_eth_set_duplex,
 519         .set_rate       = sh_eth_set_rate_r8a777x,
 520
 521         .register_type  = SH_ETH_REG_FAST_RCAR,
 522
 523         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 524         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 525         .eesipr_value   = 0x01ff009f,
 526
 527         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 528         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 529                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 530                           EESR_ECI,
 531         .fdr_value      = 0x00000f0f,
 532
 533         .trscer_err_mask = DESC_I_RINT8,
 534
 535         .apr            = 1,
 536         .mpr            = 1,
 537         .tpauser        = 1,
 538         .hw_swap        = 1,
 539         .rmiimode       = 1,
 540 };
 541
 542 static void sh_eth_set_rate_sh7724(struct net_device *ndev)
 543 {
 544         struct sh_eth_private *mdp = netdev_priv(ndev);
 545
 546         switch (mdp->speed) {
 547         case 10: /* 10BASE */
 548                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR);
 549                 break;
 550         case 100:/* 100BASE */
 551                 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR);
 552                 break;
 553         default:
 554                 break;
 555         }
 556 }
 557
 558 /* SH7724 */
 559 static struct sh_eth_cpu_data sh7724_data = {
 560         .set_duplex     = sh_eth_set_duplex,
 561         .set_rate       = sh_eth_set_rate_sh7724,
 562
 563         .register_type  = SH_ETH_REG_FAST_SH4,
 564
 565         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 566         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 567         .eesipr_value   = 0x01ff009f,
 568
 569         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 570         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 571                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 572                           EESR_ECI,
 573
 574         .apr            = 1,
 575         .mpr            = 1,
 576         .tpauser        = 1,
 577         .hw_swap        = 1,
 578         .rpadir         = 1,
 579         .rpadir_value   = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
 580 };
 581
 582 static void sh_eth_set_rate_sh7757(struct net_device *ndev)
 583 {
 584         struct sh_eth_private *mdp = netdev_priv(ndev);
 585
 586         switch (mdp->speed) {
 587         case 10: /* 10BASE */
 588                 sh_eth_write(ndev, 0, RTRATE);
 589                 break;
 590         case 100:/* 100BASE */
 591                 sh_eth_write(ndev, 1, RTRATE);
 592                 break;
 593         default:
 594                 break;
 595         }
 596 }
 597
 598 /* SH7757 */
 599 static struct sh_eth_cpu_data sh7757_data = {
 600         .set_duplex     = sh_eth_set_duplex,
 601         .set_rate       = sh_eth_set_rate_sh7757,
 602
 603         .register_type  = SH_ETH_REG_FAST_SH4,
 604
 605         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 606
 607         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 608         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 609                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 610                           EESR_ECI,
 611
 612         .irq_flags      = IRQF_SHARED,
 613         .apr            = 1,
 614         .mpr            = 1,
 615         .tpauser        = 1,
 616         .hw_swap        = 1,
 617         .no_ade         = 1,
 618         .rpadir         = 1,
 619         .rpadir_value   = 2 << 16,
 620         .rtrate         = 1,
 621 };
 622
 623 #define SH_GIGA_ETH_BASE        0xfee00000UL
 624 #define GIGA_MALR(port)         (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
 625 #define GIGA_MAHR(port)         (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
 626 static void sh_eth_chip_reset_giga(struct net_device *ndev)
 627 {
 628         int i;
 629         u32 mahr[2], malr[2];
 630
 631         /* save MAHR and MALR */
 632         for (i = 0; i < 2; i++) {
 633                 malr[i] = ioread32((void *)GIGA_MALR(i));
 634                 mahr[i] = ioread32((void *)GIGA_MAHR(i));
 635         }
 636
 637         /* reset device */
 638         iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800));
 639         mdelay(1);
 640
 641         /* restore MAHR and MALR */
 642         for (i = 0; i < 2; i++) {
 643                 iowrite32(malr[i], (void *)GIGA_MALR(i));
 644                 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
 645         }
 646 }
 647
 648 static void sh_eth_set_rate_giga(struct net_device *ndev)
 649 {
 650         struct sh_eth_private *mdp = netdev_priv(ndev);
 651
 652         switch (mdp->speed) {
 653         case 10: /* 10BASE */
 654                 sh_eth_write(ndev, 0x00000000, GECMR);
 655                 break;
 656         case 100:/* 100BASE */
 657                 sh_eth_write(ndev, 0x00000010, GECMR);
 658                 break;
 659         case 1000: /* 1000BASE */
 660                 sh_eth_write(ndev, 0x00000020, GECMR);
 661                 break;
 662         default:
 663                 break;
 664         }
 665 }
 666
 667 /* SH7757(GETHERC) */
 668 static struct sh_eth_cpu_data sh7757_data_giga = {
 669         .chip_reset     = sh_eth_chip_reset_giga,
 670         .set_duplex     = sh_eth_set_duplex,
 671         .set_rate       = sh_eth_set_rate_giga,
 672
 673         .register_type  = SH_ETH_REG_GIGABIT,
 674
 675         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 676         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 677         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 678
 679         .tx_check       = EESR_TC1 | EESR_FTC,
 680         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 681                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 682                           EESR_TDE | EESR_ECI,
 683         .fdr_value      = 0x0000072f,
 684
 685         .irq_flags      = IRQF_SHARED,
 686         .apr            = 1,
 687         .mpr            = 1,
 688         .tpauser        = 1,
 689         .bculr          = 1,
 690         .hw_swap        = 1,
 691         .rpadir         = 1,
 692         .rpadir_value   = 2 << 16,
 693         .no_trimd       = 1,
 694         .no_ade         = 1,
 695         .tsu            = 1,
 696 };
 697
 698 static void sh_eth_chip_reset(struct net_device *ndev)
 699 {
 700         struct sh_eth_private *mdp = netdev_priv(ndev);
 701
 702         /* reset device */
 703         sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
 704         mdelay(1);
 705 }
 706
 707 static void sh_eth_set_rate_gether(struct net_device *ndev)
 708 {
 709         struct sh_eth_private *mdp = netdev_priv(ndev);
 710
 711         switch (mdp->speed) {
 712         case 10: /* 10BASE */
 713                 sh_eth_write(ndev, GECMR_10, GECMR);
 714                 break;
 715         case 100:/* 100BASE */
 716                 sh_eth_write(ndev, GECMR_100, GECMR);
 717                 break;
 718         case 1000: /* 1000BASE */
 719                 sh_eth_write(ndev, GECMR_1000, GECMR);
 720                 break;
 721         default:
 722                 break;
 723         }
 724 }
 725
 726 /* SH7734 */
 727 static struct sh_eth_cpu_data sh7734_data = {
 728         .chip_reset     = sh_eth_chip_reset,
 729         .set_duplex     = sh_eth_set_duplex,
 730         .set_rate       = sh_eth_set_rate_gether,
 731
 732         .register_type  = SH_ETH_REG_GIGABIT,
 733
 734         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 735         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 736         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 737
 738         .tx_check       = EESR_TC1 | EESR_FTC,
 739         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 740                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 741                           EESR_TDE | EESR_ECI,
 742
 743         .apr            = 1,
 744         .mpr            = 1,
 745         .tpauser        = 1,
 746         .bculr          = 1,
 747         .hw_swap        = 1,
 748         .no_trimd       = 1,
 749         .no_ade         = 1,
 750         .tsu            = 1,
 751         .hw_crc         = 1,
 752         .select_mii     = 1,
 753 };
 754
 755 /* SH7763 */
 756 static struct sh_eth_cpu_data sh7763_data = {
 757         .chip_reset     = sh_eth_chip_reset,
 758         .set_duplex     = sh_eth_set_duplex,
 759         .set_rate       = sh_eth_set_rate_gether,
 760
 761         .register_type  = SH_ETH_REG_GIGABIT,
 762
 763         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 764         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 765         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 766
 767         .tx_check       = EESR_TC1 | EESR_FTC,
 768         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 769                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
 770                           EESR_ECI,
 771
 772         .apr            = 1,
 773         .mpr            = 1,
 774         .tpauser        = 1,
 775         .bculr          = 1,
 776         .hw_swap        = 1,
 777         .no_trimd       = 1,
 778         .no_ade         = 1,
 779         .tsu            = 1,
 780         .irq_flags      = IRQF_SHARED,
 781 };
 782
 783 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
 784 {
 785         struct sh_eth_private *mdp = netdev_priv(ndev);
 786
 787         /* reset device */
 788         sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
 789         mdelay(1);
 790
 791         sh_eth_select_mii(ndev);
 792 }
 793
 794 /* R8A7740 */
 795 static struct sh_eth_cpu_data r8a7740_data = {
 796         .chip_reset     = sh_eth_chip_reset_r8a7740,
 797         .set_duplex     = sh_eth_set_duplex,
 798         .set_rate       = sh_eth_set_rate_gether,
 799
 800         .register_type  = SH_ETH_REG_GIGABIT,
 801
 802         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 803         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 804         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 805
 806         .tx_check       = EESR_TC1 | EESR_FTC,
 807         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 808                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 809                           EESR_TDE | EESR_ECI,
 810         .fdr_value      = 0x0000070f,
 811
 812         .apr            = 1,
 813         .mpr            = 1,
 814         .tpauser        = 1,
 815         .bculr          = 1,
 816         .hw_swap        = 1,
 817         .rpadir         = 1,
 818         .rpadir_value   = 2 << 16,
 819         .no_trimd       = 1,
 820         .no_ade         = 1,
 821         .tsu            = 1,
 822         .select_mii     = 1,
 823         .shift_rd0      = 1,
 824 };
 825
 826 /* R7S72100 */
 827 static struct sh_eth_cpu_data r7s72100_data = {
 828         .chip_reset     = sh_eth_chip_reset,
 829         .set_duplex     = sh_eth_set_duplex,
 830
 831         .register_type  = SH_ETH_REG_FAST_RZ,
 832
 833         .ecsr_value     = ECSR_ICD,
 834         .ecsipr_value   = ECSIPR_ICDIP,
 835         .eesipr_value   = 0xff7f009f,
 836
 837         .tx_check       = EESR_TC1 | EESR_FTC,
 838         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 839                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 840                           EESR_TDE | EESR_ECI,
 841         .fdr_value      = 0x0000070f,
 842
 843         .no_psr         = 1,
 844         .apr            = 1,
 845         .mpr            = 1,
 846         .tpauser        = 1,
 847         .hw_swap        = 1,
 848         .rpadir         = 1,
 849         .rpadir_value   = 2 << 16,
 850         .no_trimd       = 1,
 851         .no_ade         = 1,
 852         .hw_crc         = 1,
 853         .tsu            = 1,
 854         .shift_rd0      = 1,
 855 };
 856
 857 static struct sh_eth_cpu_data sh7619_data = {
 858         .register_type  = SH_ETH_REG_FAST_SH3_SH2,
 859
 860         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 861
 862         .apr            = 1,
 863         .mpr            = 1,
 864         .tpauser        = 1,
 865         .hw_swap        = 1,
 866 };
 867
 868 static struct sh_eth_cpu_data sh771x_data = {
 869         .register_type  = SH_ETH_REG_FAST_SH3_SH2,
 870
 871         .eesipr_value   = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
 872         .tsu            = 1,
 873 };
 874
 875 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
 876 {
 877         if (!cd->ecsr_value)
 878                 cd->ecsr_value = DEFAULT_ECSR_INIT;
 879
 880         if (!cd->ecsipr_value)
 881                 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
 882
 883         if (!cd->fcftr_value)
 884                 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
 885                                   DEFAULT_FIFO_F_D_RFD;
 886
 887         if (!cd->fdr_value)
 888                 cd->fdr_value = DEFAULT_FDR_INIT;
 889
 890         if (!cd->tx_check)
 891                 cd->tx_check = DEFAULT_TX_CHECK;
 892
 893         if (!cd->eesr_err_check)
 894                 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
 895
 896         if (!cd->trscer_err_mask)
 897                 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK;
 898 }
 899
 900 static int sh_eth_check_reset(struct net_device *ndev)
 901 {
 902         int ret = 0;
 903         int cnt = 100;
 904
 905         while (cnt > 0) {
 906                 if (!(sh_eth_read(ndev, EDMR) & 0x3))
 907                         break;
 908                 mdelay(1);
 909                 cnt--;
 910         }
 911         if (cnt <= 0) {
 912                 netdev_err(ndev, "Device reset failed\n");
 913                 ret = -ETIMEDOUT;
 914         }
 915         return ret;
 916 }
 917
 918 static int sh_eth_reset(struct net_device *ndev)
 919 {
 920         struct sh_eth_private *mdp = netdev_priv(ndev);
 921         int ret = 0;
 922
 923         if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) {
 924                 sh_eth_write(ndev, EDSR_ENALL, EDSR);
 925                 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
 926                              EDMR);
 927
 928                 ret = sh_eth_check_reset(ndev);
 929                 if (ret)
 930                         return ret;
 931
 932                 /* Table Init */
 933                 sh_eth_write(ndev, 0x0, TDLAR);
 934                 sh_eth_write(ndev, 0x0, TDFAR);
 935                 sh_eth_write(ndev, 0x0, TDFXR);
 936                 sh_eth_write(ndev, 0x0, TDFFR);
 937                 sh_eth_write(ndev, 0x0, RDLAR);
 938                 sh_eth_write(ndev, 0x0, RDFAR);
 939                 sh_eth_write(ndev, 0x0, RDFXR);
 940                 sh_eth_write(ndev, 0x0, RDFFR);
 941
 942                 /* Reset HW CRC register */
 943                 if (mdp->cd->hw_crc)
 944                         sh_eth_write(ndev, 0x0, CSMR);
 945
 946                 /* Select MII mode */
 947                 if (mdp->cd->select_mii)
 948                         sh_eth_select_mii(ndev);
 949         } else {
 950                 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,
 951                              EDMR);
 952                 mdelay(3);
 953                 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
 954                              EDMR);
 955         }
 956
 957         return ret;
 958 }
 959
 960 static void sh_eth_set_receive_align(struct sk_buff *skb)
 961 {
 962         uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1);
 963
 964         if (reserve)
 965                 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve);
 966 }
 967
 968
 969 /* CPU <-> EDMAC endian convert */
 970 static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
 971 {
 972         switch (mdp->edmac_endian) {
 973         case EDMAC_LITTLE_ENDIAN:
 974                 return cpu_to_le32(x);
 975         case EDMAC_BIG_ENDIAN:
 976                 return cpu_to_be32(x);
 977         }
 978         return x;
 979 }
 980
 981 static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
 982 {
 983         switch (mdp->edmac_endian) {
 984         case EDMAC_LITTLE_ENDIAN:
 985                 return le32_to_cpu(x);
 986         case EDMAC_BIG_ENDIAN:
 987                 return be32_to_cpu(x);
 988         }
 989         return x;
 990 }
 991
 992 /* Program the hardware MAC address from dev->dev_addr. */
 993 static void update_mac_address(struct net_device *ndev)
 994 {
 995         sh_eth_write(ndev,
 996                      (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
 997                      (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
 998         sh_eth_write(ndev,
 999                      (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
1000 }
1001
1002 /* Get MAC address from SuperH MAC address register
1003  *
1004  * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
1005  * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
1006  * When you want use this device, you must set MAC address in bootloader.
1007  *
1008  */
1009 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
1010 {
1011         if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
1012                 memcpy(ndev->dev_addr, mac, ETH_ALEN);
1013         } else {
1014                 ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24);
1015                 ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF;
1016                 ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF;
1017                 ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF);
1018                 ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF;
1019                 ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF);
1020         }
1021 }
1022
1023 static u32 sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
1024 {
1025         if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp))
1026                 return EDTRR_TRNS_GETHER;
1027         else
1028                 return EDTRR_TRNS_ETHER;
1029 }
1030
1031 struct bb_info {
1032         void (*set_gate)(void *addr);
1033         struct mdiobb_ctrl ctrl;
1034         void *addr;
1035         u32 mmd_msk;/* MMD */
1036         u32 mdo_msk;
1037         u32 mdi_msk;
1038         u32 mdc_msk;
1039 };
1040
1041 /* PHY bit set */
1042 static void bb_set(void *addr, u32 msk)
1043 {
1044         iowrite32(ioread32(addr) | msk, addr);
1045 }
1046
1047 /* PHY bit clear */
1048 static void bb_clr(void *addr, u32 msk)
1049 {
1050         iowrite32((ioread32(addr) & ~msk), addr);
1051 }
1052
1053 /* PHY bit read */
1054 static int bb_read(void *addr, u32 msk)
1055 {
1056         return (ioread32(addr) & msk) != 0;
1057 }
1058
1059 /* Data I/O pin control */
1060 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1061 {
1062         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1063
1064         if (bitbang->set_gate)
1065                 bitbang->set_gate(bitbang->addr);
1066
1067         if (bit)
1068                 bb_set(bitbang->addr, bitbang->mmd_msk);
1069         else
1070                 bb_clr(bitbang->addr, bitbang->mmd_msk);
1071 }
1072
1073 /* Set bit data*/
1074 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1075 {
1076         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1077
1078         if (bitbang->set_gate)
1079                 bitbang->set_gate(bitbang->addr);
1080
1081         if (bit)
1082                 bb_set(bitbang->addr, bitbang->mdo_msk);
1083         else
1084                 bb_clr(bitbang->addr, bitbang->mdo_msk);
1085 }
1086
1087 /* Get bit data*/
1088 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1089 {
1090         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1091
1092         if (bitbang->set_gate)
1093                 bitbang->set_gate(bitbang->addr);
1094
1095         return bb_read(bitbang->addr, bitbang->mdi_msk);
1096 }
1097
1098 /* MDC pin control */
1099 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1100 {
1101         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1102
1103         if (bitbang->set_gate)
1104                 bitbang->set_gate(bitbang->addr);
1105
1106         if (bit)
1107                 bb_set(bitbang->addr, bitbang->mdc_msk);
1108         else
1109                 bb_clr(bitbang->addr, bitbang->mdc_msk);
1110 }
1111
1112 /* mdio bus control struct */
1113 static struct mdiobb_ops bb_ops = {
1114         .owner = THIS_MODULE,
1115         .set_mdc = sh_mdc_ctrl,
1116         .set_mdio_dir = sh_mmd_ctrl,
1117         .set_mdio_data = sh_set_mdio,
1118         .get_mdio_data = sh_get_mdio,
1119 };
1120
1121 /* free skb and descriptor buffer */
1122 static void sh_eth_ring_free(struct net_device *ndev)
1123 {
1124         struct sh_eth_private *mdp = netdev_priv(ndev);
1125         int ringsize, i;
1126
1127         /* Free Rx skb ringbuffer */
1128         if (mdp->rx_skbuff) {
1129                 for (i = 0; i < mdp->num_rx_ring; i++)
1130                         dev_kfree_skb(mdp->rx_skbuff[i]);
1131         }
1132         kfree(mdp->rx_skbuff);
1133         mdp->rx_skbuff = NULL;
1134
1135         /* Free Tx skb ringbuffer */
1136         if (mdp->tx_skbuff) {
1137                 for (i = 0; i < mdp->num_tx_ring; i++)
1138                         dev_kfree_skb(mdp->tx_skbuff[i]);
1139         }
1140         kfree(mdp->tx_skbuff);
1141         mdp->tx_skbuff = NULL;
1142
1143         if (mdp->rx_ring) {
1144                 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1145                 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1146                                   mdp->rx_desc_dma);
1147                 mdp->rx_ring = NULL;
1148         }
1149
1150         if (mdp->tx_ring) {
1151                 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1152                 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1153                                   mdp->tx_desc_dma);
1154                 mdp->tx_ring = NULL;
1155         }
1156 }
1157
1158 /* format skb and descriptor buffer */
1159 static void sh_eth_ring_format(struct net_device *ndev)
1160 {
1161         struct sh_eth_private *mdp = netdev_priv(ndev);
1162         int i;
1163         struct sk_buff *skb;
1164         struct sh_eth_rxdesc *rxdesc = NULL;
1165         struct sh_eth_txdesc *txdesc = NULL;
1166         int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1167         int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
1168         int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1169         dma_addr_t dma_addr;
1170
1171         mdp->cur_rx = 0;
1172         mdp->cur_tx = 0;
1173         mdp->dirty_rx = 0;
1174         mdp->dirty_tx = 0;
1175
1176         memset(mdp->rx_ring, 0, rx_ringsize);
1177
1178         /* build Rx ring buffer */
1179         for (i = 0; i < mdp->num_rx_ring; i++) {
1180                 /* skb */
1181                 mdp->rx_skbuff[i] = NULL;
1182                 skb = netdev_alloc_skb(ndev, skbuff_size);
1183                 if (skb == NULL)
1184                         break;
1185                 sh_eth_set_receive_align(skb);
1186
1187                 /* RX descriptor */
1188                 rxdesc = &mdp->rx_ring[i];
1189                 /* The size of the buffer is a multiple of 32 bytes. */
1190                 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 32);
1191                 dma_addr = dma_map_single(&ndev->dev, skb->data,
1192                                           rxdesc->buffer_length,
1193                                           DMA_FROM_DEVICE);
1194                 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1195                         kfree_skb(skb);
1196                         break;
1197                 }
1198                 mdp->rx_skbuff[i] = skb;
1199                 rxdesc->addr = cpu_to_edmac(mdp, dma_addr);
1200                 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1201
1202                 /* Rx descriptor address set */
1203                 if (i == 0) {
1204                         sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
1205                         if (sh_eth_is_gether(mdp) ||
1206                             sh_eth_is_rz_fast_ether(mdp))
1207                                 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
1208                 }
1209         }
1210
1211         mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
1212
1213         /* Mark the last entry as wrapping the ring. */
1214         rxdesc->status |= cpu_to_edmac(mdp, RD_RDLE);
1215
1216         memset(mdp->tx_ring, 0, tx_ringsize);
1217
1218         /* build Tx ring buffer */
1219         for (i = 0; i < mdp->num_tx_ring; i++) {
1220                 mdp->tx_skbuff[i] = NULL;
1221                 txdesc = &mdp->tx_ring[i];
1222                 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1223                 txdesc->buffer_length = 0;
1224                 if (i == 0) {
1225                         /* Tx descriptor address set */
1226                         sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
1227                         if (sh_eth_is_gether(mdp) ||
1228                             sh_eth_is_rz_fast_ether(mdp))
1229                                 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
1230                 }
1231         }
1232
1233         txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1234 }
1235
1236 /* Get skb and descriptor buffer */
1237 static int sh_eth_ring_init(struct net_device *ndev)
1238 {
1239         struct sh_eth_private *mdp = netdev_priv(ndev);
1240         int rx_ringsize, tx_ringsize;
1241
1242         /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1243          * card needs room to do 8 byte alignment, +2 so we can reserve
1244          * the first 2 bytes, and +16 gets room for the status word from the
1245          * card.
1246          */
1247         mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1248                           (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
1249         if (mdp->cd->rpadir)
1250                 mdp->rx_buf_sz += NET_IP_ALIGN;
1251
1252         /* Allocate RX and TX skb rings */
1253         mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff),
1254                                  GFP_KERNEL);
1255         if (!mdp->rx_skbuff)
1256                 return -ENOMEM;
1257
1258         mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff),
1259                                  GFP_KERNEL);
1260         if (!mdp->tx_skbuff)
1261                 goto ring_free;
1262
1263         /* Allocate all Rx descriptors. */
1264         rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1265         mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
1266                                           GFP_KERNEL);
1267         if (!mdp->rx_ring)
1268                 goto ring_free;
1269
1270         mdp->dirty_rx = 0;
1271
1272         /* Allocate all Tx descriptors. */
1273         tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1274         mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
1275                                           GFP_KERNEL);
1276         if (!mdp->tx_ring)
1277                 goto ring_free;
1278         return 0;
1279
1280 ring_free:
1281         /* Free Rx and Tx skb ring buffer and DMA buffer */
1282         sh_eth_ring_free(ndev);
1283
1284         return -ENOMEM;
1285 }
1286
1287 static int sh_eth_dev_init(struct net_device *ndev, bool start)
1288 {
1289         int ret = 0;
1290         struct sh_eth_private *mdp = netdev_priv(ndev);
1291         u32 val;
1292
1293         /* Soft Reset */
1294         ret = sh_eth_reset(ndev);
1295         if (ret)
1296                 return ret;
1297
1298         if (mdp->cd->rmiimode)
1299                 sh_eth_write(ndev, 0x1, RMIIMODE);
1300
1301         /* Descriptor format */
1302         sh_eth_ring_format(ndev);
1303         if (mdp->cd->rpadir)
1304                 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
1305
1306         /* all sh_eth int mask */
1307         sh_eth_write(ndev, 0, EESIPR);
1308
1309 #if defined(__LITTLE_ENDIAN)
1310         if (mdp->cd->hw_swap)
1311                 sh_eth_write(ndev, EDMR_EL, EDMR);
1312         else
1313 #endif
1314                 sh_eth_write(ndev, 0, EDMR);
1315
1316         /* FIFO size set */
1317         sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1318         sh_eth_write(ndev, 0, TFTR);
1319
1320         /* Frame recv control (enable multiple-packets per rx irq) */
1321         sh_eth_write(ndev, RMCR_RNC, RMCR);
1322
1323         sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);
1324
1325         if (mdp->cd->bculr)
1326                 sh_eth_write(ndev, 0x800, BCULR);       /* Burst sycle set */
1327
1328         sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
1329
1330         if (!mdp->cd->no_trimd)
1331                 sh_eth_write(ndev, 0, TRIMD);
1332
1333         /* Recv frame limit set register */
1334         sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1335                      RFLR);
1336
1337         sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
1338         if (start) {
1339                 mdp->irq_enabled = true;
1340                 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1341         }
1342
1343         /* PAUSE Prohibition */
1344         val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
1345                 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
1346
1347         sh_eth_write(ndev, val, ECMR);
1348
1349         if (mdp->cd->set_rate)
1350                 mdp->cd->set_rate(ndev);
1351
1352         /* E-MAC Status Register clear */
1353         sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1354
1355         /* E-MAC Interrupt Enable register */
1356         if (start)
1357                 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1358
1359         /* Set MAC address */
1360         update_mac_address(ndev);
1361
1362         /* mask reset */
1363         if (mdp->cd->apr)
1364                 sh_eth_write(ndev, APR_AP, APR);
1365         if (mdp->cd->mpr)
1366                 sh_eth_write(ndev, MPR_MP, MPR);
1367         if (mdp->cd->tpauser)
1368                 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1369
1370         if (start) {
1371                 /* Setting the Rx mode will start the Rx process. */
1372                 sh_eth_write(ndev, EDRRR_R, EDRRR);
1373
1374                 netif_start_queue(ndev);
1375         }
1376
1377         return ret;
1378 }
1379
1380 static void sh_eth_dev_exit(struct net_device *ndev)
1381 {
1382         struct sh_eth_private *mdp = netdev_priv(ndev);
1383         int i;
1384
1385         /* Deactivate all TX descriptors, so DMA should stop at next
1386          * packet boundary if it's currently running
1387          */
1388         for (i = 0; i < mdp->num_tx_ring; i++)
1389                 mdp->tx_ring[i].status &= ~cpu_to_edmac(mdp, TD_TACT);
1390
1391         /* Disable TX FIFO egress to MAC */
1392         sh_eth_rcv_snd_disable(ndev);
1393
1394         /* Stop RX DMA at next packet boundary */
1395         sh_eth_write(ndev, 0, EDRRR);
1396
1397         /* Aside from TX DMA, we can't tell when the hardware is
1398          * really stopped, so we need to reset to make sure.
1399          * Before doing that, wait for long enough to *probably*
1400          * finish transmitting the last packet and poll stats.
1401          */
1402         msleep(2); /* max frame time at 10 Mbps < 1250 us */
1403         sh_eth_get_stats(ndev);
1404         sh_eth_reset(ndev);
1405
1406         /* Set MAC address again */
1407         update_mac_address(ndev);
1408 }
1409
1410 /* free Tx skb function */
1411 static int sh_eth_txfree(struct net_device *ndev)
1412 {
1413         struct sh_eth_private *mdp = netdev_priv(ndev);
1414         struct sh_eth_txdesc *txdesc;
1415         int free_num = 0;
1416         int entry = 0;
1417
1418         for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1419                 entry = mdp->dirty_tx % mdp->num_tx_ring;
1420                 txdesc = &mdp->tx_ring[entry];
1421                 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
1422                         break;
1423                 /* TACT bit must be checked before all the following reads */
1424                 dma_rmb();
1425                 netif_info(mdp, tx_done, ndev,
1426                            "tx entry %d status 0x%08x\n",
1427                            entry, edmac_to_cpu(mdp, txdesc->status));
1428                 /* Free the original skb. */
1429                 if (mdp->tx_skbuff[entry]) {
1430                         dma_unmap_single(&ndev->dev,
1431                                          edmac_to_cpu(mdp, txdesc->addr),
1432                                          txdesc->buffer_length, DMA_TO_DEVICE);
1433                         dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1434                         mdp->tx_skbuff[entry] = NULL;
1435                         free_num++;
1436                 }
1437                 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1438                 if (entry >= mdp->num_tx_ring - 1)
1439                         txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1440
1441                 ndev->stats.tx_packets++;
1442                 ndev->stats.tx_bytes += txdesc->buffer_length;
1443         }
1444         return free_num;
1445 }
1446
1447 /* Packet receive function */
1448 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
1449 {
1450         struct sh_eth_private *mdp = netdev_priv(ndev);
1451         struct sh_eth_rxdesc *rxdesc;
1452
1453         int entry = mdp->cur_rx % mdp->num_rx_ring;
1454         int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
1455         int limit;
1456         struct sk_buff *skb;
1457         u16 pkt_len = 0;
1458         u32 desc_status;
1459         int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1460         dma_addr_t dma_addr;
1461
1462         boguscnt = min(boguscnt, *quota);
1463         limit = boguscnt;
1464         rxdesc = &mdp->rx_ring[entry];
1465         while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
1466                 /* RACT bit must be checked before all the following reads */
1467                 dma_rmb();
1468                 desc_status = edmac_to_cpu(mdp, rxdesc->status);
1469                 pkt_len = rxdesc->frame_length;
1470
1471                 if (--boguscnt < 0)
1472                         break;
1473
1474                 netif_info(mdp, rx_status, ndev,
1475                            "rx entry %d status 0x%08x len %d\n",
1476                            entry, desc_status, pkt_len);
1477
1478                 if (!(desc_status & RDFEND))
1479                         ndev->stats.rx_length_errors++;
1480
1481                 /* In case of almost all GETHER/ETHERs, the Receive Frame State
1482                  * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1483                  * bit 0. However, in case of the R8A7740 and R7S72100
1484                  * the RFS bits are from bit 25 to bit 16. So, the
1485                  * driver needs right shifting by 16.
1486                  */
1487                 if (mdp->cd->shift_rd0)
1488                         desc_status >>= 16;
1489
1490                 skb = mdp->rx_skbuff[entry];
1491                 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1492                                    RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1493                         ndev->stats.rx_errors++;
1494                         if (desc_status & RD_RFS1)
1495                                 ndev->stats.rx_crc_errors++;
1496                         if (desc_status & RD_RFS2)
1497                                 ndev->stats.rx_frame_errors++;
1498                         if (desc_status & RD_RFS3)
1499                                 ndev->stats.rx_length_errors++;
1500                         if (desc_status & RD_RFS4)
1501                                 ndev->stats.rx_length_errors++;
1502                         if (desc_status & RD_RFS6)
1503                                 ndev->stats.rx_missed_errors++;
1504                         if (desc_status & RD_RFS10)
1505                                 ndev->stats.rx_over_errors++;
1506                 } else  if (skb) {
1507                         dma_addr = edmac_to_cpu(mdp, rxdesc->addr);
1508                         if (!mdp->cd->hw_swap)
1509                                 sh_eth_soft_swap(
1510                                         phys_to_virt(ALIGN(dma_addr, 4)),
1511                                         pkt_len + 2);
1512                         mdp->rx_skbuff[entry] = NULL;
1513                         if (mdp->cd->rpadir)
1514                                 skb_reserve(skb, NET_IP_ALIGN);
1515                         dma_unmap_single(&ndev->dev, dma_addr,
1516                                          ALIGN(mdp->rx_buf_sz, 32),
1517                                          DMA_FROM_DEVICE);
1518                         skb_put(skb, pkt_len);
1519                         skb->protocol = eth_type_trans(skb, ndev);
1520                         netif_receive_skb(skb);
1521                         ndev->stats.rx_packets++;
1522                         ndev->stats.rx_bytes += pkt_len;
1523                         if (desc_status & RD_RFS8)
1524                                 ndev->stats.multicast++;
1525                 }
1526                 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
1527                 rxdesc = &mdp->rx_ring[entry];
1528         }
1529
1530         /* Refill the Rx ring buffers. */
1531         for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1532                 entry = mdp->dirty_rx % mdp->num_rx_ring;
1533                 rxdesc = &mdp->rx_ring[entry];
1534                 /* The size of the buffer is 32 byte boundary. */
1535                 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 32);
1536
1537                 if (mdp->rx_skbuff[entry] == NULL) {
1538                         skb = netdev_alloc_skb(ndev, skbuff_size);
1539                         if (skb == NULL)
1540                                 break;  /* Better luck next round. */
1541                         sh_eth_set_receive_align(skb);
1542                         dma_addr = dma_map_single(&ndev->dev, skb->data,
1543                                                   rxdesc->buffer_length,
1544                                                   DMA_FROM_DEVICE);
1545                         if (dma_mapping_error(&ndev->dev, dma_addr)) {
1546                                 kfree_skb(skb);
1547                                 break;
1548                         }
1549                         mdp->rx_skbuff[entry] = skb;
1550
1551                         skb_checksum_none_assert(skb);
1552                         rxdesc->addr = cpu_to_edmac(mdp, dma_addr);
1553                 }
1554                 dma_wmb(); /* RACT bit must be set after all the above writes */
1555                 if (entry >= mdp->num_rx_ring - 1)
1556                         rxdesc->status |=
1557                                 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDLE);
1558                 else
1559                         rxdesc->status |=
1560                                 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1561         }
1562
1563         /* Restart Rx engine if stopped. */
1564         /* If we don't need to check status, don't. -KDU */
1565         if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1566                 /* fix the values for the next receiving if RDE is set */
1567                 if (intr_status & EESR_RDE &&
1568                     mdp->reg_offset[RDFAR] != SH_ETH_OFFSET_INVALID) {
1569                         u32 count = (sh_eth_read(ndev, RDFAR) -
1570                                      sh_eth_read(ndev, RDLAR)) >> 4;
1571
1572                         mdp->cur_rx = count;
1573                         mdp->dirty_rx = count;
1574                 }
1575                 sh_eth_write(ndev, EDRRR_R, EDRRR);
1576         }
1577
1578         *quota -= limit - boguscnt - 1;
1579
1580         return *quota <= 0;
1581 }
1582
1583 static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1584 {
1585         /* disable tx and rx */
1586         sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
1587                 ~(ECMR_RE | ECMR_TE), ECMR);
1588 }
1589
1590 static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1591 {
1592         /* enable tx and rx */
1593         sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
1594                 (ECMR_RE | ECMR_TE), ECMR);
1595 }
1596
1597 /* error control function */
1598 static void sh_eth_error(struct net_device *ndev, u32 intr_status)
1599 {
1600         struct sh_eth_private *mdp = netdev_priv(ndev);
1601         u32 felic_stat;
1602         u32 link_stat;
1603         u32 mask;
1604
1605         if (intr_status & EESR_ECI) {
1606                 felic_stat = sh_eth_read(ndev, ECSR);
1607                 sh_eth_write(ndev, felic_stat, ECSR);   /* clear int */
1608                 if (felic_stat & ECSR_ICD)
1609                         ndev->stats.tx_carrier_errors++;
1610                 if (felic_stat & ECSR_LCHNG) {
1611                         /* Link Changed */
1612                         if (mdp->cd->no_psr || mdp->no_ether_link) {
1613                                 goto ignore_link;
1614                         } else {
1615                                 link_stat = (sh_eth_read(ndev, PSR));
1616                                 if (mdp->ether_link_active_low)
1617                                         link_stat = ~link_stat;
1618                         }
1619                         if (!(link_stat & PHY_ST_LINK)) {
1620                                 sh_eth_rcv_snd_disable(ndev);
1621                         } else {
1622                                 /* Link Up */
1623                                 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
1624                                                    ~DMAC_M_ECI, EESIPR);
1625                                 /* clear int */
1626                                 sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
1627                                              ECSR);
1628                                 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
1629                                                    DMAC_M_ECI, EESIPR);
1630                                 /* enable tx and rx */
1631                                 sh_eth_rcv_snd_enable(ndev);
1632                         }
1633                 }
1634         }
1635
1636 ignore_link:
1637         if (intr_status & EESR_TWB) {
1638                 /* Unused write back interrupt */
1639                 if (intr_status & EESR_TABT) {  /* Transmit Abort int */
1640                         ndev->stats.tx_aborted_errors++;
1641                         netif_err(mdp, tx_err, ndev, "Transmit Abort\n");
1642                 }
1643         }
1644
1645         if (intr_status & EESR_RABT) {
1646                 /* Receive Abort int */
1647                 if (intr_status & EESR_RFRMER) {
1648                         /* Receive Frame Overflow int */
1649                         ndev->stats.rx_frame_errors++;
1650                 }
1651         }
1652
1653         if (intr_status & EESR_TDE) {
1654                 /* Transmit Descriptor Empty int */
1655                 ndev->stats.tx_fifo_errors++;
1656                 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n");
1657         }
1658
1659         if (intr_status & EESR_TFE) {
1660                 /* FIFO under flow */
1661                 ndev->stats.tx_fifo_errors++;
1662                 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n");
1663         }
1664
1665         if (intr_status & EESR_RDE) {
1666                 /* Receive Descriptor Empty int */
1667                 ndev->stats.rx_over_errors++;
1668         }
1669
1670         if (intr_status & EESR_RFE) {
1671                 /* Receive FIFO Overflow int */
1672                 ndev->stats.rx_fifo_errors++;
1673         }
1674
1675         if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1676                 /* Address Error */
1677                 ndev->stats.tx_fifo_errors++;
1678                 netif_err(mdp, tx_err, ndev, "Address Error\n");
1679         }
1680
1681         mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1682         if (mdp->cd->no_ade)
1683                 mask &= ~EESR_ADE;
1684         if (intr_status & mask) {
1685                 /* Tx error */
1686                 u32 edtrr = sh_eth_read(ndev, EDTRR);
1687
1688                 /* dmesg */
1689                 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1690                            intr_status, mdp->cur_tx, mdp->dirty_tx,
1691                            (u32)ndev->state, edtrr);
1692                 /* dirty buffer free */
1693                 sh_eth_txfree(ndev);
1694
1695                 /* SH7712 BUG */
1696                 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
1697                         /* tx dma start */
1698                         sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1699                 }
1700                 /* wakeup */
1701                 netif_wake_queue(ndev);
1702         }
1703 }
1704
1705 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1706 {
1707         struct net_device *ndev = netdev;
1708         struct sh_eth_private *mdp = netdev_priv(ndev);
1709         struct sh_eth_cpu_data *cd = mdp->cd;
1710         irqreturn_t ret = IRQ_NONE;
1711         u32 intr_status, intr_enable;
1712
1713         spin_lock(&mdp->lock);
1714
1715         /* Get interrupt status */
1716         intr_status = sh_eth_read(ndev, EESR);
1717         /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1718          * enabled since it's the one that  comes thru regardless of the mask,
1719          * and we need to fully handle it in sh_eth_error() in order to quench
1720          * it as it doesn't get cleared by just writing 1 to the ECI bit...
1721          */
1722         intr_enable = sh_eth_read(ndev, EESIPR);
1723         intr_status &= intr_enable | DMAC_M_ECI;
1724         if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check))
1725                 ret = IRQ_HANDLED;
1726         else
1727                 goto out;
1728
1729         if (!likely(mdp->irq_enabled)) {
1730                 sh_eth_write(ndev, 0, EESIPR);
1731                 goto out;
1732         }
1733
1734         if (intr_status & EESR_RX_CHECK) {
1735                 if (napi_schedule_prep(&mdp->napi)) {
1736                         /* Mask Rx interrupts */
1737                         sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1738                                      EESIPR);
1739                         __napi_schedule(&mdp->napi);
1740                 } else {
1741                         netdev_warn(ndev,
1742                                     "ignoring interrupt, status 0x%08x, mask 0x%08x.\n",
1743                                     intr_status, intr_enable);
1744                 }
1745         }
1746
1747         /* Tx Check */
1748         if (intr_status & cd->tx_check) {
1749                 /* Clear Tx interrupts */
1750                 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1751
1752                 sh_eth_txfree(ndev);
1753                 netif_wake_queue(ndev);
1754         }
1755
1756         if (intr_status & cd->eesr_err_check) {
1757                 /* Clear error interrupts */
1758                 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1759
1760                 sh_eth_error(ndev, intr_status);
1761         }
1762
1763 out:
1764         spin_unlock(&mdp->lock);
1765
1766         return ret;
1767 }
1768
1769 static int sh_eth_poll(struct napi_struct *napi, int budget)
1770 {
1771         struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1772                                                   napi);
1773         struct net_device *ndev = napi->dev;
1774         int quota = budget;
1775         u32 intr_status;
1776
1777         for (;;) {
1778                 intr_status = sh_eth_read(ndev, EESR);
1779                 if (!(intr_status & EESR_RX_CHECK))
1780                         break;
1781                 /* Clear Rx interrupts */
1782                 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1783
1784                 if (sh_eth_rx(ndev, intr_status, &quota))
1785                         goto out;
1786         }
1787
1788         napi_complete(napi);
1789
1790         /* Reenable Rx interrupts */
1791         if (mdp->irq_enabled)
1792                 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1793 out:
1794         return budget - quota;
1795 }
1796
1797 /* PHY state control function */
1798 static void sh_eth_adjust_link(struct net_device *ndev)
1799 {
1800         struct sh_eth_private *mdp = netdev_priv(ndev);
1801         struct phy_device *phydev = mdp->phydev;
1802         int new_state = 0;
1803
1804         if (phydev->link) {
1805                 if (phydev->duplex != mdp->duplex) {
1806                         new_state = 1;
1807                         mdp->duplex = phydev->duplex;
1808                         if (mdp->cd->set_duplex)
1809                                 mdp->cd->set_duplex(ndev);
1810                 }
1811
1812                 if (phydev->speed != mdp->speed) {
1813                         new_state = 1;
1814                         mdp->speed = phydev->speed;
1815                         if (mdp->cd->set_rate)
1816                                 mdp->cd->set_rate(ndev);
1817                 }
1818                 if (!mdp->link) {
1819                         sh_eth_write(ndev,
1820                                      sh_eth_read(ndev, ECMR) & ~ECMR_TXF,
1821                                      ECMR);
1822                         new_state = 1;
1823                         mdp->link = phydev->link;
1824                         if (mdp->cd->no_psr || mdp->no_ether_link)
1825                                 sh_eth_rcv_snd_enable(ndev);
1826                 }
1827         } else if (mdp->link) {
1828                 new_state = 1;
1829                 mdp->link = 0;
1830                 mdp->speed = 0;
1831                 mdp->duplex = -1;
1832                 if (mdp->cd->no_psr || mdp->no_ether_link)
1833                         sh_eth_rcv_snd_disable(ndev);
1834         }
1835
1836         if (new_state && netif_msg_link(mdp))
1837                 phy_print_status(phydev);
1838 }
1839
1840 /* PHY init function */
1841 static int sh_eth_phy_init(struct net_device *ndev)
1842 {
1843         struct device_node *np = ndev->dev.parent->of_node;
1844         struct sh_eth_private *mdp = netdev_priv(ndev);
1845         struct phy_device *phydev = NULL;
1846
1847         mdp->link = 0;
1848         mdp->speed = 0;
1849         mdp->duplex = -1;
1850
1851         /* Try connect to PHY */
1852         if (np) {
1853                 struct device_node *pn;
1854
1855                 pn = of_parse_phandle(np, "phy-handle", 0);
1856                 phydev = of_phy_connect(ndev, pn,
1857                                         sh_eth_adjust_link, 0,
1858                                         mdp->phy_interface);
1859
1860                 if (!phydev)
1861                         phydev = ERR_PTR(-ENOENT);
1862         } else {
1863                 char phy_id[MII_BUS_ID_SIZE + 3];
1864
1865                 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1866                          mdp->mii_bus->id, mdp->phy_id);
1867
1868                 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1869                                      mdp->phy_interface);
1870         }
1871
1872         if (IS_ERR(phydev)) {
1873                 netdev_err(ndev, "failed to connect PHY\n");
1874                 return PTR_ERR(phydev);
1875         }
1876
1877         netdev_info(ndev, "attached PHY %d (IRQ %d) to driver %s\n",
1878                     phydev->addr, phydev->irq, phydev->drv->name);
1879
1880         mdp->phydev = phydev;
1881
1882         return 0;
1883 }
1884
1885 /* PHY control start function */
1886 static int sh_eth_phy_start(struct net_device *ndev)
1887 {
1888         struct sh_eth_private *mdp = netdev_priv(ndev);
1889         int ret;
1890
1891         ret = sh_eth_phy_init(ndev);
1892         if (ret)
1893                 return ret;
1894
1895         phy_start(mdp->phydev);
1896
1897         return 0;
1898 }
1899
1900 static int sh_eth_get_settings(struct net_device *ndev,
1901                                struct ethtool_cmd *ecmd)
1902 {
1903         struct sh_eth_private *mdp = netdev_priv(ndev);
1904         unsigned long flags;
1905         int ret;
1906
1907         if (!mdp->phydev)
1908                 return -ENODEV;
1909
1910         spin_lock_irqsave(&mdp->lock, flags);
1911         ret = phy_ethtool_gset(mdp->phydev, ecmd);
1912         spin_unlock_irqrestore(&mdp->lock, flags);
1913
1914         return ret;
1915 }
1916
1917 static int sh_eth_set_settings(struct net_device *ndev,
1918                                struct ethtool_cmd *ecmd)
1919 {
1920         struct sh_eth_private *mdp = netdev_priv(ndev);
1921         unsigned long flags;
1922         int ret;
1923
1924         if (!mdp->phydev)
1925                 return -ENODEV;
1926
1927         spin_lock_irqsave(&mdp->lock, flags);
1928
1929         /* disable tx and rx */
1930         sh_eth_rcv_snd_disable(ndev);
1931
1932         ret = phy_ethtool_sset(mdp->phydev, ecmd);
1933         if (ret)
1934                 goto error_exit;
1935
1936         if (ecmd->duplex == DUPLEX_FULL)
1937                 mdp->duplex = 1;
1938         else
1939                 mdp->duplex = 0;
1940
1941         if (mdp->cd->set_duplex)
1942                 mdp->cd->set_duplex(ndev);
1943
1944 error_exit:
1945         mdelay(1);
1946
1947         /* enable tx and rx */
1948         sh_eth_rcv_snd_enable(ndev);
1949
1950         spin_unlock_irqrestore(&mdp->lock, flags);
1951
1952         return ret;
1953 }
1954
1955 /* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the
1956  * version must be bumped as well.  Just adding registers up to that
1957  * limit is fine, as long as the existing register indices don't
1958  * change.
1959  */
1960 #define SH_ETH_REG_DUMP_VERSION         1
1961 #define SH_ETH_REG_DUMP_MAX_REGS        256
1962
1963 static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf)
1964 {
1965         struct sh_eth_private *mdp = netdev_priv(ndev);
1966         struct sh_eth_cpu_data *cd = mdp->cd;
1967         u32 *valid_map;
1968         size_t len;
1969
1970         BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS);
1971
1972         /* Dump starts with a bitmap that tells ethtool which
1973          * registers are defined for this chip.
1974          */
1975         len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32);
1976         if (buf) {
1977                 valid_map = buf;
1978                 buf += len;
1979         } else {
1980                 valid_map = NULL;
1981         }
1982
1983         /* Add a register to the dump, if it has a defined offset.
1984          * This automatically skips most undefined registers, but for
1985          * some it is also necessary to check a capability flag in
1986          * struct sh_eth_cpu_data.
1987          */
1988 #define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32)
1989 #define add_reg_from(reg, read_expr) do {                               \
1990                 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) {    \
1991                         if (buf) {                                      \
1992                                 mark_reg_valid(reg);                    \
1993                                 *buf++ = read_expr;                     \
1994                         }                                               \
1995                         ++len;                                          \
1996                 }                                                       \
1997         } while (0)
1998 #define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg))
1999 #define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg))
2000
2001         add_reg(EDSR);
2002         add_reg(EDMR);
2003         add_reg(EDTRR);
2004         add_reg(EDRRR);
2005         add_reg(EESR);
2006         add_reg(EESIPR);
2007         add_reg(TDLAR);
2008         add_reg(TDFAR);
2009         add_reg(TDFXR);
2010         add_reg(TDFFR);
2011         add_reg(RDLAR);
2012         add_reg(RDFAR);
2013         add_reg(RDFXR);
2014         add_reg(RDFFR);
2015         add_reg(TRSCER);
2016         add_reg(RMFCR);
2017         add_reg(TFTR);
2018         add_reg(FDR);
2019         add_reg(RMCR);
2020         add_reg(TFUCR);
2021         add_reg(RFOCR);
2022         if (cd->rmiimode)
2023                 add_reg(RMIIMODE);
2024         add_reg(FCFTR);
2025         if (cd->rpadir)
2026                 add_reg(RPADIR);
2027         if (!cd->no_trimd)
2028                 add_reg(TRIMD);
2029         add_reg(ECMR);
2030         add_reg(ECSR);
2031         add_reg(ECSIPR);
2032         add_reg(PIR);
2033         if (!cd->no_psr)
2034                 add_reg(PSR);
2035         add_reg(RDMLR);
2036         add_reg(RFLR);
2037         add_reg(IPGR);
2038         if (cd->apr)
2039                 add_reg(APR);
2040         if (cd->mpr)
2041                 add_reg(MPR);
2042         add_reg(RFCR);
2043         add_reg(RFCF);
2044         if (cd->tpauser)
2045                 add_reg(TPAUSER);
2046         add_reg(TPAUSECR);
2047         add_reg(GECMR);
2048         if (cd->bculr)
2049                 add_reg(BCULR);
2050         add_reg(MAHR);
2051         add_reg(MALR);
2052         add_reg(TROCR);
2053         add_reg(CDCR);
2054         add_reg(LCCR);
2055         add_reg(CNDCR);
2056         add_reg(CEFCR);
2057         add_reg(FRECR);
2058         add_reg(TSFRCR);
2059         add_reg(TLFRCR);
2060         add_reg(CERCR);
2061         add_reg(CEECR);
2062         add_reg(MAFCR);
2063         if (cd->rtrate)
2064                 add_reg(RTRATE);
2065         if (cd->hw_crc)
2066                 add_reg(CSMR);
2067         if (cd->select_mii)
2068                 add_reg(RMII_MII);
2069         add_reg(ARSTR);
2070         if (cd->tsu) {
2071                 add_tsu_reg(TSU_CTRST);
2072                 add_tsu_reg(TSU_FWEN0);
2073                 add_tsu_reg(TSU_FWEN1);
2074                 add_tsu_reg(TSU_FCM);
2075                 add_tsu_reg(TSU_BSYSL0);
2076                 add_tsu_reg(TSU_BSYSL1);
2077                 add_tsu_reg(TSU_PRISL0);
2078                 add_tsu_reg(TSU_PRISL1);
2079                 add_tsu_reg(TSU_FWSL0);
2080                 add_tsu_reg(TSU_FWSL1);
2081                 add_tsu_reg(TSU_FWSLC);
2082                 add_tsu_reg(TSU_QTAG0);
2083                 add_tsu_reg(TSU_QTAG1);
2084                 add_tsu_reg(TSU_QTAGM0);
2085                 add_tsu_reg(TSU_QTAGM1);
2086                 add_tsu_reg(TSU_FWSR);
2087                 add_tsu_reg(TSU_FWINMK);
2088                 add_tsu_reg(TSU_ADQT0);
2089                 add_tsu_reg(TSU_ADQT1);
2090                 add_tsu_reg(TSU_VTAG0);
2091                 add_tsu_reg(TSU_VTAG1);
2092                 add_tsu_reg(TSU_ADSBSY);
2093                 add_tsu_reg(TSU_TEN);
2094                 add_tsu_reg(TSU_POST1);
2095                 add_tsu_reg(TSU_POST2);
2096                 add_tsu_reg(TSU_POST3);
2097                 add_tsu_reg(TSU_POST4);
2098                 if (mdp->reg_offset[TSU_ADRH0] != SH_ETH_OFFSET_INVALID) {
2099                         /* This is the start of a table, not just a single
2100                          * register.
2101                          */
2102                         if (buf) {
2103                                 unsigned int i;
2104
2105                                 mark_reg_valid(TSU_ADRH0);
2106                                 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++)
2107                                         *buf++ = ioread32(
2108                                                 mdp->tsu_addr +
2109                                                 mdp->reg_offset[TSU_ADRH0] +
2110                                                 i * 4);
2111                         }
2112                         len += SH_ETH_TSU_CAM_ENTRIES * 2;
2113                 }
2114         }
2115
2116 #undef mark_reg_valid
2117 #undef add_reg_from
2118 #undef add_reg
2119 #undef add_tsu_reg
2120
2121         return len * 4;
2122 }
2123
2124 static int sh_eth_get_regs_len(struct net_device *ndev)
2125 {
2126         return __sh_eth_get_regs(ndev, NULL);
2127 }
2128
2129 static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs,
2130                             void *buf)
2131 {
2132         struct sh_eth_private *mdp = netdev_priv(ndev);
2133
2134         regs->version = SH_ETH_REG_DUMP_VERSION;
2135
2136         pm_runtime_get_sync(&mdp->pdev->dev);
2137         __sh_eth_get_regs(ndev, buf);
2138         pm_runtime_put_sync(&mdp->pdev->dev);
2139 }
2140
2141 static int sh_eth_nway_reset(struct net_device *ndev)
2142 {
2143         struct sh_eth_private *mdp = netdev_priv(ndev);
2144         unsigned long flags;
2145         int ret;
2146
2147         if (!mdp->phydev)
2148                 return -ENODEV;
2149
2150         spin_lock_irqsave(&mdp->lock, flags);
2151         ret = phy_start_aneg(mdp->phydev);
2152         spin_unlock_irqrestore(&mdp->lock, flags);
2153
2154         return ret;
2155 }
2156
2157 static u32 sh_eth_get_msglevel(struct net_device *ndev)
2158 {
2159         struct sh_eth_private *mdp = netdev_priv(ndev);
2160         return mdp->msg_enable;
2161 }
2162
2163 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
2164 {
2165         struct sh_eth_private *mdp = netdev_priv(ndev);
2166         mdp->msg_enable = value;
2167 }
2168
2169 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
2170         "rx_current", "tx_current",
2171         "rx_dirty", "tx_dirty",
2172 };
2173 #define SH_ETH_STATS_LEN  ARRAY_SIZE(sh_eth_gstrings_stats)
2174
2175 static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
2176 {
2177         switch (sset) {
2178         case ETH_SS_STATS:
2179                 return SH_ETH_STATS_LEN;
2180         default:
2181                 return -EOPNOTSUPP;
2182         }
2183 }
2184
2185 static void sh_eth_get_ethtool_stats(struct net_device *ndev,
2186                                      struct ethtool_stats *stats, u64 *data)
2187 {
2188         struct sh_eth_private *mdp = netdev_priv(ndev);
2189         int i = 0;
2190
2191         /* device-specific stats */
2192         data[i++] = mdp->cur_rx;
2193         data[i++] = mdp->cur_tx;
2194         data[i++] = mdp->dirty_rx;
2195         data[i++] = mdp->dirty_tx;
2196 }
2197
2198 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
2199 {
2200         switch (stringset) {
2201         case ETH_SS_STATS:
2202                 memcpy(data, *sh_eth_gstrings_stats,
2203                        sizeof(sh_eth_gstrings_stats));
2204                 break;
2205         }
2206 }
2207
2208 static void sh_eth_get_ringparam(struct net_device *ndev,
2209                                  struct ethtool_ringparam *ring)
2210 {
2211         struct sh_eth_private *mdp = netdev_priv(ndev);
2212
2213         ring->rx_max_pending = RX_RING_MAX;
2214         ring->tx_max_pending = TX_RING_MAX;
2215         ring->rx_pending = mdp->num_rx_ring;
2216         ring->tx_pending = mdp->num_tx_ring;
2217 }
2218
2219 static int sh_eth_set_ringparam(struct net_device *ndev,
2220                                 struct ethtool_ringparam *ring)
2221 {
2222         struct sh_eth_private *mdp = netdev_priv(ndev);
2223         int ret;
2224
2225         if (ring->tx_pending > TX_RING_MAX ||
2226             ring->rx_pending > RX_RING_MAX ||
2227             ring->tx_pending < TX_RING_MIN ||
2228             ring->rx_pending < RX_RING_MIN)
2229                 return -EINVAL;
2230         if (ring->rx_mini_pending || ring->rx_jumbo_pending)
2231                 return -EINVAL;
2232
2233         if (netif_running(ndev)) {
2234                 netif_device_detach(ndev);
2235                 netif_tx_disable(ndev);
2236
2237                 /* Serialise with the interrupt handler and NAPI, then
2238                  * disable interrupts.  We have to clear the
2239                  * irq_enabled flag first to ensure that interrupts
2240                  * won't be re-enabled.
2241                  */
2242                 mdp->irq_enabled = false;
2243                 synchronize_irq(ndev->irq);
2244                 napi_synchronize(&mdp->napi);
2245                 sh_eth_write(ndev, 0x0000, EESIPR);
2246
2247                 sh_eth_dev_exit(ndev);
2248
2249                 /* Free all the skbuffs in the Rx queue and the DMA buffers. */
2250                 sh_eth_ring_free(ndev);
2251         }
2252
2253         /* Set new parameters */
2254         mdp->num_rx_ring = ring->rx_pending;
2255         mdp->num_tx_ring = ring->tx_pending;
2256
2257         if (netif_running(ndev)) {
2258                 ret = sh_eth_ring_init(ndev);
2259                 if (ret < 0) {
2260                         netdev_err(ndev, "%s: sh_eth_ring_init failed.\n",
2261                                    __func__);
2262                         return ret;
2263                 }
2264                 ret = sh_eth_dev_init(ndev, false);
2265                 if (ret < 0) {
2266                         netdev_err(ndev, "%s: sh_eth_dev_init failed.\n",
2267                                    __func__);
2268                         return ret;
2269                 }
2270
2271                 mdp->irq_enabled = true;
2272                 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
2273                 /* Setting the Rx mode will start the Rx process. */
2274                 sh_eth_write(ndev, EDRRR_R, EDRRR);
2275                 netif_device_attach(ndev);
2276         }
2277
2278         return 0;
2279 }
2280
2281 static const struct ethtool_ops sh_eth_ethtool_ops = {
2282         .get_settings   = sh_eth_get_settings,
2283         .set_settings   = sh_eth_set_settings,
2284         .get_regs_len   = sh_eth_get_regs_len,
2285         .get_regs       = sh_eth_get_regs,
2286         .nway_reset     = sh_eth_nway_reset,
2287         .get_msglevel   = sh_eth_get_msglevel,
2288         .set_msglevel   = sh_eth_set_msglevel,
2289         .get_link       = ethtool_op_get_link,
2290         .get_strings    = sh_eth_get_strings,
2291         .get_ethtool_stats  = sh_eth_get_ethtool_stats,
2292         .get_sset_count     = sh_eth_get_sset_count,
2293         .get_ringparam  = sh_eth_get_ringparam,
2294         .set_ringparam  = sh_eth_set_ringparam,
2295 };
2296
2297 /* network device open function */
2298 static int sh_eth_open(struct net_device *ndev)
2299 {
2300         int ret = 0;
2301         struct sh_eth_private *mdp = netdev_priv(ndev);
2302
2303         pm_runtime_get_sync(&mdp->pdev->dev);
2304
2305         napi_enable(&mdp->napi);
2306
2307         ret = request_irq(ndev->irq, sh_eth_interrupt,
2308                           mdp->cd->irq_flags, ndev->name, ndev);
2309         if (ret) {
2310                 netdev_err(ndev, "Can not assign IRQ number\n");
2311                 goto out_napi_off;
2312         }
2313
2314         /* Descriptor set */
2315         ret = sh_eth_ring_init(ndev);
2316         if (ret)
2317                 goto out_free_irq;
2318
2319         /* device init */
2320         ret = sh_eth_dev_init(ndev, true);
2321         if (ret)
2322                 goto out_free_irq;
2323
2324         /* PHY control start*/
2325         ret = sh_eth_phy_start(ndev);
2326         if (ret)
2327                 goto out_free_irq;
2328
2329         mdp->is_opened = 1;
2330
2331         return ret;
2332
2333 out_free_irq:
2334         free_irq(ndev->irq, ndev);
2335 out_napi_off:
2336         napi_disable(&mdp->napi);
2337         pm_runtime_put_sync(&mdp->pdev->dev);
2338         return ret;
2339 }
2340
2341 /* Timeout function */
2342 static void sh_eth_tx_timeout(struct net_device *ndev)
2343 {
2344         struct sh_eth_private *mdp = netdev_priv(ndev);
2345         struct sh_eth_rxdesc *rxdesc;
2346         int i;
2347
2348         netif_stop_queue(ndev);
2349
2350         netif_err(mdp, timer, ndev,
2351                   "transmit timed out, status %8.8x, resetting...\n",
2352                   sh_eth_read(ndev, EESR));
2353
2354         /* tx_errors count up */
2355         ndev->stats.tx_errors++;
2356
2357         /* Free all the skbuffs in the Rx queue. */
2358         for (i = 0; i < mdp->num_rx_ring; i++) {
2359                 rxdesc = &mdp->rx_ring[i];
2360                 rxdesc->status = cpu_to_edmac(mdp, 0);
2361                 rxdesc->addr = cpu_to_edmac(mdp, 0xBADF00D0);
2362                 dev_kfree_skb(mdp->rx_skbuff[i]);
2363                 mdp->rx_skbuff[i] = NULL;
2364         }
2365         for (i = 0; i < mdp->num_tx_ring; i++) {
2366                 dev_kfree_skb(mdp->tx_skbuff[i]);
2367                 mdp->tx_skbuff[i] = NULL;
2368         }
2369
2370         /* device init */
2371         sh_eth_dev_init(ndev, true);
2372 }
2373
2374 /* Packet transmit function */
2375 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2376 {
2377         struct sh_eth_private *mdp = netdev_priv(ndev);
2378         struct sh_eth_txdesc *txdesc;
2379         dma_addr_t dma_addr;
2380         u32 entry;
2381         unsigned long flags;
2382
2383         spin_lock_irqsave(&mdp->lock, flags);
2384         if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
2385                 if (!sh_eth_txfree(ndev)) {
2386                         netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
2387                         netif_stop_queue(ndev);
2388                         spin_unlock_irqrestore(&mdp->lock, flags);
2389                         return NETDEV_TX_BUSY;
2390                 }
2391         }
2392         spin_unlock_irqrestore(&mdp->lock, flags);
2393
2394         if (skb_put_padto(skb, ETH_ZLEN))
2395                 return NETDEV_TX_OK;
2396
2397         entry = mdp->cur_tx % mdp->num_tx_ring;
2398         mdp->tx_skbuff[entry] = skb;
2399         txdesc = &mdp->tx_ring[entry];
2400         /* soft swap. */
2401         if (!mdp->cd->hw_swap)
2402                 sh_eth_soft_swap(PTR_ALIGN(skb->data, 4), skb->len + 2);
2403         dma_addr = dma_map_single(&ndev->dev, skb->data, skb->len,
2404                                   DMA_TO_DEVICE);
2405         if (dma_mapping_error(&ndev->dev, dma_addr)) {
2406                 kfree_skb(skb);
2407                 return NETDEV_TX_OK;
2408         }
2409         txdesc->addr = cpu_to_edmac(mdp, dma_addr);
2410         txdesc->buffer_length = skb->len;
2411
2412         dma_wmb(); /* TACT bit must be set after all the above writes */
2413         if (entry >= mdp->num_tx_ring - 1)
2414                 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
2415         else
2416                 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
2417
2418         mdp->cur_tx++;
2419
2420         if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
2421                 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
2422
2423         return NETDEV_TX_OK;
2424 }
2425
2426 /* The statistics registers have write-clear behaviour, which means we
2427  * will lose any increment between the read and write.  We mitigate
2428  * this by only clearing when we read a non-zero value, so we will
2429  * never falsely report a total of zero.
2430  */
2431 static void
2432 sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg)
2433 {
2434         u32 delta = sh_eth_read(ndev, reg);
2435
2436         if (delta) {
2437                 *stat += delta;
2438                 sh_eth_write(ndev, 0, reg);
2439         }
2440 }
2441
2442 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2443 {
2444         struct sh_eth_private *mdp = netdev_priv(ndev);
2445
2446         if (sh_eth_is_rz_fast_ether(mdp))
2447                 return &ndev->stats;
2448
2449         if (!mdp->is_opened)
2450                 return &ndev->stats;
2451
2452         sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR);
2453         sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR);
2454         sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR);
2455
2456         if (sh_eth_is_gether(mdp)) {
2457                 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2458                                    CERCR);
2459                 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2460                                    CEECR);
2461         } else {
2462                 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2463                                    CNDCR);
2464         }
2465
2466         return &ndev->stats;
2467 }
2468
2469 /* device close function */
2470 static int sh_eth_close(struct net_device *ndev)
2471 {
2472         struct sh_eth_private *mdp = netdev_priv(ndev);
2473
2474         netif_stop_queue(ndev);
2475
2476         /* Serialise with the interrupt handler and NAPI, then disable
2477          * interrupts.  We have to clear the irq_enabled flag first to
2478          * ensure that interrupts won't be re-enabled.
2479          */
2480         mdp->irq_enabled = false;
2481         synchronize_irq(ndev->irq);
2482         napi_disable(&mdp->napi);
2483         sh_eth_write(ndev, 0x0000, EESIPR);
2484
2485         sh_eth_dev_exit(ndev);
2486
2487         /* PHY Disconnect */
2488         if (mdp->phydev) {
2489                 phy_stop(mdp->phydev);
2490                 phy_disconnect(mdp->phydev);
2491                 mdp->phydev = NULL;
2492         }
2493
2494         free_irq(ndev->irq, ndev);
2495
2496         /* Free all the skbuffs in the Rx queue and the DMA buffer. */
2497         sh_eth_ring_free(ndev);
2498
2499         pm_runtime_put_sync(&mdp->pdev->dev);
2500
2501         mdp->is_opened = 0;
2502
2503         return 0;
2504 }
2505
2506 /* ioctl to device function */
2507 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2508 {
2509         struct sh_eth_private *mdp = netdev_priv(ndev);
2510         struct phy_device *phydev = mdp->phydev;
2511
2512         if (!netif_running(ndev))
2513                 return -EINVAL;
2514
2515         if (!phydev)
2516                 return -ENODEV;
2517
2518         return phy_mii_ioctl(phydev, rq, cmd);
2519 }
2520
2521 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2522 static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2523                                             int entry)
2524 {
2525         return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2526 }
2527
2528 static u32 sh_eth_tsu_get_post_mask(int entry)
2529 {
2530         return 0x0f << (28 - ((entry % 8) * 4));
2531 }
2532
2533 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2534 {
2535         return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2536 }
2537
2538 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2539                                              int entry)
2540 {
2541         struct sh_eth_private *mdp = netdev_priv(ndev);
2542         u32 tmp;
2543         void *reg_offset;
2544
2545         reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2546         tmp = ioread32(reg_offset);
2547         iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2548 }
2549
2550 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2551                                               int entry)
2552 {
2553         struct sh_eth_private *mdp = netdev_priv(ndev);
2554         u32 post_mask, ref_mask, tmp;
2555         void *reg_offset;
2556
2557         reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2558         post_mask = sh_eth_tsu_get_post_mask(entry);
2559         ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2560
2561         tmp = ioread32(reg_offset);
2562         iowrite32(tmp & ~post_mask, reg_offset);
2563
2564         /* If other port enables, the function returns "true" */
2565         return tmp & ref_mask;
2566 }
2567
2568 static int sh_eth_tsu_busy(struct net_device *ndev)
2569 {
2570         int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2571         struct sh_eth_private *mdp = netdev_priv(ndev);
2572
2573         while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2574                 udelay(10);
2575                 timeout--;
2576                 if (timeout <= 0) {
2577                         netdev_err(ndev, "%s: timeout\n", __func__);
2578                         return -ETIMEDOUT;
2579                 }
2580         }
2581
2582         return 0;
2583 }
2584
2585 static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2586                                   const u8 *addr)
2587 {
2588         u32 val;
2589
2590         val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2591         iowrite32(val, reg);
2592         if (sh_eth_tsu_busy(ndev) < 0)
2593                 return -EBUSY;
2594
2595         val = addr[4] << 8 | addr[5];
2596         iowrite32(val, reg + 4);
2597         if (sh_eth_tsu_busy(ndev) < 0)
2598                 return -EBUSY;
2599
2600         return 0;
2601 }
2602
2603 static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2604 {
2605         u32 val;
2606
2607         val = ioread32(reg);
2608         addr[0] = (val >> 24) & 0xff;
2609         addr[1] = (val >> 16) & 0xff;
2610         addr[2] = (val >> 8) & 0xff;
2611         addr[3] = val & 0xff;
2612         val = ioread32(reg + 4);
2613         addr[4] = (val >> 8) & 0xff;
2614         addr[5] = val & 0xff;
2615 }
2616
2617
2618 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2619 {
2620         struct sh_eth_private *mdp = netdev_priv(ndev);
2621         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2622         int i;
2623         u8 c_addr[ETH_ALEN];
2624
2625         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2626                 sh_eth_tsu_read_entry(reg_offset, c_addr);
2627                 if (ether_addr_equal(addr, c_addr))
2628                         return i;
2629         }
2630
2631         return -ENOENT;
2632 }
2633
2634 static int sh_eth_tsu_find_empty(struct net_device *ndev)
2635 {
2636         u8 blank[ETH_ALEN];
2637         int entry;
2638
2639         memset(blank, 0, sizeof(blank));
2640         entry = sh_eth_tsu_find_entry(ndev, blank);
2641         return (entry < 0) ? -ENOMEM : entry;
2642 }
2643
2644 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2645                                               int entry)
2646 {
2647         struct sh_eth_private *mdp = netdev_priv(ndev);
2648         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2649         int ret;
2650         u8 blank[ETH_ALEN];
2651
2652         sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2653                          ~(1 << (31 - entry)), TSU_TEN);
2654
2655         memset(blank, 0, sizeof(blank));
2656         ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2657         if (ret < 0)
2658                 return ret;
2659         return 0;
2660 }
2661
2662 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2663 {
2664         struct sh_eth_private *mdp = netdev_priv(ndev);
2665         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2666         int i, ret;
2667
2668         if (!mdp->cd->tsu)
2669                 return 0;
2670
2671         i = sh_eth_tsu_find_entry(ndev, addr);
2672         if (i < 0) {
2673                 /* No entry found, create one */
2674                 i = sh_eth_tsu_find_empty(ndev);
2675                 if (i < 0)
2676                         return -ENOMEM;
2677                 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2678                 if (ret < 0)
2679                         return ret;
2680
2681                 /* Enable the entry */
2682                 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2683                                  (1 << (31 - i)), TSU_TEN);
2684         }
2685
2686         /* Entry found or created, enable POST */
2687         sh_eth_tsu_enable_cam_entry_post(ndev, i);
2688
2689         return 0;
2690 }
2691
2692 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2693 {
2694         struct sh_eth_private *mdp = netdev_priv(ndev);
2695         int i, ret;
2696
2697         if (!mdp->cd->tsu)
2698                 return 0;
2699
2700         i = sh_eth_tsu_find_entry(ndev, addr);
2701         if (i) {
2702                 /* Entry found */
2703                 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2704                         goto done;
2705
2706                 /* Disable the entry if both ports was disabled */
2707                 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2708                 if (ret < 0)
2709                         return ret;
2710         }
2711 done:
2712         return 0;
2713 }
2714
2715 static int sh_eth_tsu_purge_all(struct net_device *ndev)
2716 {
2717         struct sh_eth_private *mdp = netdev_priv(ndev);
2718         int i, ret;
2719
2720         if (!mdp->cd->tsu)
2721                 return 0;
2722
2723         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2724                 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2725                         continue;
2726
2727                 /* Disable the entry if both ports was disabled */
2728                 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2729                 if (ret < 0)
2730                         return ret;
2731         }
2732
2733         return 0;
2734 }
2735
2736 static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2737 {
2738         struct sh_eth_private *mdp = netdev_priv(ndev);
2739         u8 addr[ETH_ALEN];
2740         void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2741         int i;
2742
2743         if (!mdp->cd->tsu)
2744                 return;
2745
2746         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2747                 sh_eth_tsu_read_entry(reg_offset, addr);
2748                 if (is_multicast_ether_addr(addr))
2749                         sh_eth_tsu_del_entry(ndev, addr);
2750         }
2751 }
2752
2753 /* Update promiscuous flag and multicast filter */
2754 static void sh_eth_set_rx_mode(struct net_device *ndev)
2755 {
2756         struct sh_eth_private *mdp = netdev_priv(ndev);
2757         u32 ecmr_bits;
2758         int mcast_all = 0;
2759         unsigned long flags;
2760
2761         spin_lock_irqsave(&mdp->lock, flags);
2762         /* Initial condition is MCT = 1, PRM = 0.
2763          * Depending on ndev->flags, set PRM or clear MCT
2764          */
2765         ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM;
2766         if (mdp->cd->tsu)
2767                 ecmr_bits |= ECMR_MCT;
2768
2769         if (!(ndev->flags & IFF_MULTICAST)) {
2770                 sh_eth_tsu_purge_mcast(ndev);
2771                 mcast_all = 1;
2772         }
2773         if (ndev->flags & IFF_ALLMULTI) {
2774                 sh_eth_tsu_purge_mcast(ndev);
2775                 ecmr_bits &= ~ECMR_MCT;
2776                 mcast_all = 1;
2777         }
2778
2779         if (ndev->flags & IFF_PROMISC) {
2780                 sh_eth_tsu_purge_all(ndev);
2781                 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2782         } else if (mdp->cd->tsu) {
2783                 struct netdev_hw_addr *ha;
2784                 netdev_for_each_mc_addr(ha, ndev) {
2785                         if (mcast_all && is_multicast_ether_addr(ha->addr))
2786                                 continue;
2787
2788                         if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2789                                 if (!mcast_all) {
2790                                         sh_eth_tsu_purge_mcast(ndev);
2791                                         ecmr_bits &= ~ECMR_MCT;
2792                                         mcast_all = 1;
2793                                 }
2794                         }
2795                 }
2796         }
2797
2798         /* update the ethernet mode */
2799         sh_eth_write(ndev, ecmr_bits, ECMR);
2800
2801         spin_unlock_irqrestore(&mdp->lock, flags);
2802 }
2803
2804 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2805 {
2806         if (!mdp->port)
2807                 return TSU_VTAG0;
2808         else
2809                 return TSU_VTAG1;
2810 }
2811
2812 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2813                                   __be16 proto, u16 vid)
2814 {
2815         struct sh_eth_private *mdp = netdev_priv(ndev);
2816         int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2817
2818         if (unlikely(!mdp->cd->tsu))
2819                 return -EPERM;
2820
2821         /* No filtering if vid = 0 */
2822         if (!vid)
2823                 return 0;
2824
2825         mdp->vlan_num_ids++;
2826
2827         /* The controller has one VLAN tag HW filter. So, if the filter is
2828          * already enabled, the driver disables it and the filte
2829          */
2830         if (mdp->vlan_num_ids > 1) {
2831                 /* disable VLAN filter */
2832                 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2833                 return 0;
2834         }
2835
2836         sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2837                          vtag_reg_index);
2838
2839         return 0;
2840 }
2841
2842 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2843                                    __be16 proto, u16 vid)
2844 {
2845         struct sh_eth_private *mdp = netdev_priv(ndev);
2846         int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2847
2848         if (unlikely(!mdp->cd->tsu))
2849                 return -EPERM;
2850
2851         /* No filtering if vid = 0 */
2852         if (!vid)
2853                 return 0;
2854
2855         mdp->vlan_num_ids--;
2856         sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2857
2858         return 0;
2859 }
2860
2861 /* SuperH's TSU register init function */
2862 static void sh_eth_tsu_init(struct sh_eth_private *mdp)
2863 {
2864         if (sh_eth_is_rz_fast_ether(mdp)) {
2865                 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2866                 return;
2867         }
2868
2869         sh_eth_tsu_write(mdp, 0, TSU_FWEN0);    /* Disable forward(0->1) */
2870         sh_eth_tsu_write(mdp, 0, TSU_FWEN1);    /* Disable forward(1->0) */
2871         sh_eth_tsu_write(mdp, 0, TSU_FCM);      /* forward fifo 3k-3k */
2872         sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2873         sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2874         sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2875         sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2876         sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2877         sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2878         sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
2879         if (sh_eth_is_gether(mdp)) {
2880                 sh_eth_tsu_write(mdp, 0, TSU_QTAG0);    /* Disable QTAG(0->1) */
2881                 sh_eth_tsu_write(mdp, 0, TSU_QTAG1);    /* Disable QTAG(1->0) */
2882         } else {
2883                 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0);   /* Disable QTAG(0->1) */
2884                 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1);   /* Disable QTAG(1->0) */
2885         }
2886         sh_eth_tsu_write(mdp, 0, TSU_FWSR);     /* all interrupt status clear */
2887         sh_eth_tsu_write(mdp, 0, TSU_FWINMK);   /* Disable all interrupt */
2888         sh_eth_tsu_write(mdp, 0, TSU_TEN);      /* Disable all CAM entry */
2889         sh_eth_tsu_write(mdp, 0, TSU_POST1);    /* Disable CAM entry [ 0- 7] */
2890         sh_eth_tsu_write(mdp, 0, TSU_POST2);    /* Disable CAM entry [ 8-15] */
2891         sh_eth_tsu_write(mdp, 0, TSU_POST3);    /* Disable CAM entry [16-23] */
2892         sh_eth_tsu_write(mdp, 0, TSU_POST4);    /* Disable CAM entry [24-31] */
2893 }
2894
2895 /* MDIO bus release function */
2896 static int sh_mdio_release(struct sh_eth_private *mdp)
2897 {
2898         /* unregister mdio bus */
2899         mdiobus_unregister(mdp->mii_bus);
2900
2901         /* free bitbang info */
2902         free_mdio_bitbang(mdp->mii_bus);
2903
2904         return 0;
2905 }
2906
2907 /* MDIO bus init function */
2908 static int sh_mdio_init(struct sh_eth_private *mdp,
2909                         struct sh_eth_plat_data *pd)
2910 {
2911         int ret, i;
2912         struct bb_info *bitbang;
2913         struct platform_device *pdev = mdp->pdev;
2914         struct device *dev = &mdp->pdev->dev;
2915
2916         /* create bit control struct for PHY */
2917         bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL);
2918         if (!bitbang)
2919                 return -ENOMEM;
2920
2921         /* bitbang init */
2922         bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
2923         bitbang->set_gate = pd->set_mdio_gate;
2924         bitbang->mdi_msk = PIR_MDI;
2925         bitbang->mdo_msk = PIR_MDO;
2926         bitbang->mmd_msk = PIR_MMD;
2927         bitbang->mdc_msk = PIR_MDC;
2928         bitbang->ctrl.ops = &bb_ops;
2929
2930         /* MII controller setting */
2931         mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
2932         if (!mdp->mii_bus)
2933                 return -ENOMEM;
2934
2935         /* Hook up MII support for ethtool */
2936         mdp->mii_bus->name = "sh_mii";
2937         mdp->mii_bus->parent = dev;
2938         snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2939                  pdev->name, pdev->id);
2940
2941         /* PHY IRQ */
2942         mdp->mii_bus->irq = devm_kmalloc_array(dev, PHY_MAX_ADDR, sizeof(int),
2943                                                GFP_KERNEL);
2944         if (!mdp->mii_bus->irq) {
2945                 ret = -ENOMEM;
2946                 goto out_free_bus;
2947         }
2948
2949         /* register MDIO bus */
2950         if (dev->of_node) {
2951                 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node);
2952         } else {
2953                 for (i = 0; i < PHY_MAX_ADDR; i++)
2954                         mdp->mii_bus->irq[i] = PHY_POLL;
2955                 if (pd->phy_irq > 0)
2956                         mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
2957
2958                 ret = mdiobus_register(mdp->mii_bus);
2959         }
2960
2961         if (ret)
2962                 goto out_free_bus;
2963
2964         return 0;
2965
2966 out_free_bus:
2967         free_mdio_bitbang(mdp->mii_bus);
2968         return ret;
2969 }
2970
2971 static const u16 *sh_eth_get_register_offset(int register_type)
2972 {
2973         const u16 *reg_offset = NULL;
2974
2975         switch (register_type) {
2976         case SH_ETH_REG_GIGABIT:
2977                 reg_offset = sh_eth_offset_gigabit;
2978                 break;
2979         case SH_ETH_REG_FAST_RZ:
2980                 reg_offset = sh_eth_offset_fast_rz;
2981                 break;
2982         case SH_ETH_REG_FAST_RCAR:
2983                 reg_offset = sh_eth_offset_fast_rcar;
2984                 break;
2985         case SH_ETH_REG_FAST_SH4:
2986                 reg_offset = sh_eth_offset_fast_sh4;
2987                 break;
2988         case SH_ETH_REG_FAST_SH3_SH2:
2989                 reg_offset = sh_eth_offset_fast_sh3_sh2;
2990                 break;
2991         default:
2992                 break;
2993         }
2994
2995         return reg_offset;
2996 }
2997
2998 static const struct net_device_ops sh_eth_netdev_ops = {
2999         .ndo_open               = sh_eth_open,
3000         .ndo_stop               = sh_eth_close,
3001         .ndo_start_xmit         = sh_eth_start_xmit,
3002         .ndo_get_stats          = sh_eth_get_stats,
3003         .ndo_set_rx_mode        = sh_eth_set_rx_mode,
3004         .ndo_tx_timeout         = sh_eth_tx_timeout,
3005         .ndo_do_ioctl           = sh_eth_do_ioctl,
3006         .ndo_validate_addr      = eth_validate_addr,
3007         .ndo_set_mac_address    = eth_mac_addr,
3008         .ndo_change_mtu         = eth_change_mtu,
3009 };
3010
3011 static const struct net_device_ops sh_eth_netdev_ops_tsu = {
3012         .ndo_open               = sh_eth_open,
3013         .ndo_stop               = sh_eth_close,
3014         .ndo_start_xmit         = sh_eth_start_xmit,
3015         .ndo_get_stats          = sh_eth_get_stats,
3016         .ndo_set_rx_mode        = sh_eth_set_rx_mode,
3017         .ndo_vlan_rx_add_vid    = sh_eth_vlan_rx_add_vid,
3018         .ndo_vlan_rx_kill_vid   = sh_eth_vlan_rx_kill_vid,
3019         .ndo_tx_timeout         = sh_eth_tx_timeout,
3020         .ndo_do_ioctl           = sh_eth_do_ioctl,
3021         .ndo_validate_addr      = eth_validate_addr,
3022         .ndo_set_mac_address    = eth_mac_addr,
3023         .ndo_change_mtu         = eth_change_mtu,
3024 };
3025
3026 #ifdef CONFIG_OF
3027 static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3028 {
3029         struct device_node *np = dev->of_node;
3030         struct sh_eth_plat_data *pdata;
3031         const char *mac_addr;
3032
3033         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
3034         if (!pdata)
3035                 return NULL;
3036
3037         pdata->phy_interface = of_get_phy_mode(np);
3038
3039         mac_addr = of_get_mac_address(np);
3040         if (mac_addr)
3041                 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
3042
3043         pdata->no_ether_link =
3044                 of_property_read_bool(np, "renesas,no-ether-link");
3045         pdata->ether_link_active_low =
3046                 of_property_read_bool(np, "renesas,ether-link-active-low");
3047
3048         return pdata;
3049 }
3050
3051 static const struct of_device_id sh_eth_match_table[] = {
3052         { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
3053         { .compatible = "renesas,ether-r8a7778", .data = &r8a777x_data },
3054         { .compatible = "renesas,ether-r8a7779", .data = &r8a777x_data },
3055         { .compatible = "renesas,ether-r8a7790", .data = &r8a779x_data },
3056         { .compatible = "renesas,ether-r8a7791", .data = &r8a779x_data },
3057         { .compatible = "renesas,ether-r8a7793", .data = &r8a779x_data },
3058         { .compatible = "renesas,ether-r8a7794", .data = &r8a779x_data },
3059         { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
3060         { }
3061 };
3062 MODULE_DEVICE_TABLE(of, sh_eth_match_table);
3063 #else
3064 static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3065 {
3066         return NULL;
3067 }
3068 #endif
3069
3070 static int sh_eth_drv_probe(struct platform_device *pdev)
3071 {
3072         int ret, devno = 0;
3073         struct resource *res;
3074         struct net_device *ndev = NULL;
3075         struct sh_eth_private *mdp = NULL;
3076         struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
3077         const struct platform_device_id *id = platform_get_device_id(pdev);
3078
3079         /* get base addr */
3080         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3081
3082         ndev = alloc_etherdev(sizeof(struct sh_eth_private));
3083         if (!ndev)
3084                 return -ENOMEM;
3085
3086         pm_runtime_enable(&pdev->dev);
3087         pm_runtime_get_sync(&pdev->dev);
3088
3089         devno = pdev->id;
3090         if (devno < 0)
3091                 devno = 0;
3092
3093         ndev->dma = -1;
3094         ret = platform_get_irq(pdev, 0);
3095         if (ret < 0)
3096                 goto out_release;
3097         ndev->irq = ret;
3098
3099         SET_NETDEV_DEV(ndev, &pdev->dev);
3100
3101         mdp = netdev_priv(ndev);
3102         mdp->num_tx_ring = TX_RING_SIZE;
3103         mdp->num_rx_ring = RX_RING_SIZE;
3104         mdp->addr = devm_ioremap_resource(&pdev->dev, res);
3105         if (IS_ERR(mdp->addr)) {
3106                 ret = PTR_ERR(mdp->addr);
3107                 goto out_release;
3108         }
3109
3110         ndev->base_addr = res->start;
3111
3112         spin_lock_init(&mdp->lock);
3113         mdp->pdev = pdev;
3114
3115         if (pdev->dev.of_node)
3116                 pd = sh_eth_parse_dt(&pdev->dev);
3117         if (!pd) {
3118                 dev_err(&pdev->dev, "no platform data\n");
3119                 ret = -EINVAL;
3120                 goto out_release;
3121         }
3122
3123         /* get PHY ID */
3124         mdp->phy_id = pd->phy;
3125         mdp->phy_interface = pd->phy_interface;
3126         /* EDMAC endian */
3127         mdp->edmac_endian = pd->edmac_endian;
3128         mdp->no_ether_link = pd->no_ether_link;
3129         mdp->ether_link_active_low = pd->ether_link_active_low;
3130
3131         /* set cpu data */
3132         if (id) {
3133                 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
3134         } else  {
3135                 const struct of_device_id *match;
3136
3137                 match = of_match_device(of_match_ptr(sh_eth_match_table),
3138                                         &pdev->dev);
3139                 mdp->cd = (struct sh_eth_cpu_data *)match->data;
3140         }
3141         mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
3142         if (!mdp->reg_offset) {
3143                 dev_err(&pdev->dev, "Unknown register type (%d)\n",
3144                         mdp->cd->register_type);
3145                 ret = -EINVAL;
3146                 goto out_release;
3147         }
3148         sh_eth_set_default_cpu_data(mdp->cd);
3149
3150         /* set function */
3151         if (mdp->cd->tsu)
3152                 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
3153         else
3154                 ndev->netdev_ops = &sh_eth_netdev_ops;
3155         ndev->ethtool_ops = &sh_eth_ethtool_ops;
3156         ndev->watchdog_timeo = TX_TIMEOUT;
3157
3158         /* debug message level */
3159         mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
3160
3161         /* read and set MAC address */
3162         read_mac_address(ndev, pd->mac_addr);
3163         if (!is_valid_ether_addr(ndev->dev_addr)) {
3164                 dev_warn(&pdev->dev,
3165                          "no valid MAC address supplied, using a random one.\n");
3166                 eth_hw_addr_random(ndev);
3167         }
3168
3169         /* ioremap the TSU registers */
3170         if (mdp->cd->tsu) {
3171                 struct resource *rtsu;
3172                 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3173                 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
3174                 if (IS_ERR(mdp->tsu_addr)) {
3175                         ret = PTR_ERR(mdp->tsu_addr);
3176                         goto out_release;
3177                 }
3178                 mdp->port = devno % 2;
3179                 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
3180         }
3181
3182         /* initialize first or needed device */
3183         if (!devno || pd->needs_init) {
3184                 if (mdp->cd->chip_reset)
3185                         mdp->cd->chip_reset(ndev);
3186
3187                 if (mdp->cd->tsu) {
3188                         /* TSU init (Init only)*/
3189                         sh_eth_tsu_init(mdp);
3190                 }
3191         }
3192
3193         if (mdp->cd->rmiimode)
3194                 sh_eth_write(ndev, 0x1, RMIIMODE);
3195
3196         /* MDIO bus init */
3197         ret = sh_mdio_init(mdp, pd);
3198         if (ret) {
3199                 dev_err(&ndev->dev, "failed to initialise MDIO\n");
3200                 goto out_release;
3201         }
3202
3203         netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
3204
3205         /* network device register */
3206         ret = register_netdev(ndev);
3207         if (ret)
3208                 goto out_napi_del;
3209
3210         /* print device information */
3211         netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
3212                     (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
3213
3214         pm_runtime_put(&pdev->dev);
3215         platform_set_drvdata(pdev, ndev);
3216
3217         return ret;
3218
3219 out_napi_del:
3220         netif_napi_del(&mdp->napi);
3221         sh_mdio_release(mdp);
3222
3223 out_release:
3224         /* net_dev free */
3225         if (ndev)
3226                 free_netdev(ndev);
3227
3228         pm_runtime_put(&pdev->dev);
3229         pm_runtime_disable(&pdev->dev);
3230         return ret;
3231 }
3232
3233 static int sh_eth_drv_remove(struct platform_device *pdev)
3234 {
3235         struct net_device *ndev = platform_get_drvdata(pdev);
3236         struct sh_eth_private *mdp = netdev_priv(ndev);
3237
3238         unregister_netdev(ndev);
3239         netif_napi_del(&mdp->napi);
3240         sh_mdio_release(mdp);
3241         pm_runtime_disable(&pdev->dev);
3242         free_netdev(ndev);
3243
3244         return 0;
3245 }
3246
3247 #ifdef CONFIG_PM
3248 #ifdef CONFIG_PM_SLEEP
3249 static int sh_eth_suspend(struct device *dev)
3250 {
3251         struct net_device *ndev = dev_get_drvdata(dev);
3252         int ret = 0;
3253
3254         if (netif_running(ndev)) {
3255                 netif_device_detach(ndev);
3256                 ret = sh_eth_close(ndev);
3257         }
3258
3259         return ret;
3260 }
3261
3262 static int sh_eth_resume(struct device *dev)
3263 {
3264         struct net_device *ndev = dev_get_drvdata(dev);
3265         int ret = 0;
3266
3267         if (netif_running(ndev)) {
3268                 ret = sh_eth_open(ndev);
3269                 if (ret < 0)
3270                         return ret;
3271                 netif_device_attach(ndev);
3272         }
3273
3274         return ret;
3275 }
3276 #endif
3277
3278 static int sh_eth_runtime_nop(struct device *dev)
3279 {
3280         /* Runtime PM callback shared between ->runtime_suspend()
3281          * and ->runtime_resume(). Simply returns success.
3282          *
3283          * This driver re-initializes all registers after
3284          * pm_runtime_get_sync() anyway so there is no need
3285          * to save and restore registers here.
3286          */
3287         return 0;
3288 }
3289
3290 static const struct dev_pm_ops sh_eth_dev_pm_ops = {
3291         SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume)
3292         SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL)
3293 };
3294 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
3295 #else
3296 #define SH_ETH_PM_OPS NULL
3297 #endif
3298
3299 static struct platform_device_id sh_eth_id_table[] = {
3300         { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
3301         { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
3302         { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
3303         { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
3304         { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
3305         { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
3306         { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
3307         { "r7s72100-ether", (kernel_ulong_t)&r7s72100_data },
3308         { "r8a7740-gether", (kernel_ulong_t)&r8a7740_data },
3309         { "r8a777x-ether", (kernel_ulong_t)&r8a777x_data },
3310         { "r8a7790-ether", (kernel_ulong_t)&r8a779x_data },
3311         { "r8a7791-ether", (kernel_ulong_t)&r8a779x_data },
3312         { "r8a7793-ether", (kernel_ulong_t)&r8a779x_data },
3313         { "r8a7794-ether", (kernel_ulong_t)&r8a779x_data },
3314         { }
3315 };
3316 MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
3317
3318 static struct platform_driver sh_eth_driver = {
3319         .probe = sh_eth_drv_probe,
3320         .remove = sh_eth_drv_remove,
3321         .id_table = sh_eth_id_table,
3322         .driver = {
3323                    .name = CARDNAME,
3324                    .pm = SH_ETH_PM_OPS,
3325                    .of_match_table = of_match_ptr(sh_eth_match_table),
3326         },
3327 };
3328
3329 module_platform_driver(sh_eth_driver);
3330
3331 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3332 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3333 MODULE_LICENSE("GPL v2");