1 /* SuperH Ethernet device driver
3 * Copyright (C) 2014 Renesas Electronics Corporation
4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
5 * Copyright (C) 2008-2014 Renesas Solutions Corp.
6 * Copyright (C) 2013-2016 Cogent Embedded, Inc.
7 * Copyright (C) 2014 Codethink Limited
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License,
11 * version 2, as published by the Free Software Foundation.
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/spinlock.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/etherdevice.h>
28 #include <linux/delay.h>
29 #include <linux/platform_device.h>
30 #include <linux/mdio-bitbang.h>
31 #include <linux/netdevice.h>
33 #include <linux/of_device.h>
34 #include <linux/of_irq.h>
35 #include <linux/of_net.h>
36 #include <linux/phy.h>
37 #include <linux/cache.h>
39 #include <linux/pm_runtime.h>
40 #include <linux/slab.h>
41 #include <linux/ethtool.h>
42 #include <linux/if_vlan.h>
43 #include <linux/clk.h>
44 #include <linux/sh_eth.h>
45 #include <linux/of_mdio.h>
49 #define SH_ETH_DEF_MSG_ENABLE \
55 #define SH_ETH_OFFSET_INVALID ((u16)~0)
57 #define SH_ETH_OFFSET_DEFAULTS \
58 [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID
60 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
61 SH_ETH_OFFSET_DEFAULTS,
116 [TSU_CTRST] = 0x0004,
117 [TSU_FWEN0] = 0x0010,
118 [TSU_FWEN1] = 0x0014,
120 [TSU_BSYSL0] = 0x0020,
121 [TSU_BSYSL1] = 0x0024,
122 [TSU_PRISL0] = 0x0028,
123 [TSU_PRISL1] = 0x002c,
124 [TSU_FWSL0] = 0x0030,
125 [TSU_FWSL1] = 0x0034,
126 [TSU_FWSLC] = 0x0038,
127 [TSU_QTAG0] = 0x0040,
128 [TSU_QTAG1] = 0x0044,
130 [TSU_FWINMK] = 0x0054,
131 [TSU_ADQT0] = 0x0048,
132 [TSU_ADQT1] = 0x004c,
133 [TSU_VTAG0] = 0x0058,
134 [TSU_VTAG1] = 0x005c,
135 [TSU_ADSBSY] = 0x0060,
137 [TSU_POST1] = 0x0070,
138 [TSU_POST2] = 0x0074,
139 [TSU_POST3] = 0x0078,
140 [TSU_POST4] = 0x007c,
141 [TSU_ADRH0] = 0x0100,
157 static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
158 SH_ETH_OFFSET_DEFAULTS,
203 [TSU_CTRST] = 0x0004,
204 [TSU_FWSLC] = 0x0038,
205 [TSU_VTAG0] = 0x0058,
206 [TSU_ADSBSY] = 0x0060,
208 [TSU_POST1] = 0x0070,
209 [TSU_POST2] = 0x0074,
210 [TSU_POST3] = 0x0078,
211 [TSU_POST4] = 0x007c,
212 [TSU_ADRH0] = 0x0100,
220 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
221 SH_ETH_OFFSET_DEFAULTS,
268 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
269 SH_ETH_OFFSET_DEFAULTS,
322 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
323 SH_ETH_OFFSET_DEFAULTS,
371 [TSU_CTRST] = 0x0004,
372 [TSU_FWEN0] = 0x0010,
373 [TSU_FWEN1] = 0x0014,
375 [TSU_BSYSL0] = 0x0020,
376 [TSU_BSYSL1] = 0x0024,
377 [TSU_PRISL0] = 0x0028,
378 [TSU_PRISL1] = 0x002c,
379 [TSU_FWSL0] = 0x0030,
380 [TSU_FWSL1] = 0x0034,
381 [TSU_FWSLC] = 0x0038,
382 [TSU_QTAGM0] = 0x0040,
383 [TSU_QTAGM1] = 0x0044,
384 [TSU_ADQT0] = 0x0048,
385 [TSU_ADQT1] = 0x004c,
387 [TSU_FWINMK] = 0x0054,
388 [TSU_ADSBSY] = 0x0060,
390 [TSU_POST1] = 0x0070,
391 [TSU_POST2] = 0x0074,
392 [TSU_POST3] = 0x0078,
393 [TSU_POST4] = 0x007c,
408 [TSU_ADRH0] = 0x0100,
411 static void sh_eth_rcv_snd_disable(struct net_device *ndev);
412 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev);
414 static void sh_eth_write(struct net_device *ndev, u32 data, int enum_index)
416 struct sh_eth_private *mdp = netdev_priv(ndev);
417 u16 offset = mdp->reg_offset[enum_index];
419 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
422 iowrite32(data, mdp->addr + offset);
425 static u32 sh_eth_read(struct net_device *ndev, int enum_index)
427 struct sh_eth_private *mdp = netdev_priv(ndev);
428 u16 offset = mdp->reg_offset[enum_index];
430 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
433 return ioread32(mdp->addr + offset);
436 static void sh_eth_modify(struct net_device *ndev, int enum_index, u32 clear,
439 sh_eth_write(ndev, (sh_eth_read(ndev, enum_index) & ~clear) | set,
443 static bool sh_eth_is_gether(struct sh_eth_private *mdp)
445 return mdp->reg_offset == sh_eth_offset_gigabit;
448 static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp)
450 return mdp->reg_offset == sh_eth_offset_fast_rz;
453 static void sh_eth_select_mii(struct net_device *ndev)
455 struct sh_eth_private *mdp = netdev_priv(ndev);
458 switch (mdp->phy_interface) {
459 case PHY_INTERFACE_MODE_GMII:
462 case PHY_INTERFACE_MODE_MII:
465 case PHY_INTERFACE_MODE_RMII:
470 "PHY interface mode was not setup. Set to MII.\n");
475 sh_eth_write(ndev, value, RMII_MII);
478 static void sh_eth_set_duplex(struct net_device *ndev)
480 struct sh_eth_private *mdp = netdev_priv(ndev);
482 sh_eth_modify(ndev, ECMR, ECMR_DM, mdp->duplex ? ECMR_DM : 0);
485 static void sh_eth_chip_reset(struct net_device *ndev)
487 struct sh_eth_private *mdp = netdev_priv(ndev);
490 sh_eth_tsu_write(mdp, ARSTR_ARST, ARSTR);
494 static void sh_eth_set_rate_gether(struct net_device *ndev)
496 struct sh_eth_private *mdp = netdev_priv(ndev);
498 switch (mdp->speed) {
499 case 10: /* 10BASE */
500 sh_eth_write(ndev, GECMR_10, GECMR);
502 case 100:/* 100BASE */
503 sh_eth_write(ndev, GECMR_100, GECMR);
505 case 1000: /* 1000BASE */
506 sh_eth_write(ndev, GECMR_1000, GECMR);
513 static struct sh_eth_cpu_data r7s72100_data = {
514 .chip_reset = sh_eth_chip_reset,
515 .set_duplex = sh_eth_set_duplex,
517 .register_type = SH_ETH_REG_FAST_RZ,
519 .ecsr_value = ECSR_ICD,
520 .ecsipr_value = ECSIPR_ICDIP,
521 .eesipr_value = 0xff7f009f,
523 .tx_check = EESR_TC1 | EESR_FTC,
524 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
525 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
527 .fdr_value = 0x0000070f,
535 .rpadir_value = 2 << 16,
543 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
545 sh_eth_chip_reset(ndev);
547 sh_eth_select_mii(ndev);
551 static struct sh_eth_cpu_data r8a7740_data = {
552 .chip_reset = sh_eth_chip_reset_r8a7740,
553 .set_duplex = sh_eth_set_duplex,
554 .set_rate = sh_eth_set_rate_gether,
556 .register_type = SH_ETH_REG_GIGABIT,
558 .ecsr_value = ECSR_ICD | ECSR_MPD,
559 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
560 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
562 .tx_check = EESR_TC1 | EESR_FTC,
563 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
564 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
566 .fdr_value = 0x0000070f,
574 .rpadir_value = 2 << 16,
582 /* There is CPU dependent code */
583 static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
585 struct sh_eth_private *mdp = netdev_priv(ndev);
587 switch (mdp->speed) {
588 case 10: /* 10BASE */
589 sh_eth_modify(ndev, ECMR, ECMR_ELB, 0);
591 case 100:/* 100BASE */
592 sh_eth_modify(ndev, ECMR, ECMR_ELB, ECMR_ELB);
598 static struct sh_eth_cpu_data r8a777x_data = {
599 .set_duplex = sh_eth_set_duplex,
600 .set_rate = sh_eth_set_rate_r8a777x,
602 .register_type = SH_ETH_REG_FAST_RCAR,
604 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
605 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
606 .eesipr_value = 0x01ff009f,
608 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
609 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
610 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
612 .fdr_value = 0x00000f0f,
621 static struct sh_eth_cpu_data r8a779x_data = {
622 .set_duplex = sh_eth_set_duplex,
623 .set_rate = sh_eth_set_rate_r8a777x,
625 .register_type = SH_ETH_REG_FAST_RCAR,
627 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
628 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
629 .eesipr_value = 0x01ff009f,
631 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
632 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
633 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
635 .fdr_value = 0x00000f0f,
637 .trscer_err_mask = DESC_I_RINT8,
645 #endif /* CONFIG_OF */
647 static void sh_eth_set_rate_sh7724(struct net_device *ndev)
649 struct sh_eth_private *mdp = netdev_priv(ndev);
651 switch (mdp->speed) {
652 case 10: /* 10BASE */
653 sh_eth_modify(ndev, ECMR, ECMR_RTM, 0);
655 case 100:/* 100BASE */
656 sh_eth_modify(ndev, ECMR, ECMR_RTM, ECMR_RTM);
662 static struct sh_eth_cpu_data sh7724_data = {
663 .set_duplex = sh_eth_set_duplex,
664 .set_rate = sh_eth_set_rate_sh7724,
666 .register_type = SH_ETH_REG_FAST_SH4,
668 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
669 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
670 .eesipr_value = 0x01ff009f,
672 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
673 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
674 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
682 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
685 static void sh_eth_set_rate_sh7757(struct net_device *ndev)
687 struct sh_eth_private *mdp = netdev_priv(ndev);
689 switch (mdp->speed) {
690 case 10: /* 10BASE */
691 sh_eth_write(ndev, 0, RTRATE);
693 case 100:/* 100BASE */
694 sh_eth_write(ndev, 1, RTRATE);
700 static struct sh_eth_cpu_data sh7757_data = {
701 .set_duplex = sh_eth_set_duplex,
702 .set_rate = sh_eth_set_rate_sh7757,
704 .register_type = SH_ETH_REG_FAST_SH4,
706 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
708 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
709 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
710 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
713 .irq_flags = IRQF_SHARED,
720 .rpadir_value = 2 << 16,
724 #define SH_GIGA_ETH_BASE 0xfee00000UL
725 #define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
726 #define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
727 static void sh_eth_chip_reset_giga(struct net_device *ndev)
729 u32 mahr[2], malr[2];
732 /* save MAHR and MALR */
733 for (i = 0; i < 2; i++) {
734 malr[i] = ioread32((void *)GIGA_MALR(i));
735 mahr[i] = ioread32((void *)GIGA_MAHR(i));
738 sh_eth_chip_reset(ndev);
740 /* restore MAHR and MALR */
741 for (i = 0; i < 2; i++) {
742 iowrite32(malr[i], (void *)GIGA_MALR(i));
743 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
747 static void sh_eth_set_rate_giga(struct net_device *ndev)
749 struct sh_eth_private *mdp = netdev_priv(ndev);
751 switch (mdp->speed) {
752 case 10: /* 10BASE */
753 sh_eth_write(ndev, 0x00000000, GECMR);
755 case 100:/* 100BASE */
756 sh_eth_write(ndev, 0x00000010, GECMR);
758 case 1000: /* 1000BASE */
759 sh_eth_write(ndev, 0x00000020, GECMR);
764 /* SH7757(GETHERC) */
765 static struct sh_eth_cpu_data sh7757_data_giga = {
766 .chip_reset = sh_eth_chip_reset_giga,
767 .set_duplex = sh_eth_set_duplex,
768 .set_rate = sh_eth_set_rate_giga,
770 .register_type = SH_ETH_REG_GIGABIT,
772 .ecsr_value = ECSR_ICD | ECSR_MPD,
773 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
774 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
776 .tx_check = EESR_TC1 | EESR_FTC,
777 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
778 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
780 .fdr_value = 0x0000072f,
782 .irq_flags = IRQF_SHARED,
789 .rpadir_value = 2 << 16,
796 static struct sh_eth_cpu_data sh7734_data = {
797 .chip_reset = sh_eth_chip_reset,
798 .set_duplex = sh_eth_set_duplex,
799 .set_rate = sh_eth_set_rate_gether,
801 .register_type = SH_ETH_REG_GIGABIT,
803 .ecsr_value = ECSR_ICD | ECSR_MPD,
804 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
805 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
807 .tx_check = EESR_TC1 | EESR_FTC,
808 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
809 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
825 static struct sh_eth_cpu_data sh7763_data = {
826 .chip_reset = sh_eth_chip_reset,
827 .set_duplex = sh_eth_set_duplex,
828 .set_rate = sh_eth_set_rate_gether,
830 .register_type = SH_ETH_REG_GIGABIT,
832 .ecsr_value = ECSR_ICD | ECSR_MPD,
833 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
834 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
836 .tx_check = EESR_TC1 | EESR_FTC,
837 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
838 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
849 .irq_flags = IRQF_SHARED,
852 static struct sh_eth_cpu_data sh7619_data = {
853 .register_type = SH_ETH_REG_FAST_SH3_SH2,
855 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
863 static struct sh_eth_cpu_data sh771x_data = {
864 .register_type = SH_ETH_REG_FAST_SH3_SH2,
866 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
870 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
873 cd->ecsr_value = DEFAULT_ECSR_INIT;
875 if (!cd->ecsipr_value)
876 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
878 if (!cd->fcftr_value)
879 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
880 DEFAULT_FIFO_F_D_RFD;
883 cd->fdr_value = DEFAULT_FDR_INIT;
886 cd->tx_check = DEFAULT_TX_CHECK;
888 if (!cd->eesr_err_check)
889 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
891 if (!cd->trscer_err_mask)
892 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK;
895 static int sh_eth_check_reset(struct net_device *ndev)
901 if (!(sh_eth_read(ndev, EDMR) & EDMR_SRST_GETHER))
907 netdev_err(ndev, "Device reset failed\n");
913 static int sh_eth_reset(struct net_device *ndev)
915 struct sh_eth_private *mdp = netdev_priv(ndev);
918 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) {
919 sh_eth_write(ndev, EDSR_ENALL, EDSR);
920 sh_eth_modify(ndev, EDMR, EDMR_SRST_GETHER, EDMR_SRST_GETHER);
922 ret = sh_eth_check_reset(ndev);
927 sh_eth_write(ndev, 0x0, TDLAR);
928 sh_eth_write(ndev, 0x0, TDFAR);
929 sh_eth_write(ndev, 0x0, TDFXR);
930 sh_eth_write(ndev, 0x0, TDFFR);
931 sh_eth_write(ndev, 0x0, RDLAR);
932 sh_eth_write(ndev, 0x0, RDFAR);
933 sh_eth_write(ndev, 0x0, RDFXR);
934 sh_eth_write(ndev, 0x0, RDFFR);
936 /* Reset HW CRC register */
938 sh_eth_write(ndev, 0x0, CSMR);
940 /* Select MII mode */
941 if (mdp->cd->select_mii)
942 sh_eth_select_mii(ndev);
944 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, EDMR_SRST_ETHER);
946 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, 0);
952 static void sh_eth_set_receive_align(struct sk_buff *skb)
954 uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1);
957 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve);
960 /* Program the hardware MAC address from dev->dev_addr. */
961 static void update_mac_address(struct net_device *ndev)
964 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
965 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
967 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
970 /* Get MAC address from SuperH MAC address register
972 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
973 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
974 * When you want use this device, you must set MAC address in bootloader.
977 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
979 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
980 memcpy(ndev->dev_addr, mac, ETH_ALEN);
982 u32 mahr = sh_eth_read(ndev, MAHR);
983 u32 malr = sh_eth_read(ndev, MALR);
985 ndev->dev_addr[0] = (mahr >> 24) & 0xFF;
986 ndev->dev_addr[1] = (mahr >> 16) & 0xFF;
987 ndev->dev_addr[2] = (mahr >> 8) & 0xFF;
988 ndev->dev_addr[3] = (mahr >> 0) & 0xFF;
989 ndev->dev_addr[4] = (malr >> 8) & 0xFF;
990 ndev->dev_addr[5] = (malr >> 0) & 0xFF;
994 static u32 sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
996 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp))
997 return EDTRR_TRNS_GETHER;
999 return EDTRR_TRNS_ETHER;
1003 void (*set_gate)(void *addr);
1004 struct mdiobb_ctrl ctrl;
1008 static void sh_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
1010 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1013 if (bitbang->set_gate)
1014 bitbang->set_gate(bitbang->addr);
1016 pir = ioread32(bitbang->addr);
1021 iowrite32(pir, bitbang->addr);
1024 /* Data I/O pin control */
1025 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1027 sh_mdio_ctrl(ctrl, PIR_MMD, bit);
1031 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1033 sh_mdio_ctrl(ctrl, PIR_MDO, bit);
1037 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1039 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1041 if (bitbang->set_gate)
1042 bitbang->set_gate(bitbang->addr);
1044 return (ioread32(bitbang->addr) & PIR_MDI) != 0;
1047 /* MDC pin control */
1048 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1050 sh_mdio_ctrl(ctrl, PIR_MDC, bit);
1053 /* mdio bus control struct */
1054 static struct mdiobb_ops bb_ops = {
1055 .owner = THIS_MODULE,
1056 .set_mdc = sh_mdc_ctrl,
1057 .set_mdio_dir = sh_mmd_ctrl,
1058 .set_mdio_data = sh_set_mdio,
1059 .get_mdio_data = sh_get_mdio,
1062 /* free skb and descriptor buffer */
1063 static void sh_eth_ring_free(struct net_device *ndev)
1065 struct sh_eth_private *mdp = netdev_priv(ndev);
1068 /* Free Rx skb ringbuffer */
1069 if (mdp->rx_skbuff) {
1070 for (i = 0; i < mdp->num_rx_ring; i++)
1071 dev_kfree_skb(mdp->rx_skbuff[i]);
1073 kfree(mdp->rx_skbuff);
1074 mdp->rx_skbuff = NULL;
1076 /* Free Tx skb ringbuffer */
1077 if (mdp->tx_skbuff) {
1078 for (i = 0; i < mdp->num_tx_ring; i++)
1079 dev_kfree_skb(mdp->tx_skbuff[i]);
1081 kfree(mdp->tx_skbuff);
1082 mdp->tx_skbuff = NULL;
1085 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1086 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1088 mdp->rx_ring = NULL;
1092 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1093 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1095 mdp->tx_ring = NULL;
1099 /* format skb and descriptor buffer */
1100 static void sh_eth_ring_format(struct net_device *ndev)
1102 struct sh_eth_private *mdp = netdev_priv(ndev);
1104 struct sk_buff *skb;
1105 struct sh_eth_rxdesc *rxdesc = NULL;
1106 struct sh_eth_txdesc *txdesc = NULL;
1107 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1108 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
1109 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1110 dma_addr_t dma_addr;
1118 memset(mdp->rx_ring, 0, rx_ringsize);
1120 /* build Rx ring buffer */
1121 for (i = 0; i < mdp->num_rx_ring; i++) {
1123 mdp->rx_skbuff[i] = NULL;
1124 skb = netdev_alloc_skb(ndev, skbuff_size);
1127 sh_eth_set_receive_align(skb);
1129 /* The size of the buffer is a multiple of 32 bytes. */
1130 buf_len = ALIGN(mdp->rx_buf_sz, 32);
1131 dma_addr = dma_map_single(&ndev->dev, skb->data, buf_len,
1133 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1137 mdp->rx_skbuff[i] = skb;
1140 rxdesc = &mdp->rx_ring[i];
1141 rxdesc->len = cpu_to_le32(buf_len << 16);
1142 rxdesc->addr = cpu_to_le32(dma_addr);
1143 rxdesc->status = cpu_to_le32(RD_RACT | RD_RFP);
1145 /* Rx descriptor address set */
1147 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
1148 if (sh_eth_is_gether(mdp) ||
1149 sh_eth_is_rz_fast_ether(mdp))
1150 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
1154 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
1156 /* Mark the last entry as wrapping the ring. */
1158 rxdesc->status |= cpu_to_le32(RD_RDLE);
1160 memset(mdp->tx_ring, 0, tx_ringsize);
1162 /* build Tx ring buffer */
1163 for (i = 0; i < mdp->num_tx_ring; i++) {
1164 mdp->tx_skbuff[i] = NULL;
1165 txdesc = &mdp->tx_ring[i];
1166 txdesc->status = cpu_to_le32(TD_TFP);
1167 txdesc->len = cpu_to_le32(0);
1169 /* Tx descriptor address set */
1170 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
1171 if (sh_eth_is_gether(mdp) ||
1172 sh_eth_is_rz_fast_ether(mdp))
1173 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
1177 txdesc->status |= cpu_to_le32(TD_TDLE);
1180 /* Get skb and descriptor buffer */
1181 static int sh_eth_ring_init(struct net_device *ndev)
1183 struct sh_eth_private *mdp = netdev_priv(ndev);
1184 int rx_ringsize, tx_ringsize;
1186 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1187 * card needs room to do 8 byte alignment, +2 so we can reserve
1188 * the first 2 bytes, and +16 gets room for the status word from the
1191 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1192 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
1193 if (mdp->cd->rpadir)
1194 mdp->rx_buf_sz += NET_IP_ALIGN;
1196 /* Allocate RX and TX skb rings */
1197 mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff),
1199 if (!mdp->rx_skbuff)
1202 mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff),
1204 if (!mdp->tx_skbuff)
1207 /* Allocate all Rx descriptors. */
1208 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1209 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
1216 /* Allocate all Tx descriptors. */
1217 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1218 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
1225 /* Free Rx and Tx skb ring buffer and DMA buffer */
1226 sh_eth_ring_free(ndev);
1231 static int sh_eth_dev_init(struct net_device *ndev)
1233 struct sh_eth_private *mdp = netdev_priv(ndev);
1237 ret = sh_eth_reset(ndev);
1241 if (mdp->cd->rmiimode)
1242 sh_eth_write(ndev, 0x1, RMIIMODE);
1244 /* Descriptor format */
1245 sh_eth_ring_format(ndev);
1246 if (mdp->cd->rpadir)
1247 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
1249 /* all sh_eth int mask */
1250 sh_eth_write(ndev, 0, EESIPR);
1252 #if defined(__LITTLE_ENDIAN)
1253 if (mdp->cd->hw_swap)
1254 sh_eth_write(ndev, EDMR_EL, EDMR);
1257 sh_eth_write(ndev, 0, EDMR);
1260 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1261 sh_eth_write(ndev, 0, TFTR);
1263 /* Frame recv control (enable multiple-packets per rx irq) */
1264 sh_eth_write(ndev, RMCR_RNC, RMCR);
1266 sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);
1269 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */
1271 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
1273 if (!mdp->cd->no_trimd)
1274 sh_eth_write(ndev, 0, TRIMD);
1276 /* Recv frame limit set register */
1277 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1280 sh_eth_modify(ndev, EESR, 0, 0);
1281 mdp->irq_enabled = true;
1282 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1284 /* PAUSE Prohibition */
1285 sh_eth_write(ndev, ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) |
1286 ECMR_TE | ECMR_RE, ECMR);
1288 if (mdp->cd->set_rate)
1289 mdp->cd->set_rate(ndev);
1291 /* E-MAC Status Register clear */
1292 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1294 /* E-MAC Interrupt Enable register */
1295 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1297 /* Set MAC address */
1298 update_mac_address(ndev);
1302 sh_eth_write(ndev, APR_AP, APR);
1304 sh_eth_write(ndev, MPR_MP, MPR);
1305 if (mdp->cd->tpauser)
1306 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1308 /* Setting the Rx mode will start the Rx process. */
1309 sh_eth_write(ndev, EDRRR_R, EDRRR);
1314 static void sh_eth_dev_exit(struct net_device *ndev)
1316 struct sh_eth_private *mdp = netdev_priv(ndev);
1319 /* Deactivate all TX descriptors, so DMA should stop at next
1320 * packet boundary if it's currently running
1322 for (i = 0; i < mdp->num_tx_ring; i++)
1323 mdp->tx_ring[i].status &= ~cpu_to_le32(TD_TACT);
1325 /* Disable TX FIFO egress to MAC */
1326 sh_eth_rcv_snd_disable(ndev);
1328 /* Stop RX DMA at next packet boundary */
1329 sh_eth_write(ndev, 0, EDRRR);
1331 /* Aside from TX DMA, we can't tell when the hardware is
1332 * really stopped, so we need to reset to make sure.
1333 * Before doing that, wait for long enough to *probably*
1334 * finish transmitting the last packet and poll stats.
1336 msleep(2); /* max frame time at 10 Mbps < 1250 us */
1337 sh_eth_get_stats(ndev);
1340 /* Set MAC address again */
1341 update_mac_address(ndev);
1344 /* free Tx skb function */
1345 static int sh_eth_txfree(struct net_device *ndev)
1347 struct sh_eth_private *mdp = netdev_priv(ndev);
1348 struct sh_eth_txdesc *txdesc;
1352 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1353 entry = mdp->dirty_tx % mdp->num_tx_ring;
1354 txdesc = &mdp->tx_ring[entry];
1355 if (txdesc->status & cpu_to_le32(TD_TACT))
1357 /* TACT bit must be checked before all the following reads */
1359 netif_info(mdp, tx_done, ndev,
1360 "tx entry %d status 0x%08x\n",
1361 entry, le32_to_cpu(txdesc->status));
1362 /* Free the original skb. */
1363 if (mdp->tx_skbuff[entry]) {
1364 dma_unmap_single(&ndev->dev, le32_to_cpu(txdesc->addr),
1365 le32_to_cpu(txdesc->len) >> 16,
1367 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1368 mdp->tx_skbuff[entry] = NULL;
1371 txdesc->status = cpu_to_le32(TD_TFP);
1372 if (entry >= mdp->num_tx_ring - 1)
1373 txdesc->status |= cpu_to_le32(TD_TDLE);
1375 ndev->stats.tx_packets++;
1376 ndev->stats.tx_bytes += le32_to_cpu(txdesc->len) >> 16;
1381 /* Packet receive function */
1382 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
1384 struct sh_eth_private *mdp = netdev_priv(ndev);
1385 struct sh_eth_rxdesc *rxdesc;
1387 int entry = mdp->cur_rx % mdp->num_rx_ring;
1388 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
1390 struct sk_buff *skb;
1392 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1393 dma_addr_t dma_addr;
1397 boguscnt = min(boguscnt, *quota);
1399 rxdesc = &mdp->rx_ring[entry];
1400 while (!(rxdesc->status & cpu_to_le32(RD_RACT))) {
1401 /* RACT bit must be checked before all the following reads */
1403 desc_status = le32_to_cpu(rxdesc->status);
1404 pkt_len = le32_to_cpu(rxdesc->len) & RD_RFL;
1409 netif_info(mdp, rx_status, ndev,
1410 "rx entry %d status 0x%08x len %d\n",
1411 entry, desc_status, pkt_len);
1413 if (!(desc_status & RDFEND))
1414 ndev->stats.rx_length_errors++;
1416 /* In case of almost all GETHER/ETHERs, the Receive Frame State
1417 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1418 * bit 0. However, in case of the R8A7740 and R7S72100
1419 * the RFS bits are from bit 25 to bit 16. So, the
1420 * driver needs right shifting by 16.
1422 if (mdp->cd->shift_rd0)
1425 skb = mdp->rx_skbuff[entry];
1426 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1427 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1428 ndev->stats.rx_errors++;
1429 if (desc_status & RD_RFS1)
1430 ndev->stats.rx_crc_errors++;
1431 if (desc_status & RD_RFS2)
1432 ndev->stats.rx_frame_errors++;
1433 if (desc_status & RD_RFS3)
1434 ndev->stats.rx_length_errors++;
1435 if (desc_status & RD_RFS4)
1436 ndev->stats.rx_length_errors++;
1437 if (desc_status & RD_RFS6)
1438 ndev->stats.rx_missed_errors++;
1439 if (desc_status & RD_RFS10)
1440 ndev->stats.rx_over_errors++;
1442 dma_addr = le32_to_cpu(rxdesc->addr);
1443 if (!mdp->cd->hw_swap)
1445 phys_to_virt(ALIGN(dma_addr, 4)),
1447 mdp->rx_skbuff[entry] = NULL;
1448 if (mdp->cd->rpadir)
1449 skb_reserve(skb, NET_IP_ALIGN);
1450 dma_unmap_single(&ndev->dev, dma_addr,
1451 ALIGN(mdp->rx_buf_sz, 32),
1453 skb_put(skb, pkt_len);
1454 skb->protocol = eth_type_trans(skb, ndev);
1455 netif_receive_skb(skb);
1456 ndev->stats.rx_packets++;
1457 ndev->stats.rx_bytes += pkt_len;
1458 if (desc_status & RD_RFS8)
1459 ndev->stats.multicast++;
1461 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
1462 rxdesc = &mdp->rx_ring[entry];
1465 /* Refill the Rx ring buffers. */
1466 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1467 entry = mdp->dirty_rx % mdp->num_rx_ring;
1468 rxdesc = &mdp->rx_ring[entry];
1469 /* The size of the buffer is 32 byte boundary. */
1470 buf_len = ALIGN(mdp->rx_buf_sz, 32);
1471 rxdesc->len = cpu_to_le32(buf_len << 16);
1473 if (mdp->rx_skbuff[entry] == NULL) {
1474 skb = netdev_alloc_skb(ndev, skbuff_size);
1476 break; /* Better luck next round. */
1477 sh_eth_set_receive_align(skb);
1478 dma_addr = dma_map_single(&ndev->dev, skb->data,
1479 buf_len, DMA_FROM_DEVICE);
1480 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1484 mdp->rx_skbuff[entry] = skb;
1486 skb_checksum_none_assert(skb);
1487 rxdesc->addr = cpu_to_le32(dma_addr);
1489 dma_wmb(); /* RACT bit must be set after all the above writes */
1490 if (entry >= mdp->num_rx_ring - 1)
1492 cpu_to_le32(RD_RACT | RD_RFP | RD_RDLE);
1494 rxdesc->status |= cpu_to_le32(RD_RACT | RD_RFP);
1497 /* Restart Rx engine if stopped. */
1498 /* If we don't need to check status, don't. -KDU */
1499 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1500 /* fix the values for the next receiving if RDE is set */
1501 if (intr_status & EESR_RDE &&
1502 mdp->reg_offset[RDFAR] != SH_ETH_OFFSET_INVALID) {
1503 u32 count = (sh_eth_read(ndev, RDFAR) -
1504 sh_eth_read(ndev, RDLAR)) >> 4;
1506 mdp->cur_rx = count;
1507 mdp->dirty_rx = count;
1509 sh_eth_write(ndev, EDRRR_R, EDRRR);
1512 *quota -= limit - boguscnt - 1;
1517 static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1519 /* disable tx and rx */
1520 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0);
1523 static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1525 /* enable tx and rx */
1526 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE);
1529 /* error control function */
1530 static void sh_eth_error(struct net_device *ndev, u32 intr_status)
1532 struct sh_eth_private *mdp = netdev_priv(ndev);
1537 if (intr_status & EESR_ECI) {
1538 felic_stat = sh_eth_read(ndev, ECSR);
1539 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
1540 if (felic_stat & ECSR_ICD)
1541 ndev->stats.tx_carrier_errors++;
1542 if (felic_stat & ECSR_LCHNG) {
1544 if (mdp->cd->no_psr || mdp->no_ether_link) {
1547 link_stat = (sh_eth_read(ndev, PSR));
1548 if (mdp->ether_link_active_low)
1549 link_stat = ~link_stat;
1551 if (!(link_stat & PHY_ST_LINK)) {
1552 sh_eth_rcv_snd_disable(ndev);
1555 sh_eth_modify(ndev, EESIPR, DMAC_M_ECI, 0);
1557 sh_eth_modify(ndev, ECSR, 0, 0);
1558 sh_eth_modify(ndev, EESIPR, DMAC_M_ECI,
1560 /* enable tx and rx */
1561 sh_eth_rcv_snd_enable(ndev);
1567 if (intr_status & EESR_TWB) {
1568 /* Unused write back interrupt */
1569 if (intr_status & EESR_TABT) { /* Transmit Abort int */
1570 ndev->stats.tx_aborted_errors++;
1571 netif_err(mdp, tx_err, ndev, "Transmit Abort\n");
1575 if (intr_status & EESR_RABT) {
1576 /* Receive Abort int */
1577 if (intr_status & EESR_RFRMER) {
1578 /* Receive Frame Overflow int */
1579 ndev->stats.rx_frame_errors++;
1583 if (intr_status & EESR_TDE) {
1584 /* Transmit Descriptor Empty int */
1585 ndev->stats.tx_fifo_errors++;
1586 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n");
1589 if (intr_status & EESR_TFE) {
1590 /* FIFO under flow */
1591 ndev->stats.tx_fifo_errors++;
1592 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n");
1595 if (intr_status & EESR_RDE) {
1596 /* Receive Descriptor Empty int */
1597 ndev->stats.rx_over_errors++;
1600 if (intr_status & EESR_RFE) {
1601 /* Receive FIFO Overflow int */
1602 ndev->stats.rx_fifo_errors++;
1605 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1607 ndev->stats.tx_fifo_errors++;
1608 netif_err(mdp, tx_err, ndev, "Address Error\n");
1611 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1612 if (mdp->cd->no_ade)
1614 if (intr_status & mask) {
1616 u32 edtrr = sh_eth_read(ndev, EDTRR);
1619 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1620 intr_status, mdp->cur_tx, mdp->dirty_tx,
1621 (u32)ndev->state, edtrr);
1622 /* dirty buffer free */
1623 sh_eth_txfree(ndev);
1626 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
1628 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1631 netif_wake_queue(ndev);
1635 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1637 struct net_device *ndev = netdev;
1638 struct sh_eth_private *mdp = netdev_priv(ndev);
1639 struct sh_eth_cpu_data *cd = mdp->cd;
1640 irqreturn_t ret = IRQ_NONE;
1641 u32 intr_status, intr_enable;
1643 spin_lock(&mdp->lock);
1645 /* Get interrupt status */
1646 intr_status = sh_eth_read(ndev, EESR);
1647 /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1648 * enabled since it's the one that comes thru regardless of the mask,
1649 * and we need to fully handle it in sh_eth_error() in order to quench
1650 * it as it doesn't get cleared by just writing 1 to the ECI bit...
1652 intr_enable = sh_eth_read(ndev, EESIPR);
1653 intr_status &= intr_enable | DMAC_M_ECI;
1654 if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check))
1659 if (!likely(mdp->irq_enabled)) {
1660 sh_eth_write(ndev, 0, EESIPR);
1664 if (intr_status & EESR_RX_CHECK) {
1665 if (napi_schedule_prep(&mdp->napi)) {
1666 /* Mask Rx interrupts */
1667 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1669 __napi_schedule(&mdp->napi);
1672 "ignoring interrupt, status 0x%08x, mask 0x%08x.\n",
1673 intr_status, intr_enable);
1678 if (intr_status & cd->tx_check) {
1679 /* Clear Tx interrupts */
1680 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1682 sh_eth_txfree(ndev);
1683 netif_wake_queue(ndev);
1686 if (intr_status & cd->eesr_err_check) {
1687 /* Clear error interrupts */
1688 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1690 sh_eth_error(ndev, intr_status);
1694 spin_unlock(&mdp->lock);
1699 static int sh_eth_poll(struct napi_struct *napi, int budget)
1701 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1703 struct net_device *ndev = napi->dev;
1708 intr_status = sh_eth_read(ndev, EESR);
1709 if (!(intr_status & EESR_RX_CHECK))
1711 /* Clear Rx interrupts */
1712 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1714 if (sh_eth_rx(ndev, intr_status, "a))
1718 napi_complete(napi);
1720 /* Reenable Rx interrupts */
1721 if (mdp->irq_enabled)
1722 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1724 return budget - quota;
1727 /* PHY state control function */
1728 static void sh_eth_adjust_link(struct net_device *ndev)
1730 struct sh_eth_private *mdp = netdev_priv(ndev);
1731 struct phy_device *phydev = mdp->phydev;
1735 if (phydev->duplex != mdp->duplex) {
1737 mdp->duplex = phydev->duplex;
1738 if (mdp->cd->set_duplex)
1739 mdp->cd->set_duplex(ndev);
1742 if (phydev->speed != mdp->speed) {
1744 mdp->speed = phydev->speed;
1745 if (mdp->cd->set_rate)
1746 mdp->cd->set_rate(ndev);
1749 sh_eth_modify(ndev, ECMR, ECMR_TXF, 0);
1751 mdp->link = phydev->link;
1752 if (mdp->cd->no_psr || mdp->no_ether_link)
1753 sh_eth_rcv_snd_enable(ndev);
1755 } else if (mdp->link) {
1760 if (mdp->cd->no_psr || mdp->no_ether_link)
1761 sh_eth_rcv_snd_disable(ndev);
1764 if (new_state && netif_msg_link(mdp))
1765 phy_print_status(phydev);
1768 /* PHY init function */
1769 static int sh_eth_phy_init(struct net_device *ndev)
1771 struct device_node *np = ndev->dev.parent->of_node;
1772 struct sh_eth_private *mdp = netdev_priv(ndev);
1773 struct phy_device *phydev;
1779 /* Try connect to PHY */
1781 struct device_node *pn;
1783 pn = of_parse_phandle(np, "phy-handle", 0);
1784 phydev = of_phy_connect(ndev, pn,
1785 sh_eth_adjust_link, 0,
1786 mdp->phy_interface);
1790 phydev = ERR_PTR(-ENOENT);
1792 char phy_id[MII_BUS_ID_SIZE + 3];
1794 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1795 mdp->mii_bus->id, mdp->phy_id);
1797 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1798 mdp->phy_interface);
1801 if (IS_ERR(phydev)) {
1802 netdev_err(ndev, "failed to connect PHY\n");
1803 return PTR_ERR(phydev);
1806 phy_attached_info(phydev);
1808 mdp->phydev = phydev;
1813 /* PHY control start function */
1814 static int sh_eth_phy_start(struct net_device *ndev)
1816 struct sh_eth_private *mdp = netdev_priv(ndev);
1819 ret = sh_eth_phy_init(ndev);
1823 phy_start(mdp->phydev);
1828 static int sh_eth_get_settings(struct net_device *ndev,
1829 struct ethtool_cmd *ecmd)
1831 struct sh_eth_private *mdp = netdev_priv(ndev);
1832 unsigned long flags;
1838 spin_lock_irqsave(&mdp->lock, flags);
1839 ret = phy_ethtool_gset(mdp->phydev, ecmd);
1840 spin_unlock_irqrestore(&mdp->lock, flags);
1845 static int sh_eth_set_settings(struct net_device *ndev,
1846 struct ethtool_cmd *ecmd)
1848 struct sh_eth_private *mdp = netdev_priv(ndev);
1849 unsigned long flags;
1855 spin_lock_irqsave(&mdp->lock, flags);
1857 /* disable tx and rx */
1858 sh_eth_rcv_snd_disable(ndev);
1860 ret = phy_ethtool_sset(mdp->phydev, ecmd);
1864 if (ecmd->duplex == DUPLEX_FULL)
1869 if (mdp->cd->set_duplex)
1870 mdp->cd->set_duplex(ndev);
1875 /* enable tx and rx */
1876 sh_eth_rcv_snd_enable(ndev);
1878 spin_unlock_irqrestore(&mdp->lock, flags);
1883 /* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the
1884 * version must be bumped as well. Just adding registers up to that
1885 * limit is fine, as long as the existing register indices don't
1888 #define SH_ETH_REG_DUMP_VERSION 1
1889 #define SH_ETH_REG_DUMP_MAX_REGS 256
1891 static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf)
1893 struct sh_eth_private *mdp = netdev_priv(ndev);
1894 struct sh_eth_cpu_data *cd = mdp->cd;
1898 BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS);
1900 /* Dump starts with a bitmap that tells ethtool which
1901 * registers are defined for this chip.
1903 len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32);
1911 /* Add a register to the dump, if it has a defined offset.
1912 * This automatically skips most undefined registers, but for
1913 * some it is also necessary to check a capability flag in
1914 * struct sh_eth_cpu_data.
1916 #define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32)
1917 #define add_reg_from(reg, read_expr) do { \
1918 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) { \
1920 mark_reg_valid(reg); \
1921 *buf++ = read_expr; \
1926 #define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg))
1927 #define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg))
1999 add_tsu_reg(TSU_CTRST);
2000 add_tsu_reg(TSU_FWEN0);
2001 add_tsu_reg(TSU_FWEN1);
2002 add_tsu_reg(TSU_FCM);
2003 add_tsu_reg(TSU_BSYSL0);
2004 add_tsu_reg(TSU_BSYSL1);
2005 add_tsu_reg(TSU_PRISL0);
2006 add_tsu_reg(TSU_PRISL1);
2007 add_tsu_reg(TSU_FWSL0);
2008 add_tsu_reg(TSU_FWSL1);
2009 add_tsu_reg(TSU_FWSLC);
2010 add_tsu_reg(TSU_QTAG0);
2011 add_tsu_reg(TSU_QTAG1);
2012 add_tsu_reg(TSU_QTAGM0);
2013 add_tsu_reg(TSU_QTAGM1);
2014 add_tsu_reg(TSU_FWSR);
2015 add_tsu_reg(TSU_FWINMK);
2016 add_tsu_reg(TSU_ADQT0);
2017 add_tsu_reg(TSU_ADQT1);
2018 add_tsu_reg(TSU_VTAG0);
2019 add_tsu_reg(TSU_VTAG1);
2020 add_tsu_reg(TSU_ADSBSY);
2021 add_tsu_reg(TSU_TEN);
2022 add_tsu_reg(TSU_POST1);
2023 add_tsu_reg(TSU_POST2);
2024 add_tsu_reg(TSU_POST3);
2025 add_tsu_reg(TSU_POST4);
2026 if (mdp->reg_offset[TSU_ADRH0] != SH_ETH_OFFSET_INVALID) {
2027 /* This is the start of a table, not just a single
2033 mark_reg_valid(TSU_ADRH0);
2034 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++)
2037 mdp->reg_offset[TSU_ADRH0] +
2040 len += SH_ETH_TSU_CAM_ENTRIES * 2;
2044 #undef mark_reg_valid
2052 static int sh_eth_get_regs_len(struct net_device *ndev)
2054 return __sh_eth_get_regs(ndev, NULL);
2057 static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs,
2060 struct sh_eth_private *mdp = netdev_priv(ndev);
2062 regs->version = SH_ETH_REG_DUMP_VERSION;
2064 pm_runtime_get_sync(&mdp->pdev->dev);
2065 __sh_eth_get_regs(ndev, buf);
2066 pm_runtime_put_sync(&mdp->pdev->dev);
2069 static int sh_eth_nway_reset(struct net_device *ndev)
2071 struct sh_eth_private *mdp = netdev_priv(ndev);
2072 unsigned long flags;
2078 spin_lock_irqsave(&mdp->lock, flags);
2079 ret = phy_start_aneg(mdp->phydev);
2080 spin_unlock_irqrestore(&mdp->lock, flags);
2085 static u32 sh_eth_get_msglevel(struct net_device *ndev)
2087 struct sh_eth_private *mdp = netdev_priv(ndev);
2088 return mdp->msg_enable;
2091 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
2093 struct sh_eth_private *mdp = netdev_priv(ndev);
2094 mdp->msg_enable = value;
2097 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
2098 "rx_current", "tx_current",
2099 "rx_dirty", "tx_dirty",
2101 #define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
2103 static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
2107 return SH_ETH_STATS_LEN;
2113 static void sh_eth_get_ethtool_stats(struct net_device *ndev,
2114 struct ethtool_stats *stats, u64 *data)
2116 struct sh_eth_private *mdp = netdev_priv(ndev);
2119 /* device-specific stats */
2120 data[i++] = mdp->cur_rx;
2121 data[i++] = mdp->cur_tx;
2122 data[i++] = mdp->dirty_rx;
2123 data[i++] = mdp->dirty_tx;
2126 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
2128 switch (stringset) {
2130 memcpy(data, *sh_eth_gstrings_stats,
2131 sizeof(sh_eth_gstrings_stats));
2136 static void sh_eth_get_ringparam(struct net_device *ndev,
2137 struct ethtool_ringparam *ring)
2139 struct sh_eth_private *mdp = netdev_priv(ndev);
2141 ring->rx_max_pending = RX_RING_MAX;
2142 ring->tx_max_pending = TX_RING_MAX;
2143 ring->rx_pending = mdp->num_rx_ring;
2144 ring->tx_pending = mdp->num_tx_ring;
2147 static int sh_eth_set_ringparam(struct net_device *ndev,
2148 struct ethtool_ringparam *ring)
2150 struct sh_eth_private *mdp = netdev_priv(ndev);
2153 if (ring->tx_pending > TX_RING_MAX ||
2154 ring->rx_pending > RX_RING_MAX ||
2155 ring->tx_pending < TX_RING_MIN ||
2156 ring->rx_pending < RX_RING_MIN)
2158 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
2161 if (netif_running(ndev)) {
2162 netif_device_detach(ndev);
2163 netif_tx_disable(ndev);
2165 /* Serialise with the interrupt handler and NAPI, then
2166 * disable interrupts. We have to clear the
2167 * irq_enabled flag first to ensure that interrupts
2168 * won't be re-enabled.
2170 mdp->irq_enabled = false;
2171 synchronize_irq(ndev->irq);
2172 napi_synchronize(&mdp->napi);
2173 sh_eth_write(ndev, 0x0000, EESIPR);
2175 sh_eth_dev_exit(ndev);
2177 /* Free all the skbuffs in the Rx queue and the DMA buffers. */
2178 sh_eth_ring_free(ndev);
2181 /* Set new parameters */
2182 mdp->num_rx_ring = ring->rx_pending;
2183 mdp->num_tx_ring = ring->tx_pending;
2185 if (netif_running(ndev)) {
2186 ret = sh_eth_ring_init(ndev);
2188 netdev_err(ndev, "%s: sh_eth_ring_init failed.\n",
2192 ret = sh_eth_dev_init(ndev);
2194 netdev_err(ndev, "%s: sh_eth_dev_init failed.\n",
2199 netif_device_attach(ndev);
2205 static const struct ethtool_ops sh_eth_ethtool_ops = {
2206 .get_settings = sh_eth_get_settings,
2207 .set_settings = sh_eth_set_settings,
2208 .get_regs_len = sh_eth_get_regs_len,
2209 .get_regs = sh_eth_get_regs,
2210 .nway_reset = sh_eth_nway_reset,
2211 .get_msglevel = sh_eth_get_msglevel,
2212 .set_msglevel = sh_eth_set_msglevel,
2213 .get_link = ethtool_op_get_link,
2214 .get_strings = sh_eth_get_strings,
2215 .get_ethtool_stats = sh_eth_get_ethtool_stats,
2216 .get_sset_count = sh_eth_get_sset_count,
2217 .get_ringparam = sh_eth_get_ringparam,
2218 .set_ringparam = sh_eth_set_ringparam,
2221 /* network device open function */
2222 static int sh_eth_open(struct net_device *ndev)
2224 struct sh_eth_private *mdp = netdev_priv(ndev);
2227 pm_runtime_get_sync(&mdp->pdev->dev);
2229 napi_enable(&mdp->napi);
2231 ret = request_irq(ndev->irq, sh_eth_interrupt,
2232 mdp->cd->irq_flags, ndev->name, ndev);
2234 netdev_err(ndev, "Can not assign IRQ number\n");
2238 /* Descriptor set */
2239 ret = sh_eth_ring_init(ndev);
2244 ret = sh_eth_dev_init(ndev);
2248 /* PHY control start*/
2249 ret = sh_eth_phy_start(ndev);
2253 netif_start_queue(ndev);
2260 free_irq(ndev->irq, ndev);
2262 napi_disable(&mdp->napi);
2263 pm_runtime_put_sync(&mdp->pdev->dev);
2267 /* Timeout function */
2268 static void sh_eth_tx_timeout(struct net_device *ndev)
2270 struct sh_eth_private *mdp = netdev_priv(ndev);
2271 struct sh_eth_rxdesc *rxdesc;
2274 netif_stop_queue(ndev);
2276 netif_err(mdp, timer, ndev,
2277 "transmit timed out, status %8.8x, resetting...\n",
2278 sh_eth_read(ndev, EESR));
2280 /* tx_errors count up */
2281 ndev->stats.tx_errors++;
2283 /* Free all the skbuffs in the Rx queue. */
2284 for (i = 0; i < mdp->num_rx_ring; i++) {
2285 rxdesc = &mdp->rx_ring[i];
2286 rxdesc->status = cpu_to_le32(0);
2287 rxdesc->addr = cpu_to_le32(0xBADF00D0);
2288 dev_kfree_skb(mdp->rx_skbuff[i]);
2289 mdp->rx_skbuff[i] = NULL;
2291 for (i = 0; i < mdp->num_tx_ring; i++) {
2292 dev_kfree_skb(mdp->tx_skbuff[i]);
2293 mdp->tx_skbuff[i] = NULL;
2297 sh_eth_dev_init(ndev);
2299 netif_start_queue(ndev);
2302 /* Packet transmit function */
2303 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2305 struct sh_eth_private *mdp = netdev_priv(ndev);
2306 struct sh_eth_txdesc *txdesc;
2307 dma_addr_t dma_addr;
2309 unsigned long flags;
2311 spin_lock_irqsave(&mdp->lock, flags);
2312 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
2313 if (!sh_eth_txfree(ndev)) {
2314 netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
2315 netif_stop_queue(ndev);
2316 spin_unlock_irqrestore(&mdp->lock, flags);
2317 return NETDEV_TX_BUSY;
2320 spin_unlock_irqrestore(&mdp->lock, flags);
2322 if (skb_put_padto(skb, ETH_ZLEN))
2323 return NETDEV_TX_OK;
2325 entry = mdp->cur_tx % mdp->num_tx_ring;
2326 mdp->tx_skbuff[entry] = skb;
2327 txdesc = &mdp->tx_ring[entry];
2329 if (!mdp->cd->hw_swap)
2330 sh_eth_soft_swap(PTR_ALIGN(skb->data, 4), skb->len + 2);
2331 dma_addr = dma_map_single(&ndev->dev, skb->data, skb->len,
2333 if (dma_mapping_error(&ndev->dev, dma_addr)) {
2335 return NETDEV_TX_OK;
2337 txdesc->addr = cpu_to_le32(dma_addr);
2338 txdesc->len = cpu_to_le32(skb->len << 16);
2340 dma_wmb(); /* TACT bit must be set after all the above writes */
2341 if (entry >= mdp->num_tx_ring - 1)
2342 txdesc->status |= cpu_to_le32(TD_TACT | TD_TDLE);
2344 txdesc->status |= cpu_to_le32(TD_TACT);
2348 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
2349 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
2351 return NETDEV_TX_OK;
2354 /* The statistics registers have write-clear behaviour, which means we
2355 * will lose any increment between the read and write. We mitigate
2356 * this by only clearing when we read a non-zero value, so we will
2357 * never falsely report a total of zero.
2360 sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg)
2362 u32 delta = sh_eth_read(ndev, reg);
2366 sh_eth_write(ndev, 0, reg);
2370 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2372 struct sh_eth_private *mdp = netdev_priv(ndev);
2374 if (sh_eth_is_rz_fast_ether(mdp))
2375 return &ndev->stats;
2377 if (!mdp->is_opened)
2378 return &ndev->stats;
2380 sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR);
2381 sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR);
2382 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR);
2384 if (sh_eth_is_gether(mdp)) {
2385 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2387 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2390 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2394 return &ndev->stats;
2397 /* device close function */
2398 static int sh_eth_close(struct net_device *ndev)
2400 struct sh_eth_private *mdp = netdev_priv(ndev);
2402 netif_stop_queue(ndev);
2404 /* Serialise with the interrupt handler and NAPI, then disable
2405 * interrupts. We have to clear the irq_enabled flag first to
2406 * ensure that interrupts won't be re-enabled.
2408 mdp->irq_enabled = false;
2409 synchronize_irq(ndev->irq);
2410 napi_disable(&mdp->napi);
2411 sh_eth_write(ndev, 0x0000, EESIPR);
2413 sh_eth_dev_exit(ndev);
2415 /* PHY Disconnect */
2417 phy_stop(mdp->phydev);
2418 phy_disconnect(mdp->phydev);
2422 free_irq(ndev->irq, ndev);
2424 /* Free all the skbuffs in the Rx queue and the DMA buffer. */
2425 sh_eth_ring_free(ndev);
2427 pm_runtime_put_sync(&mdp->pdev->dev);
2434 /* ioctl to device function */
2435 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2437 struct sh_eth_private *mdp = netdev_priv(ndev);
2438 struct phy_device *phydev = mdp->phydev;
2440 if (!netif_running(ndev))
2446 return phy_mii_ioctl(phydev, rq, cmd);
2449 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2450 static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2453 return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2456 static u32 sh_eth_tsu_get_post_mask(int entry)
2458 return 0x0f << (28 - ((entry % 8) * 4));
2461 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2463 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2466 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2469 struct sh_eth_private *mdp = netdev_priv(ndev);
2473 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2474 tmp = ioread32(reg_offset);
2475 iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2478 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2481 struct sh_eth_private *mdp = netdev_priv(ndev);
2482 u32 post_mask, ref_mask, tmp;
2485 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2486 post_mask = sh_eth_tsu_get_post_mask(entry);
2487 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2489 tmp = ioread32(reg_offset);
2490 iowrite32(tmp & ~post_mask, reg_offset);
2492 /* If other port enables, the function returns "true" */
2493 return tmp & ref_mask;
2496 static int sh_eth_tsu_busy(struct net_device *ndev)
2498 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2499 struct sh_eth_private *mdp = netdev_priv(ndev);
2501 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2505 netdev_err(ndev, "%s: timeout\n", __func__);
2513 static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2518 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2519 iowrite32(val, reg);
2520 if (sh_eth_tsu_busy(ndev) < 0)
2523 val = addr[4] << 8 | addr[5];
2524 iowrite32(val, reg + 4);
2525 if (sh_eth_tsu_busy(ndev) < 0)
2531 static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2535 val = ioread32(reg);
2536 addr[0] = (val >> 24) & 0xff;
2537 addr[1] = (val >> 16) & 0xff;
2538 addr[2] = (val >> 8) & 0xff;
2539 addr[3] = val & 0xff;
2540 val = ioread32(reg + 4);
2541 addr[4] = (val >> 8) & 0xff;
2542 addr[5] = val & 0xff;
2546 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2548 struct sh_eth_private *mdp = netdev_priv(ndev);
2549 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2551 u8 c_addr[ETH_ALEN];
2553 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2554 sh_eth_tsu_read_entry(reg_offset, c_addr);
2555 if (ether_addr_equal(addr, c_addr))
2562 static int sh_eth_tsu_find_empty(struct net_device *ndev)
2567 memset(blank, 0, sizeof(blank));
2568 entry = sh_eth_tsu_find_entry(ndev, blank);
2569 return (entry < 0) ? -ENOMEM : entry;
2572 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2575 struct sh_eth_private *mdp = netdev_priv(ndev);
2576 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2580 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2581 ~(1 << (31 - entry)), TSU_TEN);
2583 memset(blank, 0, sizeof(blank));
2584 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2590 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2592 struct sh_eth_private *mdp = netdev_priv(ndev);
2593 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2599 i = sh_eth_tsu_find_entry(ndev, addr);
2601 /* No entry found, create one */
2602 i = sh_eth_tsu_find_empty(ndev);
2605 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2609 /* Enable the entry */
2610 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2611 (1 << (31 - i)), TSU_TEN);
2614 /* Entry found or created, enable POST */
2615 sh_eth_tsu_enable_cam_entry_post(ndev, i);
2620 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2622 struct sh_eth_private *mdp = netdev_priv(ndev);
2628 i = sh_eth_tsu_find_entry(ndev, addr);
2631 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2634 /* Disable the entry if both ports was disabled */
2635 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2643 static int sh_eth_tsu_purge_all(struct net_device *ndev)
2645 struct sh_eth_private *mdp = netdev_priv(ndev);
2651 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2652 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2655 /* Disable the entry if both ports was disabled */
2656 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2664 static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2666 struct sh_eth_private *mdp = netdev_priv(ndev);
2668 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2674 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2675 sh_eth_tsu_read_entry(reg_offset, addr);
2676 if (is_multicast_ether_addr(addr))
2677 sh_eth_tsu_del_entry(ndev, addr);
2681 /* Update promiscuous flag and multicast filter */
2682 static void sh_eth_set_rx_mode(struct net_device *ndev)
2684 struct sh_eth_private *mdp = netdev_priv(ndev);
2687 unsigned long flags;
2689 spin_lock_irqsave(&mdp->lock, flags);
2690 /* Initial condition is MCT = 1, PRM = 0.
2691 * Depending on ndev->flags, set PRM or clear MCT
2693 ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM;
2695 ecmr_bits |= ECMR_MCT;
2697 if (!(ndev->flags & IFF_MULTICAST)) {
2698 sh_eth_tsu_purge_mcast(ndev);
2701 if (ndev->flags & IFF_ALLMULTI) {
2702 sh_eth_tsu_purge_mcast(ndev);
2703 ecmr_bits &= ~ECMR_MCT;
2707 if (ndev->flags & IFF_PROMISC) {
2708 sh_eth_tsu_purge_all(ndev);
2709 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2710 } else if (mdp->cd->tsu) {
2711 struct netdev_hw_addr *ha;
2712 netdev_for_each_mc_addr(ha, ndev) {
2713 if (mcast_all && is_multicast_ether_addr(ha->addr))
2716 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2718 sh_eth_tsu_purge_mcast(ndev);
2719 ecmr_bits &= ~ECMR_MCT;
2726 /* update the ethernet mode */
2727 sh_eth_write(ndev, ecmr_bits, ECMR);
2729 spin_unlock_irqrestore(&mdp->lock, flags);
2732 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2740 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2741 __be16 proto, u16 vid)
2743 struct sh_eth_private *mdp = netdev_priv(ndev);
2744 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2746 if (unlikely(!mdp->cd->tsu))
2749 /* No filtering if vid = 0 */
2753 mdp->vlan_num_ids++;
2755 /* The controller has one VLAN tag HW filter. So, if the filter is
2756 * already enabled, the driver disables it and the filte
2758 if (mdp->vlan_num_ids > 1) {
2759 /* disable VLAN filter */
2760 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2764 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2770 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2771 __be16 proto, u16 vid)
2773 struct sh_eth_private *mdp = netdev_priv(ndev);
2774 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2776 if (unlikely(!mdp->cd->tsu))
2779 /* No filtering if vid = 0 */
2783 mdp->vlan_num_ids--;
2784 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2789 /* SuperH's TSU register init function */
2790 static void sh_eth_tsu_init(struct sh_eth_private *mdp)
2792 if (sh_eth_is_rz_fast_ether(mdp)) {
2793 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2794 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL,
2795 TSU_FWSLC); /* Enable POST registers */
2799 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
2800 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
2801 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
2802 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2803 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2804 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2805 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2806 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2807 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2808 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
2809 if (sh_eth_is_gether(mdp)) {
2810 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */
2811 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */
2813 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
2814 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
2816 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
2817 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
2818 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2819 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
2820 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
2821 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
2822 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
2825 /* MDIO bus release function */
2826 static int sh_mdio_release(struct sh_eth_private *mdp)
2828 /* unregister mdio bus */
2829 mdiobus_unregister(mdp->mii_bus);
2831 /* free bitbang info */
2832 free_mdio_bitbang(mdp->mii_bus);
2837 /* MDIO bus init function */
2838 static int sh_mdio_init(struct sh_eth_private *mdp,
2839 struct sh_eth_plat_data *pd)
2842 struct bb_info *bitbang;
2843 struct platform_device *pdev = mdp->pdev;
2844 struct device *dev = &mdp->pdev->dev;
2846 /* create bit control struct for PHY */
2847 bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL);
2852 bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
2853 bitbang->set_gate = pd->set_mdio_gate;
2854 bitbang->ctrl.ops = &bb_ops;
2856 /* MII controller setting */
2857 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
2861 /* Hook up MII support for ethtool */
2862 mdp->mii_bus->name = "sh_mii";
2863 mdp->mii_bus->parent = dev;
2864 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2865 pdev->name, pdev->id);
2867 /* register MDIO bus */
2869 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node);
2871 if (pd->phy_irq > 0)
2872 mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
2874 ret = mdiobus_register(mdp->mii_bus);
2883 free_mdio_bitbang(mdp->mii_bus);
2887 static const u16 *sh_eth_get_register_offset(int register_type)
2889 const u16 *reg_offset = NULL;
2891 switch (register_type) {
2892 case SH_ETH_REG_GIGABIT:
2893 reg_offset = sh_eth_offset_gigabit;
2895 case SH_ETH_REG_FAST_RZ:
2896 reg_offset = sh_eth_offset_fast_rz;
2898 case SH_ETH_REG_FAST_RCAR:
2899 reg_offset = sh_eth_offset_fast_rcar;
2901 case SH_ETH_REG_FAST_SH4:
2902 reg_offset = sh_eth_offset_fast_sh4;
2904 case SH_ETH_REG_FAST_SH3_SH2:
2905 reg_offset = sh_eth_offset_fast_sh3_sh2;
2912 static const struct net_device_ops sh_eth_netdev_ops = {
2913 .ndo_open = sh_eth_open,
2914 .ndo_stop = sh_eth_close,
2915 .ndo_start_xmit = sh_eth_start_xmit,
2916 .ndo_get_stats = sh_eth_get_stats,
2917 .ndo_set_rx_mode = sh_eth_set_rx_mode,
2918 .ndo_tx_timeout = sh_eth_tx_timeout,
2919 .ndo_do_ioctl = sh_eth_do_ioctl,
2920 .ndo_validate_addr = eth_validate_addr,
2921 .ndo_set_mac_address = eth_mac_addr,
2922 .ndo_change_mtu = eth_change_mtu,
2925 static const struct net_device_ops sh_eth_netdev_ops_tsu = {
2926 .ndo_open = sh_eth_open,
2927 .ndo_stop = sh_eth_close,
2928 .ndo_start_xmit = sh_eth_start_xmit,
2929 .ndo_get_stats = sh_eth_get_stats,
2930 .ndo_set_rx_mode = sh_eth_set_rx_mode,
2931 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid,
2932 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid,
2933 .ndo_tx_timeout = sh_eth_tx_timeout,
2934 .ndo_do_ioctl = sh_eth_do_ioctl,
2935 .ndo_validate_addr = eth_validate_addr,
2936 .ndo_set_mac_address = eth_mac_addr,
2937 .ndo_change_mtu = eth_change_mtu,
2941 static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
2943 struct device_node *np = dev->of_node;
2944 struct sh_eth_plat_data *pdata;
2945 const char *mac_addr;
2947 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2951 pdata->phy_interface = of_get_phy_mode(np);
2953 mac_addr = of_get_mac_address(np);
2955 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
2957 pdata->no_ether_link =
2958 of_property_read_bool(np, "renesas,no-ether-link");
2959 pdata->ether_link_active_low =
2960 of_property_read_bool(np, "renesas,ether-link-active-low");
2965 static const struct of_device_id sh_eth_match_table[] = {
2966 { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
2967 { .compatible = "renesas,ether-r8a7778", .data = &r8a777x_data },
2968 { .compatible = "renesas,ether-r8a7779", .data = &r8a777x_data },
2969 { .compatible = "renesas,ether-r8a7790", .data = &r8a779x_data },
2970 { .compatible = "renesas,ether-r8a7791", .data = &r8a779x_data },
2971 { .compatible = "renesas,ether-r8a7793", .data = &r8a779x_data },
2972 { .compatible = "renesas,ether-r8a7794", .data = &r8a779x_data },
2973 { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
2976 MODULE_DEVICE_TABLE(of, sh_eth_match_table);
2978 static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
2984 static int sh_eth_drv_probe(struct platform_device *pdev)
2986 struct resource *res;
2987 struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
2988 const struct platform_device_id *id = platform_get_device_id(pdev);
2989 struct sh_eth_private *mdp;
2990 struct net_device *ndev;
2994 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2996 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
3000 pm_runtime_enable(&pdev->dev);
3001 pm_runtime_get_sync(&pdev->dev);
3007 ret = platform_get_irq(pdev, 0);
3012 SET_NETDEV_DEV(ndev, &pdev->dev);
3014 mdp = netdev_priv(ndev);
3015 mdp->num_tx_ring = TX_RING_SIZE;
3016 mdp->num_rx_ring = RX_RING_SIZE;
3017 mdp->addr = devm_ioremap_resource(&pdev->dev, res);
3018 if (IS_ERR(mdp->addr)) {
3019 ret = PTR_ERR(mdp->addr);
3023 ndev->base_addr = res->start;
3025 spin_lock_init(&mdp->lock);
3028 if (pdev->dev.of_node)
3029 pd = sh_eth_parse_dt(&pdev->dev);
3031 dev_err(&pdev->dev, "no platform data\n");
3037 mdp->phy_id = pd->phy;
3038 mdp->phy_interface = pd->phy_interface;
3039 mdp->no_ether_link = pd->no_ether_link;
3040 mdp->ether_link_active_low = pd->ether_link_active_low;
3044 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
3046 mdp->cd = (struct sh_eth_cpu_data *)of_device_get_match_data(&pdev->dev);
3048 mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
3049 if (!mdp->reg_offset) {
3050 dev_err(&pdev->dev, "Unknown register type (%d)\n",
3051 mdp->cd->register_type);
3055 sh_eth_set_default_cpu_data(mdp->cd);
3059 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
3061 ndev->netdev_ops = &sh_eth_netdev_ops;
3062 ndev->ethtool_ops = &sh_eth_ethtool_ops;
3063 ndev->watchdog_timeo = TX_TIMEOUT;
3065 /* debug message level */
3066 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
3068 /* read and set MAC address */
3069 read_mac_address(ndev, pd->mac_addr);
3070 if (!is_valid_ether_addr(ndev->dev_addr)) {
3071 dev_warn(&pdev->dev,
3072 "no valid MAC address supplied, using a random one.\n");
3073 eth_hw_addr_random(ndev);
3076 /* ioremap the TSU registers */
3078 struct resource *rtsu;
3079 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3080 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
3081 if (IS_ERR(mdp->tsu_addr)) {
3082 ret = PTR_ERR(mdp->tsu_addr);
3085 mdp->port = devno % 2;
3086 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
3089 /* initialize first or needed device */
3090 if (!devno || pd->needs_init) {
3091 if (mdp->cd->chip_reset)
3092 mdp->cd->chip_reset(ndev);
3095 /* TSU init (Init only)*/
3096 sh_eth_tsu_init(mdp);
3100 if (mdp->cd->rmiimode)
3101 sh_eth_write(ndev, 0x1, RMIIMODE);
3104 ret = sh_mdio_init(mdp, pd);
3106 dev_err(&ndev->dev, "failed to initialise MDIO\n");
3110 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
3112 /* network device register */
3113 ret = register_netdev(ndev);
3117 /* print device information */
3118 netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
3119 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
3121 pm_runtime_put(&pdev->dev);
3122 platform_set_drvdata(pdev, ndev);
3127 netif_napi_del(&mdp->napi);
3128 sh_mdio_release(mdp);
3135 pm_runtime_put(&pdev->dev);
3136 pm_runtime_disable(&pdev->dev);
3140 static int sh_eth_drv_remove(struct platform_device *pdev)
3142 struct net_device *ndev = platform_get_drvdata(pdev);
3143 struct sh_eth_private *mdp = netdev_priv(ndev);
3145 unregister_netdev(ndev);
3146 netif_napi_del(&mdp->napi);
3147 sh_mdio_release(mdp);
3148 pm_runtime_disable(&pdev->dev);
3155 #ifdef CONFIG_PM_SLEEP
3156 static int sh_eth_suspend(struct device *dev)
3158 struct net_device *ndev = dev_get_drvdata(dev);
3161 if (netif_running(ndev)) {
3162 netif_device_detach(ndev);
3163 ret = sh_eth_close(ndev);
3169 static int sh_eth_resume(struct device *dev)
3171 struct net_device *ndev = dev_get_drvdata(dev);
3174 if (netif_running(ndev)) {
3175 ret = sh_eth_open(ndev);
3178 netif_device_attach(ndev);
3185 static int sh_eth_runtime_nop(struct device *dev)
3187 /* Runtime PM callback shared between ->runtime_suspend()
3188 * and ->runtime_resume(). Simply returns success.
3190 * This driver re-initializes all registers after
3191 * pm_runtime_get_sync() anyway so there is no need
3192 * to save and restore registers here.
3197 static const struct dev_pm_ops sh_eth_dev_pm_ops = {
3198 SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume)
3199 SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL)
3201 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
3203 #define SH_ETH_PM_OPS NULL
3206 static struct platform_device_id sh_eth_id_table[] = {
3207 { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
3208 { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
3209 { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
3210 { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
3211 { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
3212 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
3213 { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
3216 MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
3218 static struct platform_driver sh_eth_driver = {
3219 .probe = sh_eth_drv_probe,
3220 .remove = sh_eth_drv_remove,
3221 .id_table = sh_eth_id_table,
3224 .pm = SH_ETH_PM_OPS,
3225 .of_match_table = of_match_ptr(sh_eth_match_table),
3229 module_platform_driver(sh_eth_driver);
3231 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3232 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3233 MODULE_LICENSE("GPL v2");