drivers/net/ethernet/renesas/sh_eth.h

   1 /*
   2  *  SuperH Ethernet device driver
   3  *
   4  *  Copyright (C) 2006-2008 Nobuhiro Iwamatsu
   5  *  Copyright (C) 2008-2011 Renesas Solutions Corp.
   6  *
   7  *  This program is free software; you can redistribute it and/or modify it
   8  *  under the terms and conditions of the GNU General Public License,
   9  *  version 2, as published by the Free Software Foundation.
  10  *
  11  *  This program is distributed in the hope it will be useful, but WITHOUT
  12  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  *  more details.
  15  *  You should have received a copy of the GNU General Public License along with
  16  *  this program; if not, write to the Free Software Foundation, Inc.,
  17  *  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  *  The full GNU General Public License is included in this distribution in
  20  *  the file called "COPYING".
  21  */
  22
  23 #ifndef __SH_ETH_H__
  24 #define __SH_ETH_H__
  25
  26 #define CARDNAME        "sh-eth"
  27 #define TX_TIMEOUT      (5*HZ)
  28 #define TX_RING_SIZE    64      /* Tx ring size */
  29 #define RX_RING_SIZE    64      /* Rx ring size */
  30 #define ETHERSMALL              60
  31 #define PKT_BUF_SZ              1538
  32 #define SH_ETH_TSU_TIMEOUT_MS   500
  33 #define SH_ETH_TSU_CAM_ENTRIES  32
  34
  35 enum {
  36         /* E-DMAC registers */
  37         EDSR = 0,
  38         EDMR,
  39         EDTRR,
  40         EDRRR,
  41         EESR,
  42         EESIPR,
  43         TDLAR,
  44         TDFAR,
  45         TDFXR,
  46         TDFFR,
  47         RDLAR,
  48         RDFAR,
  49         RDFXR,
  50         RDFFR,
  51         TRSCER,
  52         RMFCR,
  53         TFTR,
  54         FDR,
  55         RMCR,
  56         EDOCR,
  57         TFUCR,
  58         RFOCR,
  59         FCFTR,
  60         RPADIR,
  61         TRIMD,
  62         RBWAR,
  63         TBRAR,
  64
  65         /* Ether registers */
  66         ECMR,
  67         ECSR,
  68         ECSIPR,
  69         PIR,
  70         PSR,
  71         RDMLR,
  72         PIPR,
  73         RFLR,
  74         IPGR,
  75         APR,
  76         MPR,
  77         PFTCR,
  78         PFRCR,
  79         RFCR,
  80         RFCF,
  81         TPAUSER,
  82         TPAUSECR,
  83         BCFR,
  84         BCFRR,
  85         GECMR,
  86         BCULR,
  87         MAHR,
  88         MALR,
  89         TROCR,
  90         CDCR,
  91         LCCR,
  92         CNDCR,
  93         CEFCR,
  94         FRECR,
  95         TSFRCR,
  96         TLFRCR,
  97         CERCR,
  98         CEECR,
  99         MAFCR,
 100         RTRATE,
 101
 102         /* TSU Absolute address */
 103         ARSTR,
 104         TSU_CTRST,
 105         TSU_FWEN0,
 106         TSU_FWEN1,
 107         TSU_FCM,
 108         TSU_BSYSL0,
 109         TSU_BSYSL1,
 110         TSU_PRISL0,
 111         TSU_PRISL1,
 112         TSU_FWSL0,
 113         TSU_FWSL1,
 114         TSU_FWSLC,
 115         TSU_QTAG0,
 116         TSU_QTAG1,
 117         TSU_QTAGM0,
 118         TSU_QTAGM1,
 119         TSU_FWSR,
 120         TSU_FWINMK,
 121         TSU_ADQT0,
 122         TSU_ADQT1,
 123         TSU_VTAG0,
 124         TSU_VTAG1,
 125         TSU_ADSBSY,
 126         TSU_TEN,
 127         TSU_POST1,
 128         TSU_POST2,
 129         TSU_POST3,
 130         TSU_POST4,
 131         TSU_ADRH0,
 132         TSU_ADRL0,
 133         TSU_ADRH31,
 134         TSU_ADRL31,
 135
 136         TXNLCR0,
 137         TXALCR0,
 138         RXNLCR0,
 139         RXALCR0,
 140         FWNLCR0,
 141         FWALCR0,
 142         TXNLCR1,
 143         TXALCR1,
 144         RXNLCR1,
 145         RXALCR1,
 146         FWNLCR1,
 147         FWALCR1,
 148
 149         /* This value must be written at last. */
 150         SH_ETH_MAX_REGISTER_OFFSET,
 151 };
 152
 153 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
 154         [EDSR]  = 0x0000,
 155         [EDMR]  = 0x0400,
 156         [EDTRR] = 0x0408,
 157         [EDRRR] = 0x0410,
 158         [EESR]  = 0x0428,
 159         [EESIPR]        = 0x0430,
 160         [TDLAR] = 0x0010,
 161         [TDFAR] = 0x0014,
 162         [TDFXR] = 0x0018,
 163         [TDFFR] = 0x001c,
 164         [RDLAR] = 0x0030,
 165         [RDFAR] = 0x0034,
 166         [RDFXR] = 0x0038,
 167         [RDFFR] = 0x003c,
 168         [TRSCER]        = 0x0438,
 169         [RMFCR] = 0x0440,
 170         [TFTR]  = 0x0448,
 171         [FDR]   = 0x0450,
 172         [RMCR]  = 0x0458,
 173         [RPADIR]        = 0x0460,
 174         [FCFTR] = 0x0468,
 175
 176         [ECMR]  = 0x0500,
 177         [ECSR]  = 0x0510,
 178         [ECSIPR]        = 0x0518,
 179         [PIR]   = 0x0520,
 180         [PSR]   = 0x0528,
 181         [PIPR]  = 0x052c,
 182         [RFLR]  = 0x0508,
 183         [APR]   = 0x0554,
 184         [MPR]   = 0x0558,
 185         [PFTCR] = 0x055c,
 186         [PFRCR] = 0x0560,
 187         [TPAUSER]       = 0x0564,
 188         [GECMR] = 0x05b0,
 189         [BCULR] = 0x05b4,
 190         [MAHR]  = 0x05c0,
 191         [MALR]  = 0x05c8,
 192         [TROCR] = 0x0700,
 193         [CDCR]  = 0x0708,
 194         [LCCR]  = 0x0710,
 195         [CEFCR] = 0x0740,
 196         [FRECR] = 0x0748,
 197         [TSFRCR]        = 0x0750,
 198         [TLFRCR]        = 0x0758,
 199         [RFCR]  = 0x0760,
 200         [CERCR] = 0x0768,
 201         [CEECR] = 0x0770,
 202         [MAFCR] = 0x0778,
 203
 204         [ARSTR] = 0x0000,
 205         [TSU_CTRST]     = 0x0004,
 206         [TSU_FWEN0]     = 0x0010,
 207         [TSU_FWEN1]     = 0x0014,
 208         [TSU_FCM]       = 0x0018,
 209         [TSU_BSYSL0]    = 0x0020,
 210         [TSU_BSYSL1]    = 0x0024,
 211         [TSU_PRISL0]    = 0x0028,
 212         [TSU_PRISL1]    = 0x002c,
 213         [TSU_FWSL0]     = 0x0030,
 214         [TSU_FWSL1]     = 0x0034,
 215         [TSU_FWSLC]     = 0x0038,
 216         [TSU_QTAG0]     = 0x0040,
 217         [TSU_QTAG1]     = 0x0044,
 218         [TSU_FWSR]      = 0x0050,
 219         [TSU_FWINMK]    = 0x0054,
 220         [TSU_ADQT0]     = 0x0048,
 221         [TSU_ADQT1]     = 0x004c,
 222         [TSU_VTAG0]     = 0x0058,
 223         [TSU_VTAG1]     = 0x005c,
 224         [TSU_ADSBSY]    = 0x0060,
 225         [TSU_TEN]       = 0x0064,
 226         [TSU_POST1]     = 0x0070,
 227         [TSU_POST2]     = 0x0074,
 228         [TSU_POST3]     = 0x0078,
 229         [TSU_POST4]     = 0x007c,
 230         [TSU_ADRH0]     = 0x0100,
 231         [TSU_ADRL0]     = 0x0104,
 232         [TSU_ADRH31]    = 0x01f8,
 233         [TSU_ADRL31]    = 0x01fc,
 234
 235         [TXNLCR0]       = 0x0080,
 236         [TXALCR0]       = 0x0084,
 237         [RXNLCR0]       = 0x0088,
 238         [RXALCR0]       = 0x008c,
 239         [FWNLCR0]       = 0x0090,
 240         [FWALCR0]       = 0x0094,
 241         [TXNLCR1]       = 0x00a0,
 242         [TXALCR1]       = 0x00a0,
 243         [RXNLCR1]       = 0x00a8,
 244         [RXALCR1]       = 0x00ac,
 245         [FWNLCR1]       = 0x00b0,
 246         [FWALCR1]       = 0x00b4,
 247 };
 248
 249 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
 250         [ECMR]  = 0x0100,
 251         [RFLR]  = 0x0108,
 252         [ECSR]  = 0x0110,
 253         [ECSIPR]        = 0x0118,
 254         [PIR]   = 0x0120,
 255         [PSR]   = 0x0128,
 256         [RDMLR] = 0x0140,
 257         [IPGR]  = 0x0150,
 258         [APR]   = 0x0154,
 259         [MPR]   = 0x0158,
 260         [TPAUSER]       = 0x0164,
 261         [RFCF]  = 0x0160,
 262         [TPAUSECR]      = 0x0168,
 263         [BCFRR] = 0x016c,
 264         [MAHR]  = 0x01c0,
 265         [MALR]  = 0x01c8,
 266         [TROCR] = 0x01d0,
 267         [CDCR]  = 0x01d4,
 268         [LCCR]  = 0x01d8,
 269         [CNDCR] = 0x01dc,
 270         [CEFCR] = 0x01e4,
 271         [FRECR] = 0x01e8,
 272         [TSFRCR]        = 0x01ec,
 273         [TLFRCR]        = 0x01f0,
 274         [RFCR]  = 0x01f4,
 275         [MAFCR] = 0x01f8,
 276         [RTRATE]        = 0x01fc,
 277
 278         [EDMR]  = 0x0000,
 279         [EDTRR] = 0x0008,
 280         [EDRRR] = 0x0010,
 281         [TDLAR] = 0x0018,
 282         [RDLAR] = 0x0020,
 283         [EESR]  = 0x0028,
 284         [EESIPR]        = 0x0030,
 285         [TRSCER]        = 0x0038,
 286         [RMFCR] = 0x0040,
 287         [TFTR]  = 0x0048,
 288         [FDR]   = 0x0050,
 289         [RMCR]  = 0x0058,
 290         [TFUCR] = 0x0064,
 291         [RFOCR] = 0x0068,
 292         [FCFTR] = 0x0070,
 293         [RPADIR]        = 0x0078,
 294         [TRIMD] = 0x007c,
 295         [RBWAR] = 0x00c8,
 296         [RDFAR] = 0x00cc,
 297         [TBRAR] = 0x00d4,
 298         [TDFAR] = 0x00d8,
 299 };
 300
 301 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
 302         [ECMR]  = 0x0160,
 303         [ECSR]  = 0x0164,
 304         [ECSIPR]        = 0x0168,
 305         [PIR]   = 0x016c,
 306         [MAHR]  = 0x0170,
 307         [MALR]  = 0x0174,
 308         [RFLR]  = 0x0178,
 309         [PSR]   = 0x017c,
 310         [TROCR] = 0x0180,
 311         [CDCR]  = 0x0184,
 312         [LCCR]  = 0x0188,
 313         [CNDCR] = 0x018c,
 314         [CEFCR] = 0x0194,
 315         [FRECR] = 0x0198,
 316         [TSFRCR]        = 0x019c,
 317         [TLFRCR]        = 0x01a0,
 318         [RFCR]  = 0x01a4,
 319         [MAFCR] = 0x01a8,
 320         [IPGR]  = 0x01b4,
 321         [APR]   = 0x01b8,
 322         [MPR]   = 0x01bc,
 323         [TPAUSER]       = 0x01c4,
 324         [BCFR]  = 0x01cc,
 325
 326         [ARSTR] = 0x0000,
 327         [TSU_CTRST]     = 0x0004,
 328         [TSU_FWEN0]     = 0x0010,
 329         [TSU_FWEN1]     = 0x0014,
 330         [TSU_FCM]       = 0x0018,
 331         [TSU_BSYSL0]    = 0x0020,
 332         [TSU_BSYSL1]    = 0x0024,
 333         [TSU_PRISL0]    = 0x0028,
 334         [TSU_PRISL1]    = 0x002c,
 335         [TSU_FWSL0]     = 0x0030,
 336         [TSU_FWSL1]     = 0x0034,
 337         [TSU_FWSLC]     = 0x0038,
 338         [TSU_QTAGM0]    = 0x0040,
 339         [TSU_QTAGM1]    = 0x0044,
 340         [TSU_ADQT0]     = 0x0048,
 341         [TSU_ADQT1]     = 0x004c,
 342         [TSU_FWSR]      = 0x0050,
 343         [TSU_FWINMK]    = 0x0054,
 344         [TSU_ADSBSY]    = 0x0060,
 345         [TSU_TEN]       = 0x0064,
 346         [TSU_POST1]     = 0x0070,
 347         [TSU_POST2]     = 0x0074,
 348         [TSU_POST3]     = 0x0078,
 349         [TSU_POST4]     = 0x007c,
 350
 351         [TXNLCR0]       = 0x0080,
 352         [TXALCR0]       = 0x0084,
 353         [RXNLCR0]       = 0x0088,
 354         [RXALCR0]       = 0x008c,
 355         [FWNLCR0]       = 0x0090,
 356         [FWALCR0]       = 0x0094,
 357         [TXNLCR1]       = 0x00a0,
 358         [TXALCR1]       = 0x00a0,
 359         [RXNLCR1]       = 0x00a8,
 360         [RXALCR1]       = 0x00ac,
 361         [FWNLCR1]       = 0x00b0,
 362         [FWALCR1]       = 0x00b4,
 363
 364         [TSU_ADRH0]     = 0x0100,
 365         [TSU_ADRL0]     = 0x0104,
 366         [TSU_ADRL31]    = 0x01fc,
 367
 368 };
 369
 370 /* Driver's parameters */
 371 #if defined(CONFIG_CPU_SH4)
 372 #define SH4_SKB_RX_ALIGN        32
 373 #else
 374 #define SH2_SH3_SKB_RX_ALIGN    2
 375 #endif
 376
 377 /*
 378  * Register's bits
 379  */
 380 #ifdef CONFIG_CPU_SUBTYPE_SH7763
 381 /* EDSR */
 382 enum EDSR_BIT {
 383         EDSR_ENT = 0x01, EDSR_ENR = 0x02,
 384 };
 385 #define EDSR_ENALL (EDSR_ENT|EDSR_ENR)
 386
 387 /* GECMR */
 388 enum GECMR_BIT {
 389         GECMR_10 = 0x0, GECMR_100 = 0x04, GECMR_1000 = 0x01,
 390 };
 391 #endif
 392
 393 /* EDMR */
 394 enum DMAC_M_BIT {
 395         EDMR_EL = 0x40, /* Litte endian */
 396         EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
 397         EDMR_SRST_GETHER = 0x03,
 398         EDMR_SRST_ETHER = 0x01,
 399 };
 400
 401 /* EDTRR */
 402 enum DMAC_T_BIT {
 403         EDTRR_TRNS_GETHER = 0x03,
 404         EDTRR_TRNS_ETHER = 0x01,
 405 };
 406
 407 /* EDRRR*/
 408 enum EDRRR_R_BIT {
 409         EDRRR_R = 0x01,
 410 };
 411
 412 /* TPAUSER */
 413 enum TPAUSER_BIT {
 414         TPAUSER_TPAUSE = 0x0000ffff,
 415         TPAUSER_UNLIMITED = 0,
 416 };
 417
 418 /* BCFR */
 419 enum BCFR_BIT {
 420         BCFR_RPAUSE = 0x0000ffff,
 421         BCFR_UNLIMITED = 0,
 422 };
 423
 424 /* PIR */
 425 enum PIR_BIT {
 426         PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01,
 427 };
 428
 429 /* PSR */
 430 enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, };
 431
 432 /* EESR */
 433 enum EESR_BIT {
 434         EESR_TWB1       = 0x80000000,
 435         EESR_TWB        = 0x40000000,   /* same as TWB0 */
 436         EESR_TC1        = 0x20000000,
 437         EESR_TUC        = 0x10000000,
 438         EESR_ROC        = 0x08000000,
 439         EESR_TABT       = 0x04000000,
 440         EESR_RABT       = 0x02000000,
 441         EESR_RFRMER     = 0x01000000,   /* same as RFCOF */
 442         EESR_ADE        = 0x00800000,
 443         EESR_ECI        = 0x00400000,
 444         EESR_FTC        = 0x00200000,   /* same as TC or TC0 */
 445         EESR_TDE        = 0x00100000,
 446         EESR_TFE        = 0x00080000,   /* same as TFUF */
 447         EESR_FRC        = 0x00040000,   /* same as FR */
 448         EESR_RDE        = 0x00020000,
 449         EESR_RFE        = 0x00010000,
 450         EESR_CND        = 0x00000800,
 451         EESR_DLC        = 0x00000400,
 452         EESR_CD         = 0x00000200,
 453         EESR_RTO        = 0x00000100,
 454         EESR_RMAF       = 0x00000080,
 455         EESR_CEEF       = 0x00000040,
 456         EESR_CELF       = 0x00000020,
 457         EESR_RRF        = 0x00000010,
 458         EESR_RTLF       = 0x00000008,
 459         EESR_RTSF       = 0x00000004,
 460         EESR_PRE        = 0x00000002,
 461         EESR_CERF       = 0x00000001,
 462 };
 463
 464 #define DEFAULT_TX_CHECK        (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | \
 465                                  EESR_RTO)
 466 #define DEFAULT_EESR_ERR_CHECK  (EESR_TWB | EESR_TABT | EESR_RABT | \
 467                                  EESR_RDE | EESR_RFRMER | EESR_ADE | \
 468                                  EESR_TFE | EESR_TDE | EESR_ECI)
 469 #define DEFAULT_TX_ERROR_CHECK  (EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | \
 470                                  EESR_TFE)
 471
 472 /* EESIPR */
 473 enum DMAC_IM_BIT {
 474         DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000,
 475         DMAC_M_RABT = 0x02000000,
 476         DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000,
 477         DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000,
 478         DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000,
 479         DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000,
 480         DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800,
 481         DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200,
 482         DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080,
 483         DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008,
 484         DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002,
 485         DMAC_M_RINT1 = 0x00000001,
 486 };
 487
 488 /* Receive descriptor bit */
 489 enum RD_STS_BIT {
 490         RD_RACT = 0x80000000, RD_RDEL = 0x40000000,
 491         RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000,
 492         RD_RFE = 0x08000000, RD_RFS10 = 0x00000200,
 493         RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080,
 494         RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020,
 495         RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008,
 496         RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002,
 497         RD_RFS1 = 0x00000001,
 498 };
 499 #define RDF1ST  RD_RFP1
 500 #define RDFEND  RD_RFP0
 501 #define RD_RFP  (RD_RFP1|RD_RFP0)
 502
 503 /* FCFTR */
 504 enum FCFTR_BIT {
 505         FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000,
 506         FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004,
 507         FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001,
 508 };
 509 #define DEFAULT_FIFO_F_D_RFF    (FCFTR_RFF2 | FCFTR_RFF1 | FCFTR_RFF0)
 510 #define DEFAULT_FIFO_F_D_RFD    (FCFTR_RFD2 | FCFTR_RFD1 | FCFTR_RFD0)
 511
 512 /* Transfer descriptor bit */
 513 enum TD_STS_BIT {
 514         TD_TACT = 0x80000000,
 515         TD_TDLE = 0x40000000, TD_TFP1 = 0x20000000,
 516         TD_TFP0 = 0x10000000,
 517 };
 518 #define TDF1ST  TD_TFP1
 519 #define TDFEND  TD_TFP0
 520 #define TD_TFP  (TD_TFP1|TD_TFP0)
 521
 522 /* RMCR */
 523 #define DEFAULT_RMCR_VALUE      0x00000000
 524
 525 /* ECMR */
 526 enum FELIC_MODE_BIT {
 527         ECMR_TRCCM = 0x04000000, ECMR_RCSC = 0x00800000,
 528         ECMR_DPAD = 0x00200000, ECMR_RZPF = 0x00100000,
 529         ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000,
 530         ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000,
 531         ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020,
 532         ECMR_RTM = 0x00000010, ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004,
 533         ECMR_DM = 0x00000002, ECMR_PRM = 0x00000001,
 534 };
 535
 536 /* ECSR */
 537 enum ECSR_STATUS_BIT {
 538         ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10,
 539         ECSR_LCHNG = 0x04,
 540         ECSR_MPD = 0x02, ECSR_ICD = 0x01,
 541 };
 542
 543 #define DEFAULT_ECSR_INIT       (ECSR_BRCRX | ECSR_PSRTO | ECSR_LCHNG | \
 544                                  ECSR_ICD | ECSIPR_MPDIP)
 545
 546 /* ECSIPR */
 547 enum ECSIPR_STATUS_MASK_BIT {
 548         ECSIPR_BRCRXIP = 0x20, ECSIPR_PSRTOIP = 0x10,
 549         ECSIPR_LCHNGIP = 0x04,
 550         ECSIPR_MPDIP = 0x02, ECSIPR_ICDIP = 0x01,
 551 };
 552
 553 #define DEFAULT_ECSIPR_INIT     (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | \
 554                                  ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP)
 555
 556 /* APR */
 557 enum APR_BIT {
 558         APR_AP = 0x00000001,
 559 };
 560
 561 /* MPR */
 562 enum MPR_BIT {
 563         MPR_MP = 0x00000001,
 564 };
 565
 566 /* TRSCER */
 567 enum DESC_I_BIT {
 568         DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200,
 569         DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010,
 570         DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002,
 571         DESC_I_RINT1 = 0x0001,
 572 };
 573
 574 /* RPADIR */
 575 enum RPADIR_BIT {
 576         RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000,
 577         RPADIR_PADR = 0x0003f,
 578 };
 579
 580 /* FDR */
 581 #define DEFAULT_FDR_INIT        0x00000707
 582
 583 enum phy_offsets {
 584         PHY_CTRL = 0, PHY_STAT = 1, PHY_IDT1 = 2, PHY_IDT2 = 3,
 585         PHY_ANA = 4, PHY_ANL = 5, PHY_ANE = 6,
 586         PHY_16 = 16,
 587 };
 588
 589 /* PHY_CTRL */
 590 enum PHY_CTRL_BIT {
 591         PHY_C_RESET = 0x8000, PHY_C_LOOPBK = 0x4000, PHY_C_SPEEDSL = 0x2000,
 592         PHY_C_ANEGEN = 0x1000, PHY_C_PWRDN = 0x0800, PHY_C_ISO = 0x0400,
 593         PHY_C_RANEG = 0x0200, PHY_C_DUPLEX = 0x0100, PHY_C_COLT = 0x0080,
 594 };
 595 #define DM9161_PHY_C_ANEGEN 0   /* auto nego special */
 596
 597 /* PHY_STAT */
 598 enum PHY_STAT_BIT {
 599         PHY_S_100T4 = 0x8000, PHY_S_100X_F = 0x4000, PHY_S_100X_H = 0x2000,
 600         PHY_S_10T_F = 0x1000, PHY_S_10T_H = 0x0800, PHY_S_ANEGC = 0x0020,
 601         PHY_S_RFAULT = 0x0010, PHY_S_ANEGA = 0x0008, PHY_S_LINK = 0x0004,
 602         PHY_S_JAB = 0x0002, PHY_S_EXTD = 0x0001,
 603 };
 604
 605 /* PHY_ANA */
 606 enum PHY_ANA_BIT {
 607         PHY_A_NP = 0x8000, PHY_A_ACK = 0x4000, PHY_A_RF = 0x2000,
 608         PHY_A_FCS = 0x0400, PHY_A_T4 = 0x0200, PHY_A_FDX = 0x0100,
 609         PHY_A_HDX = 0x0080, PHY_A_10FDX = 0x0040, PHY_A_10HDX = 0x0020,
 610         PHY_A_SEL = 0x001e,
 611 };
 612 /* PHY_ANL */
 613 enum PHY_ANL_BIT {
 614         PHY_L_NP = 0x8000, PHY_L_ACK = 0x4000, PHY_L_RF = 0x2000,
 615         PHY_L_FCS = 0x0400, PHY_L_T4 = 0x0200, PHY_L_FDX = 0x0100,
 616         PHY_L_HDX = 0x0080, PHY_L_10FDX = 0x0040, PHY_L_10HDX = 0x0020,
 617         PHY_L_SEL = 0x001f,
 618 };
 619
 620 /* PHY_ANE */
 621 enum PHY_ANE_BIT {
 622         PHY_E_PDF = 0x0010, PHY_E_LPNPA = 0x0008, PHY_E_NPA = 0x0004,
 623         PHY_E_PRX = 0x0002, PHY_E_LPANEGA = 0x0001,
 624 };
 625
 626 /* DM9161 */
 627 enum PHY_16_BIT {
 628         PHY_16_BP4B45 = 0x8000, PHY_16_BPSCR = 0x4000, PHY_16_BPALIGN = 0x2000,
 629         PHY_16_BP_ADPOK = 0x1000, PHY_16_Repeatmode = 0x0800,
 630         PHY_16_TXselect = 0x0400,
 631         PHY_16_Rsvd = 0x0200, PHY_16_RMIIEnable = 0x0100,
 632         PHY_16_Force100LNK = 0x0080,
 633         PHY_16_APDLED_CTL = 0x0040, PHY_16_COLLED_CTL = 0x0020,
 634         PHY_16_RPDCTR_EN = 0x0010,
 635         PHY_16_ResetStMch = 0x0008, PHY_16_PreamSupr = 0x0004,
 636         PHY_16_Sleepmode = 0x0002,
 637         PHY_16_RemoteLoopOut = 0x0001,
 638 };
 639
 640 #define POST_RX         0x08
 641 #define POST_FW         0x04
 642 #define POST0_RX        (POST_RX)
 643 #define POST0_FW        (POST_FW)
 644 #define POST1_RX        (POST_RX >> 2)
 645 #define POST1_FW        (POST_FW >> 2)
 646 #define POST_ALL        (POST0_RX | POST0_FW | POST1_RX | POST1_FW)
 647
 648 /* ARSTR */
 649 enum ARSTR_BIT { ARSTR_ARSTR = 0x00000001, };
 650
 651 /* TSU_FWEN0 */
 652 enum TSU_FWEN0_BIT {
 653         TSU_FWEN0_0 = 0x00000001,
 654 };
 655
 656 /* TSU_ADSBSY */
 657 enum TSU_ADSBSY_BIT {
 658         TSU_ADSBSY_0 = 0x00000001,
 659 };
 660
 661 /* TSU_TEN */
 662 enum TSU_TEN_BIT {
 663         TSU_TEN_0 = 0x80000000,
 664 };
 665
 666 /* TSU_FWSL0 */
 667 enum TSU_FWSL0_BIT {
 668         TSU_FWSL0_FW50 = 0x1000, TSU_FWSL0_FW40 = 0x0800,
 669         TSU_FWSL0_FW30 = 0x0400, TSU_FWSL0_FW20 = 0x0200,
 670         TSU_FWSL0_FW10 = 0x0100, TSU_FWSL0_RMSA0 = 0x0010,
 671 };
 672
 673 /* TSU_FWSLC */
 674 enum TSU_FWSLC_BIT {
 675         TSU_FWSLC_POSTENU = 0x2000, TSU_FWSLC_POSTENL = 0x1000,
 676         TSU_FWSLC_CAMSEL03 = 0x0080, TSU_FWSLC_CAMSEL02 = 0x0040,
 677         TSU_FWSLC_CAMSEL01 = 0x0020, TSU_FWSLC_CAMSEL00 = 0x0010,
 678         TSU_FWSLC_CAMSEL13 = 0x0008, TSU_FWSLC_CAMSEL12 = 0x0004,
 679         TSU_FWSLC_CAMSEL11 = 0x0002, TSU_FWSLC_CAMSEL10 = 0x0001,
 680 };
 681
 682 /* TSU_VTAGn */
 683 #define TSU_VTAG_ENABLE         0x80000000
 684 #define TSU_VTAG_VID_MASK       0x00000fff
 685
 686 /*
 687  * The sh ether Tx buffer descriptors.
 688  * This structure should be 20 bytes.
 689  */
 690 struct sh_eth_txdesc {
 691         u32 status;             /* TD0 */
 692 #if defined(CONFIG_CPU_LITTLE_ENDIAN)
 693         u16 pad0;               /* TD1 */
 694         u16 buffer_length;      /* TD1 */
 695 #else
 696         u16 buffer_length;      /* TD1 */
 697         u16 pad0;               /* TD1 */
 698 #endif
 699         u32 addr;               /* TD2 */
 700         u32 pad1;               /* padding data */
 701 } __attribute__((aligned(2), packed));
 702
 703 /*
 704  * The sh ether Rx buffer descriptors.
 705  * This structure should be 20 bytes.
 706  */
 707 struct sh_eth_rxdesc {
 708         u32 status;             /* RD0 */
 709 #if defined(CONFIG_CPU_LITTLE_ENDIAN)
 710         u16 frame_length;       /* RD1 */
 711         u16 buffer_length;      /* RD1 */
 712 #else
 713         u16 buffer_length;      /* RD1 */
 714         u16 frame_length;       /* RD1 */
 715 #endif
 716         u32 addr;               /* RD2 */
 717         u32 pad0;               /* padding data */
 718 } __attribute__((aligned(2), packed));
 719
 720 /* This structure is used by each CPU dependency handling. */
 721 struct sh_eth_cpu_data {
 722         /* optional functions */
 723         void (*chip_reset)(struct net_device *ndev);
 724         void (*set_duplex)(struct net_device *ndev);
 725         void (*set_rate)(struct net_device *ndev);
 726
 727         /* mandatory initialize value */
 728         unsigned long eesipr_value;
 729
 730         /* optional initialize value */
 731         unsigned long ecsr_value;
 732         unsigned long ecsipr_value;
 733         unsigned long fdr_value;
 734         unsigned long fcftr_value;
 735         unsigned long rpadir_value;
 736         unsigned long rmcr_value;
 737
 738         /* interrupt checking mask */
 739         unsigned long tx_check;
 740         unsigned long eesr_err_check;
 741         unsigned long tx_error_check;
 742
 743         /* hardware features */
 744         unsigned no_psr:1;              /* EtherC DO NOT have PSR */
 745         unsigned apr:1;                 /* EtherC have APR */
 746         unsigned mpr:1;                 /* EtherC have MPR */
 747         unsigned tpauser:1;             /* EtherC have TPAUSER */
 748         unsigned bculr:1;               /* EtherC have BCULR */
 749         unsigned tsu:1;                 /* EtherC have TSU */
 750         unsigned hw_swap:1;             /* E-DMAC have DE bit in EDMR */
 751         unsigned rpadir:1;              /* E-DMAC have RPADIR */
 752         unsigned no_trimd:1;            /* E-DMAC DO NOT have TRIMD */
 753         unsigned no_ade:1;      /* E-DMAC DO NOT have ADE bit in EESR */
 754 };
 755
 756 struct sh_eth_private {
 757         struct platform_device *pdev;
 758         struct sh_eth_cpu_data *cd;
 759         const u16 *reg_offset;
 760         void __iomem *addr;
 761         void __iomem *tsu_addr;
 762         dma_addr_t rx_desc_dma;
 763         dma_addr_t tx_desc_dma;
 764         struct sh_eth_rxdesc *rx_ring;
 765         struct sh_eth_txdesc *tx_ring;
 766         struct sk_buff **rx_skbuff;
 767         struct sk_buff **tx_skbuff;
 768         struct timer_list timer;
 769         spinlock_t lock;
 770         u32 cur_rx, dirty_rx;   /* Producer/consumer ring indices */
 771         u32 cur_tx, dirty_tx;
 772         u32 rx_buf_sz;          /* Based on MTU+slack. */
 773         int edmac_endian;
 774         /* MII transceiver section. */
 775         u32 phy_id;                                     /* PHY ID */
 776         struct mii_bus *mii_bus;        /* MDIO bus control */
 777         struct phy_device *phydev;      /* PHY device control */
 778         enum phy_state link;
 779         phy_interface_t phy_interface;
 780         int msg_enable;
 781         int speed;
 782         int duplex;
 783         u32 rx_int_var, tx_int_var;     /* interrupt control variables */
 784         char post_rx;           /* POST receive */
 785         char post_fw;           /* POST forward */
 786         struct net_device_stats tsu_stats;      /* TSU forward status */
 787         int port;               /* for TSU */
 788         int vlan_num_ids;       /* for VLAN tag filter */
 789
 790         unsigned no_ether_link:1;
 791         unsigned ether_link_active_low:1;
 792 };
 793
 794 static inline void sh_eth_soft_swap(char *src, int len)
 795 {
 796 #ifdef __LITTLE_ENDIAN__
 797         u32 *p = (u32 *)src;
 798         u32 *maxp;
 799         maxp = p + ((len + sizeof(u32) - 1) / sizeof(u32));
 800
 801         for (; p < maxp; p++)
 802                 *p = swab32(*p);
 803 #endif
 804 }
 805
 806 static inline void sh_eth_write(struct net_device *ndev, unsigned long data,
 807                                 int enum_index)
 808 {
 809         struct sh_eth_private *mdp = netdev_priv(ndev);
 810
 811         iowrite32(data, mdp->addr + mdp->reg_offset[enum_index]);
 812 }
 813
 814 static inline unsigned long sh_eth_read(struct net_device *ndev,
 815                                         int enum_index)
 816 {
 817         struct sh_eth_private *mdp = netdev_priv(ndev);
 818
 819         return ioread32(mdp->addr + mdp->reg_offset[enum_index]);
 820 }
 821
 822 static inline void *sh_eth_tsu_get_offset(struct sh_eth_private *mdp,
 823                                           int enum_index)
 824 {
 825         return mdp->tsu_addr + mdp->reg_offset[enum_index];
 826 }
 827
 828 static inline void sh_eth_tsu_write(struct sh_eth_private *mdp,
 829                                 unsigned long data, int enum_index)
 830 {
 831         iowrite32(data, mdp->tsu_addr + mdp->reg_offset[enum_index]);
 832 }
 833
 834 static inline unsigned long sh_eth_tsu_read(struct sh_eth_private *mdp,
 835                                         int enum_index)
 836 {
 837         return ioread32(mdp->tsu_addr + mdp->reg_offset[enum_index]);
 838 }
 839
 840 #endif  /* #ifndef __SH_ETH_H__ */